drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static int  eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static int eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static int  eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static int  eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static int  eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static int eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static int eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static int eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static int eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static int igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static int igbvf_dev_close(struct rte_eth_dev *dev);
 159 static int igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static int eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .tx_queue_setup       = eth_igb_tx_queue_setup,
 384         .tx_queue_release     = eth_igb_tx_queue_release,
 385         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 386         .dev_led_on           = eth_igb_led_on,
 387         .dev_led_off          = eth_igb_led_off,
 388         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 389         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 390         .mac_addr_add         = eth_igb_rar_set,
 391         .mac_addr_remove      = eth_igb_rar_clear,
 392         .mac_addr_set         = eth_igb_default_mac_addr_set,
 393         .reta_update          = eth_igb_rss_reta_update,
 394         .reta_query           = eth_igb_rss_reta_query,
 395         .rss_hash_update      = eth_igb_rss_hash_update,
 396         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 397         .filter_ctrl          = eth_igb_filter_ctrl,
 398         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 399         .rxq_info_get         = igb_rxq_info_get,
 400         .txq_info_get         = igb_txq_info_get,
 401         .timesync_enable      = igb_timesync_enable,
 402         .timesync_disable     = igb_timesync_disable,
 403         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 404         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 405         .get_reg              = eth_igb_get_regs,
 406         .get_eeprom_length    = eth_igb_get_eeprom_length,
 407         .get_eeprom           = eth_igb_get_eeprom,
 408         .set_eeprom           = eth_igb_set_eeprom,
 409         .get_module_info      = eth_igb_get_module_info,
 410         .get_module_eeprom    = eth_igb_get_module_eeprom,
 411         .timesync_adjust_time = igb_timesync_adjust_time,
 412         .timesync_read_time   = igb_timesync_read_time,
 413         .timesync_write_time  = igb_timesync_write_time,
 414 };
 415
 416 /*
 417  * dev_ops for virtual function, bare necessities for basic vf
 418  * operation have been implemented
 419  */
 420 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 421         .dev_configure        = igbvf_dev_configure,
 422         .dev_start            = igbvf_dev_start,
 423         .dev_stop             = igbvf_dev_stop,
 424         .dev_close            = igbvf_dev_close,
 425         .promiscuous_enable   = igbvf_promiscuous_enable,
 426         .promiscuous_disable  = igbvf_promiscuous_disable,
 427         .allmulticast_enable  = igbvf_allmulticast_enable,
 428         .allmulticast_disable = igbvf_allmulticast_disable,
 429         .link_update          = eth_igb_link_update,
 430         .stats_get            = eth_igbvf_stats_get,
 431         .xstats_get           = eth_igbvf_xstats_get,
 432         .xstats_get_names     = eth_igbvf_xstats_get_names,
 433         .stats_reset          = eth_igbvf_stats_reset,
 434         .xstats_reset         = eth_igbvf_stats_reset,
 435         .vlan_filter_set      = igbvf_vlan_filter_set,
 436         .dev_infos_get        = eth_igbvf_infos_get,
 437         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 438         .rx_queue_setup       = eth_igb_rx_queue_setup,
 439         .rx_queue_release     = eth_igb_rx_queue_release,
 440         .tx_queue_setup       = eth_igb_tx_queue_setup,
 441         .tx_queue_release     = eth_igb_tx_queue_release,
 442         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 443         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 444         .rxq_info_get         = igb_rxq_info_get,
 445         .txq_info_get         = igb_txq_info_get,
 446         .mac_addr_set         = igbvf_default_mac_addr_set,
 447         .get_reg              = igbvf_get_regs,
 448 };
 449
 450 /* store statistics names and its offset in stats structure */
 451 struct rte_igb_xstats_name_off {
 452         char name[RTE_ETH_XSTATS_NAME_SIZE];
 453         unsigned offset;
 454 };
 455
 456 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 457         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 458         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 459         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 460         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 461         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 462         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 463         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 464                 ecol)},
 465         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 466         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 467         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 468         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 469         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 470         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 471         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 472         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 473         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 474         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 475         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 476                 fcruc)},
 477         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 478         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 479         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 480         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 481         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 482                 prc1023)},
 483         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 484                 prc1522)},
 485         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 486         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 487         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 488         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 489         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 490         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 491         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 492         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 493         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 494         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 495         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 496         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 497         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 498         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 499         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 500         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 501         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 502         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 ptc1023)},
 504         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 ptc1522)},
 506         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 507         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 508         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 509         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 510         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 511         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 512         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 513
 514         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 515 };
 516
 517 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 518                 sizeof(rte_igb_stats_strings[0]))
 519
 520 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 521         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 522         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 523         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 524         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 525         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 526 };
 527
 528 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 529                 sizeof(rte_igbvf_stats_strings[0]))
 530
 531
 532 static inline void
 533 igb_intr_enable(struct rte_eth_dev *dev)
 534 {
 535         struct e1000_interrupt *intr =
 536                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 537         struct e1000_hw *hw =
 538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 541
 542         if (rte_intr_allow_others(intr_handle) &&
 543                 dev->data->dev_conf.intr_conf.lsc != 0) {
 544                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 545         }
 546
 547         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 548         E1000_WRITE_FLUSH(hw);
 549 }
 550
 551 static void
 552 igb_intr_disable(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 558
 559         if (rte_intr_allow_others(intr_handle) &&
 560                 dev->data->dev_conf.intr_conf.lsc != 0) {
 561                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 562         }
 563
 564         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 565         E1000_WRITE_FLUSH(hw);
 566 }
 567
 568 static inline void
 569 igbvf_intr_enable(struct rte_eth_dev *dev)
 570 {
 571         struct e1000_hw *hw =
 572                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 573
 574         /* only for mailbox */
 575         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 576         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 577         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 578         E1000_WRITE_FLUSH(hw);
 579 }
 580
 581 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 582 static void
 583 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 584 {
 585         uint32_t tmp = 0;
 586
 587         /* mailbox */
 588         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 589         tmp |= E1000_VTIVAR_VALID;
 590         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 591 }
 592
 593 static void
 594 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 595 {
 596         struct e1000_hw *hw =
 597                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 598
 599         /* Configure VF other cause ivar */
 600         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 601 }
 602
 603 static inline int32_t
 604 igb_pf_reset_hw(struct e1000_hw *hw)
 605 {
 606         uint32_t ctrl_ext;
 607         int32_t status;
 608
 609         status = e1000_reset_hw(hw);
 610
 611         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 612         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 613         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 614         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 615         E1000_WRITE_FLUSH(hw);
 616
 617         return status;
 618 }
 619
 620 static void
 621 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 622 {
 623         struct e1000_hw *hw =
 624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 625
 626
 627         hw->vendor_id = pci_dev->id.vendor_id;
 628         hw->device_id = pci_dev->id.device_id;
 629         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 630         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 631
 632         e1000_set_mac_type(hw);
 633
 634         /* need to check if it is a vf device below */
 635 }
 636
 637 static int
 638 igb_reset_swfw_lock(struct e1000_hw *hw)
 639 {
 640         int ret_val;
 641
 642         /*
 643          * Do mac ops initialization manually here, since we will need
 644          * some function pointers set by this call.
 645          */
 646         ret_val = e1000_init_mac_params(hw);
 647         if (ret_val)
 648                 return ret_val;
 649
 650         /*
 651          * SMBI lock should not fail in this early stage. If this is the case,
 652          * it is due to an improper exit of the application.
 653          * So force the release of the faulty lock.
 654          */
 655         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 656                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 657         }
 658         e1000_put_hw_semaphore_generic(hw);
 659
 660         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 661                 uint16_t mask;
 662
 663                 /*
 664                  * Phy lock should not fail in this early stage. If this is the case,
 665                  * it is due to an improper exit of the application.
 666                  * So force the release of the faulty lock.
 667                  */
 668                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 669                 if (hw->bus.func > E1000_FUNC_1)
 670                         mask <<= 2;
 671                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 672                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 673                                     hw->bus.func);
 674                 }
 675                 hw->mac.ops.release_swfw_sync(hw, mask);
 676
 677                 /*
 678                  * This one is more tricky since it is common to all ports; but
 679                  * swfw_sync retries last long enough (1s) to be almost sure that if
 680                  * lock can not be taken it is due to an improper lock of the
 681                  * semaphore.
 682                  */
 683                 mask = E1000_SWFW_EEP_SM;
 684                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 685                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 686                 }
 687                 hw->mac.ops.release_swfw_sync(hw, mask);
 688         }
 689
 690         return E1000_SUCCESS;
 691 }
 692
 693 /* Remove all ntuple filters of the device */
 694 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_5tuple_filter *p_5tuple;
 699         struct e1000_2tuple_filter *p_2tuple;
 700
 701         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 702                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 703                         p_5tuple, entries);
 704                         rte_free(p_5tuple);
 705         }
 706         filter_info->fivetuple_mask = 0;
 707         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->twotuple_list,
 709                         p_2tuple, entries);
 710                         rte_free(p_2tuple);
 711         }
 712         filter_info->twotuple_mask = 0;
 713
 714         return 0;
 715 }
 716
 717 /* Remove all flex filters of the device */
 718 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 719 {
 720         struct e1000_filter_info *filter_info =
 721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 722         struct e1000_flex_filter *p_flex;
 723
 724         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 725                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 726                 rte_free(p_flex);
 727         }
 728         filter_info->flex_mask = 0;
 729
 730         return 0;
 731 }
 732
 733 static int
 734 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 735 {
 736         int error = 0;
 737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 738         struct e1000_hw *hw =
 739                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 740         struct e1000_vfta * shadow_vfta =
 741                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 742         struct e1000_filter_info *filter_info =
 743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 744         struct e1000_adapter *adapter =
 745                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 746
 747         uint32_t ctrl_ext;
 748
 749         eth_dev->dev_ops = &eth_igb_ops;
 750         eth_dev->rx_queue_count = eth_igb_rx_queue_count;
 751         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 752         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 753         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 754         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 755         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 756         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 757
 758         /* for secondary processes, we don't initialise any further as primary
 759          * has already done this work. Only check we don't need a different
 760          * RX function */
 761         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 762                 if (eth_dev->data->scattered_rx)
 763                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 764                 return 0;
 765         }
 766
 767         rte_eth_copy_pci_info(eth_dev, pci_dev);
 768         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 769
 770         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 771
 772         igb_identify_hardware(eth_dev, pci_dev);
 773         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 774                 error = -EIO;
 775                 goto err_late;
 776         }
 777
 778         e1000_get_bus_info(hw);
 779
 780         /* Reset any pending lock */
 781         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 782                 error = -EIO;
 783                 goto err_late;
 784         }
 785
 786         /* Finish initialization */
 787         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 788                 error = -EIO;
 789                 goto err_late;
 790         }
 791
 792         hw->mac.autoneg = 1;
 793         hw->phy.autoneg_wait_to_complete = 0;
 794         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 795
 796         /* Copper options */
 797         if (hw->phy.media_type == e1000_media_type_copper) {
 798                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 799                 hw->phy.disable_polarity_correction = 0;
 800                 hw->phy.ms_type = e1000_ms_hw_default;
 801         }
 802
 803         /*
 804          * Start from a known state, this is important in reading the nvm
 805          * and mac from that.
 806          */
 807         igb_pf_reset_hw(hw);
 808
 809         /* Make sure we have a good EEPROM before we read from it */
 810         if (e1000_validate_nvm_checksum(hw) < 0) {
 811                 /*
 812                  * Some PCI-E parts fail the first check due to
 813                  * the link being in sleep state, call it again,
 814                  * if it fails a second time its a real issue.
 815                  */
 816                 if (e1000_validate_nvm_checksum(hw) < 0) {
 817                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 818                         error = -EIO;
 819                         goto err_late;
 820                 }
 821         }
 822
 823         /* Read the permanent MAC address out of the EEPROM */
 824         if (e1000_read_mac_addr(hw) != 0) {
 825                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 826                 error = -EIO;
 827                 goto err_late;
 828         }
 829
 830         /* Allocate memory for storing MAC addresses */
 831         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 832                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 833         if (eth_dev->data->mac_addrs == NULL) {
 834                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 835                                                 "store MAC addresses",
 836                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 837                 error = -ENOMEM;
 838                 goto err_late;
 839         }
 840
 841         /* Copy the permanent MAC address */
 842         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 843                         &eth_dev->data->mac_addrs[0]);
 844
 845         /* initialize the vfta */
 846         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 847
 848         /* Now initialize the hardware */
 849         if (igb_hardware_init(hw) != 0) {
 850                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 851                 rte_free(eth_dev->data->mac_addrs);
 852                 eth_dev->data->mac_addrs = NULL;
 853                 error = -ENODEV;
 854                 goto err_late;
 855         }
 856         hw->mac.get_link_status = 1;
 857         adapter->stopped = 0;
 858
 859         /* Indicate SOL/IDER usage */
 860         if (e1000_check_reset_block(hw) < 0) {
 861                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 862                                         "SOL/IDER session");
 863         }
 864
 865         /* initialize PF if max_vfs not zero */
 866         igb_pf_host_init(eth_dev);
 867
 868         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 869         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 870         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 871         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 872         E1000_WRITE_FLUSH(hw);
 873
 874         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 875                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 876                      pci_dev->id.device_id);
 877
 878         rte_intr_callback_register(&pci_dev->intr_handle,
 879                                    eth_igb_interrupt_handler,
 880                                    (void *)eth_dev);
 881
 882         /* enable uio/vfio intr/eventfd mapping */
 883         rte_intr_enable(&pci_dev->intr_handle);
 884
 885         /* enable support intr */
 886         igb_intr_enable(eth_dev);
 887
 888         eth_igb_dev_set_link_down(eth_dev);
 889
 890         /* initialize filter info */
 891         memset(filter_info, 0,
 892                sizeof(struct e1000_filter_info));
 893
 894         TAILQ_INIT(&filter_info->flex_list);
 895         TAILQ_INIT(&filter_info->twotuple_list);
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897
 898         TAILQ_INIT(&igb_filter_ntuple_list);
 899         TAILQ_INIT(&igb_filter_ethertype_list);
 900         TAILQ_INIT(&igb_filter_syn_list);
 901         TAILQ_INIT(&igb_filter_flex_list);
 902         TAILQ_INIT(&igb_filter_rss_list);
 903         TAILQ_INIT(&igb_flow_list);
 904
 905         return 0;
 906
 907 err_late:
 908         igb_hw_control_release(hw);
 909
 910         return error;
 911 }
 912
 913 static int
 914 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 915 {
 916         PMD_INIT_FUNC_TRACE();
 917
 918         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 919                 return 0;
 920
 921         eth_igb_close(eth_dev);
 922
 923         return 0;
 924 }
 925
 926 /*
 927  * Virtual Function device init
 928  */
 929 static int
 930 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 931 {
 932         struct rte_pci_device *pci_dev;
 933         struct rte_intr_handle *intr_handle;
 934         struct e1000_adapter *adapter =
 935                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 936         struct e1000_hw *hw =
 937                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 938         int diag;
 939         struct rte_ether_addr *perm_addr =
 940                 (struct rte_ether_addr *)hw->mac.perm_addr;
 941
 942         PMD_INIT_FUNC_TRACE();
 943
 944         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 945         eth_dev->rx_descriptor_done   = eth_igb_rx_descriptor_done;
 946         eth_dev->rx_descriptor_status = eth_igb_rx_descriptor_status;
 947         eth_dev->tx_descriptor_status = eth_igb_tx_descriptor_status;
 948         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 949         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 950         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 951
 952         /* for secondary processes, we don't initialise any further as primary
 953          * has already done this work. Only check we don't need a different
 954          * RX function */
 955         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 956                 if (eth_dev->data->scattered_rx)
 957                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 958                 return 0;
 959         }
 960
 961         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 962         rte_eth_copy_pci_info(eth_dev, pci_dev);
 963         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 964
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->vendor_id = pci_dev->id.vendor_id;
 967         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 968         adapter->stopped = 0;
 969
 970         /* Initialize the shared code (base driver) */
 971         diag = e1000_setup_init_funcs(hw, TRUE);
 972         if (diag != 0) {
 973                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 974                         diag);
 975                 return -EIO;
 976         }
 977
 978         /* init_mailbox_params */
 979         hw->mbx.ops.init_params(hw);
 980
 981         /* Disable the interrupts for VF */
 982         igbvf_intr_disable(hw);
 983
 984         diag = hw->mac.ops.reset_hw(hw);
 985
 986         /* Allocate memory for storing MAC addresses */
 987         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
 988                 hw->mac.rar_entry_count, 0);
 989         if (eth_dev->data->mac_addrs == NULL) {
 990                 PMD_INIT_LOG(ERR,
 991                         "Failed to allocate %d bytes needed to store MAC "
 992                         "addresses",
 993                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 994                 return -ENOMEM;
 995         }
 996
 997         /* Generate a random MAC address, if none was assigned by PF. */
 998         if (rte_is_zero_ether_addr(perm_addr)) {
 999                 rte_eth_random_addr(perm_addr->addr_bytes);
1000                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1001                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1002                              "%02x:%02x:%02x:%02x:%02x:%02x",
1003                              perm_addr->addr_bytes[0],
1004                              perm_addr->addr_bytes[1],
1005                              perm_addr->addr_bytes[2],
1006                              perm_addr->addr_bytes[3],
1007                              perm_addr->addr_bytes[4],
1008                              perm_addr->addr_bytes[5]);
1009         }
1010
1011         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1012         if (diag) {
1013                 rte_free(eth_dev->data->mac_addrs);
1014                 eth_dev->data->mac_addrs = NULL;
1015                 return diag;
1016         }
1017         /* Copy the permanent MAC address */
1018         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1019                         &eth_dev->data->mac_addrs[0]);
1020
1021         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1022                      "mac.type=%s",
1023                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1024                      pci_dev->id.device_id, "igb_mac_82576_vf");
1025
1026         intr_handle = &pci_dev->intr_handle;
1027         rte_intr_callback_register(intr_handle,
1028                                    eth_igbvf_interrupt_handler, eth_dev);
1029
1030         return 0;
1031 }
1032
1033 static int
1034 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1035 {
1036         PMD_INIT_FUNC_TRACE();
1037
1038         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1039                 return 0;
1040
1041         igbvf_dev_close(eth_dev);
1042
1043         return 0;
1044 }
1045
1046 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1047         struct rte_pci_device *pci_dev)
1048 {
1049         return rte_eth_dev_pci_generic_probe(pci_dev,
1050                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1051 }
1052
1053 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1054 {
1055         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1056 }
1057
1058 static struct rte_pci_driver rte_igb_pmd = {
1059         .id_table = pci_id_igb_map,
1060         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1061         .probe = eth_igb_pci_probe,
1062         .remove = eth_igb_pci_remove,
1063 };
1064
1065
1066 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1067         struct rte_pci_device *pci_dev)
1068 {
1069         return rte_eth_dev_pci_generic_probe(pci_dev,
1070                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1071 }
1072
1073 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1074 {
1075         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1076 }
1077
1078 /*
1079  * virtual function driver struct
1080  */
1081 static struct rte_pci_driver rte_igbvf_pmd = {
1082         .id_table = pci_id_igbvf_map,
1083         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1084         .probe = eth_igbvf_pci_probe,
1085         .remove = eth_igbvf_pci_remove,
1086 };
1087
1088 static void
1089 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1090 {
1091         struct e1000_hw *hw =
1092                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1094         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1095         rctl |= E1000_RCTL_VFE;
1096         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1097 }
1098
1099 static int
1100 igb_check_mq_mode(struct rte_eth_dev *dev)
1101 {
1102         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1103         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1104         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1105         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1106
1107         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1108             tx_mq_mode == ETH_MQ_TX_DCB ||
1109             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1110                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1111                 return -EINVAL;
1112         }
1113         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1114                 /* Check multi-queue mode.
1115                  * To no break software we accept ETH_MQ_RX_NONE as this might
1116                  * be used to turn off VLAN filter.
1117                  */
1118
1119                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1120                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1121                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1122                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1123                 } else {
1124                         /* Only support one queue on VFs.
1125                          * RSS together with SRIOV is not supported.
1126                          */
1127                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1128                                         " wrong mq_mode rx %d.",
1129                                         rx_mq_mode);
1130                         return -EINVAL;
1131                 }
1132                 /* TX mode is not used here, so mode might be ignored.*/
1133                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1134                         /* SRIOV only works in VMDq enable mode */
1135                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1136                                         " TX mode %d is not supported. "
1137                                         " Driver will behave as %d mode.",
1138                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1139                 }
1140
1141                 /* check valid queue number */
1142                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1143                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1144                                         " only support one queue on VFs.");
1145                         return -EINVAL;
1146                 }
1147         } else {
1148                 /* To no break software that set invalid mode, only display
1149                  * warning if invalid mode is used.
1150                  */
1151                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1152                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1153                     rx_mq_mode != ETH_MQ_RX_RSS) {
1154                         /* RSS together with VMDq not supported*/
1155                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1156                                      rx_mq_mode);
1157                         return -EINVAL;
1158                 }
1159
1160                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1161                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1162                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1163                                         " Due to txmode is meaningless in this"
1164                                         " driver, just ignore.",
1165                                         tx_mq_mode);
1166                 }
1167         }
1168         return 0;
1169 }
1170
1171 static int
1172 eth_igb_configure(struct rte_eth_dev *dev)
1173 {
1174         struct e1000_interrupt *intr =
1175                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1176         int ret;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1181                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1182
1183         /* multipe queue mode checking */
1184         ret  = igb_check_mq_mode(dev);
1185         if (ret != 0) {
1186                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1187                             ret);
1188                 return ret;
1189         }
1190
1191         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1192         PMD_INIT_FUNC_TRACE();
1193
1194         return 0;
1195 }
1196
1197 static void
1198 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1199                      bool enable)
1200 {
1201         struct e1000_hw *hw =
1202                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1203         uint32_t tctl, rctl;
1204
1205         tctl = E1000_READ_REG(hw, E1000_TCTL);
1206         rctl = E1000_READ_REG(hw, E1000_RCTL);
1207
1208         if (enable) {
1209                 /* enable Tx/Rx */
1210                 tctl |= E1000_TCTL_EN;
1211                 rctl |= E1000_RCTL_EN;
1212         } else {
1213                 /* disable Tx/Rx */
1214                 tctl &= ~E1000_TCTL_EN;
1215                 rctl &= ~E1000_RCTL_EN;
1216         }
1217         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1218         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1219         E1000_WRITE_FLUSH(hw);
1220 }
1221
1222 static int
1223 eth_igb_start(struct rte_eth_dev *dev)
1224 {
1225         struct e1000_hw *hw =
1226                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1227         struct e1000_adapter *adapter =
1228                 E1000_DEV_PRIVATE(dev->data->dev_private);
1229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1230         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1231         int ret, mask;
1232         uint32_t intr_vector = 0;
1233         uint32_t ctrl_ext;
1234         uint32_t *speeds;
1235         int num_speeds;
1236         bool autoneg;
1237
1238         PMD_INIT_FUNC_TRACE();
1239
1240         /* disable uio/vfio intr/eventfd mapping */
1241         rte_intr_disable(intr_handle);
1242
1243         /* Power up the phy. Needed to make the link go Up */
1244         eth_igb_dev_set_link_up(dev);
1245
1246         /*
1247          * Packet Buffer Allocation (PBA)
1248          * Writing PBA sets the receive portion of the buffer
1249          * the remainder is used for the transmit buffer.
1250          */
1251         if (hw->mac.type == e1000_82575) {
1252                 uint32_t pba;
1253
1254                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1255                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1256         }
1257
1258         /* Put the address into the Receive Address Array */
1259         e1000_rar_set(hw, hw->mac.addr, 0);
1260
1261         /* Initialize the hardware */
1262         if (igb_hardware_init(hw)) {
1263                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1264                 return -EIO;
1265         }
1266         adapter->stopped = 0;
1267
1268         E1000_WRITE_REG(hw, E1000_VET,
1269                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1270
1271         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1272         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1273         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1274         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1275         E1000_WRITE_FLUSH(hw);
1276
1277         /* configure PF module if SRIOV enabled */
1278         igb_pf_host_configure(dev);
1279
1280         /* check and configure queue intr-vector mapping */
1281         if ((rte_intr_cap_multiple(intr_handle) ||
1282              !RTE_ETH_DEV_SRIOV(dev).active) &&
1283             dev->data->dev_conf.intr_conf.rxq != 0) {
1284                 intr_vector = dev->data->nb_rx_queues;
1285                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1286                         return -1;
1287         }
1288
1289         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1290                 intr_handle->intr_vec =
1291                         rte_zmalloc("intr_vec",
1292                                     dev->data->nb_rx_queues * sizeof(int), 0);
1293                 if (intr_handle->intr_vec == NULL) {
1294                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1295                                      " intr_vec", dev->data->nb_rx_queues);
1296                         return -ENOMEM;
1297                 }
1298         }
1299
1300         /* confiugre msix for rx interrupt */
1301         eth_igb_configure_msix_intr(dev);
1302
1303         /* Configure for OS presence */
1304         igb_init_manageability(hw);
1305
1306         eth_igb_tx_init(dev);
1307
1308         /* This can fail when allocating mbufs for descriptor rings */
1309         ret = eth_igb_rx_init(dev);
1310         if (ret) {
1311                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1312                 igb_dev_clear_queues(dev);
1313                 return ret;
1314         }
1315
1316         e1000_clear_hw_cntrs_base_generic(hw);
1317
1318         /*
1319          * VLAN Offload Settings
1320          */
1321         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1322                         ETH_VLAN_EXTEND_MASK;
1323         ret = eth_igb_vlan_offload_set(dev, mask);
1324         if (ret) {
1325                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1326                 igb_dev_clear_queues(dev);
1327                 return ret;
1328         }
1329
1330         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1331                 /* Enable VLAN filter since VMDq always use VLAN filter */
1332                 igb_vmdq_vlan_hw_filter_enable(dev);
1333         }
1334
1335         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1336                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1337                 (hw->mac.type == e1000_i211)) {
1338                 /* Configure EITR with the maximum possible value (0xFFFF) */
1339                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1340         }
1341
1342         /* Setup link speed and duplex */
1343         speeds = &dev->data->dev_conf.link_speeds;
1344         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1345                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1346                 hw->mac.autoneg = 1;
1347         } else {
1348                 num_speeds = 0;
1349                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1350
1351                 /* Reset */
1352                 hw->phy.autoneg_advertised = 0;
1353
1354                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1355                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1356                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1357                         num_speeds = -1;
1358                         goto error_invalid_config;
1359                 }
1360                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1361                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1362                         num_speeds++;
1363                 }
1364                 if (*speeds & ETH_LINK_SPEED_10M) {
1365                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1366                         num_speeds++;
1367                 }
1368                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1369                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1370                         num_speeds++;
1371                 }
1372                 if (*speeds & ETH_LINK_SPEED_100M) {
1373                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1374                         num_speeds++;
1375                 }
1376                 if (*speeds & ETH_LINK_SPEED_1G) {
1377                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1378                         num_speeds++;
1379                 }
1380                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1381                         goto error_invalid_config;
1382
1383                 /* Set/reset the mac.autoneg based on the link speed,
1384                  * fixed or not
1385                  */
1386                 if (!autoneg) {
1387                         hw->mac.autoneg = 0;
1388                         hw->mac.forced_speed_duplex =
1389                                         hw->phy.autoneg_advertised;
1390                 } else {
1391                         hw->mac.autoneg = 1;
1392                 }
1393         }
1394
1395         e1000_setup_link(hw);
1396
1397         if (rte_intr_allow_others(intr_handle)) {
1398                 /* check if lsc interrupt is enabled */
1399                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1400                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1401                 else
1402                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1403         } else {
1404                 rte_intr_callback_unregister(intr_handle,
1405                                              eth_igb_interrupt_handler,
1406                                              (void *)dev);
1407                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1408                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1409                                      " no intr multiplex");
1410         }
1411
1412         /* check if rxq interrupt is enabled */
1413         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1414             rte_intr_dp_is_en(intr_handle))
1415                 eth_igb_rxq_interrupt_setup(dev);
1416
1417         /* enable uio/vfio intr/eventfd mapping */
1418         rte_intr_enable(intr_handle);
1419
1420         /* resume enabled intr since hw reset */
1421         igb_intr_enable(dev);
1422
1423         /* restore all types filter */
1424         igb_filter_restore(dev);
1425
1426         eth_igb_rxtx_control(dev, true);
1427         eth_igb_link_update(dev, 0);
1428
1429         PMD_INIT_LOG(DEBUG, "<<");
1430
1431         return 0;
1432
1433 error_invalid_config:
1434         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1435                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1436         igb_dev_clear_queues(dev);
1437         return -EINVAL;
1438 }
1439
1440 /*********************************************************************
1441  *
1442  *  This routine disables all traffic on the adapter by issuing a
1443  *  global reset on the MAC.
1444  *
1445  **********************************************************************/
1446 static int
1447 eth_igb_stop(struct rte_eth_dev *dev)
1448 {
1449         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1450         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1451         struct rte_eth_link link;
1452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1453         struct e1000_adapter *adapter =
1454                 E1000_DEV_PRIVATE(dev->data->dev_private);
1455
1456         if (adapter->stopped)
1457                 return 0;
1458
1459         eth_igb_rxtx_control(dev, false);
1460
1461         igb_intr_disable(dev);
1462
1463         /* disable intr eventfd mapping */
1464         rte_intr_disable(intr_handle);
1465
1466         igb_pf_reset_hw(hw);
1467         E1000_WRITE_REG(hw, E1000_WUC, 0);
1468
1469         /* Set bit for Go Link disconnect if PHY reset is not blocked */
1470         if (hw->mac.type >= e1000_82580 &&
1471             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1472                 uint32_t phpm_reg;
1473
1474                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1475                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1476                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1477         }
1478
1479         /* Power down the phy. Needed to make the link go Down */
1480         eth_igb_dev_set_link_down(dev);
1481
1482         igb_dev_clear_queues(dev);
1483
1484         /* clear the recorded link status */
1485         memset(&link, 0, sizeof(link));
1486         rte_eth_linkstatus_set(dev, &link);
1487
1488         if (!rte_intr_allow_others(intr_handle))
1489                 /* resume to the default handler */
1490                 rte_intr_callback_register(intr_handle,
1491                                            eth_igb_interrupt_handler,
1492                                            (void *)dev);
1493
1494         /* Clean datapath event and queue/vec mapping */
1495         rte_intr_efd_disable(intr_handle);
1496         if (intr_handle->intr_vec != NULL) {
1497                 rte_free(intr_handle->intr_vec);
1498                 intr_handle->intr_vec = NULL;
1499         }
1500
1501         adapter->stopped = true;
1502         dev->data->dev_started = 0;
1503
1504         return 0;
1505 }
1506
1507 static int
1508 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1509 {
1510         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511
1512         if (hw->phy.media_type == e1000_media_type_copper)
1513                 e1000_power_up_phy(hw);
1514         else
1515                 e1000_power_up_fiber_serdes_link(hw);
1516
1517         return 0;
1518 }
1519
1520 static int
1521 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1522 {
1523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524
1525         if (hw->phy.media_type == e1000_media_type_copper)
1526                 e1000_power_down_phy(hw);
1527         else
1528                 e1000_shutdown_fiber_serdes_link(hw);
1529
1530         return 0;
1531 }
1532
1533 static int
1534 eth_igb_close(struct rte_eth_dev *dev)
1535 {
1536         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct rte_eth_link link;
1538         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1539         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1540         struct e1000_filter_info *filter_info =
1541                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1542         int ret;
1543
1544         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1545                 return 0;
1546
1547         ret = eth_igb_stop(dev);
1548
1549         e1000_phy_hw_reset(hw);
1550         igb_release_manageability(hw);
1551         igb_hw_control_release(hw);
1552
1553         /* Clear bit for Go Link disconnect if PHY reset is not blocked */
1554         if (hw->mac.type >= e1000_82580 &&
1555             (e1000_check_reset_block(hw) != E1000_BLK_PHY_RESET)) {
1556                 uint32_t phpm_reg;
1557
1558                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1559                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1560                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1561         }
1562
1563         igb_dev_free_queues(dev);
1564
1565         if (intr_handle->intr_vec) {
1566                 rte_free(intr_handle->intr_vec);
1567                 intr_handle->intr_vec = NULL;
1568         }
1569
1570         memset(&link, 0, sizeof(link));
1571         rte_eth_linkstatus_set(dev, &link);
1572
1573         /* Reset any pending lock */
1574         igb_reset_swfw_lock(hw);
1575
1576         /* uninitialize PF if max_vfs not zero */
1577         igb_pf_host_uninit(dev);
1578
1579         rte_intr_callback_unregister(intr_handle,
1580                                      eth_igb_interrupt_handler, dev);
1581
1582         /* clear the SYN filter info */
1583         filter_info->syn_info = 0;
1584
1585         /* clear the ethertype filters info */
1586         filter_info->ethertype_mask = 0;
1587         memset(filter_info->ethertype_filters, 0,
1588                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1589
1590         /* clear the rss filter info */
1591         memset(&filter_info->rss_info, 0,
1592                 sizeof(struct igb_rte_flow_rss_conf));
1593
1594         /* remove all ntuple filters of the device */
1595         igb_ntuple_filter_uninit(dev);
1596
1597         /* remove all flex filters of the device */
1598         igb_flex_filter_uninit(dev);
1599
1600         /* clear all the filters list */
1601         igb_filterlist_flush(dev);
1602
1603         return ret;
1604 }
1605
1606 /*
1607  * Reset PF device.
1608  */
1609 static int
1610 eth_igb_reset(struct rte_eth_dev *dev)
1611 {
1612         int ret;
1613
1614         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1615          * its VF to make them align with it. The detailed notification
1616          * mechanism is PMD specific and is currently not implemented.
1617          * To avoid unexpected behavior in VF, currently reset of PF with
1618          * SR-IOV activation is not supported. It might be supported later.
1619          */
1620         if (dev->data->sriov.active)
1621                 return -ENOTSUP;
1622
1623         ret = eth_igb_dev_uninit(dev);
1624         if (ret)
1625                 return ret;
1626
1627         ret = eth_igb_dev_init(dev);
1628
1629         return ret;
1630 }
1631
1632
1633 static int
1634 igb_get_rx_buffer_size(struct e1000_hw *hw)
1635 {
1636         uint32_t rx_buf_size;
1637         if (hw->mac.type == e1000_82576) {
1638                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1639         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1640                 /* PBS needs to be translated according to a lookup table */
1641                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1642                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1643                 rx_buf_size = (rx_buf_size << 10);
1644         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1645                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1646         } else {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1648         }
1649
1650         return rx_buf_size;
1651 }
1652
1653 /*********************************************************************
1654  *
1655  *  Initialize the hardware
1656  *
1657  **********************************************************************/
1658 static int
1659 igb_hardware_init(struct e1000_hw *hw)
1660 {
1661         uint32_t rx_buf_size;
1662         int diag;
1663
1664         /* Let the firmware know the OS is in control */
1665         igb_hw_control_acquire(hw);
1666
1667         /*
1668          * These parameters control the automatic generation (Tx) and
1669          * response (Rx) to Ethernet PAUSE frames.
1670          * - High water mark should allow for at least two standard size (1518)
1671          *   frames to be received after sending an XOFF.
1672          * - Low water mark works best when it is very near the high water mark.
1673          *   This allows the receiver to restart by sending XON when it has
1674          *   drained a bit. Here we use an arbitrary value of 1500 which will
1675          *   restart after one full frame is pulled from the buffer. There
1676          *   could be several smaller frames in the buffer and if so they will
1677          *   not trigger the XON until their total number reduces the buffer
1678          *   by 1500.
1679          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1680          */
1681         rx_buf_size = igb_get_rx_buffer_size(hw);
1682
1683         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1684         hw->fc.low_water = hw->fc.high_water - 1500;
1685         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1686         hw->fc.send_xon = 1;
1687
1688         /* Set Flow control, use the tunable location if sane */
1689         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1690                 hw->fc.requested_mode = igb_fc_setting;
1691         else
1692                 hw->fc.requested_mode = e1000_fc_none;
1693
1694         /* Issue a global reset */
1695         igb_pf_reset_hw(hw);
1696         E1000_WRITE_REG(hw, E1000_WUC, 0);
1697
1698         diag = e1000_init_hw(hw);
1699         if (diag < 0)
1700                 return diag;
1701
1702         E1000_WRITE_REG(hw, E1000_VET,
1703                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1704         e1000_get_phy_info(hw);
1705         e1000_check_for_link(hw);
1706
1707         return 0;
1708 }
1709
1710 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1711 static void
1712 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1713 {
1714         int pause_frames;
1715
1716         uint64_t old_gprc  = stats->gprc;
1717         uint64_t old_gptc  = stats->gptc;
1718         uint64_t old_tpr   = stats->tpr;
1719         uint64_t old_tpt   = stats->tpt;
1720         uint64_t old_rpthc = stats->rpthc;
1721         uint64_t old_hgptc = stats->hgptc;
1722
1723         if(hw->phy.media_type == e1000_media_type_copper ||
1724             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1725                 stats->symerrs +=
1726                     E1000_READ_REG(hw,E1000_SYMERRS);
1727                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1728         }
1729
1730         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1731         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1732         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1733         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1734
1735         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1736         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1737         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1738         stats->dc += E1000_READ_REG(hw, E1000_DC);
1739         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1740         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1741         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1742         /*
1743         ** For watchdog management we need to know if we have been
1744         ** paused during the last interval, so capture that here.
1745         */
1746         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1747         stats->xoffrxc += pause_frames;
1748         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1749         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1750         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1751         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1752         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1753         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1754         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1755         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1756         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1757         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1758         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1759         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1760
1761         /* For the 64-bit byte counters the low dword must be read first. */
1762         /* Both registers clear on the read of the high dword */
1763
1764         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1765         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1766         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1767         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1768         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1769         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1770         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1771
1772         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1773         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1774         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1775         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1776         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1777
1778         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1779         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1780
1781         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1782         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1783         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1784         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1785         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1786         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1787
1788         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1789         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1790         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1791         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1792         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1793         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1794         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1795         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1796
1797         /* Interrupt Counts */
1798
1799         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1800         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1801         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1802         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1803         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1804         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1805         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1806         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1807         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1808
1809         /* Host to Card Statistics */
1810
1811         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1812         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1813         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1814         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1815         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1816         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1817         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1818         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1819         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1820         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1821         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1822         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1823         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1824         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1825         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1826         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1827
1828         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1829         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1830         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1831         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1832         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1833         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1834 }
1835
1836 static int
1837 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1838 {
1839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct e1000_hw_stats *stats =
1841                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1842
1843         igb_read_stats_registers(hw, stats);
1844
1845         if (rte_stats == NULL)
1846                 return -EINVAL;
1847
1848         /* Rx Errors */
1849         rte_stats->imissed = stats->mpc;
1850         rte_stats->ierrors = stats->crcerrs +
1851                              stats->rlec + stats->ruc + stats->roc +
1852                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1853
1854         /* Tx Errors */
1855         rte_stats->oerrors = stats->ecol + stats->latecol;
1856
1857         rte_stats->ipackets = stats->gprc;
1858         rte_stats->opackets = stats->gptc;
1859         rte_stats->ibytes   = stats->gorc;
1860         rte_stats->obytes   = stats->gotc;
1861         return 0;
1862 }
1863
1864 static int
1865 eth_igb_stats_reset(struct rte_eth_dev *dev)
1866 {
1867         struct e1000_hw_stats *hw_stats =
1868                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1869
1870         /* HW registers are cleared on read */
1871         eth_igb_stats_get(dev, NULL);
1872
1873         /* Reset software totals */
1874         memset(hw_stats, 0, sizeof(*hw_stats));
1875
1876         return 0;
1877 }
1878
1879 static int
1880 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1881 {
1882         struct e1000_hw_stats *stats =
1883                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1884
1885         /* HW registers are cleared on read */
1886         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1887
1888         /* Reset software totals */
1889         memset(stats, 0, sizeof(*stats));
1890
1891         return 0;
1892 }
1893
1894 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1895         struct rte_eth_xstat_name *xstats_names,
1896         __rte_unused unsigned int size)
1897 {
1898         unsigned i;
1899
1900         if (xstats_names == NULL)
1901                 return IGB_NB_XSTATS;
1902
1903         /* Note: limit checked in rte_eth_xstats_names() */
1904
1905         for (i = 0; i < IGB_NB_XSTATS; i++) {
1906                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1907                         sizeof(xstats_names[i].name));
1908         }
1909
1910         return IGB_NB_XSTATS;
1911 }
1912
1913 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1914                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1915                 unsigned int limit)
1916 {
1917         unsigned int i;
1918
1919         if (!ids) {
1920                 if (xstats_names == NULL)
1921                         return IGB_NB_XSTATS;
1922
1923                 for (i = 0; i < IGB_NB_XSTATS; i++)
1924                         strlcpy(xstats_names[i].name,
1925                                 rte_igb_stats_strings[i].name,
1926                                 sizeof(xstats_names[i].name));
1927
1928                 return IGB_NB_XSTATS;
1929
1930         } else {
1931                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1932
1933                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1934                                 IGB_NB_XSTATS);
1935
1936                 for (i = 0; i < limit; i++) {
1937                         if (ids[i] >= IGB_NB_XSTATS) {
1938                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1939                                 return -1;
1940                         }
1941                         strcpy(xstats_names[i].name,
1942                                         xstats_names_copy[ids[i]].name);
1943                 }
1944                 return limit;
1945         }
1946 }
1947
1948 static int
1949 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1950                    unsigned n)
1951 {
1952         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct e1000_hw_stats *hw_stats =
1954                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1955         unsigned i;
1956
1957         if (n < IGB_NB_XSTATS)
1958                 return IGB_NB_XSTATS;
1959
1960         igb_read_stats_registers(hw, hw_stats);
1961
1962         /* If this is a reset xstats is NULL, and we have cleared the
1963          * registers by reading them.
1964          */
1965         if (!xstats)
1966                 return 0;
1967
1968         /* Extended stats */
1969         for (i = 0; i < IGB_NB_XSTATS; i++) {
1970                 xstats[i].id = i;
1971                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1972                         rte_igb_stats_strings[i].offset);
1973         }
1974
1975         return IGB_NB_XSTATS;
1976 }
1977
1978 static int
1979 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1980                 uint64_t *values, unsigned int n)
1981 {
1982         unsigned int i;
1983
1984         if (!ids) {
1985                 struct e1000_hw *hw =
1986                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987                 struct e1000_hw_stats *hw_stats =
1988                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1989
1990                 if (n < IGB_NB_XSTATS)
1991                         return IGB_NB_XSTATS;
1992
1993                 igb_read_stats_registers(hw, hw_stats);
1994
1995                 /* If this is a reset xstats is NULL, and we have cleared the
1996                  * registers by reading them.
1997                  */
1998                 if (!values)
1999                         return 0;
2000
2001                 /* Extended stats */
2002                 for (i = 0; i < IGB_NB_XSTATS; i++)
2003                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2004                                         rte_igb_stats_strings[i].offset);
2005
2006                 return IGB_NB_XSTATS;
2007
2008         } else {
2009                 uint64_t values_copy[IGB_NB_XSTATS];
2010
2011                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2012                                 IGB_NB_XSTATS);
2013
2014                 for (i = 0; i < n; i++) {
2015                         if (ids[i] >= IGB_NB_XSTATS) {
2016                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2017                                 return -1;
2018                         }
2019                         values[i] = values_copy[ids[i]];
2020                 }
2021                 return n;
2022         }
2023 }
2024
2025 static void
2026 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2027 {
2028         /* Good Rx packets, include VF loopback */
2029         UPDATE_VF_STAT(E1000_VFGPRC,
2030             hw_stats->last_gprc, hw_stats->gprc);
2031
2032         /* Good Rx octets, include VF loopback */
2033         UPDATE_VF_STAT(E1000_VFGORC,
2034             hw_stats->last_gorc, hw_stats->gorc);
2035
2036         /* Good Tx packets, include VF loopback */
2037         UPDATE_VF_STAT(E1000_VFGPTC,
2038             hw_stats->last_gptc, hw_stats->gptc);
2039
2040         /* Good Tx octets, include VF loopback */
2041         UPDATE_VF_STAT(E1000_VFGOTC,
2042             hw_stats->last_gotc, hw_stats->gotc);
2043
2044         /* Rx Multicst packets */
2045         UPDATE_VF_STAT(E1000_VFMPRC,
2046             hw_stats->last_mprc, hw_stats->mprc);
2047
2048         /* Good Rx loopback packets */
2049         UPDATE_VF_STAT(E1000_VFGPRLBC,
2050             hw_stats->last_gprlbc, hw_stats->gprlbc);
2051
2052         /* Good Rx loopback octets */
2053         UPDATE_VF_STAT(E1000_VFGORLBC,
2054             hw_stats->last_gorlbc, hw_stats->gorlbc);
2055
2056         /* Good Tx loopback packets */
2057         UPDATE_VF_STAT(E1000_VFGPTLBC,
2058             hw_stats->last_gptlbc, hw_stats->gptlbc);
2059
2060         /* Good Tx loopback octets */
2061         UPDATE_VF_STAT(E1000_VFGOTLBC,
2062             hw_stats->last_gotlbc, hw_stats->gotlbc);
2063 }
2064
2065 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2066                                      struct rte_eth_xstat_name *xstats_names,
2067                                      __rte_unused unsigned limit)
2068 {
2069         unsigned i;
2070
2071         if (xstats_names != NULL)
2072                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2073                         strlcpy(xstats_names[i].name,
2074                                 rte_igbvf_stats_strings[i].name,
2075                                 sizeof(xstats_names[i].name));
2076                 }
2077         return IGBVF_NB_XSTATS;
2078 }
2079
2080 static int
2081 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2082                      unsigned n)
2083 {
2084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2086                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2087         unsigned i;
2088
2089         if (n < IGBVF_NB_XSTATS)
2090                 return IGBVF_NB_XSTATS;
2091
2092         igbvf_read_stats_registers(hw, hw_stats);
2093
2094         if (!xstats)
2095                 return 0;
2096
2097         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2098                 xstats[i].id = i;
2099                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2100                         rte_igbvf_stats_strings[i].offset);
2101         }
2102
2103         return IGBVF_NB_XSTATS;
2104 }
2105
2106 static int
2107 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2108 {
2109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2111                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2112
2113         igbvf_read_stats_registers(hw, hw_stats);
2114
2115         if (rte_stats == NULL)
2116                 return -EINVAL;
2117
2118         rte_stats->ipackets = hw_stats->gprc;
2119         rte_stats->ibytes = hw_stats->gorc;
2120         rte_stats->opackets = hw_stats->gptc;
2121         rte_stats->obytes = hw_stats->gotc;
2122         return 0;
2123 }
2124
2125 static int
2126 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2127 {
2128         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2129                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2130
2131         /* Sync HW register to the last stats */
2132         eth_igbvf_stats_get(dev, NULL);
2133
2134         /* reset HW current stats*/
2135         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2136                offsetof(struct e1000_vf_stats, gprc));
2137
2138         return 0;
2139 }
2140
2141 static int
2142 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2143                        size_t fw_size)
2144 {
2145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146         struct e1000_fw_version fw;
2147         int ret;
2148
2149         e1000_get_fw_version(hw, &fw);
2150
2151         switch (hw->mac.type) {
2152         case e1000_i210:
2153         case e1000_i211:
2154                 if (!(e1000_get_flash_presence_i210(hw))) {
2155                         ret = snprintf(fw_version, fw_size,
2156                                  "%2d.%2d-%d",
2157                                  fw.invm_major, fw.invm_minor,
2158                                  fw.invm_img_type);
2159                         break;
2160                 }
2161                 /* fall through */
2162         default:
2163                 /* if option rom is valid, display its version too */
2164                 if (fw.or_valid) {
2165                         ret = snprintf(fw_version, fw_size,
2166                                  "%d.%d, 0x%08x, %d.%d.%d",
2167                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2168                                  fw.or_major, fw.or_build, fw.or_patch);
2169                 /* no option rom */
2170                 } else {
2171                         if (fw.etrack_id != 0X0000) {
2172                                 ret = snprintf(fw_version, fw_size,
2173                                          "%d.%d, 0x%08x",
2174                                          fw.eep_major, fw.eep_minor,
2175                                          fw.etrack_id);
2176                         } else {
2177                                 ret = snprintf(fw_version, fw_size,
2178                                          "%d.%d.%d",
2179                                          fw.eep_major, fw.eep_minor,
2180                                          fw.eep_build);
2181                         }
2182                 }
2183                 break;
2184         }
2185
2186         ret += 1; /* add the size of '\0' */
2187         if (fw_size < (u32)ret)
2188                 return ret;
2189         else
2190                 return 0;
2191 }
2192
2193 static int
2194 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2195 {
2196         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2197
2198         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2199         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2200         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2201         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2202         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2203                                     dev_info->rx_queue_offload_capa;
2204         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2205         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2206                                     dev_info->tx_queue_offload_capa;
2207
2208         switch (hw->mac.type) {
2209         case e1000_82575:
2210                 dev_info->max_rx_queues = 4;
2211                 dev_info->max_tx_queues = 4;
2212                 dev_info->max_vmdq_pools = 0;
2213                 break;
2214
2215         case e1000_82576:
2216                 dev_info->max_rx_queues = 16;
2217                 dev_info->max_tx_queues = 16;
2218                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2219                 dev_info->vmdq_queue_num = 16;
2220                 break;
2221
2222         case e1000_82580:
2223                 dev_info->max_rx_queues = 8;
2224                 dev_info->max_tx_queues = 8;
2225                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2226                 dev_info->vmdq_queue_num = 8;
2227                 break;
2228
2229         case e1000_i350:
2230                 dev_info->max_rx_queues = 8;
2231                 dev_info->max_tx_queues = 8;
2232                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2233                 dev_info->vmdq_queue_num = 8;
2234                 break;
2235
2236         case e1000_i354:
2237                 dev_info->max_rx_queues = 8;
2238                 dev_info->max_tx_queues = 8;
2239                 break;
2240
2241         case e1000_i210:
2242                 dev_info->max_rx_queues = 4;
2243                 dev_info->max_tx_queues = 4;
2244                 dev_info->max_vmdq_pools = 0;
2245                 break;
2246
2247         case e1000_i211:
2248                 dev_info->max_rx_queues = 2;
2249                 dev_info->max_tx_queues = 2;
2250                 dev_info->max_vmdq_pools = 0;
2251                 break;
2252
2253         default:
2254                 /* Should not happen */
2255                 return -EINVAL;
2256         }
2257         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2258         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2259         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2260
2261         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2262                 .rx_thresh = {
2263                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2264                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2265                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2266                 },
2267                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2268                 .rx_drop_en = 0,
2269                 .offloads = 0,
2270         };
2271
2272         dev_info->default_txconf = (struct rte_eth_txconf) {
2273                 .tx_thresh = {
2274                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2275                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2276                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2277                 },
2278                 .offloads = 0,
2279         };
2280
2281         dev_info->rx_desc_lim = rx_desc_lim;
2282         dev_info->tx_desc_lim = tx_desc_lim;
2283
2284         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2285                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2286                         ETH_LINK_SPEED_1G;
2287
2288         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2289         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2290
2291         return 0;
2292 }
2293
2294 static const uint32_t *
2295 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2296 {
2297         static const uint32_t ptypes[] = {
2298                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2299                 RTE_PTYPE_L2_ETHER,
2300                 RTE_PTYPE_L3_IPV4,
2301                 RTE_PTYPE_L3_IPV4_EXT,
2302                 RTE_PTYPE_L3_IPV6,
2303                 RTE_PTYPE_L3_IPV6_EXT,
2304                 RTE_PTYPE_L4_TCP,
2305                 RTE_PTYPE_L4_UDP,
2306                 RTE_PTYPE_L4_SCTP,
2307                 RTE_PTYPE_TUNNEL_IP,
2308                 RTE_PTYPE_INNER_L3_IPV6,
2309                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2310                 RTE_PTYPE_INNER_L4_TCP,
2311                 RTE_PTYPE_INNER_L4_UDP,
2312                 RTE_PTYPE_UNKNOWN
2313         };
2314
2315         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2316             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2317                 return ptypes;
2318         return NULL;
2319 }
2320
2321 static int
2322 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2323 {
2324         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325
2326         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2327         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2328         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2329         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2330                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2331                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2332                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2333                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2334                                 DEV_TX_OFFLOAD_TCP_TSO;
2335         switch (hw->mac.type) {
2336         case e1000_vfadapt:
2337                 dev_info->max_rx_queues = 2;
2338                 dev_info->max_tx_queues = 2;
2339                 break;
2340         case e1000_vfadapt_i350:
2341                 dev_info->max_rx_queues = 1;
2342                 dev_info->max_tx_queues = 1;
2343                 break;
2344         default:
2345                 /* Should not happen */
2346                 return -EINVAL;
2347         }
2348
2349         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2350         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2351                                     dev_info->rx_queue_offload_capa;
2352         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2353         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2354                                     dev_info->tx_queue_offload_capa;
2355
2356         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2357                 .rx_thresh = {
2358                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2359                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2360                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2361                 },
2362                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2363                 .rx_drop_en = 0,
2364                 .offloads = 0,
2365         };
2366
2367         dev_info->default_txconf = (struct rte_eth_txconf) {
2368                 .tx_thresh = {
2369                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2370                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2371                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2372                 },
2373                 .offloads = 0,
2374         };
2375
2376         dev_info->rx_desc_lim = rx_desc_lim;
2377         dev_info->tx_desc_lim = tx_desc_lim;
2378
2379         return 0;
2380 }
2381
2382 /* return 0 means link status changed, -1 means not changed */
2383 static int
2384 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2385 {
2386         struct e1000_hw *hw =
2387                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct rte_eth_link link;
2389         int link_check, count;
2390
2391         link_check = 0;
2392         hw->mac.get_link_status = 1;
2393
2394         /* possible wait-to-complete in up to 9 seconds */
2395         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2396                 /* Read the real link status */
2397                 switch (hw->phy.media_type) {
2398                 case e1000_media_type_copper:
2399                         /* Do the work to read phy */
2400                         e1000_check_for_link(hw);
2401                         link_check = !hw->mac.get_link_status;
2402                         break;
2403
2404                 case e1000_media_type_fiber:
2405                         e1000_check_for_link(hw);
2406                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2407                                       E1000_STATUS_LU);
2408                         break;
2409
2410                 case e1000_media_type_internal_serdes:
2411                         e1000_check_for_link(hw);
2412                         link_check = hw->mac.serdes_has_link;
2413                         break;
2414
2415                 /* VF device is type_unknown */
2416                 case e1000_media_type_unknown:
2417                         eth_igbvf_link_update(hw);
2418                         link_check = !hw->mac.get_link_status;
2419                         break;
2420
2421                 default:
2422                         break;
2423                 }
2424                 if (link_check || wait_to_complete == 0)
2425                         break;
2426                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2427         }
2428         memset(&link, 0, sizeof(link));
2429
2430         /* Now we check if a transition has happened */
2431         if (link_check) {
2432                 uint16_t duplex, speed;
2433                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2434                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2435                                 ETH_LINK_FULL_DUPLEX :
2436                                 ETH_LINK_HALF_DUPLEX;
2437                 link.link_speed = speed;
2438                 link.link_status = ETH_LINK_UP;
2439                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2440                                 ETH_LINK_SPEED_FIXED);
2441         } else if (!link_check) {
2442                 link.link_speed = 0;
2443                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2444                 link.link_status = ETH_LINK_DOWN;
2445                 link.link_autoneg = ETH_LINK_FIXED;
2446         }
2447
2448         return rte_eth_linkstatus_set(dev, &link);
2449 }
2450
2451 /*
2452  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2453  * For ASF and Pass Through versions of f/w this means
2454  * that the driver is loaded.
2455  */
2456 static void
2457 igb_hw_control_acquire(struct e1000_hw *hw)
2458 {
2459         uint32_t ctrl_ext;
2460
2461         /* Let firmware know the driver has taken over */
2462         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2463         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2464 }
2465
2466 /*
2467  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2468  * For ASF and Pass Through versions of f/w this means that the
2469  * driver is no longer loaded.
2470  */
2471 static void
2472 igb_hw_control_release(struct e1000_hw *hw)
2473 {
2474         uint32_t ctrl_ext;
2475
2476         /* Let firmware taken over control of h/w */
2477         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2478         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2479                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2480 }
2481
2482 /*
2483  * Bit of a misnomer, what this really means is
2484  * to enable OS management of the system... aka
2485  * to disable special hardware management features.
2486  */
2487 static void
2488 igb_init_manageability(struct e1000_hw *hw)
2489 {
2490         if (e1000_enable_mng_pass_thru(hw)) {
2491                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2492                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2493
2494                 /* disable hardware interception of ARP */
2495                 manc &= ~(E1000_MANC_ARP_EN);
2496
2497                 /* enable receiving management packets to the host */
2498                 manc |= E1000_MANC_EN_MNG2HOST;
2499                 manc2h |= 1 << 5;  /* Mng Port 623 */
2500                 manc2h |= 1 << 6;  /* Mng Port 664 */
2501                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2502                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2503         }
2504 }
2505
2506 static void
2507 igb_release_manageability(struct e1000_hw *hw)
2508 {
2509         if (e1000_enable_mng_pass_thru(hw)) {
2510                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2511
2512                 manc |= E1000_MANC_ARP_EN;
2513                 manc &= ~E1000_MANC_EN_MNG2HOST;
2514
2515                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2516         }
2517 }
2518
2519 static int
2520 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2521 {
2522         struct e1000_hw *hw =
2523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         uint32_t rctl;
2525
2526         rctl = E1000_READ_REG(hw, E1000_RCTL);
2527         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2528         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2529
2530         return 0;
2531 }
2532
2533 static int
2534 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2535 {
2536         struct e1000_hw *hw =
2537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t rctl;
2539
2540         rctl = E1000_READ_REG(hw, E1000_RCTL);
2541         rctl &= (~E1000_RCTL_UPE);
2542         if (dev->data->all_multicast == 1)
2543                 rctl |= E1000_RCTL_MPE;
2544         else
2545                 rctl &= (~E1000_RCTL_MPE);
2546         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2547
2548         return 0;
2549 }
2550
2551 static int
2552 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2553 {
2554         struct e1000_hw *hw =
2555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         uint32_t rctl;
2557
2558         rctl = E1000_READ_REG(hw, E1000_RCTL);
2559         rctl |= E1000_RCTL_MPE;
2560         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2561
2562         return 0;
2563 }
2564
2565 static int
2566 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2567 {
2568         struct e1000_hw *hw =
2569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         uint32_t rctl;
2571
2572         if (dev->data->promiscuous == 1)
2573                 return 0; /* must remain in all_multicast mode */
2574         rctl = E1000_READ_REG(hw, E1000_RCTL);
2575         rctl &= (~E1000_RCTL_MPE);
2576         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2577
2578         return 0;
2579 }
2580
2581 static int
2582 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2583 {
2584         struct e1000_hw *hw =
2585                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         struct e1000_vfta * shadow_vfta =
2587                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2588         uint32_t vfta;
2589         uint32_t vid_idx;
2590         uint32_t vid_bit;
2591
2592         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2593                               E1000_VFTA_ENTRY_MASK);
2594         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2595         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2596         if (on)
2597                 vfta |= vid_bit;
2598         else
2599                 vfta &= ~vid_bit;
2600         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2601
2602         /* update local VFTA copy */
2603         shadow_vfta->vfta[vid_idx] = vfta;
2604
2605         return 0;
2606 }
2607
2608 static int
2609 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2610                       enum rte_vlan_type vlan_type,
2611                       uint16_t tpid)
2612 {
2613         struct e1000_hw *hw =
2614                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615         uint32_t reg, qinq;
2616
2617         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2618         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2619
2620         /* only outer TPID of double VLAN can be configured*/
2621         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2622                 reg = E1000_READ_REG(hw, E1000_VET);
2623                 reg = (reg & (~E1000_VET_VET_EXT)) |
2624                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2625                 E1000_WRITE_REG(hw, E1000_VET, reg);
2626
2627                 return 0;
2628         }
2629
2630         /* all other TPID values are read-only*/
2631         PMD_DRV_LOG(ERR, "Not supported");
2632
2633         return -ENOTSUP;
2634 }
2635
2636 static void
2637 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2638 {
2639         struct e1000_hw *hw =
2640                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641         uint32_t reg;
2642
2643         /* Filter Table Disable */
2644         reg = E1000_READ_REG(hw, E1000_RCTL);
2645         reg &= ~E1000_RCTL_CFIEN;
2646         reg &= ~E1000_RCTL_VFE;
2647         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2648 }
2649
2650 static void
2651 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2652 {
2653         struct e1000_hw *hw =
2654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655         struct e1000_vfta * shadow_vfta =
2656                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2657         uint32_t reg;
2658         int i;
2659
2660         /* Filter Table Enable, CFI not used for packet acceptance */
2661         reg = E1000_READ_REG(hw, E1000_RCTL);
2662         reg &= ~E1000_RCTL_CFIEN;
2663         reg |= E1000_RCTL_VFE;
2664         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2665
2666         /* restore VFTA table */
2667         for (i = 0; i < IGB_VFTA_SIZE; i++)
2668                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2669 }
2670
2671 static void
2672 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2673 {
2674         struct e1000_hw *hw =
2675                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676         uint32_t reg;
2677
2678         /* VLAN Mode Disable */
2679         reg = E1000_READ_REG(hw, E1000_CTRL);
2680         reg &= ~E1000_CTRL_VME;
2681         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2682 }
2683
2684 static void
2685 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2686 {
2687         struct e1000_hw *hw =
2688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         uint32_t reg;
2690
2691         /* VLAN Mode Enable */
2692         reg = E1000_READ_REG(hw, E1000_CTRL);
2693         reg |= E1000_CTRL_VME;
2694         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2695 }
2696
2697 static void
2698 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2699 {
2700         struct e1000_hw *hw =
2701                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         uint32_t reg;
2703
2704         /* CTRL_EXT: Extended VLAN */
2705         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2706         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2707         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2708
2709         /* Update maximum packet length */
2710         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2711                 E1000_WRITE_REG(hw, E1000_RLPML,
2712                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2713                                                 VLAN_TAG_SIZE);
2714 }
2715
2716 static void
2717 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2718 {
2719         struct e1000_hw *hw =
2720                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721         uint32_t reg;
2722
2723         /* CTRL_EXT: Extended VLAN */
2724         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2725         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2726         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2727
2728         /* Update maximum packet length */
2729         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2730                 E1000_WRITE_REG(hw, E1000_RLPML,
2731                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2732                                                 2 * VLAN_TAG_SIZE);
2733 }
2734
2735 static int
2736 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2737 {
2738         struct rte_eth_rxmode *rxmode;
2739
2740         rxmode = &dev->data->dev_conf.rxmode;
2741         if(mask & ETH_VLAN_STRIP_MASK){
2742                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2743                         igb_vlan_hw_strip_enable(dev);
2744                 else
2745                         igb_vlan_hw_strip_disable(dev);
2746         }
2747
2748         if(mask & ETH_VLAN_FILTER_MASK){
2749                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2750                         igb_vlan_hw_filter_enable(dev);
2751                 else
2752                         igb_vlan_hw_filter_disable(dev);
2753         }
2754
2755         if(mask & ETH_VLAN_EXTEND_MASK){
2756                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2757                         igb_vlan_hw_extend_enable(dev);
2758                 else
2759                         igb_vlan_hw_extend_disable(dev);
2760         }
2761
2762         return 0;
2763 }
2764
2765
2766 /**
2767  * It enables the interrupt mask and then enable the interrupt.
2768  *
2769  * @param dev
2770  *  Pointer to struct rte_eth_dev.
2771  * @param on
2772  *  Enable or Disable
2773  *
2774  * @return
2775  *  - On success, zero.
2776  *  - On failure, a negative value.
2777  */
2778 static int
2779 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2780 {
2781         struct e1000_interrupt *intr =
2782                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2783
2784         if (on)
2785                 intr->mask |= E1000_ICR_LSC;
2786         else
2787                 intr->mask &= ~E1000_ICR_LSC;
2788
2789         return 0;
2790 }
2791
2792 /* It clears the interrupt causes and enables the interrupt.
2793  * It will be called once only during nic initialized.
2794  *
2795  * @param dev
2796  *  Pointer to struct rte_eth_dev.
2797  *
2798  * @return
2799  *  - On success, zero.
2800  *  - On failure, a negative value.
2801  */
2802 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2803 {
2804         uint32_t mask, regval;
2805         int ret;
2806         struct e1000_hw *hw =
2807                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2810         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2811         struct rte_eth_dev_info dev_info;
2812
2813         memset(&dev_info, 0, sizeof(dev_info));
2814         ret = eth_igb_infos_get(dev, &dev_info);
2815         if (ret != 0)
2816                 return ret;
2817
2818         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2819         regval = E1000_READ_REG(hw, E1000_EIMS);
2820         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2821
2822         return 0;
2823 }
2824
2825 /*
2826  * It reads ICR and gets interrupt causes, check it and set a bit flag
2827  * to update link status.
2828  *
2829  * @param dev
2830  *  Pointer to struct rte_eth_dev.
2831  *
2832  * @return
2833  *  - On success, zero.
2834  *  - On failure, a negative value.
2835  */
2836 static int
2837 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2838 {
2839         uint32_t icr;
2840         struct e1000_hw *hw =
2841                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         struct e1000_interrupt *intr =
2843                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2844
2845         igb_intr_disable(dev);
2846
2847         /* read-on-clear nic registers here */
2848         icr = E1000_READ_REG(hw, E1000_ICR);
2849
2850         intr->flags = 0;
2851         if (icr & E1000_ICR_LSC) {
2852                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2853         }
2854
2855         if (icr & E1000_ICR_VMMB)
2856                 intr->flags |= E1000_FLAG_MAILBOX;
2857
2858         return 0;
2859 }
2860
2861 /*
2862  * It executes link_update after knowing an interrupt is prsent.
2863  *
2864  * @param dev
2865  *  Pointer to struct rte_eth_dev.
2866  *
2867  * @return
2868  *  - On success, zero.
2869  *  - On failure, a negative value.
2870  */
2871 static int
2872 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2873                          struct rte_intr_handle *intr_handle)
2874 {
2875         struct e1000_hw *hw =
2876                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct e1000_interrupt *intr =
2878                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2879         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2880         struct rte_eth_link link;
2881         int ret;
2882
2883         if (intr->flags & E1000_FLAG_MAILBOX) {
2884                 igb_pf_mbx_process(dev);
2885                 intr->flags &= ~E1000_FLAG_MAILBOX;
2886         }
2887
2888         igb_intr_enable(dev);
2889         rte_intr_ack(intr_handle);
2890
2891         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2892                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2893
2894                 /* set get_link_status to check register later */
2895                 hw->mac.get_link_status = 1;
2896                 ret = eth_igb_link_update(dev, 0);
2897
2898                 /* check if link has changed */
2899                 if (ret < 0)
2900                         return 0;
2901
2902                 rte_eth_linkstatus_get(dev, &link);
2903                 if (link.link_status) {
2904                         PMD_INIT_LOG(INFO,
2905                                      " Port %d: Link Up - speed %u Mbps - %s",
2906                                      dev->data->port_id,
2907                                      (unsigned)link.link_speed,
2908                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2909                                      "full-duplex" : "half-duplex");
2910                 } else {
2911                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2912                                      dev->data->port_id);
2913                 }
2914
2915                 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2916                              pci_dev->addr.domain,
2917                              pci_dev->addr.bus,
2918                              pci_dev->addr.devid,
2919                              pci_dev->addr.function);
2920                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2921         }
2922
2923         return 0;
2924 }
2925
2926 /**
2927  * Interrupt handler which shall be registered at first.
2928  *
2929  * @param handle
2930  *  Pointer to interrupt handle.
2931  * @param param
2932  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2933  *
2934  * @return
2935  *  void
2936  */
2937 static void
2938 eth_igb_interrupt_handler(void *param)
2939 {
2940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2941
2942         eth_igb_interrupt_get_status(dev);
2943         eth_igb_interrupt_action(dev, dev->intr_handle);
2944 }
2945
2946 static int
2947 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2948 {
2949         uint32_t eicr;
2950         struct e1000_hw *hw =
2951                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         struct e1000_interrupt *intr =
2953                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2954
2955         igbvf_intr_disable(hw);
2956
2957         /* read-on-clear nic registers here */
2958         eicr = E1000_READ_REG(hw, E1000_EICR);
2959         intr->flags = 0;
2960
2961         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2962                 intr->flags |= E1000_FLAG_MAILBOX;
2963
2964         return 0;
2965 }
2966
2967 void igbvf_mbx_process(struct rte_eth_dev *dev)
2968 {
2969         struct e1000_hw *hw =
2970                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         struct e1000_mbx_info *mbx = &hw->mbx;
2972         u32 in_msg = 0;
2973
2974         /* peek the message first */
2975         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2976
2977         /* PF reset VF event */
2978         if (in_msg == E1000_PF_CONTROL_MSG) {
2979                 /* dummy mbx read to ack pf */
2980                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2981                         return;
2982                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2983                                              NULL);
2984         }
2985 }
2986
2987 static int
2988 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2989 {
2990         struct e1000_interrupt *intr =
2991                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2992
2993         if (intr->flags & E1000_FLAG_MAILBOX) {
2994                 igbvf_mbx_process(dev);
2995                 intr->flags &= ~E1000_FLAG_MAILBOX;
2996         }
2997
2998         igbvf_intr_enable(dev);
2999         rte_intr_ack(intr_handle);
3000
3001         return 0;
3002 }
3003
3004 static void
3005 eth_igbvf_interrupt_handler(void *param)
3006 {
3007         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3008
3009         eth_igbvf_interrupt_get_status(dev);
3010         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3011 }
3012
3013 static int
3014 eth_igb_led_on(struct rte_eth_dev *dev)
3015 {
3016         struct e1000_hw *hw;
3017
3018         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3020 }
3021
3022 static int
3023 eth_igb_led_off(struct rte_eth_dev *dev)
3024 {
3025         struct e1000_hw *hw;
3026
3027         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3029 }
3030
3031 static int
3032 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3033 {
3034         struct e1000_hw *hw;
3035         uint32_t ctrl;
3036         int tx_pause;
3037         int rx_pause;
3038
3039         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040         fc_conf->pause_time = hw->fc.pause_time;
3041         fc_conf->high_water = hw->fc.high_water;
3042         fc_conf->low_water = hw->fc.low_water;
3043         fc_conf->send_xon = hw->fc.send_xon;
3044         fc_conf->autoneg = hw->mac.autoneg;
3045
3046         /*
3047          * Return rx_pause and tx_pause status according to actual setting of
3048          * the TFCE and RFCE bits in the CTRL register.
3049          */
3050         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3051         if (ctrl & E1000_CTRL_TFCE)
3052                 tx_pause = 1;
3053         else
3054                 tx_pause = 0;
3055
3056         if (ctrl & E1000_CTRL_RFCE)
3057                 rx_pause = 1;
3058         else
3059                 rx_pause = 0;
3060
3061         if (rx_pause && tx_pause)
3062                 fc_conf->mode = RTE_FC_FULL;
3063         else if (rx_pause)
3064                 fc_conf->mode = RTE_FC_RX_PAUSE;
3065         else if (tx_pause)
3066                 fc_conf->mode = RTE_FC_TX_PAUSE;
3067         else
3068                 fc_conf->mode = RTE_FC_NONE;
3069
3070         return 0;
3071 }
3072
3073 static int
3074 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3075 {
3076         struct e1000_hw *hw;
3077         int err;
3078         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3079                 e1000_fc_none,
3080                 e1000_fc_rx_pause,
3081                 e1000_fc_tx_pause,
3082                 e1000_fc_full
3083         };
3084         uint32_t rx_buf_size;
3085         uint32_t max_high_water;
3086         uint32_t rctl;
3087
3088         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089         if (fc_conf->autoneg != hw->mac.autoneg)
3090                 return -ENOTSUP;
3091         rx_buf_size = igb_get_rx_buffer_size(hw);
3092         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3093
3094         /* At least reserve one Ethernet frame for watermark */
3095         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3096         if ((fc_conf->high_water > max_high_water) ||
3097             (fc_conf->high_water < fc_conf->low_water)) {
3098                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3099                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3100                 return -EINVAL;
3101         }
3102
3103         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3104         hw->fc.pause_time     = fc_conf->pause_time;
3105         hw->fc.high_water     = fc_conf->high_water;
3106         hw->fc.low_water      = fc_conf->low_water;
3107         hw->fc.send_xon       = fc_conf->send_xon;
3108
3109         err = e1000_setup_link_generic(hw);
3110         if (err == E1000_SUCCESS) {
3111
3112                 /* check if we want to forward MAC frames - driver doesn't have native
3113                  * capability to do that, so we'll write the registers ourselves */
3114
3115                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3116
3117                 /* set or clear MFLCN.PMCF bit depending on configuration */
3118                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3119                         rctl |= E1000_RCTL_PMCF;
3120                 else
3121                         rctl &= ~E1000_RCTL_PMCF;
3122
3123                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3124                 E1000_WRITE_FLUSH(hw);
3125
3126                 return 0;
3127         }
3128
3129         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3130         return -EIO;
3131 }
3132
3133 #define E1000_RAH_POOLSEL_SHIFT      (18)
3134 static int
3135 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3136                 uint32_t index, uint32_t pool)
3137 {
3138         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139         uint32_t rah;
3140
3141         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3142         rah = E1000_READ_REG(hw, E1000_RAH(index));
3143         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3144         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3145         return 0;
3146 }
3147
3148 static void
3149 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3150 {
3151         uint8_t addr[RTE_ETHER_ADDR_LEN];
3152         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3153
3154         memset(addr, 0, sizeof(addr));
3155
3156         e1000_rar_set(hw, addr, index);
3157 }
3158
3159 static int
3160 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3161                                 struct rte_ether_addr *addr)
3162 {
3163         eth_igb_rar_clear(dev, 0);
3164         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3165
3166         return 0;
3167 }
3168 /*
3169  * Virtual Function operations
3170  */
3171 static void
3172 igbvf_intr_disable(struct e1000_hw *hw)
3173 {
3174         PMD_INIT_FUNC_TRACE();
3175
3176         /* Clear interrupt mask to stop from interrupts being generated */
3177         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3178
3179         E1000_WRITE_FLUSH(hw);
3180 }
3181
3182 static void
3183 igbvf_stop_adapter(struct rte_eth_dev *dev)
3184 {
3185         u32 reg_val;
3186         u16 i;
3187         struct rte_eth_dev_info dev_info;
3188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189         int ret;
3190
3191         memset(&dev_info, 0, sizeof(dev_info));
3192         ret = eth_igbvf_infos_get(dev, &dev_info);
3193         if (ret != 0)
3194                 return;
3195
3196         /* Clear interrupt mask to stop from interrupts being generated */
3197         igbvf_intr_disable(hw);
3198
3199         /* Clear any pending interrupts, flush previous writes */
3200         E1000_READ_REG(hw, E1000_EICR);
3201
3202         /* Disable the transmit unit.  Each queue must be disabled. */
3203         for (i = 0; i < dev_info.max_tx_queues; i++)
3204                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3205
3206         /* Disable the receive unit by stopping each queue */
3207         for (i = 0; i < dev_info.max_rx_queues; i++) {
3208                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3209                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3210                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3211                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3212                         ;
3213         }
3214
3215         /* flush all queues disables */
3216         E1000_WRITE_FLUSH(hw);
3217         msec_delay(2);
3218 }
3219
3220 static int eth_igbvf_link_update(struct e1000_hw *hw)
3221 {
3222         struct e1000_mbx_info *mbx = &hw->mbx;
3223         struct e1000_mac_info *mac = &hw->mac;
3224         int ret_val = E1000_SUCCESS;
3225
3226         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3227
3228         /*
3229          * We only want to run this if there has been a rst asserted.
3230          * in this case that could mean a link change, device reset,
3231          * or a virtual function reset
3232          */
3233
3234         /* If we were hit with a reset or timeout drop the link */
3235         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3236                 mac->get_link_status = TRUE;
3237
3238         if (!mac->get_link_status)
3239                 goto out;
3240
3241         /* if link status is down no point in checking to see if pf is up */
3242         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3243                 goto out;
3244
3245         /* if we passed all the tests above then the link is up and we no
3246          * longer need to check for link */
3247         mac->get_link_status = FALSE;
3248
3249 out:
3250         return ret_val;
3251 }
3252
3253
3254 static int
3255 igbvf_dev_configure(struct rte_eth_dev *dev)
3256 {
3257         struct rte_eth_conf* conf = &dev->data->dev_conf;
3258
3259         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3260                      dev->data->port_id);
3261
3262         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3263                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3264
3265         /*
3266          * VF has no ability to enable/disable HW CRC
3267          * Keep the persistent behavior the same as Host PF
3268          */
3269 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3270         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3271                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3272                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3273         }
3274 #else
3275         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3276                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3277                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3278         }
3279 #endif
3280
3281         return 0;
3282 }
3283
3284 static int
3285 igbvf_dev_start(struct rte_eth_dev *dev)
3286 {
3287         struct e1000_hw *hw =
3288                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3289         struct e1000_adapter *adapter =
3290                 E1000_DEV_PRIVATE(dev->data->dev_private);
3291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3293         int ret;
3294         uint32_t intr_vector = 0;
3295
3296         PMD_INIT_FUNC_TRACE();
3297
3298         hw->mac.ops.reset_hw(hw);
3299         adapter->stopped = 0;
3300
3301         /* Set all vfta */
3302         igbvf_set_vfta_all(dev,1);
3303
3304         eth_igbvf_tx_init(dev);
3305
3306         /* This can fail when allocating mbufs for descriptor rings */
3307         ret = eth_igbvf_rx_init(dev);
3308         if (ret) {
3309                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3310                 igb_dev_clear_queues(dev);
3311                 return ret;
3312         }
3313
3314         /* check and configure queue intr-vector mapping */
3315         if (rte_intr_cap_multiple(intr_handle) &&
3316             dev->data->dev_conf.intr_conf.rxq) {
3317                 intr_vector = dev->data->nb_rx_queues;
3318                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3319                 if (ret)
3320                         return ret;
3321         }
3322
3323         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3324                 intr_handle->intr_vec =
3325                         rte_zmalloc("intr_vec",
3326                                     dev->data->nb_rx_queues * sizeof(int), 0);
3327                 if (!intr_handle->intr_vec) {
3328                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3329                                      " intr_vec", dev->data->nb_rx_queues);
3330                         return -ENOMEM;
3331                 }
3332         }
3333
3334         eth_igbvf_configure_msix_intr(dev);
3335
3336         /* enable uio/vfio intr/eventfd mapping */
3337         rte_intr_enable(intr_handle);
3338
3339         /* resume enabled intr since hw reset */
3340         igbvf_intr_enable(dev);
3341
3342         return 0;
3343 }
3344
3345 static int
3346 igbvf_dev_stop(struct rte_eth_dev *dev)
3347 {
3348         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3349         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3350         struct e1000_adapter *adapter =
3351                 E1000_DEV_PRIVATE(dev->data->dev_private);
3352
3353         if (adapter->stopped)
3354                 return 0;
3355
3356         PMD_INIT_FUNC_TRACE();
3357
3358         igbvf_stop_adapter(dev);
3359
3360         /*
3361           * Clear what we set, but we still keep shadow_vfta to
3362           * restore after device starts
3363           */
3364         igbvf_set_vfta_all(dev,0);
3365
3366         igb_dev_clear_queues(dev);
3367
3368         /* disable intr eventfd mapping */
3369         rte_intr_disable(intr_handle);
3370
3371         /* Clean datapath event and queue/vec mapping */
3372         rte_intr_efd_disable(intr_handle);
3373         if (intr_handle->intr_vec) {
3374                 rte_free(intr_handle->intr_vec);
3375                 intr_handle->intr_vec = NULL;
3376         }
3377
3378         adapter->stopped = true;
3379         dev->data->dev_started = 0;
3380
3381         return 0;
3382 }
3383
3384 static int
3385 igbvf_dev_close(struct rte_eth_dev *dev)
3386 {
3387         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388         struct rte_ether_addr addr;
3389         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3390         int ret;
3391
3392         PMD_INIT_FUNC_TRACE();
3393
3394         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3395                 return 0;
3396
3397         e1000_reset_hw(hw);
3398
3399         ret = igbvf_dev_stop(dev);
3400         if (ret != 0)
3401                 return ret;
3402
3403         igb_dev_free_queues(dev);
3404
3405         /**
3406          * reprogram the RAR with a zero mac address,
3407          * to ensure that the VF traffic goes to the PF
3408          * after stop, close and detach of the VF.
3409          **/
3410
3411         memset(&addr, 0, sizeof(addr));
3412         igbvf_default_mac_addr_set(dev, &addr);
3413
3414         rte_intr_callback_unregister(&pci_dev->intr_handle,
3415                                      eth_igbvf_interrupt_handler,
3416                                      (void *)dev);
3417
3418         return 0;
3419 }
3420
3421 static int
3422 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3423 {
3424         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425
3426         /* Set both unicast and multicast promisc */
3427         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3428
3429         return 0;
3430 }
3431
3432 static int
3433 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3434 {
3435         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436
3437         /* If in allmulticast mode leave multicast promisc */
3438         if (dev->data->all_multicast == 1)
3439                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3440         else
3441                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3442
3443         return 0;
3444 }
3445
3446 static int
3447 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3448 {
3449         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450
3451         /* In promiscuous mode multicast promisc already set */
3452         if (dev->data->promiscuous == 0)
3453                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3454
3455         return 0;
3456 }
3457
3458 static int
3459 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3460 {
3461         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462
3463         /* In promiscuous mode leave multicast promisc enabled */
3464         if (dev->data->promiscuous == 0)
3465                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3466
3467         return 0;
3468 }
3469
3470 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3471 {
3472         struct e1000_mbx_info *mbx = &hw->mbx;
3473         uint32_t msgbuf[2];
3474         s32 err;
3475
3476         /* After set vlan, vlan strip will also be enabled in igb driver*/
3477         msgbuf[0] = E1000_VF_SET_VLAN;
3478         msgbuf[1] = vid;
3479         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3480         if (on)
3481                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3482
3483         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3484         if (err)
3485                 goto mbx_err;
3486
3487         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3488         if (err)
3489                 goto mbx_err;
3490
3491         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3492         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3493                 err = -EINVAL;
3494
3495 mbx_err:
3496         return err;
3497 }
3498
3499 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3500 {
3501         struct e1000_hw *hw =
3502                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3503         struct e1000_vfta * shadow_vfta =
3504                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3505         int i = 0, j = 0, vfta = 0, mask = 1;
3506
3507         for (i = 0; i < IGB_VFTA_SIZE; i++){
3508                 vfta = shadow_vfta->vfta[i];
3509                 if(vfta){
3510                         mask = 1;
3511                         for (j = 0; j < 32; j++){
3512                                 if(vfta & mask)
3513                                         igbvf_set_vfta(hw,
3514                                                 (uint16_t)((i<<5)+j), on);
3515                                 mask<<=1;
3516                         }
3517                 }
3518         }
3519
3520 }
3521
3522 static int
3523 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3524 {
3525         struct e1000_hw *hw =
3526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3527         struct e1000_vfta * shadow_vfta =
3528                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3529         uint32_t vid_idx = 0;
3530         uint32_t vid_bit = 0;
3531         int ret = 0;
3532
3533         PMD_INIT_FUNC_TRACE();
3534
3535         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3536         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3537         if(ret){
3538                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3539                 return ret;
3540         }
3541         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3542         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3543
3544         /*Save what we set and retore it after device reset*/
3545         if (on)
3546                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3547         else
3548                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3549
3550         return 0;
3551 }
3552
3553 static int
3554 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3555 {
3556         struct e1000_hw *hw =
3557                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558
3559         /* index is not used by rar_set() */
3560         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3561         return 0;
3562 }
3563
3564
3565 static int
3566 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3567                         struct rte_eth_rss_reta_entry64 *reta_conf,
3568                         uint16_t reta_size)
3569 {
3570         uint8_t i, j, mask;
3571         uint32_t reta, r;
3572         uint16_t idx, shift;
3573         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574
3575         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3576                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3577                         "(%d) doesn't match the number hardware can supported "
3578                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3579                 return -EINVAL;
3580         }
3581
3582         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3583                 idx = i / RTE_RETA_GROUP_SIZE;
3584                 shift = i % RTE_RETA_GROUP_SIZE;
3585                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3586                                                 IGB_4_BIT_MASK);
3587                 if (!mask)
3588                         continue;
3589                 if (mask == IGB_4_BIT_MASK)
3590                         r = 0;
3591                 else
3592                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3593                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3594                         if (mask & (0x1 << j))
3595                                 reta |= reta_conf[idx].reta[shift + j] <<
3596                                                         (CHAR_BIT * j);
3597                         else
3598                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3599                 }
3600                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3601         }
3602
3603         return 0;
3604 }
3605
3606 static int
3607 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3608                        struct rte_eth_rss_reta_entry64 *reta_conf,
3609                        uint16_t reta_size)
3610 {
3611         uint8_t i, j, mask;
3612         uint32_t reta;
3613         uint16_t idx, shift;
3614         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615
3616         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3617                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3618                         "(%d) doesn't match the number hardware can supported "
3619                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3620                 return -EINVAL;
3621         }
3622
3623         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3624                 idx = i / RTE_RETA_GROUP_SIZE;
3625                 shift = i % RTE_RETA_GROUP_SIZE;
3626                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3627                                                 IGB_4_BIT_MASK);
3628                 if (!mask)
3629                         continue;
3630                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3631                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3632                         if (mask & (0x1 << j))
3633                                 reta_conf[idx].reta[shift + j] =
3634                                         ((reta >> (CHAR_BIT * j)) &
3635                                                 IGB_8_BIT_MASK);
3636                 }
3637         }
3638
3639         return 0;
3640 }
3641
3642 int
3643 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3644                         struct rte_eth_syn_filter *filter,
3645                         bool add)
3646 {
3647         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648         struct e1000_filter_info *filter_info =
3649                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3650         uint32_t synqf, rfctl;
3651
3652         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3653                 return -EINVAL;
3654
3655         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3656
3657         if (add) {
3658                 if (synqf & E1000_SYN_FILTER_ENABLE)
3659                         return -EINVAL;
3660
3661                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3662                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3663
3664                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3665                 if (filter->hig_pri)
3666                         rfctl |= E1000_RFCTL_SYNQFP;
3667                 else
3668                         rfctl &= ~E1000_RFCTL_SYNQFP;
3669
3670                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3671         } else {
3672                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3673                         return -ENOENT;
3674                 synqf = 0;
3675         }
3676
3677         filter_info->syn_info = synqf;
3678         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3679         E1000_WRITE_FLUSH(hw);
3680         return 0;
3681 }
3682
3683 static int
3684 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3685                         struct rte_eth_syn_filter *filter)
3686 {
3687         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3688         uint32_t synqf, rfctl;
3689
3690         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3691         if (synqf & E1000_SYN_FILTER_ENABLE) {
3692                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3693                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3694                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3695                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3696                 return 0;
3697         }
3698
3699         return -ENOENT;
3700 }
3701
3702 static int
3703 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3704                         enum rte_filter_op filter_op,
3705                         void *arg)
3706 {
3707         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3708         int ret;
3709
3710         MAC_TYPE_FILTER_SUP(hw->mac.type);
3711
3712         if (filter_op == RTE_ETH_FILTER_NOP)
3713                 return 0;
3714
3715         if (arg == NULL) {
3716                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3717                             filter_op);
3718                 return -EINVAL;
3719         }
3720
3721         switch (filter_op) {
3722         case RTE_ETH_FILTER_ADD:
3723                 ret = eth_igb_syn_filter_set(dev,
3724                                 (struct rte_eth_syn_filter *)arg,
3725                                 TRUE);
3726                 break;
3727         case RTE_ETH_FILTER_DELETE:
3728                 ret = eth_igb_syn_filter_set(dev,
3729                                 (struct rte_eth_syn_filter *)arg,
3730                                 FALSE);
3731                 break;
3732         case RTE_ETH_FILTER_GET:
3733                 ret = eth_igb_syn_filter_get(dev,
3734                                 (struct rte_eth_syn_filter *)arg);
3735                 break;
3736         default:
3737                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3738                 ret = -EINVAL;
3739                 break;
3740         }
3741
3742         return ret;
3743 }
3744
3745 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3746 static inline int
3747 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3748                         struct e1000_2tuple_filter_info *filter_info)
3749 {
3750         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3751                 return -EINVAL;
3752         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3753                 return -EINVAL;  /* filter index is out of range. */
3754         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
3755                 return -EINVAL;  /* flags is invalid. */
3756
3757         switch (filter->dst_port_mask) {
3758         case UINT16_MAX:
3759                 filter_info->dst_port_mask = 0;
3760                 filter_info->dst_port = filter->dst_port;
3761                 break;
3762         case 0:
3763                 filter_info->dst_port_mask = 1;
3764                 break;
3765         default:
3766                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3767                 return -EINVAL;
3768         }
3769
3770         switch (filter->proto_mask) {
3771         case UINT8_MAX:
3772                 filter_info->proto_mask = 0;
3773                 filter_info->proto = filter->proto;
3774                 break;
3775         case 0:
3776                 filter_info->proto_mask = 1;
3777                 break;
3778         default:
3779                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3780                 return -EINVAL;
3781         }
3782
3783         filter_info->priority = (uint8_t)filter->priority;
3784         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3785                 filter_info->tcp_flags = filter->tcp_flags;
3786         else
3787                 filter_info->tcp_flags = 0;
3788
3789         return 0;
3790 }
3791
3792 static inline struct e1000_2tuple_filter *
3793 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3794                         struct e1000_2tuple_filter_info *key)
3795 {
3796         struct e1000_2tuple_filter *it;
3797
3798         TAILQ_FOREACH(it, filter_list, entries) {
3799                 if (memcmp(key, &it->filter_info,
3800                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3801                         return it;
3802                 }
3803         }
3804         return NULL;
3805 }
3806
3807 /* inject a igb 2tuple filter to HW */
3808 static inline void
3809 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3810                            struct e1000_2tuple_filter *filter)
3811 {
3812         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3813         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3814         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3815         int i;
3816
3817         i = filter->index;
3818         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3819         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3820                 imir |= E1000_IMIR_PORT_BP;
3821         else
3822                 imir &= ~E1000_IMIR_PORT_BP;
3823
3824         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3825
3826         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3827         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3828         ttqf |= (uint32_t)(filter->filter_info.proto &
3829                                                 E1000_TTQF_PROTOCOL_MASK);
3830         if (filter->filter_info.proto_mask == 0)
3831                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3832
3833         /* tcp flags bits setting. */
3834         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
3835                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
3836                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3837                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
3838                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3839                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
3840                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3841                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
3842                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3843                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
3844                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3845                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
3846                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3847         } else {
3848                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3849         }
3850         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3851         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3852         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3853 }
3854
3855 /*
3856  * igb_add_2tuple_filter - add a 2tuple filter
3857  *
3858  * @param
3859  * dev: Pointer to struct rte_eth_dev.
3860  * ntuple_filter: ponter to the filter that will be added.
3861  *
3862  * @return
3863  *    - On success, zero.
3864  *    - On failure, a negative value.
3865  */
3866 static int
3867 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3868                         struct rte_eth_ntuple_filter *ntuple_filter)
3869 {
3870         struct e1000_filter_info *filter_info =
3871                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3872         struct e1000_2tuple_filter *filter;
3873         int i, ret;
3874
3875         filter = rte_zmalloc("e1000_2tuple_filter",
3876                         sizeof(struct e1000_2tuple_filter), 0);
3877         if (filter == NULL)
3878                 return -ENOMEM;
3879
3880         ret = ntuple_filter_to_2tuple(ntuple_filter,
3881                                       &filter->filter_info);
3882         if (ret < 0) {
3883                 rte_free(filter);
3884                 return ret;
3885         }
3886         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3887                                          &filter->filter_info) != NULL) {
3888                 PMD_DRV_LOG(ERR, "filter exists.");
3889                 rte_free(filter);
3890                 return -EEXIST;
3891         }
3892         filter->queue = ntuple_filter->queue;
3893
3894         /*
3895          * look for an unused 2tuple filter index,
3896          * and insert the filter to list.
3897          */
3898         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3899                 if (!(filter_info->twotuple_mask & (1 << i))) {
3900                         filter_info->twotuple_mask |= 1 << i;
3901                         filter->index = i;
3902                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3903                                           filter,
3904                                           entries);
3905                         break;
3906                 }
3907         }
3908         if (i >= E1000_MAX_TTQF_FILTERS) {
3909                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3910                 rte_free(filter);
3911                 return -ENOSYS;
3912         }
3913
3914         igb_inject_2uple_filter(dev, filter);
3915         return 0;
3916 }
3917
3918 int
3919 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3920                         struct e1000_2tuple_filter *filter)
3921 {
3922         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923         struct e1000_filter_info *filter_info =
3924                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3925
3926         filter_info->twotuple_mask &= ~(1 << filter->index);
3927         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3928         rte_free(filter);
3929
3930         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3931         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3932         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3933         return 0;
3934 }
3935
3936 /*
3937  * igb_remove_2tuple_filter - remove a 2tuple filter
3938  *
3939  * @param
3940  * dev: Pointer to struct rte_eth_dev.
3941  * ntuple_filter: ponter to the filter that will be removed.
3942  *
3943  * @return
3944  *    - On success, zero.
3945  *    - On failure, a negative value.
3946  */
3947 static int
3948 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3949                         struct rte_eth_ntuple_filter *ntuple_filter)
3950 {
3951         struct e1000_filter_info *filter_info =
3952                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3953         struct e1000_2tuple_filter_info filter_2tuple;
3954         struct e1000_2tuple_filter *filter;
3955         int ret;
3956
3957         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3958         ret = ntuple_filter_to_2tuple(ntuple_filter,
3959                                       &filter_2tuple);
3960         if (ret < 0)
3961                 return ret;
3962
3963         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3964                                          &filter_2tuple);
3965         if (filter == NULL) {
3966                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3967                 return -ENOENT;
3968         }
3969
3970         igb_delete_2tuple_filter(dev, filter);
3971
3972         return 0;
3973 }
3974
3975 /* inject a igb flex filter to HW */
3976 static inline void
3977 igb_inject_flex_filter(struct rte_eth_dev *dev,
3978                            struct e1000_flex_filter *filter)
3979 {
3980         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3981         uint32_t wufc, queueing;
3982         uint32_t reg_off;
3983         uint8_t i, j = 0;
3984
3985         wufc = E1000_READ_REG(hw, E1000_WUFC);
3986         if (filter->index < E1000_MAX_FHFT)
3987                 reg_off = E1000_FHFT(filter->index);
3988         else
3989                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3990
3991         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3992                         (E1000_WUFC_FLX0 << filter->index));
3993         queueing = filter->filter_info.len |
3994                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3995                 (filter->filter_info.priority <<
3996                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3997         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3998                         queueing);
3999
4000         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
4001                 E1000_WRITE_REG(hw, reg_off,
4002                                 filter->filter_info.dwords[j]);
4003                 reg_off += sizeof(uint32_t);
4004                 E1000_WRITE_REG(hw, reg_off,
4005                                 filter->filter_info.dwords[++j]);
4006                 reg_off += sizeof(uint32_t);
4007                 E1000_WRITE_REG(hw, reg_off,
4008                         (uint32_t)filter->filter_info.mask[i]);
4009                 reg_off += sizeof(uint32_t) * 2;
4010                 ++j;
4011         }
4012 }
4013
4014 static inline struct e1000_flex_filter *
4015 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
4016                         struct e1000_flex_filter_info *key)
4017 {
4018         struct e1000_flex_filter *it;
4019
4020         TAILQ_FOREACH(it, filter_list, entries) {
4021                 if (memcmp(key, &it->filter_info,
4022                         sizeof(struct e1000_flex_filter_info)) == 0)
4023                         return it;
4024         }
4025
4026         return NULL;
4027 }
4028
4029 /* remove a flex byte filter
4030  * @param
4031  * dev: Pointer to struct rte_eth_dev.
4032  * filter: the pointer of the filter will be removed.
4033  */
4034 void
4035 igb_remove_flex_filter(struct rte_eth_dev *dev,
4036                         struct e1000_flex_filter *filter)
4037 {
4038         struct e1000_filter_info *filter_info =
4039                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         uint32_t wufc, i;
4042         uint32_t reg_off;
4043
4044         wufc = E1000_READ_REG(hw, E1000_WUFC);
4045         if (filter->index < E1000_MAX_FHFT)
4046                 reg_off = E1000_FHFT(filter->index);
4047         else
4048                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4049
4050         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4051                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4052
4053         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4054                 (~(E1000_WUFC_FLX0 << filter->index)));
4055
4056         filter_info->flex_mask &= ~(1 << filter->index);
4057         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4058         rte_free(filter);
4059 }
4060
4061 int
4062 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4063                         struct rte_eth_flex_filter *filter,
4064                         bool add)
4065 {
4066         struct e1000_filter_info *filter_info =
4067                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4068         struct e1000_flex_filter *flex_filter, *it;
4069         uint32_t mask;
4070         uint8_t shift, i;
4071
4072         flex_filter = rte_zmalloc("e1000_flex_filter",
4073                         sizeof(struct e1000_flex_filter), 0);
4074         if (flex_filter == NULL)
4075                 return -ENOMEM;
4076
4077         flex_filter->filter_info.len = filter->len;
4078         flex_filter->filter_info.priority = filter->priority;
4079         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4080         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4081                 mask = 0;
4082                 /* reverse bits in flex filter's mask*/
4083                 for (shift = 0; shift < CHAR_BIT; shift++) {
4084                         if (filter->mask[i] & (0x01 << shift))
4085                                 mask |= (0x80 >> shift);
4086                 }
4087                 flex_filter->filter_info.mask[i] = mask;
4088         }
4089
4090         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4091                                 &flex_filter->filter_info);
4092         if (it == NULL && !add) {
4093                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4094                 rte_free(flex_filter);
4095                 return -ENOENT;
4096         }
4097         if (it != NULL && add) {
4098                 PMD_DRV_LOG(ERR, "filter exists.");
4099                 rte_free(flex_filter);
4100                 return -EEXIST;
4101         }
4102
4103         if (add) {
4104                 flex_filter->queue = filter->queue;
4105                 /*
4106                  * look for an unused flex filter index
4107                  * and insert the filter into the list.
4108                  */
4109                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4110                         if (!(filter_info->flex_mask & (1 << i))) {
4111                                 filter_info->flex_mask |= 1 << i;
4112                                 flex_filter->index = i;
4113                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4114                                         flex_filter,
4115                                         entries);
4116                                 break;
4117                         }
4118                 }
4119                 if (i >= E1000_MAX_FLEX_FILTERS) {
4120                         PMD_DRV_LOG(ERR, "flex filters are full.");
4121                         rte_free(flex_filter);
4122                         return -ENOSYS;
4123                 }
4124
4125                 igb_inject_flex_filter(dev, flex_filter);
4126
4127         } else {
4128                 igb_remove_flex_filter(dev, it);
4129                 rte_free(flex_filter);
4130         }
4131
4132         return 0;
4133 }
4134
4135 static int
4136 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4137                         struct rte_eth_flex_filter *filter)
4138 {
4139         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         struct e1000_filter_info *filter_info =
4141                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4142         struct e1000_flex_filter flex_filter, *it;
4143         uint32_t wufc, queueing, wufc_en = 0;
4144
4145         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4146         flex_filter.filter_info.len = filter->len;
4147         flex_filter.filter_info.priority = filter->priority;
4148         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4149         memcpy(flex_filter.filter_info.mask, filter->mask,
4150                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4151
4152         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4153                                 &flex_filter.filter_info);
4154         if (it == NULL) {
4155                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4156                 return -ENOENT;
4157         }
4158
4159         wufc = E1000_READ_REG(hw, E1000_WUFC);
4160         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4161
4162         if ((wufc & wufc_en) == wufc_en) {
4163                 uint32_t reg_off = 0;
4164                 if (it->index < E1000_MAX_FHFT)
4165                         reg_off = E1000_FHFT(it->index);
4166                 else
4167                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4168
4169                 queueing = E1000_READ_REG(hw,
4170                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4171                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4172                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4173                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4174                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4175                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4176                 return 0;
4177         }
4178         return -ENOENT;
4179 }
4180
4181 static int
4182 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4183                         enum rte_filter_op filter_op,
4184                         void *arg)
4185 {
4186         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4187         struct rte_eth_flex_filter *filter;
4188         int ret = 0;
4189
4190         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4191
4192         if (filter_op == RTE_ETH_FILTER_NOP)
4193                 return ret;
4194
4195         if (arg == NULL) {
4196                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4197                             filter_op);
4198                 return -EINVAL;
4199         }
4200
4201         filter = (struct rte_eth_flex_filter *)arg;
4202         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4203             || filter->len % sizeof(uint64_t) != 0) {
4204                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4205                 return -EINVAL;
4206         }
4207         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4208                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4209                 return -EINVAL;
4210         }
4211
4212         switch (filter_op) {
4213         case RTE_ETH_FILTER_ADD:
4214                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4215                 break;
4216         case RTE_ETH_FILTER_DELETE:
4217                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4218                 break;
4219         case RTE_ETH_FILTER_GET:
4220                 ret = eth_igb_get_flex_filter(dev, filter);
4221                 break;
4222         default:
4223                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4224                 ret = -EINVAL;
4225                 break;
4226         }
4227
4228         return ret;
4229 }
4230
4231 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4232 static inline int
4233 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4234                         struct e1000_5tuple_filter_info *filter_info)
4235 {
4236         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4237                 return -EINVAL;
4238         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4239                 return -EINVAL;  /* filter index is out of range. */
4240         if (filter->tcp_flags > RTE_NTUPLE_TCP_FLAGS_MASK)
4241                 return -EINVAL;  /* flags is invalid. */
4242
4243         switch (filter->dst_ip_mask) {
4244         case UINT32_MAX:
4245                 filter_info->dst_ip_mask = 0;
4246                 filter_info->dst_ip = filter->dst_ip;
4247                 break;
4248         case 0:
4249                 filter_info->dst_ip_mask = 1;
4250                 break;
4251         default:
4252                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4253                 return -EINVAL;
4254         }
4255
4256         switch (filter->src_ip_mask) {
4257         case UINT32_MAX:
4258                 filter_info->src_ip_mask = 0;
4259                 filter_info->src_ip = filter->src_ip;
4260                 break;
4261         case 0:
4262                 filter_info->src_ip_mask = 1;
4263                 break;
4264         default:
4265                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4266                 return -EINVAL;
4267         }
4268
4269         switch (filter->dst_port_mask) {
4270         case UINT16_MAX:
4271                 filter_info->dst_port_mask = 0;
4272                 filter_info->dst_port = filter->dst_port;
4273                 break;
4274         case 0:
4275                 filter_info->dst_port_mask = 1;
4276                 break;
4277         default:
4278                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4279                 return -EINVAL;
4280         }
4281
4282         switch (filter->src_port_mask) {
4283         case UINT16_MAX:
4284                 filter_info->src_port_mask = 0;
4285                 filter_info->src_port = filter->src_port;
4286                 break;
4287         case 0:
4288                 filter_info->src_port_mask = 1;
4289                 break;
4290         default:
4291                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4292                 return -EINVAL;
4293         }
4294
4295         switch (filter->proto_mask) {
4296         case UINT8_MAX:
4297                 filter_info->proto_mask = 0;
4298                 filter_info->proto = filter->proto;
4299                 break;
4300         case 0:
4301                 filter_info->proto_mask = 1;
4302                 break;
4303         default:
4304                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4305                 return -EINVAL;
4306         }
4307
4308         filter_info->priority = (uint8_t)filter->priority;
4309         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4310                 filter_info->tcp_flags = filter->tcp_flags;
4311         else
4312                 filter_info->tcp_flags = 0;
4313
4314         return 0;
4315 }
4316
4317 static inline struct e1000_5tuple_filter *
4318 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4319                         struct e1000_5tuple_filter_info *key)
4320 {
4321         struct e1000_5tuple_filter *it;
4322
4323         TAILQ_FOREACH(it, filter_list, entries) {
4324                 if (memcmp(key, &it->filter_info,
4325                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4326                         return it;
4327                 }
4328         }
4329         return NULL;
4330 }
4331
4332 /* inject a igb 5-tuple filter to HW */
4333 static inline void
4334 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4335                            struct e1000_5tuple_filter *filter)
4336 {
4337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4339         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4340         uint8_t i;
4341
4342         i = filter->index;
4343         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4344         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4345                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4346         if (filter->filter_info.dst_ip_mask == 0)
4347                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4348         if (filter->filter_info.src_port_mask == 0)
4349                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4350         if (filter->filter_info.proto_mask == 0)
4351                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4352         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4353                 E1000_FTQF_QUEUE_MASK;
4354         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4355         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4356         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4357         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4358
4359         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4360         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4361
4362         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4363         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4364                 imir |= E1000_IMIR_PORT_BP;
4365         else
4366                 imir &= ~E1000_IMIR_PORT_BP;
4367         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4368
4369         /* tcp flags bits setting. */
4370         if (filter->filter_info.tcp_flags & RTE_NTUPLE_TCP_FLAGS_MASK) {
4371                 if (filter->filter_info.tcp_flags & RTE_TCP_URG_FLAG)
4372                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4373                 if (filter->filter_info.tcp_flags & RTE_TCP_ACK_FLAG)
4374                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4375                 if (filter->filter_info.tcp_flags & RTE_TCP_PSH_FLAG)
4376                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4377                 if (filter->filter_info.tcp_flags & RTE_TCP_RST_FLAG)
4378                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4379                 if (filter->filter_info.tcp_flags & RTE_TCP_SYN_FLAG)
4380                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4381                 if (filter->filter_info.tcp_flags & RTE_TCP_FIN_FLAG)
4382                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4383         } else {
4384                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4385         }
4386         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4387         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4388 }
4389
4390 /*
4391  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4392  *
4393  * @param
4394  * dev: Pointer to struct rte_eth_dev.
4395  * ntuple_filter: ponter to the filter that will be added.
4396  *
4397  * @return
4398  *    - On success, zero.
4399  *    - On failure, a negative value.
4400  */
4401 static int
4402 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4403                         struct rte_eth_ntuple_filter *ntuple_filter)
4404 {
4405         struct e1000_filter_info *filter_info =
4406                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4407         struct e1000_5tuple_filter *filter;
4408         uint8_t i;
4409         int ret;
4410
4411         filter = rte_zmalloc("e1000_5tuple_filter",
4412                         sizeof(struct e1000_5tuple_filter), 0);
4413         if (filter == NULL)
4414                 return -ENOMEM;
4415
4416         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4417                                             &filter->filter_info);
4418         if (ret < 0) {
4419                 rte_free(filter);
4420                 return ret;
4421         }
4422
4423         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4424                                          &filter->filter_info) != NULL) {
4425                 PMD_DRV_LOG(ERR, "filter exists.");
4426                 rte_free(filter);
4427                 return -EEXIST;
4428         }
4429         filter->queue = ntuple_filter->queue;
4430
4431         /*
4432          * look for an unused 5tuple filter index,
4433          * and insert the filter to list.
4434          */
4435         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4436                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4437                         filter_info->fivetuple_mask |= 1 << i;
4438                         filter->index = i;
4439                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4440                                           filter,
4441                                           entries);
4442                         break;
4443                 }
4444         }
4445         if (i >= E1000_MAX_FTQF_FILTERS) {
4446                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4447                 rte_free(filter);
4448                 return -ENOSYS;
4449         }
4450
4451         igb_inject_5tuple_filter_82576(dev, filter);
4452         return 0;
4453 }
4454
4455 int
4456 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4457                                 struct e1000_5tuple_filter *filter)
4458 {
4459         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460         struct e1000_filter_info *filter_info =
4461                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4462
4463         filter_info->fivetuple_mask &= ~(1 << filter->index);
4464         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4465         rte_free(filter);
4466
4467         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4468                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4469         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4470         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4471         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4472         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4473         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4474         return 0;
4475 }
4476
4477 /*
4478  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4479  *
4480  * @param
4481  * dev: Pointer to struct rte_eth_dev.
4482  * ntuple_filter: ponter to the filter that will be removed.
4483  *
4484  * @return
4485  *    - On success, zero.
4486  *    - On failure, a negative value.
4487  */
4488 static int
4489 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4490                                 struct rte_eth_ntuple_filter *ntuple_filter)
4491 {
4492         struct e1000_filter_info *filter_info =
4493                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4494         struct e1000_5tuple_filter_info filter_5tuple;
4495         struct e1000_5tuple_filter *filter;
4496         int ret;
4497
4498         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4499         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4500                                             &filter_5tuple);
4501         if (ret < 0)
4502                 return ret;
4503
4504         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4505                                          &filter_5tuple);
4506         if (filter == NULL) {
4507                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4508                 return -ENOENT;
4509         }
4510
4511         igb_delete_5tuple_filter_82576(dev, filter);
4512
4513         return 0;
4514 }
4515
4516 static int
4517 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4518 {
4519         uint32_t rctl;
4520         struct e1000_hw *hw;
4521         struct rte_eth_dev_info dev_info;
4522         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4523         int ret;
4524
4525         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526
4527 #ifdef RTE_LIBRTE_82571_SUPPORT
4528         /* XXX: not bigger than max_rx_pktlen */
4529         if (hw->mac.type == e1000_82571)
4530                 return -ENOTSUP;
4531 #endif
4532         ret = eth_igb_infos_get(dev, &dev_info);
4533         if (ret != 0)
4534                 return ret;
4535
4536         /* check that mtu is within the allowed range */
4537         if (mtu < RTE_ETHER_MIN_MTU ||
4538                         frame_size > dev_info.max_rx_pktlen)
4539                 return -EINVAL;
4540
4541         /* refuse mtu that requires the support of scattered packets when this
4542          * feature has not been enabled before. */
4543         if (!dev->data->scattered_rx &&
4544             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4545                 return -EINVAL;
4546
4547         rctl = E1000_READ_REG(hw, E1000_RCTL);
4548
4549         /* switch to jumbo mode if needed */
4550         if (frame_size > RTE_ETHER_MAX_LEN) {
4551                 dev->data->dev_conf.rxmode.offloads |=
4552                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4553                 rctl |= E1000_RCTL_LPE;
4554         } else {
4555                 dev->data->dev_conf.rxmode.offloads &=
4556                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4557                 rctl &= ~E1000_RCTL_LPE;
4558         }
4559         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4560
4561         /* update max frame size */
4562         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4563
4564         E1000_WRITE_REG(hw, E1000_RLPML,
4565                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4566
4567         return 0;
4568 }
4569
4570 /*
4571  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4572  *
4573  * @param
4574  * dev: Pointer to struct rte_eth_dev.
4575  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4576  * add: if true, add filter, if false, remove filter
4577  *
4578  * @return
4579  *    - On success, zero.
4580  *    - On failure, a negative value.
4581  */
4582 int
4583 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4584                         struct rte_eth_ntuple_filter *ntuple_filter,
4585                         bool add)
4586 {
4587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588         int ret;
4589
4590         switch (ntuple_filter->flags) {
4591         case RTE_5TUPLE_FLAGS:
4592         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4593                 if (hw->mac.type != e1000_82576)
4594                         return -ENOTSUP;
4595                 if (add)
4596                         ret = igb_add_5tuple_filter_82576(dev,
4597                                                           ntuple_filter);
4598                 else
4599                         ret = igb_remove_5tuple_filter_82576(dev,
4600                                                              ntuple_filter);
4601                 break;
4602         case RTE_2TUPLE_FLAGS:
4603         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4604                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4605                         hw->mac.type != e1000_i210 &&
4606                         hw->mac.type != e1000_i211)
4607                         return -ENOTSUP;
4608                 if (add)
4609                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4610                 else
4611                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4612                 break;
4613         default:
4614                 ret = -EINVAL;
4615                 break;
4616         }
4617
4618         return ret;
4619 }
4620
4621 /*
4622  * igb_get_ntuple_filter - get a ntuple filter
4623  *
4624  * @param
4625  * dev: Pointer to struct rte_eth_dev.
4626  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4627  *
4628  * @return
4629  *    - On success, zero.
4630  *    - On failure, a negative value.
4631  */
4632 static int
4633 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4634                         struct rte_eth_ntuple_filter *ntuple_filter)
4635 {
4636         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         struct e1000_filter_info *filter_info =
4638                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4639         struct e1000_5tuple_filter_info filter_5tuple;
4640         struct e1000_2tuple_filter_info filter_2tuple;
4641         struct e1000_5tuple_filter *p_5tuple_filter;
4642         struct e1000_2tuple_filter *p_2tuple_filter;
4643         int ret;
4644
4645         switch (ntuple_filter->flags) {
4646         case RTE_5TUPLE_FLAGS:
4647         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4648                 if (hw->mac.type != e1000_82576)
4649                         return -ENOTSUP;
4650                 memset(&filter_5tuple,
4651                         0,
4652                         sizeof(struct e1000_5tuple_filter_info));
4653                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4654                                                     &filter_5tuple);
4655                 if (ret < 0)
4656                         return ret;
4657                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4658                                         &filter_info->fivetuple_list,
4659                                         &filter_5tuple);
4660                 if (p_5tuple_filter == NULL) {
4661                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4662                         return -ENOENT;
4663                 }
4664                 ntuple_filter->queue = p_5tuple_filter->queue;
4665                 break;
4666         case RTE_2TUPLE_FLAGS:
4667         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4668                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4669                         return -ENOTSUP;
4670                 memset(&filter_2tuple,
4671                         0,
4672                         sizeof(struct e1000_2tuple_filter_info));
4673                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4674                 if (ret < 0)
4675                         return ret;
4676                 p_2tuple_filter = igb_2tuple_filter_lookup(
4677                                         &filter_info->twotuple_list,
4678                                         &filter_2tuple);
4679                 if (p_2tuple_filter == NULL) {
4680                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4681                         return -ENOENT;
4682                 }
4683                 ntuple_filter->queue = p_2tuple_filter->queue;
4684                 break;
4685         default:
4686                 ret = -EINVAL;
4687                 break;
4688         }
4689
4690         return 0;
4691 }
4692
4693 /*
4694  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4695  * @dev: pointer to rte_eth_dev structure
4696  * @filter_op:operation will be taken.
4697  * @arg: a pointer to specific structure corresponding to the filter_op
4698  */
4699 static int
4700 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4701                                 enum rte_filter_op filter_op,
4702                                 void *arg)
4703 {
4704         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705         int ret;
4706
4707         MAC_TYPE_FILTER_SUP(hw->mac.type);
4708
4709         if (filter_op == RTE_ETH_FILTER_NOP)
4710                 return 0;
4711
4712         if (arg == NULL) {
4713                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4714                             filter_op);
4715                 return -EINVAL;
4716         }
4717
4718         switch (filter_op) {
4719         case RTE_ETH_FILTER_ADD:
4720                 ret = igb_add_del_ntuple_filter(dev,
4721                         (struct rte_eth_ntuple_filter *)arg,
4722                         TRUE);
4723                 break;
4724         case RTE_ETH_FILTER_DELETE:
4725                 ret = igb_add_del_ntuple_filter(dev,
4726                         (struct rte_eth_ntuple_filter *)arg,
4727                         FALSE);
4728                 break;
4729         case RTE_ETH_FILTER_GET:
4730                 ret = igb_get_ntuple_filter(dev,
4731                         (struct rte_eth_ntuple_filter *)arg);
4732                 break;
4733         default:
4734                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4735                 ret = -EINVAL;
4736                 break;
4737         }
4738         return ret;
4739 }
4740
4741 static inline int
4742 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4743                         uint16_t ethertype)
4744 {
4745         int i;
4746
4747         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4748                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4749                     (filter_info->ethertype_mask & (1 << i)))
4750                         return i;
4751         }
4752         return -1;
4753 }
4754
4755 static inline int
4756 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4757                         uint16_t ethertype, uint32_t etqf)
4758 {
4759         int i;
4760
4761         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4762                 if (!(filter_info->ethertype_mask & (1 << i))) {
4763                         filter_info->ethertype_mask |= 1 << i;
4764                         filter_info->ethertype_filters[i].ethertype = ethertype;
4765                         filter_info->ethertype_filters[i].etqf = etqf;
4766                         return i;
4767                 }
4768         }
4769         return -1;
4770 }
4771
4772 int
4773 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4774                         uint8_t idx)
4775 {
4776         if (idx >= E1000_MAX_ETQF_FILTERS)
4777                 return -1;
4778         filter_info->ethertype_mask &= ~(1 << idx);
4779         filter_info->ethertype_filters[idx].ethertype = 0;
4780         filter_info->ethertype_filters[idx].etqf = 0;
4781         return idx;
4782 }
4783
4784
4785 int
4786 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4787                         struct rte_eth_ethertype_filter *filter,
4788                         bool add)
4789 {
4790         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         struct e1000_filter_info *filter_info =
4792                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4793         uint32_t etqf = 0;
4794         int ret;
4795
4796         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4797                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4798                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4799                         " ethertype filter.", filter->ether_type);
4800                 return -EINVAL;
4801         }
4802
4803         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4804                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4805                 return -EINVAL;
4806         }
4807         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4808                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4809                 return -EINVAL;
4810         }
4811
4812         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4813         if (ret >= 0 && add) {
4814                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4815                             filter->ether_type);
4816                 return -EEXIST;
4817         }
4818         if (ret < 0 && !add) {
4819                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4820                             filter->ether_type);
4821                 return -ENOENT;
4822         }
4823
4824         if (add) {
4825                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4826                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4827                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4828                 ret = igb_ethertype_filter_insert(filter_info,
4829                                 filter->ether_type, etqf);
4830                 if (ret < 0) {
4831                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4832                         return -ENOSYS;
4833                 }
4834         } else {
4835                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4836                 if (ret < 0)
4837                         return -ENOSYS;
4838         }
4839         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4840         E1000_WRITE_FLUSH(hw);
4841
4842         return 0;
4843 }
4844
4845 static int
4846 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4847                         struct rte_eth_ethertype_filter *filter)
4848 {
4849         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         struct e1000_filter_info *filter_info =
4851                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4852         uint32_t etqf;
4853         int ret;
4854
4855         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4856         if (ret < 0) {
4857                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4858                             filter->ether_type);
4859                 return -ENOENT;
4860         }
4861
4862         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4863         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4864                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4865                 filter->flags = 0;
4866                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4867                                 E1000_ETQF_QUEUE_SHIFT;
4868                 return 0;
4869         }
4870
4871         return -ENOENT;
4872 }
4873
4874 /*
4875  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4876  * @dev: pointer to rte_eth_dev structure
4877  * @filter_op:operation will be taken.
4878  * @arg: a pointer to specific structure corresponding to the filter_op
4879  */
4880 static int
4881 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4882                                 enum rte_filter_op filter_op,
4883                                 void *arg)
4884 {
4885         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         int ret;
4887
4888         MAC_TYPE_FILTER_SUP(hw->mac.type);
4889
4890         if (filter_op == RTE_ETH_FILTER_NOP)
4891                 return 0;
4892
4893         if (arg == NULL) {
4894                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4895                             filter_op);
4896                 return -EINVAL;
4897         }
4898
4899         switch (filter_op) {
4900         case RTE_ETH_FILTER_ADD:
4901                 ret = igb_add_del_ethertype_filter(dev,
4902                         (struct rte_eth_ethertype_filter *)arg,
4903                         TRUE);
4904                 break;
4905         case RTE_ETH_FILTER_DELETE:
4906                 ret = igb_add_del_ethertype_filter(dev,
4907                         (struct rte_eth_ethertype_filter *)arg,
4908                         FALSE);
4909                 break;
4910         case RTE_ETH_FILTER_GET:
4911                 ret = igb_get_ethertype_filter(dev,
4912                         (struct rte_eth_ethertype_filter *)arg);
4913                 break;
4914         default:
4915                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4916                 ret = -EINVAL;
4917                 break;
4918         }
4919         return ret;
4920 }
4921
4922 static int
4923 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4924                      enum rte_filter_type filter_type,
4925                      enum rte_filter_op filter_op,
4926                      void *arg)
4927 {
4928         int ret = 0;
4929
4930         switch (filter_type) {
4931         case RTE_ETH_FILTER_NTUPLE:
4932                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4933                 break;
4934         case RTE_ETH_FILTER_ETHERTYPE:
4935                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4936                 break;
4937         case RTE_ETH_FILTER_SYN:
4938                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4939                 break;
4940         case RTE_ETH_FILTER_FLEXIBLE:
4941                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4942                 break;
4943         case RTE_ETH_FILTER_GENERIC:
4944                 if (filter_op != RTE_ETH_FILTER_GET)
4945                         return -EINVAL;
4946                 *(const void **)arg = &igb_flow_ops;
4947                 break;
4948         default:
4949                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4950                                                         filter_type);
4951                 break;
4952         }
4953
4954         return ret;
4955 }
4956
4957 static int
4958 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4959                          struct rte_ether_addr *mc_addr_set,
4960                          uint32_t nb_mc_addr)
4961 {
4962         struct e1000_hw *hw;
4963
4964         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4966         return 0;
4967 }
4968
4969 static uint64_t
4970 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4971 {
4972         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4973         uint64_t systime_cycles;
4974
4975         switch (hw->mac.type) {
4976         case e1000_i210:
4977         case e1000_i211:
4978                 /*
4979                  * Need to read System Time Residue Register to be able
4980                  * to read the other two registers.
4981                  */
4982                 E1000_READ_REG(hw, E1000_SYSTIMR);
4983                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4984                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4985                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4986                                 * NSEC_PER_SEC;
4987                 break;
4988         case e1000_82580:
4989         case e1000_i350:
4990         case e1000_i354:
4991                 /*
4992                  * Need to read System Time Residue Register to be able
4993                  * to read the other two registers.
4994                  */
4995                 E1000_READ_REG(hw, E1000_SYSTIMR);
4996                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4997                 /* Only the 8 LSB are valid. */
4998                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4999                                 & 0xff) << 32;
5000                 break;
5001         default:
5002                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
5003                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
5004                                 << 32;
5005                 break;
5006         }
5007
5008         return systime_cycles;
5009 }
5010
5011 static uint64_t
5012 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5013 {
5014         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015         uint64_t rx_tstamp_cycles;
5016
5017         switch (hw->mac.type) {
5018         case e1000_i210:
5019         case e1000_i211:
5020                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5021                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5022                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5023                                 * NSEC_PER_SEC;
5024                 break;
5025         case e1000_82580:
5026         case e1000_i350:
5027         case e1000_i354:
5028                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5029                 /* Only the 8 LSB are valid. */
5030                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
5031                                 & 0xff) << 32;
5032                 break;
5033         default:
5034                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
5035                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
5036                                 << 32;
5037                 break;
5038         }
5039
5040         return rx_tstamp_cycles;
5041 }
5042
5043 static uint64_t
5044 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5045 {
5046         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047         uint64_t tx_tstamp_cycles;
5048
5049         switch (hw->mac.type) {
5050         case e1000_i210:
5051         case e1000_i211:
5052                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5053                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5054                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5055                                 * NSEC_PER_SEC;
5056                 break;
5057         case e1000_82580:
5058         case e1000_i350:
5059         case e1000_i354:
5060                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5061                 /* Only the 8 LSB are valid. */
5062                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5063                                 & 0xff) << 32;
5064                 break;
5065         default:
5066                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5067                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5068                                 << 32;
5069                 break;
5070         }
5071
5072         return tx_tstamp_cycles;
5073 }
5074
5075 static void
5076 igb_start_timecounters(struct rte_eth_dev *dev)
5077 {
5078         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5079         struct e1000_adapter *adapter = dev->data->dev_private;
5080         uint32_t incval = 1;
5081         uint32_t shift = 0;
5082         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5083
5084         switch (hw->mac.type) {
5085         case e1000_82580:
5086         case e1000_i350:
5087         case e1000_i354:
5088                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5089                 mask = (1ULL << 40) - 1;
5090                 /* fall-through */
5091         case e1000_i210:
5092         case e1000_i211:
5093                 /*
5094                  * Start incrementing the register
5095                  * used to timestamp PTP packets.
5096                  */
5097                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5098                 break;
5099         case e1000_82576:
5100                 incval = E1000_INCVALUE_82576;
5101                 shift = IGB_82576_TSYNC_SHIFT;
5102                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5103                                 E1000_INCPERIOD_82576 | incval);
5104                 break;
5105         default:
5106                 /* Not supported */
5107                 return;
5108         }
5109
5110         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5111         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5112         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5113
5114         adapter->systime_tc.cc_mask = mask;
5115         adapter->systime_tc.cc_shift = shift;
5116         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5117
5118         adapter->rx_tstamp_tc.cc_mask = mask;
5119         adapter->rx_tstamp_tc.cc_shift = shift;
5120         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5121
5122         adapter->tx_tstamp_tc.cc_mask = mask;
5123         adapter->tx_tstamp_tc.cc_shift = shift;
5124         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5125 }
5126
5127 static int
5128 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5129 {
5130         struct e1000_adapter *adapter = dev->data->dev_private;
5131
5132         adapter->systime_tc.nsec += delta;
5133         adapter->rx_tstamp_tc.nsec += delta;
5134         adapter->tx_tstamp_tc.nsec += delta;
5135
5136         return 0;
5137 }
5138
5139 static int
5140 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5141 {
5142         uint64_t ns;
5143         struct e1000_adapter *adapter = dev->data->dev_private;
5144
5145         ns = rte_timespec_to_ns(ts);
5146
5147         /* Set the timecounters to a new value. */
5148         adapter->systime_tc.nsec = ns;
5149         adapter->rx_tstamp_tc.nsec = ns;
5150         adapter->tx_tstamp_tc.nsec = ns;
5151
5152         return 0;
5153 }
5154
5155 static int
5156 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5157 {
5158         uint64_t ns, systime_cycles;
5159         struct e1000_adapter *adapter = dev->data->dev_private;
5160
5161         systime_cycles = igb_read_systime_cyclecounter(dev);
5162         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5163         *ts = rte_ns_to_timespec(ns);
5164
5165         return 0;
5166 }
5167
5168 static int
5169 igb_timesync_enable(struct rte_eth_dev *dev)
5170 {
5171         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172         uint32_t tsync_ctl;
5173         uint32_t tsauxc;
5174
5175         /* Stop the timesync system time. */
5176         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5177         /* Reset the timesync system time value. */
5178         switch (hw->mac.type) {
5179         case e1000_82580:
5180         case e1000_i350:
5181         case e1000_i354:
5182         case e1000_i210:
5183         case e1000_i211:
5184                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5185                 /* fall-through */
5186         case e1000_82576:
5187                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5188                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5189                 break;
5190         default:
5191                 /* Not supported. */
5192                 return -ENOTSUP;
5193         }
5194
5195         /* Enable system time for it isn't on by default. */
5196         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5197         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5198         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5199
5200         igb_start_timecounters(dev);
5201
5202         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5203         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5204                         (RTE_ETHER_TYPE_1588 |
5205                          E1000_ETQF_FILTER_ENABLE |
5206                          E1000_ETQF_1588));
5207
5208         /* Enable timestamping of received PTP packets. */
5209         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5210         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5211         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5212
5213         /* Enable Timestamping of transmitted PTP packets. */
5214         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5215         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5216         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5217
5218         return 0;
5219 }
5220
5221 static int
5222 igb_timesync_disable(struct rte_eth_dev *dev)
5223 {
5224         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225         uint32_t tsync_ctl;
5226
5227         /* Disable timestamping of transmitted PTP packets. */
5228         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5229         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5230         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5231
5232         /* Disable timestamping of received PTP packets. */
5233         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5234         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5235         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5236
5237         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5238         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5239
5240         /* Stop incrementating the System Time registers. */
5241         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5242
5243         return 0;
5244 }
5245
5246 static int
5247 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5248                                struct timespec *timestamp,
5249                                uint32_t flags __rte_unused)
5250 {
5251         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252         struct e1000_adapter *adapter = dev->data->dev_private;
5253         uint32_t tsync_rxctl;
5254         uint64_t rx_tstamp_cycles;
5255         uint64_t ns;
5256
5257         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5258         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5259                 return -EINVAL;
5260
5261         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5262         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5263         *timestamp = rte_ns_to_timespec(ns);
5264
5265         return  0;
5266 }
5267
5268 static int
5269 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5270                                struct timespec *timestamp)
5271 {
5272         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273         struct e1000_adapter *adapter = dev->data->dev_private;
5274         uint32_t tsync_txctl;
5275         uint64_t tx_tstamp_cycles;
5276         uint64_t ns;
5277
5278         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5279         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5280                 return -EINVAL;
5281
5282         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5283         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5284         *timestamp = rte_ns_to_timespec(ns);
5285
5286         return  0;
5287 }
5288
5289 static int
5290 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5291 {
5292         int count = 0;
5293         int g_ind = 0;
5294         const struct reg_info *reg_group;
5295
5296         while ((reg_group = igb_regs[g_ind++]))
5297                 count += igb_reg_group_count(reg_group);
5298
5299         return count;
5300 }
5301
5302 static int
5303 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5304 {
5305         int count = 0;
5306         int g_ind = 0;
5307         const struct reg_info *reg_group;
5308
5309         while ((reg_group = igbvf_regs[g_ind++]))
5310                 count += igb_reg_group_count(reg_group);
5311
5312         return count;
5313 }
5314
5315 static int
5316 eth_igb_get_regs(struct rte_eth_dev *dev,
5317         struct rte_dev_reg_info *regs)
5318 {
5319         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5320         uint32_t *data = regs->data;
5321         int g_ind = 0;
5322         int count = 0;
5323         const struct reg_info *reg_group;
5324
5325         if (data == NULL) {
5326                 regs->length = eth_igb_get_reg_length(dev);
5327                 regs->width = sizeof(uint32_t);
5328                 return 0;
5329         }
5330
5331         /* Support only full register dump */
5332         if ((regs->length == 0) ||
5333             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5334                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5335                         hw->device_id;
5336                 while ((reg_group = igb_regs[g_ind++]))
5337                         count += igb_read_regs_group(dev, &data[count],
5338                                                         reg_group);
5339                 return 0;
5340         }
5341
5342         return -ENOTSUP;
5343 }
5344
5345 static int
5346 igbvf_get_regs(struct rte_eth_dev *dev,
5347         struct rte_dev_reg_info *regs)
5348 {
5349         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5350         uint32_t *data = regs->data;
5351         int g_ind = 0;
5352         int count = 0;
5353         const struct reg_info *reg_group;
5354
5355         if (data == NULL) {
5356                 regs->length = igbvf_get_reg_length(dev);
5357                 regs->width = sizeof(uint32_t);
5358                 return 0;
5359         }
5360
5361         /* Support only full register dump */
5362         if ((regs->length == 0) ||
5363             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5364                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5365                         hw->device_id;
5366                 while ((reg_group = igbvf_regs[g_ind++]))
5367                         count += igb_read_regs_group(dev, &data[count],
5368                                                         reg_group);
5369                 return 0;
5370         }
5371
5372         return -ENOTSUP;
5373 }
5374
5375 static int
5376 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5377 {
5378         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5379
5380         /* Return unit is byte count */
5381         return hw->nvm.word_size * 2;
5382 }
5383
5384 static int
5385 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5386         struct rte_dev_eeprom_info *in_eeprom)
5387 {
5388         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5389         struct e1000_nvm_info *nvm = &hw->nvm;
5390         uint16_t *data = in_eeprom->data;
5391         int first, length;
5392
5393         first = in_eeprom->offset >> 1;
5394         length = in_eeprom->length >> 1;
5395         if ((first >= hw->nvm.word_size) ||
5396             ((first + length) >= hw->nvm.word_size))
5397                 return -EINVAL;
5398
5399         in_eeprom->magic = hw->vendor_id |
5400                 ((uint32_t)hw->device_id << 16);
5401
5402         if ((nvm->ops.read) == NULL)
5403                 return -ENOTSUP;
5404
5405         return nvm->ops.read(hw, first, length, data);
5406 }
5407
5408 static int
5409 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5410         struct rte_dev_eeprom_info *in_eeprom)
5411 {
5412         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413         struct e1000_nvm_info *nvm = &hw->nvm;
5414         uint16_t *data = in_eeprom->data;
5415         int first, length;
5416
5417         first = in_eeprom->offset >> 1;
5418         length = in_eeprom->length >> 1;
5419         if ((first >= hw->nvm.word_size) ||
5420             ((first + length) >= hw->nvm.word_size))
5421                 return -EINVAL;
5422
5423         in_eeprom->magic = (uint32_t)hw->vendor_id |
5424                 ((uint32_t)hw->device_id << 16);
5425
5426         if ((nvm->ops.write) == NULL)
5427                 return -ENOTSUP;
5428         return nvm->ops.write(hw,  first, length, data);
5429 }
5430
5431 static int
5432 eth_igb_get_module_info(struct rte_eth_dev *dev,
5433                         struct rte_eth_dev_module_info *modinfo)
5434 {
5435         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5436
5437         uint32_t status = 0;
5438         uint16_t sff8472_rev, addr_mode;
5439         bool page_swap = false;
5440
5441         if (hw->phy.media_type == e1000_media_type_copper ||
5442             hw->phy.media_type == e1000_media_type_unknown)
5443                 return -EOPNOTSUPP;
5444
5445         /* Check whether we support SFF-8472 or not */
5446         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5447         if (status)
5448                 return -EIO;
5449
5450         /* addressing mode is not supported */
5451         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5452         if (status)
5453                 return -EIO;
5454
5455         /* addressing mode is not supported */
5456         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5457                 PMD_DRV_LOG(ERR,
5458                             "Address change required to access page 0xA2, "
5459                             "but not supported. Please report the module "
5460                             "type to the driver maintainers.\n");
5461                 page_swap = true;
5462         }
5463
5464         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5465                 /* We have an SFP, but it does not support SFF-8472 */
5466                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5467                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5468         } else {
5469                 /* We have an SFP which supports a revision of SFF-8472 */
5470                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5471                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5472         }
5473
5474         return 0;
5475 }
5476
5477 static int
5478 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5479                           struct rte_dev_eeprom_info *info)
5480 {
5481         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5482
5483         uint32_t status = 0;
5484         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5485         u16 first_word, last_word;
5486         int i = 0;
5487
5488         if (info->length == 0)
5489                 return -EINVAL;
5490
5491         first_word = info->offset >> 1;
5492         last_word = (info->offset + info->length - 1) >> 1;
5493
5494         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5495         for (i = 0; i < last_word - first_word + 1; i++) {
5496                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5497                                                 &dataword[i]);
5498                 if (status) {
5499                         /* Error occurred while reading module */
5500                         return -EIO;
5501                 }
5502
5503                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5504         }
5505
5506         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5507
5508         return 0;
5509 }
5510
5511 static int
5512 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5513 {
5514         struct e1000_hw *hw =
5515                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5517         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5518         uint32_t vec = E1000_MISC_VEC_ID;
5519
5520         if (rte_intr_allow_others(intr_handle))
5521                 vec = E1000_RX_VEC_START;
5522
5523         uint32_t mask = 1 << (queue_id + vec);
5524
5525         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5526         E1000_WRITE_FLUSH(hw);
5527
5528         return 0;
5529 }
5530
5531 static int
5532 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5533 {
5534         struct e1000_hw *hw =
5535                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5536         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5537         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5538         uint32_t vec = E1000_MISC_VEC_ID;
5539
5540         if (rte_intr_allow_others(intr_handle))
5541                 vec = E1000_RX_VEC_START;
5542
5543         uint32_t mask = 1 << (queue_id + vec);
5544         uint32_t regval;
5545
5546         regval = E1000_READ_REG(hw, E1000_EIMS);
5547         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5548         E1000_WRITE_FLUSH(hw);
5549
5550         rte_intr_ack(intr_handle);
5551
5552         return 0;
5553 }
5554
5555 static void
5556 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5557                    uint8_t index, uint8_t offset)
5558 {
5559         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5560
5561         /* clear bits */
5562         val &= ~((uint32_t)0xFF << offset);
5563
5564         /* write vector and valid bit */
5565         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5566
5567         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5568 }
5569
5570 static void
5571 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5572                            uint8_t queue, uint8_t msix_vector)
5573 {
5574         uint32_t tmp = 0;
5575
5576         if (hw->mac.type == e1000_82575) {
5577                 if (direction == 0)
5578                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5579                 else if (direction == 1)
5580                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5581                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5582         } else if (hw->mac.type == e1000_82576) {
5583                 if ((direction == 0) || (direction == 1))
5584                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5585                                            ((queue & 0x8) << 1) +
5586                                            8 * direction);
5587         } else if ((hw->mac.type == e1000_82580) ||
5588                         (hw->mac.type == e1000_i350) ||
5589                         (hw->mac.type == e1000_i354) ||
5590                         (hw->mac.type == e1000_i210) ||
5591                         (hw->mac.type == e1000_i211)) {
5592                 if ((direction == 0) || (direction == 1))
5593                         eth_igb_write_ivar(hw, msix_vector,
5594                                            queue >> 1,
5595                                            ((queue & 0x1) << 4) +
5596                                            8 * direction);
5597         }
5598 }
5599
5600 /* Sets up the hardware to generate MSI-X interrupts properly
5601  * @hw
5602  *  board private structure
5603  */
5604 static void
5605 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5606 {
5607         int queue_id;
5608         uint32_t tmpval, regval, intr_mask;
5609         struct e1000_hw *hw =
5610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611         uint32_t vec = E1000_MISC_VEC_ID;
5612         uint32_t base = E1000_MISC_VEC_ID;
5613         uint32_t misc_shift = 0;
5614         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5615         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5616
5617         /* won't configure msix register if no mapping is done
5618          * between intr vector and event fd
5619          */
5620         if (!rte_intr_dp_is_en(intr_handle))
5621                 return;
5622
5623         if (rte_intr_allow_others(intr_handle)) {
5624                 vec = base = E1000_RX_VEC_START;
5625                 misc_shift = 1;
5626         }
5627
5628         /* set interrupt vector for other causes */
5629         if (hw->mac.type == e1000_82575) {
5630                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5631                 /* enable MSI-X PBA support */
5632                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5633
5634                 /* Auto-Mask interrupts upon ICR read */
5635                 tmpval |= E1000_CTRL_EXT_EIAME;
5636                 tmpval |= E1000_CTRL_EXT_IRCA;
5637
5638                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5639
5640                 /* enable msix_other interrupt */
5641                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5642                 regval = E1000_READ_REG(hw, E1000_EIAC);
5643                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5644                 regval = E1000_READ_REG(hw, E1000_EIAM);
5645                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5646         } else if ((hw->mac.type == e1000_82576) ||
5647                         (hw->mac.type == e1000_82580) ||
5648                         (hw->mac.type == e1000_i350) ||
5649                         (hw->mac.type == e1000_i354) ||
5650                         (hw->mac.type == e1000_i210) ||
5651                         (hw->mac.type == e1000_i211)) {
5652                 /* turn on MSI-X capability first */
5653                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5654                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5655                                         E1000_GPIE_NSICR);
5656                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5657                         misc_shift;
5658
5659                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5660                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5661
5662                 regval = E1000_READ_REG(hw, E1000_EIAC);
5663                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5664
5665                 /* enable msix_other interrupt */
5666                 regval = E1000_READ_REG(hw, E1000_EIMS);
5667                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5668                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5669                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5670         }
5671
5672         /* use EIAM to auto-mask when MSI-X interrupt
5673          * is asserted, this saves a register write for every interrupt
5674          */
5675         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5676                 misc_shift;
5677
5678         if (dev->data->dev_conf.intr_conf.lsc != 0)
5679                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5680
5681         regval = E1000_READ_REG(hw, E1000_EIAM);
5682         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5683
5684         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5685                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5686                 intr_handle->intr_vec[queue_id] = vec;
5687                 if (vec < base + intr_handle->nb_efd - 1)
5688                         vec++;
5689         }
5690
5691         E1000_WRITE_FLUSH(hw);
5692 }
5693
5694 /* restore n-tuple filter */
5695 static inline void
5696 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5697 {
5698         struct e1000_filter_info *filter_info =
5699                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5700         struct e1000_5tuple_filter *p_5tuple;
5701         struct e1000_2tuple_filter *p_2tuple;
5702
5703         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5704                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5705         }
5706
5707         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5708                 igb_inject_2uple_filter(dev, p_2tuple);
5709         }
5710 }
5711
5712 /* restore SYN filter */
5713 static inline void
5714 igb_syn_filter_restore(struct rte_eth_dev *dev)
5715 {
5716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5717         struct e1000_filter_info *filter_info =
5718                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5719         uint32_t synqf;
5720
5721         synqf = filter_info->syn_info;
5722
5723         if (synqf & E1000_SYN_FILTER_ENABLE) {
5724                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5725                 E1000_WRITE_FLUSH(hw);
5726         }
5727 }
5728
5729 /* restore ethernet type filter */
5730 static inline void
5731 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5732 {
5733         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5734         struct e1000_filter_info *filter_info =
5735                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5736         int i;
5737
5738         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5739                 if (filter_info->ethertype_mask & (1 << i)) {
5740                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5741                                 filter_info->ethertype_filters[i].etqf);
5742                         E1000_WRITE_FLUSH(hw);
5743                 }
5744         }
5745 }
5746
5747 /* restore flex byte filter */
5748 static inline void
5749 igb_flex_filter_restore(struct rte_eth_dev *dev)
5750 {
5751         struct e1000_filter_info *filter_info =
5752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5753         struct e1000_flex_filter *flex_filter;
5754
5755         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5756                 igb_inject_flex_filter(dev, flex_filter);
5757         }
5758 }
5759
5760 /* restore rss filter */
5761 static inline void
5762 igb_rss_filter_restore(struct rte_eth_dev *dev)
5763 {
5764         struct e1000_filter_info *filter_info =
5765                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5766
5767         if (filter_info->rss_info.conf.queue_num)
5768                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5769 }
5770
5771 /* restore all types filter */
5772 static int
5773 igb_filter_restore(struct rte_eth_dev *dev)
5774 {
5775         igb_ntuple_filter_restore(dev);
5776         igb_ethertype_filter_restore(dev);
5777         igb_syn_filter_restore(dev);
5778         igb_flex_filter_restore(dev);
5779         igb_rss_filter_restore(dev);
5780
5781         return 0;
5782 }
5783
5784 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5785 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5786 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5787 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5788 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5789 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5790
5791 /* see e1000_logs.c */
5792 RTE_INIT(e1000_init_log)
5793 {
5794         e1000_igb_init_log();
5795 }