drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* initialize the vfta */
 847         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 848
 849         /* Now initialize the hardware */
 850         if (igb_hardware_init(hw) != 0) {
 851                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 852                 rte_free(eth_dev->data->mac_addrs);
 853                 eth_dev->data->mac_addrs = NULL;
 854                 error = -ENODEV;
 855                 goto err_late;
 856         }
 857         hw->mac.get_link_status = 1;
 858         adapter->stopped = 0;
 859
 860         /* Indicate SOL/IDER usage */
 861         if (e1000_check_reset_block(hw) < 0) {
 862                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 863                                         "SOL/IDER session");
 864         }
 865
 866         /* initialize PF if max_vfs not zero */
 867         igb_pf_host_init(eth_dev);
 868
 869         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 872         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 873         E1000_WRITE_FLUSH(hw);
 874
 875         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 876                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 877                      pci_dev->id.device_id);
 878
 879         rte_intr_callback_register(&pci_dev->intr_handle,
 880                                    eth_igb_interrupt_handler,
 881                                    (void *)eth_dev);
 882
 883         /* enable uio/vfio intr/eventfd mapping */
 884         rte_intr_enable(&pci_dev->intr_handle);
 885
 886         /* enable support intr */
 887         igb_intr_enable(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         struct rte_pci_device *pci_dev;
 916         struct rte_intr_handle *intr_handle;
 917         struct e1000_hw *hw;
 918         struct e1000_adapter *adapter =
 919                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 920         struct e1000_filter_info *filter_info =
 921                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 922
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 926                 return -EPERM;
 927
 928         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 930         intr_handle = &pci_dev->intr_handle;
 931
 932         if (adapter->stopped == 0)
 933                 eth_igb_close(eth_dev);
 934
 935         eth_dev->dev_ops = NULL;
 936         eth_dev->rx_pkt_burst = NULL;
 937         eth_dev->tx_pkt_burst = NULL;
 938
 939         /* Reset any pending lock */
 940         igb_reset_swfw_lock(hw);
 941
 942         /* uninitialize PF if max_vfs not zero */
 943         igb_pf_host_uninit(eth_dev);
 944
 945         /* disable uio intr before callback unregister */
 946         rte_intr_disable(intr_handle);
 947         rte_intr_callback_unregister(intr_handle,
 948                                      eth_igb_interrupt_handler, eth_dev);
 949
 950         /* clear the SYN filter info */
 951         filter_info->syn_info = 0;
 952
 953         /* clear the ethertype filters info */
 954         filter_info->ethertype_mask = 0;
 955         memset(filter_info->ethertype_filters, 0,
 956                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 957
 958         /* clear the rss filter info */
 959         memset(&filter_info->rss_info, 0,
 960                 sizeof(struct igb_rte_flow_rss_conf));
 961
 962         /* remove all ntuple filters of the device */
 963         igb_ntuple_filter_uninit(eth_dev);
 964
 965         /* remove all flex filters of the device */
 966         igb_flex_filter_uninit(eth_dev);
 967
 968         /* clear all the filters list */
 969         igb_filterlist_flush(eth_dev);
 970
 971         return 0;
 972 }
 973
 974 /*
 975  * Virtual Function device init
 976  */
 977 static int
 978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 979 {
 980         struct rte_pci_device *pci_dev;
 981         struct rte_intr_handle *intr_handle;
 982         struct e1000_adapter *adapter =
 983                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 984         struct e1000_hw *hw =
 985                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 986         int diag;
 987         struct rte_ether_addr *perm_addr =
 988                 (struct rte_ether_addr *)hw->mac.perm_addr;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 993         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 994         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 995         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 996
 997         /* for secondary processes, we don't initialise any further as primary
 998          * has already done this work. Only check we don't need a different
 999          * RX function */
1000         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001                 if (eth_dev->data->scattered_rx)
1002                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1003                 return 0;
1004         }
1005
1006         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007         rte_eth_copy_pci_info(eth_dev, pci_dev);
1008
1009         hw->device_id = pci_dev->id.device_id;
1010         hw->vendor_id = pci_dev->id.vendor_id;
1011         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012         adapter->stopped = 0;
1013
1014         /* Initialize the shared code (base driver) */
1015         diag = e1000_setup_init_funcs(hw, TRUE);
1016         if (diag != 0) {
1017                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1018                         diag);
1019                 return -EIO;
1020         }
1021
1022         /* init_mailbox_params */
1023         hw->mbx.ops.init_params(hw);
1024
1025         /* Disable the interrupts for VF */
1026         igbvf_intr_disable(hw);
1027
1028         diag = hw->mac.ops.reset_hw(hw);
1029
1030         /* Allocate memory for storing MAC addresses */
1031         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", RTE_ETHER_ADDR_LEN *
1032                 hw->mac.rar_entry_count, 0);
1033         if (eth_dev->data->mac_addrs == NULL) {
1034                 PMD_INIT_LOG(ERR,
1035                         "Failed to allocate %d bytes needed to store MAC "
1036                         "addresses",
1037                         RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1038                 return -ENOMEM;
1039         }
1040
1041         /* Generate a random MAC address, if none was assigned by PF. */
1042         if (rte_is_zero_ether_addr(perm_addr)) {
1043                 rte_eth_random_addr(perm_addr->addr_bytes);
1044                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046                              "%02x:%02x:%02x:%02x:%02x:%02x",
1047                              perm_addr->addr_bytes[0],
1048                              perm_addr->addr_bytes[1],
1049                              perm_addr->addr_bytes[2],
1050                              perm_addr->addr_bytes[3],
1051                              perm_addr->addr_bytes[4],
1052                              perm_addr->addr_bytes[5]);
1053         }
1054
1055         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1056         if (diag) {
1057                 rte_free(eth_dev->data->mac_addrs);
1058                 eth_dev->data->mac_addrs = NULL;
1059                 return diag;
1060         }
1061         /* Copy the permanent MAC address */
1062         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063                         &eth_dev->data->mac_addrs[0]);
1064
1065         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1066                      "mac.type=%s",
1067                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1068                      pci_dev->id.device_id, "igb_mac_82576_vf");
1069
1070         intr_handle = &pci_dev->intr_handle;
1071         rte_intr_callback_register(intr_handle,
1072                                    eth_igbvf_interrupt_handler, eth_dev);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1079 {
1080         struct e1000_adapter *adapter =
1081                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1083
1084         PMD_INIT_FUNC_TRACE();
1085
1086         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1087                 return -EPERM;
1088
1089         if (adapter->stopped == 0)
1090                 igbvf_dev_close(eth_dev);
1091
1092         eth_dev->dev_ops = NULL;
1093         eth_dev->rx_pkt_burst = NULL;
1094         eth_dev->tx_pkt_burst = NULL;
1095
1096         /* disable uio intr before callback unregister */
1097         rte_intr_disable(&pci_dev->intr_handle);
1098         rte_intr_callback_unregister(&pci_dev->intr_handle,
1099                                      eth_igbvf_interrupt_handler,
1100                                      (void *)eth_dev);
1101
1102         return 0;
1103 }
1104
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106         struct rte_pci_device *pci_dev)
1107 {
1108         return rte_eth_dev_pci_generic_probe(pci_dev,
1109                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1110 }
1111
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1113 {
1114         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1115 }
1116
1117 static struct rte_pci_driver rte_igb_pmd = {
1118         .id_table = pci_id_igb_map,
1119         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1120                      RTE_PCI_DRV_IOVA_AS_VA,
1121         .probe = eth_igb_pci_probe,
1122         .remove = eth_igb_pci_remove,
1123 };
1124
1125
1126 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1127         struct rte_pci_device *pci_dev)
1128 {
1129         return rte_eth_dev_pci_generic_probe(pci_dev,
1130                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1131 }
1132
1133 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1134 {
1135         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1136 }
1137
1138 /*
1139  * virtual function driver struct
1140  */
1141 static struct rte_pci_driver rte_igbvf_pmd = {
1142         .id_table = pci_id_igbvf_map,
1143         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1144         .probe = eth_igbvf_pci_probe,
1145         .remove = eth_igbvf_pci_remove,
1146 };
1147
1148 static void
1149 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1150 {
1151         struct e1000_hw *hw =
1152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1154         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1155         rctl |= E1000_RCTL_VFE;
1156         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1157 }
1158
1159 static int
1160 igb_check_mq_mode(struct rte_eth_dev *dev)
1161 {
1162         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1163         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1164         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1165         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1166
1167         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1168             tx_mq_mode == ETH_MQ_TX_DCB ||
1169             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1170                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1171                 return -EINVAL;
1172         }
1173         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1174                 /* Check multi-queue mode.
1175                  * To no break software we accept ETH_MQ_RX_NONE as this might
1176                  * be used to turn off VLAN filter.
1177                  */
1178
1179                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1180                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1181                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1182                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1183                 } else {
1184                         /* Only support one queue on VFs.
1185                          * RSS together with SRIOV is not supported.
1186                          */
1187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1188                                         " wrong mq_mode rx %d.",
1189                                         rx_mq_mode);
1190                         return -EINVAL;
1191                 }
1192                 /* TX mode is not used here, so mode might be ignored.*/
1193                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1194                         /* SRIOV only works in VMDq enable mode */
1195                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1196                                         " TX mode %d is not supported. "
1197                                         " Driver will behave as %d mode.",
1198                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1199                 }
1200
1201                 /* check valid queue number */
1202                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1203                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1204                                         " only support one queue on VFs.");
1205                         return -EINVAL;
1206                 }
1207         } else {
1208                 /* To no break software that set invalid mode, only display
1209                  * warning if invalid mode is used.
1210                  */
1211                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1212                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1213                     rx_mq_mode != ETH_MQ_RX_RSS) {
1214                         /* RSS together with VMDq not supported*/
1215                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1216                                      rx_mq_mode);
1217                         return -EINVAL;
1218                 }
1219
1220                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1221                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1222                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1223                                         " Due to txmode is meaningless in this"
1224                                         " driver, just ignore.",
1225                                         tx_mq_mode);
1226                 }
1227         }
1228         return 0;
1229 }
1230
1231 static int
1232 eth_igb_configure(struct rte_eth_dev *dev)
1233 {
1234         struct e1000_interrupt *intr =
1235                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1236         int ret;
1237
1238         PMD_INIT_FUNC_TRACE();
1239
1240         /* multipe queue mode checking */
1241         ret  = igb_check_mq_mode(dev);
1242         if (ret != 0) {
1243                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1244                             ret);
1245                 return ret;
1246         }
1247
1248         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1249         PMD_INIT_FUNC_TRACE();
1250
1251         return 0;
1252 }
1253
1254 static void
1255 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1256                      bool enable)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         uint32_t tctl, rctl;
1261
1262         tctl = E1000_READ_REG(hw, E1000_TCTL);
1263         rctl = E1000_READ_REG(hw, E1000_RCTL);
1264
1265         if (enable) {
1266                 /* enable Tx/Rx */
1267                 tctl |= E1000_TCTL_EN;
1268                 rctl |= E1000_RCTL_EN;
1269         } else {
1270                 /* disable Tx/Rx */
1271                 tctl &= ~E1000_TCTL_EN;
1272                 rctl &= ~E1000_RCTL_EN;
1273         }
1274         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1275         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1276         E1000_WRITE_FLUSH(hw);
1277 }
1278
1279 static int
1280 eth_igb_start(struct rte_eth_dev *dev)
1281 {
1282         struct e1000_hw *hw =
1283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         struct e1000_adapter *adapter =
1285                 E1000_DEV_PRIVATE(dev->data->dev_private);
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         int ret, mask;
1289         uint32_t intr_vector = 0;
1290         uint32_t ctrl_ext;
1291         uint32_t *speeds;
1292         int num_speeds;
1293         bool autoneg;
1294
1295         PMD_INIT_FUNC_TRACE();
1296
1297         /* disable uio/vfio intr/eventfd mapping */
1298         rte_intr_disable(intr_handle);
1299
1300         /* Power up the phy. Needed to make the link go Up */
1301         eth_igb_dev_set_link_up(dev);
1302
1303         /*
1304          * Packet Buffer Allocation (PBA)
1305          * Writing PBA sets the receive portion of the buffer
1306          * the remainder is used for the transmit buffer.
1307          */
1308         if (hw->mac.type == e1000_82575) {
1309                 uint32_t pba;
1310
1311                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1312                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1313         }
1314
1315         /* Put the address into the Receive Address Array */
1316         e1000_rar_set(hw, hw->mac.addr, 0);
1317
1318         /* Initialize the hardware */
1319         if (igb_hardware_init(hw)) {
1320                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1321                 return -EIO;
1322         }
1323         adapter->stopped = 0;
1324
1325         E1000_WRITE_REG(hw, E1000_VET,
1326                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1327
1328         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1329         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1330         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1331         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1332         E1000_WRITE_FLUSH(hw);
1333
1334         /* configure PF module if SRIOV enabled */
1335         igb_pf_host_configure(dev);
1336
1337         /* check and configure queue intr-vector mapping */
1338         if ((rte_intr_cap_multiple(intr_handle) ||
1339              !RTE_ETH_DEV_SRIOV(dev).active) &&
1340             dev->data->dev_conf.intr_conf.rxq != 0) {
1341                 intr_vector = dev->data->nb_rx_queues;
1342                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1343                         return -1;
1344         }
1345
1346         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1347                 intr_handle->intr_vec =
1348                         rte_zmalloc("intr_vec",
1349                                     dev->data->nb_rx_queues * sizeof(int), 0);
1350                 if (intr_handle->intr_vec == NULL) {
1351                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1352                                      " intr_vec", dev->data->nb_rx_queues);
1353                         return -ENOMEM;
1354                 }
1355         }
1356
1357         /* confiugre msix for rx interrupt */
1358         eth_igb_configure_msix_intr(dev);
1359
1360         /* Configure for OS presence */
1361         igb_init_manageability(hw);
1362
1363         eth_igb_tx_init(dev);
1364
1365         /* This can fail when allocating mbufs for descriptor rings */
1366         ret = eth_igb_rx_init(dev);
1367         if (ret) {
1368                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1369                 igb_dev_clear_queues(dev);
1370                 return ret;
1371         }
1372
1373         e1000_clear_hw_cntrs_base_generic(hw);
1374
1375         /*
1376          * VLAN Offload Settings
1377          */
1378         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1379                         ETH_VLAN_EXTEND_MASK;
1380         ret = eth_igb_vlan_offload_set(dev, mask);
1381         if (ret) {
1382                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1383                 igb_dev_clear_queues(dev);
1384                 return ret;
1385         }
1386
1387         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1388                 /* Enable VLAN filter since VMDq always use VLAN filter */
1389                 igb_vmdq_vlan_hw_filter_enable(dev);
1390         }
1391
1392         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1393                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1394                 (hw->mac.type == e1000_i211)) {
1395                 /* Configure EITR with the maximum possible value (0xFFFF) */
1396                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1397         }
1398
1399         /* Setup link speed and duplex */
1400         speeds = &dev->data->dev_conf.link_speeds;
1401         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1402                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1403                 hw->mac.autoneg = 1;
1404         } else {
1405                 num_speeds = 0;
1406                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1407
1408                 /* Reset */
1409                 hw->phy.autoneg_advertised = 0;
1410
1411                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1412                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1413                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1414                         num_speeds = -1;
1415                         goto error_invalid_config;
1416                 }
1417                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1418                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1419                         num_speeds++;
1420                 }
1421                 if (*speeds & ETH_LINK_SPEED_10M) {
1422                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1423                         num_speeds++;
1424                 }
1425                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1426                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1427                         num_speeds++;
1428                 }
1429                 if (*speeds & ETH_LINK_SPEED_100M) {
1430                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1431                         num_speeds++;
1432                 }
1433                 if (*speeds & ETH_LINK_SPEED_1G) {
1434                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1435                         num_speeds++;
1436                 }
1437                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1438                         goto error_invalid_config;
1439
1440                 /* Set/reset the mac.autoneg based on the link speed,
1441                  * fixed or not
1442                  */
1443                 if (!autoneg) {
1444                         hw->mac.autoneg = 0;
1445                         hw->mac.forced_speed_duplex =
1446                                         hw->phy.autoneg_advertised;
1447                 } else {
1448                         hw->mac.autoneg = 1;
1449                 }
1450         }
1451
1452         e1000_setup_link(hw);
1453
1454         if (rte_intr_allow_others(intr_handle)) {
1455                 /* check if lsc interrupt is enabled */
1456                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1457                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1458                 else
1459                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1460         } else {
1461                 rte_intr_callback_unregister(intr_handle,
1462                                              eth_igb_interrupt_handler,
1463                                              (void *)dev);
1464                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1465                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1466                                      " no intr multiplex");
1467         }
1468
1469         /* check if rxq interrupt is enabled */
1470         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1471             rte_intr_dp_is_en(intr_handle))
1472                 eth_igb_rxq_interrupt_setup(dev);
1473
1474         /* enable uio/vfio intr/eventfd mapping */
1475         rte_intr_enable(intr_handle);
1476
1477         /* resume enabled intr since hw reset */
1478         igb_intr_enable(dev);
1479
1480         /* restore all types filter */
1481         igb_filter_restore(dev);
1482
1483         eth_igb_rxtx_control(dev, true);
1484         eth_igb_link_update(dev, 0);
1485
1486         PMD_INIT_LOG(DEBUG, "<<");
1487
1488         return 0;
1489
1490 error_invalid_config:
1491         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1492                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1493         igb_dev_clear_queues(dev);
1494         return -EINVAL;
1495 }
1496
1497 /*********************************************************************
1498  *
1499  *  This routine disables all traffic on the adapter by issuing a
1500  *  global reset on the MAC.
1501  *
1502  **********************************************************************/
1503 static void
1504 eth_igb_stop(struct rte_eth_dev *dev)
1505 {
1506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1507         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1508         struct rte_eth_link link;
1509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510
1511         eth_igb_rxtx_control(dev, false);
1512
1513         igb_intr_disable(dev);
1514
1515         /* disable intr eventfd mapping */
1516         rte_intr_disable(intr_handle);
1517
1518         igb_pf_reset_hw(hw);
1519         E1000_WRITE_REG(hw, E1000_WUC, 0);
1520
1521         /* Set bit for Go Link disconnect */
1522         if (hw->mac.type >= e1000_82580) {
1523                 uint32_t phpm_reg;
1524
1525                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1526                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1527                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1528         }
1529
1530         /* Power down the phy. Needed to make the link go Down */
1531         eth_igb_dev_set_link_down(dev);
1532
1533         igb_dev_clear_queues(dev);
1534
1535         /* clear the recorded link status */
1536         memset(&link, 0, sizeof(link));
1537         rte_eth_linkstatus_set(dev, &link);
1538
1539         if (!rte_intr_allow_others(intr_handle))
1540                 /* resume to the default handler */
1541                 rte_intr_callback_register(intr_handle,
1542                                            eth_igb_interrupt_handler,
1543                                            (void *)dev);
1544
1545         /* Clean datapath event and queue/vec mapping */
1546         rte_intr_efd_disable(intr_handle);
1547         if (intr_handle->intr_vec != NULL) {
1548                 rte_free(intr_handle->intr_vec);
1549                 intr_handle->intr_vec = NULL;
1550         }
1551 }
1552
1553 static int
1554 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1555 {
1556         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557
1558         if (hw->phy.media_type == e1000_media_type_copper)
1559                 e1000_power_up_phy(hw);
1560         else
1561                 e1000_power_up_fiber_serdes_link(hw);
1562
1563         return 0;
1564 }
1565
1566 static int
1567 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         if (hw->phy.media_type == e1000_media_type_copper)
1572                 e1000_power_down_phy(hw);
1573         else
1574                 e1000_shutdown_fiber_serdes_link(hw);
1575
1576         return 0;
1577 }
1578
1579 static void
1580 eth_igb_close(struct rte_eth_dev *dev)
1581 {
1582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1583         struct e1000_adapter *adapter =
1584                 E1000_DEV_PRIVATE(dev->data->dev_private);
1585         struct rte_eth_link link;
1586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588
1589         eth_igb_stop(dev);
1590         adapter->stopped = 1;
1591
1592         e1000_phy_hw_reset(hw);
1593         igb_release_manageability(hw);
1594         igb_hw_control_release(hw);
1595
1596         /* Clear bit for Go Link disconnect */
1597         if (hw->mac.type >= e1000_82580) {
1598                 uint32_t phpm_reg;
1599
1600                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1601                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1602                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1603         }
1604
1605         igb_dev_free_queues(dev);
1606
1607         if (intr_handle->intr_vec) {
1608                 rte_free(intr_handle->intr_vec);
1609                 intr_handle->intr_vec = NULL;
1610         }
1611
1612         memset(&link, 0, sizeof(link));
1613         rte_eth_linkstatus_set(dev, &link);
1614 }
1615
1616 /*
1617  * Reset PF device.
1618  */
1619 static int
1620 eth_igb_reset(struct rte_eth_dev *dev)
1621 {
1622         int ret;
1623
1624         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1625          * its VF to make them align with it. The detailed notification
1626          * mechanism is PMD specific and is currently not implemented.
1627          * To avoid unexpected behavior in VF, currently reset of PF with
1628          * SR-IOV activation is not supported. It might be supported later.
1629          */
1630         if (dev->data->sriov.active)
1631                 return -ENOTSUP;
1632
1633         ret = eth_igb_dev_uninit(dev);
1634         if (ret)
1635                 return ret;
1636
1637         ret = eth_igb_dev_init(dev);
1638
1639         return ret;
1640 }
1641
1642
1643 static int
1644 igb_get_rx_buffer_size(struct e1000_hw *hw)
1645 {
1646         uint32_t rx_buf_size;
1647         if (hw->mac.type == e1000_82576) {
1648                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1649         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1650                 /* PBS needs to be translated according to a lookup table */
1651                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1652                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1653                 rx_buf_size = (rx_buf_size << 10);
1654         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1655                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1656         } else {
1657                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1658         }
1659
1660         return rx_buf_size;
1661 }
1662
1663 /*********************************************************************
1664  *
1665  *  Initialize the hardware
1666  *
1667  **********************************************************************/
1668 static int
1669 igb_hardware_init(struct e1000_hw *hw)
1670 {
1671         uint32_t rx_buf_size;
1672         int diag;
1673
1674         /* Let the firmware know the OS is in control */
1675         igb_hw_control_acquire(hw);
1676
1677         /*
1678          * These parameters control the automatic generation (Tx) and
1679          * response (Rx) to Ethernet PAUSE frames.
1680          * - High water mark should allow for at least two standard size (1518)
1681          *   frames to be received after sending an XOFF.
1682          * - Low water mark works best when it is very near the high water mark.
1683          *   This allows the receiver to restart by sending XON when it has
1684          *   drained a bit. Here we use an arbitrary value of 1500 which will
1685          *   restart after one full frame is pulled from the buffer. There
1686          *   could be several smaller frames in the buffer and if so they will
1687          *   not trigger the XON until their total number reduces the buffer
1688          *   by 1500.
1689          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1690          */
1691         rx_buf_size = igb_get_rx_buffer_size(hw);
1692
1693         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
1694         hw->fc.low_water = hw->fc.high_water - 1500;
1695         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1696         hw->fc.send_xon = 1;
1697
1698         /* Set Flow control, use the tunable location if sane */
1699         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1700                 hw->fc.requested_mode = igb_fc_setting;
1701         else
1702                 hw->fc.requested_mode = e1000_fc_none;
1703
1704         /* Issue a global reset */
1705         igb_pf_reset_hw(hw);
1706         E1000_WRITE_REG(hw, E1000_WUC, 0);
1707
1708         diag = e1000_init_hw(hw);
1709         if (diag < 0)
1710                 return diag;
1711
1712         E1000_WRITE_REG(hw, E1000_VET,
1713                         RTE_ETHER_TYPE_VLAN << 16 | RTE_ETHER_TYPE_VLAN);
1714         e1000_get_phy_info(hw);
1715         e1000_check_for_link(hw);
1716
1717         return 0;
1718 }
1719
1720 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1721 static void
1722 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1723 {
1724         int pause_frames;
1725
1726         uint64_t old_gprc  = stats->gprc;
1727         uint64_t old_gptc  = stats->gptc;
1728         uint64_t old_tpr   = stats->tpr;
1729         uint64_t old_tpt   = stats->tpt;
1730         uint64_t old_rpthc = stats->rpthc;
1731         uint64_t old_hgptc = stats->hgptc;
1732
1733         if(hw->phy.media_type == e1000_media_type_copper ||
1734             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1735                 stats->symerrs +=
1736                     E1000_READ_REG(hw,E1000_SYMERRS);
1737                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1738         }
1739
1740         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1741         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1742         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1743         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1744
1745         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1746         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1747         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1748         stats->dc += E1000_READ_REG(hw, E1000_DC);
1749         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1750         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1751         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1752         /*
1753         ** For watchdog management we need to know if we have been
1754         ** paused during the last interval, so capture that here.
1755         */
1756         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1757         stats->xoffrxc += pause_frames;
1758         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1759         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1760         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1761         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1762         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1763         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1764         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1765         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1766         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1767         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1768         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1769         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1770
1771         /* For the 64-bit byte counters the low dword must be read first. */
1772         /* Both registers clear on the read of the high dword */
1773
1774         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1775         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1776         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1777         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1778         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1779         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1780         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1781
1782         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1783         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1784         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1785         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1786         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1787
1788         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1789         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1790
1791         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1792         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1793         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1794         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1795         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1796         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1797
1798         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1799         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1800         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1801         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1802         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1803         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1804         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1805         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1806
1807         /* Interrupt Counts */
1808
1809         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1810         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1811         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1812         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1813         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1814         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1815         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1816         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1817         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1818
1819         /* Host to Card Statistics */
1820
1821         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1822         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1823         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1824         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1825         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1826         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1827         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1828         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1829         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1830         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1831         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1832         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1833         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1834         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1835         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1836         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1837
1838         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1839         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1840         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1841         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1842         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1843         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1844 }
1845
1846 static int
1847 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1848 {
1849         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1850         struct e1000_hw_stats *stats =
1851                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1852
1853         igb_read_stats_registers(hw, stats);
1854
1855         if (rte_stats == NULL)
1856                 return -EINVAL;
1857
1858         /* Rx Errors */
1859         rte_stats->imissed = stats->mpc;
1860         rte_stats->ierrors = stats->crcerrs +
1861                              stats->rlec + stats->ruc + stats->roc +
1862                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1863
1864         /* Tx Errors */
1865         rte_stats->oerrors = stats->ecol + stats->latecol;
1866
1867         rte_stats->ipackets = stats->gprc;
1868         rte_stats->opackets = stats->gptc;
1869         rte_stats->ibytes   = stats->gorc;
1870         rte_stats->obytes   = stats->gotc;
1871         return 0;
1872 }
1873
1874 static void
1875 eth_igb_stats_reset(struct rte_eth_dev *dev)
1876 {
1877         struct e1000_hw_stats *hw_stats =
1878                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1879
1880         /* HW registers are cleared on read */
1881         eth_igb_stats_get(dev, NULL);
1882
1883         /* Reset software totals */
1884         memset(hw_stats, 0, sizeof(*hw_stats));
1885 }
1886
1887 static void
1888 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1889 {
1890         struct e1000_hw_stats *stats =
1891                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1892
1893         /* HW registers are cleared on read */
1894         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1895
1896         /* Reset software totals */
1897         memset(stats, 0, sizeof(*stats));
1898 }
1899
1900 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1901         struct rte_eth_xstat_name *xstats_names,
1902         __rte_unused unsigned int size)
1903 {
1904         unsigned i;
1905
1906         if (xstats_names == NULL)
1907                 return IGB_NB_XSTATS;
1908
1909         /* Note: limit checked in rte_eth_xstats_names() */
1910
1911         for (i = 0; i < IGB_NB_XSTATS; i++) {
1912                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1913                         sizeof(xstats_names[i].name));
1914         }
1915
1916         return IGB_NB_XSTATS;
1917 }
1918
1919 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1920                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1921                 unsigned int limit)
1922 {
1923         unsigned int i;
1924
1925         if (!ids) {
1926                 if (xstats_names == NULL)
1927                         return IGB_NB_XSTATS;
1928
1929                 for (i = 0; i < IGB_NB_XSTATS; i++)
1930                         strlcpy(xstats_names[i].name,
1931                                 rte_igb_stats_strings[i].name,
1932                                 sizeof(xstats_names[i].name));
1933
1934                 return IGB_NB_XSTATS;
1935
1936         } else {
1937                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1938
1939                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1940                                 IGB_NB_XSTATS);
1941
1942                 for (i = 0; i < limit; i++) {
1943                         if (ids[i] >= IGB_NB_XSTATS) {
1944                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1945                                 return -1;
1946                         }
1947                         strcpy(xstats_names[i].name,
1948                                         xstats_names_copy[ids[i]].name);
1949                 }
1950                 return limit;
1951         }
1952 }
1953
1954 static int
1955 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1956                    unsigned n)
1957 {
1958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct e1000_hw_stats *hw_stats =
1960                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1961         unsigned i;
1962
1963         if (n < IGB_NB_XSTATS)
1964                 return IGB_NB_XSTATS;
1965
1966         igb_read_stats_registers(hw, hw_stats);
1967
1968         /* If this is a reset xstats is NULL, and we have cleared the
1969          * registers by reading them.
1970          */
1971         if (!xstats)
1972                 return 0;
1973
1974         /* Extended stats */
1975         for (i = 0; i < IGB_NB_XSTATS; i++) {
1976                 xstats[i].id = i;
1977                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1978                         rte_igb_stats_strings[i].offset);
1979         }
1980
1981         return IGB_NB_XSTATS;
1982 }
1983
1984 static int
1985 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1986                 uint64_t *values, unsigned int n)
1987 {
1988         unsigned int i;
1989
1990         if (!ids) {
1991                 struct e1000_hw *hw =
1992                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993                 struct e1000_hw_stats *hw_stats =
1994                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1995
1996                 if (n < IGB_NB_XSTATS)
1997                         return IGB_NB_XSTATS;
1998
1999                 igb_read_stats_registers(hw, hw_stats);
2000
2001                 /* If this is a reset xstats is NULL, and we have cleared the
2002                  * registers by reading them.
2003                  */
2004                 if (!values)
2005                         return 0;
2006
2007                 /* Extended stats */
2008                 for (i = 0; i < IGB_NB_XSTATS; i++)
2009                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2010                                         rte_igb_stats_strings[i].offset);
2011
2012                 return IGB_NB_XSTATS;
2013
2014         } else {
2015                 uint64_t values_copy[IGB_NB_XSTATS];
2016
2017                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2018                                 IGB_NB_XSTATS);
2019
2020                 for (i = 0; i < n; i++) {
2021                         if (ids[i] >= IGB_NB_XSTATS) {
2022                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2023                                 return -1;
2024                         }
2025                         values[i] = values_copy[ids[i]];
2026                 }
2027                 return n;
2028         }
2029 }
2030
2031 static void
2032 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2033 {
2034         /* Good Rx packets, include VF loopback */
2035         UPDATE_VF_STAT(E1000_VFGPRC,
2036             hw_stats->last_gprc, hw_stats->gprc);
2037
2038         /* Good Rx octets, include VF loopback */
2039         UPDATE_VF_STAT(E1000_VFGORC,
2040             hw_stats->last_gorc, hw_stats->gorc);
2041
2042         /* Good Tx packets, include VF loopback */
2043         UPDATE_VF_STAT(E1000_VFGPTC,
2044             hw_stats->last_gptc, hw_stats->gptc);
2045
2046         /* Good Tx octets, include VF loopback */
2047         UPDATE_VF_STAT(E1000_VFGOTC,
2048             hw_stats->last_gotc, hw_stats->gotc);
2049
2050         /* Rx Multicst packets */
2051         UPDATE_VF_STAT(E1000_VFMPRC,
2052             hw_stats->last_mprc, hw_stats->mprc);
2053
2054         /* Good Rx loopback packets */
2055         UPDATE_VF_STAT(E1000_VFGPRLBC,
2056             hw_stats->last_gprlbc, hw_stats->gprlbc);
2057
2058         /* Good Rx loopback octets */
2059         UPDATE_VF_STAT(E1000_VFGORLBC,
2060             hw_stats->last_gorlbc, hw_stats->gorlbc);
2061
2062         /* Good Tx loopback packets */
2063         UPDATE_VF_STAT(E1000_VFGPTLBC,
2064             hw_stats->last_gptlbc, hw_stats->gptlbc);
2065
2066         /* Good Tx loopback octets */
2067         UPDATE_VF_STAT(E1000_VFGOTLBC,
2068             hw_stats->last_gotlbc, hw_stats->gotlbc);
2069 }
2070
2071 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2072                                      struct rte_eth_xstat_name *xstats_names,
2073                                      __rte_unused unsigned limit)
2074 {
2075         unsigned i;
2076
2077         if (xstats_names != NULL)
2078                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2079                         strlcpy(xstats_names[i].name,
2080                                 rte_igbvf_stats_strings[i].name,
2081                                 sizeof(xstats_names[i].name));
2082                 }
2083         return IGBVF_NB_XSTATS;
2084 }
2085
2086 static int
2087 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2088                      unsigned n)
2089 {
2090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2092                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2093         unsigned i;
2094
2095         if (n < IGBVF_NB_XSTATS)
2096                 return IGBVF_NB_XSTATS;
2097
2098         igbvf_read_stats_registers(hw, hw_stats);
2099
2100         if (!xstats)
2101                 return 0;
2102
2103         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2104                 xstats[i].id = i;
2105                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2106                         rte_igbvf_stats_strings[i].offset);
2107         }
2108
2109         return IGBVF_NB_XSTATS;
2110 }
2111
2112 static int
2113 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2114 {
2115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2117                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2118
2119         igbvf_read_stats_registers(hw, hw_stats);
2120
2121         if (rte_stats == NULL)
2122                 return -EINVAL;
2123
2124         rte_stats->ipackets = hw_stats->gprc;
2125         rte_stats->ibytes = hw_stats->gorc;
2126         rte_stats->opackets = hw_stats->gptc;
2127         rte_stats->obytes = hw_stats->gotc;
2128         return 0;
2129 }
2130
2131 static void
2132 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2133 {
2134         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2135                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2136
2137         /* Sync HW register to the last stats */
2138         eth_igbvf_stats_get(dev, NULL);
2139
2140         /* reset HW current stats*/
2141         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2142                offsetof(struct e1000_vf_stats, gprc));
2143 }
2144
2145 static int
2146 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2147                        size_t fw_size)
2148 {
2149         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct e1000_fw_version fw;
2151         int ret;
2152
2153         e1000_get_fw_version(hw, &fw);
2154
2155         switch (hw->mac.type) {
2156         case e1000_i210:
2157         case e1000_i211:
2158                 if (!(e1000_get_flash_presence_i210(hw))) {
2159                         ret = snprintf(fw_version, fw_size,
2160                                  "%2d.%2d-%d",
2161                                  fw.invm_major, fw.invm_minor,
2162                                  fw.invm_img_type);
2163                         break;
2164                 }
2165                 /* fall through */
2166         default:
2167                 /* if option rom is valid, display its version too */
2168                 if (fw.or_valid) {
2169                         ret = snprintf(fw_version, fw_size,
2170                                  "%d.%d, 0x%08x, %d.%d.%d",
2171                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2172                                  fw.or_major, fw.or_build, fw.or_patch);
2173                 /* no option rom */
2174                 } else {
2175                         if (fw.etrack_id != 0X0000) {
2176                                 ret = snprintf(fw_version, fw_size,
2177                                          "%d.%d, 0x%08x",
2178                                          fw.eep_major, fw.eep_minor,
2179                                          fw.etrack_id);
2180                         } else {
2181                                 ret = snprintf(fw_version, fw_size,
2182                                          "%d.%d.%d",
2183                                          fw.eep_major, fw.eep_minor,
2184                                          fw.eep_build);
2185                         }
2186                 }
2187                 break;
2188         }
2189
2190         ret += 1; /* add the size of '\0' */
2191         if (fw_size < (u32)ret)
2192                 return ret;
2193         else
2194                 return 0;
2195 }
2196
2197 static void
2198 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2199 {
2200         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201
2202         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2203         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2204         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2205         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2206         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2207                                     dev_info->rx_queue_offload_capa;
2208         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2209         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2210                                     dev_info->tx_queue_offload_capa;
2211
2212         switch (hw->mac.type) {
2213         case e1000_82575:
2214                 dev_info->max_rx_queues = 4;
2215                 dev_info->max_tx_queues = 4;
2216                 dev_info->max_vmdq_pools = 0;
2217                 break;
2218
2219         case e1000_82576:
2220                 dev_info->max_rx_queues = 16;
2221                 dev_info->max_tx_queues = 16;
2222                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2223                 dev_info->vmdq_queue_num = 16;
2224                 break;
2225
2226         case e1000_82580:
2227                 dev_info->max_rx_queues = 8;
2228                 dev_info->max_tx_queues = 8;
2229                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2230                 dev_info->vmdq_queue_num = 8;
2231                 break;
2232
2233         case e1000_i350:
2234                 dev_info->max_rx_queues = 8;
2235                 dev_info->max_tx_queues = 8;
2236                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2237                 dev_info->vmdq_queue_num = 8;
2238                 break;
2239
2240         case e1000_i354:
2241                 dev_info->max_rx_queues = 8;
2242                 dev_info->max_tx_queues = 8;
2243                 break;
2244
2245         case e1000_i210:
2246                 dev_info->max_rx_queues = 4;
2247                 dev_info->max_tx_queues = 4;
2248                 dev_info->max_vmdq_pools = 0;
2249                 break;
2250
2251         case e1000_i211:
2252                 dev_info->max_rx_queues = 2;
2253                 dev_info->max_tx_queues = 2;
2254                 dev_info->max_vmdq_pools = 0;
2255                 break;
2256
2257         default:
2258                 /* Should not happen */
2259                 break;
2260         }
2261         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2262         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2263         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2264
2265         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2266                 .rx_thresh = {
2267                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2268                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2269                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2270                 },
2271                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2272                 .rx_drop_en = 0,
2273                 .offloads = 0,
2274         };
2275
2276         dev_info->default_txconf = (struct rte_eth_txconf) {
2277                 .tx_thresh = {
2278                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2279                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2280                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2281                 },
2282                 .offloads = 0,
2283         };
2284
2285         dev_info->rx_desc_lim = rx_desc_lim;
2286         dev_info->tx_desc_lim = tx_desc_lim;
2287
2288         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2289                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2290                         ETH_LINK_SPEED_1G;
2291
2292         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2293         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2294
2295 }
2296
2297 static const uint32_t *
2298 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2299 {
2300         static const uint32_t ptypes[] = {
2301                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2302                 RTE_PTYPE_L2_ETHER,
2303                 RTE_PTYPE_L3_IPV4,
2304                 RTE_PTYPE_L3_IPV4_EXT,
2305                 RTE_PTYPE_L3_IPV6,
2306                 RTE_PTYPE_L3_IPV6_EXT,
2307                 RTE_PTYPE_L4_TCP,
2308                 RTE_PTYPE_L4_UDP,
2309                 RTE_PTYPE_L4_SCTP,
2310                 RTE_PTYPE_TUNNEL_IP,
2311                 RTE_PTYPE_INNER_L3_IPV6,
2312                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2313                 RTE_PTYPE_INNER_L4_TCP,
2314                 RTE_PTYPE_INNER_L4_UDP,
2315                 RTE_PTYPE_UNKNOWN
2316         };
2317
2318         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2319             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2320                 return ptypes;
2321         return NULL;
2322 }
2323
2324 static void
2325 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2326 {
2327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328
2329         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2330         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2331         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2332         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2333                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2334                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2335                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2336                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2337                                 DEV_TX_OFFLOAD_TCP_TSO;
2338         switch (hw->mac.type) {
2339         case e1000_vfadapt:
2340                 dev_info->max_rx_queues = 2;
2341                 dev_info->max_tx_queues = 2;
2342                 break;
2343         case e1000_vfadapt_i350:
2344                 dev_info->max_rx_queues = 1;
2345                 dev_info->max_tx_queues = 1;
2346                 break;
2347         default:
2348                 /* Should not happen */
2349                 break;
2350         }
2351
2352         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2353         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2354                                     dev_info->rx_queue_offload_capa;
2355         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2356         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2357                                     dev_info->tx_queue_offload_capa;
2358
2359         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2360                 .rx_thresh = {
2361                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2362                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2363                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2364                 },
2365                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2366                 .rx_drop_en = 0,
2367                 .offloads = 0,
2368         };
2369
2370         dev_info->default_txconf = (struct rte_eth_txconf) {
2371                 .tx_thresh = {
2372                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2373                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2374                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2375                 },
2376                 .offloads = 0,
2377         };
2378
2379         dev_info->rx_desc_lim = rx_desc_lim;
2380         dev_info->tx_desc_lim = tx_desc_lim;
2381 }
2382
2383 /* return 0 means link status changed, -1 means not changed */
2384 static int
2385 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2386 {
2387         struct e1000_hw *hw =
2388                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389         struct rte_eth_link link;
2390         int link_check, count;
2391
2392         link_check = 0;
2393         hw->mac.get_link_status = 1;
2394
2395         /* possible wait-to-complete in up to 9 seconds */
2396         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2397                 /* Read the real link status */
2398                 switch (hw->phy.media_type) {
2399                 case e1000_media_type_copper:
2400                         /* Do the work to read phy */
2401                         e1000_check_for_link(hw);
2402                         link_check = !hw->mac.get_link_status;
2403                         break;
2404
2405                 case e1000_media_type_fiber:
2406                         e1000_check_for_link(hw);
2407                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2408                                       E1000_STATUS_LU);
2409                         break;
2410
2411                 case e1000_media_type_internal_serdes:
2412                         e1000_check_for_link(hw);
2413                         link_check = hw->mac.serdes_has_link;
2414                         break;
2415
2416                 /* VF device is type_unknown */
2417                 case e1000_media_type_unknown:
2418                         eth_igbvf_link_update(hw);
2419                         link_check = !hw->mac.get_link_status;
2420                         break;
2421
2422                 default:
2423                         break;
2424                 }
2425                 if (link_check || wait_to_complete == 0)
2426                         break;
2427                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2428         }
2429         memset(&link, 0, sizeof(link));
2430
2431         /* Now we check if a transition has happened */
2432         if (link_check) {
2433                 uint16_t duplex, speed;
2434                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2435                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2436                                 ETH_LINK_FULL_DUPLEX :
2437                                 ETH_LINK_HALF_DUPLEX;
2438                 link.link_speed = speed;
2439                 link.link_status = ETH_LINK_UP;
2440                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2441                                 ETH_LINK_SPEED_FIXED);
2442         } else if (!link_check) {
2443                 link.link_speed = 0;
2444                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2445                 link.link_status = ETH_LINK_DOWN;
2446                 link.link_autoneg = ETH_LINK_FIXED;
2447         }
2448
2449         return rte_eth_linkstatus_set(dev, &link);
2450 }
2451
2452 /*
2453  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2454  * For ASF and Pass Through versions of f/w this means
2455  * that the driver is loaded.
2456  */
2457 static void
2458 igb_hw_control_acquire(struct e1000_hw *hw)
2459 {
2460         uint32_t ctrl_ext;
2461
2462         /* Let firmware know the driver has taken over */
2463         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2464         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2465 }
2466
2467 /*
2468  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2469  * For ASF and Pass Through versions of f/w this means that the
2470  * driver is no longer loaded.
2471  */
2472 static void
2473 igb_hw_control_release(struct e1000_hw *hw)
2474 {
2475         uint32_t ctrl_ext;
2476
2477         /* Let firmware taken over control of h/w */
2478         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2479         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2480                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2481 }
2482
2483 /*
2484  * Bit of a misnomer, what this really means is
2485  * to enable OS management of the system... aka
2486  * to disable special hardware management features.
2487  */
2488 static void
2489 igb_init_manageability(struct e1000_hw *hw)
2490 {
2491         if (e1000_enable_mng_pass_thru(hw)) {
2492                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2493                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2494
2495                 /* disable hardware interception of ARP */
2496                 manc &= ~(E1000_MANC_ARP_EN);
2497
2498                 /* enable receiving management packets to the host */
2499                 manc |= E1000_MANC_EN_MNG2HOST;
2500                 manc2h |= 1 << 5;  /* Mng Port 623 */
2501                 manc2h |= 1 << 6;  /* Mng Port 664 */
2502                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2503                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2504         }
2505 }
2506
2507 static void
2508 igb_release_manageability(struct e1000_hw *hw)
2509 {
2510         if (e1000_enable_mng_pass_thru(hw)) {
2511                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2512
2513                 manc |= E1000_MANC_ARP_EN;
2514                 manc &= ~E1000_MANC_EN_MNG2HOST;
2515
2516                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2517         }
2518 }
2519
2520 static void
2521 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2522 {
2523         struct e1000_hw *hw =
2524                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525         uint32_t rctl;
2526
2527         rctl = E1000_READ_REG(hw, E1000_RCTL);
2528         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2529         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2530 }
2531
2532 static void
2533 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2534 {
2535         struct e1000_hw *hw =
2536                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537         uint32_t rctl;
2538
2539         rctl = E1000_READ_REG(hw, E1000_RCTL);
2540         rctl &= (~E1000_RCTL_UPE);
2541         if (dev->data->all_multicast == 1)
2542                 rctl |= E1000_RCTL_MPE;
2543         else
2544                 rctl &= (~E1000_RCTL_MPE);
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546 }
2547
2548 static void
2549 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2550 {
2551         struct e1000_hw *hw =
2552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         uint32_t rctl;
2554
2555         rctl = E1000_READ_REG(hw, E1000_RCTL);
2556         rctl |= E1000_RCTL_MPE;
2557         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2558 }
2559
2560 static void
2561 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t rctl;
2566
2567         if (dev->data->promiscuous == 1)
2568                 return; /* must remain in all_multicast mode */
2569         rctl = E1000_READ_REG(hw, E1000_RCTL);
2570         rctl &= (~E1000_RCTL_MPE);
2571         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2572 }
2573
2574 static int
2575 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2576 {
2577         struct e1000_hw *hw =
2578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         struct e1000_vfta * shadow_vfta =
2580                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2581         uint32_t vfta;
2582         uint32_t vid_idx;
2583         uint32_t vid_bit;
2584
2585         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2586                               E1000_VFTA_ENTRY_MASK);
2587         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2588         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2589         if (on)
2590                 vfta |= vid_bit;
2591         else
2592                 vfta &= ~vid_bit;
2593         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2594
2595         /* update local VFTA copy */
2596         shadow_vfta->vfta[vid_idx] = vfta;
2597
2598         return 0;
2599 }
2600
2601 static int
2602 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2603                       enum rte_vlan_type vlan_type,
2604                       uint16_t tpid)
2605 {
2606         struct e1000_hw *hw =
2607                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608         uint32_t reg, qinq;
2609
2610         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2611         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2612
2613         /* only outer TPID of double VLAN can be configured*/
2614         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2615                 reg = E1000_READ_REG(hw, E1000_VET);
2616                 reg = (reg & (~E1000_VET_VET_EXT)) |
2617                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2618                 E1000_WRITE_REG(hw, E1000_VET, reg);
2619
2620                 return 0;
2621         }
2622
2623         /* all other TPID values are read-only*/
2624         PMD_DRV_LOG(ERR, "Not supported");
2625
2626         return -ENOTSUP;
2627 }
2628
2629 static void
2630 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2631 {
2632         struct e1000_hw *hw =
2633                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2634         uint32_t reg;
2635
2636         /* Filter Table Disable */
2637         reg = E1000_READ_REG(hw, E1000_RCTL);
2638         reg &= ~E1000_RCTL_CFIEN;
2639         reg &= ~E1000_RCTL_VFE;
2640         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2641 }
2642
2643 static void
2644 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2645 {
2646         struct e1000_hw *hw =
2647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648         struct e1000_vfta * shadow_vfta =
2649                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2650         uint32_t reg;
2651         int i;
2652
2653         /* Filter Table Enable, CFI not used for packet acceptance */
2654         reg = E1000_READ_REG(hw, E1000_RCTL);
2655         reg &= ~E1000_RCTL_CFIEN;
2656         reg |= E1000_RCTL_VFE;
2657         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2658
2659         /* restore VFTA table */
2660         for (i = 0; i < IGB_VFTA_SIZE; i++)
2661                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2662 }
2663
2664 static void
2665 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2666 {
2667         struct e1000_hw *hw =
2668                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669         uint32_t reg;
2670
2671         /* VLAN Mode Disable */
2672         reg = E1000_READ_REG(hw, E1000_CTRL);
2673         reg &= ~E1000_CTRL_VME;
2674         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2675 }
2676
2677 static void
2678 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2679 {
2680         struct e1000_hw *hw =
2681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682         uint32_t reg;
2683
2684         /* VLAN Mode Enable */
2685         reg = E1000_READ_REG(hw, E1000_CTRL);
2686         reg |= E1000_CTRL_VME;
2687         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2688 }
2689
2690 static void
2691 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2692 {
2693         struct e1000_hw *hw =
2694                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695         uint32_t reg;
2696
2697         /* CTRL_EXT: Extended VLAN */
2698         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2699         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2700         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2701
2702         /* Update maximum packet length */
2703         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2704                 E1000_WRITE_REG(hw, E1000_RLPML,
2705                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2706                                                 VLAN_TAG_SIZE);
2707 }
2708
2709 static void
2710 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2711 {
2712         struct e1000_hw *hw =
2713                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         uint32_t reg;
2715
2716         /* CTRL_EXT: Extended VLAN */
2717         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2718         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2719         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2720
2721         /* Update maximum packet length */
2722         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2723                 E1000_WRITE_REG(hw, E1000_RLPML,
2724                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2725                                                 2 * VLAN_TAG_SIZE);
2726 }
2727
2728 static int
2729 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2730 {
2731         struct rte_eth_rxmode *rxmode;
2732
2733         rxmode = &dev->data->dev_conf.rxmode;
2734         if(mask & ETH_VLAN_STRIP_MASK){
2735                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2736                         igb_vlan_hw_strip_enable(dev);
2737                 else
2738                         igb_vlan_hw_strip_disable(dev);
2739         }
2740
2741         if(mask & ETH_VLAN_FILTER_MASK){
2742                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2743                         igb_vlan_hw_filter_enable(dev);
2744                 else
2745                         igb_vlan_hw_filter_disable(dev);
2746         }
2747
2748         if(mask & ETH_VLAN_EXTEND_MASK){
2749                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2750                         igb_vlan_hw_extend_enable(dev);
2751                 else
2752                         igb_vlan_hw_extend_disable(dev);
2753         }
2754
2755         return 0;
2756 }
2757
2758
2759 /**
2760  * It enables the interrupt mask and then enable the interrupt.
2761  *
2762  * @param dev
2763  *  Pointer to struct rte_eth_dev.
2764  * @param on
2765  *  Enable or Disable
2766  *
2767  * @return
2768  *  - On success, zero.
2769  *  - On failure, a negative value.
2770  */
2771 static int
2772 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2773 {
2774         struct e1000_interrupt *intr =
2775                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2776
2777         if (on)
2778                 intr->mask |= E1000_ICR_LSC;
2779         else
2780                 intr->mask &= ~E1000_ICR_LSC;
2781
2782         return 0;
2783 }
2784
2785 /* It clears the interrupt causes and enables the interrupt.
2786  * It will be called once only during nic initialized.
2787  *
2788  * @param dev
2789  *  Pointer to struct rte_eth_dev.
2790  *
2791  * @return
2792  *  - On success, zero.
2793  *  - On failure, a negative value.
2794  */
2795 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2796 {
2797         uint32_t mask, regval;
2798         struct e1000_hw *hw =
2799                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2801         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2802         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2803         struct rte_eth_dev_info dev_info;
2804
2805         memset(&dev_info, 0, sizeof(dev_info));
2806         eth_igb_infos_get(dev, &dev_info);
2807
2808         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2809         regval = E1000_READ_REG(hw, E1000_EIMS);
2810         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2811
2812         return 0;
2813 }
2814
2815 /*
2816  * It reads ICR and gets interrupt causes, check it and set a bit flag
2817  * to update link status.
2818  *
2819  * @param dev
2820  *  Pointer to struct rte_eth_dev.
2821  *
2822  * @return
2823  *  - On success, zero.
2824  *  - On failure, a negative value.
2825  */
2826 static int
2827 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2828 {
2829         uint32_t icr;
2830         struct e1000_hw *hw =
2831                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         struct e1000_interrupt *intr =
2833                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2834
2835         igb_intr_disable(dev);
2836
2837         /* read-on-clear nic registers here */
2838         icr = E1000_READ_REG(hw, E1000_ICR);
2839
2840         intr->flags = 0;
2841         if (icr & E1000_ICR_LSC) {
2842                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2843         }
2844
2845         if (icr & E1000_ICR_VMMB)
2846                 intr->flags |= E1000_FLAG_MAILBOX;
2847
2848         return 0;
2849 }
2850
2851 /*
2852  * It executes link_update after knowing an interrupt is prsent.
2853  *
2854  * @param dev
2855  *  Pointer to struct rte_eth_dev.
2856  *
2857  * @return
2858  *  - On success, zero.
2859  *  - On failure, a negative value.
2860  */
2861 static int
2862 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2863                          struct rte_intr_handle *intr_handle)
2864 {
2865         struct e1000_hw *hw =
2866                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2867         struct e1000_interrupt *intr =
2868                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2870         struct rte_eth_link link;
2871         int ret;
2872
2873         if (intr->flags & E1000_FLAG_MAILBOX) {
2874                 igb_pf_mbx_process(dev);
2875                 intr->flags &= ~E1000_FLAG_MAILBOX;
2876         }
2877
2878         igb_intr_enable(dev);
2879         rte_intr_enable(intr_handle);
2880
2881         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2882                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2883
2884                 /* set get_link_status to check register later */
2885                 hw->mac.get_link_status = 1;
2886                 ret = eth_igb_link_update(dev, 0);
2887
2888                 /* check if link has changed */
2889                 if (ret < 0)
2890                         return 0;
2891
2892                 rte_eth_linkstatus_get(dev, &link);
2893                 if (link.link_status) {
2894                         PMD_INIT_LOG(INFO,
2895                                      " Port %d: Link Up - speed %u Mbps - %s",
2896                                      dev->data->port_id,
2897                                      (unsigned)link.link_speed,
2898                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2899                                      "full-duplex" : "half-duplex");
2900                 } else {
2901                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2902                                      dev->data->port_id);
2903                 }
2904
2905                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2906                              pci_dev->addr.domain,
2907                              pci_dev->addr.bus,
2908                              pci_dev->addr.devid,
2909                              pci_dev->addr.function);
2910                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2911                                               NULL);
2912         }
2913
2914         return 0;
2915 }
2916
2917 /**
2918  * Interrupt handler which shall be registered at first.
2919  *
2920  * @param handle
2921  *  Pointer to interrupt handle.
2922  * @param param
2923  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2924  *
2925  * @return
2926  *  void
2927  */
2928 static void
2929 eth_igb_interrupt_handler(void *param)
2930 {
2931         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2932
2933         eth_igb_interrupt_get_status(dev);
2934         eth_igb_interrupt_action(dev, dev->intr_handle);
2935 }
2936
2937 static int
2938 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2939 {
2940         uint32_t eicr;
2941         struct e1000_hw *hw =
2942                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         struct e1000_interrupt *intr =
2944                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2945
2946         igbvf_intr_disable(hw);
2947
2948         /* read-on-clear nic registers here */
2949         eicr = E1000_READ_REG(hw, E1000_EICR);
2950         intr->flags = 0;
2951
2952         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2953                 intr->flags |= E1000_FLAG_MAILBOX;
2954
2955         return 0;
2956 }
2957
2958 void igbvf_mbx_process(struct rte_eth_dev *dev)
2959 {
2960         struct e1000_hw *hw =
2961                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         struct e1000_mbx_info *mbx = &hw->mbx;
2963         u32 in_msg = 0;
2964
2965         /* peek the message first */
2966         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2967
2968         /* PF reset VF event */
2969         if (in_msg == E1000_PF_CONTROL_MSG) {
2970                 /* dummy mbx read to ack pf */
2971                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2972                         return;
2973                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2974                                               NULL);
2975         }
2976 }
2977
2978 static int
2979 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2980 {
2981         struct e1000_interrupt *intr =
2982                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2983
2984         if (intr->flags & E1000_FLAG_MAILBOX) {
2985                 igbvf_mbx_process(dev);
2986                 intr->flags &= ~E1000_FLAG_MAILBOX;
2987         }
2988
2989         igbvf_intr_enable(dev);
2990         rte_intr_enable(intr_handle);
2991
2992         return 0;
2993 }
2994
2995 static void
2996 eth_igbvf_interrupt_handler(void *param)
2997 {
2998         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2999
3000         eth_igbvf_interrupt_get_status(dev);
3001         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3002 }
3003
3004 static int
3005 eth_igb_led_on(struct rte_eth_dev *dev)
3006 {
3007         struct e1000_hw *hw;
3008
3009         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3011 }
3012
3013 static int
3014 eth_igb_led_off(struct rte_eth_dev *dev)
3015 {
3016         struct e1000_hw *hw;
3017
3018         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3020 }
3021
3022 static int
3023 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3024 {
3025         struct e1000_hw *hw;
3026         uint32_t ctrl;
3027         int tx_pause;
3028         int rx_pause;
3029
3030         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031         fc_conf->pause_time = hw->fc.pause_time;
3032         fc_conf->high_water = hw->fc.high_water;
3033         fc_conf->low_water = hw->fc.low_water;
3034         fc_conf->send_xon = hw->fc.send_xon;
3035         fc_conf->autoneg = hw->mac.autoneg;
3036
3037         /*
3038          * Return rx_pause and tx_pause status according to actual setting of
3039          * the TFCE and RFCE bits in the CTRL register.
3040          */
3041         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3042         if (ctrl & E1000_CTRL_TFCE)
3043                 tx_pause = 1;
3044         else
3045                 tx_pause = 0;
3046
3047         if (ctrl & E1000_CTRL_RFCE)
3048                 rx_pause = 1;
3049         else
3050                 rx_pause = 0;
3051
3052         if (rx_pause && tx_pause)
3053                 fc_conf->mode = RTE_FC_FULL;
3054         else if (rx_pause)
3055                 fc_conf->mode = RTE_FC_RX_PAUSE;
3056         else if (tx_pause)
3057                 fc_conf->mode = RTE_FC_TX_PAUSE;
3058         else
3059                 fc_conf->mode = RTE_FC_NONE;
3060
3061         return 0;
3062 }
3063
3064 static int
3065 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3066 {
3067         struct e1000_hw *hw;
3068         int err;
3069         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3070                 e1000_fc_none,
3071                 e1000_fc_rx_pause,
3072                 e1000_fc_tx_pause,
3073                 e1000_fc_full
3074         };
3075         uint32_t rx_buf_size;
3076         uint32_t max_high_water;
3077         uint32_t rctl;
3078
3079         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         if (fc_conf->autoneg != hw->mac.autoneg)
3081                 return -ENOTSUP;
3082         rx_buf_size = igb_get_rx_buffer_size(hw);
3083         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3084
3085         /* At least reserve one Ethernet frame for watermark */
3086         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
3087         if ((fc_conf->high_water > max_high_water) ||
3088             (fc_conf->high_water < fc_conf->low_water)) {
3089                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3090                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3091                 return -EINVAL;
3092         }
3093
3094         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3095         hw->fc.pause_time     = fc_conf->pause_time;
3096         hw->fc.high_water     = fc_conf->high_water;
3097         hw->fc.low_water      = fc_conf->low_water;
3098         hw->fc.send_xon       = fc_conf->send_xon;
3099
3100         err = e1000_setup_link_generic(hw);
3101         if (err == E1000_SUCCESS) {
3102
3103                 /* check if we want to forward MAC frames - driver doesn't have native
3104                  * capability to do that, so we'll write the registers ourselves */
3105
3106                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3107
3108                 /* set or clear MFLCN.PMCF bit depending on configuration */
3109                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3110                         rctl |= E1000_RCTL_PMCF;
3111                 else
3112                         rctl &= ~E1000_RCTL_PMCF;
3113
3114                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3115                 E1000_WRITE_FLUSH(hw);
3116
3117                 return 0;
3118         }
3119
3120         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3121         return -EIO;
3122 }
3123
3124 #define E1000_RAH_POOLSEL_SHIFT      (18)
3125 static int
3126 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3127                 uint32_t index, uint32_t pool)
3128 {
3129         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         uint32_t rah;
3131
3132         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3133         rah = E1000_READ_REG(hw, E1000_RAH(index));
3134         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3135         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3136         return 0;
3137 }
3138
3139 static void
3140 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3141 {
3142         uint8_t addr[RTE_ETHER_ADDR_LEN];
3143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3144
3145         memset(addr, 0, sizeof(addr));
3146
3147         e1000_rar_set(hw, addr, index);
3148 }
3149
3150 static int
3151 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3152                                 struct rte_ether_addr *addr)
3153 {
3154         eth_igb_rar_clear(dev, 0);
3155         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3156
3157         return 0;
3158 }
3159 /*
3160  * Virtual Function operations
3161  */
3162 static void
3163 igbvf_intr_disable(struct e1000_hw *hw)
3164 {
3165         PMD_INIT_FUNC_TRACE();
3166
3167         /* Clear interrupt mask to stop from interrupts being generated */
3168         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3169
3170         E1000_WRITE_FLUSH(hw);
3171 }
3172
3173 static void
3174 igbvf_stop_adapter(struct rte_eth_dev *dev)
3175 {
3176         u32 reg_val;
3177         u16 i;
3178         struct rte_eth_dev_info dev_info;
3179         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3180
3181         memset(&dev_info, 0, sizeof(dev_info));
3182         eth_igbvf_infos_get(dev, &dev_info);
3183
3184         /* Clear interrupt mask to stop from interrupts being generated */
3185         igbvf_intr_disable(hw);
3186
3187         /* Clear any pending interrupts, flush previous writes */
3188         E1000_READ_REG(hw, E1000_EICR);
3189
3190         /* Disable the transmit unit.  Each queue must be disabled. */
3191         for (i = 0; i < dev_info.max_tx_queues; i++)
3192                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3193
3194         /* Disable the receive unit by stopping each queue */
3195         for (i = 0; i < dev_info.max_rx_queues; i++) {
3196                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3197                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3198                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3199                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3200                         ;
3201         }
3202
3203         /* flush all queues disables */
3204         E1000_WRITE_FLUSH(hw);
3205         msec_delay(2);
3206 }
3207
3208 static int eth_igbvf_link_update(struct e1000_hw *hw)
3209 {
3210         struct e1000_mbx_info *mbx = &hw->mbx;
3211         struct e1000_mac_info *mac = &hw->mac;
3212         int ret_val = E1000_SUCCESS;
3213
3214         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3215
3216         /*
3217          * We only want to run this if there has been a rst asserted.
3218          * in this case that could mean a link change, device reset,
3219          * or a virtual function reset
3220          */
3221
3222         /* If we were hit with a reset or timeout drop the link */
3223         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3224                 mac->get_link_status = TRUE;
3225
3226         if (!mac->get_link_status)
3227                 goto out;
3228
3229         /* if link status is down no point in checking to see if pf is up */
3230         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3231                 goto out;
3232
3233         /* if we passed all the tests above then the link is up and we no
3234          * longer need to check for link */
3235         mac->get_link_status = FALSE;
3236
3237 out:
3238         return ret_val;
3239 }
3240
3241
3242 static int
3243 igbvf_dev_configure(struct rte_eth_dev *dev)
3244 {
3245         struct rte_eth_conf* conf = &dev->data->dev_conf;
3246
3247         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3248                      dev->data->port_id);
3249
3250         /*
3251          * VF has no ability to enable/disable HW CRC
3252          * Keep the persistent behavior the same as Host PF
3253          */
3254 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3255         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3256                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3257                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3258         }
3259 #else
3260         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3261                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3262                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3263         }
3264 #endif
3265
3266         return 0;
3267 }
3268
3269 static int
3270 igbvf_dev_start(struct rte_eth_dev *dev)
3271 {
3272         struct e1000_hw *hw =
3273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274         struct e1000_adapter *adapter =
3275                 E1000_DEV_PRIVATE(dev->data->dev_private);
3276         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3277         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3278         int ret;
3279         uint32_t intr_vector = 0;
3280
3281         PMD_INIT_FUNC_TRACE();
3282
3283         hw->mac.ops.reset_hw(hw);
3284         adapter->stopped = 0;
3285
3286         /* Set all vfta */
3287         igbvf_set_vfta_all(dev,1);
3288
3289         eth_igbvf_tx_init(dev);
3290
3291         /* This can fail when allocating mbufs for descriptor rings */
3292         ret = eth_igbvf_rx_init(dev);
3293         if (ret) {
3294                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3295                 igb_dev_clear_queues(dev);
3296                 return ret;
3297         }
3298
3299         /* check and configure queue intr-vector mapping */
3300         if (rte_intr_cap_multiple(intr_handle) &&
3301             dev->data->dev_conf.intr_conf.rxq) {
3302                 intr_vector = dev->data->nb_rx_queues;
3303                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3304                 if (ret)
3305                         return ret;
3306         }
3307
3308         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3309                 intr_handle->intr_vec =
3310                         rte_zmalloc("intr_vec",
3311                                     dev->data->nb_rx_queues * sizeof(int), 0);
3312                 if (!intr_handle->intr_vec) {
3313                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3314                                      " intr_vec", dev->data->nb_rx_queues);
3315                         return -ENOMEM;
3316                 }
3317         }
3318
3319         eth_igbvf_configure_msix_intr(dev);
3320
3321         /* enable uio/vfio intr/eventfd mapping */
3322         rte_intr_enable(intr_handle);
3323
3324         /* resume enabled intr since hw reset */
3325         igbvf_intr_enable(dev);
3326
3327         return 0;
3328 }
3329
3330 static void
3331 igbvf_dev_stop(struct rte_eth_dev *dev)
3332 {
3333         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3335
3336         PMD_INIT_FUNC_TRACE();
3337
3338         igbvf_stop_adapter(dev);
3339
3340         /*
3341           * Clear what we set, but we still keep shadow_vfta to
3342           * restore after device starts
3343           */
3344         igbvf_set_vfta_all(dev,0);
3345
3346         igb_dev_clear_queues(dev);
3347
3348         /* disable intr eventfd mapping */
3349         rte_intr_disable(intr_handle);
3350
3351         /* Clean datapath event and queue/vec mapping */
3352         rte_intr_efd_disable(intr_handle);
3353         if (intr_handle->intr_vec) {
3354                 rte_free(intr_handle->intr_vec);
3355                 intr_handle->intr_vec = NULL;
3356         }
3357 }
3358
3359 static void
3360 igbvf_dev_close(struct rte_eth_dev *dev)
3361 {
3362         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363         struct e1000_adapter *adapter =
3364                 E1000_DEV_PRIVATE(dev->data->dev_private);
3365         struct rte_ether_addr addr;
3366
3367         PMD_INIT_FUNC_TRACE();
3368
3369         e1000_reset_hw(hw);
3370
3371         igbvf_dev_stop(dev);
3372         adapter->stopped = 1;
3373         igb_dev_free_queues(dev);
3374
3375         /**
3376          * reprogram the RAR with a zero mac address,
3377          * to ensure that the VF traffic goes to the PF
3378          * after stop, close and detach of the VF.
3379          **/
3380
3381         memset(&addr, 0, sizeof(addr));
3382         igbvf_default_mac_addr_set(dev, &addr);
3383 }
3384
3385 static void
3386 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3387 {
3388         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3389
3390         /* Set both unicast and multicast promisc */
3391         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3392 }
3393
3394 static void
3395 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3396 {
3397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398
3399         /* If in allmulticast mode leave multicast promisc */
3400         if (dev->data->all_multicast == 1)
3401                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3402         else
3403                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3404 }
3405
3406 static void
3407 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3408 {
3409         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3410
3411         /* In promiscuous mode multicast promisc already set */
3412         if (dev->data->promiscuous == 0)
3413                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3414 }
3415
3416 static void
3417 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3418 {
3419         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420
3421         /* In promiscuous mode leave multicast promisc enabled */
3422         if (dev->data->promiscuous == 0)
3423                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3424 }
3425
3426 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3427 {
3428         struct e1000_mbx_info *mbx = &hw->mbx;
3429         uint32_t msgbuf[2];
3430         s32 err;
3431
3432         /* After set vlan, vlan strip will also be enabled in igb driver*/
3433         msgbuf[0] = E1000_VF_SET_VLAN;
3434         msgbuf[1] = vid;
3435         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3436         if (on)
3437                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3438
3439         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3440         if (err)
3441                 goto mbx_err;
3442
3443         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3444         if (err)
3445                 goto mbx_err;
3446
3447         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3448         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3449                 err = -EINVAL;
3450
3451 mbx_err:
3452         return err;
3453 }
3454
3455 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3456 {
3457         struct e1000_hw *hw =
3458                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3459         struct e1000_vfta * shadow_vfta =
3460                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3461         int i = 0, j = 0, vfta = 0, mask = 1;
3462
3463         for (i = 0; i < IGB_VFTA_SIZE; i++){
3464                 vfta = shadow_vfta->vfta[i];
3465                 if(vfta){
3466                         mask = 1;
3467                         for (j = 0; j < 32; j++){
3468                                 if(vfta & mask)
3469                                         igbvf_set_vfta(hw,
3470                                                 (uint16_t)((i<<5)+j), on);
3471                                 mask<<=1;
3472                         }
3473                 }
3474         }
3475
3476 }
3477
3478 static int
3479 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3480 {
3481         struct e1000_hw *hw =
3482                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483         struct e1000_vfta * shadow_vfta =
3484                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3485         uint32_t vid_idx = 0;
3486         uint32_t vid_bit = 0;
3487         int ret = 0;
3488
3489         PMD_INIT_FUNC_TRACE();
3490
3491         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3492         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3493         if(ret){
3494                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3495                 return ret;
3496         }
3497         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3498         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3499
3500         /*Save what we set and retore it after device reset*/
3501         if (on)
3502                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3503         else
3504                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3505
3506         return 0;
3507 }
3508
3509 static int
3510 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3511 {
3512         struct e1000_hw *hw =
3513                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514
3515         /* index is not used by rar_set() */
3516         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3517         return 0;
3518 }
3519
3520
3521 static int
3522 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3523                         struct rte_eth_rss_reta_entry64 *reta_conf,
3524                         uint16_t reta_size)
3525 {
3526         uint8_t i, j, mask;
3527         uint32_t reta, r;
3528         uint16_t idx, shift;
3529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530
3531         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3532                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3533                         "(%d) doesn't match the number hardware can supported "
3534                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3535                 return -EINVAL;
3536         }
3537
3538         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3539                 idx = i / RTE_RETA_GROUP_SIZE;
3540                 shift = i % RTE_RETA_GROUP_SIZE;
3541                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3542                                                 IGB_4_BIT_MASK);
3543                 if (!mask)
3544                         continue;
3545                 if (mask == IGB_4_BIT_MASK)
3546                         r = 0;
3547                 else
3548                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3549                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3550                         if (mask & (0x1 << j))
3551                                 reta |= reta_conf[idx].reta[shift + j] <<
3552                                                         (CHAR_BIT * j);
3553                         else
3554                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3555                 }
3556                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3557         }
3558
3559         return 0;
3560 }
3561
3562 static int
3563 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3564                        struct rte_eth_rss_reta_entry64 *reta_conf,
3565                        uint16_t reta_size)
3566 {
3567         uint8_t i, j, mask;
3568         uint32_t reta;
3569         uint16_t idx, shift;
3570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571
3572         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3573                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3574                         "(%d) doesn't match the number hardware can supported "
3575                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3576                 return -EINVAL;
3577         }
3578
3579         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3580                 idx = i / RTE_RETA_GROUP_SIZE;
3581                 shift = i % RTE_RETA_GROUP_SIZE;
3582                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3583                                                 IGB_4_BIT_MASK);
3584                 if (!mask)
3585                         continue;
3586                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3587                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3588                         if (mask & (0x1 << j))
3589                                 reta_conf[idx].reta[shift + j] =
3590                                         ((reta >> (CHAR_BIT * j)) &
3591                                                 IGB_8_BIT_MASK);
3592                 }
3593         }
3594
3595         return 0;
3596 }
3597
3598 int
3599 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3600                         struct rte_eth_syn_filter *filter,
3601                         bool add)
3602 {
3603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3604         struct e1000_filter_info *filter_info =
3605                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3606         uint32_t synqf, rfctl;
3607
3608         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3609                 return -EINVAL;
3610
3611         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3612
3613         if (add) {
3614                 if (synqf & E1000_SYN_FILTER_ENABLE)
3615                         return -EINVAL;
3616
3617                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3618                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3619
3620                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3621                 if (filter->hig_pri)
3622                         rfctl |= E1000_RFCTL_SYNQFP;
3623                 else
3624                         rfctl &= ~E1000_RFCTL_SYNQFP;
3625
3626                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3627         } else {
3628                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3629                         return -ENOENT;
3630                 synqf = 0;
3631         }
3632
3633         filter_info->syn_info = synqf;
3634         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3635         E1000_WRITE_FLUSH(hw);
3636         return 0;
3637 }
3638
3639 static int
3640 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3641                         struct rte_eth_syn_filter *filter)
3642 {
3643         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644         uint32_t synqf, rfctl;
3645
3646         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3647         if (synqf & E1000_SYN_FILTER_ENABLE) {
3648                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3649                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3650                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3651                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3652                 return 0;
3653         }
3654
3655         return -ENOENT;
3656 }
3657
3658 static int
3659 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3660                         enum rte_filter_op filter_op,
3661                         void *arg)
3662 {
3663         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3664         int ret;
3665
3666         MAC_TYPE_FILTER_SUP(hw->mac.type);
3667
3668         if (filter_op == RTE_ETH_FILTER_NOP)
3669                 return 0;
3670
3671         if (arg == NULL) {
3672                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3673                             filter_op);
3674                 return -EINVAL;
3675         }
3676
3677         switch (filter_op) {
3678         case RTE_ETH_FILTER_ADD:
3679                 ret = eth_igb_syn_filter_set(dev,
3680                                 (struct rte_eth_syn_filter *)arg,
3681                                 TRUE);
3682                 break;
3683         case RTE_ETH_FILTER_DELETE:
3684                 ret = eth_igb_syn_filter_set(dev,
3685                                 (struct rte_eth_syn_filter *)arg,
3686                                 FALSE);
3687                 break;
3688         case RTE_ETH_FILTER_GET:
3689                 ret = eth_igb_syn_filter_get(dev,
3690                                 (struct rte_eth_syn_filter *)arg);
3691                 break;
3692         default:
3693                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3694                 ret = -EINVAL;
3695                 break;
3696         }
3697
3698         return ret;
3699 }
3700
3701 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3702 static inline int
3703 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3704                         struct e1000_2tuple_filter_info *filter_info)
3705 {
3706         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3707                 return -EINVAL;
3708         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3709                 return -EINVAL;  /* filter index is out of range. */
3710         if (filter->tcp_flags > TCP_FLAG_ALL)
3711                 return -EINVAL;  /* flags is invalid. */
3712
3713         switch (filter->dst_port_mask) {
3714         case UINT16_MAX:
3715                 filter_info->dst_port_mask = 0;
3716                 filter_info->dst_port = filter->dst_port;
3717                 break;
3718         case 0:
3719                 filter_info->dst_port_mask = 1;
3720                 break;
3721         default:
3722                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3723                 return -EINVAL;
3724         }
3725
3726         switch (filter->proto_mask) {
3727         case UINT8_MAX:
3728                 filter_info->proto_mask = 0;
3729                 filter_info->proto = filter->proto;
3730                 break;
3731         case 0:
3732                 filter_info->proto_mask = 1;
3733                 break;
3734         default:
3735                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3736                 return -EINVAL;
3737         }
3738
3739         filter_info->priority = (uint8_t)filter->priority;
3740         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3741                 filter_info->tcp_flags = filter->tcp_flags;
3742         else
3743                 filter_info->tcp_flags = 0;
3744
3745         return 0;
3746 }
3747
3748 static inline struct e1000_2tuple_filter *
3749 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3750                         struct e1000_2tuple_filter_info *key)
3751 {
3752         struct e1000_2tuple_filter *it;
3753
3754         TAILQ_FOREACH(it, filter_list, entries) {
3755                 if (memcmp(key, &it->filter_info,
3756                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3757                         return it;
3758                 }
3759         }
3760         return NULL;
3761 }
3762
3763 /* inject a igb 2tuple filter to HW */
3764 static inline void
3765 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3766                            struct e1000_2tuple_filter *filter)
3767 {
3768         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3770         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3771         int i;
3772
3773         i = filter->index;
3774         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3775         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3776                 imir |= E1000_IMIR_PORT_BP;
3777         else
3778                 imir &= ~E1000_IMIR_PORT_BP;
3779
3780         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3781
3782         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3783         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3784         ttqf |= (uint32_t)(filter->filter_info.proto &
3785                                                 E1000_TTQF_PROTOCOL_MASK);
3786         if (filter->filter_info.proto_mask == 0)
3787                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3788
3789         /* tcp flags bits setting. */
3790         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3791                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3792                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3793                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3795                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3796                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3797                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3798                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3799                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3800                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3801                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3802                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3803         } else {
3804                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3805         }
3806         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3807         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3808         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3809 }
3810
3811 /*
3812  * igb_add_2tuple_filter - add a 2tuple filter
3813  *
3814  * @param
3815  * dev: Pointer to struct rte_eth_dev.
3816  * ntuple_filter: ponter to the filter that will be added.
3817  *
3818  * @return
3819  *    - On success, zero.
3820  *    - On failure, a negative value.
3821  */
3822 static int
3823 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3824                         struct rte_eth_ntuple_filter *ntuple_filter)
3825 {
3826         struct e1000_filter_info *filter_info =
3827                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828         struct e1000_2tuple_filter *filter;
3829         int i, ret;
3830
3831         filter = rte_zmalloc("e1000_2tuple_filter",
3832                         sizeof(struct e1000_2tuple_filter), 0);
3833         if (filter == NULL)
3834                 return -ENOMEM;
3835
3836         ret = ntuple_filter_to_2tuple(ntuple_filter,
3837                                       &filter->filter_info);
3838         if (ret < 0) {
3839                 rte_free(filter);
3840                 return ret;
3841         }
3842         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3843                                          &filter->filter_info) != NULL) {
3844                 PMD_DRV_LOG(ERR, "filter exists.");
3845                 rte_free(filter);
3846                 return -EEXIST;
3847         }
3848         filter->queue = ntuple_filter->queue;
3849
3850         /*
3851          * look for an unused 2tuple filter index,
3852          * and insert the filter to list.
3853          */
3854         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3855                 if (!(filter_info->twotuple_mask & (1 << i))) {
3856                         filter_info->twotuple_mask |= 1 << i;
3857                         filter->index = i;
3858                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3859                                           filter,
3860                                           entries);
3861                         break;
3862                 }
3863         }
3864         if (i >= E1000_MAX_TTQF_FILTERS) {
3865                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3866                 rte_free(filter);
3867                 return -ENOSYS;
3868         }
3869
3870         igb_inject_2uple_filter(dev, filter);
3871         return 0;
3872 }
3873
3874 int
3875 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3876                         struct e1000_2tuple_filter *filter)
3877 {
3878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct e1000_filter_info *filter_info =
3880                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3881
3882         filter_info->twotuple_mask &= ~(1 << filter->index);
3883         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3884         rte_free(filter);
3885
3886         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3887         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3888         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3889         return 0;
3890 }
3891
3892 /*
3893  * igb_remove_2tuple_filter - remove a 2tuple filter
3894  *
3895  * @param
3896  * dev: Pointer to struct rte_eth_dev.
3897  * ntuple_filter: ponter to the filter that will be removed.
3898  *
3899  * @return
3900  *    - On success, zero.
3901  *    - On failure, a negative value.
3902  */
3903 static int
3904 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3905                         struct rte_eth_ntuple_filter *ntuple_filter)
3906 {
3907         struct e1000_filter_info *filter_info =
3908                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3909         struct e1000_2tuple_filter_info filter_2tuple;
3910         struct e1000_2tuple_filter *filter;
3911         int ret;
3912
3913         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3914         ret = ntuple_filter_to_2tuple(ntuple_filter,
3915                                       &filter_2tuple);
3916         if (ret < 0)
3917                 return ret;
3918
3919         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3920                                          &filter_2tuple);
3921         if (filter == NULL) {
3922                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3923                 return -ENOENT;
3924         }
3925
3926         igb_delete_2tuple_filter(dev, filter);
3927
3928         return 0;
3929 }
3930
3931 /* inject a igb flex filter to HW */
3932 static inline void
3933 igb_inject_flex_filter(struct rte_eth_dev *dev,
3934                            struct e1000_flex_filter *filter)
3935 {
3936         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         uint32_t wufc, queueing;
3938         uint32_t reg_off;
3939         uint8_t i, j = 0;
3940
3941         wufc = E1000_READ_REG(hw, E1000_WUFC);
3942         if (filter->index < E1000_MAX_FHFT)
3943                 reg_off = E1000_FHFT(filter->index);
3944         else
3945                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3946
3947         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3948                         (E1000_WUFC_FLX0 << filter->index));
3949         queueing = filter->filter_info.len |
3950                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3951                 (filter->filter_info.priority <<
3952                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3953         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3954                         queueing);
3955
3956         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3957                 E1000_WRITE_REG(hw, reg_off,
3958                                 filter->filter_info.dwords[j]);
3959                 reg_off += sizeof(uint32_t);
3960                 E1000_WRITE_REG(hw, reg_off,
3961                                 filter->filter_info.dwords[++j]);
3962                 reg_off += sizeof(uint32_t);
3963                 E1000_WRITE_REG(hw, reg_off,
3964                         (uint32_t)filter->filter_info.mask[i]);
3965                 reg_off += sizeof(uint32_t) * 2;
3966                 ++j;
3967         }
3968 }
3969
3970 static inline struct e1000_flex_filter *
3971 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3972                         struct e1000_flex_filter_info *key)
3973 {
3974         struct e1000_flex_filter *it;
3975
3976         TAILQ_FOREACH(it, filter_list, entries) {
3977                 if (memcmp(key, &it->filter_info,
3978                         sizeof(struct e1000_flex_filter_info)) == 0)
3979                         return it;
3980         }
3981
3982         return NULL;
3983 }
3984
3985 /* remove a flex byte filter
3986  * @param
3987  * dev: Pointer to struct rte_eth_dev.
3988  * filter: the pointer of the filter will be removed.
3989  */
3990 void
3991 igb_remove_flex_filter(struct rte_eth_dev *dev,
3992                         struct e1000_flex_filter *filter)
3993 {
3994         struct e1000_filter_info *filter_info =
3995                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3996         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3997         uint32_t wufc, i;
3998         uint32_t reg_off;
3999
4000         wufc = E1000_READ_REG(hw, E1000_WUFC);
4001         if (filter->index < E1000_MAX_FHFT)
4002                 reg_off = E1000_FHFT(filter->index);
4003         else
4004                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4005
4006         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4007                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4008
4009         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4010                 (~(E1000_WUFC_FLX0 << filter->index)));
4011
4012         filter_info->flex_mask &= ~(1 << filter->index);
4013         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4014         rte_free(filter);
4015 }
4016
4017 int
4018 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4019                         struct rte_eth_flex_filter *filter,
4020                         bool add)
4021 {
4022         struct e1000_filter_info *filter_info =
4023                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4024         struct e1000_flex_filter *flex_filter, *it;
4025         uint32_t mask;
4026         uint8_t shift, i;
4027
4028         flex_filter = rte_zmalloc("e1000_flex_filter",
4029                         sizeof(struct e1000_flex_filter), 0);
4030         if (flex_filter == NULL)
4031                 return -ENOMEM;
4032
4033         flex_filter->filter_info.len = filter->len;
4034         flex_filter->filter_info.priority = filter->priority;
4035         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4036         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4037                 mask = 0;
4038                 /* reverse bits in flex filter's mask*/
4039                 for (shift = 0; shift < CHAR_BIT; shift++) {
4040                         if (filter->mask[i] & (0x01 << shift))
4041                                 mask |= (0x80 >> shift);
4042                 }
4043                 flex_filter->filter_info.mask[i] = mask;
4044         }
4045
4046         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4047                                 &flex_filter->filter_info);
4048         if (it == NULL && !add) {
4049                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4050                 rte_free(flex_filter);
4051                 return -ENOENT;
4052         }
4053         if (it != NULL && add) {
4054                 PMD_DRV_LOG(ERR, "filter exists.");
4055                 rte_free(flex_filter);
4056                 return -EEXIST;
4057         }
4058
4059         if (add) {
4060                 flex_filter->queue = filter->queue;
4061                 /*
4062                  * look for an unused flex filter index
4063                  * and insert the filter into the list.
4064                  */
4065                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4066                         if (!(filter_info->flex_mask & (1 << i))) {
4067                                 filter_info->flex_mask |= 1 << i;
4068                                 flex_filter->index = i;
4069                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4070                                         flex_filter,
4071                                         entries);
4072                                 break;
4073                         }
4074                 }
4075                 if (i >= E1000_MAX_FLEX_FILTERS) {
4076                         PMD_DRV_LOG(ERR, "flex filters are full.");
4077                         rte_free(flex_filter);
4078                         return -ENOSYS;
4079                 }
4080
4081                 igb_inject_flex_filter(dev, flex_filter);
4082
4083         } else {
4084                 igb_remove_flex_filter(dev, it);
4085                 rte_free(flex_filter);
4086         }
4087
4088         return 0;
4089 }
4090
4091 static int
4092 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4093                         struct rte_eth_flex_filter *filter)
4094 {
4095         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4096         struct e1000_filter_info *filter_info =
4097                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4098         struct e1000_flex_filter flex_filter, *it;
4099         uint32_t wufc, queueing, wufc_en = 0;
4100
4101         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4102         flex_filter.filter_info.len = filter->len;
4103         flex_filter.filter_info.priority = filter->priority;
4104         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4105         memcpy(flex_filter.filter_info.mask, filter->mask,
4106                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4107
4108         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4109                                 &flex_filter.filter_info);
4110         if (it == NULL) {
4111                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4112                 return -ENOENT;
4113         }
4114
4115         wufc = E1000_READ_REG(hw, E1000_WUFC);
4116         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4117
4118         if ((wufc & wufc_en) == wufc_en) {
4119                 uint32_t reg_off = 0;
4120                 if (it->index < E1000_MAX_FHFT)
4121                         reg_off = E1000_FHFT(it->index);
4122                 else
4123                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4124
4125                 queueing = E1000_READ_REG(hw,
4126                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4127                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4128                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4129                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4130                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4131                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4132                 return 0;
4133         }
4134         return -ENOENT;
4135 }
4136
4137 static int
4138 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4139                         enum rte_filter_op filter_op,
4140                         void *arg)
4141 {
4142         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4143         struct rte_eth_flex_filter *filter;
4144         int ret = 0;
4145
4146         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4147
4148         if (filter_op == RTE_ETH_FILTER_NOP)
4149                 return ret;
4150
4151         if (arg == NULL) {
4152                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4153                             filter_op);
4154                 return -EINVAL;
4155         }
4156
4157         filter = (struct rte_eth_flex_filter *)arg;
4158         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4159             || filter->len % sizeof(uint64_t) != 0) {
4160                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4161                 return -EINVAL;
4162         }
4163         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4164                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4165                 return -EINVAL;
4166         }
4167
4168         switch (filter_op) {
4169         case RTE_ETH_FILTER_ADD:
4170                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4171                 break;
4172         case RTE_ETH_FILTER_DELETE:
4173                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4174                 break;
4175         case RTE_ETH_FILTER_GET:
4176                 ret = eth_igb_get_flex_filter(dev, filter);
4177                 break;
4178         default:
4179                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4180                 ret = -EINVAL;
4181                 break;
4182         }
4183
4184         return ret;
4185 }
4186
4187 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4188 static inline int
4189 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4190                         struct e1000_5tuple_filter_info *filter_info)
4191 {
4192         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4193                 return -EINVAL;
4194         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4195                 return -EINVAL;  /* filter index is out of range. */
4196         if (filter->tcp_flags > TCP_FLAG_ALL)
4197                 return -EINVAL;  /* flags is invalid. */
4198
4199         switch (filter->dst_ip_mask) {
4200         case UINT32_MAX:
4201                 filter_info->dst_ip_mask = 0;
4202                 filter_info->dst_ip = filter->dst_ip;
4203                 break;
4204         case 0:
4205                 filter_info->dst_ip_mask = 1;
4206                 break;
4207         default:
4208                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4209                 return -EINVAL;
4210         }
4211
4212         switch (filter->src_ip_mask) {
4213         case UINT32_MAX:
4214                 filter_info->src_ip_mask = 0;
4215                 filter_info->src_ip = filter->src_ip;
4216                 break;
4217         case 0:
4218                 filter_info->src_ip_mask = 1;
4219                 break;
4220         default:
4221                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4222                 return -EINVAL;
4223         }
4224
4225         switch (filter->dst_port_mask) {
4226         case UINT16_MAX:
4227                 filter_info->dst_port_mask = 0;
4228                 filter_info->dst_port = filter->dst_port;
4229                 break;
4230         case 0:
4231                 filter_info->dst_port_mask = 1;
4232                 break;
4233         default:
4234                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4235                 return -EINVAL;
4236         }
4237
4238         switch (filter->src_port_mask) {
4239         case UINT16_MAX:
4240                 filter_info->src_port_mask = 0;
4241                 filter_info->src_port = filter->src_port;
4242                 break;
4243         case 0:
4244                 filter_info->src_port_mask = 1;
4245                 break;
4246         default:
4247                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4248                 return -EINVAL;
4249         }
4250
4251         switch (filter->proto_mask) {
4252         case UINT8_MAX:
4253                 filter_info->proto_mask = 0;
4254                 filter_info->proto = filter->proto;
4255                 break;
4256         case 0:
4257                 filter_info->proto_mask = 1;
4258                 break;
4259         default:
4260                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4261                 return -EINVAL;
4262         }
4263
4264         filter_info->priority = (uint8_t)filter->priority;
4265         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4266                 filter_info->tcp_flags = filter->tcp_flags;
4267         else
4268                 filter_info->tcp_flags = 0;
4269
4270         return 0;
4271 }
4272
4273 static inline struct e1000_5tuple_filter *
4274 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4275                         struct e1000_5tuple_filter_info *key)
4276 {
4277         struct e1000_5tuple_filter *it;
4278
4279         TAILQ_FOREACH(it, filter_list, entries) {
4280                 if (memcmp(key, &it->filter_info,
4281                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4282                         return it;
4283                 }
4284         }
4285         return NULL;
4286 }
4287
4288 /* inject a igb 5-tuple filter to HW */
4289 static inline void
4290 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4291                            struct e1000_5tuple_filter *filter)
4292 {
4293         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4294         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4295         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4296         uint8_t i;
4297
4298         i = filter->index;
4299         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4300         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4301                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4302         if (filter->filter_info.dst_ip_mask == 0)
4303                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4304         if (filter->filter_info.src_port_mask == 0)
4305                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4306         if (filter->filter_info.proto_mask == 0)
4307                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4308         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4309                 E1000_FTQF_QUEUE_MASK;
4310         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4311         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4312         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4313         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4314
4315         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4316         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4317
4318         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4319         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4320                 imir |= E1000_IMIR_PORT_BP;
4321         else
4322                 imir &= ~E1000_IMIR_PORT_BP;
4323         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4324
4325         /* tcp flags bits setting. */
4326         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4327                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4328                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4329                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4330                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4331                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4332                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4333                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4334                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4335                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4336                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4337                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4338                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4339         } else {
4340                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4341         }
4342         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4343         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4344 }
4345
4346 /*
4347  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4348  *
4349  * @param
4350  * dev: Pointer to struct rte_eth_dev.
4351  * ntuple_filter: ponter to the filter that will be added.
4352  *
4353  * @return
4354  *    - On success, zero.
4355  *    - On failure, a negative value.
4356  */
4357 static int
4358 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4359                         struct rte_eth_ntuple_filter *ntuple_filter)
4360 {
4361         struct e1000_filter_info *filter_info =
4362                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4363         struct e1000_5tuple_filter *filter;
4364         uint8_t i;
4365         int ret;
4366
4367         filter = rte_zmalloc("e1000_5tuple_filter",
4368                         sizeof(struct e1000_5tuple_filter), 0);
4369         if (filter == NULL)
4370                 return -ENOMEM;
4371
4372         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4373                                             &filter->filter_info);
4374         if (ret < 0) {
4375                 rte_free(filter);
4376                 return ret;
4377         }
4378
4379         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4380                                          &filter->filter_info) != NULL) {
4381                 PMD_DRV_LOG(ERR, "filter exists.");
4382                 rte_free(filter);
4383                 return -EEXIST;
4384         }
4385         filter->queue = ntuple_filter->queue;
4386
4387         /*
4388          * look for an unused 5tuple filter index,
4389          * and insert the filter to list.
4390          */
4391         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4392                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4393                         filter_info->fivetuple_mask |= 1 << i;
4394                         filter->index = i;
4395                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4396                                           filter,
4397                                           entries);
4398                         break;
4399                 }
4400         }
4401         if (i >= E1000_MAX_FTQF_FILTERS) {
4402                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4403                 rte_free(filter);
4404                 return -ENOSYS;
4405         }
4406
4407         igb_inject_5tuple_filter_82576(dev, filter);
4408         return 0;
4409 }
4410
4411 int
4412 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4413                                 struct e1000_5tuple_filter *filter)
4414 {
4415         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416         struct e1000_filter_info *filter_info =
4417                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4418
4419         filter_info->fivetuple_mask &= ~(1 << filter->index);
4420         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4421         rte_free(filter);
4422
4423         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4424                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4425         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4426         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4427         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4428         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4429         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4430         return 0;
4431 }
4432
4433 /*
4434  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4435  *
4436  * @param
4437  * dev: Pointer to struct rte_eth_dev.
4438  * ntuple_filter: ponter to the filter that will be removed.
4439  *
4440  * @return
4441  *    - On success, zero.
4442  *    - On failure, a negative value.
4443  */
4444 static int
4445 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4446                                 struct rte_eth_ntuple_filter *ntuple_filter)
4447 {
4448         struct e1000_filter_info *filter_info =
4449                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4450         struct e1000_5tuple_filter_info filter_5tuple;
4451         struct e1000_5tuple_filter *filter;
4452         int ret;
4453
4454         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4455         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4456                                             &filter_5tuple);
4457         if (ret < 0)
4458                 return ret;
4459
4460         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4461                                          &filter_5tuple);
4462         if (filter == NULL) {
4463                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4464                 return -ENOENT;
4465         }
4466
4467         igb_delete_5tuple_filter_82576(dev, filter);
4468
4469         return 0;
4470 }
4471
4472 static int
4473 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4474 {
4475         uint32_t rctl;
4476         struct e1000_hw *hw;
4477         struct rte_eth_dev_info dev_info;
4478         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4479
4480         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481
4482 #ifdef RTE_LIBRTE_82571_SUPPORT
4483         /* XXX: not bigger than max_rx_pktlen */
4484         if (hw->mac.type == e1000_82571)
4485                 return -ENOTSUP;
4486 #endif
4487         eth_igb_infos_get(dev, &dev_info);
4488
4489         /* check that mtu is within the allowed range */
4490         if (mtu < RTE_ETHER_MIN_MTU ||
4491                         frame_size > dev_info.max_rx_pktlen)
4492                 return -EINVAL;
4493
4494         /* refuse mtu that requires the support of scattered packets when this
4495          * feature has not been enabled before. */
4496         if (!dev->data->scattered_rx &&
4497             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4498                 return -EINVAL;
4499
4500         rctl = E1000_READ_REG(hw, E1000_RCTL);
4501
4502         /* switch to jumbo mode if needed */
4503         if (frame_size > RTE_ETHER_MAX_LEN) {
4504                 dev->data->dev_conf.rxmode.offloads |=
4505                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4506                 rctl |= E1000_RCTL_LPE;
4507         } else {
4508                 dev->data->dev_conf.rxmode.offloads &=
4509                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4510                 rctl &= ~E1000_RCTL_LPE;
4511         }
4512         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4513
4514         /* update max frame size */
4515         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4516
4517         E1000_WRITE_REG(hw, E1000_RLPML,
4518                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4519
4520         return 0;
4521 }
4522
4523 /*
4524  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4525  *
4526  * @param
4527  * dev: Pointer to struct rte_eth_dev.
4528  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4529  * add: if true, add filter, if false, remove filter
4530  *
4531  * @return
4532  *    - On success, zero.
4533  *    - On failure, a negative value.
4534  */
4535 int
4536 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4537                         struct rte_eth_ntuple_filter *ntuple_filter,
4538                         bool add)
4539 {
4540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         int ret;
4542
4543         switch (ntuple_filter->flags) {
4544         case RTE_5TUPLE_FLAGS:
4545         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4546                 if (hw->mac.type != e1000_82576)
4547                         return -ENOTSUP;
4548                 if (add)
4549                         ret = igb_add_5tuple_filter_82576(dev,
4550                                                           ntuple_filter);
4551                 else
4552                         ret = igb_remove_5tuple_filter_82576(dev,
4553                                                              ntuple_filter);
4554                 break;
4555         case RTE_2TUPLE_FLAGS:
4556         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4557                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4558                         hw->mac.type != e1000_i210 &&
4559                         hw->mac.type != e1000_i211)
4560                         return -ENOTSUP;
4561                 if (add)
4562                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4563                 else
4564                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4565                 break;
4566         default:
4567                 ret = -EINVAL;
4568                 break;
4569         }
4570
4571         return ret;
4572 }
4573
4574 /*
4575  * igb_get_ntuple_filter - get a ntuple filter
4576  *
4577  * @param
4578  * dev: Pointer to struct rte_eth_dev.
4579  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4580  *
4581  * @return
4582  *    - On success, zero.
4583  *    - On failure, a negative value.
4584  */
4585 static int
4586 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4587                         struct rte_eth_ntuple_filter *ntuple_filter)
4588 {
4589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590         struct e1000_filter_info *filter_info =
4591                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4592         struct e1000_5tuple_filter_info filter_5tuple;
4593         struct e1000_2tuple_filter_info filter_2tuple;
4594         struct e1000_5tuple_filter *p_5tuple_filter;
4595         struct e1000_2tuple_filter *p_2tuple_filter;
4596         int ret;
4597
4598         switch (ntuple_filter->flags) {
4599         case RTE_5TUPLE_FLAGS:
4600         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4601                 if (hw->mac.type != e1000_82576)
4602                         return -ENOTSUP;
4603                 memset(&filter_5tuple,
4604                         0,
4605                         sizeof(struct e1000_5tuple_filter_info));
4606                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4607                                                     &filter_5tuple);
4608                 if (ret < 0)
4609                         return ret;
4610                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4611                                         &filter_info->fivetuple_list,
4612                                         &filter_5tuple);
4613                 if (p_5tuple_filter == NULL) {
4614                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4615                         return -ENOENT;
4616                 }
4617                 ntuple_filter->queue = p_5tuple_filter->queue;
4618                 break;
4619         case RTE_2TUPLE_FLAGS:
4620         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4621                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4622                         return -ENOTSUP;
4623                 memset(&filter_2tuple,
4624                         0,
4625                         sizeof(struct e1000_2tuple_filter_info));
4626                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4627                 if (ret < 0)
4628                         return ret;
4629                 p_2tuple_filter = igb_2tuple_filter_lookup(
4630                                         &filter_info->twotuple_list,
4631                                         &filter_2tuple);
4632                 if (p_2tuple_filter == NULL) {
4633                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4634                         return -ENOENT;
4635                 }
4636                 ntuple_filter->queue = p_2tuple_filter->queue;
4637                 break;
4638         default:
4639                 ret = -EINVAL;
4640                 break;
4641         }
4642
4643         return 0;
4644 }
4645
4646 /*
4647  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4648  * @dev: pointer to rte_eth_dev structure
4649  * @filter_op:operation will be taken.
4650  * @arg: a pointer to specific structure corresponding to the filter_op
4651  */
4652 static int
4653 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4654                                 enum rte_filter_op filter_op,
4655                                 void *arg)
4656 {
4657         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658         int ret;
4659
4660         MAC_TYPE_FILTER_SUP(hw->mac.type);
4661
4662         if (filter_op == RTE_ETH_FILTER_NOP)
4663                 return 0;
4664
4665         if (arg == NULL) {
4666                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4667                             filter_op);
4668                 return -EINVAL;
4669         }
4670
4671         switch (filter_op) {
4672         case RTE_ETH_FILTER_ADD:
4673                 ret = igb_add_del_ntuple_filter(dev,
4674                         (struct rte_eth_ntuple_filter *)arg,
4675                         TRUE);
4676                 break;
4677         case RTE_ETH_FILTER_DELETE:
4678                 ret = igb_add_del_ntuple_filter(dev,
4679                         (struct rte_eth_ntuple_filter *)arg,
4680                         FALSE);
4681                 break;
4682         case RTE_ETH_FILTER_GET:
4683                 ret = igb_get_ntuple_filter(dev,
4684                         (struct rte_eth_ntuple_filter *)arg);
4685                 break;
4686         default:
4687                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4688                 ret = -EINVAL;
4689                 break;
4690         }
4691         return ret;
4692 }
4693
4694 static inline int
4695 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4696                         uint16_t ethertype)
4697 {
4698         int i;
4699
4700         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4701                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4702                     (filter_info->ethertype_mask & (1 << i)))
4703                         return i;
4704         }
4705         return -1;
4706 }
4707
4708 static inline int
4709 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4710                         uint16_t ethertype, uint32_t etqf)
4711 {
4712         int i;
4713
4714         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4715                 if (!(filter_info->ethertype_mask & (1 << i))) {
4716                         filter_info->ethertype_mask |= 1 << i;
4717                         filter_info->ethertype_filters[i].ethertype = ethertype;
4718                         filter_info->ethertype_filters[i].etqf = etqf;
4719                         return i;
4720                 }
4721         }
4722         return -1;
4723 }
4724
4725 int
4726 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4727                         uint8_t idx)
4728 {
4729         if (idx >= E1000_MAX_ETQF_FILTERS)
4730                 return -1;
4731         filter_info->ethertype_mask &= ~(1 << idx);
4732         filter_info->ethertype_filters[idx].ethertype = 0;
4733         filter_info->ethertype_filters[idx].etqf = 0;
4734         return idx;
4735 }
4736
4737
4738 int
4739 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4740                         struct rte_eth_ethertype_filter *filter,
4741                         bool add)
4742 {
4743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         struct e1000_filter_info *filter_info =
4745                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4746         uint32_t etqf = 0;
4747         int ret;
4748
4749         if (filter->ether_type == RTE_ETHER_TYPE_IPv4 ||
4750                 filter->ether_type == RTE_ETHER_TYPE_IPv6) {
4751                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4752                         " ethertype filter.", filter->ether_type);
4753                 return -EINVAL;
4754         }
4755
4756         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4757                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4758                 return -EINVAL;
4759         }
4760         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4761                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4762                 return -EINVAL;
4763         }
4764
4765         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4766         if (ret >= 0 && add) {
4767                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4768                             filter->ether_type);
4769                 return -EEXIST;
4770         }
4771         if (ret < 0 && !add) {
4772                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4773                             filter->ether_type);
4774                 return -ENOENT;
4775         }
4776
4777         if (add) {
4778                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4779                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4780                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4781                 ret = igb_ethertype_filter_insert(filter_info,
4782                                 filter->ether_type, etqf);
4783                 if (ret < 0) {
4784                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4785                         return -ENOSYS;
4786                 }
4787         } else {
4788                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4789                 if (ret < 0)
4790                         return -ENOSYS;
4791         }
4792         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4793         E1000_WRITE_FLUSH(hw);
4794
4795         return 0;
4796 }
4797
4798 static int
4799 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4800                         struct rte_eth_ethertype_filter *filter)
4801 {
4802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4803         struct e1000_filter_info *filter_info =
4804                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4805         uint32_t etqf;
4806         int ret;
4807
4808         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4809         if (ret < 0) {
4810                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4811                             filter->ether_type);
4812                 return -ENOENT;
4813         }
4814
4815         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4816         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4817                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4818                 filter->flags = 0;
4819                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4820                                 E1000_ETQF_QUEUE_SHIFT;
4821                 return 0;
4822         }
4823
4824         return -ENOENT;
4825 }
4826
4827 /*
4828  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4829  * @dev: pointer to rte_eth_dev structure
4830  * @filter_op:operation will be taken.
4831  * @arg: a pointer to specific structure corresponding to the filter_op
4832  */
4833 static int
4834 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4835                                 enum rte_filter_op filter_op,
4836                                 void *arg)
4837 {
4838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         int ret;
4840
4841         MAC_TYPE_FILTER_SUP(hw->mac.type);
4842
4843         if (filter_op == RTE_ETH_FILTER_NOP)
4844                 return 0;
4845
4846         if (arg == NULL) {
4847                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4848                             filter_op);
4849                 return -EINVAL;
4850         }
4851
4852         switch (filter_op) {
4853         case RTE_ETH_FILTER_ADD:
4854                 ret = igb_add_del_ethertype_filter(dev,
4855                         (struct rte_eth_ethertype_filter *)arg,
4856                         TRUE);
4857                 break;
4858         case RTE_ETH_FILTER_DELETE:
4859                 ret = igb_add_del_ethertype_filter(dev,
4860                         (struct rte_eth_ethertype_filter *)arg,
4861                         FALSE);
4862                 break;
4863         case RTE_ETH_FILTER_GET:
4864                 ret = igb_get_ethertype_filter(dev,
4865                         (struct rte_eth_ethertype_filter *)arg);
4866                 break;
4867         default:
4868                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4869                 ret = -EINVAL;
4870                 break;
4871         }
4872         return ret;
4873 }
4874
4875 static int
4876 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4877                      enum rte_filter_type filter_type,
4878                      enum rte_filter_op filter_op,
4879                      void *arg)
4880 {
4881         int ret = 0;
4882
4883         switch (filter_type) {
4884         case RTE_ETH_FILTER_NTUPLE:
4885                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4886                 break;
4887         case RTE_ETH_FILTER_ETHERTYPE:
4888                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4889                 break;
4890         case RTE_ETH_FILTER_SYN:
4891                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4892                 break;
4893         case RTE_ETH_FILTER_FLEXIBLE:
4894                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4895                 break;
4896         case RTE_ETH_FILTER_GENERIC:
4897                 if (filter_op != RTE_ETH_FILTER_GET)
4898                         return -EINVAL;
4899                 *(const void **)arg = &igb_flow_ops;
4900                 break;
4901         default:
4902                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4903                                                         filter_type);
4904                 break;
4905         }
4906
4907         return ret;
4908 }
4909
4910 static int
4911 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4912                          struct rte_ether_addr *mc_addr_set,
4913                          uint32_t nb_mc_addr)
4914 {
4915         struct e1000_hw *hw;
4916
4917         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4919         return 0;
4920 }
4921
4922 static uint64_t
4923 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4924 {
4925         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926         uint64_t systime_cycles;
4927
4928         switch (hw->mac.type) {
4929         case e1000_i210:
4930         case e1000_i211:
4931                 /*
4932                  * Need to read System Time Residue Register to be able
4933                  * to read the other two registers.
4934                  */
4935                 E1000_READ_REG(hw, E1000_SYSTIMR);
4936                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4937                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4938                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4939                                 * NSEC_PER_SEC;
4940                 break;
4941         case e1000_82580:
4942         case e1000_i350:
4943         case e1000_i354:
4944                 /*
4945                  * Need to read System Time Residue Register to be able
4946                  * to read the other two registers.
4947                  */
4948                 E1000_READ_REG(hw, E1000_SYSTIMR);
4949                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4950                 /* Only the 8 LSB are valid. */
4951                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4952                                 & 0xff) << 32;
4953                 break;
4954         default:
4955                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4956                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4957                                 << 32;
4958                 break;
4959         }
4960
4961         return systime_cycles;
4962 }
4963
4964 static uint64_t
4965 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4966 {
4967         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968         uint64_t rx_tstamp_cycles;
4969
4970         switch (hw->mac.type) {
4971         case e1000_i210:
4972         case e1000_i211:
4973                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4974                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4975                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4976                                 * NSEC_PER_SEC;
4977                 break;
4978         case e1000_82580:
4979         case e1000_i350:
4980         case e1000_i354:
4981                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4982                 /* Only the 8 LSB are valid. */
4983                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4984                                 & 0xff) << 32;
4985                 break;
4986         default:
4987                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4988                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4989                                 << 32;
4990                 break;
4991         }
4992
4993         return rx_tstamp_cycles;
4994 }
4995
4996 static uint64_t
4997 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4998 {
4999         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         uint64_t tx_tstamp_cycles;
5001
5002         switch (hw->mac.type) {
5003         case e1000_i210:
5004         case e1000_i211:
5005                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5006                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5007                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5008                                 * NSEC_PER_SEC;
5009                 break;
5010         case e1000_82580:
5011         case e1000_i350:
5012         case e1000_i354:
5013                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5014                 /* Only the 8 LSB are valid. */
5015                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5016                                 & 0xff) << 32;
5017                 break;
5018         default:
5019                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5020                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5021                                 << 32;
5022                 break;
5023         }
5024
5025         return tx_tstamp_cycles;
5026 }
5027
5028 static void
5029 igb_start_timecounters(struct rte_eth_dev *dev)
5030 {
5031         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032         struct e1000_adapter *adapter =
5033                 (struct e1000_adapter *)dev->data->dev_private;
5034         uint32_t incval = 1;
5035         uint32_t shift = 0;
5036         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5037
5038         switch (hw->mac.type) {
5039         case e1000_82580:
5040         case e1000_i350:
5041         case e1000_i354:
5042                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5043                 mask = (1ULL << 40) - 1;
5044                 /* fall-through */
5045         case e1000_i210:
5046         case e1000_i211:
5047                 /*
5048                  * Start incrementing the register
5049                  * used to timestamp PTP packets.
5050                  */
5051                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5052                 break;
5053         case e1000_82576:
5054                 incval = E1000_INCVALUE_82576;
5055                 shift = IGB_82576_TSYNC_SHIFT;
5056                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5057                                 E1000_INCPERIOD_82576 | incval);
5058                 break;
5059         default:
5060                 /* Not supported */
5061                 return;
5062         }
5063
5064         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5065         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5066         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5067
5068         adapter->systime_tc.cc_mask = mask;
5069         adapter->systime_tc.cc_shift = shift;
5070         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5071
5072         adapter->rx_tstamp_tc.cc_mask = mask;
5073         adapter->rx_tstamp_tc.cc_shift = shift;
5074         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5075
5076         adapter->tx_tstamp_tc.cc_mask = mask;
5077         adapter->tx_tstamp_tc.cc_shift = shift;
5078         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5079 }
5080
5081 static int
5082 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5083 {
5084         struct e1000_adapter *adapter =
5085                         (struct e1000_adapter *)dev->data->dev_private;
5086
5087         adapter->systime_tc.nsec += delta;
5088         adapter->rx_tstamp_tc.nsec += delta;
5089         adapter->tx_tstamp_tc.nsec += delta;
5090
5091         return 0;
5092 }
5093
5094 static int
5095 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5096 {
5097         uint64_t ns;
5098         struct e1000_adapter *adapter =
5099                         (struct e1000_adapter *)dev->data->dev_private;
5100
5101         ns = rte_timespec_to_ns(ts);
5102
5103         /* Set the timecounters to a new value. */
5104         adapter->systime_tc.nsec = ns;
5105         adapter->rx_tstamp_tc.nsec = ns;
5106         adapter->tx_tstamp_tc.nsec = ns;
5107
5108         return 0;
5109 }
5110
5111 static int
5112 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5113 {
5114         uint64_t ns, systime_cycles;
5115         struct e1000_adapter *adapter =
5116                         (struct e1000_adapter *)dev->data->dev_private;
5117
5118         systime_cycles = igb_read_systime_cyclecounter(dev);
5119         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5120         *ts = rte_ns_to_timespec(ns);
5121
5122         return 0;
5123 }
5124
5125 static int
5126 igb_timesync_enable(struct rte_eth_dev *dev)
5127 {
5128         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5129         uint32_t tsync_ctl;
5130         uint32_t tsauxc;
5131
5132         /* Stop the timesync system time. */
5133         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5134         /* Reset the timesync system time value. */
5135         switch (hw->mac.type) {
5136         case e1000_82580:
5137         case e1000_i350:
5138         case e1000_i354:
5139         case e1000_i210:
5140         case e1000_i211:
5141                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5142                 /* fall-through */
5143         case e1000_82576:
5144                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5145                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5146                 break;
5147         default:
5148                 /* Not supported. */
5149                 return -ENOTSUP;
5150         }
5151
5152         /* Enable system time for it isn't on by default. */
5153         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5154         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5155         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5156
5157         igb_start_timecounters(dev);
5158
5159         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5160         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5161                         (RTE_ETHER_TYPE_1588 |
5162                          E1000_ETQF_FILTER_ENABLE |
5163                          E1000_ETQF_1588));
5164
5165         /* Enable timestamping of received PTP packets. */
5166         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5167         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5168         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5169
5170         /* Enable Timestamping of transmitted PTP packets. */
5171         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5172         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5173         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5174
5175         return 0;
5176 }
5177
5178 static int
5179 igb_timesync_disable(struct rte_eth_dev *dev)
5180 {
5181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182         uint32_t tsync_ctl;
5183
5184         /* Disable timestamping of transmitted PTP packets. */
5185         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5186         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5187         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5188
5189         /* Disable timestamping of received PTP packets. */
5190         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5191         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5192         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5193
5194         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5195         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5196
5197         /* Stop incrementating the System Time registers. */
5198         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5199
5200         return 0;
5201 }
5202
5203 static int
5204 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5205                                struct timespec *timestamp,
5206                                uint32_t flags __rte_unused)
5207 {
5208         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5209         struct e1000_adapter *adapter =
5210                         (struct e1000_adapter *)dev->data->dev_private;
5211         uint32_t tsync_rxctl;
5212         uint64_t rx_tstamp_cycles;
5213         uint64_t ns;
5214
5215         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5216         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5217                 return -EINVAL;
5218
5219         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5220         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5221         *timestamp = rte_ns_to_timespec(ns);
5222
5223         return  0;
5224 }
5225
5226 static int
5227 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5228                                struct timespec *timestamp)
5229 {
5230         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5231         struct e1000_adapter *adapter =
5232                         (struct e1000_adapter *)dev->data->dev_private;
5233         uint32_t tsync_txctl;
5234         uint64_t tx_tstamp_cycles;
5235         uint64_t ns;
5236
5237         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5238         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5239                 return -EINVAL;
5240
5241         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5242         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5243         *timestamp = rte_ns_to_timespec(ns);
5244
5245         return  0;
5246 }
5247
5248 static int
5249 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5250 {
5251         int count = 0;
5252         int g_ind = 0;
5253         const struct reg_info *reg_group;
5254
5255         while ((reg_group = igb_regs[g_ind++]))
5256                 count += igb_reg_group_count(reg_group);
5257
5258         return count;
5259 }
5260
5261 static int
5262 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5263 {
5264         int count = 0;
5265         int g_ind = 0;
5266         const struct reg_info *reg_group;
5267
5268         while ((reg_group = igbvf_regs[g_ind++]))
5269                 count += igb_reg_group_count(reg_group);
5270
5271         return count;
5272 }
5273
5274 static int
5275 eth_igb_get_regs(struct rte_eth_dev *dev,
5276         struct rte_dev_reg_info *regs)
5277 {
5278         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5279         uint32_t *data = regs->data;
5280         int g_ind = 0;
5281         int count = 0;
5282         const struct reg_info *reg_group;
5283
5284         if (data == NULL) {
5285                 regs->length = eth_igb_get_reg_length(dev);
5286                 regs->width = sizeof(uint32_t);
5287                 return 0;
5288         }
5289
5290         /* Support only full register dump */
5291         if ((regs->length == 0) ||
5292             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5293                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5294                         hw->device_id;
5295                 while ((reg_group = igb_regs[g_ind++]))
5296                         count += igb_read_regs_group(dev, &data[count],
5297                                                         reg_group);
5298                 return 0;
5299         }
5300
5301         return -ENOTSUP;
5302 }
5303
5304 static int
5305 igbvf_get_regs(struct rte_eth_dev *dev,
5306         struct rte_dev_reg_info *regs)
5307 {
5308         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309         uint32_t *data = regs->data;
5310         int g_ind = 0;
5311         int count = 0;
5312         const struct reg_info *reg_group;
5313
5314         if (data == NULL) {
5315                 regs->length = igbvf_get_reg_length(dev);
5316                 regs->width = sizeof(uint32_t);
5317                 return 0;
5318         }
5319
5320         /* Support only full register dump */
5321         if ((regs->length == 0) ||
5322             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5323                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5324                         hw->device_id;
5325                 while ((reg_group = igbvf_regs[g_ind++]))
5326                         count += igb_read_regs_group(dev, &data[count],
5327                                                         reg_group);
5328                 return 0;
5329         }
5330
5331         return -ENOTSUP;
5332 }
5333
5334 static int
5335 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5336 {
5337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338
5339         /* Return unit is byte count */
5340         return hw->nvm.word_size * 2;
5341 }
5342
5343 static int
5344 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5345         struct rte_dev_eeprom_info *in_eeprom)
5346 {
5347         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348         struct e1000_nvm_info *nvm = &hw->nvm;
5349         uint16_t *data = in_eeprom->data;
5350         int first, length;
5351
5352         first = in_eeprom->offset >> 1;
5353         length = in_eeprom->length >> 1;
5354         if ((first >= hw->nvm.word_size) ||
5355             ((first + length) >= hw->nvm.word_size))
5356                 return -EINVAL;
5357
5358         in_eeprom->magic = hw->vendor_id |
5359                 ((uint32_t)hw->device_id << 16);
5360
5361         if ((nvm->ops.read) == NULL)
5362                 return -ENOTSUP;
5363
5364         return nvm->ops.read(hw, first, length, data);
5365 }
5366
5367 static int
5368 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5369         struct rte_dev_eeprom_info *in_eeprom)
5370 {
5371         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372         struct e1000_nvm_info *nvm = &hw->nvm;
5373         uint16_t *data = in_eeprom->data;
5374         int first, length;
5375
5376         first = in_eeprom->offset >> 1;
5377         length = in_eeprom->length >> 1;
5378         if ((first >= hw->nvm.word_size) ||
5379             ((first + length) >= hw->nvm.word_size))
5380                 return -EINVAL;
5381
5382         in_eeprom->magic = (uint32_t)hw->vendor_id |
5383                 ((uint32_t)hw->device_id << 16);
5384
5385         if ((nvm->ops.write) == NULL)
5386                 return -ENOTSUP;
5387         return nvm->ops.write(hw,  first, length, data);
5388 }
5389
5390 static int
5391 eth_igb_get_module_info(struct rte_eth_dev *dev,
5392                         struct rte_eth_dev_module_info *modinfo)
5393 {
5394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395
5396         uint32_t status = 0;
5397         uint16_t sff8472_rev, addr_mode;
5398         bool page_swap = false;
5399
5400         if (hw->phy.media_type == e1000_media_type_copper ||
5401             hw->phy.media_type == e1000_media_type_unknown)
5402                 return -EOPNOTSUPP;
5403
5404         /* Check whether we support SFF-8472 or not */
5405         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5406         if (status)
5407                 return -EIO;
5408
5409         /* addressing mode is not supported */
5410         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5411         if (status)
5412                 return -EIO;
5413
5414         /* addressing mode is not supported */
5415         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5416                 PMD_DRV_LOG(ERR,
5417                             "Address change required to access page 0xA2, "
5418                             "but not supported. Please report the module "
5419                             "type to the driver maintainers.\n");
5420                 page_swap = true;
5421         }
5422
5423         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5424                 /* We have an SFP, but it does not support SFF-8472 */
5425                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5426                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5427         } else {
5428                 /* We have an SFP which supports a revision of SFF-8472 */
5429                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5430                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5431         }
5432
5433         return 0;
5434 }
5435
5436 static int
5437 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5438                           struct rte_dev_eeprom_info *info)
5439 {
5440         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5441
5442         uint32_t status = 0;
5443         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5444         u16 first_word, last_word;
5445         int i = 0;
5446
5447         if (info->length == 0)
5448                 return -EINVAL;
5449
5450         first_word = info->offset >> 1;
5451         last_word = (info->offset + info->length - 1) >> 1;
5452
5453         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5454         for (i = 0; i < last_word - first_word + 1; i++) {
5455                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5456                                                 &dataword[i]);
5457                 if (status) {
5458                         /* Error occurred while reading module */
5459                         return -EIO;
5460                 }
5461
5462                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5463         }
5464
5465         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5466
5467         return 0;
5468 }
5469
5470 static int
5471 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5472 {
5473         struct e1000_hw *hw =
5474                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5476         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5477         uint32_t vec = E1000_MISC_VEC_ID;
5478
5479         if (rte_intr_allow_others(intr_handle))
5480                 vec = E1000_RX_VEC_START;
5481
5482         uint32_t mask = 1 << (queue_id + vec);
5483
5484         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5485         E1000_WRITE_FLUSH(hw);
5486
5487         return 0;
5488 }
5489
5490 static int
5491 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5492 {
5493         struct e1000_hw *hw =
5494                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5496         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5497         uint32_t vec = E1000_MISC_VEC_ID;
5498
5499         if (rte_intr_allow_others(intr_handle))
5500                 vec = E1000_RX_VEC_START;
5501
5502         uint32_t mask = 1 << (queue_id + vec);
5503         uint32_t regval;
5504
5505         regval = E1000_READ_REG(hw, E1000_EIMS);
5506         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5507         E1000_WRITE_FLUSH(hw);
5508
5509         rte_intr_enable(intr_handle);
5510
5511         return 0;
5512 }
5513
5514 static void
5515 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5516                    uint8_t index, uint8_t offset)
5517 {
5518         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5519
5520         /* clear bits */
5521         val &= ~((uint32_t)0xFF << offset);
5522
5523         /* write vector and valid bit */
5524         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5525
5526         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5527 }
5528
5529 static void
5530 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5531                            uint8_t queue, uint8_t msix_vector)
5532 {
5533         uint32_t tmp = 0;
5534
5535         if (hw->mac.type == e1000_82575) {
5536                 if (direction == 0)
5537                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5538                 else if (direction == 1)
5539                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5540                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5541         } else if (hw->mac.type == e1000_82576) {
5542                 if ((direction == 0) || (direction == 1))
5543                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5544                                            ((queue & 0x8) << 1) +
5545                                            8 * direction);
5546         } else if ((hw->mac.type == e1000_82580) ||
5547                         (hw->mac.type == e1000_i350) ||
5548                         (hw->mac.type == e1000_i354) ||
5549                         (hw->mac.type == e1000_i210) ||
5550                         (hw->mac.type == e1000_i211)) {
5551                 if ((direction == 0) || (direction == 1))
5552                         eth_igb_write_ivar(hw, msix_vector,
5553                                            queue >> 1,
5554                                            ((queue & 0x1) << 4) +
5555                                            8 * direction);
5556         }
5557 }
5558
5559 /* Sets up the hardware to generate MSI-X interrupts properly
5560  * @hw
5561  *  board private structure
5562  */
5563 static void
5564 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5565 {
5566         int queue_id;
5567         uint32_t tmpval, regval, intr_mask;
5568         struct e1000_hw *hw =
5569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570         uint32_t vec = E1000_MISC_VEC_ID;
5571         uint32_t base = E1000_MISC_VEC_ID;
5572         uint32_t misc_shift = 0;
5573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5575
5576         /* won't configure msix register if no mapping is done
5577          * between intr vector and event fd
5578          */
5579         if (!rte_intr_dp_is_en(intr_handle))
5580                 return;
5581
5582         if (rte_intr_allow_others(intr_handle)) {
5583                 vec = base = E1000_RX_VEC_START;
5584                 misc_shift = 1;
5585         }
5586
5587         /* set interrupt vector for other causes */
5588         if (hw->mac.type == e1000_82575) {
5589                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5590                 /* enable MSI-X PBA support */
5591                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5592
5593                 /* Auto-Mask interrupts upon ICR read */
5594                 tmpval |= E1000_CTRL_EXT_EIAME;
5595                 tmpval |= E1000_CTRL_EXT_IRCA;
5596
5597                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5598
5599                 /* enable msix_other interrupt */
5600                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5601                 regval = E1000_READ_REG(hw, E1000_EIAC);
5602                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5603                 regval = E1000_READ_REG(hw, E1000_EIAM);
5604                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5605         } else if ((hw->mac.type == e1000_82576) ||
5606                         (hw->mac.type == e1000_82580) ||
5607                         (hw->mac.type == e1000_i350) ||
5608                         (hw->mac.type == e1000_i354) ||
5609                         (hw->mac.type == e1000_i210) ||
5610                         (hw->mac.type == e1000_i211)) {
5611                 /* turn on MSI-X capability first */
5612                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5613                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5614                                         E1000_GPIE_NSICR);
5615                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5616                         misc_shift;
5617
5618                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5619                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5620
5621                 regval = E1000_READ_REG(hw, E1000_EIAC);
5622                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5623
5624                 /* enable msix_other interrupt */
5625                 regval = E1000_READ_REG(hw, E1000_EIMS);
5626                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5627                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5628                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5629         }
5630
5631         /* use EIAM to auto-mask when MSI-X interrupt
5632          * is asserted, this saves a register write for every interrupt
5633          */
5634         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5635                 misc_shift;
5636
5637         if (dev->data->dev_conf.intr_conf.lsc != 0)
5638                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5639
5640         regval = E1000_READ_REG(hw, E1000_EIAM);
5641         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5642
5643         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5644                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5645                 intr_handle->intr_vec[queue_id] = vec;
5646                 if (vec < base + intr_handle->nb_efd - 1)
5647                         vec++;
5648         }
5649
5650         E1000_WRITE_FLUSH(hw);
5651 }
5652
5653 /* restore n-tuple filter */
5654 static inline void
5655 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5656 {
5657         struct e1000_filter_info *filter_info =
5658                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5659         struct e1000_5tuple_filter *p_5tuple;
5660         struct e1000_2tuple_filter *p_2tuple;
5661
5662         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5663                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5664         }
5665
5666         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5667                 igb_inject_2uple_filter(dev, p_2tuple);
5668         }
5669 }
5670
5671 /* restore SYN filter */
5672 static inline void
5673 igb_syn_filter_restore(struct rte_eth_dev *dev)
5674 {
5675         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5676         struct e1000_filter_info *filter_info =
5677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5678         uint32_t synqf;
5679
5680         synqf = filter_info->syn_info;
5681
5682         if (synqf & E1000_SYN_FILTER_ENABLE) {
5683                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5684                 E1000_WRITE_FLUSH(hw);
5685         }
5686 }
5687
5688 /* restore ethernet type filter */
5689 static inline void
5690 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5691 {
5692         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct e1000_filter_info *filter_info =
5694                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5695         int i;
5696
5697         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5698                 if (filter_info->ethertype_mask & (1 << i)) {
5699                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5700                                 filter_info->ethertype_filters[i].etqf);
5701                         E1000_WRITE_FLUSH(hw);
5702                 }
5703         }
5704 }
5705
5706 /* restore flex byte filter */
5707 static inline void
5708 igb_flex_filter_restore(struct rte_eth_dev *dev)
5709 {
5710         struct e1000_filter_info *filter_info =
5711                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5712         struct e1000_flex_filter *flex_filter;
5713
5714         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5715                 igb_inject_flex_filter(dev, flex_filter);
5716         }
5717 }
5718
5719 /* restore rss filter */
5720 static inline void
5721 igb_rss_filter_restore(struct rte_eth_dev *dev)
5722 {
5723         struct e1000_filter_info *filter_info =
5724                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5725
5726         if (filter_info->rss_info.conf.queue_num)
5727                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5728 }
5729
5730 /* restore all types filter */
5731 static int
5732 igb_filter_restore(struct rte_eth_dev *dev)
5733 {
5734         igb_ntuple_filter_restore(dev);
5735         igb_ethertype_filter_restore(dev);
5736         igb_syn_filter_restore(dev);
5737         igb_flex_filter_restore(dev);
5738         igb_rss_filter_restore(dev);
5739
5740         return 0;
5741 }
5742
5743 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5744 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5745 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5746 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5747 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5748 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5749
5750 /* see e1000_logs.c */
5751 RTE_INIT(e1000_init_log)
5752 {
5753         e1000_igb_init_log();
5754 }