drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 100 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_dev_info *dev_info);
 102 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 103                                 struct rte_eth_dev_info *dev_info);
 104 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 105                                 struct rte_eth_fc_conf *fc_conf);
 106 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 107                                 struct rte_eth_fc_conf *fc_conf);
 108 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 109 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 110 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 111 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 112 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 113                                                         void *param);
 114 static int  igb_hardware_init(struct e1000_hw *hw);
 115 static void igb_hw_control_acquire(struct e1000_hw *hw);
 116 static void igb_hw_control_release(struct e1000_hw *hw);
 117 static void igb_init_manageability(struct e1000_hw *hw);
 118 static void igb_release_manageability(struct e1000_hw *hw);
 119
 120 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 121
 122 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 123                 uint16_t vlan_id, int on);
 124 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 125 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 126
 127 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 128 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 129 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 130 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 133
 134 static int eth_igb_led_on(struct rte_eth_dev *dev);
 135 static int eth_igb_led_off(struct rte_eth_dev *dev);
 136
 137 static void igb_intr_disable(struct e1000_hw *hw);
 138 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 139 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 140                 struct ether_addr *mac_addr,
 141                 uint32_t index, uint32_t pool);
 142 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 143 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 144                 struct ether_addr *addr);
 145
 146 static void igbvf_intr_disable(struct e1000_hw *hw);
 147 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 148 static int igbvf_dev_start(struct rte_eth_dev *dev);
 149 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 150 static void igbvf_dev_close(struct rte_eth_dev *dev);
 151 static int eth_igbvf_link_update(struct e1000_hw *hw);
 152 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 153 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 154 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 155                 uint16_t vlan_id, int on);
 156 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 157 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 158 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 159                 struct ether_addr *addr);
 160 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 161 static int igbvf_get_regs(struct rte_eth_dev *dev,
 162                 struct rte_dev_reg_info *regs);
 163
 164 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 165                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 166                                    uint16_t reta_size);
 167 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 168                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 169                                   uint16_t reta_size);
 170
 171 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 172                         struct rte_eth_syn_filter *filter,
 173                         bool add);
 174 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 175                         struct rte_eth_syn_filter *filter);
 176 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 177                         enum rte_filter_op filter_op,
 178                         void *arg);
 179 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 180                         struct rte_eth_ntuple_filter *ntuple_filter);
 181 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 182                         struct rte_eth_ntuple_filter *ntuple_filter);
 183 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 184                         struct rte_eth_flex_filter *filter,
 185                         bool add);
 186 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_flex_filter *filter);
 188 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 189                         enum rte_filter_op filter_op,
 190                         void *arg);
 191 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_ntuple_filter *filter,
 197                         bool add);
 198 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *filter);
 200 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 201                                 enum rte_filter_op filter_op,
 202                                 void *arg);
 203 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 204                         struct rte_eth_ethertype_filter *filter,
 205                         bool add);
 206 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ethertype_filter *filter);
 211 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 212                      enum rte_filter_type filter_type,
 213                      enum rte_filter_op filter_op,
 214                      void *arg);
 215 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 216 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 217                 struct rte_dev_reg_info *regs);
 218 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 220                 struct rte_dev_eeprom_info *eeprom);
 221 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 222                 struct rte_dev_eeprom_info *eeprom);
 223 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 224                                     struct ether_addr *mc_addr_set,
 225                                     uint32_t nb_mc_addr);
 226 static int igb_timesync_enable(struct rte_eth_dev *dev);
 227 static int igb_timesync_disable(struct rte_eth_dev *dev);
 228 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 229                                           struct timespec *timestamp,
 230                                           uint32_t flags);
 231 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp);
 233 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                         uint16_t queue_id);
 235 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                          uint16_t queue_id);
 237 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 238                                        uint8_t queue, uint8_t msix_vector);
 239 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 240                                uint8_t index, uint8_t offset);
 241 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 242
 243 /*
 244  * Define VF Stats MACRO for Non "cleared on read" register
 245  */
 246 #define UPDATE_VF_STAT(reg, last, cur)            \
 247 {                                                 \
 248         u32 latest = E1000_READ_REG(hw, reg);     \
 249         cur += (latest - last) & UINT_MAX;        \
 250         last = latest;                            \
 251 }
 252
 253 #define IGB_FC_PAUSE_TIME 0x0680
 254 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 255 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 256
 257 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 258
 259 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 260
 261 /*
 262  * The set of PCI devices this driver supports
 263  */
 264 static const struct rte_pci_id pci_id_igb_map[] = {
 265
 266 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 267 #include "rte_pci_dev_ids.h"
 268
 269 {0},
 270 };
 271
 272 /*
 273  * The set of PCI devices this driver supports (for 82576&I350 VF)
 274  */
 275 static const struct rte_pci_id pci_id_igbvf_map[] = {
 276
 277 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 278 #include "rte_pci_dev_ids.h"
 279
 280 {0},
 281 };
 282
 283 static const struct rte_eth_desc_lim rx_desc_lim = {
 284         .nb_max = E1000_MAX_RING_DESC,
 285         .nb_min = E1000_MIN_RING_DESC,
 286         .nb_align = IGB_RXD_ALIGN,
 287 };
 288
 289 static const struct rte_eth_desc_lim tx_desc_lim = {
 290         .nb_max = E1000_MAX_RING_DESC,
 291         .nb_min = E1000_MIN_RING_DESC,
 292         .nb_align = IGB_RXD_ALIGN,
 293 };
 294
 295 static const struct eth_dev_ops eth_igb_ops = {
 296         .dev_configure        = eth_igb_configure,
 297         .dev_start            = eth_igb_start,
 298         .dev_stop             = eth_igb_stop,
 299         .dev_close            = eth_igb_close,
 300         .promiscuous_enable   = eth_igb_promiscuous_enable,
 301         .promiscuous_disable  = eth_igb_promiscuous_disable,
 302         .allmulticast_enable  = eth_igb_allmulticast_enable,
 303         .allmulticast_disable = eth_igb_allmulticast_disable,
 304         .link_update          = eth_igb_link_update,
 305         .stats_get            = eth_igb_stats_get,
 306         .stats_reset          = eth_igb_stats_reset,
 307         .dev_infos_get        = eth_igb_infos_get,
 308         .mtu_set              = eth_igb_mtu_set,
 309         .vlan_filter_set      = eth_igb_vlan_filter_set,
 310         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 311         .vlan_offload_set     = eth_igb_vlan_offload_set,
 312         .rx_queue_setup       = eth_igb_rx_queue_setup,
 313         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 314         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 315         .rx_queue_release     = eth_igb_rx_queue_release,
 316         .rx_queue_count       = eth_igb_rx_queue_count,
 317         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 318         .tx_queue_setup       = eth_igb_tx_queue_setup,
 319         .tx_queue_release     = eth_igb_tx_queue_release,
 320         .dev_led_on           = eth_igb_led_on,
 321         .dev_led_off          = eth_igb_led_off,
 322         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 323         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 324         .mac_addr_add         = eth_igb_rar_set,
 325         .mac_addr_remove      = eth_igb_rar_clear,
 326         .mac_addr_set         = eth_igb_default_mac_addr_set,
 327         .reta_update          = eth_igb_rss_reta_update,
 328         .reta_query           = eth_igb_rss_reta_query,
 329         .rss_hash_update      = eth_igb_rss_hash_update,
 330         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 331         .filter_ctrl          = eth_igb_filter_ctrl,
 332         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 333         .rxq_info_get         = igb_rxq_info_get,
 334         .txq_info_get         = igb_txq_info_get,
 335         .timesync_enable      = igb_timesync_enable,
 336         .timesync_disable     = igb_timesync_disable,
 337         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 338         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 339         .get_reg_length       = eth_igb_get_reg_length,
 340         .get_reg              = eth_igb_get_regs,
 341         .get_eeprom_length    = eth_igb_get_eeprom_length,
 342         .get_eeprom           = eth_igb_get_eeprom,
 343         .set_eeprom           = eth_igb_set_eeprom,
 344 };
 345
 346 /*
 347  * dev_ops for virtual function, bare necessities for basic vf
 348  * operation have been implemented
 349  */
 350 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 351         .dev_configure        = igbvf_dev_configure,
 352         .dev_start            = igbvf_dev_start,
 353         .dev_stop             = igbvf_dev_stop,
 354         .dev_close            = igbvf_dev_close,
 355         .link_update          = eth_igb_link_update,
 356         .stats_get            = eth_igbvf_stats_get,
 357         .stats_reset          = eth_igbvf_stats_reset,
 358         .vlan_filter_set      = igbvf_vlan_filter_set,
 359         .dev_infos_get        = eth_igbvf_infos_get,
 360         .rx_queue_setup       = eth_igb_rx_queue_setup,
 361         .rx_queue_release     = eth_igb_rx_queue_release,
 362         .tx_queue_setup       = eth_igb_tx_queue_setup,
 363         .tx_queue_release     = eth_igb_tx_queue_release,
 364         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 365         .rxq_info_get         = igb_rxq_info_get,
 366         .txq_info_get         = igb_txq_info_get,
 367         .mac_addr_set         = igbvf_default_mac_addr_set,
 368         .get_reg_length       = igbvf_get_reg_length,
 369         .get_reg              = igbvf_get_regs,
 370 };
 371
 372 /**
 373  * Atomically reads the link status information from global
 374  * structure rte_eth_dev.
 375  *
 376  * @param dev
 377  *   - Pointer to the structure rte_eth_dev to read from.
 378  *   - Pointer to the buffer to be saved with the link status.
 379  *
 380  * @return
 381  *   - On success, zero.
 382  *   - On failure, negative value.
 383  */
 384 static inline int
 385 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 386                                 struct rte_eth_link *link)
 387 {
 388         struct rte_eth_link *dst = link;
 389         struct rte_eth_link *src = &(dev->data->dev_link);
 390
 391         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 392                                         *(uint64_t *)src) == 0)
 393                 return -1;
 394
 395         return 0;
 396 }
 397
 398 /**
 399  * Atomically writes the link status information into global
 400  * structure rte_eth_dev.
 401  *
 402  * @param dev
 403  *   - Pointer to the structure rte_eth_dev to read from.
 404  *   - Pointer to the buffer to be saved with the link status.
 405  *
 406  * @return
 407  *   - On success, zero.
 408  *   - On failure, negative value.
 409  */
 410 static inline int
 411 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 412                                 struct rte_eth_link *link)
 413 {
 414         struct rte_eth_link *dst = &(dev->data->dev_link);
 415         struct rte_eth_link *src = link;
 416
 417         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 418                                         *(uint64_t *)src) == 0)
 419                 return -1;
 420
 421         return 0;
 422 }
 423
 424 static inline void
 425 igb_intr_enable(struct rte_eth_dev *dev)
 426 {
 427         struct e1000_interrupt *intr =
 428                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 429         struct e1000_hw *hw =
 430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 431
 432         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 433         E1000_WRITE_FLUSH(hw);
 434 }
 435
 436 static void
 437 igb_intr_disable(struct e1000_hw *hw)
 438 {
 439         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 440         E1000_WRITE_FLUSH(hw);
 441 }
 442
 443 static inline int32_t
 444 igb_pf_reset_hw(struct e1000_hw *hw)
 445 {
 446         uint32_t ctrl_ext;
 447         int32_t status;
 448
 449         status = e1000_reset_hw(hw);
 450
 451         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 452         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 453         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 454         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 455         E1000_WRITE_FLUSH(hw);
 456
 457         return status;
 458 }
 459
 460 static void
 461 igb_identify_hardware(struct rte_eth_dev *dev)
 462 {
 463         struct e1000_hw *hw =
 464                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 465
 466         hw->vendor_id = dev->pci_dev->id.vendor_id;
 467         hw->device_id = dev->pci_dev->id.device_id;
 468         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 469         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 470
 471         e1000_set_mac_type(hw);
 472
 473         /* need to check if it is a vf device below */
 474 }
 475
 476 static int
 477 igb_reset_swfw_lock(struct e1000_hw *hw)
 478 {
 479         int ret_val;
 480
 481         /*
 482          * Do mac ops initialization manually here, since we will need
 483          * some function pointers set by this call.
 484          */
 485         ret_val = e1000_init_mac_params(hw);
 486         if (ret_val)
 487                 return ret_val;
 488
 489         /*
 490          * SMBI lock should not fail in this early stage. If this is the case,
 491          * it is due to an improper exit of the application.
 492          * So force the release of the faulty lock.
 493          */
 494         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 495                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 496         }
 497         e1000_put_hw_semaphore_generic(hw);
 498
 499         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 500                 uint16_t mask;
 501
 502                 /*
 503                  * Phy lock should not fail in this early stage. If this is the case,
 504                  * it is due to an improper exit of the application.
 505                  * So force the release of the faulty lock.
 506                  */
 507                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 508                 if (hw->bus.func > E1000_FUNC_1)
 509                         mask <<= 2;
 510                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 511                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 512                                     hw->bus.func);
 513                 }
 514                 hw->mac.ops.release_swfw_sync(hw, mask);
 515
 516                 /*
 517                  * This one is more tricky since it is common to all ports; but
 518                  * swfw_sync retries last long enough (1s) to be almost sure that if
 519                  * lock can not be taken it is due to an improper lock of the
 520                  * semaphore.
 521                  */
 522                 mask = E1000_SWFW_EEP_SM;
 523                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 524                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 525                 }
 526                 hw->mac.ops.release_swfw_sync(hw, mask);
 527         }
 528
 529         return E1000_SUCCESS;
 530 }
 531
 532 static int
 533 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 534 {
 535         int error = 0;
 536         struct rte_pci_device *pci_dev;
 537         struct e1000_hw *hw =
 538                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 539         struct e1000_vfta * shadow_vfta =
 540                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 541         struct e1000_filter_info *filter_info =
 542                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 543         struct e1000_adapter *adapter =
 544                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 545
 546         uint32_t ctrl_ext;
 547
 548         pci_dev = eth_dev->pci_dev;
 549         eth_dev->dev_ops = &eth_igb_ops;
 550         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 551         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 552
 553         /* for secondary processes, we don't initialise any further as primary
 554          * has already done this work. Only check we don't need a different
 555          * RX function */
 556         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 557                 if (eth_dev->data->scattered_rx)
 558                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 559                 return 0;
 560         }
 561
 562         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 563
 564         igb_identify_hardware(eth_dev);
 565         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 566                 error = -EIO;
 567                 goto err_late;
 568         }
 569
 570         e1000_get_bus_info(hw);
 571
 572         /* Reset any pending lock */
 573         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 574                 error = -EIO;
 575                 goto err_late;
 576         }
 577
 578         /* Finish initialization */
 579         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 580                 error = -EIO;
 581                 goto err_late;
 582         }
 583
 584         hw->mac.autoneg = 1;
 585         hw->phy.autoneg_wait_to_complete = 0;
 586         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 587
 588         /* Copper options */
 589         if (hw->phy.media_type == e1000_media_type_copper) {
 590                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 591                 hw->phy.disable_polarity_correction = 0;
 592                 hw->phy.ms_type = e1000_ms_hw_default;
 593         }
 594
 595         /*
 596          * Start from a known state, this is important in reading the nvm
 597          * and mac from that.
 598          */
 599         igb_pf_reset_hw(hw);
 600
 601         /* Make sure we have a good EEPROM before we read from it */
 602         if (e1000_validate_nvm_checksum(hw) < 0) {
 603                 /*
 604                  * Some PCI-E parts fail the first check due to
 605                  * the link being in sleep state, call it again,
 606                  * if it fails a second time its a real issue.
 607                  */
 608                 if (e1000_validate_nvm_checksum(hw) < 0) {
 609                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 610                         error = -EIO;
 611                         goto err_late;
 612                 }
 613         }
 614
 615         /* Read the permanent MAC address out of the EEPROM */
 616         if (e1000_read_mac_addr(hw) != 0) {
 617                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 618                 error = -EIO;
 619                 goto err_late;
 620         }
 621
 622         /* Allocate memory for storing MAC addresses */
 623         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 624                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 625         if (eth_dev->data->mac_addrs == NULL) {
 626                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 627                                                 "store MAC addresses",
 628                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 629                 error = -ENOMEM;
 630                 goto err_late;
 631         }
 632
 633         /* Copy the permanent MAC address */
 634         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 635
 636         /* initialize the vfta */
 637         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 638
 639         /* Now initialize the hardware */
 640         if (igb_hardware_init(hw) != 0) {
 641                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 642                 rte_free(eth_dev->data->mac_addrs);
 643                 eth_dev->data->mac_addrs = NULL;
 644                 error = -ENODEV;
 645                 goto err_late;
 646         }
 647         hw->mac.get_link_status = 1;
 648         adapter->stopped = 0;
 649
 650         /* Indicate SOL/IDER usage */
 651         if (e1000_check_reset_block(hw) < 0) {
 652                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 653                                         "SOL/IDER session");
 654         }
 655
 656         /* initialize PF if max_vfs not zero */
 657         igb_pf_host_init(eth_dev);
 658
 659         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 660         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 661         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 662         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 663         E1000_WRITE_FLUSH(hw);
 664
 665         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 666                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 667                      pci_dev->id.device_id);
 668
 669         /* enable support intr */
 670         igb_intr_enable(eth_dev);
 671
 672         TAILQ_INIT(&filter_info->flex_list);
 673         filter_info->flex_mask = 0;
 674         TAILQ_INIT(&filter_info->twotuple_list);
 675         filter_info->twotuple_mask = 0;
 676         TAILQ_INIT(&filter_info->fivetuple_list);
 677         filter_info->fivetuple_mask = 0;
 678
 679         return 0;
 680
 681 err_late:
 682         igb_hw_control_release(hw);
 683
 684         return (error);
 685 }
 686
 687 static int
 688 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 689 {
 690         struct rte_pci_device *pci_dev;
 691         struct e1000_hw *hw;
 692         struct e1000_adapter *adapter =
 693                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 698                 return -EPERM;
 699
 700         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 701         pci_dev = eth_dev->pci_dev;
 702
 703         if (adapter->stopped == 0)
 704                 eth_igb_close(eth_dev);
 705
 706         eth_dev->dev_ops = NULL;
 707         eth_dev->rx_pkt_burst = NULL;
 708         eth_dev->tx_pkt_burst = NULL;
 709
 710         /* Reset any pending lock */
 711         igb_reset_swfw_lock(hw);
 712
 713         rte_free(eth_dev->data->mac_addrs);
 714         eth_dev->data->mac_addrs = NULL;
 715
 716         /* uninitialize PF if max_vfs not zero */
 717         igb_pf_host_uninit(eth_dev);
 718
 719         /* disable uio intr before callback unregister */
 720         rte_intr_disable(&(pci_dev->intr_handle));
 721         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 722                 eth_igb_interrupt_handler, (void *)eth_dev);
 723
 724         return 0;
 725 }
 726
 727 /*
 728  * Virtual Function device init
 729  */
 730 static int
 731 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 732 {
 733         struct rte_pci_device *pci_dev;
 734         struct e1000_adapter *adapter =
 735                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 736         struct e1000_hw *hw =
 737                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 738         int diag;
 739
 740         PMD_INIT_FUNC_TRACE();
 741
 742         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 743         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 744         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 745
 746         /* for secondary processes, we don't initialise any further as primary
 747          * has already done this work. Only check we don't need a different
 748          * RX function */
 749         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 750                 if (eth_dev->data->scattered_rx)
 751                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 752                 return 0;
 753         }
 754
 755         pci_dev = eth_dev->pci_dev;
 756
 757         hw->device_id = pci_dev->id.device_id;
 758         hw->vendor_id = pci_dev->id.vendor_id;
 759         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 760         adapter->stopped = 0;
 761
 762         /* Initialize the shared code (base driver) */
 763         diag = e1000_setup_init_funcs(hw, TRUE);
 764         if (diag != 0) {
 765                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 766                         diag);
 767                 return -EIO;
 768         }
 769
 770         /* init_mailbox_params */
 771         hw->mbx.ops.init_params(hw);
 772
 773         /* Disable the interrupts for VF */
 774         igbvf_intr_disable(hw);
 775
 776         diag = hw->mac.ops.reset_hw(hw);
 777
 778         /* Allocate memory for storing MAC addresses */
 779         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 780                 hw->mac.rar_entry_count, 0);
 781         if (eth_dev->data->mac_addrs == NULL) {
 782                 PMD_INIT_LOG(ERR,
 783                         "Failed to allocate %d bytes needed to store MAC "
 784                         "addresses",
 785                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 786                 return -ENOMEM;
 787         }
 788
 789         /* Copy the permanent MAC address */
 790         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 791                         &eth_dev->data->mac_addrs[0]);
 792
 793         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 794                      "mac.type=%s",
 795                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 796                      pci_dev->id.device_id, "igb_mac_82576_vf");
 797
 798         return 0;
 799 }
 800
 801 static int
 802 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 803 {
 804         struct e1000_adapter *adapter =
 805                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 806
 807         PMD_INIT_FUNC_TRACE();
 808
 809         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 810                 return -EPERM;
 811
 812         if (adapter->stopped == 0)
 813                 igbvf_dev_close(eth_dev);
 814
 815         eth_dev->dev_ops = NULL;
 816         eth_dev->rx_pkt_burst = NULL;
 817         eth_dev->tx_pkt_burst = NULL;
 818
 819         rte_free(eth_dev->data->mac_addrs);
 820         eth_dev->data->mac_addrs = NULL;
 821
 822         return 0;
 823 }
 824
 825 static struct eth_driver rte_igb_pmd = {
 826         .pci_drv = {
 827                 .name = "rte_igb_pmd",
 828                 .id_table = pci_id_igb_map,
 829                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 830                         RTE_PCI_DRV_DETACHABLE,
 831         },
 832         .eth_dev_init = eth_igb_dev_init,
 833         .eth_dev_uninit = eth_igb_dev_uninit,
 834         .dev_private_size = sizeof(struct e1000_adapter),
 835 };
 836
 837 /*
 838  * virtual function driver struct
 839  */
 840 static struct eth_driver rte_igbvf_pmd = {
 841         .pci_drv = {
 842                 .name = "rte_igbvf_pmd",
 843                 .id_table = pci_id_igbvf_map,
 844                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 845         },
 846         .eth_dev_init = eth_igbvf_dev_init,
 847         .eth_dev_uninit = eth_igbvf_dev_uninit,
 848         .dev_private_size = sizeof(struct e1000_adapter),
 849 };
 850
 851 static int
 852 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 853 {
 854         rte_eth_driver_register(&rte_igb_pmd);
 855         return 0;
 856 }
 857
 858 static void
 859 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 860 {
 861         struct e1000_hw *hw =
 862                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 863         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 864         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 865         rctl |= E1000_RCTL_VFE;
 866         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 867 }
 868
 869 /*
 870  * VF Driver initialization routine.
 871  * Invoked one at EAL init time.
 872  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 873  */
 874 static int
 875 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 876 {
 877         PMD_INIT_FUNC_TRACE();
 878
 879         rte_eth_driver_register(&rte_igbvf_pmd);
 880         return (0);
 881 }
 882
 883 static int
 884 igb_check_mq_mode(struct rte_eth_dev *dev)
 885 {
 886         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 887         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 888         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 889         uint16_t nb_tx_q = dev->data->nb_rx_queues;
 890
 891         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
 892             tx_mq_mode == ETH_MQ_TX_DCB ||
 893             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 894                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 895                 return -EINVAL;
 896         }
 897         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
 898                 /* Check multi-queue mode.
 899                  * To no break software we accept ETH_MQ_RX_NONE as this might
 900                  * be used to turn off VLAN filter.
 901                  */
 902
 903                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
 904                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 905                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
 906                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
 907                 } else {
 908                         /* Only support one queue on VFs.
 909                          * RSS together with SRIOV is not supported.
 910                          */
 911                         PMD_INIT_LOG(ERR, "SRIOV is active,"
 912                                         " wrong mq_mode rx %d.",
 913                                         rx_mq_mode);
 914                         return -EINVAL;
 915                 }
 916                 /* TX mode is not used here, so mode might be ignored.*/
 917                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
 918                         /* SRIOV only works in VMDq enable mode */
 919                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
 920                                         " TX mode %d is not supported. "
 921                                         " Driver will behave as %d mode.",
 922                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
 923                 }
 924
 925                 /* check valid queue number */
 926                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
 927                         PMD_INIT_LOG(ERR, "SRIOV is active,"
 928                                         " only support one queue on VFs.");
 929                         return -EINVAL;
 930                 }
 931         } else {
 932                 /* To no break software that set invalid mode, only display
 933                  * warning if invalid mode is used.
 934                  */
 935                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
 936                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
 937                     rx_mq_mode != ETH_MQ_RX_RSS) {
 938                         /* RSS together with VMDq not supported*/
 939                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
 940                                      rx_mq_mode);
 941                         return -EINVAL;
 942                 }
 943
 944                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
 945                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
 946                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
 947                                         " Due to txmode is meaningless in this"
 948                                         " driver, just ignore.",
 949                                         tx_mq_mode);
 950                 }
 951         }
 952         return 0;
 953 }
 954
 955 static int
 956 eth_igb_configure(struct rte_eth_dev *dev)
 957 {
 958         struct e1000_interrupt *intr =
 959                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 960         int ret;
 961
 962         PMD_INIT_FUNC_TRACE();
 963
 964         /* multipe queue mode checking */
 965         ret  = igb_check_mq_mode(dev);
 966         if (ret != 0) {
 967                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
 968                             ret);
 969                 return ret;
 970         }
 971
 972         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
 973         PMD_INIT_FUNC_TRACE();
 974
 975         return 0;
 976 }
 977
 978 static int
 979 eth_igb_start(struct rte_eth_dev *dev)
 980 {
 981         struct e1000_hw *hw =
 982                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 983         struct e1000_adapter *adapter =
 984                 E1000_DEV_PRIVATE(dev->data->dev_private);
 985         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 986         int ret, mask;
 987         uint32_t intr_vector = 0;
 988         uint32_t ctrl_ext;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         /* Power up the phy. Needed to make the link go Up */
 993         e1000_power_up_phy(hw);
 994
 995         /*
 996          * Packet Buffer Allocation (PBA)
 997          * Writing PBA sets the receive portion of the buffer
 998          * the remainder is used for the transmit buffer.
 999          */
1000         if (hw->mac.type == e1000_82575) {
1001                 uint32_t pba;
1002
1003                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1004                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1005         }
1006
1007         /* Put the address into the Receive Address Array */
1008         e1000_rar_set(hw, hw->mac.addr, 0);
1009
1010         /* Initialize the hardware */
1011         if (igb_hardware_init(hw)) {
1012                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1013                 return (-EIO);
1014         }
1015         adapter->stopped = 0;
1016
1017         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1018
1019         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1020         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1021         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1022         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1023         E1000_WRITE_FLUSH(hw);
1024
1025         /* configure PF module if SRIOV enabled */
1026         igb_pf_host_configure(dev);
1027
1028         /* check and configure queue intr-vector mapping */
1029         if (dev->data->dev_conf.intr_conf.rxq != 0)
1030                 intr_vector = dev->data->nb_rx_queues;
1031
1032         if (rte_intr_efd_enable(intr_handle, intr_vector))
1033                 return -1;
1034
1035         if (rte_intr_dp_is_en(intr_handle)) {
1036                 intr_handle->intr_vec =
1037                         rte_zmalloc("intr_vec",
1038                                     dev->data->nb_rx_queues * sizeof(int), 0);
1039                 if (intr_handle->intr_vec == NULL) {
1040                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1041                                      " intr_vec\n", dev->data->nb_rx_queues);
1042                         return -ENOMEM;
1043                 }
1044         }
1045
1046         /* confiugre msix for rx interrupt */
1047         eth_igb_configure_msix_intr(dev);
1048
1049         /* Configure for OS presence */
1050         igb_init_manageability(hw);
1051
1052         eth_igb_tx_init(dev);
1053
1054         /* This can fail when allocating mbufs for descriptor rings */
1055         ret = eth_igb_rx_init(dev);
1056         if (ret) {
1057                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1058                 igb_dev_clear_queues(dev);
1059                 return ret;
1060         }
1061
1062         e1000_clear_hw_cntrs_base_generic(hw);
1063
1064         /*
1065          * VLAN Offload Settings
1066          */
1067         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1068                         ETH_VLAN_EXTEND_MASK;
1069         eth_igb_vlan_offload_set(dev, mask);
1070
1071         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1072                 /* Enable VLAN filter since VMDq always use VLAN filter */
1073                 igb_vmdq_vlan_hw_filter_enable(dev);
1074         }
1075
1076         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1077                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1078                 (hw->mac.type == e1000_i211)) {
1079                 /* Configure EITR with the maximum possible value (0xFFFF) */
1080                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1081         }
1082
1083         /* Setup link speed and duplex */
1084         switch (dev->data->dev_conf.link_speed) {
1085         case ETH_LINK_SPEED_AUTONEG:
1086                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1087                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1088                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1089                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1090                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1091                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1092                 else
1093                         goto error_invalid_config;
1094                 break;
1095         case ETH_LINK_SPEED_10:
1096                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1097                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1098                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1099                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1100                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1101                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1102                 else
1103                         goto error_invalid_config;
1104                 break;
1105         case ETH_LINK_SPEED_100:
1106                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1107                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1108                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1109                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1110                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1111                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1112                 else
1113                         goto error_invalid_config;
1114                 break;
1115         case ETH_LINK_SPEED_1000:
1116                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1117                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1118                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1119                 else
1120                         goto error_invalid_config;
1121                 break;
1122         case ETH_LINK_SPEED_10000:
1123         default:
1124                 goto error_invalid_config;
1125         }
1126         e1000_setup_link(hw);
1127
1128         /* check if lsc interrupt feature is enabled */
1129         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1130                 if (rte_intr_allow_others(intr_handle)) {
1131                         rte_intr_callback_register(intr_handle,
1132                                                    eth_igb_interrupt_handler,
1133                                                    (void *)dev);
1134                         eth_igb_lsc_interrupt_setup(dev);
1135                 } else
1136                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1137                                      " no intr multiplex\n");
1138         }
1139
1140         /* check if rxq interrupt is enabled */
1141         if (dev->data->dev_conf.intr_conf.rxq != 0)
1142                 eth_igb_rxq_interrupt_setup(dev);
1143
1144         /* enable uio/vfio intr/eventfd mapping */
1145         rte_intr_enable(intr_handle);
1146
1147         /* resume enabled intr since hw reset */
1148         igb_intr_enable(dev);
1149
1150         PMD_INIT_LOG(DEBUG, "<<");
1151
1152         return (0);
1153
1154 error_invalid_config:
1155         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1156                      dev->data->dev_conf.link_speed,
1157                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1158         igb_dev_clear_queues(dev);
1159         return (-EINVAL);
1160 }
1161
1162 /*********************************************************************
1163  *
1164  *  This routine disables all traffic on the adapter by issuing a
1165  *  global reset on the MAC.
1166  *
1167  **********************************************************************/
1168 static void
1169 eth_igb_stop(struct rte_eth_dev *dev)
1170 {
1171         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1172         struct e1000_filter_info *filter_info =
1173                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1174         struct rte_eth_link link;
1175         struct e1000_flex_filter *p_flex;
1176         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1177         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1178         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1179
1180         igb_intr_disable(hw);
1181
1182         /* disable intr eventfd mapping */
1183         rte_intr_disable(intr_handle);
1184
1185         igb_pf_reset_hw(hw);
1186         E1000_WRITE_REG(hw, E1000_WUC, 0);
1187
1188         /* Set bit for Go Link disconnect */
1189         if (hw->mac.type >= e1000_82580) {
1190                 uint32_t phpm_reg;
1191
1192                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1193                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1194                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1195         }
1196
1197         /* Power down the phy. Needed to make the link go Down */
1198         if (hw->phy.media_type == e1000_media_type_copper)
1199                 e1000_power_down_phy(hw);
1200         else
1201                 e1000_shutdown_fiber_serdes_link(hw);
1202
1203         igb_dev_clear_queues(dev);
1204
1205         /* clear the recorded link status */
1206         memset(&link, 0, sizeof(link));
1207         rte_igb_dev_atomic_write_link_status(dev, &link);
1208
1209         /* Remove all flex filters of the device */
1210         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1211                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1212                 rte_free(p_flex);
1213         }
1214         filter_info->flex_mask = 0;
1215
1216         /* Remove all ntuple filters of the device */
1217         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1218              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1219                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1220                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1221                              p_5tuple, entries);
1222                 rte_free(p_5tuple);
1223         }
1224         filter_info->fivetuple_mask = 0;
1225         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1226              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1227                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1228                 TAILQ_REMOVE(&filter_info->twotuple_list,
1229                              p_2tuple, entries);
1230                 rte_free(p_2tuple);
1231         }
1232         filter_info->twotuple_mask = 0;
1233
1234         /* Clean datapath event and queue/vec mapping */
1235         rte_intr_efd_disable(intr_handle);
1236         if (intr_handle->intr_vec != NULL) {
1237                 rte_free(intr_handle->intr_vec);
1238                 intr_handle->intr_vec = NULL;
1239         }
1240 }
1241
1242 static void
1243 eth_igb_close(struct rte_eth_dev *dev)
1244 {
1245         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246         struct e1000_adapter *adapter =
1247                 E1000_DEV_PRIVATE(dev->data->dev_private);
1248         struct rte_eth_link link;
1249         struct rte_pci_device *pci_dev;
1250
1251         eth_igb_stop(dev);
1252         adapter->stopped = 1;
1253
1254         e1000_phy_hw_reset(hw);
1255         igb_release_manageability(hw);
1256         igb_hw_control_release(hw);
1257
1258         /* Clear bit for Go Link disconnect */
1259         if (hw->mac.type >= e1000_82580) {
1260                 uint32_t phpm_reg;
1261
1262                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1263                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1264                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1265         }
1266
1267         igb_dev_free_queues(dev);
1268
1269         pci_dev = dev->pci_dev;
1270         if (pci_dev->intr_handle.intr_vec) {
1271                 rte_free(pci_dev->intr_handle.intr_vec);
1272                 pci_dev->intr_handle.intr_vec = NULL;
1273         }
1274
1275         memset(&link, 0, sizeof(link));
1276         rte_igb_dev_atomic_write_link_status(dev, &link);
1277 }
1278
1279 static int
1280 igb_get_rx_buffer_size(struct e1000_hw *hw)
1281 {
1282         uint32_t rx_buf_size;
1283         if (hw->mac.type == e1000_82576) {
1284                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1285         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1286                 /* PBS needs to be translated according to a lookup table */
1287                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1288                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1289                 rx_buf_size = (rx_buf_size << 10);
1290         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1291                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1292         } else {
1293                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1294         }
1295
1296         return rx_buf_size;
1297 }
1298
1299 /*********************************************************************
1300  *
1301  *  Initialize the hardware
1302  *
1303  **********************************************************************/
1304 static int
1305 igb_hardware_init(struct e1000_hw *hw)
1306 {
1307         uint32_t rx_buf_size;
1308         int diag;
1309
1310         /* Let the firmware know the OS is in control */
1311         igb_hw_control_acquire(hw);
1312
1313         /*
1314          * These parameters control the automatic generation (Tx) and
1315          * response (Rx) to Ethernet PAUSE frames.
1316          * - High water mark should allow for at least two standard size (1518)
1317          *   frames to be received after sending an XOFF.
1318          * - Low water mark works best when it is very near the high water mark.
1319          *   This allows the receiver to restart by sending XON when it has
1320          *   drained a bit. Here we use an arbitrary value of 1500 which will
1321          *   restart after one full frame is pulled from the buffer. There
1322          *   could be several smaller frames in the buffer and if so they will
1323          *   not trigger the XON until their total number reduces the buffer
1324          *   by 1500.
1325          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1326          */
1327         rx_buf_size = igb_get_rx_buffer_size(hw);
1328
1329         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1330         hw->fc.low_water = hw->fc.high_water - 1500;
1331         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1332         hw->fc.send_xon = 1;
1333
1334         /* Set Flow control, use the tunable location if sane */
1335         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1336                 hw->fc.requested_mode = igb_fc_setting;
1337         else
1338                 hw->fc.requested_mode = e1000_fc_none;
1339
1340         /* Issue a global reset */
1341         igb_pf_reset_hw(hw);
1342         E1000_WRITE_REG(hw, E1000_WUC, 0);
1343
1344         diag = e1000_init_hw(hw);
1345         if (diag < 0)
1346                 return (diag);
1347
1348         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1349         e1000_get_phy_info(hw);
1350         e1000_check_for_link(hw);
1351
1352         return (0);
1353 }
1354
1355 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1356 static void
1357 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1358 {
1359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1360         struct e1000_hw_stats *stats =
1361                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1362         int pause_frames;
1363
1364         if(hw->phy.media_type == e1000_media_type_copper ||
1365             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1366                 stats->symerrs +=
1367                     E1000_READ_REG(hw,E1000_SYMERRS);
1368                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1369         }
1370
1371         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1372         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1373         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1374         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1375
1376         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1377         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1378         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1379         stats->dc += E1000_READ_REG(hw, E1000_DC);
1380         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1381         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1382         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1383         /*
1384         ** For watchdog management we need to know if we have been
1385         ** paused during the last interval, so capture that here.
1386         */
1387         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1388         stats->xoffrxc += pause_frames;
1389         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1390         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1391         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1392         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1393         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1394         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1395         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1396         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1397         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1398         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1399         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1400         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1401
1402         /* For the 64-bit byte counters the low dword must be read first. */
1403         /* Both registers clear on the read of the high dword */
1404
1405         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1406         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1407         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1408         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1409
1410         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1411         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1412         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1413         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1414         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1415
1416         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1417         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1418         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1419         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1420
1421         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1422         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1423         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1424         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1425         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1426         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1427         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1428         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1429         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1430         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1431
1432         /* Interrupt Counts */
1433
1434         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1435         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1436         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1437         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1438         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1439         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1440         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1441         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1442         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1443
1444         /* Host to Card Statistics */
1445
1446         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1447         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1448         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1449         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1450         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1451         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1452         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1453         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1454         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1455         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1456         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1457         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1458         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1459         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1460
1461         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1462         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1463         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1464         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1465         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1466         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1467
1468         if (rte_stats == NULL)
1469                 return;
1470
1471         /* Rx Errors */
1472         rte_stats->ibadcrc = stats->crcerrs;
1473         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1474         rte_stats->imissed = stats->mpc;
1475         rte_stats->ierrors = rte_stats->ibadcrc +
1476                              rte_stats->ibadlen +
1477                              rte_stats->imissed +
1478                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1479
1480         /* Tx Errors */
1481         rte_stats->oerrors = stats->ecol + stats->latecol;
1482
1483         /* XON/XOFF pause frames */
1484         rte_stats->tx_pause_xon  = stats->xontxc;
1485         rte_stats->rx_pause_xon  = stats->xonrxc;
1486         rte_stats->tx_pause_xoff = stats->xofftxc;
1487         rte_stats->rx_pause_xoff = stats->xoffrxc;
1488
1489         rte_stats->ipackets = stats->gprc;
1490         rte_stats->opackets = stats->gptc;
1491         rte_stats->ibytes   = stats->gorc;
1492         rte_stats->obytes   = stats->gotc;
1493 }
1494
1495 static void
1496 eth_igb_stats_reset(struct rte_eth_dev *dev)
1497 {
1498         struct e1000_hw_stats *hw_stats =
1499                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1500
1501         /* HW registers are cleared on read */
1502         eth_igb_stats_get(dev, NULL);
1503
1504         /* Reset software totals */
1505         memset(hw_stats, 0, sizeof(*hw_stats));
1506 }
1507
1508 static void
1509 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1510 {
1511         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1512         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1513                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1514
1515         /* Good Rx packets, include VF loopback */
1516         UPDATE_VF_STAT(E1000_VFGPRC,
1517             hw_stats->last_gprc, hw_stats->gprc);
1518
1519         /* Good Rx octets, include VF loopback */
1520         UPDATE_VF_STAT(E1000_VFGORC,
1521             hw_stats->last_gorc, hw_stats->gorc);
1522
1523         /* Good Tx packets, include VF loopback */
1524         UPDATE_VF_STAT(E1000_VFGPTC,
1525             hw_stats->last_gptc, hw_stats->gptc);
1526
1527         /* Good Tx octets, include VF loopback */
1528         UPDATE_VF_STAT(E1000_VFGOTC,
1529             hw_stats->last_gotc, hw_stats->gotc);
1530
1531         /* Rx Multicst packets */
1532         UPDATE_VF_STAT(E1000_VFMPRC,
1533             hw_stats->last_mprc, hw_stats->mprc);
1534
1535         /* Good Rx loopback packets */
1536         UPDATE_VF_STAT(E1000_VFGPRLBC,
1537             hw_stats->last_gprlbc, hw_stats->gprlbc);
1538
1539         /* Good Rx loopback octets */
1540         UPDATE_VF_STAT(E1000_VFGORLBC,
1541             hw_stats->last_gorlbc, hw_stats->gorlbc);
1542
1543         /* Good Tx loopback packets */
1544         UPDATE_VF_STAT(E1000_VFGPTLBC,
1545             hw_stats->last_gptlbc, hw_stats->gptlbc);
1546
1547         /* Good Tx loopback octets */
1548         UPDATE_VF_STAT(E1000_VFGOTLBC,
1549             hw_stats->last_gotlbc, hw_stats->gotlbc);
1550
1551         if (rte_stats == NULL)
1552                 return;
1553
1554         rte_stats->ipackets = hw_stats->gprc;
1555         rte_stats->ibytes = hw_stats->gorc;
1556         rte_stats->opackets = hw_stats->gptc;
1557         rte_stats->obytes = hw_stats->gotc;
1558         rte_stats->imcasts = hw_stats->mprc;
1559         rte_stats->ilbpackets = hw_stats->gprlbc;
1560         rte_stats->ilbbytes = hw_stats->gorlbc;
1561         rte_stats->olbpackets = hw_stats->gptlbc;
1562         rte_stats->olbbytes = hw_stats->gotlbc;
1563
1564 }
1565
1566 static void
1567 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1568 {
1569         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1570                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1571
1572         /* Sync HW register to the last stats */
1573         eth_igbvf_stats_get(dev, NULL);
1574
1575         /* reset HW current stats*/
1576         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1577                offsetof(struct e1000_vf_stats, gprc));
1578
1579 }
1580
1581 static void
1582 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1583 {
1584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585
1586         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1587         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1588         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1589         dev_info->rx_offload_capa =
1590                 DEV_RX_OFFLOAD_VLAN_STRIP |
1591                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1592                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1593                 DEV_RX_OFFLOAD_TCP_CKSUM;
1594         dev_info->tx_offload_capa =
1595                 DEV_TX_OFFLOAD_VLAN_INSERT |
1596                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1597                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1598                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1599                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1600                 DEV_TX_OFFLOAD_TCP_TSO;
1601
1602         switch (hw->mac.type) {
1603         case e1000_82575:
1604                 dev_info->max_rx_queues = 4;
1605                 dev_info->max_tx_queues = 4;
1606                 dev_info->max_vmdq_pools = 0;
1607                 break;
1608
1609         case e1000_82576:
1610                 dev_info->max_rx_queues = 16;
1611                 dev_info->max_tx_queues = 16;
1612                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1613                 dev_info->vmdq_queue_num = 16;
1614                 break;
1615
1616         case e1000_82580:
1617                 dev_info->max_rx_queues = 8;
1618                 dev_info->max_tx_queues = 8;
1619                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1620                 dev_info->vmdq_queue_num = 8;
1621                 break;
1622
1623         case e1000_i350:
1624                 dev_info->max_rx_queues = 8;
1625                 dev_info->max_tx_queues = 8;
1626                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1627                 dev_info->vmdq_queue_num = 8;
1628                 break;
1629
1630         case e1000_i354:
1631                 dev_info->max_rx_queues = 8;
1632                 dev_info->max_tx_queues = 8;
1633                 break;
1634
1635         case e1000_i210:
1636                 dev_info->max_rx_queues = 4;
1637                 dev_info->max_tx_queues = 4;
1638                 dev_info->max_vmdq_pools = 0;
1639                 break;
1640
1641         case e1000_i211:
1642                 dev_info->max_rx_queues = 2;
1643                 dev_info->max_tx_queues = 2;
1644                 dev_info->max_vmdq_pools = 0;
1645                 break;
1646
1647         default:
1648                 /* Should not happen */
1649                 break;
1650         }
1651         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1652         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1653         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1654
1655         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1656                 .rx_thresh = {
1657                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1658                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1659                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1660                 },
1661                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1662                 .rx_drop_en = 0,
1663         };
1664
1665         dev_info->default_txconf = (struct rte_eth_txconf) {
1666                 .tx_thresh = {
1667                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1668                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1669                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1670                 },
1671                 .txq_flags = 0,
1672         };
1673
1674         dev_info->rx_desc_lim = rx_desc_lim;
1675         dev_info->tx_desc_lim = tx_desc_lim;
1676 }
1677
1678 static void
1679 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1680 {
1681         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1684         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1685         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1686         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1687                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1688                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1689                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1690         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1691                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1692                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1693                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1694                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1695                                 DEV_TX_OFFLOAD_TCP_TSO;
1696         switch (hw->mac.type) {
1697         case e1000_vfadapt:
1698                 dev_info->max_rx_queues = 2;
1699                 dev_info->max_tx_queues = 2;
1700                 break;
1701         case e1000_vfadapt_i350:
1702                 dev_info->max_rx_queues = 1;
1703                 dev_info->max_tx_queues = 1;
1704                 break;
1705         default:
1706                 /* Should not happen */
1707                 break;
1708         }
1709
1710         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1711                 .rx_thresh = {
1712                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1713                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1714                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1715                 },
1716                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1717                 .rx_drop_en = 0,
1718         };
1719
1720         dev_info->default_txconf = (struct rte_eth_txconf) {
1721                 .tx_thresh = {
1722                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1723                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1724                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1725                 },
1726                 .txq_flags = 0,
1727         };
1728
1729         dev_info->rx_desc_lim = rx_desc_lim;
1730         dev_info->tx_desc_lim = tx_desc_lim;
1731 }
1732
1733 /* return 0 means link status changed, -1 means not changed */
1734 static int
1735 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1736 {
1737         struct e1000_hw *hw =
1738                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739         struct rte_eth_link link, old;
1740         int link_check, count;
1741
1742         link_check = 0;
1743         hw->mac.get_link_status = 1;
1744
1745         /* possible wait-to-complete in up to 9 seconds */
1746         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1747                 /* Read the real link status */
1748                 switch (hw->phy.media_type) {
1749                 case e1000_media_type_copper:
1750                         /* Do the work to read phy */
1751                         e1000_check_for_link(hw);
1752                         link_check = !hw->mac.get_link_status;
1753                         break;
1754
1755                 case e1000_media_type_fiber:
1756                         e1000_check_for_link(hw);
1757                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1758                                       E1000_STATUS_LU);
1759                         break;
1760
1761                 case e1000_media_type_internal_serdes:
1762                         e1000_check_for_link(hw);
1763                         link_check = hw->mac.serdes_has_link;
1764                         break;
1765
1766                 /* VF device is type_unknown */
1767                 case e1000_media_type_unknown:
1768                         eth_igbvf_link_update(hw);
1769                         link_check = !hw->mac.get_link_status;
1770                         break;
1771
1772                 default:
1773                         break;
1774                 }
1775                 if (link_check || wait_to_complete == 0)
1776                         break;
1777                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1778         }
1779         memset(&link, 0, sizeof(link));
1780         rte_igb_dev_atomic_read_link_status(dev, &link);
1781         old = link;
1782
1783         /* Now we check if a transition has happened */
1784         if (link_check) {
1785                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1786                                           &link.link_duplex);
1787                 link.link_status = 1;
1788         } else if (!link_check) {
1789                 link.link_speed = 0;
1790                 link.link_duplex = 0;
1791                 link.link_status = 0;
1792         }
1793         rte_igb_dev_atomic_write_link_status(dev, &link);
1794
1795         /* not changed */
1796         if (old.link_status == link.link_status)
1797                 return -1;
1798
1799         /* changed */
1800         return 0;
1801 }
1802
1803 /*
1804  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1805  * For ASF and Pass Through versions of f/w this means
1806  * that the driver is loaded.
1807  */
1808 static void
1809 igb_hw_control_acquire(struct e1000_hw *hw)
1810 {
1811         uint32_t ctrl_ext;
1812
1813         /* Let firmware know the driver has taken over */
1814         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1815         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1816 }
1817
1818 /*
1819  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1820  * For ASF and Pass Through versions of f/w this means that the
1821  * driver is no longer loaded.
1822  */
1823 static void
1824 igb_hw_control_release(struct e1000_hw *hw)
1825 {
1826         uint32_t ctrl_ext;
1827
1828         /* Let firmware taken over control of h/w */
1829         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1830         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1831                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1832 }
1833
1834 /*
1835  * Bit of a misnomer, what this really means is
1836  * to enable OS management of the system... aka
1837  * to disable special hardware management features.
1838  */
1839 static void
1840 igb_init_manageability(struct e1000_hw *hw)
1841 {
1842         if (e1000_enable_mng_pass_thru(hw)) {
1843                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1844                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1845
1846                 /* disable hardware interception of ARP */
1847                 manc &= ~(E1000_MANC_ARP_EN);
1848
1849                 /* enable receiving management packets to the host */
1850                 manc |= E1000_MANC_EN_MNG2HOST;
1851                 manc2h |= 1 << 5;  /* Mng Port 623 */
1852                 manc2h |= 1 << 6;  /* Mng Port 664 */
1853                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1854                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1855         }
1856 }
1857
1858 static void
1859 igb_release_manageability(struct e1000_hw *hw)
1860 {
1861         if (e1000_enable_mng_pass_thru(hw)) {
1862                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1863
1864                 manc |= E1000_MANC_ARP_EN;
1865                 manc &= ~E1000_MANC_EN_MNG2HOST;
1866
1867                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1868         }
1869 }
1870
1871 static void
1872 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1873 {
1874         struct e1000_hw *hw =
1875                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         uint32_t rctl;
1877
1878         rctl = E1000_READ_REG(hw, E1000_RCTL);
1879         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1880         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1881 }
1882
1883 static void
1884 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
1885 {
1886         struct e1000_hw *hw =
1887                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888         uint32_t rctl;
1889
1890         rctl = E1000_READ_REG(hw, E1000_RCTL);
1891         rctl &= (~E1000_RCTL_UPE);
1892         if (dev->data->all_multicast == 1)
1893                 rctl |= E1000_RCTL_MPE;
1894         else
1895                 rctl &= (~E1000_RCTL_MPE);
1896         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1897 }
1898
1899 static void
1900 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
1901 {
1902         struct e1000_hw *hw =
1903                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         uint32_t rctl;
1905
1906         rctl = E1000_READ_REG(hw, E1000_RCTL);
1907         rctl |= E1000_RCTL_MPE;
1908         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1909 }
1910
1911 static void
1912 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1913 {
1914         struct e1000_hw *hw =
1915                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         uint32_t rctl;
1917
1918         if (dev->data->promiscuous == 1)
1919                 return; /* must remain in all_multicast mode */
1920         rctl = E1000_READ_REG(hw, E1000_RCTL);
1921         rctl &= (~E1000_RCTL_MPE);
1922         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1923 }
1924
1925 static int
1926 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1927 {
1928         struct e1000_hw *hw =
1929                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct e1000_vfta * shadow_vfta =
1931                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1932         uint32_t vfta;
1933         uint32_t vid_idx;
1934         uint32_t vid_bit;
1935
1936         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1937                               E1000_VFTA_ENTRY_MASK);
1938         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1939         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1940         if (on)
1941                 vfta |= vid_bit;
1942         else
1943                 vfta &= ~vid_bit;
1944         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1945
1946         /* update local VFTA copy */
1947         shadow_vfta->vfta[vid_idx] = vfta;
1948
1949         return 0;
1950 }
1951
1952 static void
1953 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1954 {
1955         struct e1000_hw *hw =
1956                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957         uint32_t reg = ETHER_TYPE_VLAN ;
1958
1959         reg |= (tpid << 16);
1960         E1000_WRITE_REG(hw, E1000_VET, reg);
1961 }
1962
1963 static void
1964 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1965 {
1966         struct e1000_hw *hw =
1967                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1968         uint32_t reg;
1969
1970         /* Filter Table Disable */
1971         reg = E1000_READ_REG(hw, E1000_RCTL);
1972         reg &= ~E1000_RCTL_CFIEN;
1973         reg &= ~E1000_RCTL_VFE;
1974         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1975 }
1976
1977 static void
1978 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1979 {
1980         struct e1000_hw *hw =
1981                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982         struct e1000_vfta * shadow_vfta =
1983                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1984         uint32_t reg;
1985         int i;
1986
1987         /* Filter Table Enable, CFI not used for packet acceptance */
1988         reg = E1000_READ_REG(hw, E1000_RCTL);
1989         reg &= ~E1000_RCTL_CFIEN;
1990         reg |= E1000_RCTL_VFE;
1991         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1992
1993         /* restore VFTA table */
1994         for (i = 0; i < IGB_VFTA_SIZE; i++)
1995                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1996 }
1997
1998 static void
1999 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2000 {
2001         struct e1000_hw *hw =
2002                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003         uint32_t reg;
2004
2005         /* VLAN Mode Disable */
2006         reg = E1000_READ_REG(hw, E1000_CTRL);
2007         reg &= ~E1000_CTRL_VME;
2008         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2009 }
2010
2011 static void
2012 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2013 {
2014         struct e1000_hw *hw =
2015                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016         uint32_t reg;
2017
2018         /* VLAN Mode Enable */
2019         reg = E1000_READ_REG(hw, E1000_CTRL);
2020         reg |= E1000_CTRL_VME;
2021         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2022 }
2023
2024 static void
2025 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2026 {
2027         struct e1000_hw *hw =
2028                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t reg;
2030
2031         /* CTRL_EXT: Extended VLAN */
2032         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2033         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2034         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2035
2036         /* Update maximum packet length */
2037         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2038                 E1000_WRITE_REG(hw, E1000_RLPML,
2039                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2040                                                 VLAN_TAG_SIZE);
2041 }
2042
2043 static void
2044 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2045 {
2046         struct e1000_hw *hw =
2047                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         uint32_t reg;
2049
2050         /* CTRL_EXT: Extended VLAN */
2051         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2052         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2053         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2054
2055         /* Update maximum packet length */
2056         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2057                 E1000_WRITE_REG(hw, E1000_RLPML,
2058                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2059                                                 2 * VLAN_TAG_SIZE);
2060 }
2061
2062 static void
2063 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2064 {
2065         if(mask & ETH_VLAN_STRIP_MASK){
2066                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2067                         igb_vlan_hw_strip_enable(dev);
2068                 else
2069                         igb_vlan_hw_strip_disable(dev);
2070         }
2071
2072         if(mask & ETH_VLAN_FILTER_MASK){
2073                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2074                         igb_vlan_hw_filter_enable(dev);
2075                 else
2076                         igb_vlan_hw_filter_disable(dev);
2077         }
2078
2079         if(mask & ETH_VLAN_EXTEND_MASK){
2080                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2081                         igb_vlan_hw_extend_enable(dev);
2082                 else
2083                         igb_vlan_hw_extend_disable(dev);
2084         }
2085 }
2086
2087
2088 /**
2089  * It enables the interrupt mask and then enable the interrupt.
2090  *
2091  * @param dev
2092  *  Pointer to struct rte_eth_dev.
2093  *
2094  * @return
2095  *  - On success, zero.
2096  *  - On failure, a negative value.
2097  */
2098 static int
2099 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2100 {
2101         struct e1000_interrupt *intr =
2102                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2103
2104         intr->mask |= E1000_ICR_LSC;
2105
2106         return 0;
2107 }
2108
2109 /* It clears the interrupt causes and enables the interrupt.
2110  * It will be called once only during nic initialized.
2111  *
2112  * @param dev
2113  *  Pointer to struct rte_eth_dev.
2114  *
2115  * @return
2116  *  - On success, zero.
2117  *  - On failure, a negative value.
2118  */
2119 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2120 {
2121         uint32_t mask, regval;
2122         struct e1000_hw *hw =
2123                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         struct rte_eth_dev_info dev_info;
2125
2126         memset(&dev_info, 0, sizeof(dev_info));
2127         eth_igb_infos_get(dev, &dev_info);
2128
2129         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2130         regval = E1000_READ_REG(hw, E1000_EIMS);
2131         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2132
2133         return 0;
2134 }
2135
2136 /*
2137  * It reads ICR and gets interrupt causes, check it and set a bit flag
2138  * to update link status.
2139  *
2140  * @param dev
2141  *  Pointer to struct rte_eth_dev.
2142  *
2143  * @return
2144  *  - On success, zero.
2145  *  - On failure, a negative value.
2146  */
2147 static int
2148 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2149 {
2150         uint32_t icr;
2151         struct e1000_hw *hw =
2152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         struct e1000_interrupt *intr =
2154                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2155
2156         igb_intr_disable(hw);
2157
2158         /* read-on-clear nic registers here */
2159         icr = E1000_READ_REG(hw, E1000_ICR);
2160
2161         intr->flags = 0;
2162         if (icr & E1000_ICR_LSC) {
2163                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2164         }
2165
2166         if (icr & E1000_ICR_VMMB)
2167                 intr->flags |= E1000_FLAG_MAILBOX;
2168
2169         return 0;
2170 }
2171
2172 /*
2173  * It executes link_update after knowing an interrupt is prsent.
2174  *
2175  * @param dev
2176  *  Pointer to struct rte_eth_dev.
2177  *
2178  * @return
2179  *  - On success, zero.
2180  *  - On failure, a negative value.
2181  */
2182 static int
2183 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2184 {
2185         struct e1000_hw *hw =
2186                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2187         struct e1000_interrupt *intr =
2188                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2189         uint32_t tctl, rctl;
2190         struct rte_eth_link link;
2191         int ret;
2192
2193         if (intr->flags & E1000_FLAG_MAILBOX) {
2194                 igb_pf_mbx_process(dev);
2195                 intr->flags &= ~E1000_FLAG_MAILBOX;
2196         }
2197
2198         igb_intr_enable(dev);
2199         rte_intr_enable(&(dev->pci_dev->intr_handle));
2200
2201         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2202                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2203
2204                 /* set get_link_status to check register later */
2205                 hw->mac.get_link_status = 1;
2206                 ret = eth_igb_link_update(dev, 0);
2207
2208                 /* check if link has changed */
2209                 if (ret < 0)
2210                         return 0;
2211
2212                 memset(&link, 0, sizeof(link));
2213                 rte_igb_dev_atomic_read_link_status(dev, &link);
2214                 if (link.link_status) {
2215                         PMD_INIT_LOG(INFO,
2216                                      " Port %d: Link Up - speed %u Mbps - %s",
2217                                      dev->data->port_id,
2218                                      (unsigned)link.link_speed,
2219                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2220                                      "full-duplex" : "half-duplex");
2221                 } else {
2222                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2223                                      dev->data->port_id);
2224                 }
2225
2226                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2227                              dev->pci_dev->addr.domain,
2228                              dev->pci_dev->addr.bus,
2229                              dev->pci_dev->addr.devid,
2230                              dev->pci_dev->addr.function);
2231                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2232                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2233                 if (link.link_status) {
2234                         /* enable Tx/Rx */
2235                         tctl |= E1000_TCTL_EN;
2236                         rctl |= E1000_RCTL_EN;
2237                 } else {
2238                         /* disable Tx/Rx */
2239                         tctl &= ~E1000_TCTL_EN;
2240                         rctl &= ~E1000_RCTL_EN;
2241                 }
2242                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2243                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2244                 E1000_WRITE_FLUSH(hw);
2245                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2246         }
2247
2248         return 0;
2249 }
2250
2251 /**
2252  * Interrupt handler which shall be registered at first.
2253  *
2254  * @param handle
2255  *  Pointer to interrupt handle.
2256  * @param param
2257  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2258  *
2259  * @return
2260  *  void
2261  */
2262 static void
2263 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2264                                                         void *param)
2265 {
2266         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2267
2268         eth_igb_interrupt_get_status(dev);
2269         eth_igb_interrupt_action(dev);
2270 }
2271
2272 static int
2273 eth_igb_led_on(struct rte_eth_dev *dev)
2274 {
2275         struct e1000_hw *hw;
2276
2277         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2279 }
2280
2281 static int
2282 eth_igb_led_off(struct rte_eth_dev *dev)
2283 {
2284         struct e1000_hw *hw;
2285
2286         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2288 }
2289
2290 static int
2291 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2292 {
2293         struct e1000_hw *hw;
2294         uint32_t ctrl;
2295         int tx_pause;
2296         int rx_pause;
2297
2298         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2299         fc_conf->pause_time = hw->fc.pause_time;
2300         fc_conf->high_water = hw->fc.high_water;
2301         fc_conf->low_water = hw->fc.low_water;
2302         fc_conf->send_xon = hw->fc.send_xon;
2303         fc_conf->autoneg = hw->mac.autoneg;
2304
2305         /*
2306          * Return rx_pause and tx_pause status according to actual setting of
2307          * the TFCE and RFCE bits in the CTRL register.
2308          */
2309         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2310         if (ctrl & E1000_CTRL_TFCE)
2311                 tx_pause = 1;
2312         else
2313                 tx_pause = 0;
2314
2315         if (ctrl & E1000_CTRL_RFCE)
2316                 rx_pause = 1;
2317         else
2318                 rx_pause = 0;
2319
2320         if (rx_pause && tx_pause)
2321                 fc_conf->mode = RTE_FC_FULL;
2322         else if (rx_pause)
2323                 fc_conf->mode = RTE_FC_RX_PAUSE;
2324         else if (tx_pause)
2325                 fc_conf->mode = RTE_FC_TX_PAUSE;
2326         else
2327                 fc_conf->mode = RTE_FC_NONE;
2328
2329         return 0;
2330 }
2331
2332 static int
2333 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2334 {
2335         struct e1000_hw *hw;
2336         int err;
2337         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2338                 e1000_fc_none,
2339                 e1000_fc_rx_pause,
2340                 e1000_fc_tx_pause,
2341                 e1000_fc_full
2342         };
2343         uint32_t rx_buf_size;
2344         uint32_t max_high_water;
2345         uint32_t rctl;
2346
2347         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2348         if (fc_conf->autoneg != hw->mac.autoneg)
2349                 return -ENOTSUP;
2350         rx_buf_size = igb_get_rx_buffer_size(hw);
2351         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2352
2353         /* At least reserve one Ethernet frame for watermark */
2354         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2355         if ((fc_conf->high_water > max_high_water) ||
2356             (fc_conf->high_water < fc_conf->low_water)) {
2357                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2358                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2359                 return (-EINVAL);
2360         }
2361
2362         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2363         hw->fc.pause_time     = fc_conf->pause_time;
2364         hw->fc.high_water     = fc_conf->high_water;
2365         hw->fc.low_water      = fc_conf->low_water;
2366         hw->fc.send_xon       = fc_conf->send_xon;
2367
2368         err = e1000_setup_link_generic(hw);
2369         if (err == E1000_SUCCESS) {
2370
2371                 /* check if we want to forward MAC frames - driver doesn't have native
2372                  * capability to do that, so we'll write the registers ourselves */
2373
2374                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2375
2376                 /* set or clear MFLCN.PMCF bit depending on configuration */
2377                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2378                         rctl |= E1000_RCTL_PMCF;
2379                 else
2380                         rctl &= ~E1000_RCTL_PMCF;
2381
2382                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2383                 E1000_WRITE_FLUSH(hw);
2384
2385                 return 0;
2386         }
2387
2388         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2389         return (-EIO);
2390 }
2391
2392 #define E1000_RAH_POOLSEL_SHIFT      (18)
2393 static void
2394 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2395                 uint32_t index, __rte_unused uint32_t pool)
2396 {
2397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         uint32_t rah;
2399
2400         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2401         rah = E1000_READ_REG(hw, E1000_RAH(index));
2402         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2403         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2404 }
2405
2406 static void
2407 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2408 {
2409         uint8_t addr[ETHER_ADDR_LEN];
2410         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411
2412         memset(addr, 0, sizeof(addr));
2413
2414         e1000_rar_set(hw, addr, index);
2415 }
2416
2417 static void
2418 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2419                                 struct ether_addr *addr)
2420 {
2421         eth_igb_rar_clear(dev, 0);
2422
2423         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2424 }
2425 /*
2426  * Virtual Function operations
2427  */
2428 static void
2429 igbvf_intr_disable(struct e1000_hw *hw)
2430 {
2431         PMD_INIT_FUNC_TRACE();
2432
2433         /* Clear interrupt mask to stop from interrupts being generated */
2434         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2435
2436         E1000_WRITE_FLUSH(hw);
2437 }
2438
2439 static void
2440 igbvf_stop_adapter(struct rte_eth_dev *dev)
2441 {
2442         u32 reg_val;
2443         u16 i;
2444         struct rte_eth_dev_info dev_info;
2445         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446
2447         memset(&dev_info, 0, sizeof(dev_info));
2448         eth_igbvf_infos_get(dev, &dev_info);
2449
2450         /* Clear interrupt mask to stop from interrupts being generated */
2451         igbvf_intr_disable(hw);
2452
2453         /* Clear any pending interrupts, flush previous writes */
2454         E1000_READ_REG(hw, E1000_EICR);
2455
2456         /* Disable the transmit unit.  Each queue must be disabled. */
2457         for (i = 0; i < dev_info.max_tx_queues; i++)
2458                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2459
2460         /* Disable the receive unit by stopping each queue */
2461         for (i = 0; i < dev_info.max_rx_queues; i++) {
2462                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2463                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2464                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2465                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2466                         ;
2467         }
2468
2469         /* flush all queues disables */
2470         E1000_WRITE_FLUSH(hw);
2471         msec_delay(2);
2472 }
2473
2474 static int eth_igbvf_link_update(struct e1000_hw *hw)
2475 {
2476         struct e1000_mbx_info *mbx = &hw->mbx;
2477         struct e1000_mac_info *mac = &hw->mac;
2478         int ret_val = E1000_SUCCESS;
2479
2480         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2481
2482         /*
2483          * We only want to run this if there has been a rst asserted.
2484          * in this case that could mean a link change, device reset,
2485          * or a virtual function reset
2486          */
2487
2488         /* If we were hit with a reset or timeout drop the link */
2489         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2490                 mac->get_link_status = TRUE;
2491
2492         if (!mac->get_link_status)
2493                 goto out;
2494
2495         /* if link status is down no point in checking to see if pf is up */
2496         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2497                 goto out;
2498
2499         /* if we passed all the tests above then the link is up and we no
2500          * longer need to check for link */
2501         mac->get_link_status = FALSE;
2502
2503 out:
2504         return ret_val;
2505 }
2506
2507
2508 static int
2509 igbvf_dev_configure(struct rte_eth_dev *dev)
2510 {
2511         struct rte_eth_conf* conf = &dev->data->dev_conf;
2512
2513         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2514                      dev->data->port_id);
2515
2516         /*
2517          * VF has no ability to enable/disable HW CRC
2518          * Keep the persistent behavior the same as Host PF
2519          */
2520 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2521         if (!conf->rxmode.hw_strip_crc) {
2522                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2523                 conf->rxmode.hw_strip_crc = 1;
2524         }
2525 #else
2526         if (conf->rxmode.hw_strip_crc) {
2527                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2528                 conf->rxmode.hw_strip_crc = 0;
2529         }
2530 #endif
2531
2532         return 0;
2533 }
2534
2535 static int
2536 igbvf_dev_start(struct rte_eth_dev *dev)
2537 {
2538         struct e1000_hw *hw =
2539                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2540         struct e1000_adapter *adapter =
2541                 E1000_DEV_PRIVATE(dev->data->dev_private);
2542         int ret;
2543
2544         PMD_INIT_FUNC_TRACE();
2545
2546         hw->mac.ops.reset_hw(hw);
2547         adapter->stopped = 0;
2548
2549         /* Set all vfta */
2550         igbvf_set_vfta_all(dev,1);
2551
2552         eth_igbvf_tx_init(dev);
2553
2554         /* This can fail when allocating mbufs for descriptor rings */
2555         ret = eth_igbvf_rx_init(dev);
2556         if (ret) {
2557                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2558                 igb_dev_clear_queues(dev);
2559                 return ret;
2560         }
2561
2562         return 0;
2563 }
2564
2565 static void
2566 igbvf_dev_stop(struct rte_eth_dev *dev)
2567 {
2568         PMD_INIT_FUNC_TRACE();
2569
2570         igbvf_stop_adapter(dev);
2571
2572         /*
2573           * Clear what we set, but we still keep shadow_vfta to
2574           * restore after device starts
2575           */
2576         igbvf_set_vfta_all(dev,0);
2577
2578         igb_dev_clear_queues(dev);
2579 }
2580
2581 static void
2582 igbvf_dev_close(struct rte_eth_dev *dev)
2583 {
2584         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         struct e1000_adapter *adapter =
2586                 E1000_DEV_PRIVATE(dev->data->dev_private);
2587
2588         PMD_INIT_FUNC_TRACE();
2589
2590         e1000_reset_hw(hw);
2591
2592         igbvf_dev_stop(dev);
2593         adapter->stopped = 1;
2594         igb_dev_free_queues(dev);
2595 }
2596
2597 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2598 {
2599         struct e1000_mbx_info *mbx = &hw->mbx;
2600         uint32_t msgbuf[2];
2601
2602         /* After set vlan, vlan strip will also be enabled in igb driver*/
2603         msgbuf[0] = E1000_VF_SET_VLAN;
2604         msgbuf[1] = vid;
2605         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2606         if (on)
2607                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2608
2609         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2610 }
2611
2612 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2613 {
2614         struct e1000_hw *hw =
2615                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct e1000_vfta * shadow_vfta =
2617                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2618         int i = 0, j = 0, vfta = 0, mask = 1;
2619
2620         for (i = 0; i < IGB_VFTA_SIZE; i++){
2621                 vfta = shadow_vfta->vfta[i];
2622                 if(vfta){
2623                         mask = 1;
2624                         for (j = 0; j < 32; j++){
2625                                 if(vfta & mask)
2626                                         igbvf_set_vfta(hw,
2627                                                 (uint16_t)((i<<5)+j), on);
2628                                 mask<<=1;
2629                         }
2630                 }
2631         }
2632
2633 }
2634
2635 static int
2636 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2637 {
2638         struct e1000_hw *hw =
2639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct e1000_vfta * shadow_vfta =
2641                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2642         uint32_t vid_idx = 0;
2643         uint32_t vid_bit = 0;
2644         int ret = 0;
2645
2646         PMD_INIT_FUNC_TRACE();
2647
2648         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2649         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2650         if(ret){
2651                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2652                 return ret;
2653         }
2654         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2655         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2656
2657         /*Save what we set and retore it after device reset*/
2658         if (on)
2659                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2660         else
2661                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2662
2663         return 0;
2664 }
2665
2666 static void
2667 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2668 {
2669         struct e1000_hw *hw =
2670                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671
2672         /* index is not used by rar_set() */
2673         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2674 }
2675
2676
2677 static int
2678 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2679                         struct rte_eth_rss_reta_entry64 *reta_conf,
2680                         uint16_t reta_size)
2681 {
2682         uint8_t i, j, mask;
2683         uint32_t reta, r;
2684         uint16_t idx, shift;
2685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686
2687         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2688                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2689                         "(%d) doesn't match the number hardware can supported "
2690                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2691                 return -EINVAL;
2692         }
2693
2694         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2695                 idx = i / RTE_RETA_GROUP_SIZE;
2696                 shift = i % RTE_RETA_GROUP_SIZE;
2697                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2698                                                 IGB_4_BIT_MASK);
2699                 if (!mask)
2700                         continue;
2701                 if (mask == IGB_4_BIT_MASK)
2702                         r = 0;
2703                 else
2704                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2705                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2706                         if (mask & (0x1 << j))
2707                                 reta |= reta_conf[idx].reta[shift + j] <<
2708                                                         (CHAR_BIT * j);
2709                         else
2710                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2711                 }
2712                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2713         }
2714
2715         return 0;
2716 }
2717
2718 static int
2719 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2720                        struct rte_eth_rss_reta_entry64 *reta_conf,
2721                        uint16_t reta_size)
2722 {
2723         uint8_t i, j, mask;
2724         uint32_t reta;
2725         uint16_t idx, shift;
2726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727
2728         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2729                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2730                         "(%d) doesn't match the number hardware can supported "
2731                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2732                 return -EINVAL;
2733         }
2734
2735         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2736                 idx = i / RTE_RETA_GROUP_SIZE;
2737                 shift = i % RTE_RETA_GROUP_SIZE;
2738                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2739                                                 IGB_4_BIT_MASK);
2740                 if (!mask)
2741                         continue;
2742                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2743                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2744                         if (mask & (0x1 << j))
2745                                 reta_conf[idx].reta[shift + j] =
2746                                         ((reta >> (CHAR_BIT * j)) &
2747                                                 IGB_8_BIT_MASK);
2748                 }
2749         }
2750
2751         return 0;
2752 }
2753
2754 #define MAC_TYPE_FILTER_SUP(type)    do {\
2755         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2756                 (type) != e1000_82576)\
2757                 return -ENOTSUP;\
2758 } while (0)
2759
2760 static int
2761 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2762                         struct rte_eth_syn_filter *filter,
2763                         bool add)
2764 {
2765         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766         uint32_t synqf, rfctl;
2767
2768         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2769                 return -EINVAL;
2770
2771         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2772
2773         if (add) {
2774                 if (synqf & E1000_SYN_FILTER_ENABLE)
2775                         return -EINVAL;
2776
2777                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2778                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2779
2780                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2781                 if (filter->hig_pri)
2782                         rfctl |= E1000_RFCTL_SYNQFP;
2783                 else
2784                         rfctl &= ~E1000_RFCTL_SYNQFP;
2785
2786                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2787         } else {
2788                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2789                         return -ENOENT;
2790                 synqf = 0;
2791         }
2792
2793         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2794         E1000_WRITE_FLUSH(hw);
2795         return 0;
2796 }
2797
2798 static int
2799 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2800                         struct rte_eth_syn_filter *filter)
2801 {
2802         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         uint32_t synqf, rfctl;
2804
2805         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2806         if (synqf & E1000_SYN_FILTER_ENABLE) {
2807                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2808                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2809                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2810                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2811                 return 0;
2812         }
2813
2814         return -ENOENT;
2815 }
2816
2817 static int
2818 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2819                         enum rte_filter_op filter_op,
2820                         void *arg)
2821 {
2822         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         int ret;
2824
2825         MAC_TYPE_FILTER_SUP(hw->mac.type);
2826
2827         if (filter_op == RTE_ETH_FILTER_NOP)
2828                 return 0;
2829
2830         if (arg == NULL) {
2831                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2832                             filter_op);
2833                 return -EINVAL;
2834         }
2835
2836         switch (filter_op) {
2837         case RTE_ETH_FILTER_ADD:
2838                 ret = eth_igb_syn_filter_set(dev,
2839                                 (struct rte_eth_syn_filter *)arg,
2840                                 TRUE);
2841                 break;
2842         case RTE_ETH_FILTER_DELETE:
2843                 ret = eth_igb_syn_filter_set(dev,
2844                                 (struct rte_eth_syn_filter *)arg,
2845                                 FALSE);
2846                 break;
2847         case RTE_ETH_FILTER_GET:
2848                 ret = eth_igb_syn_filter_get(dev,
2849                                 (struct rte_eth_syn_filter *)arg);
2850                 break;
2851         default:
2852                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2853                 ret = -EINVAL;
2854                 break;
2855         }
2856
2857         return ret;
2858 }
2859
2860 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2861         if ((type) != e1000_82580 && (type) != e1000_i350)\
2862                 return -ENOSYS; \
2863 } while (0)
2864
2865 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2866 static inline int
2867 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2868                         struct e1000_2tuple_filter_info *filter_info)
2869 {
2870         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2871                 return -EINVAL;
2872         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2873                 return -EINVAL;  /* filter index is out of range. */
2874         if (filter->tcp_flags > TCP_FLAG_ALL)
2875                 return -EINVAL;  /* flags is invalid. */
2876
2877         switch (filter->dst_port_mask) {
2878         case UINT16_MAX:
2879                 filter_info->dst_port_mask = 0;
2880                 filter_info->dst_port = filter->dst_port;
2881                 break;
2882         case 0:
2883                 filter_info->dst_port_mask = 1;
2884                 break;
2885         default:
2886                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2887                 return -EINVAL;
2888         }
2889
2890         switch (filter->proto_mask) {
2891         case UINT8_MAX:
2892                 filter_info->proto_mask = 0;
2893                 filter_info->proto = filter->proto;
2894                 break;
2895         case 0:
2896                 filter_info->proto_mask = 1;
2897                 break;
2898         default:
2899                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2900                 return -EINVAL;
2901         }
2902
2903         filter_info->priority = (uint8_t)filter->priority;
2904         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
2905                 filter_info->tcp_flags = filter->tcp_flags;
2906         else
2907                 filter_info->tcp_flags = 0;
2908
2909         return 0;
2910 }
2911
2912 static inline struct e1000_2tuple_filter *
2913 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
2914                         struct e1000_2tuple_filter_info *key)
2915 {
2916         struct e1000_2tuple_filter *it;
2917
2918         TAILQ_FOREACH(it, filter_list, entries) {
2919                 if (memcmp(key, &it->filter_info,
2920                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
2921                         return it;
2922                 }
2923         }
2924         return NULL;
2925 }
2926
2927 /*
2928  * igb_add_2tuple_filter - add a 2tuple filter
2929  *
2930  * @param
2931  * dev: Pointer to struct rte_eth_dev.
2932  * ntuple_filter: ponter to the filter that will be added.
2933  *
2934  * @return
2935  *    - On success, zero.
2936  *    - On failure, a negative value.
2937  */
2938 static int
2939 igb_add_2tuple_filter(struct rte_eth_dev *dev,
2940                         struct rte_eth_ntuple_filter *ntuple_filter)
2941 {
2942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943         struct e1000_filter_info *filter_info =
2944                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2945         struct e1000_2tuple_filter *filter;
2946         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
2947         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
2948         int i, ret;
2949
2950         filter = rte_zmalloc("e1000_2tuple_filter",
2951                         sizeof(struct e1000_2tuple_filter), 0);
2952         if (filter == NULL)
2953                 return -ENOMEM;
2954
2955         ret = ntuple_filter_to_2tuple(ntuple_filter,
2956                                       &filter->filter_info);
2957         if (ret < 0) {
2958                 rte_free(filter);
2959                 return ret;
2960         }
2961         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
2962                                          &filter->filter_info) != NULL) {
2963                 PMD_DRV_LOG(ERR, "filter exists.");
2964                 rte_free(filter);
2965                 return -EEXIST;
2966         }
2967         filter->queue = ntuple_filter->queue;
2968
2969         /*
2970          * look for an unused 2tuple filter index,
2971          * and insert the filter to list.
2972          */
2973         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
2974                 if (!(filter_info->twotuple_mask & (1 << i))) {
2975                         filter_info->twotuple_mask |= 1 << i;
2976                         filter->index = i;
2977                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
2978                                           filter,
2979                                           entries);
2980                         break;
2981                 }
2982         }
2983         if (i >= E1000_MAX_TTQF_FILTERS) {
2984                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
2985                 rte_free(filter);
2986                 return -ENOSYS;
2987         }
2988
2989         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
2990         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
2991                 imir |= E1000_IMIR_PORT_BP;
2992         else
2993                 imir &= ~E1000_IMIR_PORT_BP;
2994
2995         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
2996
2997         ttqf |= E1000_TTQF_QUEUE_ENABLE;
2998         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
2999         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3000         if (filter->filter_info.proto_mask == 0)
3001                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3002
3003         /* tcp flags bits setting. */
3004         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3005                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3006                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3007                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3008                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3009                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3010                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3011                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3012                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3013                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3014                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3015                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3016                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3017         } else
3018                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3019         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3020         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3021         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3022         return 0;
3023 }
3024
3025 /*
3026  * igb_remove_2tuple_filter - remove a 2tuple filter
3027  *
3028  * @param
3029  * dev: Pointer to struct rte_eth_dev.
3030  * ntuple_filter: ponter to the filter that will be removed.
3031  *
3032  * @return
3033  *    - On success, zero.
3034  *    - On failure, a negative value.
3035  */
3036 static int
3037 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3038                         struct rte_eth_ntuple_filter *ntuple_filter)
3039 {
3040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3041         struct e1000_filter_info *filter_info =
3042                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3043         struct e1000_2tuple_filter_info filter_2tuple;
3044         struct e1000_2tuple_filter *filter;
3045         int ret;
3046
3047         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3048         ret = ntuple_filter_to_2tuple(ntuple_filter,
3049                                       &filter_2tuple);
3050         if (ret < 0)
3051                 return ret;
3052
3053         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3054                                          &filter_2tuple);
3055         if (filter == NULL) {
3056                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3057                 return -ENOENT;
3058         }
3059
3060         filter_info->twotuple_mask &= ~(1 << filter->index);
3061         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3062         rte_free(filter);
3063
3064         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3065         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3066         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3067         return 0;
3068 }
3069
3070 static inline struct e1000_flex_filter *
3071 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3072                         struct e1000_flex_filter_info *key)
3073 {
3074         struct e1000_flex_filter *it;
3075
3076         TAILQ_FOREACH(it, filter_list, entries) {
3077                 if (memcmp(key, &it->filter_info,
3078                         sizeof(struct e1000_flex_filter_info)) == 0)
3079                         return it;
3080         }
3081
3082         return NULL;
3083 }
3084
3085 static int
3086 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3087                         struct rte_eth_flex_filter *filter,
3088                         bool add)
3089 {
3090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         struct e1000_filter_info *filter_info =
3092                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3093         struct e1000_flex_filter *flex_filter, *it;
3094         uint32_t wufc, queueing, mask;
3095         uint32_t reg_off;
3096         uint8_t shift, i, j = 0;
3097
3098         flex_filter = rte_zmalloc("e1000_flex_filter",
3099                         sizeof(struct e1000_flex_filter), 0);
3100         if (flex_filter == NULL)
3101                 return -ENOMEM;
3102
3103         flex_filter->filter_info.len = filter->len;
3104         flex_filter->filter_info.priority = filter->priority;
3105         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3106         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3107                 mask = 0;
3108                 /* reverse bits in flex filter's mask*/
3109                 for (shift = 0; shift < CHAR_BIT; shift++) {
3110                         if (filter->mask[i] & (0x01 << shift))
3111                                 mask |= (0x80 >> shift);
3112                 }
3113                 flex_filter->filter_info.mask[i] = mask;
3114         }
3115
3116         wufc = E1000_READ_REG(hw, E1000_WUFC);
3117         if (flex_filter->index < E1000_MAX_FHFT)
3118                 reg_off = E1000_FHFT(flex_filter->index);
3119         else
3120                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3121
3122         if (add) {
3123                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3124                                 &flex_filter->filter_info) != NULL) {
3125                         PMD_DRV_LOG(ERR, "filter exists.");
3126                         rte_free(flex_filter);
3127                         return -EEXIST;
3128                 }
3129                 flex_filter->queue = filter->queue;
3130                 /*
3131                  * look for an unused flex filter index
3132                  * and insert the filter into the list.
3133                  */
3134                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3135                         if (!(filter_info->flex_mask & (1 << i))) {
3136                                 filter_info->flex_mask |= 1 << i;
3137                                 flex_filter->index = i;
3138                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3139                                         flex_filter,
3140                                         entries);
3141                                 break;
3142                         }
3143                 }
3144                 if (i >= E1000_MAX_FLEX_FILTERS) {
3145                         PMD_DRV_LOG(ERR, "flex filters are full.");
3146                         rte_free(flex_filter);
3147                         return -ENOSYS;
3148                 }
3149
3150                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3151                                 (E1000_WUFC_FLX0 << flex_filter->index));
3152                 queueing = filter->len |
3153                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3154                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3155                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3156                                 queueing);
3157                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3158                         E1000_WRITE_REG(hw, reg_off,
3159                                         flex_filter->filter_info.dwords[j]);
3160                         reg_off += sizeof(uint32_t);
3161                         E1000_WRITE_REG(hw, reg_off,
3162                                         flex_filter->filter_info.dwords[++j]);
3163                         reg_off += sizeof(uint32_t);
3164                         E1000_WRITE_REG(hw, reg_off,
3165                                 (uint32_t)flex_filter->filter_info.mask[i]);
3166                         reg_off += sizeof(uint32_t) * 2;
3167                         ++j;
3168                 }
3169         } else {
3170                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3171                                 &flex_filter->filter_info);
3172                 if (it == NULL) {
3173                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3174                         rte_free(flex_filter);
3175                         return -ENOENT;
3176                 }
3177
3178                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3179                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3180                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3181                         (~(E1000_WUFC_FLX0 << it->index)));
3182
3183                 filter_info->flex_mask &= ~(1 << it->index);
3184                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3185                 rte_free(it);
3186                 rte_free(flex_filter);
3187         }
3188
3189         return 0;
3190 }
3191
3192 static int
3193 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3194                         struct rte_eth_flex_filter *filter)
3195 {
3196         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197         struct e1000_filter_info *filter_info =
3198                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3199         struct e1000_flex_filter flex_filter, *it;
3200         uint32_t wufc, queueing, wufc_en = 0;
3201
3202         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3203         flex_filter.filter_info.len = filter->len;
3204         flex_filter.filter_info.priority = filter->priority;
3205         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3206         memcpy(flex_filter.filter_info.mask, filter->mask,
3207                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3208
3209         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3210                                 &flex_filter.filter_info);
3211         if (it == NULL) {
3212                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3213                 return -ENOENT;
3214         }
3215
3216         wufc = E1000_READ_REG(hw, E1000_WUFC);
3217         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3218
3219         if ((wufc & wufc_en) == wufc_en) {
3220                 uint32_t reg_off = 0;
3221                 if (it->index < E1000_MAX_FHFT)
3222                         reg_off = E1000_FHFT(it->index);
3223                 else
3224                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3225
3226                 queueing = E1000_READ_REG(hw,
3227                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3228                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3229                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3230                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3231                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3232                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3233                 return 0;
3234         }
3235         return -ENOENT;
3236 }
3237
3238 static int
3239 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3240                         enum rte_filter_op filter_op,
3241                         void *arg)
3242 {
3243         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3244         struct rte_eth_flex_filter *filter;
3245         int ret = 0;
3246
3247         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3248
3249         if (filter_op == RTE_ETH_FILTER_NOP)
3250                 return ret;
3251
3252         if (arg == NULL) {
3253                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3254                             filter_op);
3255                 return -EINVAL;
3256         }
3257
3258         filter = (struct rte_eth_flex_filter *)arg;
3259         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3260             || filter->len % sizeof(uint64_t) != 0) {
3261                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3262                 return -EINVAL;
3263         }
3264         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3265                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3266                 return -EINVAL;
3267         }
3268
3269         switch (filter_op) {
3270         case RTE_ETH_FILTER_ADD:
3271                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3272                 break;
3273         case RTE_ETH_FILTER_DELETE:
3274                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3275                 break;
3276         case RTE_ETH_FILTER_GET:
3277                 ret = eth_igb_get_flex_filter(dev, filter);
3278                 break;
3279         default:
3280                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3281                 ret = -EINVAL;
3282                 break;
3283         }
3284
3285         return ret;
3286 }
3287
3288 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3289 static inline int
3290 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3291                         struct e1000_5tuple_filter_info *filter_info)
3292 {
3293         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3294                 return -EINVAL;
3295         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3296                 return -EINVAL;  /* filter index is out of range. */
3297         if (filter->tcp_flags > TCP_FLAG_ALL)
3298                 return -EINVAL;  /* flags is invalid. */
3299
3300         switch (filter->dst_ip_mask) {
3301         case UINT32_MAX:
3302                 filter_info->dst_ip_mask = 0;
3303                 filter_info->dst_ip = filter->dst_ip;
3304                 break;
3305         case 0:
3306                 filter_info->dst_ip_mask = 1;
3307                 break;
3308         default:
3309                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3310                 return -EINVAL;
3311         }
3312
3313         switch (filter->src_ip_mask) {
3314         case UINT32_MAX:
3315                 filter_info->src_ip_mask = 0;
3316                 filter_info->src_ip = filter->src_ip;
3317                 break;
3318         case 0:
3319                 filter_info->src_ip_mask = 1;
3320                 break;
3321         default:
3322                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3323                 return -EINVAL;
3324         }
3325
3326         switch (filter->dst_port_mask) {
3327         case UINT16_MAX:
3328                 filter_info->dst_port_mask = 0;
3329                 filter_info->dst_port = filter->dst_port;
3330                 break;
3331         case 0:
3332                 filter_info->dst_port_mask = 1;
3333                 break;
3334         default:
3335                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3336                 return -EINVAL;
3337         }
3338
3339         switch (filter->src_port_mask) {
3340         case UINT16_MAX:
3341                 filter_info->src_port_mask = 0;
3342                 filter_info->src_port = filter->src_port;
3343                 break;
3344         case 0:
3345                 filter_info->src_port_mask = 1;
3346                 break;
3347         default:
3348                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3349                 return -EINVAL;
3350         }
3351
3352         switch (filter->proto_mask) {
3353         case UINT8_MAX:
3354                 filter_info->proto_mask = 0;
3355                 filter_info->proto = filter->proto;
3356                 break;
3357         case 0:
3358                 filter_info->proto_mask = 1;
3359                 break;
3360         default:
3361                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3362                 return -EINVAL;
3363         }
3364
3365         filter_info->priority = (uint8_t)filter->priority;
3366         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3367                 filter_info->tcp_flags = filter->tcp_flags;
3368         else
3369                 filter_info->tcp_flags = 0;
3370
3371         return 0;
3372 }
3373
3374 static inline struct e1000_5tuple_filter *
3375 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3376                         struct e1000_5tuple_filter_info *key)
3377 {
3378         struct e1000_5tuple_filter *it;
3379
3380         TAILQ_FOREACH(it, filter_list, entries) {
3381                 if (memcmp(key, &it->filter_info,
3382                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3383                         return it;
3384                 }
3385         }
3386         return NULL;
3387 }
3388
3389 /*
3390  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3391  *
3392  * @param
3393  * dev: Pointer to struct rte_eth_dev.
3394  * ntuple_filter: ponter to the filter that will be added.
3395  *
3396  * @return
3397  *    - On success, zero.
3398  *    - On failure, a negative value.
3399  */
3400 static int
3401 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3402                         struct rte_eth_ntuple_filter *ntuple_filter)
3403 {
3404         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405         struct e1000_filter_info *filter_info =
3406                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3407         struct e1000_5tuple_filter *filter;
3408         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3409         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3410         uint8_t i;
3411         int ret;
3412
3413         filter = rte_zmalloc("e1000_5tuple_filter",
3414                         sizeof(struct e1000_5tuple_filter), 0);
3415         if (filter == NULL)
3416                 return -ENOMEM;
3417
3418         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3419                                             &filter->filter_info);
3420         if (ret < 0) {
3421                 rte_free(filter);
3422                 return ret;
3423         }
3424
3425         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3426                                          &filter->filter_info) != NULL) {
3427                 PMD_DRV_LOG(ERR, "filter exists.");
3428                 rte_free(filter);
3429                 return -EEXIST;
3430         }
3431         filter->queue = ntuple_filter->queue;
3432
3433         /*
3434          * look for an unused 5tuple filter index,
3435          * and insert the filter to list.
3436          */
3437         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3438                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3439                         filter_info->fivetuple_mask |= 1 << i;
3440                         filter->index = i;
3441                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3442                                           filter,
3443                                           entries);
3444                         break;
3445                 }
3446         }
3447         if (i >= E1000_MAX_FTQF_FILTERS) {
3448                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3449                 rte_free(filter);
3450                 return -ENOSYS;
3451         }
3452
3453         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3454         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3455                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3456         if (filter->filter_info.dst_ip_mask == 0)
3457                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3458         if (filter->filter_info.src_port_mask == 0)
3459                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3460         if (filter->filter_info.proto_mask == 0)
3461                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3462         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3463                 E1000_FTQF_QUEUE_MASK;
3464         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3465         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3466         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3467         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3468
3469         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3470         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3471
3472         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3473         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3474                 imir |= E1000_IMIR_PORT_BP;
3475         else
3476                 imir &= ~E1000_IMIR_PORT_BP;
3477         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3478
3479         /* tcp flags bits setting. */
3480         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3481                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3482                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3483                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3484                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3485                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3486                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3487                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3488                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3489                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3490                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3491                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3492                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3493         } else
3494                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3495         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3496         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3497         return 0;
3498 }
3499
3500 /*
3501  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3502  *
3503  * @param
3504  * dev: Pointer to struct rte_eth_dev.
3505  * ntuple_filter: ponter to the filter that will be removed.
3506  *
3507  * @return
3508  *    - On success, zero.
3509  *    - On failure, a negative value.
3510  */
3511 static int
3512 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3513                                 struct rte_eth_ntuple_filter *ntuple_filter)
3514 {
3515         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3516         struct e1000_filter_info *filter_info =
3517                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3518         struct e1000_5tuple_filter_info filter_5tuple;
3519         struct e1000_5tuple_filter *filter;
3520         int ret;
3521
3522         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3523         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3524                                             &filter_5tuple);
3525         if (ret < 0)
3526                 return ret;
3527
3528         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3529                                          &filter_5tuple);
3530         if (filter == NULL) {
3531                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3532                 return -ENOENT;
3533         }
3534
3535         filter_info->fivetuple_mask &= ~(1 << filter->index);
3536         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3537         rte_free(filter);
3538
3539         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3540                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3541         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3542         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3543         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3544         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3545         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3546         return 0;
3547 }
3548
3549 static int
3550 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3551 {
3552         uint32_t rctl;
3553         struct e1000_hw *hw;
3554         struct rte_eth_dev_info dev_info;
3555         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3556                                      VLAN_TAG_SIZE);
3557
3558         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559
3560 #ifdef RTE_LIBRTE_82571_SUPPORT
3561         /* XXX: not bigger than max_rx_pktlen */
3562         if (hw->mac.type == e1000_82571)
3563                 return -ENOTSUP;
3564 #endif
3565         eth_igb_infos_get(dev, &dev_info);
3566
3567         /* check that mtu is within the allowed range */
3568         if ((mtu < ETHER_MIN_MTU) ||
3569             (frame_size > dev_info.max_rx_pktlen))
3570                 return -EINVAL;
3571
3572         /* refuse mtu that requires the support of scattered packets when this
3573          * feature has not been enabled before. */
3574         if (!dev->data->scattered_rx &&
3575             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3576                 return -EINVAL;
3577
3578         rctl = E1000_READ_REG(hw, E1000_RCTL);
3579
3580         /* switch to jumbo mode if needed */
3581         if (frame_size > ETHER_MAX_LEN) {
3582                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3583                 rctl |= E1000_RCTL_LPE;
3584         } else {
3585                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3586                 rctl &= ~E1000_RCTL_LPE;
3587         }
3588         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3589
3590         /* update max frame size */
3591         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3592
3593         E1000_WRITE_REG(hw, E1000_RLPML,
3594                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3595
3596         return 0;
3597 }
3598
3599 /*
3600  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3601  *
3602  * @param
3603  * dev: Pointer to struct rte_eth_dev.
3604  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3605  * add: if true, add filter, if false, remove filter
3606  *
3607  * @return
3608  *    - On success, zero.
3609  *    - On failure, a negative value.
3610  */
3611 static int
3612 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3613                         struct rte_eth_ntuple_filter *ntuple_filter,
3614                         bool add)
3615 {
3616         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617         int ret;
3618
3619         switch (ntuple_filter->flags) {
3620         case RTE_5TUPLE_FLAGS:
3621         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3622                 if (hw->mac.type != e1000_82576)
3623                         return -ENOTSUP;
3624                 if (add)
3625                         ret = igb_add_5tuple_filter_82576(dev,
3626                                                           ntuple_filter);
3627                 else
3628                         ret = igb_remove_5tuple_filter_82576(dev,
3629                                                              ntuple_filter);
3630                 break;
3631         case RTE_2TUPLE_FLAGS:
3632         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3633                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3634                         return -ENOTSUP;
3635                 if (add)
3636                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3637                 else
3638                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3639                 break;
3640         default:
3641                 ret = -EINVAL;
3642                 break;
3643         }
3644
3645         return ret;
3646 }
3647
3648 /*
3649  * igb_get_ntuple_filter - get a ntuple filter
3650  *
3651  * @param
3652  * dev: Pointer to struct rte_eth_dev.
3653  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3654  *
3655  * @return
3656  *    - On success, zero.
3657  *    - On failure, a negative value.
3658  */
3659 static int
3660 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3661                         struct rte_eth_ntuple_filter *ntuple_filter)
3662 {
3663         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3664         struct e1000_filter_info *filter_info =
3665                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3666         struct e1000_5tuple_filter_info filter_5tuple;
3667         struct e1000_2tuple_filter_info filter_2tuple;
3668         struct e1000_5tuple_filter *p_5tuple_filter;
3669         struct e1000_2tuple_filter *p_2tuple_filter;
3670         int ret;
3671
3672         switch (ntuple_filter->flags) {
3673         case RTE_5TUPLE_FLAGS:
3674         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3675                 if (hw->mac.type != e1000_82576)
3676                         return -ENOTSUP;
3677                 memset(&filter_5tuple,
3678                         0,
3679                         sizeof(struct e1000_5tuple_filter_info));
3680                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3681                                                     &filter_5tuple);
3682                 if (ret < 0)
3683                         return ret;
3684                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3685                                         &filter_info->fivetuple_list,
3686                                         &filter_5tuple);
3687                 if (p_5tuple_filter == NULL) {
3688                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3689                         return -ENOENT;
3690                 }
3691                 ntuple_filter->queue = p_5tuple_filter->queue;
3692                 break;
3693         case RTE_2TUPLE_FLAGS:
3694         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3695                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3696                         return -ENOTSUP;
3697                 memset(&filter_2tuple,
3698                         0,
3699                         sizeof(struct e1000_2tuple_filter_info));
3700                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3701                 if (ret < 0)
3702                         return ret;
3703                 p_2tuple_filter = igb_2tuple_filter_lookup(
3704                                         &filter_info->twotuple_list,
3705                                         &filter_2tuple);
3706                 if (p_2tuple_filter == NULL) {
3707                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3708                         return -ENOENT;
3709                 }
3710                 ntuple_filter->queue = p_2tuple_filter->queue;
3711                 break;
3712         default:
3713                 ret = -EINVAL;
3714                 break;
3715         }
3716
3717         return 0;
3718 }
3719
3720 /*
3721  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3722  * @dev: pointer to rte_eth_dev structure
3723  * @filter_op:operation will be taken.
3724  * @arg: a pointer to specific structure corresponding to the filter_op
3725  */
3726 static int
3727 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3728                                 enum rte_filter_op filter_op,
3729                                 void *arg)
3730 {
3731         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732         int ret;
3733
3734         MAC_TYPE_FILTER_SUP(hw->mac.type);
3735
3736         if (filter_op == RTE_ETH_FILTER_NOP)
3737                 return 0;
3738
3739         if (arg == NULL) {
3740                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3741                             filter_op);
3742                 return -EINVAL;
3743         }
3744
3745         switch (filter_op) {
3746         case RTE_ETH_FILTER_ADD:
3747                 ret = igb_add_del_ntuple_filter(dev,
3748                         (struct rte_eth_ntuple_filter *)arg,
3749                         TRUE);
3750                 break;
3751         case RTE_ETH_FILTER_DELETE:
3752                 ret = igb_add_del_ntuple_filter(dev,
3753                         (struct rte_eth_ntuple_filter *)arg,
3754                         FALSE);
3755                 break;
3756         case RTE_ETH_FILTER_GET:
3757                 ret = igb_get_ntuple_filter(dev,
3758                         (struct rte_eth_ntuple_filter *)arg);
3759                 break;
3760         default:
3761                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3762                 ret = -EINVAL;
3763                 break;
3764         }
3765         return ret;
3766 }
3767
3768 static inline int
3769 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3770                         uint16_t ethertype)
3771 {
3772         int i;
3773
3774         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3775                 if (filter_info->ethertype_filters[i] == ethertype &&
3776                     (filter_info->ethertype_mask & (1 << i)))
3777                         return i;
3778         }
3779         return -1;
3780 }
3781
3782 static inline int
3783 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3784                         uint16_t ethertype)
3785 {
3786         int i;
3787
3788         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3789                 if (!(filter_info->ethertype_mask & (1 << i))) {
3790                         filter_info->ethertype_mask |= 1 << i;
3791                         filter_info->ethertype_filters[i] = ethertype;
3792                         return i;
3793                 }
3794         }
3795         return -1;
3796 }
3797
3798 static inline int
3799 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3800                         uint8_t idx)
3801 {
3802         if (idx >= E1000_MAX_ETQF_FILTERS)
3803                 return -1;
3804         filter_info->ethertype_mask &= ~(1 << idx);
3805         filter_info->ethertype_filters[idx] = 0;
3806         return idx;
3807 }
3808
3809
3810 static int
3811 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3812                         struct rte_eth_ethertype_filter *filter,
3813                         bool add)
3814 {
3815         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3816         struct e1000_filter_info *filter_info =
3817                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3818         uint32_t etqf = 0;
3819         int ret;
3820
3821         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3822                 filter->ether_type == ETHER_TYPE_IPv6) {
3823                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3824                         " ethertype filter.", filter->ether_type);
3825                 return -EINVAL;
3826         }
3827
3828         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3829                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3830                 return -EINVAL;
3831         }
3832         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3833                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3834                 return -EINVAL;
3835         }
3836
3837         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3838         if (ret >= 0 && add) {
3839                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3840                             filter->ether_type);
3841                 return -EEXIST;
3842         }
3843         if (ret < 0 && !add) {
3844                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3845                             filter->ether_type);
3846                 return -ENOENT;
3847         }
3848
3849         if (add) {
3850                 ret = igb_ethertype_filter_insert(filter_info,
3851                         filter->ether_type);
3852                 if (ret < 0) {
3853                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3854                         return -ENOSYS;
3855                 }
3856
3857                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3858                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3859                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3860         } else {
3861                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3862                 if (ret < 0)
3863                         return -ENOSYS;
3864         }
3865         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3866         E1000_WRITE_FLUSH(hw);
3867
3868         return 0;
3869 }
3870
3871 static int
3872 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3873                         struct rte_eth_ethertype_filter *filter)
3874 {
3875         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         struct e1000_filter_info *filter_info =
3877                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3878         uint32_t etqf;
3879         int ret;
3880
3881         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3882         if (ret < 0) {
3883                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3884                             filter->ether_type);
3885                 return -ENOENT;
3886         }
3887
3888         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
3889         if (etqf & E1000_ETQF_FILTER_ENABLE) {
3890                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
3891                 filter->flags = 0;
3892                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
3893                                 E1000_ETQF_QUEUE_SHIFT;
3894                 return 0;
3895         }
3896
3897         return -ENOENT;
3898 }
3899
3900 /*
3901  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
3902  * @dev: pointer to rte_eth_dev structure
3903  * @filter_op:operation will be taken.
3904  * @arg: a pointer to specific structure corresponding to the filter_op
3905  */
3906 static int
3907 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
3908                                 enum rte_filter_op filter_op,
3909                                 void *arg)
3910 {
3911         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912         int ret;
3913
3914         MAC_TYPE_FILTER_SUP(hw->mac.type);
3915
3916         if (filter_op == RTE_ETH_FILTER_NOP)
3917                 return 0;
3918
3919         if (arg == NULL) {
3920                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3921                             filter_op);
3922                 return -EINVAL;
3923         }
3924
3925         switch (filter_op) {
3926         case RTE_ETH_FILTER_ADD:
3927                 ret = igb_add_del_ethertype_filter(dev,
3928                         (struct rte_eth_ethertype_filter *)arg,
3929                         TRUE);
3930                 break;
3931         case RTE_ETH_FILTER_DELETE:
3932                 ret = igb_add_del_ethertype_filter(dev,
3933                         (struct rte_eth_ethertype_filter *)arg,
3934                         FALSE);
3935                 break;
3936         case RTE_ETH_FILTER_GET:
3937                 ret = igb_get_ethertype_filter(dev,
3938                         (struct rte_eth_ethertype_filter *)arg);
3939                 break;
3940         default:
3941                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3942                 ret = -EINVAL;
3943                 break;
3944         }
3945         return ret;
3946 }
3947
3948 static int
3949 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
3950                      enum rte_filter_type filter_type,
3951                      enum rte_filter_op filter_op,
3952                      void *arg)
3953 {
3954         int ret = -EINVAL;
3955
3956         switch (filter_type) {
3957         case RTE_ETH_FILTER_NTUPLE:
3958                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
3959                 break;
3960         case RTE_ETH_FILTER_ETHERTYPE:
3961                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
3962                 break;
3963         case RTE_ETH_FILTER_SYN:
3964                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
3965                 break;
3966         case RTE_ETH_FILTER_FLEXIBLE:
3967                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
3968                 break;
3969         default:
3970                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3971                                                         filter_type);
3972                 break;
3973         }
3974
3975         return ret;
3976 }
3977
3978 static int
3979 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
3980                          struct ether_addr *mc_addr_set,
3981                          uint32_t nb_mc_addr)
3982 {
3983         struct e1000_hw *hw;
3984
3985         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
3987         return 0;
3988 }
3989
3990 static int
3991 igb_timesync_enable(struct rte_eth_dev *dev)
3992 {
3993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994         uint32_t tsync_ctl;
3995         uint32_t tsauxc;
3996
3997         /* Enable system time for it isn't on by default. */
3998         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
3999         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4000         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4001
4002         /* Start incrementing the register used to timestamp PTP packets. */
4003         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4004
4005         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4006         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4007                         (ETHER_TYPE_1588 |
4008                          E1000_ETQF_FILTER_ENABLE |
4009                          E1000_ETQF_1588));
4010
4011         /* Enable timestamping of received PTP packets. */
4012         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4013         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4014         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4015
4016         /* Enable Timestamping of transmitted PTP packets. */
4017         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4018         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4019         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4020
4021         return 0;
4022 }
4023
4024 static int
4025 igb_timesync_disable(struct rte_eth_dev *dev)
4026 {
4027         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4028         uint32_t tsync_ctl;
4029
4030         /* Disable timestamping of transmitted PTP packets. */
4031         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4032         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4033         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4034
4035         /* Disable timestamping of received PTP packets. */
4036         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4037         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4038         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4039
4040         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4041         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4042
4043         /* Stop incrementating the System Time registers. */
4044         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4045
4046         return 0;
4047 }
4048
4049 static int
4050 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4051                                struct timespec *timestamp,
4052                                uint32_t flags __rte_unused)
4053 {
4054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t tsync_rxctl;
4056         uint32_t rx_stmpl;
4057         uint32_t rx_stmph;
4058
4059         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4060         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4061                 return -EINVAL;
4062
4063         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4064         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4065
4066         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4067         timestamp->tv_nsec = 0;
4068
4069         return  0;
4070 }
4071
4072 static int
4073 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4074                                struct timespec *timestamp)
4075 {
4076         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4077         uint32_t tsync_txctl;
4078         uint32_t tx_stmpl;
4079         uint32_t tx_stmph;
4080
4081         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4082         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4083                 return -EINVAL;
4084
4085         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4086         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4087
4088         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4089         timestamp->tv_nsec = 0;
4090
4091         return  0;
4092 }
4093
4094 static int
4095 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4096 {
4097         int count = 0;
4098         int g_ind = 0;
4099         const struct reg_info *reg_group;
4100
4101         while ((reg_group = igb_regs[g_ind++]))
4102                 count += igb_reg_group_count(reg_group);
4103
4104         return count;
4105 }
4106
4107 static int
4108 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4109 {
4110         int count = 0;
4111         int g_ind = 0;
4112         const struct reg_info *reg_group;
4113
4114         while ((reg_group = igbvf_regs[g_ind++]))
4115                 count += igb_reg_group_count(reg_group);
4116
4117         return count;
4118 }
4119
4120 static int
4121 eth_igb_get_regs(struct rte_eth_dev *dev,
4122         struct rte_dev_reg_info *regs)
4123 {
4124         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125         uint32_t *data = regs->data;
4126         int g_ind = 0;
4127         int count = 0;
4128         const struct reg_info *reg_group;
4129
4130         /* Support only full register dump */
4131         if ((regs->length == 0) ||
4132             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4133                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4134                         hw->device_id;
4135                 while ((reg_group = igb_regs[g_ind++]))
4136                         count += igb_read_regs_group(dev, &data[count],
4137                                                         reg_group);
4138                 return 0;
4139         }
4140
4141         return -ENOTSUP;
4142 }
4143
4144 static int
4145 igbvf_get_regs(struct rte_eth_dev *dev,
4146         struct rte_dev_reg_info *regs)
4147 {
4148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         uint32_t *data = regs->data;
4150         int g_ind = 0;
4151         int count = 0;
4152         const struct reg_info *reg_group;
4153
4154         /* Support only full register dump */
4155         if ((regs->length == 0) ||
4156             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4157                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4158                         hw->device_id;
4159                 while ((reg_group = igbvf_regs[g_ind++]))
4160                         count += igb_read_regs_group(dev, &data[count],
4161                                                         reg_group);
4162                 return 0;
4163         }
4164
4165         return -ENOTSUP;
4166 }
4167
4168 static int
4169 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4170 {
4171         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172
4173         /* Return unit is byte count */
4174         return hw->nvm.word_size * 2;
4175 }
4176
4177 static int
4178 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4179         struct rte_dev_eeprom_info *in_eeprom)
4180 {
4181         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182         struct e1000_nvm_info *nvm = &hw->nvm;
4183         uint16_t *data = in_eeprom->data;
4184         int first, length;
4185
4186         first = in_eeprom->offset >> 1;
4187         length = in_eeprom->length >> 1;
4188         if ((first >= hw->nvm.word_size) ||
4189             ((first + length) >= hw->nvm.word_size))
4190                 return -EINVAL;
4191
4192         in_eeprom->magic = hw->vendor_id |
4193                 ((uint32_t)hw->device_id << 16);
4194
4195         if ((nvm->ops.read) == NULL)
4196                 return -ENOTSUP;
4197
4198         return nvm->ops.read(hw, first, length, data);
4199 }
4200
4201 static int
4202 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4203         struct rte_dev_eeprom_info *in_eeprom)
4204 {
4205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206         struct e1000_nvm_info *nvm = &hw->nvm;
4207         uint16_t *data = in_eeprom->data;
4208         int first, length;
4209
4210         first = in_eeprom->offset >> 1;
4211         length = in_eeprom->length >> 1;
4212         if ((first >= hw->nvm.word_size) ||
4213             ((first + length) >= hw->nvm.word_size))
4214                 return -EINVAL;
4215
4216         in_eeprom->magic = (uint32_t)hw->vendor_id |
4217                 ((uint32_t)hw->device_id << 16);
4218
4219         if ((nvm->ops.write) == NULL)
4220                 return -ENOTSUP;
4221         return nvm->ops.write(hw,  first, length, data);
4222 }
4223
4224 static struct rte_driver pmd_igb_drv = {
4225         .type = PMD_PDEV,
4226         .init = rte_igb_pmd_init,
4227 };
4228
4229 static struct rte_driver pmd_igbvf_drv = {
4230         .type = PMD_PDEV,
4231         .init = rte_igbvf_pmd_init,
4232 };
4233
4234 static int
4235 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4236 {
4237         struct e1000_hw *hw =
4238                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239         uint32_t mask = 1 << queue_id;
4240
4241         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4242         E1000_WRITE_FLUSH(hw);
4243
4244         return 0;
4245 }
4246
4247 static int
4248 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4249 {
4250         struct e1000_hw *hw =
4251                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4252         uint32_t mask = 1 << queue_id;
4253         uint32_t regval;
4254
4255         regval = E1000_READ_REG(hw, E1000_EIMS);
4256         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4257         E1000_WRITE_FLUSH(hw);
4258
4259         rte_intr_enable(&dev->pci_dev->intr_handle);
4260
4261         return 0;
4262 }
4263
4264 static void
4265 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4266                    uint8_t index, uint8_t offset)
4267 {
4268         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4269
4270         /* clear bits */
4271         val &= ~((uint32_t)0xFF << offset);
4272
4273         /* write vector and valid bit */
4274         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4275
4276         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4277 }
4278
4279 static void
4280 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4281                            uint8_t queue, uint8_t msix_vector)
4282 {
4283         uint32_t tmp = 0;
4284
4285         if (hw->mac.type == e1000_82575) {
4286                 if (direction == 0)
4287                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4288                 else if (direction == 1)
4289                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4290                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4291         } else if (hw->mac.type == e1000_82576) {
4292                 if ((direction == 0) || (direction == 1))
4293                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4294                                            ((queue & 0x8) << 1) +
4295                                            8 * direction);
4296         } else if ((hw->mac.type == e1000_82580) ||
4297                         (hw->mac.type == e1000_i350) ||
4298                         (hw->mac.type == e1000_i354) ||
4299                         (hw->mac.type == e1000_i210) ||
4300                         (hw->mac.type == e1000_i211)) {
4301                 if ((direction == 0) || (direction == 1))
4302                         eth_igb_write_ivar(hw, msix_vector,
4303                                            queue >> 1,
4304                                            ((queue & 0x1) << 4) +
4305                                            8 * direction);
4306         }
4307 }
4308
4309 /* Sets up the hardware to generate MSI-X interrupts properly
4310  * @hw
4311  *  board private structure
4312  */
4313 static void
4314 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4315 {
4316         int queue_id;
4317         uint32_t tmpval, regval, intr_mask;
4318         struct e1000_hw *hw =
4319                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         uint32_t vec = 0;
4321         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4322
4323         /* won't configure msix register if no mapping is done
4324          * between intr vector and event fd
4325          */
4326         if (!rte_intr_dp_is_en(intr_handle))
4327                 return;
4328
4329         /* set interrupt vector for other causes */
4330         if (hw->mac.type == e1000_82575) {
4331                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4332                 /* enable MSI-X PBA support */
4333                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4334
4335                 /* Auto-Mask interrupts upon ICR read */
4336                 tmpval |= E1000_CTRL_EXT_EIAME;
4337                 tmpval |= E1000_CTRL_EXT_IRCA;
4338
4339                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4340
4341                 /* enable msix_other interrupt */
4342                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4343                 regval = E1000_READ_REG(hw, E1000_EIAC);
4344                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4345                 regval = E1000_READ_REG(hw, E1000_EIAM);
4346                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4347         } else if ((hw->mac.type == e1000_82576) ||
4348                         (hw->mac.type == e1000_82580) ||
4349                         (hw->mac.type == e1000_i350) ||
4350                         (hw->mac.type == e1000_i354) ||
4351                         (hw->mac.type == e1000_i210) ||
4352                         (hw->mac.type == e1000_i211)) {
4353                 /* turn on MSI-X capability first */
4354                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4355                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4356                                         E1000_GPIE_NSICR);
4357
4358                 intr_mask = (1 << intr_handle->max_intr) - 1;
4359                 regval = E1000_READ_REG(hw, E1000_EIAC);
4360                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4361
4362                 /* enable msix_other interrupt */
4363                 regval = E1000_READ_REG(hw, E1000_EIMS);
4364                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4365                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4366                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4367         }
4368
4369         /* use EIAM to auto-mask when MSI-X interrupt
4370          * is asserted, this saves a register write for every interrupt
4371          */
4372         intr_mask = (1 << intr_handle->nb_efd) - 1;
4373         regval = E1000_READ_REG(hw, E1000_EIAM);
4374         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4375
4376         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4377                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4378                 intr_handle->intr_vec[queue_id] = vec;
4379                 if (vec < intr_handle->nb_efd - 1)
4380                         vec++;
4381         }
4382
4383         E1000_WRITE_FLUSH(hw);
4384 }
4385
4386 PMD_REGISTER_DRIVER(pmd_igb_drv);
4387 PMD_REGISTER_DRIVER(pmd_igbvf_drv);