drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 317
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 321
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 328
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372 };
 373
 374 static const struct eth_dev_ops eth_igb_ops = {
 375         .dev_configure        = eth_igb_configure,
 376         .dev_start            = eth_igb_start,
 377         .dev_stop             = eth_igb_stop,
 378         .dev_set_link_up      = eth_igb_dev_set_link_up,
 379         .dev_set_link_down    = eth_igb_dev_set_link_down,
 380         .dev_close            = eth_igb_close,
 381         .promiscuous_enable   = eth_igb_promiscuous_enable,
 382         .promiscuous_disable  = eth_igb_promiscuous_disable,
 383         .allmulticast_enable  = eth_igb_allmulticast_enable,
 384         .allmulticast_disable = eth_igb_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igb_stats_get,
 387         .xstats_get           = eth_igb_xstats_get,
 388         .xstats_get_names     = eth_igb_xstats_get_names,
 389         .stats_reset          = eth_igb_stats_reset,
 390         .xstats_reset         = eth_igb_xstats_reset,
 391         .dev_infos_get        = eth_igb_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .mtu_set              = eth_igb_mtu_set,
 394         .vlan_filter_set      = eth_igb_vlan_filter_set,
 395         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 396         .vlan_offload_set     = eth_igb_vlan_offload_set,
 397         .rx_queue_setup       = eth_igb_rx_queue_setup,
 398         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 399         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 400         .rx_queue_release     = eth_igb_rx_queue_release,
 401         .rx_queue_count       = eth_igb_rx_queue_count,
 402         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .dev_led_on           = eth_igb_led_on,
 406         .dev_led_off          = eth_igb_led_off,
 407         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 408         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 409         .mac_addr_add         = eth_igb_rar_set,
 410         .mac_addr_remove      = eth_igb_rar_clear,
 411         .mac_addr_set         = eth_igb_default_mac_addr_set,
 412         .reta_update          = eth_igb_rss_reta_update,
 413         .reta_query           = eth_igb_rss_reta_query,
 414         .rss_hash_update      = eth_igb_rss_hash_update,
 415         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 416         .filter_ctrl          = eth_igb_filter_ctrl,
 417         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 418         .rxq_info_get         = igb_rxq_info_get,
 419         .txq_info_get         = igb_txq_info_get,
 420         .timesync_enable      = igb_timesync_enable,
 421         .timesync_disable     = igb_timesync_disable,
 422         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 423         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 424         .get_reg              = eth_igb_get_regs,
 425         .get_eeprom_length    = eth_igb_get_eeprom_length,
 426         .get_eeprom           = eth_igb_get_eeprom,
 427         .set_eeprom           = eth_igb_set_eeprom,
 428         .timesync_adjust_time = igb_timesync_adjust_time,
 429         .timesync_read_time   = igb_timesync_read_time,
 430         .timesync_write_time  = igb_timesync_write_time,
 431 };
 432
 433 /*
 434  * dev_ops for virtual function, bare necessities for basic vf
 435  * operation have been implemented
 436  */
 437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 438         .dev_configure        = igbvf_dev_configure,
 439         .dev_start            = igbvf_dev_start,
 440         .dev_stop             = igbvf_dev_stop,
 441         .dev_close            = igbvf_dev_close,
 442         .promiscuous_enable   = igbvf_promiscuous_enable,
 443         .promiscuous_disable  = igbvf_promiscuous_disable,
 444         .allmulticast_enable  = igbvf_allmulticast_enable,
 445         .allmulticast_disable = igbvf_allmulticast_disable,
 446         .link_update          = eth_igb_link_update,
 447         .stats_get            = eth_igbvf_stats_get,
 448         .xstats_get           = eth_igbvf_xstats_get,
 449         .xstats_get_names     = eth_igbvf_xstats_get_names,
 450         .stats_reset          = eth_igbvf_stats_reset,
 451         .xstats_reset         = eth_igbvf_stats_reset,
 452         .vlan_filter_set      = igbvf_vlan_filter_set,
 453         .dev_infos_get        = eth_igbvf_infos_get,
 454         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 455         .rx_queue_setup       = eth_igb_rx_queue_setup,
 456         .rx_queue_release     = eth_igb_rx_queue_release,
 457         .tx_queue_setup       = eth_igb_tx_queue_setup,
 458         .tx_queue_release     = eth_igb_tx_queue_release,
 459         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 460         .rxq_info_get         = igb_rxq_info_get,
 461         .txq_info_get         = igb_txq_info_get,
 462         .mac_addr_set         = igbvf_default_mac_addr_set,
 463         .get_reg              = igbvf_get_regs,
 464 };
 465
 466 /* store statistics names and its offset in stats structure */
 467 struct rte_igb_xstats_name_off {
 468         char name[RTE_ETH_XSTATS_NAME_SIZE];
 469         unsigned offset;
 470 };
 471
 472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 473         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 474         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 475         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 476         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 477         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 478         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 479         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 480                 ecol)},
 481         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 482         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 483         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 484         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 485         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 486         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 487         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 488         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 489         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 490         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 491         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 492                 fcruc)},
 493         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 494         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 495         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 496         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 497         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 prc1023)},
 499         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 prc1522)},
 501         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 502         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 503         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 504         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 505         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 506         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 507         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 508         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 509         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 510         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 511         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 512         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 513         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 514         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 515         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 516         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 517         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 518         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 519                 ptc1023)},
 520         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 521                 ptc1522)},
 522         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 523         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 524         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 525         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 526         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 527         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 528         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 529
 530         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 531 };
 532
 533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 534                 sizeof(rte_igb_stats_strings[0]))
 535
 536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 537         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 538         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 539         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 540         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 541         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 542 };
 543
 544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 545                 sizeof(rte_igbvf_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 static inline void
 600 igb_intr_enable(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_interrupt *intr =
 603                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 604         struct e1000_hw *hw =
 605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 608         E1000_WRITE_FLUSH(hw);
 609 }
 610
 611 static void
 612 igb_intr_disable(struct e1000_hw *hw)
 613 {
 614         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static inline void
 619 igbvf_intr_enable(struct rte_eth_dev *dev)
 620 {
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         /* only for mailbox */
 625         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 626         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_FLUSH(hw);
 629 }
 630
 631 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 632 static void
 633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 634 {
 635         uint32_t tmp = 0;
 636
 637         /* mailbox */
 638         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 639         tmp |= E1000_VTIVAR_VALID;
 640         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 641 }
 642
 643 static void
 644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 645 {
 646         struct e1000_hw *hw =
 647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 648
 649         /* Configure VF other cause ivar */
 650         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 651 }
 652
 653 static inline int32_t
 654 igb_pf_reset_hw(struct e1000_hw *hw)
 655 {
 656         uint32_t ctrl_ext;
 657         int32_t status;
 658
 659         status = e1000_reset_hw(hw);
 660
 661         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 665         E1000_WRITE_FLUSH(hw);
 666
 667         return status;
 668 }
 669
 670 static void
 671 igb_identify_hardware(struct rte_eth_dev *dev)
 672 {
 673         struct e1000_hw *hw =
 674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         hw->vendor_id = dev->pci_dev->id.vendor_id;
 677         hw->device_id = dev->pci_dev->id.device_id;
 678         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 679         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 680
 681         e1000_set_mac_type(hw);
 682
 683         /* need to check if it is a vf device below */
 684 }
 685
 686 static int
 687 igb_reset_swfw_lock(struct e1000_hw *hw)
 688 {
 689         int ret_val;
 690
 691         /*
 692          * Do mac ops initialization manually here, since we will need
 693          * some function pointers set by this call.
 694          */
 695         ret_val = e1000_init_mac_params(hw);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         /*
 700          * SMBI lock should not fail in this early stage. If this is the case,
 701          * it is due to an improper exit of the application.
 702          * So force the release of the faulty lock.
 703          */
 704         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 706         }
 707         e1000_put_hw_semaphore_generic(hw);
 708
 709         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 710                 uint16_t mask;
 711
 712                 /*
 713                  * Phy lock should not fail in this early stage. If this is the case,
 714                  * it is due to an improper exit of the application.
 715                  * So force the release of the faulty lock.
 716                  */
 717                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 718                 if (hw->bus.func > E1000_FUNC_1)
 719                         mask <<= 2;
 720                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 721                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 722                                     hw->bus.func);
 723                 }
 724                 hw->mac.ops.release_swfw_sync(hw, mask);
 725
 726                 /*
 727                  * This one is more tricky since it is common to all ports; but
 728                  * swfw_sync retries last long enough (1s) to be almost sure that if
 729                  * lock can not be taken it is due to an improper lock of the
 730                  * semaphore.
 731                  */
 732                 mask = E1000_SWFW_EEP_SM;
 733                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 734                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 735                 }
 736                 hw->mac.ops.release_swfw_sync(hw, mask);
 737         }
 738
 739         return E1000_SUCCESS;
 740 }
 741
 742 static int
 743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         int error = 0;
 746         struct rte_pci_device *pci_dev;
 747         struct e1000_hw *hw =
 748                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 749         struct e1000_vfta * shadow_vfta =
 750                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_adapter *adapter =
 754                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 755
 756         uint32_t ctrl_ext;
 757
 758         pci_dev = eth_dev->pci_dev;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct e1000_hw *hw;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return -EPERM;
 919
 920         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         pci_dev = eth_dev->pci_dev;
 922
 923         if (adapter->stopped == 0)
 924                 eth_igb_close(eth_dev);
 925
 926         eth_dev->dev_ops = NULL;
 927         eth_dev->rx_pkt_burst = NULL;
 928         eth_dev->tx_pkt_burst = NULL;
 929
 930         /* Reset any pending lock */
 931         igb_reset_swfw_lock(hw);
 932
 933         rte_free(eth_dev->data->mac_addrs);
 934         eth_dev->data->mac_addrs = NULL;
 935
 936         /* uninitialize PF if max_vfs not zero */
 937         igb_pf_host_uninit(eth_dev);
 938
 939         /* disable uio intr before callback unregister */
 940         rte_intr_disable(&(pci_dev->intr_handle));
 941         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 942                 eth_igb_interrupt_handler, (void *)eth_dev);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * Virtual Function device init
 949  */
 950 static int
 951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966
 967         /* for secondary processes, we don't initialise any further as primary
 968          * has already done this work. Only check we don't need a different
 969          * RX function */
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 971                 if (eth_dev->data->scattered_rx)
 972                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 973                 return 0;
 974         }
 975
 976         pci_dev = eth_dev->pci_dev;
 977
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1016                 if (diag) {
1017                         rte_free(eth_dev->data->mac_addrs);
1018                         eth_dev->data->mac_addrs = NULL;
1019                         return diag;
1020                 }
1021                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023                              "%02x:%02x:%02x:%02x:%02x:%02x",
1024                              perm_addr->addr_bytes[0],
1025                              perm_addr->addr_bytes[1],
1026                              perm_addr->addr_bytes[2],
1027                              perm_addr->addr_bytes[3],
1028                              perm_addr->addr_bytes[4],
1029                              perm_addr->addr_bytes[5]);
1030         }
1031
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         rte_intr_callback_register(&pci_dev->intr_handle,
1042                                    eth_igbvf_interrupt_handler,
1043                                    (void *)eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static struct eth_driver rte_igb_pmd = {
1080         .pci_drv = {
1081                 .name = "rte_igb_pmd",
1082                 .id_table = pci_id_igb_map,
1083                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1084                         RTE_PCI_DRV_DETACHABLE,
1085                 .probe = rte_eth_dev_pci_probe,
1086                 .remove = rte_eth_dev_pci_remove,
1087         },
1088         .eth_dev_init = eth_igb_dev_init,
1089         .eth_dev_uninit = eth_igb_dev_uninit,
1090         .dev_private_size = sizeof(struct e1000_adapter),
1091 };
1092
1093 /*
1094  * virtual function driver struct
1095  */
1096 static struct eth_driver rte_igbvf_pmd = {
1097         .pci_drv = {
1098                 .name = "rte_igbvf_pmd",
1099                 .id_table = pci_id_igbvf_map,
1100                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1101                 .probe = rte_eth_dev_pci_probe,
1102                 .remove = rte_eth_dev_pci_remove,
1103         },
1104         .eth_dev_init = eth_igbvf_dev_init,
1105         .eth_dev_uninit = eth_igbvf_dev_uninit,
1106         .dev_private_size = sizeof(struct e1000_adapter),
1107 };
1108
1109 static void
1110 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1111 {
1112         struct e1000_hw *hw =
1113                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1115         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1116         rctl |= E1000_RCTL_VFE;
1117         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1118 }
1119
1120 static int
1121 igb_check_mq_mode(struct rte_eth_dev *dev)
1122 {
1123         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1124         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1125         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1126         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1127
1128         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1129             tx_mq_mode == ETH_MQ_TX_DCB ||
1130             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1131                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1132                 return -EINVAL;
1133         }
1134         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1135                 /* Check multi-queue mode.
1136                  * To no break software we accept ETH_MQ_RX_NONE as this might
1137                  * be used to turn off VLAN filter.
1138                  */
1139
1140                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1141                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1142                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1143                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1144                 } else {
1145                         /* Only support one queue on VFs.
1146                          * RSS together with SRIOV is not supported.
1147                          */
1148                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1149                                         " wrong mq_mode rx %d.",
1150                                         rx_mq_mode);
1151                         return -EINVAL;
1152                 }
1153                 /* TX mode is not used here, so mode might be ignored.*/
1154                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1155                         /* SRIOV only works in VMDq enable mode */
1156                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1157                                         " TX mode %d is not supported. "
1158                                         " Driver will behave as %d mode.",
1159                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1160                 }
1161
1162                 /* check valid queue number */
1163                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1164                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1165                                         " only support one queue on VFs.");
1166                         return -EINVAL;
1167                 }
1168         } else {
1169                 /* To no break software that set invalid mode, only display
1170                  * warning if invalid mode is used.
1171                  */
1172                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1173                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1174                     rx_mq_mode != ETH_MQ_RX_RSS) {
1175                         /* RSS together with VMDq not supported*/
1176                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1177                                      rx_mq_mode);
1178                         return -EINVAL;
1179                 }
1180
1181                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1182                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1183                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1184                                         " Due to txmode is meaningless in this"
1185                                         " driver, just ignore.",
1186                                         tx_mq_mode);
1187                 }
1188         }
1189         return 0;
1190 }
1191
1192 static int
1193 eth_igb_configure(struct rte_eth_dev *dev)
1194 {
1195         struct e1000_interrupt *intr =
1196                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1197         int ret;
1198
1199         PMD_INIT_FUNC_TRACE();
1200
1201         /* multipe queue mode checking */
1202         ret  = igb_check_mq_mode(dev);
1203         if (ret != 0) {
1204                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1205                             ret);
1206                 return ret;
1207         }
1208
1209         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1210         PMD_INIT_FUNC_TRACE();
1211
1212         return 0;
1213 }
1214
1215 static int
1216 eth_igb_start(struct rte_eth_dev *dev)
1217 {
1218         struct e1000_hw *hw =
1219                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220         struct e1000_adapter *adapter =
1221                 E1000_DEV_PRIVATE(dev->data->dev_private);
1222         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1223         int ret, mask;
1224         uint32_t intr_vector = 0;
1225         uint32_t ctrl_ext;
1226         uint32_t *speeds;
1227         int num_speeds;
1228         bool autoneg;
1229
1230         PMD_INIT_FUNC_TRACE();
1231
1232         /* disable uio/vfio intr/eventfd mapping */
1233         rte_intr_disable(intr_handle);
1234
1235         /* Power up the phy. Needed to make the link go Up */
1236         eth_igb_dev_set_link_up(dev);
1237
1238         /*
1239          * Packet Buffer Allocation (PBA)
1240          * Writing PBA sets the receive portion of the buffer
1241          * the remainder is used for the transmit buffer.
1242          */
1243         if (hw->mac.type == e1000_82575) {
1244                 uint32_t pba;
1245
1246                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1247                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1248         }
1249
1250         /* Put the address into the Receive Address Array */
1251         e1000_rar_set(hw, hw->mac.addr, 0);
1252
1253         /* Initialize the hardware */
1254         if (igb_hardware_init(hw)) {
1255                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1256                 return -EIO;
1257         }
1258         adapter->stopped = 0;
1259
1260         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1261
1262         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1265         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1266         E1000_WRITE_FLUSH(hw);
1267
1268         /* configure PF module if SRIOV enabled */
1269         igb_pf_host_configure(dev);
1270
1271         /* check and configure queue intr-vector mapping */
1272         if ((rte_intr_cap_multiple(intr_handle) ||
1273              !RTE_ETH_DEV_SRIOV(dev).active) &&
1274             dev->data->dev_conf.intr_conf.rxq != 0) {
1275                 intr_vector = dev->data->nb_rx_queues;
1276                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1277                         return -1;
1278         }
1279
1280         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1281                 intr_handle->intr_vec =
1282                         rte_zmalloc("intr_vec",
1283                                     dev->data->nb_rx_queues * sizeof(int), 0);
1284                 if (intr_handle->intr_vec == NULL) {
1285                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1286                                      " intr_vec\n", dev->data->nb_rx_queues);
1287                         return -ENOMEM;
1288                 }
1289         }
1290
1291         /* confiugre msix for rx interrupt */
1292         eth_igb_configure_msix_intr(dev);
1293
1294         /* Configure for OS presence */
1295         igb_init_manageability(hw);
1296
1297         eth_igb_tx_init(dev);
1298
1299         /* This can fail when allocating mbufs for descriptor rings */
1300         ret = eth_igb_rx_init(dev);
1301         if (ret) {
1302                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1303                 igb_dev_clear_queues(dev);
1304                 return ret;
1305         }
1306
1307         e1000_clear_hw_cntrs_base_generic(hw);
1308
1309         /*
1310          * VLAN Offload Settings
1311          */
1312         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1313                         ETH_VLAN_EXTEND_MASK;
1314         eth_igb_vlan_offload_set(dev, mask);
1315
1316         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1317                 /* Enable VLAN filter since VMDq always use VLAN filter */
1318                 igb_vmdq_vlan_hw_filter_enable(dev);
1319         }
1320
1321         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1322                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1323                 (hw->mac.type == e1000_i211)) {
1324                 /* Configure EITR with the maximum possible value (0xFFFF) */
1325                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1326         }
1327
1328         /* Setup link speed and duplex */
1329         speeds = &dev->data->dev_conf.link_speeds;
1330         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1331                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1332         } else {
1333                 num_speeds = 0;
1334                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1335
1336                 /* Reset */
1337                 hw->phy.autoneg_advertised = 0;
1338
1339                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1340                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1341                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1342                         num_speeds = -1;
1343                         goto error_invalid_config;
1344                 }
1345                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1346                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1347                         num_speeds++;
1348                 }
1349                 if (*speeds & ETH_LINK_SPEED_10M) {
1350                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1351                         num_speeds++;
1352                 }
1353                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1354                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1355                         num_speeds++;
1356                 }
1357                 if (*speeds & ETH_LINK_SPEED_100M) {
1358                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1359                         num_speeds++;
1360                 }
1361                 if (*speeds & ETH_LINK_SPEED_1G) {
1362                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1363                         num_speeds++;
1364                 }
1365                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1366                         goto error_invalid_config;
1367         }
1368
1369         e1000_setup_link(hw);
1370
1371         if (rte_intr_allow_others(intr_handle)) {
1372                 /* check if lsc interrupt is enabled */
1373                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1374                         eth_igb_lsc_interrupt_setup(dev);
1375         } else {
1376                 rte_intr_callback_unregister(intr_handle,
1377                                              eth_igb_interrupt_handler,
1378                                              (void *)dev);
1379                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1380                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1381                                      " no intr multiplex\n");
1382         }
1383
1384         /* check if rxq interrupt is enabled */
1385         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1386             rte_intr_dp_is_en(intr_handle))
1387                 eth_igb_rxq_interrupt_setup(dev);
1388
1389         /* enable uio/vfio intr/eventfd mapping */
1390         rte_intr_enable(intr_handle);
1391
1392         /* resume enabled intr since hw reset */
1393         igb_intr_enable(dev);
1394
1395         PMD_INIT_LOG(DEBUG, "<<");
1396
1397         return 0;
1398
1399 error_invalid_config:
1400         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1401                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1402         igb_dev_clear_queues(dev);
1403         return -EINVAL;
1404 }
1405
1406 /*********************************************************************
1407  *
1408  *  This routine disables all traffic on the adapter by issuing a
1409  *  global reset on the MAC.
1410  *
1411  **********************************************************************/
1412 static void
1413 eth_igb_stop(struct rte_eth_dev *dev)
1414 {
1415         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1416         struct e1000_filter_info *filter_info =
1417                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1418         struct rte_eth_link link;
1419         struct e1000_flex_filter *p_flex;
1420         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1421         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1422         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1423
1424         igb_intr_disable(hw);
1425
1426         /* disable intr eventfd mapping */
1427         rte_intr_disable(intr_handle);
1428
1429         igb_pf_reset_hw(hw);
1430         E1000_WRITE_REG(hw, E1000_WUC, 0);
1431
1432         /* Set bit for Go Link disconnect */
1433         if (hw->mac.type >= e1000_82580) {
1434                 uint32_t phpm_reg;
1435
1436                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1437                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1438                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1439         }
1440
1441         /* Power down the phy. Needed to make the link go Down */
1442         eth_igb_dev_set_link_down(dev);
1443
1444         igb_dev_clear_queues(dev);
1445
1446         /* clear the recorded link status */
1447         memset(&link, 0, sizeof(link));
1448         rte_igb_dev_atomic_write_link_status(dev, &link);
1449
1450         /* Remove all flex filters of the device */
1451         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1452                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1453                 rte_free(p_flex);
1454         }
1455         filter_info->flex_mask = 0;
1456
1457         /* Remove all ntuple filters of the device */
1458         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1459              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1460                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1461                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1462                              p_5tuple, entries);
1463                 rte_free(p_5tuple);
1464         }
1465         filter_info->fivetuple_mask = 0;
1466         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1467              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1468                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1469                 TAILQ_REMOVE(&filter_info->twotuple_list,
1470                              p_2tuple, entries);
1471                 rte_free(p_2tuple);
1472         }
1473         filter_info->twotuple_mask = 0;
1474
1475         if (!rte_intr_allow_others(intr_handle))
1476                 /* resume to the default handler */
1477                 rte_intr_callback_register(intr_handle,
1478                                            eth_igb_interrupt_handler,
1479                                            (void *)dev);
1480
1481         /* Clean datapath event and queue/vec mapping */
1482         rte_intr_efd_disable(intr_handle);
1483         if (intr_handle->intr_vec != NULL) {
1484                 rte_free(intr_handle->intr_vec);
1485                 intr_handle->intr_vec = NULL;
1486         }
1487 }
1488
1489 static int
1490 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1491 {
1492         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1493
1494         if (hw->phy.media_type == e1000_media_type_copper)
1495                 e1000_power_up_phy(hw);
1496         else
1497                 e1000_power_up_fiber_serdes_link(hw);
1498
1499         return 0;
1500 }
1501
1502 static int
1503 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506
1507         if (hw->phy.media_type == e1000_media_type_copper)
1508                 e1000_power_down_phy(hw);
1509         else
1510                 e1000_shutdown_fiber_serdes_link(hw);
1511
1512         return 0;
1513 }
1514
1515 static void
1516 eth_igb_close(struct rte_eth_dev *dev)
1517 {
1518         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519         struct e1000_adapter *adapter =
1520                 E1000_DEV_PRIVATE(dev->data->dev_private);
1521         struct rte_eth_link link;
1522         struct rte_pci_device *pci_dev;
1523
1524         eth_igb_stop(dev);
1525         adapter->stopped = 1;
1526
1527         e1000_phy_hw_reset(hw);
1528         igb_release_manageability(hw);
1529         igb_hw_control_release(hw);
1530
1531         /* Clear bit for Go Link disconnect */
1532         if (hw->mac.type >= e1000_82580) {
1533                 uint32_t phpm_reg;
1534
1535                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1536                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1537                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1538         }
1539
1540         igb_dev_free_queues(dev);
1541
1542         pci_dev = dev->pci_dev;
1543         if (pci_dev->intr_handle.intr_vec) {
1544                 rte_free(pci_dev->intr_handle.intr_vec);
1545                 pci_dev->intr_handle.intr_vec = NULL;
1546         }
1547
1548         memset(&link, 0, sizeof(link));
1549         rte_igb_dev_atomic_write_link_status(dev, &link);
1550 }
1551
1552 static int
1553 igb_get_rx_buffer_size(struct e1000_hw *hw)
1554 {
1555         uint32_t rx_buf_size;
1556         if (hw->mac.type == e1000_82576) {
1557                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1558         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1559                 /* PBS needs to be translated according to a lookup table */
1560                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1561                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1562                 rx_buf_size = (rx_buf_size << 10);
1563         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1564                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1565         } else {
1566                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1567         }
1568
1569         return rx_buf_size;
1570 }
1571
1572 /*********************************************************************
1573  *
1574  *  Initialize the hardware
1575  *
1576  **********************************************************************/
1577 static int
1578 igb_hardware_init(struct e1000_hw *hw)
1579 {
1580         uint32_t rx_buf_size;
1581         int diag;
1582
1583         /* Let the firmware know the OS is in control */
1584         igb_hw_control_acquire(hw);
1585
1586         /*
1587          * These parameters control the automatic generation (Tx) and
1588          * response (Rx) to Ethernet PAUSE frames.
1589          * - High water mark should allow for at least two standard size (1518)
1590          *   frames to be received after sending an XOFF.
1591          * - Low water mark works best when it is very near the high water mark.
1592          *   This allows the receiver to restart by sending XON when it has
1593          *   drained a bit. Here we use an arbitrary value of 1500 which will
1594          *   restart after one full frame is pulled from the buffer. There
1595          *   could be several smaller frames in the buffer and if so they will
1596          *   not trigger the XON until their total number reduces the buffer
1597          *   by 1500.
1598          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1599          */
1600         rx_buf_size = igb_get_rx_buffer_size(hw);
1601
1602         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1603         hw->fc.low_water = hw->fc.high_water - 1500;
1604         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1605         hw->fc.send_xon = 1;
1606
1607         /* Set Flow control, use the tunable location if sane */
1608         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1609                 hw->fc.requested_mode = igb_fc_setting;
1610         else
1611                 hw->fc.requested_mode = e1000_fc_none;
1612
1613         /* Issue a global reset */
1614         igb_pf_reset_hw(hw);
1615         E1000_WRITE_REG(hw, E1000_WUC, 0);
1616
1617         diag = e1000_init_hw(hw);
1618         if (diag < 0)
1619                 return diag;
1620
1621         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1622         e1000_get_phy_info(hw);
1623         e1000_check_for_link(hw);
1624
1625         return 0;
1626 }
1627
1628 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1629 static void
1630 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1631 {
1632         int pause_frames;
1633
1634         uint64_t old_gprc  = stats->gprc;
1635         uint64_t old_gptc  = stats->gptc;
1636         uint64_t old_tpr   = stats->tpr;
1637         uint64_t old_tpt   = stats->tpt;
1638         uint64_t old_rpthc = stats->rpthc;
1639         uint64_t old_hgptc = stats->hgptc;
1640
1641         if(hw->phy.media_type == e1000_media_type_copper ||
1642             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1643                 stats->symerrs +=
1644                     E1000_READ_REG(hw,E1000_SYMERRS);
1645                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1646         }
1647
1648         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1649         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1650         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1651         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1652
1653         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1654         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1655         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1656         stats->dc += E1000_READ_REG(hw, E1000_DC);
1657         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1658         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1659         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1660         /*
1661         ** For watchdog management we need to know if we have been
1662         ** paused during the last interval, so capture that here.
1663         */
1664         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1665         stats->xoffrxc += pause_frames;
1666         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1667         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1668         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1669         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1670         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1671         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1672         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1673         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1674         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1675         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1676         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1677         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1678
1679         /* For the 64-bit byte counters the low dword must be read first. */
1680         /* Both registers clear on the read of the high dword */
1681
1682         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1683         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1684         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1685         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1686         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1687         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1688         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1689
1690         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1691         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1692         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1693         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1694         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1695
1696         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1697         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1698
1699         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1700         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1701         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1702         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1703         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1704         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1705
1706         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1707         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1708         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1709         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1710         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1711         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1712         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1713         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1714
1715         /* Interrupt Counts */
1716
1717         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1718         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1719         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1720         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1721         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1722         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1723         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1724         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1725         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1726
1727         /* Host to Card Statistics */
1728
1729         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1730         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1731         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1732         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1733         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1734         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1735         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1736         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1737         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1738         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1739         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1740         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1741         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1742         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1743         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1744         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1745
1746         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1747         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1748         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1749         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1750         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1751         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1752 }
1753
1754 static void
1755 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1756 {
1757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758         struct e1000_hw_stats *stats =
1759                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1760
1761         igb_read_stats_registers(hw, stats);
1762
1763         if (rte_stats == NULL)
1764                 return;
1765
1766         /* Rx Errors */
1767         rte_stats->imissed = stats->mpc;
1768         rte_stats->ierrors = stats->crcerrs +
1769                              stats->rlec + stats->ruc + stats->roc +
1770                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1771
1772         /* Tx Errors */
1773         rte_stats->oerrors = stats->ecol + stats->latecol;
1774
1775         rte_stats->ipackets = stats->gprc;
1776         rte_stats->opackets = stats->gptc;
1777         rte_stats->ibytes   = stats->gorc;
1778         rte_stats->obytes   = stats->gotc;
1779 }
1780
1781 static void
1782 eth_igb_stats_reset(struct rte_eth_dev *dev)
1783 {
1784         struct e1000_hw_stats *hw_stats =
1785                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1786
1787         /* HW registers are cleared on read */
1788         eth_igb_stats_get(dev, NULL);
1789
1790         /* Reset software totals */
1791         memset(hw_stats, 0, sizeof(*hw_stats));
1792 }
1793
1794 static void
1795 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1796 {
1797         struct e1000_hw_stats *stats =
1798                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1799
1800         /* HW registers are cleared on read */
1801         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1802
1803         /* Reset software totals */
1804         memset(stats, 0, sizeof(*stats));
1805 }
1806
1807 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1808         struct rte_eth_xstat_name *xstats_names,
1809         __rte_unused unsigned limit)
1810 {
1811         unsigned i;
1812
1813         if (xstats_names == NULL)
1814                 return IGB_NB_XSTATS;
1815
1816         /* Note: limit checked in rte_eth_xstats_names() */
1817
1818         for (i = 0; i < IGB_NB_XSTATS; i++) {
1819                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1820                          "%s", rte_igb_stats_strings[i].name);
1821         }
1822
1823         return IGB_NB_XSTATS;
1824 }
1825
1826 static int
1827 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1828                    unsigned n)
1829 {
1830         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831         struct e1000_hw_stats *hw_stats =
1832                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1833         unsigned i;
1834
1835         if (n < IGB_NB_XSTATS)
1836                 return IGB_NB_XSTATS;
1837
1838         igb_read_stats_registers(hw, hw_stats);
1839
1840         /* If this is a reset xstats is NULL, and we have cleared the
1841          * registers by reading them.
1842          */
1843         if (!xstats)
1844                 return 0;
1845
1846         /* Extended stats */
1847         for (i = 0; i < IGB_NB_XSTATS; i++) {
1848                 xstats[i].id = i;
1849                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1850                         rte_igb_stats_strings[i].offset);
1851         }
1852
1853         return IGB_NB_XSTATS;
1854 }
1855
1856 static void
1857 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1858 {
1859         /* Good Rx packets, include VF loopback */
1860         UPDATE_VF_STAT(E1000_VFGPRC,
1861             hw_stats->last_gprc, hw_stats->gprc);
1862
1863         /* Good Rx octets, include VF loopback */
1864         UPDATE_VF_STAT(E1000_VFGORC,
1865             hw_stats->last_gorc, hw_stats->gorc);
1866
1867         /* Good Tx packets, include VF loopback */
1868         UPDATE_VF_STAT(E1000_VFGPTC,
1869             hw_stats->last_gptc, hw_stats->gptc);
1870
1871         /* Good Tx octets, include VF loopback */
1872         UPDATE_VF_STAT(E1000_VFGOTC,
1873             hw_stats->last_gotc, hw_stats->gotc);
1874
1875         /* Rx Multicst packets */
1876         UPDATE_VF_STAT(E1000_VFMPRC,
1877             hw_stats->last_mprc, hw_stats->mprc);
1878
1879         /* Good Rx loopback packets */
1880         UPDATE_VF_STAT(E1000_VFGPRLBC,
1881             hw_stats->last_gprlbc, hw_stats->gprlbc);
1882
1883         /* Good Rx loopback octets */
1884         UPDATE_VF_STAT(E1000_VFGORLBC,
1885             hw_stats->last_gorlbc, hw_stats->gorlbc);
1886
1887         /* Good Tx loopback packets */
1888         UPDATE_VF_STAT(E1000_VFGPTLBC,
1889             hw_stats->last_gptlbc, hw_stats->gptlbc);
1890
1891         /* Good Tx loopback octets */
1892         UPDATE_VF_STAT(E1000_VFGOTLBC,
1893             hw_stats->last_gotlbc, hw_stats->gotlbc);
1894 }
1895
1896 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1897                                      struct rte_eth_xstat_name *xstats_names,
1898                                      __rte_unused unsigned limit)
1899 {
1900         unsigned i;
1901
1902         if (xstats_names != NULL)
1903                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1904                         snprintf(xstats_names[i].name,
1905                                 sizeof(xstats_names[i].name), "%s",
1906                                 rte_igbvf_stats_strings[i].name);
1907                 }
1908         return IGBVF_NB_XSTATS;
1909 }
1910
1911 static int
1912 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1913                      unsigned n)
1914 {
1915         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1917                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1918         unsigned i;
1919
1920         if (n < IGBVF_NB_XSTATS)
1921                 return IGBVF_NB_XSTATS;
1922
1923         igbvf_read_stats_registers(hw, hw_stats);
1924
1925         if (!xstats)
1926                 return 0;
1927
1928         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1929                 xstats[i].id = i;
1930                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1931                         rte_igbvf_stats_strings[i].offset);
1932         }
1933
1934         return IGBVF_NB_XSTATS;
1935 }
1936
1937 static void
1938 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1939 {
1940         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1942                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1943
1944         igbvf_read_stats_registers(hw, hw_stats);
1945
1946         if (rte_stats == NULL)
1947                 return;
1948
1949         rte_stats->ipackets = hw_stats->gprc;
1950         rte_stats->ibytes = hw_stats->gorc;
1951         rte_stats->opackets = hw_stats->gptc;
1952         rte_stats->obytes = hw_stats->gotc;
1953 }
1954
1955 static void
1956 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1957 {
1958         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1959                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1960
1961         /* Sync HW register to the last stats */
1962         eth_igbvf_stats_get(dev, NULL);
1963
1964         /* reset HW current stats*/
1965         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1966                offsetof(struct e1000_vf_stats, gprc));
1967 }
1968
1969 static void
1970 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1971 {
1972         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973
1974         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1975         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1976         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1977         dev_info->rx_offload_capa =
1978                 DEV_RX_OFFLOAD_VLAN_STRIP |
1979                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1980                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1981                 DEV_RX_OFFLOAD_TCP_CKSUM;
1982         dev_info->tx_offload_capa =
1983                 DEV_TX_OFFLOAD_VLAN_INSERT |
1984                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1985                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1986                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1987                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1988                 DEV_TX_OFFLOAD_TCP_TSO;
1989
1990         switch (hw->mac.type) {
1991         case e1000_82575:
1992                 dev_info->max_rx_queues = 4;
1993                 dev_info->max_tx_queues = 4;
1994                 dev_info->max_vmdq_pools = 0;
1995                 break;
1996
1997         case e1000_82576:
1998                 dev_info->max_rx_queues = 16;
1999                 dev_info->max_tx_queues = 16;
2000                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2001                 dev_info->vmdq_queue_num = 16;
2002                 break;
2003
2004         case e1000_82580:
2005                 dev_info->max_rx_queues = 8;
2006                 dev_info->max_tx_queues = 8;
2007                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2008                 dev_info->vmdq_queue_num = 8;
2009                 break;
2010
2011         case e1000_i350:
2012                 dev_info->max_rx_queues = 8;
2013                 dev_info->max_tx_queues = 8;
2014                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2015                 dev_info->vmdq_queue_num = 8;
2016                 break;
2017
2018         case e1000_i354:
2019                 dev_info->max_rx_queues = 8;
2020                 dev_info->max_tx_queues = 8;
2021                 break;
2022
2023         case e1000_i210:
2024                 dev_info->max_rx_queues = 4;
2025                 dev_info->max_tx_queues = 4;
2026                 dev_info->max_vmdq_pools = 0;
2027                 break;
2028
2029         case e1000_i211:
2030                 dev_info->max_rx_queues = 2;
2031                 dev_info->max_tx_queues = 2;
2032                 dev_info->max_vmdq_pools = 0;
2033                 break;
2034
2035         default:
2036                 /* Should not happen */
2037                 break;
2038         }
2039         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2040         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2041         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2042
2043         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2044                 .rx_thresh = {
2045                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2046                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2047                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2048                 },
2049                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2050                 .rx_drop_en = 0,
2051         };
2052
2053         dev_info->default_txconf = (struct rte_eth_txconf) {
2054                 .tx_thresh = {
2055                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2056                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2057                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2058                 },
2059                 .txq_flags = 0,
2060         };
2061
2062         dev_info->rx_desc_lim = rx_desc_lim;
2063         dev_info->tx_desc_lim = tx_desc_lim;
2064
2065         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2066                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2067                         ETH_LINK_SPEED_1G;
2068 }
2069
2070 static const uint32_t *
2071 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2072 {
2073         static const uint32_t ptypes[] = {
2074                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2075                 RTE_PTYPE_L2_ETHER,
2076                 RTE_PTYPE_L3_IPV4,
2077                 RTE_PTYPE_L3_IPV4_EXT,
2078                 RTE_PTYPE_L3_IPV6,
2079                 RTE_PTYPE_L3_IPV6_EXT,
2080                 RTE_PTYPE_L4_TCP,
2081                 RTE_PTYPE_L4_UDP,
2082                 RTE_PTYPE_L4_SCTP,
2083                 RTE_PTYPE_TUNNEL_IP,
2084                 RTE_PTYPE_INNER_L3_IPV6,
2085                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2086                 RTE_PTYPE_INNER_L4_TCP,
2087                 RTE_PTYPE_INNER_L4_UDP,
2088                 RTE_PTYPE_UNKNOWN
2089         };
2090
2091         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2092             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2093                 return ptypes;
2094         return NULL;
2095 }
2096
2097 static void
2098 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2099 {
2100         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101
2102         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2103         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2104         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2105         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2106                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2107                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2108                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2109         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2110                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2111                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2112                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2113                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2114                                 DEV_TX_OFFLOAD_TCP_TSO;
2115         switch (hw->mac.type) {
2116         case e1000_vfadapt:
2117                 dev_info->max_rx_queues = 2;
2118                 dev_info->max_tx_queues = 2;
2119                 break;
2120         case e1000_vfadapt_i350:
2121                 dev_info->max_rx_queues = 1;
2122                 dev_info->max_tx_queues = 1;
2123                 break;
2124         default:
2125                 /* Should not happen */
2126                 break;
2127         }
2128
2129         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2130                 .rx_thresh = {
2131                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2132                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2133                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2134                 },
2135                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2136                 .rx_drop_en = 0,
2137         };
2138
2139         dev_info->default_txconf = (struct rte_eth_txconf) {
2140                 .tx_thresh = {
2141                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2142                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2143                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2144                 },
2145                 .txq_flags = 0,
2146         };
2147
2148         dev_info->rx_desc_lim = rx_desc_lim;
2149         dev_info->tx_desc_lim = tx_desc_lim;
2150 }
2151
2152 /* return 0 means link status changed, -1 means not changed */
2153 static int
2154 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2155 {
2156         struct e1000_hw *hw =
2157                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         struct rte_eth_link link, old;
2159         int link_check, count;
2160
2161         link_check = 0;
2162         hw->mac.get_link_status = 1;
2163
2164         /* possible wait-to-complete in up to 9 seconds */
2165         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2166                 /* Read the real link status */
2167                 switch (hw->phy.media_type) {
2168                 case e1000_media_type_copper:
2169                         /* Do the work to read phy */
2170                         e1000_check_for_link(hw);
2171                         link_check = !hw->mac.get_link_status;
2172                         break;
2173
2174                 case e1000_media_type_fiber:
2175                         e1000_check_for_link(hw);
2176                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2177                                       E1000_STATUS_LU);
2178                         break;
2179
2180                 case e1000_media_type_internal_serdes:
2181                         e1000_check_for_link(hw);
2182                         link_check = hw->mac.serdes_has_link;
2183                         break;
2184
2185                 /* VF device is type_unknown */
2186                 case e1000_media_type_unknown:
2187                         eth_igbvf_link_update(hw);
2188                         link_check = !hw->mac.get_link_status;
2189                         break;
2190
2191                 default:
2192                         break;
2193                 }
2194                 if (link_check || wait_to_complete == 0)
2195                         break;
2196                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2197         }
2198         memset(&link, 0, sizeof(link));
2199         rte_igb_dev_atomic_read_link_status(dev, &link);
2200         old = link;
2201
2202         /* Now we check if a transition has happened */
2203         if (link_check) {
2204                 uint16_t duplex, speed;
2205                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2206                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2207                                 ETH_LINK_FULL_DUPLEX :
2208                                 ETH_LINK_HALF_DUPLEX;
2209                 link.link_speed = speed;
2210                 link.link_status = ETH_LINK_UP;
2211                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2212                                 ETH_LINK_SPEED_FIXED);
2213         } else if (!link_check) {
2214                 link.link_speed = 0;
2215                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2216                 link.link_status = ETH_LINK_DOWN;
2217                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2218         }
2219         rte_igb_dev_atomic_write_link_status(dev, &link);
2220
2221         /* not changed */
2222         if (old.link_status == link.link_status)
2223                 return -1;
2224
2225         /* changed */
2226         return 0;
2227 }
2228
2229 /*
2230  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2231  * For ASF and Pass Through versions of f/w this means
2232  * that the driver is loaded.
2233  */
2234 static void
2235 igb_hw_control_acquire(struct e1000_hw *hw)
2236 {
2237         uint32_t ctrl_ext;
2238
2239         /* Let firmware know the driver has taken over */
2240         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2241         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2242 }
2243
2244 /*
2245  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2246  * For ASF and Pass Through versions of f/w this means that the
2247  * driver is no longer loaded.
2248  */
2249 static void
2250 igb_hw_control_release(struct e1000_hw *hw)
2251 {
2252         uint32_t ctrl_ext;
2253
2254         /* Let firmware taken over control of h/w */
2255         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2256         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2257                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2258 }
2259
2260 /*
2261  * Bit of a misnomer, what this really means is
2262  * to enable OS management of the system... aka
2263  * to disable special hardware management features.
2264  */
2265 static void
2266 igb_init_manageability(struct e1000_hw *hw)
2267 {
2268         if (e1000_enable_mng_pass_thru(hw)) {
2269                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2270                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2271
2272                 /* disable hardware interception of ARP */
2273                 manc &= ~(E1000_MANC_ARP_EN);
2274
2275                 /* enable receiving management packets to the host */
2276                 manc |= E1000_MANC_EN_MNG2HOST;
2277                 manc2h |= 1 << 5;  /* Mng Port 623 */
2278                 manc2h |= 1 << 6;  /* Mng Port 664 */
2279                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2280                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2281         }
2282 }
2283
2284 static void
2285 igb_release_manageability(struct e1000_hw *hw)
2286 {
2287         if (e1000_enable_mng_pass_thru(hw)) {
2288                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2289
2290                 manc |= E1000_MANC_ARP_EN;
2291                 manc &= ~E1000_MANC_EN_MNG2HOST;
2292
2293                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2294         }
2295 }
2296
2297 static void
2298 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2299 {
2300         struct e1000_hw *hw =
2301                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         uint32_t rctl;
2303
2304         rctl = E1000_READ_REG(hw, E1000_RCTL);
2305         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2306         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2307 }
2308
2309 static void
2310 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2311 {
2312         struct e1000_hw *hw =
2313                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314         uint32_t rctl;
2315
2316         rctl = E1000_READ_REG(hw, E1000_RCTL);
2317         rctl &= (~E1000_RCTL_UPE);
2318         if (dev->data->all_multicast == 1)
2319                 rctl |= E1000_RCTL_MPE;
2320         else
2321                 rctl &= (~E1000_RCTL_MPE);
2322         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2323 }
2324
2325 static void
2326 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2327 {
2328         struct e1000_hw *hw =
2329                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330         uint32_t rctl;
2331
2332         rctl = E1000_READ_REG(hw, E1000_RCTL);
2333         rctl |= E1000_RCTL_MPE;
2334         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2335 }
2336
2337 static void
2338 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2339 {
2340         struct e1000_hw *hw =
2341                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         uint32_t rctl;
2343
2344         if (dev->data->promiscuous == 1)
2345                 return; /* must remain in all_multicast mode */
2346         rctl = E1000_READ_REG(hw, E1000_RCTL);
2347         rctl &= (~E1000_RCTL_MPE);
2348         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2349 }
2350
2351 static int
2352 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2353 {
2354         struct e1000_hw *hw =
2355                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct e1000_vfta * shadow_vfta =
2357                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2358         uint32_t vfta;
2359         uint32_t vid_idx;
2360         uint32_t vid_bit;
2361
2362         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2363                               E1000_VFTA_ENTRY_MASK);
2364         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2365         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2366         if (on)
2367                 vfta |= vid_bit;
2368         else
2369                 vfta &= ~vid_bit;
2370         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2371
2372         /* update local VFTA copy */
2373         shadow_vfta->vfta[vid_idx] = vfta;
2374
2375         return 0;
2376 }
2377
2378 static int
2379 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2380                       enum rte_vlan_type vlan_type,
2381                       uint16_t tpid)
2382 {
2383         struct e1000_hw *hw =
2384                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2385         uint32_t reg, qinq;
2386
2387         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2388         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2389
2390         /* only outer TPID of double VLAN can be configured*/
2391         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2392                 reg = E1000_READ_REG(hw, E1000_VET);
2393                 reg = (reg & (~E1000_VET_VET_EXT)) |
2394                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2395                 E1000_WRITE_REG(hw, E1000_VET, reg);
2396
2397                 return 0;
2398         }
2399
2400         /* all other TPID values are read-only*/
2401         PMD_DRV_LOG(ERR, "Not supported");
2402
2403         return -ENOTSUP;
2404 }
2405
2406 static void
2407 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2408 {
2409         struct e1000_hw *hw =
2410                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         uint32_t reg;
2412
2413         /* Filter Table Disable */
2414         reg = E1000_READ_REG(hw, E1000_RCTL);
2415         reg &= ~E1000_RCTL_CFIEN;
2416         reg &= ~E1000_RCTL_VFE;
2417         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2418 }
2419
2420 static void
2421 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2422 {
2423         struct e1000_hw *hw =
2424                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct e1000_vfta * shadow_vfta =
2426                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2427         uint32_t reg;
2428         int i;
2429
2430         /* Filter Table Enable, CFI not used for packet acceptance */
2431         reg = E1000_READ_REG(hw, E1000_RCTL);
2432         reg &= ~E1000_RCTL_CFIEN;
2433         reg |= E1000_RCTL_VFE;
2434         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2435
2436         /* restore VFTA table */
2437         for (i = 0; i < IGB_VFTA_SIZE; i++)
2438                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2439 }
2440
2441 static void
2442 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2443 {
2444         struct e1000_hw *hw =
2445                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         uint32_t reg;
2447
2448         /* VLAN Mode Disable */
2449         reg = E1000_READ_REG(hw, E1000_CTRL);
2450         reg &= ~E1000_CTRL_VME;
2451         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2452 }
2453
2454 static void
2455 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2456 {
2457         struct e1000_hw *hw =
2458                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2459         uint32_t reg;
2460
2461         /* VLAN Mode Enable */
2462         reg = E1000_READ_REG(hw, E1000_CTRL);
2463         reg |= E1000_CTRL_VME;
2464         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2465 }
2466
2467 static void
2468 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2469 {
2470         struct e1000_hw *hw =
2471                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2472         uint32_t reg;
2473
2474         /* CTRL_EXT: Extended VLAN */
2475         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2476         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2477         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2478
2479         /* Update maximum packet length */
2480         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2481                 E1000_WRITE_REG(hw, E1000_RLPML,
2482                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2483                                                 VLAN_TAG_SIZE);
2484 }
2485
2486 static void
2487 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2488 {
2489         struct e1000_hw *hw =
2490                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         uint32_t reg;
2492
2493         /* CTRL_EXT: Extended VLAN */
2494         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2495         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2496         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2497
2498         /* Update maximum packet length */
2499         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2500                 E1000_WRITE_REG(hw, E1000_RLPML,
2501                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2502                                                 2 * VLAN_TAG_SIZE);
2503 }
2504
2505 static void
2506 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2507 {
2508         if(mask & ETH_VLAN_STRIP_MASK){
2509                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2510                         igb_vlan_hw_strip_enable(dev);
2511                 else
2512                         igb_vlan_hw_strip_disable(dev);
2513         }
2514
2515         if(mask & ETH_VLAN_FILTER_MASK){
2516                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2517                         igb_vlan_hw_filter_enable(dev);
2518                 else
2519                         igb_vlan_hw_filter_disable(dev);
2520         }
2521
2522         if(mask & ETH_VLAN_EXTEND_MASK){
2523                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2524                         igb_vlan_hw_extend_enable(dev);
2525                 else
2526                         igb_vlan_hw_extend_disable(dev);
2527         }
2528 }
2529
2530
2531 /**
2532  * It enables the interrupt mask and then enable the interrupt.
2533  *
2534  * @param dev
2535  *  Pointer to struct rte_eth_dev.
2536  *
2537  * @return
2538  *  - On success, zero.
2539  *  - On failure, a negative value.
2540  */
2541 static int
2542 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2543 {
2544         struct e1000_interrupt *intr =
2545                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2546
2547         intr->mask |= E1000_ICR_LSC;
2548
2549         return 0;
2550 }
2551
2552 /* It clears the interrupt causes and enables the interrupt.
2553  * It will be called once only during nic initialized.
2554  *
2555  * @param dev
2556  *  Pointer to struct rte_eth_dev.
2557  *
2558  * @return
2559  *  - On success, zero.
2560  *  - On failure, a negative value.
2561  */
2562 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2563 {
2564         uint32_t mask, regval;
2565         struct e1000_hw *hw =
2566                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567         struct rte_eth_dev_info dev_info;
2568
2569         memset(&dev_info, 0, sizeof(dev_info));
2570         eth_igb_infos_get(dev, &dev_info);
2571
2572         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2573         regval = E1000_READ_REG(hw, E1000_EIMS);
2574         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2575
2576         return 0;
2577 }
2578
2579 /*
2580  * It reads ICR and gets interrupt causes, check it and set a bit flag
2581  * to update link status.
2582  *
2583  * @param dev
2584  *  Pointer to struct rte_eth_dev.
2585  *
2586  * @return
2587  *  - On success, zero.
2588  *  - On failure, a negative value.
2589  */
2590 static int
2591 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2592 {
2593         uint32_t icr;
2594         struct e1000_hw *hw =
2595                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596         struct e1000_interrupt *intr =
2597                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2598
2599         igb_intr_disable(hw);
2600
2601         /* read-on-clear nic registers here */
2602         icr = E1000_READ_REG(hw, E1000_ICR);
2603
2604         intr->flags = 0;
2605         if (icr & E1000_ICR_LSC) {
2606                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2607         }
2608
2609         if (icr & E1000_ICR_VMMB)
2610                 intr->flags |= E1000_FLAG_MAILBOX;
2611
2612         return 0;
2613 }
2614
2615 /*
2616  * It executes link_update after knowing an interrupt is prsent.
2617  *
2618  * @param dev
2619  *  Pointer to struct rte_eth_dev.
2620  *
2621  * @return
2622  *  - On success, zero.
2623  *  - On failure, a negative value.
2624  */
2625 static int
2626 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2627 {
2628         struct e1000_hw *hw =
2629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630         struct e1000_interrupt *intr =
2631                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2632         uint32_t tctl, rctl;
2633         struct rte_eth_link link;
2634         int ret;
2635
2636         if (intr->flags & E1000_FLAG_MAILBOX) {
2637                 igb_pf_mbx_process(dev);
2638                 intr->flags &= ~E1000_FLAG_MAILBOX;
2639         }
2640
2641         igb_intr_enable(dev);
2642         rte_intr_enable(&(dev->pci_dev->intr_handle));
2643
2644         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2645                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2646
2647                 /* set get_link_status to check register later */
2648                 hw->mac.get_link_status = 1;
2649                 ret = eth_igb_link_update(dev, 0);
2650
2651                 /* check if link has changed */
2652                 if (ret < 0)
2653                         return 0;
2654
2655                 memset(&link, 0, sizeof(link));
2656                 rte_igb_dev_atomic_read_link_status(dev, &link);
2657                 if (link.link_status) {
2658                         PMD_INIT_LOG(INFO,
2659                                      " Port %d: Link Up - speed %u Mbps - %s",
2660                                      dev->data->port_id,
2661                                      (unsigned)link.link_speed,
2662                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2663                                      "full-duplex" : "half-duplex");
2664                 } else {
2665                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2666                                      dev->data->port_id);
2667                 }
2668
2669                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2670                              dev->pci_dev->addr.domain,
2671                              dev->pci_dev->addr.bus,
2672                              dev->pci_dev->addr.devid,
2673                              dev->pci_dev->addr.function);
2674                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2675                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2676                 if (link.link_status) {
2677                         /* enable Tx/Rx */
2678                         tctl |= E1000_TCTL_EN;
2679                         rctl |= E1000_RCTL_EN;
2680                 } else {
2681                         /* disable Tx/Rx */
2682                         tctl &= ~E1000_TCTL_EN;
2683                         rctl &= ~E1000_RCTL_EN;
2684                 }
2685                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2686                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2687                 E1000_WRITE_FLUSH(hw);
2688                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2689         }
2690
2691         return 0;
2692 }
2693
2694 /**
2695  * Interrupt handler which shall be registered at first.
2696  *
2697  * @param handle
2698  *  Pointer to interrupt handle.
2699  * @param param
2700  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2701  *
2702  * @return
2703  *  void
2704  */
2705 static void
2706 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2707                                                         void *param)
2708 {
2709         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2710
2711         eth_igb_interrupt_get_status(dev);
2712         eth_igb_interrupt_action(dev);
2713 }
2714
2715 static int
2716 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2717 {
2718         uint32_t eicr;
2719         struct e1000_hw *hw =
2720                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2721         struct e1000_interrupt *intr =
2722                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2723
2724         igbvf_intr_disable(hw);
2725
2726         /* read-on-clear nic registers here */
2727         eicr = E1000_READ_REG(hw, E1000_EICR);
2728         intr->flags = 0;
2729
2730         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2731                 intr->flags |= E1000_FLAG_MAILBOX;
2732
2733         return 0;
2734 }
2735
2736 void igbvf_mbx_process(struct rte_eth_dev *dev)
2737 {
2738         struct e1000_hw *hw =
2739                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2740         struct e1000_mbx_info *mbx = &hw->mbx;
2741         u32 in_msg = 0;
2742
2743         if (mbx->ops.read(hw, &in_msg, 1, 0))
2744                 return;
2745
2746         /* PF reset VF event */
2747         if (in_msg == E1000_PF_CONTROL_MSG)
2748                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2749 }
2750
2751 static int
2752 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2753 {
2754         struct e1000_interrupt *intr =
2755                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2756
2757         if (intr->flags & E1000_FLAG_MAILBOX) {
2758                 igbvf_mbx_process(dev);
2759                 intr->flags &= ~E1000_FLAG_MAILBOX;
2760         }
2761
2762         igbvf_intr_enable(dev);
2763         rte_intr_enable(&dev->pci_dev->intr_handle);
2764
2765         return 0;
2766 }
2767
2768 static void
2769 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2770                             void *param)
2771 {
2772         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2773
2774         eth_igbvf_interrupt_get_status(dev);
2775         eth_igbvf_interrupt_action(dev);
2776 }
2777
2778 static int
2779 eth_igb_led_on(struct rte_eth_dev *dev)
2780 {
2781         struct e1000_hw *hw;
2782
2783         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2785 }
2786
2787 static int
2788 eth_igb_led_off(struct rte_eth_dev *dev)
2789 {
2790         struct e1000_hw *hw;
2791
2792         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2794 }
2795
2796 static int
2797 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2798 {
2799         struct e1000_hw *hw;
2800         uint32_t ctrl;
2801         int tx_pause;
2802         int rx_pause;
2803
2804         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         fc_conf->pause_time = hw->fc.pause_time;
2806         fc_conf->high_water = hw->fc.high_water;
2807         fc_conf->low_water = hw->fc.low_water;
2808         fc_conf->send_xon = hw->fc.send_xon;
2809         fc_conf->autoneg = hw->mac.autoneg;
2810
2811         /*
2812          * Return rx_pause and tx_pause status according to actual setting of
2813          * the TFCE and RFCE bits in the CTRL register.
2814          */
2815         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2816         if (ctrl & E1000_CTRL_TFCE)
2817                 tx_pause = 1;
2818         else
2819                 tx_pause = 0;
2820
2821         if (ctrl & E1000_CTRL_RFCE)
2822                 rx_pause = 1;
2823         else
2824                 rx_pause = 0;
2825
2826         if (rx_pause && tx_pause)
2827                 fc_conf->mode = RTE_FC_FULL;
2828         else if (rx_pause)
2829                 fc_conf->mode = RTE_FC_RX_PAUSE;
2830         else if (tx_pause)
2831                 fc_conf->mode = RTE_FC_TX_PAUSE;
2832         else
2833                 fc_conf->mode = RTE_FC_NONE;
2834
2835         return 0;
2836 }
2837
2838 static int
2839 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2840 {
2841         struct e1000_hw *hw;
2842         int err;
2843         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2844                 e1000_fc_none,
2845                 e1000_fc_rx_pause,
2846                 e1000_fc_tx_pause,
2847                 e1000_fc_full
2848         };
2849         uint32_t rx_buf_size;
2850         uint32_t max_high_water;
2851         uint32_t rctl;
2852
2853         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2854         if (fc_conf->autoneg != hw->mac.autoneg)
2855                 return -ENOTSUP;
2856         rx_buf_size = igb_get_rx_buffer_size(hw);
2857         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2858
2859         /* At least reserve one Ethernet frame for watermark */
2860         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2861         if ((fc_conf->high_water > max_high_water) ||
2862             (fc_conf->high_water < fc_conf->low_water)) {
2863                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2864                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2865                 return -EINVAL;
2866         }
2867
2868         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2869         hw->fc.pause_time     = fc_conf->pause_time;
2870         hw->fc.high_water     = fc_conf->high_water;
2871         hw->fc.low_water      = fc_conf->low_water;
2872         hw->fc.send_xon       = fc_conf->send_xon;
2873
2874         err = e1000_setup_link_generic(hw);
2875         if (err == E1000_SUCCESS) {
2876
2877                 /* check if we want to forward MAC frames - driver doesn't have native
2878                  * capability to do that, so we'll write the registers ourselves */
2879
2880                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2881
2882                 /* set or clear MFLCN.PMCF bit depending on configuration */
2883                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2884                         rctl |= E1000_RCTL_PMCF;
2885                 else
2886                         rctl &= ~E1000_RCTL_PMCF;
2887
2888                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2889                 E1000_WRITE_FLUSH(hw);
2890
2891                 return 0;
2892         }
2893
2894         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2895         return -EIO;
2896 }
2897
2898 #define E1000_RAH_POOLSEL_SHIFT      (18)
2899 static void
2900 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2901                 uint32_t index, __rte_unused uint32_t pool)
2902 {
2903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904         uint32_t rah;
2905
2906         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2907         rah = E1000_READ_REG(hw, E1000_RAH(index));
2908         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2909         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2910 }
2911
2912 static void
2913 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2914 {
2915         uint8_t addr[ETHER_ADDR_LEN];
2916         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917
2918         memset(addr, 0, sizeof(addr));
2919
2920         e1000_rar_set(hw, addr, index);
2921 }
2922
2923 static void
2924 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2925                                 struct ether_addr *addr)
2926 {
2927         eth_igb_rar_clear(dev, 0);
2928
2929         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2930 }
2931 /*
2932  * Virtual Function operations
2933  */
2934 static void
2935 igbvf_intr_disable(struct e1000_hw *hw)
2936 {
2937         PMD_INIT_FUNC_TRACE();
2938
2939         /* Clear interrupt mask to stop from interrupts being generated */
2940         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2941
2942         E1000_WRITE_FLUSH(hw);
2943 }
2944
2945 static void
2946 igbvf_stop_adapter(struct rte_eth_dev *dev)
2947 {
2948         u32 reg_val;
2949         u16 i;
2950         struct rte_eth_dev_info dev_info;
2951         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952
2953         memset(&dev_info, 0, sizeof(dev_info));
2954         eth_igbvf_infos_get(dev, &dev_info);
2955
2956         /* Clear interrupt mask to stop from interrupts being generated */
2957         igbvf_intr_disable(hw);
2958
2959         /* Clear any pending interrupts, flush previous writes */
2960         E1000_READ_REG(hw, E1000_EICR);
2961
2962         /* Disable the transmit unit.  Each queue must be disabled. */
2963         for (i = 0; i < dev_info.max_tx_queues; i++)
2964                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2965
2966         /* Disable the receive unit by stopping each queue */
2967         for (i = 0; i < dev_info.max_rx_queues; i++) {
2968                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2969                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2970                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2971                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2972                         ;
2973         }
2974
2975         /* flush all queues disables */
2976         E1000_WRITE_FLUSH(hw);
2977         msec_delay(2);
2978 }
2979
2980 static int eth_igbvf_link_update(struct e1000_hw *hw)
2981 {
2982         struct e1000_mbx_info *mbx = &hw->mbx;
2983         struct e1000_mac_info *mac = &hw->mac;
2984         int ret_val = E1000_SUCCESS;
2985
2986         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2987
2988         /*
2989          * We only want to run this if there has been a rst asserted.
2990          * in this case that could mean a link change, device reset,
2991          * or a virtual function reset
2992          */
2993
2994         /* If we were hit with a reset or timeout drop the link */
2995         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2996                 mac->get_link_status = TRUE;
2997
2998         if (!mac->get_link_status)
2999                 goto out;
3000
3001         /* if link status is down no point in checking to see if pf is up */
3002         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3003                 goto out;
3004
3005         /* if we passed all the tests above then the link is up and we no
3006          * longer need to check for link */
3007         mac->get_link_status = FALSE;
3008
3009 out:
3010         return ret_val;
3011 }
3012
3013
3014 static int
3015 igbvf_dev_configure(struct rte_eth_dev *dev)
3016 {
3017         struct rte_eth_conf* conf = &dev->data->dev_conf;
3018
3019         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3020                      dev->data->port_id);
3021
3022         /*
3023          * VF has no ability to enable/disable HW CRC
3024          * Keep the persistent behavior the same as Host PF
3025          */
3026 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3027         if (!conf->rxmode.hw_strip_crc) {
3028                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3029                 conf->rxmode.hw_strip_crc = 1;
3030         }
3031 #else
3032         if (conf->rxmode.hw_strip_crc) {
3033                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3034                 conf->rxmode.hw_strip_crc = 0;
3035         }
3036 #endif
3037
3038         return 0;
3039 }
3040
3041 static int
3042 igbvf_dev_start(struct rte_eth_dev *dev)
3043 {
3044         struct e1000_hw *hw =
3045                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046         struct e1000_adapter *adapter =
3047                 E1000_DEV_PRIVATE(dev->data->dev_private);
3048         int ret;
3049         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3050         uint32_t intr_vector = 0;
3051
3052         PMD_INIT_FUNC_TRACE();
3053
3054         hw->mac.ops.reset_hw(hw);
3055         adapter->stopped = 0;
3056
3057         /* Set all vfta */
3058         igbvf_set_vfta_all(dev,1);
3059
3060         eth_igbvf_tx_init(dev);
3061
3062         /* This can fail when allocating mbufs for descriptor rings */
3063         ret = eth_igbvf_rx_init(dev);
3064         if (ret) {
3065                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3066                 igb_dev_clear_queues(dev);
3067                 return ret;
3068         }
3069
3070         /* check and configure queue intr-vector mapping */
3071         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3072                 intr_vector = dev->data->nb_rx_queues;
3073                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3074                 if (ret)
3075                         return ret;
3076         }
3077
3078         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3079                 intr_handle->intr_vec =
3080                         rte_zmalloc("intr_vec",
3081                                     dev->data->nb_rx_queues * sizeof(int), 0);
3082                 if (!intr_handle->intr_vec) {
3083                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3084                                      " intr_vec\n", dev->data->nb_rx_queues);
3085                         return -ENOMEM;
3086                 }
3087         }
3088
3089         eth_igbvf_configure_msix_intr(dev);
3090
3091         /* enable uio/vfio intr/eventfd mapping */
3092         rte_intr_enable(intr_handle);
3093
3094         /* resume enabled intr since hw reset */
3095         igbvf_intr_enable(dev);
3096
3097         return 0;
3098 }
3099
3100 static void
3101 igbvf_dev_stop(struct rte_eth_dev *dev)
3102 {
3103         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3104
3105         PMD_INIT_FUNC_TRACE();
3106
3107         igbvf_stop_adapter(dev);
3108
3109         /*
3110           * Clear what we set, but we still keep shadow_vfta to
3111           * restore after device starts
3112           */
3113         igbvf_set_vfta_all(dev,0);
3114
3115         igb_dev_clear_queues(dev);
3116
3117         /* disable intr eventfd mapping */
3118         rte_intr_disable(intr_handle);
3119
3120         /* Clean datapath event and queue/vec mapping */
3121         rte_intr_efd_disable(intr_handle);
3122         if (intr_handle->intr_vec) {
3123                 rte_free(intr_handle->intr_vec);
3124                 intr_handle->intr_vec = NULL;
3125         }
3126 }
3127
3128 static void
3129 igbvf_dev_close(struct rte_eth_dev *dev)
3130 {
3131         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132         struct e1000_adapter *adapter =
3133                 E1000_DEV_PRIVATE(dev->data->dev_private);
3134         struct ether_addr addr;
3135
3136         PMD_INIT_FUNC_TRACE();
3137
3138         e1000_reset_hw(hw);
3139
3140         igbvf_dev_stop(dev);
3141         adapter->stopped = 1;
3142         igb_dev_free_queues(dev);
3143
3144         /**
3145          * reprogram the RAR with a zero mac address,
3146          * to ensure that the VF traffic goes to the PF
3147          * after stop, close and detach of the VF.
3148          **/
3149
3150         memset(&addr, 0, sizeof(addr));
3151         igbvf_default_mac_addr_set(dev, &addr);
3152 }
3153
3154 static void
3155 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3156 {
3157         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158
3159         /* Set both unicast and multicast promisc */
3160         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3161 }
3162
3163 static void
3164 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3165 {
3166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167
3168         /* If in allmulticast mode leave multicast promisc */
3169         if (dev->data->all_multicast == 1)
3170                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3171         else
3172                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3173 }
3174
3175 static void
3176 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3177 {
3178         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179
3180         /* In promiscuous mode multicast promisc already set */
3181         if (dev->data->promiscuous == 0)
3182                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3183 }
3184
3185 static void
3186 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3187 {
3188         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3189
3190         /* In promiscuous mode leave multicast promisc enabled */
3191         if (dev->data->promiscuous == 0)
3192                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3193 }
3194
3195 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3196 {
3197         struct e1000_mbx_info *mbx = &hw->mbx;
3198         uint32_t msgbuf[2];
3199         s32 err;
3200
3201         /* After set vlan, vlan strip will also be enabled in igb driver*/
3202         msgbuf[0] = E1000_VF_SET_VLAN;
3203         msgbuf[1] = vid;
3204         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3205         if (on)
3206                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3207
3208         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3209         if (err)
3210                 goto mbx_err;
3211
3212         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3213         if (err)
3214                 goto mbx_err;
3215
3216         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3217         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3218                 err = -EINVAL;
3219
3220 mbx_err:
3221         return err;
3222 }
3223
3224 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3225 {
3226         struct e1000_hw *hw =
3227                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228         struct e1000_vfta * shadow_vfta =
3229                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3230         int i = 0, j = 0, vfta = 0, mask = 1;
3231
3232         for (i = 0; i < IGB_VFTA_SIZE; i++){
3233                 vfta = shadow_vfta->vfta[i];
3234                 if(vfta){
3235                         mask = 1;
3236                         for (j = 0; j < 32; j++){
3237                                 if(vfta & mask)
3238                                         igbvf_set_vfta(hw,
3239                                                 (uint16_t)((i<<5)+j), on);
3240                                 mask<<=1;
3241                         }
3242                 }
3243         }
3244
3245 }
3246
3247 static int
3248 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3249 {
3250         struct e1000_hw *hw =
3251                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252         struct e1000_vfta * shadow_vfta =
3253                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3254         uint32_t vid_idx = 0;
3255         uint32_t vid_bit = 0;
3256         int ret = 0;
3257
3258         PMD_INIT_FUNC_TRACE();
3259
3260         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3261         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3262         if(ret){
3263                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3264                 return ret;
3265         }
3266         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3267         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3268
3269         /*Save what we set and retore it after device reset*/
3270         if (on)
3271                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3272         else
3273                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3274
3275         return 0;
3276 }
3277
3278 static void
3279 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3280 {
3281         struct e1000_hw *hw =
3282                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3283
3284         /* index is not used by rar_set() */
3285         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3286 }
3287
3288
3289 static int
3290 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3291                         struct rte_eth_rss_reta_entry64 *reta_conf,
3292                         uint16_t reta_size)
3293 {
3294         uint8_t i, j, mask;
3295         uint32_t reta, r;
3296         uint16_t idx, shift;
3297         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298
3299         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3300                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3301                         "(%d) doesn't match the number hardware can supported "
3302                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3303                 return -EINVAL;
3304         }
3305
3306         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3307                 idx = i / RTE_RETA_GROUP_SIZE;
3308                 shift = i % RTE_RETA_GROUP_SIZE;
3309                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3310                                                 IGB_4_BIT_MASK);
3311                 if (!mask)
3312                         continue;
3313                 if (mask == IGB_4_BIT_MASK)
3314                         r = 0;
3315                 else
3316                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3317                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3318                         if (mask & (0x1 << j))
3319                                 reta |= reta_conf[idx].reta[shift + j] <<
3320                                                         (CHAR_BIT * j);
3321                         else
3322                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3323                 }
3324                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3325         }
3326
3327         return 0;
3328 }
3329
3330 static int
3331 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3332                        struct rte_eth_rss_reta_entry64 *reta_conf,
3333                        uint16_t reta_size)
3334 {
3335         uint8_t i, j, mask;
3336         uint32_t reta;
3337         uint16_t idx, shift;
3338         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3339
3340         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3341                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3342                         "(%d) doesn't match the number hardware can supported "
3343                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3344                 return -EINVAL;
3345         }
3346
3347         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3348                 idx = i / RTE_RETA_GROUP_SIZE;
3349                 shift = i % RTE_RETA_GROUP_SIZE;
3350                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3351                                                 IGB_4_BIT_MASK);
3352                 if (!mask)
3353                         continue;
3354                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3355                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3356                         if (mask & (0x1 << j))
3357                                 reta_conf[idx].reta[shift + j] =
3358                                         ((reta >> (CHAR_BIT * j)) &
3359                                                 IGB_8_BIT_MASK);
3360                 }
3361         }
3362
3363         return 0;
3364 }
3365
3366 #define MAC_TYPE_FILTER_SUP(type)    do {\
3367         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3368                 (type) != e1000_82576)\
3369                 return -ENOTSUP;\
3370 } while (0)
3371
3372 static int
3373 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3374                         struct rte_eth_syn_filter *filter,
3375                         bool add)
3376 {
3377         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378         uint32_t synqf, rfctl;
3379
3380         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3381                 return -EINVAL;
3382
3383         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3384
3385         if (add) {
3386                 if (synqf & E1000_SYN_FILTER_ENABLE)
3387                         return -EINVAL;
3388
3389                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3390                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3391
3392                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3393                 if (filter->hig_pri)
3394                         rfctl |= E1000_RFCTL_SYNQFP;
3395                 else
3396                         rfctl &= ~E1000_RFCTL_SYNQFP;
3397
3398                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3399         } else {
3400                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3401                         return -ENOENT;
3402                 synqf = 0;
3403         }
3404
3405         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3406         E1000_WRITE_FLUSH(hw);
3407         return 0;
3408 }
3409
3410 static int
3411 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3412                         struct rte_eth_syn_filter *filter)
3413 {
3414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415         uint32_t synqf, rfctl;
3416
3417         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3418         if (synqf & E1000_SYN_FILTER_ENABLE) {
3419                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3420                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3421                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3422                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3423                 return 0;
3424         }
3425
3426         return -ENOENT;
3427 }
3428
3429 static int
3430 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3431                         enum rte_filter_op filter_op,
3432                         void *arg)
3433 {
3434         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3435         int ret;
3436
3437         MAC_TYPE_FILTER_SUP(hw->mac.type);
3438
3439         if (filter_op == RTE_ETH_FILTER_NOP)
3440                 return 0;
3441
3442         if (arg == NULL) {
3443                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3444                             filter_op);
3445                 return -EINVAL;
3446         }
3447
3448         switch (filter_op) {
3449         case RTE_ETH_FILTER_ADD:
3450                 ret = eth_igb_syn_filter_set(dev,
3451                                 (struct rte_eth_syn_filter *)arg,
3452                                 TRUE);
3453                 break;
3454         case RTE_ETH_FILTER_DELETE:
3455                 ret = eth_igb_syn_filter_set(dev,
3456                                 (struct rte_eth_syn_filter *)arg,
3457                                 FALSE);
3458                 break;
3459         case RTE_ETH_FILTER_GET:
3460                 ret = eth_igb_syn_filter_get(dev,
3461                                 (struct rte_eth_syn_filter *)arg);
3462                 break;
3463         default:
3464                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3465                 ret = -EINVAL;
3466                 break;
3467         }
3468
3469         return ret;
3470 }
3471
3472 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3473         if ((type) != e1000_82580 && (type) != e1000_i350)\
3474                 return -ENOSYS; \
3475 } while (0)
3476
3477 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3478 static inline int
3479 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3480                         struct e1000_2tuple_filter_info *filter_info)
3481 {
3482         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3483                 return -EINVAL;
3484         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3485                 return -EINVAL;  /* filter index is out of range. */
3486         if (filter->tcp_flags > TCP_FLAG_ALL)
3487                 return -EINVAL;  /* flags is invalid. */
3488
3489         switch (filter->dst_port_mask) {
3490         case UINT16_MAX:
3491                 filter_info->dst_port_mask = 0;
3492                 filter_info->dst_port = filter->dst_port;
3493                 break;
3494         case 0:
3495                 filter_info->dst_port_mask = 1;
3496                 break;
3497         default:
3498                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3499                 return -EINVAL;
3500         }
3501
3502         switch (filter->proto_mask) {
3503         case UINT8_MAX:
3504                 filter_info->proto_mask = 0;
3505                 filter_info->proto = filter->proto;
3506                 break;
3507         case 0:
3508                 filter_info->proto_mask = 1;
3509                 break;
3510         default:
3511                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3512                 return -EINVAL;
3513         }
3514
3515         filter_info->priority = (uint8_t)filter->priority;
3516         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3517                 filter_info->tcp_flags = filter->tcp_flags;
3518         else
3519                 filter_info->tcp_flags = 0;
3520
3521         return 0;
3522 }
3523
3524 static inline struct e1000_2tuple_filter *
3525 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3526                         struct e1000_2tuple_filter_info *key)
3527 {
3528         struct e1000_2tuple_filter *it;
3529
3530         TAILQ_FOREACH(it, filter_list, entries) {
3531                 if (memcmp(key, &it->filter_info,
3532                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3533                         return it;
3534                 }
3535         }
3536         return NULL;
3537 }
3538
3539 /*
3540  * igb_add_2tuple_filter - add a 2tuple filter
3541  *
3542  * @param
3543  * dev: Pointer to struct rte_eth_dev.
3544  * ntuple_filter: ponter to the filter that will be added.
3545  *
3546  * @return
3547  *    - On success, zero.
3548  *    - On failure, a negative value.
3549  */
3550 static int
3551 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3552                         struct rte_eth_ntuple_filter *ntuple_filter)
3553 {
3554         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555         struct e1000_filter_info *filter_info =
3556                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3557         struct e1000_2tuple_filter *filter;
3558         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3559         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3560         int i, ret;
3561
3562         filter = rte_zmalloc("e1000_2tuple_filter",
3563                         sizeof(struct e1000_2tuple_filter), 0);
3564         if (filter == NULL)
3565                 return -ENOMEM;
3566
3567         ret = ntuple_filter_to_2tuple(ntuple_filter,
3568                                       &filter->filter_info);
3569         if (ret < 0) {
3570                 rte_free(filter);
3571                 return ret;
3572         }
3573         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3574                                          &filter->filter_info) != NULL) {
3575                 PMD_DRV_LOG(ERR, "filter exists.");
3576                 rte_free(filter);
3577                 return -EEXIST;
3578         }
3579         filter->queue = ntuple_filter->queue;
3580
3581         /*
3582          * look for an unused 2tuple filter index,
3583          * and insert the filter to list.
3584          */
3585         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3586                 if (!(filter_info->twotuple_mask & (1 << i))) {
3587                         filter_info->twotuple_mask |= 1 << i;
3588                         filter->index = i;
3589                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3590                                           filter,
3591                                           entries);
3592                         break;
3593                 }
3594         }
3595         if (i >= E1000_MAX_TTQF_FILTERS) {
3596                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3597                 rte_free(filter);
3598                 return -ENOSYS;
3599         }
3600
3601         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3602         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3603                 imir |= E1000_IMIR_PORT_BP;
3604         else
3605                 imir &= ~E1000_IMIR_PORT_BP;
3606
3607         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3608
3609         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3610         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3611         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3612         if (filter->filter_info.proto_mask == 0)
3613                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3614
3615         /* tcp flags bits setting. */
3616         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3617                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3618                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3619                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3620                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3621                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3622                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3623                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3624                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3625                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3626                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3627                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3628                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3629         } else
3630                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3631         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3632         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3633         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3634         return 0;
3635 }
3636
3637 /*
3638  * igb_remove_2tuple_filter - remove a 2tuple filter
3639  *
3640  * @param
3641  * dev: Pointer to struct rte_eth_dev.
3642  * ntuple_filter: ponter to the filter that will be removed.
3643  *
3644  * @return
3645  *    - On success, zero.
3646  *    - On failure, a negative value.
3647  */
3648 static int
3649 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3650                         struct rte_eth_ntuple_filter *ntuple_filter)
3651 {
3652         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3653         struct e1000_filter_info *filter_info =
3654                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3655         struct e1000_2tuple_filter_info filter_2tuple;
3656         struct e1000_2tuple_filter *filter;
3657         int ret;
3658
3659         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3660         ret = ntuple_filter_to_2tuple(ntuple_filter,
3661                                       &filter_2tuple);
3662         if (ret < 0)
3663                 return ret;
3664
3665         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3666                                          &filter_2tuple);
3667         if (filter == NULL) {
3668                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3669                 return -ENOENT;
3670         }
3671
3672         filter_info->twotuple_mask &= ~(1 << filter->index);
3673         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3674         rte_free(filter);
3675
3676         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3677         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3678         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3679         return 0;
3680 }
3681
3682 static inline struct e1000_flex_filter *
3683 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3684                         struct e1000_flex_filter_info *key)
3685 {
3686         struct e1000_flex_filter *it;
3687
3688         TAILQ_FOREACH(it, filter_list, entries) {
3689                 if (memcmp(key, &it->filter_info,
3690                         sizeof(struct e1000_flex_filter_info)) == 0)
3691                         return it;
3692         }
3693
3694         return NULL;
3695 }
3696
3697 static int
3698 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3699                         struct rte_eth_flex_filter *filter,
3700                         bool add)
3701 {
3702         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703         struct e1000_filter_info *filter_info =
3704                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3705         struct e1000_flex_filter *flex_filter, *it;
3706         uint32_t wufc, queueing, mask;
3707         uint32_t reg_off;
3708         uint8_t shift, i, j = 0;
3709
3710         flex_filter = rte_zmalloc("e1000_flex_filter",
3711                         sizeof(struct e1000_flex_filter), 0);
3712         if (flex_filter == NULL)
3713                 return -ENOMEM;
3714
3715         flex_filter->filter_info.len = filter->len;
3716         flex_filter->filter_info.priority = filter->priority;
3717         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3718         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3719                 mask = 0;
3720                 /* reverse bits in flex filter's mask*/
3721                 for (shift = 0; shift < CHAR_BIT; shift++) {
3722                         if (filter->mask[i] & (0x01 << shift))
3723                                 mask |= (0x80 >> shift);
3724                 }
3725                 flex_filter->filter_info.mask[i] = mask;
3726         }
3727
3728         wufc = E1000_READ_REG(hw, E1000_WUFC);
3729         if (flex_filter->index < E1000_MAX_FHFT)
3730                 reg_off = E1000_FHFT(flex_filter->index);
3731         else
3732                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3733
3734         if (add) {
3735                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3736                                 &flex_filter->filter_info) != NULL) {
3737                         PMD_DRV_LOG(ERR, "filter exists.");
3738                         rte_free(flex_filter);
3739                         return -EEXIST;
3740                 }
3741                 flex_filter->queue = filter->queue;
3742                 /*
3743                  * look for an unused flex filter index
3744                  * and insert the filter into the list.
3745                  */
3746                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3747                         if (!(filter_info->flex_mask & (1 << i))) {
3748                                 filter_info->flex_mask |= 1 << i;
3749                                 flex_filter->index = i;
3750                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3751                                         flex_filter,
3752                                         entries);
3753                                 break;
3754                         }
3755                 }
3756                 if (i >= E1000_MAX_FLEX_FILTERS) {
3757                         PMD_DRV_LOG(ERR, "flex filters are full.");
3758                         rte_free(flex_filter);
3759                         return -ENOSYS;
3760                 }
3761
3762                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3763                                 (E1000_WUFC_FLX0 << flex_filter->index));
3764                 queueing = filter->len |
3765                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3766                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3767                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3768                                 queueing);
3769                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3770                         E1000_WRITE_REG(hw, reg_off,
3771                                         flex_filter->filter_info.dwords[j]);
3772                         reg_off += sizeof(uint32_t);
3773                         E1000_WRITE_REG(hw, reg_off,
3774                                         flex_filter->filter_info.dwords[++j]);
3775                         reg_off += sizeof(uint32_t);
3776                         E1000_WRITE_REG(hw, reg_off,
3777                                 (uint32_t)flex_filter->filter_info.mask[i]);
3778                         reg_off += sizeof(uint32_t) * 2;
3779                         ++j;
3780                 }
3781         } else {
3782                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3783                                 &flex_filter->filter_info);
3784                 if (it == NULL) {
3785                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3786                         rte_free(flex_filter);
3787                         return -ENOENT;
3788                 }
3789
3790                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3791                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3792                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3793                         (~(E1000_WUFC_FLX0 << it->index)));
3794
3795                 filter_info->flex_mask &= ~(1 << it->index);
3796                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3797                 rte_free(it);
3798                 rte_free(flex_filter);
3799         }
3800
3801         return 0;
3802 }
3803
3804 static int
3805 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3806                         struct rte_eth_flex_filter *filter)
3807 {
3808         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809         struct e1000_filter_info *filter_info =
3810                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3811         struct e1000_flex_filter flex_filter, *it;
3812         uint32_t wufc, queueing, wufc_en = 0;
3813
3814         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3815         flex_filter.filter_info.len = filter->len;
3816         flex_filter.filter_info.priority = filter->priority;
3817         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3818         memcpy(flex_filter.filter_info.mask, filter->mask,
3819                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3820
3821         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3822                                 &flex_filter.filter_info);
3823         if (it == NULL) {
3824                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3825                 return -ENOENT;
3826         }
3827
3828         wufc = E1000_READ_REG(hw, E1000_WUFC);
3829         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3830
3831         if ((wufc & wufc_en) == wufc_en) {
3832                 uint32_t reg_off = 0;
3833                 if (it->index < E1000_MAX_FHFT)
3834                         reg_off = E1000_FHFT(it->index);
3835                 else
3836                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3837
3838                 queueing = E1000_READ_REG(hw,
3839                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3840                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3841                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3842                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3843                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3844                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3845                 return 0;
3846         }
3847         return -ENOENT;
3848 }
3849
3850 static int
3851 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3852                         enum rte_filter_op filter_op,
3853                         void *arg)
3854 {
3855         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856         struct rte_eth_flex_filter *filter;
3857         int ret = 0;
3858
3859         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3860
3861         if (filter_op == RTE_ETH_FILTER_NOP)
3862                 return ret;
3863
3864         if (arg == NULL) {
3865                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3866                             filter_op);
3867                 return -EINVAL;
3868         }
3869
3870         filter = (struct rte_eth_flex_filter *)arg;
3871         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3872             || filter->len % sizeof(uint64_t) != 0) {
3873                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3874                 return -EINVAL;
3875         }
3876         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3877                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3878                 return -EINVAL;
3879         }
3880
3881         switch (filter_op) {
3882         case RTE_ETH_FILTER_ADD:
3883                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3884                 break;
3885         case RTE_ETH_FILTER_DELETE:
3886                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3887                 break;
3888         case RTE_ETH_FILTER_GET:
3889                 ret = eth_igb_get_flex_filter(dev, filter);
3890                 break;
3891         default:
3892                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3893                 ret = -EINVAL;
3894                 break;
3895         }
3896
3897         return ret;
3898 }
3899
3900 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3901 static inline int
3902 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3903                         struct e1000_5tuple_filter_info *filter_info)
3904 {
3905         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3906                 return -EINVAL;
3907         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3908                 return -EINVAL;  /* filter index is out of range. */
3909         if (filter->tcp_flags > TCP_FLAG_ALL)
3910                 return -EINVAL;  /* flags is invalid. */
3911
3912         switch (filter->dst_ip_mask) {
3913         case UINT32_MAX:
3914                 filter_info->dst_ip_mask = 0;
3915                 filter_info->dst_ip = filter->dst_ip;
3916                 break;
3917         case 0:
3918                 filter_info->dst_ip_mask = 1;
3919                 break;
3920         default:
3921                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3922                 return -EINVAL;
3923         }
3924
3925         switch (filter->src_ip_mask) {
3926         case UINT32_MAX:
3927                 filter_info->src_ip_mask = 0;
3928                 filter_info->src_ip = filter->src_ip;
3929                 break;
3930         case 0:
3931                 filter_info->src_ip_mask = 1;
3932                 break;
3933         default:
3934                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3935                 return -EINVAL;
3936         }
3937
3938         switch (filter->dst_port_mask) {
3939         case UINT16_MAX:
3940                 filter_info->dst_port_mask = 0;
3941                 filter_info->dst_port = filter->dst_port;
3942                 break;
3943         case 0:
3944                 filter_info->dst_port_mask = 1;
3945                 break;
3946         default:
3947                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3948                 return -EINVAL;
3949         }
3950
3951         switch (filter->src_port_mask) {
3952         case UINT16_MAX:
3953                 filter_info->src_port_mask = 0;
3954                 filter_info->src_port = filter->src_port;
3955                 break;
3956         case 0:
3957                 filter_info->src_port_mask = 1;
3958                 break;
3959         default:
3960                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3961                 return -EINVAL;
3962         }
3963
3964         switch (filter->proto_mask) {
3965         case UINT8_MAX:
3966                 filter_info->proto_mask = 0;
3967                 filter_info->proto = filter->proto;
3968                 break;
3969         case 0:
3970                 filter_info->proto_mask = 1;
3971                 break;
3972         default:
3973                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3974                 return -EINVAL;
3975         }
3976
3977         filter_info->priority = (uint8_t)filter->priority;
3978         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3979                 filter_info->tcp_flags = filter->tcp_flags;
3980         else
3981                 filter_info->tcp_flags = 0;
3982
3983         return 0;
3984 }
3985
3986 static inline struct e1000_5tuple_filter *
3987 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3988                         struct e1000_5tuple_filter_info *key)
3989 {
3990         struct e1000_5tuple_filter *it;
3991
3992         TAILQ_FOREACH(it, filter_list, entries) {
3993                 if (memcmp(key, &it->filter_info,
3994                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3995                         return it;
3996                 }
3997         }
3998         return NULL;
3999 }
4000
4001 /*
4002  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4003  *
4004  * @param
4005  * dev: Pointer to struct rte_eth_dev.
4006  * ntuple_filter: ponter to the filter that will be added.
4007  *
4008  * @return
4009  *    - On success, zero.
4010  *    - On failure, a negative value.
4011  */
4012 static int
4013 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4014                         struct rte_eth_ntuple_filter *ntuple_filter)
4015 {
4016         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017         struct e1000_filter_info *filter_info =
4018                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4019         struct e1000_5tuple_filter *filter;
4020         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4021         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4022         uint8_t i;
4023         int ret;
4024
4025         filter = rte_zmalloc("e1000_5tuple_filter",
4026                         sizeof(struct e1000_5tuple_filter), 0);
4027         if (filter == NULL)
4028                 return -ENOMEM;
4029
4030         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4031                                             &filter->filter_info);
4032         if (ret < 0) {
4033                 rte_free(filter);
4034                 return ret;
4035         }
4036
4037         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4038                                          &filter->filter_info) != NULL) {
4039                 PMD_DRV_LOG(ERR, "filter exists.");
4040                 rte_free(filter);
4041                 return -EEXIST;
4042         }
4043         filter->queue = ntuple_filter->queue;
4044
4045         /*
4046          * look for an unused 5tuple filter index,
4047          * and insert the filter to list.
4048          */
4049         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4050                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4051                         filter_info->fivetuple_mask |= 1 << i;
4052                         filter->index = i;
4053                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4054                                           filter,
4055                                           entries);
4056                         break;
4057                 }
4058         }
4059         if (i >= E1000_MAX_FTQF_FILTERS) {
4060                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4061                 rte_free(filter);
4062                 return -ENOSYS;
4063         }
4064
4065         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4066         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4067                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4068         if (filter->filter_info.dst_ip_mask == 0)
4069                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4070         if (filter->filter_info.src_port_mask == 0)
4071                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4072         if (filter->filter_info.proto_mask == 0)
4073                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4074         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4075                 E1000_FTQF_QUEUE_MASK;
4076         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4077         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4078         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4079         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4080
4081         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4082         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4083
4084         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4085         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4086                 imir |= E1000_IMIR_PORT_BP;
4087         else
4088                 imir &= ~E1000_IMIR_PORT_BP;
4089         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4090
4091         /* tcp flags bits setting. */
4092         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4093                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4094                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4095                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4096                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4097                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4098                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4099                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4100                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4101                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4102                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4103                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4104                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4105         } else
4106                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4107         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4108         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4109         return 0;
4110 }
4111
4112 /*
4113  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4114  *
4115  * @param
4116  * dev: Pointer to struct rte_eth_dev.
4117  * ntuple_filter: ponter to the filter that will be removed.
4118  *
4119  * @return
4120  *    - On success, zero.
4121  *    - On failure, a negative value.
4122  */
4123 static int
4124 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4125                                 struct rte_eth_ntuple_filter *ntuple_filter)
4126 {
4127         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128         struct e1000_filter_info *filter_info =
4129                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4130         struct e1000_5tuple_filter_info filter_5tuple;
4131         struct e1000_5tuple_filter *filter;
4132         int ret;
4133
4134         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4135         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4136                                             &filter_5tuple);
4137         if (ret < 0)
4138                 return ret;
4139
4140         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4141                                          &filter_5tuple);
4142         if (filter == NULL) {
4143                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4144                 return -ENOENT;
4145         }
4146
4147         filter_info->fivetuple_mask &= ~(1 << filter->index);
4148         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4149         rte_free(filter);
4150
4151         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4152                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4153         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4154         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4155         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4156         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4157         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4158         return 0;
4159 }
4160
4161 static int
4162 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4163 {
4164         uint32_t rctl;
4165         struct e1000_hw *hw;
4166         struct rte_eth_dev_info dev_info;
4167         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4168                                      VLAN_TAG_SIZE);
4169
4170         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171
4172 #ifdef RTE_LIBRTE_82571_SUPPORT
4173         /* XXX: not bigger than max_rx_pktlen */
4174         if (hw->mac.type == e1000_82571)
4175                 return -ENOTSUP;
4176 #endif
4177         eth_igb_infos_get(dev, &dev_info);
4178
4179         /* check that mtu is within the allowed range */
4180         if ((mtu < ETHER_MIN_MTU) ||
4181             (frame_size > dev_info.max_rx_pktlen))
4182                 return -EINVAL;
4183
4184         /* refuse mtu that requires the support of scattered packets when this
4185          * feature has not been enabled before. */
4186         if (!dev->data->scattered_rx &&
4187             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4188                 return -EINVAL;
4189
4190         rctl = E1000_READ_REG(hw, E1000_RCTL);
4191
4192         /* switch to jumbo mode if needed */
4193         if (frame_size > ETHER_MAX_LEN) {
4194                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4195                 rctl |= E1000_RCTL_LPE;
4196         } else {
4197                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4198                 rctl &= ~E1000_RCTL_LPE;
4199         }
4200         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4201
4202         /* update max frame size */
4203         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4204
4205         E1000_WRITE_REG(hw, E1000_RLPML,
4206                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4207
4208         return 0;
4209 }
4210
4211 /*
4212  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4213  *
4214  * @param
4215  * dev: Pointer to struct rte_eth_dev.
4216  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4217  * add: if true, add filter, if false, remove filter
4218  *
4219  * @return
4220  *    - On success, zero.
4221  *    - On failure, a negative value.
4222  */
4223 static int
4224 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4225                         struct rte_eth_ntuple_filter *ntuple_filter,
4226                         bool add)
4227 {
4228         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229         int ret;
4230
4231         switch (ntuple_filter->flags) {
4232         case RTE_5TUPLE_FLAGS:
4233         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4234                 if (hw->mac.type != e1000_82576)
4235                         return -ENOTSUP;
4236                 if (add)
4237                         ret = igb_add_5tuple_filter_82576(dev,
4238                                                           ntuple_filter);
4239                 else
4240                         ret = igb_remove_5tuple_filter_82576(dev,
4241                                                              ntuple_filter);
4242                 break;
4243         case RTE_2TUPLE_FLAGS:
4244         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4245                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4246                         return -ENOTSUP;
4247                 if (add)
4248                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4249                 else
4250                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4251                 break;
4252         default:
4253                 ret = -EINVAL;
4254                 break;
4255         }
4256
4257         return ret;
4258 }
4259
4260 /*
4261  * igb_get_ntuple_filter - get a ntuple filter
4262  *
4263  * @param
4264  * dev: Pointer to struct rte_eth_dev.
4265  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4266  *
4267  * @return
4268  *    - On success, zero.
4269  *    - On failure, a negative value.
4270  */
4271 static int
4272 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4273                         struct rte_eth_ntuple_filter *ntuple_filter)
4274 {
4275         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276         struct e1000_filter_info *filter_info =
4277                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4278         struct e1000_5tuple_filter_info filter_5tuple;
4279         struct e1000_2tuple_filter_info filter_2tuple;
4280         struct e1000_5tuple_filter *p_5tuple_filter;
4281         struct e1000_2tuple_filter *p_2tuple_filter;
4282         int ret;
4283
4284         switch (ntuple_filter->flags) {
4285         case RTE_5TUPLE_FLAGS:
4286         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4287                 if (hw->mac.type != e1000_82576)
4288                         return -ENOTSUP;
4289                 memset(&filter_5tuple,
4290                         0,
4291                         sizeof(struct e1000_5tuple_filter_info));
4292                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4293                                                     &filter_5tuple);
4294                 if (ret < 0)
4295                         return ret;
4296                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4297                                         &filter_info->fivetuple_list,
4298                                         &filter_5tuple);
4299                 if (p_5tuple_filter == NULL) {
4300                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4301                         return -ENOENT;
4302                 }
4303                 ntuple_filter->queue = p_5tuple_filter->queue;
4304                 break;
4305         case RTE_2TUPLE_FLAGS:
4306         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4307                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4308                         return -ENOTSUP;
4309                 memset(&filter_2tuple,
4310                         0,
4311                         sizeof(struct e1000_2tuple_filter_info));
4312                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4313                 if (ret < 0)
4314                         return ret;
4315                 p_2tuple_filter = igb_2tuple_filter_lookup(
4316                                         &filter_info->twotuple_list,
4317                                         &filter_2tuple);
4318                 if (p_2tuple_filter == NULL) {
4319                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4320                         return -ENOENT;
4321                 }
4322                 ntuple_filter->queue = p_2tuple_filter->queue;
4323                 break;
4324         default:
4325                 ret = -EINVAL;
4326                 break;
4327         }
4328
4329         return 0;
4330 }
4331
4332 /*
4333  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4334  * @dev: pointer to rte_eth_dev structure
4335  * @filter_op:operation will be taken.
4336  * @arg: a pointer to specific structure corresponding to the filter_op
4337  */
4338 static int
4339 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4340                                 enum rte_filter_op filter_op,
4341                                 void *arg)
4342 {
4343         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         int ret;
4345
4346         MAC_TYPE_FILTER_SUP(hw->mac.type);
4347
4348         if (filter_op == RTE_ETH_FILTER_NOP)
4349                 return 0;
4350
4351         if (arg == NULL) {
4352                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4353                             filter_op);
4354                 return -EINVAL;
4355         }
4356
4357         switch (filter_op) {
4358         case RTE_ETH_FILTER_ADD:
4359                 ret = igb_add_del_ntuple_filter(dev,
4360                         (struct rte_eth_ntuple_filter *)arg,
4361                         TRUE);
4362                 break;
4363         case RTE_ETH_FILTER_DELETE:
4364                 ret = igb_add_del_ntuple_filter(dev,
4365                         (struct rte_eth_ntuple_filter *)arg,
4366                         FALSE);
4367                 break;
4368         case RTE_ETH_FILTER_GET:
4369                 ret = igb_get_ntuple_filter(dev,
4370                         (struct rte_eth_ntuple_filter *)arg);
4371                 break;
4372         default:
4373                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4374                 ret = -EINVAL;
4375                 break;
4376         }
4377         return ret;
4378 }
4379
4380 static inline int
4381 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4382                         uint16_t ethertype)
4383 {
4384         int i;
4385
4386         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4387                 if (filter_info->ethertype_filters[i] == ethertype &&
4388                     (filter_info->ethertype_mask & (1 << i)))
4389                         return i;
4390         }
4391         return -1;
4392 }
4393
4394 static inline int
4395 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4396                         uint16_t ethertype)
4397 {
4398         int i;
4399
4400         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4401                 if (!(filter_info->ethertype_mask & (1 << i))) {
4402                         filter_info->ethertype_mask |= 1 << i;
4403                         filter_info->ethertype_filters[i] = ethertype;
4404                         return i;
4405                 }
4406         }
4407         return -1;
4408 }
4409
4410 static inline int
4411 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4412                         uint8_t idx)
4413 {
4414         if (idx >= E1000_MAX_ETQF_FILTERS)
4415                 return -1;
4416         filter_info->ethertype_mask &= ~(1 << idx);
4417         filter_info->ethertype_filters[idx] = 0;
4418         return idx;
4419 }
4420
4421
4422 static int
4423 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4424                         struct rte_eth_ethertype_filter *filter,
4425                         bool add)
4426 {
4427         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428         struct e1000_filter_info *filter_info =
4429                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4430         uint32_t etqf = 0;
4431         int ret;
4432
4433         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4434                 filter->ether_type == ETHER_TYPE_IPv6) {
4435                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4436                         " ethertype filter.", filter->ether_type);
4437                 return -EINVAL;
4438         }
4439
4440         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4441                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4442                 return -EINVAL;
4443         }
4444         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4445                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4446                 return -EINVAL;
4447         }
4448
4449         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4450         if (ret >= 0 && add) {
4451                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4452                             filter->ether_type);
4453                 return -EEXIST;
4454         }
4455         if (ret < 0 && !add) {
4456                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4457                             filter->ether_type);
4458                 return -ENOENT;
4459         }
4460
4461         if (add) {
4462                 ret = igb_ethertype_filter_insert(filter_info,
4463                         filter->ether_type);
4464                 if (ret < 0) {
4465                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4466                         return -ENOSYS;
4467                 }
4468
4469                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4470                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4471                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4472         } else {
4473                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4474                 if (ret < 0)
4475                         return -ENOSYS;
4476         }
4477         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4478         E1000_WRITE_FLUSH(hw);
4479
4480         return 0;
4481 }
4482
4483 static int
4484 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4485                         struct rte_eth_ethertype_filter *filter)
4486 {
4487         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488         struct e1000_filter_info *filter_info =
4489                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4490         uint32_t etqf;
4491         int ret;
4492
4493         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4494         if (ret < 0) {
4495                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4496                             filter->ether_type);
4497                 return -ENOENT;
4498         }
4499
4500         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4501         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4502                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4503                 filter->flags = 0;
4504                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4505                                 E1000_ETQF_QUEUE_SHIFT;
4506                 return 0;
4507         }
4508
4509         return -ENOENT;
4510 }
4511
4512 /*
4513  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4514  * @dev: pointer to rte_eth_dev structure
4515  * @filter_op:operation will be taken.
4516  * @arg: a pointer to specific structure corresponding to the filter_op
4517  */
4518 static int
4519 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4520                                 enum rte_filter_op filter_op,
4521                                 void *arg)
4522 {
4523         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524         int ret;
4525
4526         MAC_TYPE_FILTER_SUP(hw->mac.type);
4527
4528         if (filter_op == RTE_ETH_FILTER_NOP)
4529                 return 0;
4530
4531         if (arg == NULL) {
4532                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4533                             filter_op);
4534                 return -EINVAL;
4535         }
4536
4537         switch (filter_op) {
4538         case RTE_ETH_FILTER_ADD:
4539                 ret = igb_add_del_ethertype_filter(dev,
4540                         (struct rte_eth_ethertype_filter *)arg,
4541                         TRUE);
4542                 break;
4543         case RTE_ETH_FILTER_DELETE:
4544                 ret = igb_add_del_ethertype_filter(dev,
4545                         (struct rte_eth_ethertype_filter *)arg,
4546                         FALSE);
4547                 break;
4548         case RTE_ETH_FILTER_GET:
4549                 ret = igb_get_ethertype_filter(dev,
4550                         (struct rte_eth_ethertype_filter *)arg);
4551                 break;
4552         default:
4553                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4554                 ret = -EINVAL;
4555                 break;
4556         }
4557         return ret;
4558 }
4559
4560 static int
4561 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4562                      enum rte_filter_type filter_type,
4563                      enum rte_filter_op filter_op,
4564                      void *arg)
4565 {
4566         int ret = -EINVAL;
4567
4568         switch (filter_type) {
4569         case RTE_ETH_FILTER_NTUPLE:
4570                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4571                 break;
4572         case RTE_ETH_FILTER_ETHERTYPE:
4573                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4574                 break;
4575         case RTE_ETH_FILTER_SYN:
4576                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4577                 break;
4578         case RTE_ETH_FILTER_FLEXIBLE:
4579                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4580                 break;
4581         default:
4582                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4583                                                         filter_type);
4584                 break;
4585         }
4586
4587         return ret;
4588 }
4589
4590 static int
4591 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4592                          struct ether_addr *mc_addr_set,
4593                          uint32_t nb_mc_addr)
4594 {
4595         struct e1000_hw *hw;
4596
4597         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4598         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4599         return 0;
4600 }
4601
4602 static uint64_t
4603 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4604 {
4605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606         uint64_t systime_cycles;
4607
4608         switch (hw->mac.type) {
4609         case e1000_i210:
4610         case e1000_i211:
4611                 /*
4612                  * Need to read System Time Residue Register to be able
4613                  * to read the other two registers.
4614                  */
4615                 E1000_READ_REG(hw, E1000_SYSTIMR);
4616                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4617                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4618                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4619                                 * NSEC_PER_SEC;
4620                 break;
4621         case e1000_82580:
4622         case e1000_i350:
4623         case e1000_i354:
4624                 /*
4625                  * Need to read System Time Residue Register to be able
4626                  * to read the other two registers.
4627                  */
4628                 E1000_READ_REG(hw, E1000_SYSTIMR);
4629                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4630                 /* Only the 8 LSB are valid. */
4631                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4632                                 & 0xff) << 32;
4633                 break;
4634         default:
4635                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4636                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4637                                 << 32;
4638                 break;
4639         }
4640
4641         return systime_cycles;
4642 }
4643
4644 static uint64_t
4645 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4646 {
4647         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4648         uint64_t rx_tstamp_cycles;
4649
4650         switch (hw->mac.type) {
4651         case e1000_i210:
4652         case e1000_i211:
4653                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4654                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4655                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4656                                 * NSEC_PER_SEC;
4657                 break;
4658         case e1000_82580:
4659         case e1000_i350:
4660         case e1000_i354:
4661                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4662                 /* Only the 8 LSB are valid. */
4663                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4664                                 & 0xff) << 32;
4665                 break;
4666         default:
4667                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4668                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4669                                 << 32;
4670                 break;
4671         }
4672
4673         return rx_tstamp_cycles;
4674 }
4675
4676 static uint64_t
4677 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4678 {
4679         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680         uint64_t tx_tstamp_cycles;
4681
4682         switch (hw->mac.type) {
4683         case e1000_i210:
4684         case e1000_i211:
4685                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4686                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4687                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4688                                 * NSEC_PER_SEC;
4689                 break;
4690         case e1000_82580:
4691         case e1000_i350:
4692         case e1000_i354:
4693                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4694                 /* Only the 8 LSB are valid. */
4695                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4696                                 & 0xff) << 32;
4697                 break;
4698         default:
4699                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4700                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4701                                 << 32;
4702                 break;
4703         }
4704
4705         return tx_tstamp_cycles;
4706 }
4707
4708 static void
4709 igb_start_timecounters(struct rte_eth_dev *dev)
4710 {
4711         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712         struct e1000_adapter *adapter =
4713                 (struct e1000_adapter *)dev->data->dev_private;
4714         uint32_t incval = 1;
4715         uint32_t shift = 0;
4716         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4717
4718         switch (hw->mac.type) {
4719         case e1000_82580:
4720         case e1000_i350:
4721         case e1000_i354:
4722                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4723                 mask = (1ULL << 40) - 1;
4724                 /* fall-through */
4725         case e1000_i210:
4726         case e1000_i211:
4727                 /*
4728                  * Start incrementing the register
4729                  * used to timestamp PTP packets.
4730                  */
4731                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4732                 break;
4733         case e1000_82576:
4734                 incval = E1000_INCVALUE_82576;
4735                 shift = IGB_82576_TSYNC_SHIFT;
4736                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4737                                 E1000_INCPERIOD_82576 | incval);
4738                 break;
4739         default:
4740                 /* Not supported */
4741                 return;
4742         }
4743
4744         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4745         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4746         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4747
4748         adapter->systime_tc.cc_mask = mask;
4749         adapter->systime_tc.cc_shift = shift;
4750         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4751
4752         adapter->rx_tstamp_tc.cc_mask = mask;
4753         adapter->rx_tstamp_tc.cc_shift = shift;
4754         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4755
4756         adapter->tx_tstamp_tc.cc_mask = mask;
4757         adapter->tx_tstamp_tc.cc_shift = shift;
4758         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4759 }
4760
4761 static int
4762 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4763 {
4764         struct e1000_adapter *adapter =
4765                         (struct e1000_adapter *)dev->data->dev_private;
4766
4767         adapter->systime_tc.nsec += delta;
4768         adapter->rx_tstamp_tc.nsec += delta;
4769         adapter->tx_tstamp_tc.nsec += delta;
4770
4771         return 0;
4772 }
4773
4774 static int
4775 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4776 {
4777         uint64_t ns;
4778         struct e1000_adapter *adapter =
4779                         (struct e1000_adapter *)dev->data->dev_private;
4780
4781         ns = rte_timespec_to_ns(ts);
4782
4783         /* Set the timecounters to a new value. */
4784         adapter->systime_tc.nsec = ns;
4785         adapter->rx_tstamp_tc.nsec = ns;
4786         adapter->tx_tstamp_tc.nsec = ns;
4787
4788         return 0;
4789 }
4790
4791 static int
4792 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4793 {
4794         uint64_t ns, systime_cycles;
4795         struct e1000_adapter *adapter =
4796                         (struct e1000_adapter *)dev->data->dev_private;
4797
4798         systime_cycles = igb_read_systime_cyclecounter(dev);
4799         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4800         *ts = rte_ns_to_timespec(ns);
4801
4802         return 0;
4803 }
4804
4805 static int
4806 igb_timesync_enable(struct rte_eth_dev *dev)
4807 {
4808         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809         uint32_t tsync_ctl;
4810         uint32_t tsauxc;
4811
4812         /* Stop the timesync system time. */
4813         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4814         /* Reset the timesync system time value. */
4815         switch (hw->mac.type) {
4816         case e1000_82580:
4817         case e1000_i350:
4818         case e1000_i354:
4819         case e1000_i210:
4820         case e1000_i211:
4821                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4822                 /* fall-through */
4823         case e1000_82576:
4824                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4825                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4826                 break;
4827         default:
4828                 /* Not supported. */
4829                 return -ENOTSUP;
4830         }
4831
4832         /* Enable system time for it isn't on by default. */
4833         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4834         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4835         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4836
4837         igb_start_timecounters(dev);
4838
4839         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4840         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4841                         (ETHER_TYPE_1588 |
4842                          E1000_ETQF_FILTER_ENABLE |
4843                          E1000_ETQF_1588));
4844
4845         /* Enable timestamping of received PTP packets. */
4846         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4847         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4848         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4849
4850         /* Enable Timestamping of transmitted PTP packets. */
4851         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4852         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4853         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4854
4855         return 0;
4856 }
4857
4858 static int
4859 igb_timesync_disable(struct rte_eth_dev *dev)
4860 {
4861         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862         uint32_t tsync_ctl;
4863
4864         /* Disable timestamping of transmitted PTP packets. */
4865         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4866         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4867         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4868
4869         /* Disable timestamping of received PTP packets. */
4870         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4871         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4872         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4873
4874         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4875         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4876
4877         /* Stop incrementating the System Time registers. */
4878         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4879
4880         return 0;
4881 }
4882
4883 static int
4884 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4885                                struct timespec *timestamp,
4886                                uint32_t flags __rte_unused)
4887 {
4888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889         struct e1000_adapter *adapter =
4890                         (struct e1000_adapter *)dev->data->dev_private;
4891         uint32_t tsync_rxctl;
4892         uint64_t rx_tstamp_cycles;
4893         uint64_t ns;
4894
4895         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4896         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4897                 return -EINVAL;
4898
4899         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4900         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4901         *timestamp = rte_ns_to_timespec(ns);
4902
4903         return  0;
4904 }
4905
4906 static int
4907 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4908                                struct timespec *timestamp)
4909 {
4910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         struct e1000_adapter *adapter =
4912                         (struct e1000_adapter *)dev->data->dev_private;
4913         uint32_t tsync_txctl;
4914         uint64_t tx_tstamp_cycles;
4915         uint64_t ns;
4916
4917         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4918         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4919                 return -EINVAL;
4920
4921         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4922         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4923         *timestamp = rte_ns_to_timespec(ns);
4924
4925         return  0;
4926 }
4927
4928 static int
4929 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4930 {
4931         int count = 0;
4932         int g_ind = 0;
4933         const struct reg_info *reg_group;
4934
4935         while ((reg_group = igb_regs[g_ind++]))
4936                 count += igb_reg_group_count(reg_group);
4937
4938         return count;
4939 }
4940
4941 static int
4942 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4943 {
4944         int count = 0;
4945         int g_ind = 0;
4946         const struct reg_info *reg_group;
4947
4948         while ((reg_group = igbvf_regs[g_ind++]))
4949                 count += igb_reg_group_count(reg_group);
4950
4951         return count;
4952 }
4953
4954 static int
4955 eth_igb_get_regs(struct rte_eth_dev *dev,
4956         struct rte_dev_reg_info *regs)
4957 {
4958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4959         uint32_t *data = regs->data;
4960         int g_ind = 0;
4961         int count = 0;
4962         const struct reg_info *reg_group;
4963
4964         if (data == NULL) {
4965                 regs->length = eth_igb_get_reg_length(dev);
4966                 regs->width = sizeof(uint32_t);
4967                 return 0;
4968         }
4969
4970         /* Support only full register dump */
4971         if ((regs->length == 0) ||
4972             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4973                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4974                         hw->device_id;
4975                 while ((reg_group = igb_regs[g_ind++]))
4976                         count += igb_read_regs_group(dev, &data[count],
4977                                                         reg_group);
4978                 return 0;
4979         }
4980
4981         return -ENOTSUP;
4982 }
4983
4984 static int
4985 igbvf_get_regs(struct rte_eth_dev *dev,
4986         struct rte_dev_reg_info *regs)
4987 {
4988         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989         uint32_t *data = regs->data;
4990         int g_ind = 0;
4991         int count = 0;
4992         const struct reg_info *reg_group;
4993
4994         if (data == NULL) {
4995                 regs->length = igbvf_get_reg_length(dev);
4996                 regs->width = sizeof(uint32_t);
4997                 return 0;
4998         }
4999
5000         /* Support only full register dump */
5001         if ((regs->length == 0) ||
5002             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5003                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5004                         hw->device_id;
5005                 while ((reg_group = igbvf_regs[g_ind++]))
5006                         count += igb_read_regs_group(dev, &data[count],
5007                                                         reg_group);
5008                 return 0;
5009         }
5010
5011         return -ENOTSUP;
5012 }
5013
5014 static int
5015 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5016 {
5017         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018
5019         /* Return unit is byte count */
5020         return hw->nvm.word_size * 2;
5021 }
5022
5023 static int
5024 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5025         struct rte_dev_eeprom_info *in_eeprom)
5026 {
5027         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5028         struct e1000_nvm_info *nvm = &hw->nvm;
5029         uint16_t *data = in_eeprom->data;
5030         int first, length;
5031
5032         first = in_eeprom->offset >> 1;
5033         length = in_eeprom->length >> 1;
5034         if ((first >= hw->nvm.word_size) ||
5035             ((first + length) >= hw->nvm.word_size))
5036                 return -EINVAL;
5037
5038         in_eeprom->magic = hw->vendor_id |
5039                 ((uint32_t)hw->device_id << 16);
5040
5041         if ((nvm->ops.read) == NULL)
5042                 return -ENOTSUP;
5043
5044         return nvm->ops.read(hw, first, length, data);
5045 }
5046
5047 static int
5048 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5049         struct rte_dev_eeprom_info *in_eeprom)
5050 {
5051         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5052         struct e1000_nvm_info *nvm = &hw->nvm;
5053         uint16_t *data = in_eeprom->data;
5054         int first, length;
5055
5056         first = in_eeprom->offset >> 1;
5057         length = in_eeprom->length >> 1;
5058         if ((first >= hw->nvm.word_size) ||
5059             ((first + length) >= hw->nvm.word_size))
5060                 return -EINVAL;
5061
5062         in_eeprom->magic = (uint32_t)hw->vendor_id |
5063                 ((uint32_t)hw->device_id << 16);
5064
5065         if ((nvm->ops.write) == NULL)
5066                 return -ENOTSUP;
5067         return nvm->ops.write(hw,  first, length, data);
5068 }
5069
5070 static int
5071 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5072 {
5073         struct e1000_hw *hw =
5074                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         uint32_t mask = 1 << queue_id;
5076
5077         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5078         E1000_WRITE_FLUSH(hw);
5079
5080         return 0;
5081 }
5082
5083 static int
5084 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5085 {
5086         struct e1000_hw *hw =
5087                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088         uint32_t mask = 1 << queue_id;
5089         uint32_t regval;
5090
5091         regval = E1000_READ_REG(hw, E1000_EIMS);
5092         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5093         E1000_WRITE_FLUSH(hw);
5094
5095         rte_intr_enable(&dev->pci_dev->intr_handle);
5096
5097         return 0;
5098 }
5099
5100 static void
5101 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5102                    uint8_t index, uint8_t offset)
5103 {
5104         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5105
5106         /* clear bits */
5107         val &= ~((uint32_t)0xFF << offset);
5108
5109         /* write vector and valid bit */
5110         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5111
5112         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5113 }
5114
5115 static void
5116 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5117                            uint8_t queue, uint8_t msix_vector)
5118 {
5119         uint32_t tmp = 0;
5120
5121         if (hw->mac.type == e1000_82575) {
5122                 if (direction == 0)
5123                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5124                 else if (direction == 1)
5125                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5126                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5127         } else if (hw->mac.type == e1000_82576) {
5128                 if ((direction == 0) || (direction == 1))
5129                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5130                                            ((queue & 0x8) << 1) +
5131                                            8 * direction);
5132         } else if ((hw->mac.type == e1000_82580) ||
5133                         (hw->mac.type == e1000_i350) ||
5134                         (hw->mac.type == e1000_i354) ||
5135                         (hw->mac.type == e1000_i210) ||
5136                         (hw->mac.type == e1000_i211)) {
5137                 if ((direction == 0) || (direction == 1))
5138                         eth_igb_write_ivar(hw, msix_vector,
5139                                            queue >> 1,
5140                                            ((queue & 0x1) << 4) +
5141                                            8 * direction);
5142         }
5143 }
5144
5145 /* Sets up the hardware to generate MSI-X interrupts properly
5146  * @hw
5147  *  board private structure
5148  */
5149 static void
5150 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5151 {
5152         int queue_id;
5153         uint32_t tmpval, regval, intr_mask;
5154         struct e1000_hw *hw =
5155                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5156         uint32_t vec = E1000_MISC_VEC_ID;
5157         uint32_t base = E1000_MISC_VEC_ID;
5158         uint32_t misc_shift = 0;
5159
5160         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5161
5162         /* won't configure msix register if no mapping is done
5163          * between intr vector and event fd
5164          */
5165         if (!rte_intr_dp_is_en(intr_handle))
5166                 return;
5167
5168         if (rte_intr_allow_others(intr_handle)) {
5169                 vec = base = E1000_RX_VEC_START;
5170                 misc_shift = 1;
5171         }
5172
5173         /* set interrupt vector for other causes */
5174         if (hw->mac.type == e1000_82575) {
5175                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5176                 /* enable MSI-X PBA support */
5177                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5178
5179                 /* Auto-Mask interrupts upon ICR read */
5180                 tmpval |= E1000_CTRL_EXT_EIAME;
5181                 tmpval |= E1000_CTRL_EXT_IRCA;
5182
5183                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5184
5185                 /* enable msix_other interrupt */
5186                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5187                 regval = E1000_READ_REG(hw, E1000_EIAC);
5188                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5189                 regval = E1000_READ_REG(hw, E1000_EIAM);
5190                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5191         } else if ((hw->mac.type == e1000_82576) ||
5192                         (hw->mac.type == e1000_82580) ||
5193                         (hw->mac.type == e1000_i350) ||
5194                         (hw->mac.type == e1000_i354) ||
5195                         (hw->mac.type == e1000_i210) ||
5196                         (hw->mac.type == e1000_i211)) {
5197                 /* turn on MSI-X capability first */
5198                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5199                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5200                                         E1000_GPIE_NSICR);
5201                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5202                         misc_shift;
5203                 regval = E1000_READ_REG(hw, E1000_EIAC);
5204                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5205
5206                 /* enable msix_other interrupt */
5207                 regval = E1000_READ_REG(hw, E1000_EIMS);
5208                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5209                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5210                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5211         }
5212
5213         /* use EIAM to auto-mask when MSI-X interrupt
5214          * is asserted, this saves a register write for every interrupt
5215          */
5216         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5217                 misc_shift;
5218         regval = E1000_READ_REG(hw, E1000_EIAM);
5219         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5220
5221         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5222                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5223                 intr_handle->intr_vec[queue_id] = vec;
5224                 if (vec < base + intr_handle->nb_efd - 1)
5225                         vec++;
5226         }
5227
5228         E1000_WRITE_FLUSH(hw);
5229 }
5230
5231 DRIVER_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5232 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5233 DRIVER_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5234 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);