drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_string_fns.h>
  12 #include <rte_common.h>
  13 #include <rte_interrupts.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_log.h>
  16 #include <rte_debug.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memory.h>
  23 #include <rte_eal.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 /* Bit shift and mask */
  46 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  47 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  48 #define IGB_8_BIT_WIDTH  CHAR_BIT
  49 #define IGB_8_BIT_MASK   UINT8_MAX
  50
  51 /* Additional timesync values. */
  52 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  53 #define E1000_ETQF_FILTER_1588       3
  54 #define IGB_82576_TSYNC_SHIFT        16
  55 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  56 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  57 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  58
  59 #define E1000_VTIVAR_MISC                0x01740
  60 #define E1000_VTIVAR_MISC_MASK           0xFF
  61 #define E1000_VTIVAR_VALID               0x80
  62 #define E1000_VTIVAR_MISC_MAILBOX        0
  63 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  64
  65 /* External VLAN Enable bit mask */
  66 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  67
  68 /* External VLAN Ether Type bit mask and shift */
  69 #define E1000_VET_VET_EXT            0xFFFF0000
  70 #define E1000_VET_VET_EXT_SHIFT      16
  71
  72 /* MSI-X other interrupt vector */
  73 #define IGB_MSIX_OTHER_INTR_VEC      0
  74
  75 static int  eth_igb_configure(struct rte_eth_dev *dev);
  76 static int  eth_igb_start(struct rte_eth_dev *dev);
  77 static void eth_igb_stop(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  79 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  80 static void eth_igb_close(struct rte_eth_dev *dev);
  81 static int eth_igb_reset(struct rte_eth_dev *dev);
  82 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  87                                 int wait_to_complete);
  88 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  89                                 struct rte_eth_stats *rte_stats);
  90 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  91                               struct rte_eth_xstat *xstats, unsigned n);
  92 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  93                 const uint64_t *ids,
  94                 uint64_t *values, unsigned int n);
  95 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  96                                     struct rte_eth_xstat_name *xstats_names,
  97                                     unsigned int size);
  98 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  99                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 100                 unsigned int limit);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 104                                    char *fw_version, size_t fw_size);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 108 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_dev_info *dev_info);
 110 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 113                                 struct rte_eth_fc_conf *fc_conf);
 114 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 115 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 117 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 118                                     struct rte_intr_handle *handle);
 119 static void eth_igb_interrupt_handler(void *param);
 120 static int  igb_hardware_init(struct e1000_hw *hw);
 121 static void igb_hw_control_acquire(struct e1000_hw *hw);
 122 static void igb_hw_control_release(struct e1000_hw *hw);
 123 static void igb_init_manageability(struct e1000_hw *hw);
 124 static void igb_release_manageability(struct e1000_hw *hw);
 125
 126 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 127
 128 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 129                 uint16_t vlan_id, int on);
 130 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 131                                  enum rte_vlan_type vlan_type,
 132                                  uint16_t tpid_id);
 133 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134
 135 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 140 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 141
 142 static int eth_igb_led_on(struct rte_eth_dev *dev);
 143 static int eth_igb_led_off(struct rte_eth_dev *dev);
 144
 145 static void igb_intr_disable(struct rte_eth_dev *dev);
 146 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 147 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 148                            struct rte_ether_addr *mac_addr,
 149                            uint32_t index, uint32_t pool);
 150 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 151 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 152                 struct rte_ether_addr *addr);
 153
 154 static void igbvf_intr_disable(struct e1000_hw *hw);
 155 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 156 static int igbvf_dev_start(struct rte_eth_dev *dev);
 157 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 158 static void igbvf_dev_close(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 160 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 162 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int eth_igbvf_link_update(struct e1000_hw *hw);
 164 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_stats *rte_stats);
 166 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 167                                 struct rte_eth_xstat *xstats, unsigned n);
 168 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 169                                       struct rte_eth_xstat_name *xstats_names,
 170                                       unsigned limit);
 171 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 172 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 173                 uint16_t vlan_id, int on);
 174 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 175 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 176 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 177                 struct rte_ether_addr *addr);
 178 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 179 static int igbvf_get_regs(struct rte_eth_dev *dev,
 180                 struct rte_dev_reg_info *regs);
 181
 182 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 183                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                    uint16_t reta_size);
 185 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 186                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                   uint16_t reta_size);
 188
 189 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 190                         struct rte_eth_syn_filter *filter);
 191 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_flex_filter *filter);
 200 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 201                         enum rte_filter_op filter_op,
 202                         void *arg);
 203 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *filter);
 209 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 230                                    struct rte_eth_dev_module_info *modinfo);
 231 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 232                                      struct rte_dev_eeprom_info *info);
 233 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 234                                     struct rte_ether_addr *mc_addr_set,
 235                                     uint32_t nb_mc_addr);
 236 static int igb_timesync_enable(struct rte_eth_dev *dev);
 237 static int igb_timesync_disable(struct rte_eth_dev *dev);
 238 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp,
 240                                           uint32_t flags);
 241 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp);
 243 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 244 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 245                                   struct timespec *timestamp);
 246 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 247                                    const struct timespec *timestamp);
 248 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                         uint16_t queue_id);
 250 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                          uint16_t queue_id);
 252 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 253                                        uint8_t queue, uint8_t msix_vector);
 254 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 255                                uint8_t index, uint8_t offset);
 256 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 257 static void eth_igbvf_interrupt_handler(void *param);
 258 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 259 static int igb_filter_restore(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 291
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 302
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 324         { .vendor_id = 0, /* sentinel */ },
 325 };
 326
 327 /*
 328  * The set of PCI devices this driver supports (for 82576&I350 VF)
 329  */
 330 static const struct rte_pci_id pci_id_igbvf_map[] = {
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 335         { .vendor_id = 0, /* sentinel */ },
 336 };
 337
 338 static const struct rte_eth_desc_lim rx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342 };
 343
 344 static const struct rte_eth_desc_lim tx_desc_lim = {
 345         .nb_max = E1000_MAX_RING_DESC,
 346         .nb_min = E1000_MIN_RING_DESC,
 347         .nb_align = IGB_RXD_ALIGN,
 348         .nb_seg_max = IGB_TX_MAX_SEG,
 349         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 350 };
 351
 352 static const struct eth_dev_ops eth_igb_ops = {
 353         .dev_configure        = eth_igb_configure,
 354         .dev_start            = eth_igb_start,
 355         .dev_stop             = eth_igb_stop,
 356         .dev_set_link_up      = eth_igb_dev_set_link_up,
 357         .dev_set_link_down    = eth_igb_dev_set_link_down,
 358         .dev_close            = eth_igb_close,
 359         .dev_reset            = eth_igb_reset,
 360         .promiscuous_enable   = eth_igb_promiscuous_enable,
 361         .promiscuous_disable  = eth_igb_promiscuous_disable,
 362         .allmulticast_enable  = eth_igb_allmulticast_enable,
 363         .allmulticast_disable = eth_igb_allmulticast_disable,
 364         .link_update          = eth_igb_link_update,
 365         .stats_get            = eth_igb_stats_get,
 366         .xstats_get           = eth_igb_xstats_get,
 367         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 368         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 369         .xstats_get_names     = eth_igb_xstats_get_names,
 370         .stats_reset          = eth_igb_stats_reset,
 371         .xstats_reset         = eth_igb_xstats_reset,
 372         .fw_version_get       = eth_igb_fw_version_get,
 373         .dev_infos_get        = eth_igb_infos_get,
 374         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 375         .mtu_set              = eth_igb_mtu_set,
 376         .vlan_filter_set      = eth_igb_vlan_filter_set,
 377         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 378         .vlan_offload_set     = eth_igb_vlan_offload_set,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 381         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 382         .rx_queue_release     = eth_igb_rx_queue_release,
 383         .rx_queue_count       = eth_igb_rx_queue_count,
 384         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 385         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 386         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 387         .tx_queue_setup       = eth_igb_tx_queue_setup,
 388         .tx_queue_release     = eth_igb_tx_queue_release,
 389         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 390         .dev_led_on           = eth_igb_led_on,
 391         .dev_led_off          = eth_igb_led_off,
 392         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 393         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 394         .mac_addr_add         = eth_igb_rar_set,
 395         .mac_addr_remove      = eth_igb_rar_clear,
 396         .mac_addr_set         = eth_igb_default_mac_addr_set,
 397         .reta_update          = eth_igb_rss_reta_update,
 398         .reta_query           = eth_igb_rss_reta_query,
 399         .rss_hash_update      = eth_igb_rss_hash_update,
 400         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 401         .filter_ctrl          = eth_igb_filter_ctrl,
 402         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 403         .rxq_info_get         = igb_rxq_info_get,
 404         .txq_info_get         = igb_txq_info_get,
 405         .timesync_enable      = igb_timesync_enable,
 406         .timesync_disable     = igb_timesync_disable,
 407         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 409         .get_reg              = eth_igb_get_regs,
 410         .get_eeprom_length    = eth_igb_get_eeprom_length,
 411         .get_eeprom           = eth_igb_get_eeprom,
 412         .set_eeprom           = eth_igb_set_eeprom,
 413         .get_module_info      = eth_igb_get_module_info,
 414         .get_module_eeprom    = eth_igb_get_module_eeprom,
 415         .timesync_adjust_time = igb_timesync_adjust_time,
 416         .timesync_read_time   = igb_timesync_read_time,
 417         .timesync_write_time  = igb_timesync_write_time,
 418 };
 419
 420 /*
 421  * dev_ops for virtual function, bare necessities for basic vf
 422  * operation have been implemented
 423  */
 424 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 425         .dev_configure        = igbvf_dev_configure,
 426         .dev_start            = igbvf_dev_start,
 427         .dev_stop             = igbvf_dev_stop,
 428         .dev_close            = igbvf_dev_close,
 429         .promiscuous_enable   = igbvf_promiscuous_enable,
 430         .promiscuous_disable  = igbvf_promiscuous_disable,
 431         .allmulticast_enable  = igbvf_allmulticast_enable,
 432         .allmulticast_disable = igbvf_allmulticast_disable,
 433         .link_update          = eth_igb_link_update,
 434         .stats_get            = eth_igbvf_stats_get,
 435         .xstats_get           = eth_igbvf_xstats_get,
 436         .xstats_get_names     = eth_igbvf_xstats_get_names,
 437         .stats_reset          = eth_igbvf_stats_reset,
 438         .xstats_reset         = eth_igbvf_stats_reset,
 439         .vlan_filter_set      = igbvf_vlan_filter_set,
 440         .dev_infos_get        = eth_igbvf_infos_get,
 441         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 442         .rx_queue_setup       = eth_igb_rx_queue_setup,
 443         .rx_queue_release     = eth_igb_rx_queue_release,
 444         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 445         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 446         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 447         .tx_queue_setup       = eth_igb_tx_queue_setup,
 448         .tx_queue_release     = eth_igb_tx_queue_release,
 449         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 450         .rxq_info_get         = igb_rxq_info_get,
 451         .txq_info_get         = igb_txq_info_get,
 452         .mac_addr_set         = igbvf_default_mac_addr_set,
 453         .get_reg              = igbvf_get_regs,
 454 };
 455
 456 /* store statistics names and its offset in stats structure */
 457 struct rte_igb_xstats_name_off {
 458         char name[RTE_ETH_XSTATS_NAME_SIZE];
 459         unsigned offset;
 460 };
 461
 462 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 463         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 464         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 465         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 466         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 467         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 468         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 469         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 470                 ecol)},
 471         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 472         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 473         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 474         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 475         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 476         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 477         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 478         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 479         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 480         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 481         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 482                 fcruc)},
 483         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 484         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 485         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 486         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 487         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 488                 prc1023)},
 489         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 490                 prc1522)},
 491         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 492         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 493         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 494         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 495         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 496         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 497         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 498         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 499         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 500         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 501         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 502         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 503         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 504         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 505         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 506         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 507         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 508         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 509                 ptc1023)},
 510         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 511                 ptc1522)},
 512         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 513         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 514         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 515         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 516         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 517         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 518         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 519
 520         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 521 };
 522
 523 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 524                 sizeof(rte_igb_stats_strings[0]))
 525
 526 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 527         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 528         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 529         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 530         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 531         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 532 };
 533
 534 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 535                 sizeof(rte_igbvf_stats_strings[0]))
 536
 537
 538 static inline void
 539 igb_intr_enable(struct rte_eth_dev *dev)
 540 {
 541         struct e1000_interrupt *intr =
 542                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 543         struct e1000_hw *hw =
 544                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 547
 548         if (rte_intr_allow_others(intr_handle) &&
 549                 dev->data->dev_conf.intr_conf.lsc != 0) {
 550                 E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC);
 551         }
 552
 553         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 static void
 558 igb_intr_disable(struct rte_eth_dev *dev)
 559 {
 560         struct e1000_hw *hw =
 561                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 564
 565         if (rte_intr_allow_others(intr_handle) &&
 566                 dev->data->dev_conf.intr_conf.lsc != 0) {
 567                 E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC);
 568         }
 569
 570         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static inline void
 575 igbvf_intr_enable(struct rte_eth_dev *dev)
 576 {
 577         struct e1000_hw *hw =
 578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         /* only for mailbox */
 581         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 582         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 583         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 584         E1000_WRITE_FLUSH(hw);
 585 }
 586
 587 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 588 static void
 589 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 590 {
 591         uint32_t tmp = 0;
 592
 593         /* mailbox */
 594         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 595         tmp |= E1000_VTIVAR_VALID;
 596         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 597 }
 598
 599 static void
 600 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_hw *hw =
 603                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         /* Configure VF other cause ivar */
 606         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 607 }
 608
 609 static inline int32_t
 610 igb_pf_reset_hw(struct e1000_hw *hw)
 611 {
 612         uint32_t ctrl_ext;
 613         int32_t status;
 614
 615         status = e1000_reset_hw(hw);
 616
 617         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 618         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 619         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 620         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 621         E1000_WRITE_FLUSH(hw);
 622
 623         return status;
 624 }
 625
 626 static void
 627 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632
 633         hw->vendor_id = pci_dev->id.vendor_id;
 634         hw->device_id = pci_dev->id.device_id;
 635         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 636         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 637
 638         e1000_set_mac_type(hw);
 639
 640         /* need to check if it is a vf device below */
 641 }
 642
 643 static int
 644 igb_reset_swfw_lock(struct e1000_hw *hw)
 645 {
 646         int ret_val;
 647
 648         /*
 649          * Do mac ops initialization manually here, since we will need
 650          * some function pointers set by this call.
 651          */
 652         ret_val = e1000_init_mac_params(hw);
 653         if (ret_val)
 654                 return ret_val;
 655
 656         /*
 657          * SMBI lock should not fail in this early stage. If this is the case,
 658          * it is due to an improper exit of the application.
 659          * So force the release of the faulty lock.
 660          */
 661         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 662                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 663         }
 664         e1000_put_hw_semaphore_generic(hw);
 665
 666         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 667                 uint16_t mask;
 668
 669                 /*
 670                  * Phy lock should not fail in this early stage. If this is the case,
 671                  * it is due to an improper exit of the application.
 672                  * So force the release of the faulty lock.
 673                  */
 674                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 675                 if (hw->bus.func > E1000_FUNC_1)
 676                         mask <<= 2;
 677                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 678                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 679                                     hw->bus.func);
 680                 }
 681                 hw->mac.ops.release_swfw_sync(hw, mask);
 682
 683                 /*
 684                  * This one is more tricky since it is common to all ports; but
 685                  * swfw_sync retries last long enough (1s) to be almost sure that if
 686                  * lock can not be taken it is due to an improper lock of the
 687                  * semaphore.
 688                  */
 689                 mask = E1000_SWFW_EEP_SM;
 690                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 691                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 692                 }
 693                 hw->mac.ops.release_swfw_sync(hw, mask);
 694         }
 695
 696         return E1000_SUCCESS;
 697 }
 698
 699 /* Remove all ntuple filters of the device */
 700 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 701 {
 702         struct e1000_filter_info *filter_info =
 703                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 704         struct e1000_5tuple_filter *p_5tuple;
 705         struct e1000_2tuple_filter *p_2tuple;
 706
 707         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 708                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 709                         p_5tuple, entries);
 710                         rte_free(p_5tuple);
 711         }
 712         filter_info->fivetuple_mask = 0;
 713         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 714                 TAILQ_REMOVE(&filter_info->twotuple_list,
 715                         p_2tuple, entries);
 716                         rte_free(p_2tuple);
 717         }
 718         filter_info->twotuple_mask = 0;
 719
 720         return 0;
 721 }
 722
 723 /* Remove all flex filters of the device */
 724 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 725 {
 726         struct e1000_filter_info *filter_info =
 727                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 728         struct e1000_flex_filter *p_flex;
 729
 730         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 731                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 732                 rte_free(p_flex);
 733         }
 734         filter_info->flex_mask = 0;
 735
 736         return 0;
 737 }
 738
 739 static int
 740 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 741 {
 742         int error = 0;
 743         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 744         struct e1000_hw *hw =
 745                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 746         struct e1000_vfta * shadow_vfta =
 747                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_adapter *adapter =
 751                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 752
 753         uint32_t ctrl_ext;
 754
 755         eth_dev->dev_ops = &eth_igb_ops;
 756         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 757         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 758         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 759
 760         /* for secondary processes, we don't initialise any further as primary
 761          * has already done this work. Only check we don't need a different
 762          * RX function */
 763         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 764                 if (eth_dev->data->scattered_rx)
 765                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 766                 return 0;
 767         }
 768
 769         rte_eth_copy_pci_info(eth_dev, pci_dev);
 770
 771         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 772
 773         igb_identify_hardware(eth_dev, pci_dev);
 774         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 775                 error = -EIO;
 776                 goto err_late;
 777         }
 778
 779         e1000_get_bus_info(hw);
 780
 781         /* Reset any pending lock */
 782         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 783                 error = -EIO;
 784                 goto err_late;
 785         }
 786
 787         /* Finish initialization */
 788         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 789                 error = -EIO;
 790                 goto err_late;
 791         }
 792
 793         hw->mac.autoneg = 1;
 794         hw->phy.autoneg_wait_to_complete = 0;
 795         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 796
 797         /* Copper options */
 798         if (hw->phy.media_type == e1000_media_type_copper) {
 799                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 800                 hw->phy.disable_polarity_correction = 0;
 801                 hw->phy.ms_type = e1000_ms_hw_default;
 802         }
 803
 804         /*
 805          * Start from a known state, this is important in reading the nvm
 806          * and mac from that.
 807          */
 808         igb_pf_reset_hw(hw);
 809
 810         /* Make sure we have a good EEPROM before we read from it */
 811         if (e1000_validate_nvm_checksum(hw) < 0) {
 812                 /*
 813                  * Some PCI-E parts fail the first check due to
 814                  * the link being in sleep state, call it again,
 815                  * if it fails a second time its a real issue.
 816                  */
 817                 if (e1000_validate_nvm_checksum(hw) < 0) {
 818                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 819                         error = -EIO;
 820                         goto err_late;
 821                 }
 822         }
 823
 824         /* Read the permanent MAC address out of the EEPROM */
 825         if (e1000_read_mac_addr(hw) != 0) {
 826                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 827                 error = -EIO;
 828                 goto err_late;
 829         }
 830
 831         /* Allocate memory for storing MAC addresses */
 832         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 833                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 834         if (eth_dev->data->mac_addrs == NULL) {
 835                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 836                                                 "store MAC addresses",
 837                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 838                 error = -ENOMEM;
 839                 goto err_late;
 840         }
 841
 842         /* Copy the permanent MAC address */
 843         ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 844                         &eth_dev->data->mac_addrs[0]);
 845
 846         /* initialize the vfta */
 847         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 848
 849         /* Now initialize the hardware */
 850         if (igb_hardware_init(hw) != 0) {
 851                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 852                 rte_free(eth_dev->data->mac_addrs);
 853                 eth_dev->data->mac_addrs = NULL;
 854                 error = -ENODEV;
 855                 goto err_late;
 856         }
 857         hw->mac.get_link_status = 1;
 858         adapter->stopped = 0;
 859
 860         /* Indicate SOL/IDER usage */
 861         if (e1000_check_reset_block(hw) < 0) {
 862                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 863                                         "SOL/IDER session");
 864         }
 865
 866         /* initialize PF if max_vfs not zero */
 867         igb_pf_host_init(eth_dev);
 868
 869         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 870         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 871         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 872         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 873         E1000_WRITE_FLUSH(hw);
 874
 875         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 876                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 877                      pci_dev->id.device_id);
 878
 879         rte_intr_callback_register(&pci_dev->intr_handle,
 880                                    eth_igb_interrupt_handler,
 881                                    (void *)eth_dev);
 882
 883         /* enable uio/vfio intr/eventfd mapping */
 884         rte_intr_enable(&pci_dev->intr_handle);
 885
 886         /* enable support intr */
 887         igb_intr_enable(eth_dev);
 888
 889         /* initialize filter info */
 890         memset(filter_info, 0,
 891                sizeof(struct e1000_filter_info));
 892
 893         TAILQ_INIT(&filter_info->flex_list);
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         TAILQ_INIT(&filter_info->fivetuple_list);
 896
 897         TAILQ_INIT(&igb_filter_ntuple_list);
 898         TAILQ_INIT(&igb_filter_ethertype_list);
 899         TAILQ_INIT(&igb_filter_syn_list);
 900         TAILQ_INIT(&igb_filter_flex_list);
 901         TAILQ_INIT(&igb_filter_rss_list);
 902         TAILQ_INIT(&igb_flow_list);
 903
 904         return 0;
 905
 906 err_late:
 907         igb_hw_control_release(hw);
 908
 909         return error;
 910 }
 911
 912 static int
 913 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 914 {
 915         struct rte_pci_device *pci_dev;
 916         struct rte_intr_handle *intr_handle;
 917         struct e1000_hw *hw;
 918         struct e1000_adapter *adapter =
 919                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 920         struct e1000_filter_info *filter_info =
 921                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 922
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 926                 return -EPERM;
 927
 928         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 929         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 930         intr_handle = &pci_dev->intr_handle;
 931
 932         if (adapter->stopped == 0)
 933                 eth_igb_close(eth_dev);
 934
 935         eth_dev->dev_ops = NULL;
 936         eth_dev->rx_pkt_burst = NULL;
 937         eth_dev->tx_pkt_burst = NULL;
 938
 939         /* Reset any pending lock */
 940         igb_reset_swfw_lock(hw);
 941
 942         /* uninitialize PF if max_vfs not zero */
 943         igb_pf_host_uninit(eth_dev);
 944
 945         /* disable uio intr before callback unregister */
 946         rte_intr_disable(intr_handle);
 947         rte_intr_callback_unregister(intr_handle,
 948                                      eth_igb_interrupt_handler, eth_dev);
 949
 950         /* clear the SYN filter info */
 951         filter_info->syn_info = 0;
 952
 953         /* clear the ethertype filters info */
 954         filter_info->ethertype_mask = 0;
 955         memset(filter_info->ethertype_filters, 0,
 956                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 957
 958         /* clear the rss filter info */
 959         memset(&filter_info->rss_info, 0,
 960                 sizeof(struct igb_rte_flow_rss_conf));
 961
 962         /* remove all ntuple filters of the device */
 963         igb_ntuple_filter_uninit(eth_dev);
 964
 965         /* remove all flex filters of the device */
 966         igb_flex_filter_uninit(eth_dev);
 967
 968         /* clear all the filters list */
 969         igb_filterlist_flush(eth_dev);
 970
 971         return 0;
 972 }
 973
 974 /*
 975  * Virtual Function device init
 976  */
 977 static int
 978 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 979 {
 980         struct rte_pci_device *pci_dev;
 981         struct rte_intr_handle *intr_handle;
 982         struct e1000_adapter *adapter =
 983                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 984         struct e1000_hw *hw =
 985                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 986         int diag;
 987         struct rte_ether_addr *perm_addr =
 988                 (struct rte_ether_addr *)hw->mac.perm_addr;
 989
 990         PMD_INIT_FUNC_TRACE();
 991
 992         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 993         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 994         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 995         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 996
 997         /* for secondary processes, we don't initialise any further as primary
 998          * has already done this work. Only check we don't need a different
 999          * RX function */
1000         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1001                 if (eth_dev->data->scattered_rx)
1002                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1003                 return 0;
1004         }
1005
1006         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1007         rte_eth_copy_pci_info(eth_dev, pci_dev);
1008
1009         hw->device_id = pci_dev->id.device_id;
1010         hw->vendor_id = pci_dev->id.vendor_id;
1011         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1012         adapter->stopped = 0;
1013
1014         /* Initialize the shared code (base driver) */
1015         diag = e1000_setup_init_funcs(hw, TRUE);
1016         if (diag != 0) {
1017                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1018                         diag);
1019                 return -EIO;
1020         }
1021
1022         /* init_mailbox_params */
1023         hw->mbx.ops.init_params(hw);
1024
1025         /* Disable the interrupts for VF */
1026         igbvf_intr_disable(hw);
1027
1028         diag = hw->mac.ops.reset_hw(hw);
1029
1030         /* Allocate memory for storing MAC addresses */
1031         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1032                 hw->mac.rar_entry_count, 0);
1033         if (eth_dev->data->mac_addrs == NULL) {
1034                 PMD_INIT_LOG(ERR,
1035                         "Failed to allocate %d bytes needed to store MAC "
1036                         "addresses",
1037                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1038                 return -ENOMEM;
1039         }
1040
1041         /* Generate a random MAC address, if none was assigned by PF. */
1042         if (is_zero_ether_addr(perm_addr)) {
1043                 eth_random_addr(perm_addr->addr_bytes);
1044                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1045                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1046                              "%02x:%02x:%02x:%02x:%02x:%02x",
1047                              perm_addr->addr_bytes[0],
1048                              perm_addr->addr_bytes[1],
1049                              perm_addr->addr_bytes[2],
1050                              perm_addr->addr_bytes[3],
1051                              perm_addr->addr_bytes[4],
1052                              perm_addr->addr_bytes[5]);
1053         }
1054
1055         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1056         if (diag) {
1057                 rte_free(eth_dev->data->mac_addrs);
1058                 eth_dev->data->mac_addrs = NULL;
1059                 return diag;
1060         }
1061         /* Copy the permanent MAC address */
1062         ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1063                         &eth_dev->data->mac_addrs[0]);
1064
1065         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1066                      "mac.type=%s",
1067                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1068                      pci_dev->id.device_id, "igb_mac_82576_vf");
1069
1070         intr_handle = &pci_dev->intr_handle;
1071         rte_intr_callback_register(intr_handle,
1072                                    eth_igbvf_interrupt_handler, eth_dev);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1079 {
1080         struct e1000_adapter *adapter =
1081                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1083
1084         PMD_INIT_FUNC_TRACE();
1085
1086         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1087                 return -EPERM;
1088
1089         if (adapter->stopped == 0)
1090                 igbvf_dev_close(eth_dev);
1091
1092         eth_dev->dev_ops = NULL;
1093         eth_dev->rx_pkt_burst = NULL;
1094         eth_dev->tx_pkt_burst = NULL;
1095
1096         /* disable uio intr before callback unregister */
1097         rte_intr_disable(&pci_dev->intr_handle);
1098         rte_intr_callback_unregister(&pci_dev->intr_handle,
1099                                      eth_igbvf_interrupt_handler,
1100                                      (void *)eth_dev);
1101
1102         return 0;
1103 }
1104
1105 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1106         struct rte_pci_device *pci_dev)
1107 {
1108         return rte_eth_dev_pci_generic_probe(pci_dev,
1109                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1110 }
1111
1112 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1113 {
1114         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1115 }
1116
1117 static struct rte_pci_driver rte_igb_pmd = {
1118         .id_table = pci_id_igb_map,
1119         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1120                      RTE_PCI_DRV_IOVA_AS_VA,
1121         .probe = eth_igb_pci_probe,
1122         .remove = eth_igb_pci_remove,
1123 };
1124
1125
1126 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1127         struct rte_pci_device *pci_dev)
1128 {
1129         return rte_eth_dev_pci_generic_probe(pci_dev,
1130                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1131 }
1132
1133 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1134 {
1135         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1136 }
1137
1138 /*
1139  * virtual function driver struct
1140  */
1141 static struct rte_pci_driver rte_igbvf_pmd = {
1142         .id_table = pci_id_igbvf_map,
1143         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1144         .probe = eth_igbvf_pci_probe,
1145         .remove = eth_igbvf_pci_remove,
1146 };
1147
1148 static void
1149 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1150 {
1151         struct e1000_hw *hw =
1152                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1153         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1154         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1155         rctl |= E1000_RCTL_VFE;
1156         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1157 }
1158
1159 static int
1160 igb_check_mq_mode(struct rte_eth_dev *dev)
1161 {
1162         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1163         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1164         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1165         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1166
1167         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1168             tx_mq_mode == ETH_MQ_TX_DCB ||
1169             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1170                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1171                 return -EINVAL;
1172         }
1173         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1174                 /* Check multi-queue mode.
1175                  * To no break software we accept ETH_MQ_RX_NONE as this might
1176                  * be used to turn off VLAN filter.
1177                  */
1178
1179                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1180                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1181                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1182                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1183                 } else {
1184                         /* Only support one queue on VFs.
1185                          * RSS together with SRIOV is not supported.
1186                          */
1187                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1188                                         " wrong mq_mode rx %d.",
1189                                         rx_mq_mode);
1190                         return -EINVAL;
1191                 }
1192                 /* TX mode is not used here, so mode might be ignored.*/
1193                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1194                         /* SRIOV only works in VMDq enable mode */
1195                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1196                                         " TX mode %d is not supported. "
1197                                         " Driver will behave as %d mode.",
1198                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1199                 }
1200
1201                 /* check valid queue number */
1202                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1203                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1204                                         " only support one queue on VFs.");
1205                         return -EINVAL;
1206                 }
1207         } else {
1208                 /* To no break software that set invalid mode, only display
1209                  * warning if invalid mode is used.
1210                  */
1211                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1212                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1213                     rx_mq_mode != ETH_MQ_RX_RSS) {
1214                         /* RSS together with VMDq not supported*/
1215                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1216                                      rx_mq_mode);
1217                         return -EINVAL;
1218                 }
1219
1220                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1221                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1222                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1223                                         " Due to txmode is meaningless in this"
1224                                         " driver, just ignore.",
1225                                         tx_mq_mode);
1226                 }
1227         }
1228         return 0;
1229 }
1230
1231 static int
1232 eth_igb_configure(struct rte_eth_dev *dev)
1233 {
1234         struct e1000_interrupt *intr =
1235                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1236         int ret;
1237
1238         PMD_INIT_FUNC_TRACE();
1239
1240         /* multipe queue mode checking */
1241         ret  = igb_check_mq_mode(dev);
1242         if (ret != 0) {
1243                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1244                             ret);
1245                 return ret;
1246         }
1247
1248         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1249         PMD_INIT_FUNC_TRACE();
1250
1251         return 0;
1252 }
1253
1254 static void
1255 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1256                      bool enable)
1257 {
1258         struct e1000_hw *hw =
1259                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1260         uint32_t tctl, rctl;
1261
1262         tctl = E1000_READ_REG(hw, E1000_TCTL);
1263         rctl = E1000_READ_REG(hw, E1000_RCTL);
1264
1265         if (enable) {
1266                 /* enable Tx/Rx */
1267                 tctl |= E1000_TCTL_EN;
1268                 rctl |= E1000_RCTL_EN;
1269         } else {
1270                 /* disable Tx/Rx */
1271                 tctl &= ~E1000_TCTL_EN;
1272                 rctl &= ~E1000_RCTL_EN;
1273         }
1274         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1275         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1276         E1000_WRITE_FLUSH(hw);
1277 }
1278
1279 static int
1280 eth_igb_start(struct rte_eth_dev *dev)
1281 {
1282         struct e1000_hw *hw =
1283                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284         struct e1000_adapter *adapter =
1285                 E1000_DEV_PRIVATE(dev->data->dev_private);
1286         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1287         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288         int ret, mask;
1289         uint32_t intr_vector = 0;
1290         uint32_t ctrl_ext;
1291         uint32_t *speeds;
1292         int num_speeds;
1293         bool autoneg;
1294
1295         PMD_INIT_FUNC_TRACE();
1296
1297         /* disable uio/vfio intr/eventfd mapping */
1298         rte_intr_disable(intr_handle);
1299
1300         /* Power up the phy. Needed to make the link go Up */
1301         eth_igb_dev_set_link_up(dev);
1302
1303         /*
1304          * Packet Buffer Allocation (PBA)
1305          * Writing PBA sets the receive portion of the buffer
1306          * the remainder is used for the transmit buffer.
1307          */
1308         if (hw->mac.type == e1000_82575) {
1309                 uint32_t pba;
1310
1311                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1312                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1313         }
1314
1315         /* Put the address into the Receive Address Array */
1316         e1000_rar_set(hw, hw->mac.addr, 0);
1317
1318         /* Initialize the hardware */
1319         if (igb_hardware_init(hw)) {
1320                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1321                 return -EIO;
1322         }
1323         adapter->stopped = 0;
1324
1325         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1326
1327         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1329         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1330         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1331         E1000_WRITE_FLUSH(hw);
1332
1333         /* configure PF module if SRIOV enabled */
1334         igb_pf_host_configure(dev);
1335
1336         /* check and configure queue intr-vector mapping */
1337         if ((rte_intr_cap_multiple(intr_handle) ||
1338              !RTE_ETH_DEV_SRIOV(dev).active) &&
1339             dev->data->dev_conf.intr_conf.rxq != 0) {
1340                 intr_vector = dev->data->nb_rx_queues;
1341                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1342                         return -1;
1343         }
1344
1345         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1346                 intr_handle->intr_vec =
1347                         rte_zmalloc("intr_vec",
1348                                     dev->data->nb_rx_queues * sizeof(int), 0);
1349                 if (intr_handle->intr_vec == NULL) {
1350                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1351                                      " intr_vec", dev->data->nb_rx_queues);
1352                         return -ENOMEM;
1353                 }
1354         }
1355
1356         /* confiugre msix for rx interrupt */
1357         eth_igb_configure_msix_intr(dev);
1358
1359         /* Configure for OS presence */
1360         igb_init_manageability(hw);
1361
1362         eth_igb_tx_init(dev);
1363
1364         /* This can fail when allocating mbufs for descriptor rings */
1365         ret = eth_igb_rx_init(dev);
1366         if (ret) {
1367                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1368                 igb_dev_clear_queues(dev);
1369                 return ret;
1370         }
1371
1372         e1000_clear_hw_cntrs_base_generic(hw);
1373
1374         /*
1375          * VLAN Offload Settings
1376          */
1377         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1378                         ETH_VLAN_EXTEND_MASK;
1379         ret = eth_igb_vlan_offload_set(dev, mask);
1380         if (ret) {
1381                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1382                 igb_dev_clear_queues(dev);
1383                 return ret;
1384         }
1385
1386         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1387                 /* Enable VLAN filter since VMDq always use VLAN filter */
1388                 igb_vmdq_vlan_hw_filter_enable(dev);
1389         }
1390
1391         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1392                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1393                 (hw->mac.type == e1000_i211)) {
1394                 /* Configure EITR with the maximum possible value (0xFFFF) */
1395                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1396         }
1397
1398         /* Setup link speed and duplex */
1399         speeds = &dev->data->dev_conf.link_speeds;
1400         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1401                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1402                 hw->mac.autoneg = 1;
1403         } else {
1404                 num_speeds = 0;
1405                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1406
1407                 /* Reset */
1408                 hw->phy.autoneg_advertised = 0;
1409
1410                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1411                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1412                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1413                         num_speeds = -1;
1414                         goto error_invalid_config;
1415                 }
1416                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1417                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1418                         num_speeds++;
1419                 }
1420                 if (*speeds & ETH_LINK_SPEED_10M) {
1421                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1422                         num_speeds++;
1423                 }
1424                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1425                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1426                         num_speeds++;
1427                 }
1428                 if (*speeds & ETH_LINK_SPEED_100M) {
1429                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1430                         num_speeds++;
1431                 }
1432                 if (*speeds & ETH_LINK_SPEED_1G) {
1433                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1434                         num_speeds++;
1435                 }
1436                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1437                         goto error_invalid_config;
1438
1439                 /* Set/reset the mac.autoneg based on the link speed,
1440                  * fixed or not
1441                  */
1442                 if (!autoneg) {
1443                         hw->mac.autoneg = 0;
1444                         hw->mac.forced_speed_duplex =
1445                                         hw->phy.autoneg_advertised;
1446                 } else {
1447                         hw->mac.autoneg = 1;
1448                 }
1449         }
1450
1451         e1000_setup_link(hw);
1452
1453         if (rte_intr_allow_others(intr_handle)) {
1454                 /* check if lsc interrupt is enabled */
1455                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1456                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1457                 else
1458                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1459         } else {
1460                 rte_intr_callback_unregister(intr_handle,
1461                                              eth_igb_interrupt_handler,
1462                                              (void *)dev);
1463                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1464                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1465                                      " no intr multiplex");
1466         }
1467
1468         /* check if rxq interrupt is enabled */
1469         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1470             rte_intr_dp_is_en(intr_handle))
1471                 eth_igb_rxq_interrupt_setup(dev);
1472
1473         /* enable uio/vfio intr/eventfd mapping */
1474         rte_intr_enable(intr_handle);
1475
1476         /* resume enabled intr since hw reset */
1477         igb_intr_enable(dev);
1478
1479         /* restore all types filter */
1480         igb_filter_restore(dev);
1481
1482         eth_igb_rxtx_control(dev, true);
1483         eth_igb_link_update(dev, 0);
1484
1485         PMD_INIT_LOG(DEBUG, "<<");
1486
1487         return 0;
1488
1489 error_invalid_config:
1490         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1491                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1492         igb_dev_clear_queues(dev);
1493         return -EINVAL;
1494 }
1495
1496 /*********************************************************************
1497  *
1498  *  This routine disables all traffic on the adapter by issuing a
1499  *  global reset on the MAC.
1500  *
1501  **********************************************************************/
1502 static void
1503 eth_igb_stop(struct rte_eth_dev *dev)
1504 {
1505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507         struct rte_eth_link link;
1508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1509
1510         eth_igb_rxtx_control(dev, false);
1511
1512         igb_intr_disable(dev);
1513
1514         /* disable intr eventfd mapping */
1515         rte_intr_disable(intr_handle);
1516
1517         igb_pf_reset_hw(hw);
1518         E1000_WRITE_REG(hw, E1000_WUC, 0);
1519
1520         /* Set bit for Go Link disconnect */
1521         if (hw->mac.type >= e1000_82580) {
1522                 uint32_t phpm_reg;
1523
1524                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1525                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1526                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1527         }
1528
1529         /* Power down the phy. Needed to make the link go Down */
1530         eth_igb_dev_set_link_down(dev);
1531
1532         igb_dev_clear_queues(dev);
1533
1534         /* clear the recorded link status */
1535         memset(&link, 0, sizeof(link));
1536         rte_eth_linkstatus_set(dev, &link);
1537
1538         if (!rte_intr_allow_others(intr_handle))
1539                 /* resume to the default handler */
1540                 rte_intr_callback_register(intr_handle,
1541                                            eth_igb_interrupt_handler,
1542                                            (void *)dev);
1543
1544         /* Clean datapath event and queue/vec mapping */
1545         rte_intr_efd_disable(intr_handle);
1546         if (intr_handle->intr_vec != NULL) {
1547                 rte_free(intr_handle->intr_vec);
1548                 intr_handle->intr_vec = NULL;
1549         }
1550 }
1551
1552 static int
1553 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556
1557         if (hw->phy.media_type == e1000_media_type_copper)
1558                 e1000_power_up_phy(hw);
1559         else
1560                 e1000_power_up_fiber_serdes_link(hw);
1561
1562         return 0;
1563 }
1564
1565 static int
1566 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1567 {
1568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1569
1570         if (hw->phy.media_type == e1000_media_type_copper)
1571                 e1000_power_down_phy(hw);
1572         else
1573                 e1000_shutdown_fiber_serdes_link(hw);
1574
1575         return 0;
1576 }
1577
1578 static void
1579 eth_igb_close(struct rte_eth_dev *dev)
1580 {
1581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1582         struct e1000_adapter *adapter =
1583                 E1000_DEV_PRIVATE(dev->data->dev_private);
1584         struct rte_eth_link link;
1585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1586         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1587
1588         eth_igb_stop(dev);
1589         adapter->stopped = 1;
1590
1591         e1000_phy_hw_reset(hw);
1592         igb_release_manageability(hw);
1593         igb_hw_control_release(hw);
1594
1595         /* Clear bit for Go Link disconnect */
1596         if (hw->mac.type >= e1000_82580) {
1597                 uint32_t phpm_reg;
1598
1599                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1600                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1601                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1602         }
1603
1604         igb_dev_free_queues(dev);
1605
1606         if (intr_handle->intr_vec) {
1607                 rte_free(intr_handle->intr_vec);
1608                 intr_handle->intr_vec = NULL;
1609         }
1610
1611         memset(&link, 0, sizeof(link));
1612         rte_eth_linkstatus_set(dev, &link);
1613 }
1614
1615 /*
1616  * Reset PF device.
1617  */
1618 static int
1619 eth_igb_reset(struct rte_eth_dev *dev)
1620 {
1621         int ret;
1622
1623         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1624          * its VF to make them align with it. The detailed notification
1625          * mechanism is PMD specific and is currently not implemented.
1626          * To avoid unexpected behavior in VF, currently reset of PF with
1627          * SR-IOV activation is not supported. It might be supported later.
1628          */
1629         if (dev->data->sriov.active)
1630                 return -ENOTSUP;
1631
1632         ret = eth_igb_dev_uninit(dev);
1633         if (ret)
1634                 return ret;
1635
1636         ret = eth_igb_dev_init(dev);
1637
1638         return ret;
1639 }
1640
1641
1642 static int
1643 igb_get_rx_buffer_size(struct e1000_hw *hw)
1644 {
1645         uint32_t rx_buf_size;
1646         if (hw->mac.type == e1000_82576) {
1647                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1648         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1649                 /* PBS needs to be translated according to a lookup table */
1650                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1651                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1652                 rx_buf_size = (rx_buf_size << 10);
1653         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1654                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1655         } else {
1656                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1657         }
1658
1659         return rx_buf_size;
1660 }
1661
1662 /*********************************************************************
1663  *
1664  *  Initialize the hardware
1665  *
1666  **********************************************************************/
1667 static int
1668 igb_hardware_init(struct e1000_hw *hw)
1669 {
1670         uint32_t rx_buf_size;
1671         int diag;
1672
1673         /* Let the firmware know the OS is in control */
1674         igb_hw_control_acquire(hw);
1675
1676         /*
1677          * These parameters control the automatic generation (Tx) and
1678          * response (Rx) to Ethernet PAUSE frames.
1679          * - High water mark should allow for at least two standard size (1518)
1680          *   frames to be received after sending an XOFF.
1681          * - Low water mark works best when it is very near the high water mark.
1682          *   This allows the receiver to restart by sending XON when it has
1683          *   drained a bit. Here we use an arbitrary value of 1500 which will
1684          *   restart after one full frame is pulled from the buffer. There
1685          *   could be several smaller frames in the buffer and if so they will
1686          *   not trigger the XON until their total number reduces the buffer
1687          *   by 1500.
1688          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1689          */
1690         rx_buf_size = igb_get_rx_buffer_size(hw);
1691
1692         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1693         hw->fc.low_water = hw->fc.high_water - 1500;
1694         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1695         hw->fc.send_xon = 1;
1696
1697         /* Set Flow control, use the tunable location if sane */
1698         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1699                 hw->fc.requested_mode = igb_fc_setting;
1700         else
1701                 hw->fc.requested_mode = e1000_fc_none;
1702
1703         /* Issue a global reset */
1704         igb_pf_reset_hw(hw);
1705         E1000_WRITE_REG(hw, E1000_WUC, 0);
1706
1707         diag = e1000_init_hw(hw);
1708         if (diag < 0)
1709                 return diag;
1710
1711         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1712         e1000_get_phy_info(hw);
1713         e1000_check_for_link(hw);
1714
1715         return 0;
1716 }
1717
1718 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1719 static void
1720 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1721 {
1722         int pause_frames;
1723
1724         uint64_t old_gprc  = stats->gprc;
1725         uint64_t old_gptc  = stats->gptc;
1726         uint64_t old_tpr   = stats->tpr;
1727         uint64_t old_tpt   = stats->tpt;
1728         uint64_t old_rpthc = stats->rpthc;
1729         uint64_t old_hgptc = stats->hgptc;
1730
1731         if(hw->phy.media_type == e1000_media_type_copper ||
1732             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1733                 stats->symerrs +=
1734                     E1000_READ_REG(hw,E1000_SYMERRS);
1735                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1736         }
1737
1738         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1739         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1740         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1741         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1742
1743         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1744         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1745         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1746         stats->dc += E1000_READ_REG(hw, E1000_DC);
1747         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1748         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1749         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1750         /*
1751         ** For watchdog management we need to know if we have been
1752         ** paused during the last interval, so capture that here.
1753         */
1754         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1755         stats->xoffrxc += pause_frames;
1756         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1757         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1758         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1759         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1760         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1761         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1762         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1763         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1764         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1765         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1766         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1767         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1768
1769         /* For the 64-bit byte counters the low dword must be read first. */
1770         /* Both registers clear on the read of the high dword */
1771
1772         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1773         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1774         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1775         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1776         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1777         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1778         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1779
1780         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1781         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1782         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1783         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1784         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1785
1786         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1787         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1788
1789         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1790         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1791         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1792         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1793         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1794         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1795
1796         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1797         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1798         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1799         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1800         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1801         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1802         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1803         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1804
1805         /* Interrupt Counts */
1806
1807         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1808         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1809         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1810         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1811         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1812         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1813         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1814         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1815         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1816
1817         /* Host to Card Statistics */
1818
1819         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1820         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1821         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1822         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1823         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1824         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1825         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1826         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1827         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1828         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1829         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1830         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1831         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1832         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1833         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1834         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1835
1836         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1837         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1838         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1839         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1840         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1841         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1842 }
1843
1844 static int
1845 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1846 {
1847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct e1000_hw_stats *stats =
1849                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1850
1851         igb_read_stats_registers(hw, stats);
1852
1853         if (rte_stats == NULL)
1854                 return -EINVAL;
1855
1856         /* Rx Errors */
1857         rte_stats->imissed = stats->mpc;
1858         rte_stats->ierrors = stats->crcerrs +
1859                              stats->rlec + stats->ruc + stats->roc +
1860                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1861
1862         /* Tx Errors */
1863         rte_stats->oerrors = stats->ecol + stats->latecol;
1864
1865         rte_stats->ipackets = stats->gprc;
1866         rte_stats->opackets = stats->gptc;
1867         rte_stats->ibytes   = stats->gorc;
1868         rte_stats->obytes   = stats->gotc;
1869         return 0;
1870 }
1871
1872 static void
1873 eth_igb_stats_reset(struct rte_eth_dev *dev)
1874 {
1875         struct e1000_hw_stats *hw_stats =
1876                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1877
1878         /* HW registers are cleared on read */
1879         eth_igb_stats_get(dev, NULL);
1880
1881         /* Reset software totals */
1882         memset(hw_stats, 0, sizeof(*hw_stats));
1883 }
1884
1885 static void
1886 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1887 {
1888         struct e1000_hw_stats *stats =
1889                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1890
1891         /* HW registers are cleared on read */
1892         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1893
1894         /* Reset software totals */
1895         memset(stats, 0, sizeof(*stats));
1896 }
1897
1898 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1899         struct rte_eth_xstat_name *xstats_names,
1900         __rte_unused unsigned int size)
1901 {
1902         unsigned i;
1903
1904         if (xstats_names == NULL)
1905                 return IGB_NB_XSTATS;
1906
1907         /* Note: limit checked in rte_eth_xstats_names() */
1908
1909         for (i = 0; i < IGB_NB_XSTATS; i++) {
1910                 strlcpy(xstats_names[i].name, rte_igb_stats_strings[i].name,
1911                         sizeof(xstats_names[i].name));
1912         }
1913
1914         return IGB_NB_XSTATS;
1915 }
1916
1917 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1918                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1919                 unsigned int limit)
1920 {
1921         unsigned int i;
1922
1923         if (!ids) {
1924                 if (xstats_names == NULL)
1925                         return IGB_NB_XSTATS;
1926
1927                 for (i = 0; i < IGB_NB_XSTATS; i++)
1928                         strlcpy(xstats_names[i].name,
1929                                 rte_igb_stats_strings[i].name,
1930                                 sizeof(xstats_names[i].name));
1931
1932                 return IGB_NB_XSTATS;
1933
1934         } else {
1935                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1936
1937                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1938                                 IGB_NB_XSTATS);
1939
1940                 for (i = 0; i < limit; i++) {
1941                         if (ids[i] >= IGB_NB_XSTATS) {
1942                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1943                                 return -1;
1944                         }
1945                         strcpy(xstats_names[i].name,
1946                                         xstats_names_copy[ids[i]].name);
1947                 }
1948                 return limit;
1949         }
1950 }
1951
1952 static int
1953 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1954                    unsigned n)
1955 {
1956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957         struct e1000_hw_stats *hw_stats =
1958                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1959         unsigned i;
1960
1961         if (n < IGB_NB_XSTATS)
1962                 return IGB_NB_XSTATS;
1963
1964         igb_read_stats_registers(hw, hw_stats);
1965
1966         /* If this is a reset xstats is NULL, and we have cleared the
1967          * registers by reading them.
1968          */
1969         if (!xstats)
1970                 return 0;
1971
1972         /* Extended stats */
1973         for (i = 0; i < IGB_NB_XSTATS; i++) {
1974                 xstats[i].id = i;
1975                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1976                         rte_igb_stats_strings[i].offset);
1977         }
1978
1979         return IGB_NB_XSTATS;
1980 }
1981
1982 static int
1983 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1984                 uint64_t *values, unsigned int n)
1985 {
1986         unsigned int i;
1987
1988         if (!ids) {
1989                 struct e1000_hw *hw =
1990                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991                 struct e1000_hw_stats *hw_stats =
1992                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1993
1994                 if (n < IGB_NB_XSTATS)
1995                         return IGB_NB_XSTATS;
1996
1997                 igb_read_stats_registers(hw, hw_stats);
1998
1999                 /* If this is a reset xstats is NULL, and we have cleared the
2000                  * registers by reading them.
2001                  */
2002                 if (!values)
2003                         return 0;
2004
2005                 /* Extended stats */
2006                 for (i = 0; i < IGB_NB_XSTATS; i++)
2007                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2008                                         rte_igb_stats_strings[i].offset);
2009
2010                 return IGB_NB_XSTATS;
2011
2012         } else {
2013                 uint64_t values_copy[IGB_NB_XSTATS];
2014
2015                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2016                                 IGB_NB_XSTATS);
2017
2018                 for (i = 0; i < n; i++) {
2019                         if (ids[i] >= IGB_NB_XSTATS) {
2020                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2021                                 return -1;
2022                         }
2023                         values[i] = values_copy[ids[i]];
2024                 }
2025                 return n;
2026         }
2027 }
2028
2029 static void
2030 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2031 {
2032         /* Good Rx packets, include VF loopback */
2033         UPDATE_VF_STAT(E1000_VFGPRC,
2034             hw_stats->last_gprc, hw_stats->gprc);
2035
2036         /* Good Rx octets, include VF loopback */
2037         UPDATE_VF_STAT(E1000_VFGORC,
2038             hw_stats->last_gorc, hw_stats->gorc);
2039
2040         /* Good Tx packets, include VF loopback */
2041         UPDATE_VF_STAT(E1000_VFGPTC,
2042             hw_stats->last_gptc, hw_stats->gptc);
2043
2044         /* Good Tx octets, include VF loopback */
2045         UPDATE_VF_STAT(E1000_VFGOTC,
2046             hw_stats->last_gotc, hw_stats->gotc);
2047
2048         /* Rx Multicst packets */
2049         UPDATE_VF_STAT(E1000_VFMPRC,
2050             hw_stats->last_mprc, hw_stats->mprc);
2051
2052         /* Good Rx loopback packets */
2053         UPDATE_VF_STAT(E1000_VFGPRLBC,
2054             hw_stats->last_gprlbc, hw_stats->gprlbc);
2055
2056         /* Good Rx loopback octets */
2057         UPDATE_VF_STAT(E1000_VFGORLBC,
2058             hw_stats->last_gorlbc, hw_stats->gorlbc);
2059
2060         /* Good Tx loopback packets */
2061         UPDATE_VF_STAT(E1000_VFGPTLBC,
2062             hw_stats->last_gptlbc, hw_stats->gptlbc);
2063
2064         /* Good Tx loopback octets */
2065         UPDATE_VF_STAT(E1000_VFGOTLBC,
2066             hw_stats->last_gotlbc, hw_stats->gotlbc);
2067 }
2068
2069 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2070                                      struct rte_eth_xstat_name *xstats_names,
2071                                      __rte_unused unsigned limit)
2072 {
2073         unsigned i;
2074
2075         if (xstats_names != NULL)
2076                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2077                         strlcpy(xstats_names[i].name,
2078                                 rte_igbvf_stats_strings[i].name,
2079                                 sizeof(xstats_names[i].name));
2080                 }
2081         return IGBVF_NB_XSTATS;
2082 }
2083
2084 static int
2085 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2086                      unsigned n)
2087 {
2088         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2090                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2091         unsigned i;
2092
2093         if (n < IGBVF_NB_XSTATS)
2094                 return IGBVF_NB_XSTATS;
2095
2096         igbvf_read_stats_registers(hw, hw_stats);
2097
2098         if (!xstats)
2099                 return 0;
2100
2101         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2102                 xstats[i].id = i;
2103                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2104                         rte_igbvf_stats_strings[i].offset);
2105         }
2106
2107         return IGBVF_NB_XSTATS;
2108 }
2109
2110 static int
2111 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2112 {
2113         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2115                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2116
2117         igbvf_read_stats_registers(hw, hw_stats);
2118
2119         if (rte_stats == NULL)
2120                 return -EINVAL;
2121
2122         rte_stats->ipackets = hw_stats->gprc;
2123         rte_stats->ibytes = hw_stats->gorc;
2124         rte_stats->opackets = hw_stats->gptc;
2125         rte_stats->obytes = hw_stats->gotc;
2126         return 0;
2127 }
2128
2129 static void
2130 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2131 {
2132         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2133                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2134
2135         /* Sync HW register to the last stats */
2136         eth_igbvf_stats_get(dev, NULL);
2137
2138         /* reset HW current stats*/
2139         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2140                offsetof(struct e1000_vf_stats, gprc));
2141 }
2142
2143 static int
2144 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2145                        size_t fw_size)
2146 {
2147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         struct e1000_fw_version fw;
2149         int ret;
2150
2151         e1000_get_fw_version(hw, &fw);
2152
2153         switch (hw->mac.type) {
2154         case e1000_i210:
2155         case e1000_i211:
2156                 if (!(e1000_get_flash_presence_i210(hw))) {
2157                         ret = snprintf(fw_version, fw_size,
2158                                  "%2d.%2d-%d",
2159                                  fw.invm_major, fw.invm_minor,
2160                                  fw.invm_img_type);
2161                         break;
2162                 }
2163                 /* fall through */
2164         default:
2165                 /* if option rom is valid, display its version too */
2166                 if (fw.or_valid) {
2167                         ret = snprintf(fw_version, fw_size,
2168                                  "%d.%d, 0x%08x, %d.%d.%d",
2169                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2170                                  fw.or_major, fw.or_build, fw.or_patch);
2171                 /* no option rom */
2172                 } else {
2173                         if (fw.etrack_id != 0X0000) {
2174                                 ret = snprintf(fw_version, fw_size,
2175                                          "%d.%d, 0x%08x",
2176                                          fw.eep_major, fw.eep_minor,
2177                                          fw.etrack_id);
2178                         } else {
2179                                 ret = snprintf(fw_version, fw_size,
2180                                          "%d.%d.%d",
2181                                          fw.eep_major, fw.eep_minor,
2182                                          fw.eep_build);
2183                         }
2184                 }
2185                 break;
2186         }
2187
2188         ret += 1; /* add the size of '\0' */
2189         if (fw_size < (u32)ret)
2190                 return ret;
2191         else
2192                 return 0;
2193 }
2194
2195 static void
2196 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2197 {
2198         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199
2200         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2201         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2202         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2203         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2204         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2205                                     dev_info->rx_queue_offload_capa;
2206         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2207         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2208                                     dev_info->tx_queue_offload_capa;
2209
2210         switch (hw->mac.type) {
2211         case e1000_82575:
2212                 dev_info->max_rx_queues = 4;
2213                 dev_info->max_tx_queues = 4;
2214                 dev_info->max_vmdq_pools = 0;
2215                 break;
2216
2217         case e1000_82576:
2218                 dev_info->max_rx_queues = 16;
2219                 dev_info->max_tx_queues = 16;
2220                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221                 dev_info->vmdq_queue_num = 16;
2222                 break;
2223
2224         case e1000_82580:
2225                 dev_info->max_rx_queues = 8;
2226                 dev_info->max_tx_queues = 8;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 8;
2229                 break;
2230
2231         case e1000_i350:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2235                 dev_info->vmdq_queue_num = 8;
2236                 break;
2237
2238         case e1000_i354:
2239                 dev_info->max_rx_queues = 8;
2240                 dev_info->max_tx_queues = 8;
2241                 break;
2242
2243         case e1000_i210:
2244                 dev_info->max_rx_queues = 4;
2245                 dev_info->max_tx_queues = 4;
2246                 dev_info->max_vmdq_pools = 0;
2247                 break;
2248
2249         case e1000_i211:
2250                 dev_info->max_rx_queues = 2;
2251                 dev_info->max_tx_queues = 2;
2252                 dev_info->max_vmdq_pools = 0;
2253                 break;
2254
2255         default:
2256                 /* Should not happen */
2257                 break;
2258         }
2259         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2260         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2261         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2262
2263         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2264                 .rx_thresh = {
2265                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2266                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2267                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2268                 },
2269                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2270                 .rx_drop_en = 0,
2271                 .offloads = 0,
2272         };
2273
2274         dev_info->default_txconf = (struct rte_eth_txconf) {
2275                 .tx_thresh = {
2276                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2277                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2278                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2279                 },
2280                 .offloads = 0,
2281         };
2282
2283         dev_info->rx_desc_lim = rx_desc_lim;
2284         dev_info->tx_desc_lim = tx_desc_lim;
2285
2286         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2287                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2288                         ETH_LINK_SPEED_1G;
2289
2290         dev_info->max_mtu = dev_info->max_rx_pktlen - E1000_ETH_OVERHEAD;
2291         dev_info->min_mtu = ETHER_MIN_MTU;
2292
2293 }
2294
2295 static const uint32_t *
2296 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2297 {
2298         static const uint32_t ptypes[] = {
2299                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2300                 RTE_PTYPE_L2_ETHER,
2301                 RTE_PTYPE_L3_IPV4,
2302                 RTE_PTYPE_L3_IPV4_EXT,
2303                 RTE_PTYPE_L3_IPV6,
2304                 RTE_PTYPE_L3_IPV6_EXT,
2305                 RTE_PTYPE_L4_TCP,
2306                 RTE_PTYPE_L4_UDP,
2307                 RTE_PTYPE_L4_SCTP,
2308                 RTE_PTYPE_TUNNEL_IP,
2309                 RTE_PTYPE_INNER_L3_IPV6,
2310                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2311                 RTE_PTYPE_INNER_L4_TCP,
2312                 RTE_PTYPE_INNER_L4_UDP,
2313                 RTE_PTYPE_UNKNOWN
2314         };
2315
2316         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2317             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2318                 return ptypes;
2319         return NULL;
2320 }
2321
2322 static void
2323 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2324 {
2325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326
2327         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2328         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2329         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2330         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2331                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2332                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2333                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2334                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2335                                 DEV_TX_OFFLOAD_TCP_TSO;
2336         switch (hw->mac.type) {
2337         case e1000_vfadapt:
2338                 dev_info->max_rx_queues = 2;
2339                 dev_info->max_tx_queues = 2;
2340                 break;
2341         case e1000_vfadapt_i350:
2342                 dev_info->max_rx_queues = 1;
2343                 dev_info->max_tx_queues = 1;
2344                 break;
2345         default:
2346                 /* Should not happen */
2347                 break;
2348         }
2349
2350         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2351         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2352                                     dev_info->rx_queue_offload_capa;
2353         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2354         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2355                                     dev_info->tx_queue_offload_capa;
2356
2357         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2358                 .rx_thresh = {
2359                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2360                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2361                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2362                 },
2363                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2364                 .rx_drop_en = 0,
2365                 .offloads = 0,
2366         };
2367
2368         dev_info->default_txconf = (struct rte_eth_txconf) {
2369                 .tx_thresh = {
2370                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2371                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2372                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2373                 },
2374                 .offloads = 0,
2375         };
2376
2377         dev_info->rx_desc_lim = rx_desc_lim;
2378         dev_info->tx_desc_lim = tx_desc_lim;
2379 }
2380
2381 /* return 0 means link status changed, -1 means not changed */
2382 static int
2383 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2384 {
2385         struct e1000_hw *hw =
2386                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2387         struct rte_eth_link link;
2388         int link_check, count;
2389
2390         link_check = 0;
2391         hw->mac.get_link_status = 1;
2392
2393         /* possible wait-to-complete in up to 9 seconds */
2394         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2395                 /* Read the real link status */
2396                 switch (hw->phy.media_type) {
2397                 case e1000_media_type_copper:
2398                         /* Do the work to read phy */
2399                         e1000_check_for_link(hw);
2400                         link_check = !hw->mac.get_link_status;
2401                         break;
2402
2403                 case e1000_media_type_fiber:
2404                         e1000_check_for_link(hw);
2405                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2406                                       E1000_STATUS_LU);
2407                         break;
2408
2409                 case e1000_media_type_internal_serdes:
2410                         e1000_check_for_link(hw);
2411                         link_check = hw->mac.serdes_has_link;
2412                         break;
2413
2414                 /* VF device is type_unknown */
2415                 case e1000_media_type_unknown:
2416                         eth_igbvf_link_update(hw);
2417                         link_check = !hw->mac.get_link_status;
2418                         break;
2419
2420                 default:
2421                         break;
2422                 }
2423                 if (link_check || wait_to_complete == 0)
2424                         break;
2425                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2426         }
2427         memset(&link, 0, sizeof(link));
2428
2429         /* Now we check if a transition has happened */
2430         if (link_check) {
2431                 uint16_t duplex, speed;
2432                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2433                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2434                                 ETH_LINK_FULL_DUPLEX :
2435                                 ETH_LINK_HALF_DUPLEX;
2436                 link.link_speed = speed;
2437                 link.link_status = ETH_LINK_UP;
2438                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2439                                 ETH_LINK_SPEED_FIXED);
2440         } else if (!link_check) {
2441                 link.link_speed = 0;
2442                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2443                 link.link_status = ETH_LINK_DOWN;
2444                 link.link_autoneg = ETH_LINK_FIXED;
2445         }
2446
2447         return rte_eth_linkstatus_set(dev, &link);
2448 }
2449
2450 /*
2451  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2452  * For ASF and Pass Through versions of f/w this means
2453  * that the driver is loaded.
2454  */
2455 static void
2456 igb_hw_control_acquire(struct e1000_hw *hw)
2457 {
2458         uint32_t ctrl_ext;
2459
2460         /* Let firmware know the driver has taken over */
2461         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2462         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2463 }
2464
2465 /*
2466  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2467  * For ASF and Pass Through versions of f/w this means that the
2468  * driver is no longer loaded.
2469  */
2470 static void
2471 igb_hw_control_release(struct e1000_hw *hw)
2472 {
2473         uint32_t ctrl_ext;
2474
2475         /* Let firmware taken over control of h/w */
2476         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2477         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2478                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2479 }
2480
2481 /*
2482  * Bit of a misnomer, what this really means is
2483  * to enable OS management of the system... aka
2484  * to disable special hardware management features.
2485  */
2486 static void
2487 igb_init_manageability(struct e1000_hw *hw)
2488 {
2489         if (e1000_enable_mng_pass_thru(hw)) {
2490                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2491                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2492
2493                 /* disable hardware interception of ARP */
2494                 manc &= ~(E1000_MANC_ARP_EN);
2495
2496                 /* enable receiving management packets to the host */
2497                 manc |= E1000_MANC_EN_MNG2HOST;
2498                 manc2h |= 1 << 5;  /* Mng Port 623 */
2499                 manc2h |= 1 << 6;  /* Mng Port 664 */
2500                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2501                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2502         }
2503 }
2504
2505 static void
2506 igb_release_manageability(struct e1000_hw *hw)
2507 {
2508         if (e1000_enable_mng_pass_thru(hw)) {
2509                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2510
2511                 manc |= E1000_MANC_ARP_EN;
2512                 manc &= ~E1000_MANC_EN_MNG2HOST;
2513
2514                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2515         }
2516 }
2517
2518 static void
2519 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rctl;
2524
2525         rctl = E1000_READ_REG(hw, E1000_RCTL);
2526         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528 }
2529
2530 static void
2531 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw =
2534                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         uint32_t rctl;
2536
2537         rctl = E1000_READ_REG(hw, E1000_RCTL);
2538         rctl &= (~E1000_RCTL_UPE);
2539         if (dev->data->all_multicast == 1)
2540                 rctl |= E1000_RCTL_MPE;
2541         else
2542                 rctl &= (~E1000_RCTL_MPE);
2543         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2544 }
2545
2546 static void
2547 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2548 {
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         uint32_t rctl;
2552
2553         rctl = E1000_READ_REG(hw, E1000_RCTL);
2554         rctl |= E1000_RCTL_MPE;
2555         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556 }
2557
2558 static void
2559 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2560 {
2561         struct e1000_hw *hw =
2562                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563         uint32_t rctl;
2564
2565         if (dev->data->promiscuous == 1)
2566                 return; /* must remain in all_multicast mode */
2567         rctl = E1000_READ_REG(hw, E1000_RCTL);
2568         rctl &= (~E1000_RCTL_MPE);
2569         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2570 }
2571
2572 static int
2573 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2574 {
2575         struct e1000_hw *hw =
2576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577         struct e1000_vfta * shadow_vfta =
2578                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2579         uint32_t vfta;
2580         uint32_t vid_idx;
2581         uint32_t vid_bit;
2582
2583         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2584                               E1000_VFTA_ENTRY_MASK);
2585         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2586         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2587         if (on)
2588                 vfta |= vid_bit;
2589         else
2590                 vfta &= ~vid_bit;
2591         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2592
2593         /* update local VFTA copy */
2594         shadow_vfta->vfta[vid_idx] = vfta;
2595
2596         return 0;
2597 }
2598
2599 static int
2600 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2601                       enum rte_vlan_type vlan_type,
2602                       uint16_t tpid)
2603 {
2604         struct e1000_hw *hw =
2605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         uint32_t reg, qinq;
2607
2608         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2609         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2610
2611         /* only outer TPID of double VLAN can be configured*/
2612         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2613                 reg = E1000_READ_REG(hw, E1000_VET);
2614                 reg = (reg & (~E1000_VET_VET_EXT)) |
2615                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2616                 E1000_WRITE_REG(hw, E1000_VET, reg);
2617
2618                 return 0;
2619         }
2620
2621         /* all other TPID values are read-only*/
2622         PMD_DRV_LOG(ERR, "Not supported");
2623
2624         return -ENOTSUP;
2625 }
2626
2627 static void
2628 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2629 {
2630         struct e1000_hw *hw =
2631                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         uint32_t reg;
2633
2634         /* Filter Table Disable */
2635         reg = E1000_READ_REG(hw, E1000_RCTL);
2636         reg &= ~E1000_RCTL_CFIEN;
2637         reg &= ~E1000_RCTL_VFE;
2638         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2639 }
2640
2641 static void
2642 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2643 {
2644         struct e1000_hw *hw =
2645                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646         struct e1000_vfta * shadow_vfta =
2647                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2648         uint32_t reg;
2649         int i;
2650
2651         /* Filter Table Enable, CFI not used for packet acceptance */
2652         reg = E1000_READ_REG(hw, E1000_RCTL);
2653         reg &= ~E1000_RCTL_CFIEN;
2654         reg |= E1000_RCTL_VFE;
2655         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2656
2657         /* restore VFTA table */
2658         for (i = 0; i < IGB_VFTA_SIZE; i++)
2659                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2660 }
2661
2662 static void
2663 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2664 {
2665         struct e1000_hw *hw =
2666                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667         uint32_t reg;
2668
2669         /* VLAN Mode Disable */
2670         reg = E1000_READ_REG(hw, E1000_CTRL);
2671         reg &= ~E1000_CTRL_VME;
2672         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2673 }
2674
2675 static void
2676 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2677 {
2678         struct e1000_hw *hw =
2679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         uint32_t reg;
2681
2682         /* VLAN Mode Enable */
2683         reg = E1000_READ_REG(hw, E1000_CTRL);
2684         reg |= E1000_CTRL_VME;
2685         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2686 }
2687
2688 static void
2689 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2690 {
2691         struct e1000_hw *hw =
2692                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2693         uint32_t reg;
2694
2695         /* CTRL_EXT: Extended VLAN */
2696         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2697         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2698         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2699
2700         /* Update maximum packet length */
2701         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2702                 E1000_WRITE_REG(hw, E1000_RLPML,
2703                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2704                                                 VLAN_TAG_SIZE);
2705 }
2706
2707 static void
2708 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2709 {
2710         struct e1000_hw *hw =
2711                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2712         uint32_t reg;
2713
2714         /* CTRL_EXT: Extended VLAN */
2715         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2716         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2717         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2718
2719         /* Update maximum packet length */
2720         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2721                 E1000_WRITE_REG(hw, E1000_RLPML,
2722                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2723                                                 2 * VLAN_TAG_SIZE);
2724 }
2725
2726 static int
2727 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2728 {
2729         struct rte_eth_rxmode *rxmode;
2730
2731         rxmode = &dev->data->dev_conf.rxmode;
2732         if(mask & ETH_VLAN_STRIP_MASK){
2733                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2734                         igb_vlan_hw_strip_enable(dev);
2735                 else
2736                         igb_vlan_hw_strip_disable(dev);
2737         }
2738
2739         if(mask & ETH_VLAN_FILTER_MASK){
2740                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2741                         igb_vlan_hw_filter_enable(dev);
2742                 else
2743                         igb_vlan_hw_filter_disable(dev);
2744         }
2745
2746         if(mask & ETH_VLAN_EXTEND_MASK){
2747                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2748                         igb_vlan_hw_extend_enable(dev);
2749                 else
2750                         igb_vlan_hw_extend_disable(dev);
2751         }
2752
2753         return 0;
2754 }
2755
2756
2757 /**
2758  * It enables the interrupt mask and then enable the interrupt.
2759  *
2760  * @param dev
2761  *  Pointer to struct rte_eth_dev.
2762  * @param on
2763  *  Enable or Disable
2764  *
2765  * @return
2766  *  - On success, zero.
2767  *  - On failure, a negative value.
2768  */
2769 static int
2770 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2771 {
2772         struct e1000_interrupt *intr =
2773                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2774
2775         if (on)
2776                 intr->mask |= E1000_ICR_LSC;
2777         else
2778                 intr->mask &= ~E1000_ICR_LSC;
2779
2780         return 0;
2781 }
2782
2783 /* It clears the interrupt causes and enables the interrupt.
2784  * It will be called once only during nic initialized.
2785  *
2786  * @param dev
2787  *  Pointer to struct rte_eth_dev.
2788  *
2789  * @return
2790  *  - On success, zero.
2791  *  - On failure, a negative value.
2792  */
2793 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2794 {
2795         uint32_t mask, regval;
2796         struct e1000_hw *hw =
2797                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2799         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2800         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
2801         struct rte_eth_dev_info dev_info;
2802
2803         memset(&dev_info, 0, sizeof(dev_info));
2804         eth_igb_infos_get(dev, &dev_info);
2805
2806         mask = (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift;
2807         regval = E1000_READ_REG(hw, E1000_EIMS);
2808         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2809
2810         return 0;
2811 }
2812
2813 /*
2814  * It reads ICR and gets interrupt causes, check it and set a bit flag
2815  * to update link status.
2816  *
2817  * @param dev
2818  *  Pointer to struct rte_eth_dev.
2819  *
2820  * @return
2821  *  - On success, zero.
2822  *  - On failure, a negative value.
2823  */
2824 static int
2825 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2826 {
2827         uint32_t icr;
2828         struct e1000_hw *hw =
2829                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830         struct e1000_interrupt *intr =
2831                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2832
2833         igb_intr_disable(dev);
2834
2835         /* read-on-clear nic registers here */
2836         icr = E1000_READ_REG(hw, E1000_ICR);
2837
2838         intr->flags = 0;
2839         if (icr & E1000_ICR_LSC) {
2840                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2841         }
2842
2843         if (icr & E1000_ICR_VMMB)
2844                 intr->flags |= E1000_FLAG_MAILBOX;
2845
2846         return 0;
2847 }
2848
2849 /*
2850  * It executes link_update after knowing an interrupt is prsent.
2851  *
2852  * @param dev
2853  *  Pointer to struct rte_eth_dev.
2854  *
2855  * @return
2856  *  - On success, zero.
2857  *  - On failure, a negative value.
2858  */
2859 static int
2860 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2861                          struct rte_intr_handle *intr_handle)
2862 {
2863         struct e1000_hw *hw =
2864                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct e1000_interrupt *intr =
2866                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2868         struct rte_eth_link link;
2869         int ret;
2870
2871         if (intr->flags & E1000_FLAG_MAILBOX) {
2872                 igb_pf_mbx_process(dev);
2873                 intr->flags &= ~E1000_FLAG_MAILBOX;
2874         }
2875
2876         igb_intr_enable(dev);
2877         rte_intr_enable(intr_handle);
2878
2879         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2880                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2881
2882                 /* set get_link_status to check register later */
2883                 hw->mac.get_link_status = 1;
2884                 ret = eth_igb_link_update(dev, 0);
2885
2886                 /* check if link has changed */
2887                 if (ret < 0)
2888                         return 0;
2889
2890                 rte_eth_linkstatus_get(dev, &link);
2891                 if (link.link_status) {
2892                         PMD_INIT_LOG(INFO,
2893                                      " Port %d: Link Up - speed %u Mbps - %s",
2894                                      dev->data->port_id,
2895                                      (unsigned)link.link_speed,
2896                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2897                                      "full-duplex" : "half-duplex");
2898                 } else {
2899                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2900                                      dev->data->port_id);
2901                 }
2902
2903                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2904                              pci_dev->addr.domain,
2905                              pci_dev->addr.bus,
2906                              pci_dev->addr.devid,
2907                              pci_dev->addr.function);
2908                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2909                                               NULL);
2910         }
2911
2912         return 0;
2913 }
2914
2915 /**
2916  * Interrupt handler which shall be registered at first.
2917  *
2918  * @param handle
2919  *  Pointer to interrupt handle.
2920  * @param param
2921  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2922  *
2923  * @return
2924  *  void
2925  */
2926 static void
2927 eth_igb_interrupt_handler(void *param)
2928 {
2929         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2930
2931         eth_igb_interrupt_get_status(dev);
2932         eth_igb_interrupt_action(dev, dev->intr_handle);
2933 }
2934
2935 static int
2936 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2937 {
2938         uint32_t eicr;
2939         struct e1000_hw *hw =
2940                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         struct e1000_interrupt *intr =
2942                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2943
2944         igbvf_intr_disable(hw);
2945
2946         /* read-on-clear nic registers here */
2947         eicr = E1000_READ_REG(hw, E1000_EICR);
2948         intr->flags = 0;
2949
2950         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2951                 intr->flags |= E1000_FLAG_MAILBOX;
2952
2953         return 0;
2954 }
2955
2956 void igbvf_mbx_process(struct rte_eth_dev *dev)
2957 {
2958         struct e1000_hw *hw =
2959                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct e1000_mbx_info *mbx = &hw->mbx;
2961         u32 in_msg = 0;
2962
2963         /* peek the message first */
2964         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2965
2966         /* PF reset VF event */
2967         if (in_msg == E1000_PF_CONTROL_MSG) {
2968                 /* dummy mbx read to ack pf */
2969                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2970                         return;
2971                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2972                                               NULL);
2973         }
2974 }
2975
2976 static int
2977 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2978 {
2979         struct e1000_interrupt *intr =
2980                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2981
2982         if (intr->flags & E1000_FLAG_MAILBOX) {
2983                 igbvf_mbx_process(dev);
2984                 intr->flags &= ~E1000_FLAG_MAILBOX;
2985         }
2986
2987         igbvf_intr_enable(dev);
2988         rte_intr_enable(intr_handle);
2989
2990         return 0;
2991 }
2992
2993 static void
2994 eth_igbvf_interrupt_handler(void *param)
2995 {
2996         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2997
2998         eth_igbvf_interrupt_get_status(dev);
2999         eth_igbvf_interrupt_action(dev, dev->intr_handle);
3000 }
3001
3002 static int
3003 eth_igb_led_on(struct rte_eth_dev *dev)
3004 {
3005         struct e1000_hw *hw;
3006
3007         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3008         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3009 }
3010
3011 static int
3012 eth_igb_led_off(struct rte_eth_dev *dev)
3013 {
3014         struct e1000_hw *hw;
3015
3016         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3018 }
3019
3020 static int
3021 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3022 {
3023         struct e1000_hw *hw;
3024         uint32_t ctrl;
3025         int tx_pause;
3026         int rx_pause;
3027
3028         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3029         fc_conf->pause_time = hw->fc.pause_time;
3030         fc_conf->high_water = hw->fc.high_water;
3031         fc_conf->low_water = hw->fc.low_water;
3032         fc_conf->send_xon = hw->fc.send_xon;
3033         fc_conf->autoneg = hw->mac.autoneg;
3034
3035         /*
3036          * Return rx_pause and tx_pause status according to actual setting of
3037          * the TFCE and RFCE bits in the CTRL register.
3038          */
3039         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3040         if (ctrl & E1000_CTRL_TFCE)
3041                 tx_pause = 1;
3042         else
3043                 tx_pause = 0;
3044
3045         if (ctrl & E1000_CTRL_RFCE)
3046                 rx_pause = 1;
3047         else
3048                 rx_pause = 0;
3049
3050         if (rx_pause && tx_pause)
3051                 fc_conf->mode = RTE_FC_FULL;
3052         else if (rx_pause)
3053                 fc_conf->mode = RTE_FC_RX_PAUSE;
3054         else if (tx_pause)
3055                 fc_conf->mode = RTE_FC_TX_PAUSE;
3056         else
3057                 fc_conf->mode = RTE_FC_NONE;
3058
3059         return 0;
3060 }
3061
3062 static int
3063 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3064 {
3065         struct e1000_hw *hw;
3066         int err;
3067         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3068                 e1000_fc_none,
3069                 e1000_fc_rx_pause,
3070                 e1000_fc_tx_pause,
3071                 e1000_fc_full
3072         };
3073         uint32_t rx_buf_size;
3074         uint32_t max_high_water;
3075         uint32_t rctl;
3076
3077         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3078         if (fc_conf->autoneg != hw->mac.autoneg)
3079                 return -ENOTSUP;
3080         rx_buf_size = igb_get_rx_buffer_size(hw);
3081         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3082
3083         /* At least reserve one Ethernet frame for watermark */
3084         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3085         if ((fc_conf->high_water > max_high_water) ||
3086             (fc_conf->high_water < fc_conf->low_water)) {
3087                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3088                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3089                 return -EINVAL;
3090         }
3091
3092         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3093         hw->fc.pause_time     = fc_conf->pause_time;
3094         hw->fc.high_water     = fc_conf->high_water;
3095         hw->fc.low_water      = fc_conf->low_water;
3096         hw->fc.send_xon       = fc_conf->send_xon;
3097
3098         err = e1000_setup_link_generic(hw);
3099         if (err == E1000_SUCCESS) {
3100
3101                 /* check if we want to forward MAC frames - driver doesn't have native
3102                  * capability to do that, so we'll write the registers ourselves */
3103
3104                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3105
3106                 /* set or clear MFLCN.PMCF bit depending on configuration */
3107                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3108                         rctl |= E1000_RCTL_PMCF;
3109                 else
3110                         rctl &= ~E1000_RCTL_PMCF;
3111
3112                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3113                 E1000_WRITE_FLUSH(hw);
3114
3115                 return 0;
3116         }
3117
3118         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3119         return -EIO;
3120 }
3121
3122 #define E1000_RAH_POOLSEL_SHIFT      (18)
3123 static int
3124 eth_igb_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3125                 uint32_t index, uint32_t pool)
3126 {
3127         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128         uint32_t rah;
3129
3130         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3131         rah = E1000_READ_REG(hw, E1000_RAH(index));
3132         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3133         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3134         return 0;
3135 }
3136
3137 static void
3138 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3139 {
3140         uint8_t addr[ETHER_ADDR_LEN];
3141         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142
3143         memset(addr, 0, sizeof(addr));
3144
3145         e1000_rar_set(hw, addr, index);
3146 }
3147
3148 static int
3149 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3150                                 struct rte_ether_addr *addr)
3151 {
3152         eth_igb_rar_clear(dev, 0);
3153         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3154
3155         return 0;
3156 }
3157 /*
3158  * Virtual Function operations
3159  */
3160 static void
3161 igbvf_intr_disable(struct e1000_hw *hw)
3162 {
3163         PMD_INIT_FUNC_TRACE();
3164
3165         /* Clear interrupt mask to stop from interrupts being generated */
3166         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3167
3168         E1000_WRITE_FLUSH(hw);
3169 }
3170
3171 static void
3172 igbvf_stop_adapter(struct rte_eth_dev *dev)
3173 {
3174         u32 reg_val;
3175         u16 i;
3176         struct rte_eth_dev_info dev_info;
3177         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3178
3179         memset(&dev_info, 0, sizeof(dev_info));
3180         eth_igbvf_infos_get(dev, &dev_info);
3181
3182         /* Clear interrupt mask to stop from interrupts being generated */
3183         igbvf_intr_disable(hw);
3184
3185         /* Clear any pending interrupts, flush previous writes */
3186         E1000_READ_REG(hw, E1000_EICR);
3187
3188         /* Disable the transmit unit.  Each queue must be disabled. */
3189         for (i = 0; i < dev_info.max_tx_queues; i++)
3190                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3191
3192         /* Disable the receive unit by stopping each queue */
3193         for (i = 0; i < dev_info.max_rx_queues; i++) {
3194                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3195                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3196                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3197                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3198                         ;
3199         }
3200
3201         /* flush all queues disables */
3202         E1000_WRITE_FLUSH(hw);
3203         msec_delay(2);
3204 }
3205
3206 static int eth_igbvf_link_update(struct e1000_hw *hw)
3207 {
3208         struct e1000_mbx_info *mbx = &hw->mbx;
3209         struct e1000_mac_info *mac = &hw->mac;
3210         int ret_val = E1000_SUCCESS;
3211
3212         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3213
3214         /*
3215          * We only want to run this if there has been a rst asserted.
3216          * in this case that could mean a link change, device reset,
3217          * or a virtual function reset
3218          */
3219
3220         /* If we were hit with a reset or timeout drop the link */
3221         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3222                 mac->get_link_status = TRUE;
3223
3224         if (!mac->get_link_status)
3225                 goto out;
3226
3227         /* if link status is down no point in checking to see if pf is up */
3228         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3229                 goto out;
3230
3231         /* if we passed all the tests above then the link is up and we no
3232          * longer need to check for link */
3233         mac->get_link_status = FALSE;
3234
3235 out:
3236         return ret_val;
3237 }
3238
3239
3240 static int
3241 igbvf_dev_configure(struct rte_eth_dev *dev)
3242 {
3243         struct rte_eth_conf* conf = &dev->data->dev_conf;
3244
3245         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3246                      dev->data->port_id);
3247
3248         /*
3249          * VF has no ability to enable/disable HW CRC
3250          * Keep the persistent behavior the same as Host PF
3251          */
3252 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3253         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
3254                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3255                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
3256         }
3257 #else
3258         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
3259                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3260                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
3261         }
3262 #endif
3263
3264         return 0;
3265 }
3266
3267 static int
3268 igbvf_dev_start(struct rte_eth_dev *dev)
3269 {
3270         struct e1000_hw *hw =
3271                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272         struct e1000_adapter *adapter =
3273                 E1000_DEV_PRIVATE(dev->data->dev_private);
3274         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3276         int ret;
3277         uint32_t intr_vector = 0;
3278
3279         PMD_INIT_FUNC_TRACE();
3280
3281         hw->mac.ops.reset_hw(hw);
3282         adapter->stopped = 0;
3283
3284         /* Set all vfta */
3285         igbvf_set_vfta_all(dev,1);
3286
3287         eth_igbvf_tx_init(dev);
3288
3289         /* This can fail when allocating mbufs for descriptor rings */
3290         ret = eth_igbvf_rx_init(dev);
3291         if (ret) {
3292                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3293                 igb_dev_clear_queues(dev);
3294                 return ret;
3295         }
3296
3297         /* check and configure queue intr-vector mapping */
3298         if (rte_intr_cap_multiple(intr_handle) &&
3299             dev->data->dev_conf.intr_conf.rxq) {
3300                 intr_vector = dev->data->nb_rx_queues;
3301                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3302                 if (ret)
3303                         return ret;
3304         }
3305
3306         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3307                 intr_handle->intr_vec =
3308                         rte_zmalloc("intr_vec",
3309                                     dev->data->nb_rx_queues * sizeof(int), 0);
3310                 if (!intr_handle->intr_vec) {
3311                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3312                                      " intr_vec", dev->data->nb_rx_queues);
3313                         return -ENOMEM;
3314                 }
3315         }
3316
3317         eth_igbvf_configure_msix_intr(dev);
3318
3319         /* enable uio/vfio intr/eventfd mapping */
3320         rte_intr_enable(intr_handle);
3321
3322         /* resume enabled intr since hw reset */
3323         igbvf_intr_enable(dev);
3324
3325         return 0;
3326 }
3327
3328 static void
3329 igbvf_dev_stop(struct rte_eth_dev *dev)
3330 {
3331         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3332         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3333
3334         PMD_INIT_FUNC_TRACE();
3335
3336         igbvf_stop_adapter(dev);
3337
3338         /*
3339           * Clear what we set, but we still keep shadow_vfta to
3340           * restore after device starts
3341           */
3342         igbvf_set_vfta_all(dev,0);
3343
3344         igb_dev_clear_queues(dev);
3345
3346         /* disable intr eventfd mapping */
3347         rte_intr_disable(intr_handle);
3348
3349         /* Clean datapath event and queue/vec mapping */
3350         rte_intr_efd_disable(intr_handle);
3351         if (intr_handle->intr_vec) {
3352                 rte_free(intr_handle->intr_vec);
3353                 intr_handle->intr_vec = NULL;
3354         }
3355 }
3356
3357 static void
3358 igbvf_dev_close(struct rte_eth_dev *dev)
3359 {
3360         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3361         struct e1000_adapter *adapter =
3362                 E1000_DEV_PRIVATE(dev->data->dev_private);
3363         struct rte_ether_addr addr;
3364
3365         PMD_INIT_FUNC_TRACE();
3366
3367         e1000_reset_hw(hw);
3368
3369         igbvf_dev_stop(dev);
3370         adapter->stopped = 1;
3371         igb_dev_free_queues(dev);
3372
3373         /**
3374          * reprogram the RAR with a zero mac address,
3375          * to ensure that the VF traffic goes to the PF
3376          * after stop, close and detach of the VF.
3377          **/
3378
3379         memset(&addr, 0, sizeof(addr));
3380         igbvf_default_mac_addr_set(dev, &addr);
3381 }
3382
3383 static void
3384 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3385 {
3386         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387
3388         /* Set both unicast and multicast promisc */
3389         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3390 }
3391
3392 static void
3393 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3394 {
3395         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396
3397         /* If in allmulticast mode leave multicast promisc */
3398         if (dev->data->all_multicast == 1)
3399                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3400         else
3401                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3402 }
3403
3404 static void
3405 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3406 {
3407         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3408
3409         /* In promiscuous mode multicast promisc already set */
3410         if (dev->data->promiscuous == 0)
3411                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3412 }
3413
3414 static void
3415 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3416 {
3417         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418
3419         /* In promiscuous mode leave multicast promisc enabled */
3420         if (dev->data->promiscuous == 0)
3421                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3422 }
3423
3424 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3425 {
3426         struct e1000_mbx_info *mbx = &hw->mbx;
3427         uint32_t msgbuf[2];
3428         s32 err;
3429
3430         /* After set vlan, vlan strip will also be enabled in igb driver*/
3431         msgbuf[0] = E1000_VF_SET_VLAN;
3432         msgbuf[1] = vid;
3433         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3434         if (on)
3435                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3436
3437         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3438         if (err)
3439                 goto mbx_err;
3440
3441         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3442         if (err)
3443                 goto mbx_err;
3444
3445         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3446         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3447                 err = -EINVAL;
3448
3449 mbx_err:
3450         return err;
3451 }
3452
3453 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3454 {
3455         struct e1000_hw *hw =
3456                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3457         struct e1000_vfta * shadow_vfta =
3458                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3459         int i = 0, j = 0, vfta = 0, mask = 1;
3460
3461         for (i = 0; i < IGB_VFTA_SIZE; i++){
3462                 vfta = shadow_vfta->vfta[i];
3463                 if(vfta){
3464                         mask = 1;
3465                         for (j = 0; j < 32; j++){
3466                                 if(vfta & mask)
3467                                         igbvf_set_vfta(hw,
3468                                                 (uint16_t)((i<<5)+j), on);
3469                                 mask<<=1;
3470                         }
3471                 }
3472         }
3473
3474 }
3475
3476 static int
3477 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3478 {
3479         struct e1000_hw *hw =
3480                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3481         struct e1000_vfta * shadow_vfta =
3482                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3483         uint32_t vid_idx = 0;
3484         uint32_t vid_bit = 0;
3485         int ret = 0;
3486
3487         PMD_INIT_FUNC_TRACE();
3488
3489         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3490         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3491         if(ret){
3492                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3493                 return ret;
3494         }
3495         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3496         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3497
3498         /*Save what we set and retore it after device reset*/
3499         if (on)
3500                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3501         else
3502                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3503
3504         return 0;
3505 }
3506
3507 static int
3508 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3509 {
3510         struct e1000_hw *hw =
3511                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3512
3513         /* index is not used by rar_set() */
3514         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3515         return 0;
3516 }
3517
3518
3519 static int
3520 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3521                         struct rte_eth_rss_reta_entry64 *reta_conf,
3522                         uint16_t reta_size)
3523 {
3524         uint8_t i, j, mask;
3525         uint32_t reta, r;
3526         uint16_t idx, shift;
3527         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528
3529         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3530                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3531                         "(%d) doesn't match the number hardware can supported "
3532                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3533                 return -EINVAL;
3534         }
3535
3536         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3537                 idx = i / RTE_RETA_GROUP_SIZE;
3538                 shift = i % RTE_RETA_GROUP_SIZE;
3539                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3540                                                 IGB_4_BIT_MASK);
3541                 if (!mask)
3542                         continue;
3543                 if (mask == IGB_4_BIT_MASK)
3544                         r = 0;
3545                 else
3546                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3547                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3548                         if (mask & (0x1 << j))
3549                                 reta |= reta_conf[idx].reta[shift + j] <<
3550                                                         (CHAR_BIT * j);
3551                         else
3552                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3553                 }
3554                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3555         }
3556
3557         return 0;
3558 }
3559
3560 static int
3561 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3562                        struct rte_eth_rss_reta_entry64 *reta_conf,
3563                        uint16_t reta_size)
3564 {
3565         uint8_t i, j, mask;
3566         uint32_t reta;
3567         uint16_t idx, shift;
3568         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569
3570         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3571                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3572                         "(%d) doesn't match the number hardware can supported "
3573                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3574                 return -EINVAL;
3575         }
3576
3577         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3578                 idx = i / RTE_RETA_GROUP_SIZE;
3579                 shift = i % RTE_RETA_GROUP_SIZE;
3580                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3581                                                 IGB_4_BIT_MASK);
3582                 if (!mask)
3583                         continue;
3584                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3585                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3586                         if (mask & (0x1 << j))
3587                                 reta_conf[idx].reta[shift + j] =
3588                                         ((reta >> (CHAR_BIT * j)) &
3589                                                 IGB_8_BIT_MASK);
3590                 }
3591         }
3592
3593         return 0;
3594 }
3595
3596 int
3597 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3598                         struct rte_eth_syn_filter *filter,
3599                         bool add)
3600 {
3601         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602         struct e1000_filter_info *filter_info =
3603                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3604         uint32_t synqf, rfctl;
3605
3606         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3607                 return -EINVAL;
3608
3609         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3610
3611         if (add) {
3612                 if (synqf & E1000_SYN_FILTER_ENABLE)
3613                         return -EINVAL;
3614
3615                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3616                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3617
3618                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3619                 if (filter->hig_pri)
3620                         rfctl |= E1000_RFCTL_SYNQFP;
3621                 else
3622                         rfctl &= ~E1000_RFCTL_SYNQFP;
3623
3624                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3625         } else {
3626                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3627                         return -ENOENT;
3628                 synqf = 0;
3629         }
3630
3631         filter_info->syn_info = synqf;
3632         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3633         E1000_WRITE_FLUSH(hw);
3634         return 0;
3635 }
3636
3637 static int
3638 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3639                         struct rte_eth_syn_filter *filter)
3640 {
3641         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3642         uint32_t synqf, rfctl;
3643
3644         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3645         if (synqf & E1000_SYN_FILTER_ENABLE) {
3646                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3647                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3648                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3649                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3650                 return 0;
3651         }
3652
3653         return -ENOENT;
3654 }
3655
3656 static int
3657 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3658                         enum rte_filter_op filter_op,
3659                         void *arg)
3660 {
3661         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662         int ret;
3663
3664         MAC_TYPE_FILTER_SUP(hw->mac.type);
3665
3666         if (filter_op == RTE_ETH_FILTER_NOP)
3667                 return 0;
3668
3669         if (arg == NULL) {
3670                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3671                             filter_op);
3672                 return -EINVAL;
3673         }
3674
3675         switch (filter_op) {
3676         case RTE_ETH_FILTER_ADD:
3677                 ret = eth_igb_syn_filter_set(dev,
3678                                 (struct rte_eth_syn_filter *)arg,
3679                                 TRUE);
3680                 break;
3681         case RTE_ETH_FILTER_DELETE:
3682                 ret = eth_igb_syn_filter_set(dev,
3683                                 (struct rte_eth_syn_filter *)arg,
3684                                 FALSE);
3685                 break;
3686         case RTE_ETH_FILTER_GET:
3687                 ret = eth_igb_syn_filter_get(dev,
3688                                 (struct rte_eth_syn_filter *)arg);
3689                 break;
3690         default:
3691                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3692                 ret = -EINVAL;
3693                 break;
3694         }
3695
3696         return ret;
3697 }
3698
3699 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3700 static inline int
3701 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3702                         struct e1000_2tuple_filter_info *filter_info)
3703 {
3704         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3705                 return -EINVAL;
3706         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3707                 return -EINVAL;  /* filter index is out of range. */
3708         if (filter->tcp_flags > TCP_FLAG_ALL)
3709                 return -EINVAL;  /* flags is invalid. */
3710
3711         switch (filter->dst_port_mask) {
3712         case UINT16_MAX:
3713                 filter_info->dst_port_mask = 0;
3714                 filter_info->dst_port = filter->dst_port;
3715                 break;
3716         case 0:
3717                 filter_info->dst_port_mask = 1;
3718                 break;
3719         default:
3720                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3721                 return -EINVAL;
3722         }
3723
3724         switch (filter->proto_mask) {
3725         case UINT8_MAX:
3726                 filter_info->proto_mask = 0;
3727                 filter_info->proto = filter->proto;
3728                 break;
3729         case 0:
3730                 filter_info->proto_mask = 1;
3731                 break;
3732         default:
3733                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3734                 return -EINVAL;
3735         }
3736
3737         filter_info->priority = (uint8_t)filter->priority;
3738         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3739                 filter_info->tcp_flags = filter->tcp_flags;
3740         else
3741                 filter_info->tcp_flags = 0;
3742
3743         return 0;
3744 }
3745
3746 static inline struct e1000_2tuple_filter *
3747 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3748                         struct e1000_2tuple_filter_info *key)
3749 {
3750         struct e1000_2tuple_filter *it;
3751
3752         TAILQ_FOREACH(it, filter_list, entries) {
3753                 if (memcmp(key, &it->filter_info,
3754                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3755                         return it;
3756                 }
3757         }
3758         return NULL;
3759 }
3760
3761 /* inject a igb 2tuple filter to HW */
3762 static inline void
3763 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3764                            struct e1000_2tuple_filter *filter)
3765 {
3766         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3768         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3769         int i;
3770
3771         i = filter->index;
3772         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3773         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3774                 imir |= E1000_IMIR_PORT_BP;
3775         else
3776                 imir &= ~E1000_IMIR_PORT_BP;
3777
3778         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3779
3780         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3781         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3782         ttqf |= (uint32_t)(filter->filter_info.proto &
3783                                                 E1000_TTQF_PROTOCOL_MASK);
3784         if (filter->filter_info.proto_mask == 0)
3785                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3786
3787         /* tcp flags bits setting. */
3788         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3789                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3790                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3791                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3792                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3793                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3794                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3795                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3796                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3797                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3798                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3799                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3800                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3801         } else {
3802                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3803         }
3804         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3805         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3806         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3807 }
3808
3809 /*
3810  * igb_add_2tuple_filter - add a 2tuple filter
3811  *
3812  * @param
3813  * dev: Pointer to struct rte_eth_dev.
3814  * ntuple_filter: ponter to the filter that will be added.
3815  *
3816  * @return
3817  *    - On success, zero.
3818  *    - On failure, a negative value.
3819  */
3820 static int
3821 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3822                         struct rte_eth_ntuple_filter *ntuple_filter)
3823 {
3824         struct e1000_filter_info *filter_info =
3825                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3826         struct e1000_2tuple_filter *filter;
3827         int i, ret;
3828
3829         filter = rte_zmalloc("e1000_2tuple_filter",
3830                         sizeof(struct e1000_2tuple_filter), 0);
3831         if (filter == NULL)
3832                 return -ENOMEM;
3833
3834         ret = ntuple_filter_to_2tuple(ntuple_filter,
3835                                       &filter->filter_info);
3836         if (ret < 0) {
3837                 rte_free(filter);
3838                 return ret;
3839         }
3840         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3841                                          &filter->filter_info) != NULL) {
3842                 PMD_DRV_LOG(ERR, "filter exists.");
3843                 rte_free(filter);
3844                 return -EEXIST;
3845         }
3846         filter->queue = ntuple_filter->queue;
3847
3848         /*
3849          * look for an unused 2tuple filter index,
3850          * and insert the filter to list.
3851          */
3852         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3853                 if (!(filter_info->twotuple_mask & (1 << i))) {
3854                         filter_info->twotuple_mask |= 1 << i;
3855                         filter->index = i;
3856                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3857                                           filter,
3858                                           entries);
3859                         break;
3860                 }
3861         }
3862         if (i >= E1000_MAX_TTQF_FILTERS) {
3863                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3864                 rte_free(filter);
3865                 return -ENOSYS;
3866         }
3867
3868         igb_inject_2uple_filter(dev, filter);
3869         return 0;
3870 }
3871
3872 int
3873 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3874                         struct e1000_2tuple_filter *filter)
3875 {
3876         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3877         struct e1000_filter_info *filter_info =
3878                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3879
3880         filter_info->twotuple_mask &= ~(1 << filter->index);
3881         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3882         rte_free(filter);
3883
3884         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3885         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3886         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3887         return 0;
3888 }
3889
3890 /*
3891  * igb_remove_2tuple_filter - remove a 2tuple filter
3892  *
3893  * @param
3894  * dev: Pointer to struct rte_eth_dev.
3895  * ntuple_filter: ponter to the filter that will be removed.
3896  *
3897  * @return
3898  *    - On success, zero.
3899  *    - On failure, a negative value.
3900  */
3901 static int
3902 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3903                         struct rte_eth_ntuple_filter *ntuple_filter)
3904 {
3905         struct e1000_filter_info *filter_info =
3906                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3907         struct e1000_2tuple_filter_info filter_2tuple;
3908         struct e1000_2tuple_filter *filter;
3909         int ret;
3910
3911         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3912         ret = ntuple_filter_to_2tuple(ntuple_filter,
3913                                       &filter_2tuple);
3914         if (ret < 0)
3915                 return ret;
3916
3917         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3918                                          &filter_2tuple);
3919         if (filter == NULL) {
3920                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3921                 return -ENOENT;
3922         }
3923
3924         igb_delete_2tuple_filter(dev, filter);
3925
3926         return 0;
3927 }
3928
3929 /* inject a igb flex filter to HW */
3930 static inline void
3931 igb_inject_flex_filter(struct rte_eth_dev *dev,
3932                            struct e1000_flex_filter *filter)
3933 {
3934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935         uint32_t wufc, queueing;
3936         uint32_t reg_off;
3937         uint8_t i, j = 0;
3938
3939         wufc = E1000_READ_REG(hw, E1000_WUFC);
3940         if (filter->index < E1000_MAX_FHFT)
3941                 reg_off = E1000_FHFT(filter->index);
3942         else
3943                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3944
3945         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3946                         (E1000_WUFC_FLX0 << filter->index));
3947         queueing = filter->filter_info.len |
3948                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3949                 (filter->filter_info.priority <<
3950                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3951         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3952                         queueing);
3953
3954         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3955                 E1000_WRITE_REG(hw, reg_off,
3956                                 filter->filter_info.dwords[j]);
3957                 reg_off += sizeof(uint32_t);
3958                 E1000_WRITE_REG(hw, reg_off,
3959                                 filter->filter_info.dwords[++j]);
3960                 reg_off += sizeof(uint32_t);
3961                 E1000_WRITE_REG(hw, reg_off,
3962                         (uint32_t)filter->filter_info.mask[i]);
3963                 reg_off += sizeof(uint32_t) * 2;
3964                 ++j;
3965         }
3966 }
3967
3968 static inline struct e1000_flex_filter *
3969 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3970                         struct e1000_flex_filter_info *key)
3971 {
3972         struct e1000_flex_filter *it;
3973
3974         TAILQ_FOREACH(it, filter_list, entries) {
3975                 if (memcmp(key, &it->filter_info,
3976                         sizeof(struct e1000_flex_filter_info)) == 0)
3977                         return it;
3978         }
3979
3980         return NULL;
3981 }
3982
3983 /* remove a flex byte filter
3984  * @param
3985  * dev: Pointer to struct rte_eth_dev.
3986  * filter: the pointer of the filter will be removed.
3987  */
3988 void
3989 igb_remove_flex_filter(struct rte_eth_dev *dev,
3990                         struct e1000_flex_filter *filter)
3991 {
3992         struct e1000_filter_info *filter_info =
3993                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3994         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         uint32_t wufc, i;
3996         uint32_t reg_off;
3997
3998         wufc = E1000_READ_REG(hw, E1000_WUFC);
3999         if (filter->index < E1000_MAX_FHFT)
4000                 reg_off = E1000_FHFT(filter->index);
4001         else
4002                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
4003
4004         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4005                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4006
4007         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4008                 (~(E1000_WUFC_FLX0 << filter->index)));
4009
4010         filter_info->flex_mask &= ~(1 << filter->index);
4011         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
4012         rte_free(filter);
4013 }
4014
4015 int
4016 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
4017                         struct rte_eth_flex_filter *filter,
4018                         bool add)
4019 {
4020         struct e1000_filter_info *filter_info =
4021                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4022         struct e1000_flex_filter *flex_filter, *it;
4023         uint32_t mask;
4024         uint8_t shift, i;
4025
4026         flex_filter = rte_zmalloc("e1000_flex_filter",
4027                         sizeof(struct e1000_flex_filter), 0);
4028         if (flex_filter == NULL)
4029                 return -ENOMEM;
4030
4031         flex_filter->filter_info.len = filter->len;
4032         flex_filter->filter_info.priority = filter->priority;
4033         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4034         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4035                 mask = 0;
4036                 /* reverse bits in flex filter's mask*/
4037                 for (shift = 0; shift < CHAR_BIT; shift++) {
4038                         if (filter->mask[i] & (0x01 << shift))
4039                                 mask |= (0x80 >> shift);
4040                 }
4041                 flex_filter->filter_info.mask[i] = mask;
4042         }
4043
4044         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4045                                 &flex_filter->filter_info);
4046         if (it == NULL && !add) {
4047                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4048                 rte_free(flex_filter);
4049                 return -ENOENT;
4050         }
4051         if (it != NULL && add) {
4052                 PMD_DRV_LOG(ERR, "filter exists.");
4053                 rte_free(flex_filter);
4054                 return -EEXIST;
4055         }
4056
4057         if (add) {
4058                 flex_filter->queue = filter->queue;
4059                 /*
4060                  * look for an unused flex filter index
4061                  * and insert the filter into the list.
4062                  */
4063                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4064                         if (!(filter_info->flex_mask & (1 << i))) {
4065                                 filter_info->flex_mask |= 1 << i;
4066                                 flex_filter->index = i;
4067                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4068                                         flex_filter,
4069                                         entries);
4070                                 break;
4071                         }
4072                 }
4073                 if (i >= E1000_MAX_FLEX_FILTERS) {
4074                         PMD_DRV_LOG(ERR, "flex filters are full.");
4075                         rte_free(flex_filter);
4076                         return -ENOSYS;
4077                 }
4078
4079                 igb_inject_flex_filter(dev, flex_filter);
4080
4081         } else {
4082                 igb_remove_flex_filter(dev, it);
4083                 rte_free(flex_filter);
4084         }
4085
4086         return 0;
4087 }
4088
4089 static int
4090 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4091                         struct rte_eth_flex_filter *filter)
4092 {
4093         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4094         struct e1000_filter_info *filter_info =
4095                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4096         struct e1000_flex_filter flex_filter, *it;
4097         uint32_t wufc, queueing, wufc_en = 0;
4098
4099         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4100         flex_filter.filter_info.len = filter->len;
4101         flex_filter.filter_info.priority = filter->priority;
4102         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4103         memcpy(flex_filter.filter_info.mask, filter->mask,
4104                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4105
4106         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4107                                 &flex_filter.filter_info);
4108         if (it == NULL) {
4109                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4110                 return -ENOENT;
4111         }
4112
4113         wufc = E1000_READ_REG(hw, E1000_WUFC);
4114         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4115
4116         if ((wufc & wufc_en) == wufc_en) {
4117                 uint32_t reg_off = 0;
4118                 if (it->index < E1000_MAX_FHFT)
4119                         reg_off = E1000_FHFT(it->index);
4120                 else
4121                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4122
4123                 queueing = E1000_READ_REG(hw,
4124                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4125                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4126                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4127                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4128                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4129                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4130                 return 0;
4131         }
4132         return -ENOENT;
4133 }
4134
4135 static int
4136 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4137                         enum rte_filter_op filter_op,
4138                         void *arg)
4139 {
4140         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         struct rte_eth_flex_filter *filter;
4142         int ret = 0;
4143
4144         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4145
4146         if (filter_op == RTE_ETH_FILTER_NOP)
4147                 return ret;
4148
4149         if (arg == NULL) {
4150                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4151                             filter_op);
4152                 return -EINVAL;
4153         }
4154
4155         filter = (struct rte_eth_flex_filter *)arg;
4156         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4157             || filter->len % sizeof(uint64_t) != 0) {
4158                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4159                 return -EINVAL;
4160         }
4161         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4162                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4163                 return -EINVAL;
4164         }
4165
4166         switch (filter_op) {
4167         case RTE_ETH_FILTER_ADD:
4168                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4169                 break;
4170         case RTE_ETH_FILTER_DELETE:
4171                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4172                 break;
4173         case RTE_ETH_FILTER_GET:
4174                 ret = eth_igb_get_flex_filter(dev, filter);
4175                 break;
4176         default:
4177                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4178                 ret = -EINVAL;
4179                 break;
4180         }
4181
4182         return ret;
4183 }
4184
4185 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4186 static inline int
4187 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4188                         struct e1000_5tuple_filter_info *filter_info)
4189 {
4190         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4191                 return -EINVAL;
4192         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4193                 return -EINVAL;  /* filter index is out of range. */
4194         if (filter->tcp_flags > TCP_FLAG_ALL)
4195                 return -EINVAL;  /* flags is invalid. */
4196
4197         switch (filter->dst_ip_mask) {
4198         case UINT32_MAX:
4199                 filter_info->dst_ip_mask = 0;
4200                 filter_info->dst_ip = filter->dst_ip;
4201                 break;
4202         case 0:
4203                 filter_info->dst_ip_mask = 1;
4204                 break;
4205         default:
4206                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4207                 return -EINVAL;
4208         }
4209
4210         switch (filter->src_ip_mask) {
4211         case UINT32_MAX:
4212                 filter_info->src_ip_mask = 0;
4213                 filter_info->src_ip = filter->src_ip;
4214                 break;
4215         case 0:
4216                 filter_info->src_ip_mask = 1;
4217                 break;
4218         default:
4219                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4220                 return -EINVAL;
4221         }
4222
4223         switch (filter->dst_port_mask) {
4224         case UINT16_MAX:
4225                 filter_info->dst_port_mask = 0;
4226                 filter_info->dst_port = filter->dst_port;
4227                 break;
4228         case 0:
4229                 filter_info->dst_port_mask = 1;
4230                 break;
4231         default:
4232                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4233                 return -EINVAL;
4234         }
4235
4236         switch (filter->src_port_mask) {
4237         case UINT16_MAX:
4238                 filter_info->src_port_mask = 0;
4239                 filter_info->src_port = filter->src_port;
4240                 break;
4241         case 0:
4242                 filter_info->src_port_mask = 1;
4243                 break;
4244         default:
4245                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4246                 return -EINVAL;
4247         }
4248
4249         switch (filter->proto_mask) {
4250         case UINT8_MAX:
4251                 filter_info->proto_mask = 0;
4252                 filter_info->proto = filter->proto;
4253                 break;
4254         case 0:
4255                 filter_info->proto_mask = 1;
4256                 break;
4257         default:
4258                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4259                 return -EINVAL;
4260         }
4261
4262         filter_info->priority = (uint8_t)filter->priority;
4263         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4264                 filter_info->tcp_flags = filter->tcp_flags;
4265         else
4266                 filter_info->tcp_flags = 0;
4267
4268         return 0;
4269 }
4270
4271 static inline struct e1000_5tuple_filter *
4272 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4273                         struct e1000_5tuple_filter_info *key)
4274 {
4275         struct e1000_5tuple_filter *it;
4276
4277         TAILQ_FOREACH(it, filter_list, entries) {
4278                 if (memcmp(key, &it->filter_info,
4279                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4280                         return it;
4281                 }
4282         }
4283         return NULL;
4284 }
4285
4286 /* inject a igb 5-tuple filter to HW */
4287 static inline void
4288 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4289                            struct e1000_5tuple_filter *filter)
4290 {
4291         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4292         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4293         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4294         uint8_t i;
4295
4296         i = filter->index;
4297         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4298         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4299                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4300         if (filter->filter_info.dst_ip_mask == 0)
4301                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4302         if (filter->filter_info.src_port_mask == 0)
4303                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4304         if (filter->filter_info.proto_mask == 0)
4305                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4306         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4307                 E1000_FTQF_QUEUE_MASK;
4308         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4309         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4310         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4311         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4312
4313         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4314         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4315
4316         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4317         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4318                 imir |= E1000_IMIR_PORT_BP;
4319         else
4320                 imir &= ~E1000_IMIR_PORT_BP;
4321         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4322
4323         /* tcp flags bits setting. */
4324         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4325                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4326                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4327                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4328                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4329                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4330                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4331                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4332                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4333                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4334                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4335                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4336                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4337         } else {
4338                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4339         }
4340         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4341         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4342 }
4343
4344 /*
4345  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4346  *
4347  * @param
4348  * dev: Pointer to struct rte_eth_dev.
4349  * ntuple_filter: ponter to the filter that will be added.
4350  *
4351  * @return
4352  *    - On success, zero.
4353  *    - On failure, a negative value.
4354  */
4355 static int
4356 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4357                         struct rte_eth_ntuple_filter *ntuple_filter)
4358 {
4359         struct e1000_filter_info *filter_info =
4360                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4361         struct e1000_5tuple_filter *filter;
4362         uint8_t i;
4363         int ret;
4364
4365         filter = rte_zmalloc("e1000_5tuple_filter",
4366                         sizeof(struct e1000_5tuple_filter), 0);
4367         if (filter == NULL)
4368                 return -ENOMEM;
4369
4370         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4371                                             &filter->filter_info);
4372         if (ret < 0) {
4373                 rte_free(filter);
4374                 return ret;
4375         }
4376
4377         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4378                                          &filter->filter_info) != NULL) {
4379                 PMD_DRV_LOG(ERR, "filter exists.");
4380                 rte_free(filter);
4381                 return -EEXIST;
4382         }
4383         filter->queue = ntuple_filter->queue;
4384
4385         /*
4386          * look for an unused 5tuple filter index,
4387          * and insert the filter to list.
4388          */
4389         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4390                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4391                         filter_info->fivetuple_mask |= 1 << i;
4392                         filter->index = i;
4393                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4394                                           filter,
4395                                           entries);
4396                         break;
4397                 }
4398         }
4399         if (i >= E1000_MAX_FTQF_FILTERS) {
4400                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4401                 rte_free(filter);
4402                 return -ENOSYS;
4403         }
4404
4405         igb_inject_5tuple_filter_82576(dev, filter);
4406         return 0;
4407 }
4408
4409 int
4410 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4411                                 struct e1000_5tuple_filter *filter)
4412 {
4413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         struct e1000_filter_info *filter_info =
4415                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4416
4417         filter_info->fivetuple_mask &= ~(1 << filter->index);
4418         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4419         rte_free(filter);
4420
4421         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4422                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4423         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4424         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4425         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4426         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4427         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4428         return 0;
4429 }
4430
4431 /*
4432  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4433  *
4434  * @param
4435  * dev: Pointer to struct rte_eth_dev.
4436  * ntuple_filter: ponter to the filter that will be removed.
4437  *
4438  * @return
4439  *    - On success, zero.
4440  *    - On failure, a negative value.
4441  */
4442 static int
4443 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4444                                 struct rte_eth_ntuple_filter *ntuple_filter)
4445 {
4446         struct e1000_filter_info *filter_info =
4447                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4448         struct e1000_5tuple_filter_info filter_5tuple;
4449         struct e1000_5tuple_filter *filter;
4450         int ret;
4451
4452         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4453         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4454                                             &filter_5tuple);
4455         if (ret < 0)
4456                 return ret;
4457
4458         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4459                                          &filter_5tuple);
4460         if (filter == NULL) {
4461                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4462                 return -ENOENT;
4463         }
4464
4465         igb_delete_5tuple_filter_82576(dev, filter);
4466
4467         return 0;
4468 }
4469
4470 static int
4471 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4472 {
4473         uint32_t rctl;
4474         struct e1000_hw *hw;
4475         struct rte_eth_dev_info dev_info;
4476         uint32_t frame_size = mtu + E1000_ETH_OVERHEAD;
4477
4478         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479
4480 #ifdef RTE_LIBRTE_82571_SUPPORT
4481         /* XXX: not bigger than max_rx_pktlen */
4482         if (hw->mac.type == e1000_82571)
4483                 return -ENOTSUP;
4484 #endif
4485         eth_igb_infos_get(dev, &dev_info);
4486
4487         /* check that mtu is within the allowed range */
4488         if ((mtu < ETHER_MIN_MTU) ||
4489             (frame_size > dev_info.max_rx_pktlen))
4490                 return -EINVAL;
4491
4492         /* refuse mtu that requires the support of scattered packets when this
4493          * feature has not been enabled before. */
4494         if (!dev->data->scattered_rx &&
4495             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4496                 return -EINVAL;
4497
4498         rctl = E1000_READ_REG(hw, E1000_RCTL);
4499
4500         /* switch to jumbo mode if needed */
4501         if (frame_size > ETHER_MAX_LEN) {
4502                 dev->data->dev_conf.rxmode.offloads |=
4503                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4504                 rctl |= E1000_RCTL_LPE;
4505         } else {
4506                 dev->data->dev_conf.rxmode.offloads &=
4507                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4508                 rctl &= ~E1000_RCTL_LPE;
4509         }
4510         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4511
4512         /* update max frame size */
4513         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4514
4515         E1000_WRITE_REG(hw, E1000_RLPML,
4516                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4517
4518         return 0;
4519 }
4520
4521 /*
4522  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4523  *
4524  * @param
4525  * dev: Pointer to struct rte_eth_dev.
4526  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4527  * add: if true, add filter, if false, remove filter
4528  *
4529  * @return
4530  *    - On success, zero.
4531  *    - On failure, a negative value.
4532  */
4533 int
4534 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4535                         struct rte_eth_ntuple_filter *ntuple_filter,
4536                         bool add)
4537 {
4538         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4539         int ret;
4540
4541         switch (ntuple_filter->flags) {
4542         case RTE_5TUPLE_FLAGS:
4543         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4544                 if (hw->mac.type != e1000_82576)
4545                         return -ENOTSUP;
4546                 if (add)
4547                         ret = igb_add_5tuple_filter_82576(dev,
4548                                                           ntuple_filter);
4549                 else
4550                         ret = igb_remove_5tuple_filter_82576(dev,
4551                                                              ntuple_filter);
4552                 break;
4553         case RTE_2TUPLE_FLAGS:
4554         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4555                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4556                         hw->mac.type != e1000_i210 &&
4557                         hw->mac.type != e1000_i211)
4558                         return -ENOTSUP;
4559                 if (add)
4560                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4561                 else
4562                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4563                 break;
4564         default:
4565                 ret = -EINVAL;
4566                 break;
4567         }
4568
4569         return ret;
4570 }
4571
4572 /*
4573  * igb_get_ntuple_filter - get a ntuple filter
4574  *
4575  * @param
4576  * dev: Pointer to struct rte_eth_dev.
4577  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4578  *
4579  * @return
4580  *    - On success, zero.
4581  *    - On failure, a negative value.
4582  */
4583 static int
4584 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4585                         struct rte_eth_ntuple_filter *ntuple_filter)
4586 {
4587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588         struct e1000_filter_info *filter_info =
4589                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4590         struct e1000_5tuple_filter_info filter_5tuple;
4591         struct e1000_2tuple_filter_info filter_2tuple;
4592         struct e1000_5tuple_filter *p_5tuple_filter;
4593         struct e1000_2tuple_filter *p_2tuple_filter;
4594         int ret;
4595
4596         switch (ntuple_filter->flags) {
4597         case RTE_5TUPLE_FLAGS:
4598         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4599                 if (hw->mac.type != e1000_82576)
4600                         return -ENOTSUP;
4601                 memset(&filter_5tuple,
4602                         0,
4603                         sizeof(struct e1000_5tuple_filter_info));
4604                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4605                                                     &filter_5tuple);
4606                 if (ret < 0)
4607                         return ret;
4608                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4609                                         &filter_info->fivetuple_list,
4610                                         &filter_5tuple);
4611                 if (p_5tuple_filter == NULL) {
4612                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4613                         return -ENOENT;
4614                 }
4615                 ntuple_filter->queue = p_5tuple_filter->queue;
4616                 break;
4617         case RTE_2TUPLE_FLAGS:
4618         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4619                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4620                         return -ENOTSUP;
4621                 memset(&filter_2tuple,
4622                         0,
4623                         sizeof(struct e1000_2tuple_filter_info));
4624                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4625                 if (ret < 0)
4626                         return ret;
4627                 p_2tuple_filter = igb_2tuple_filter_lookup(
4628                                         &filter_info->twotuple_list,
4629                                         &filter_2tuple);
4630                 if (p_2tuple_filter == NULL) {
4631                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4632                         return -ENOENT;
4633                 }
4634                 ntuple_filter->queue = p_2tuple_filter->queue;
4635                 break;
4636         default:
4637                 ret = -EINVAL;
4638                 break;
4639         }
4640
4641         return 0;
4642 }
4643
4644 /*
4645  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4646  * @dev: pointer to rte_eth_dev structure
4647  * @filter_op:operation will be taken.
4648  * @arg: a pointer to specific structure corresponding to the filter_op
4649  */
4650 static int
4651 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4652                                 enum rte_filter_op filter_op,
4653                                 void *arg)
4654 {
4655         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656         int ret;
4657
4658         MAC_TYPE_FILTER_SUP(hw->mac.type);
4659
4660         if (filter_op == RTE_ETH_FILTER_NOP)
4661                 return 0;
4662
4663         if (arg == NULL) {
4664                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4665                             filter_op);
4666                 return -EINVAL;
4667         }
4668
4669         switch (filter_op) {
4670         case RTE_ETH_FILTER_ADD:
4671                 ret = igb_add_del_ntuple_filter(dev,
4672                         (struct rte_eth_ntuple_filter *)arg,
4673                         TRUE);
4674                 break;
4675         case RTE_ETH_FILTER_DELETE:
4676                 ret = igb_add_del_ntuple_filter(dev,
4677                         (struct rte_eth_ntuple_filter *)arg,
4678                         FALSE);
4679                 break;
4680         case RTE_ETH_FILTER_GET:
4681                 ret = igb_get_ntuple_filter(dev,
4682                         (struct rte_eth_ntuple_filter *)arg);
4683                 break;
4684         default:
4685                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4686                 ret = -EINVAL;
4687                 break;
4688         }
4689         return ret;
4690 }
4691
4692 static inline int
4693 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4694                         uint16_t ethertype)
4695 {
4696         int i;
4697
4698         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4699                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4700                     (filter_info->ethertype_mask & (1 << i)))
4701                         return i;
4702         }
4703         return -1;
4704 }
4705
4706 static inline int
4707 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4708                         uint16_t ethertype, uint32_t etqf)
4709 {
4710         int i;
4711
4712         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4713                 if (!(filter_info->ethertype_mask & (1 << i))) {
4714                         filter_info->ethertype_mask |= 1 << i;
4715                         filter_info->ethertype_filters[i].ethertype = ethertype;
4716                         filter_info->ethertype_filters[i].etqf = etqf;
4717                         return i;
4718                 }
4719         }
4720         return -1;
4721 }
4722
4723 int
4724 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4725                         uint8_t idx)
4726 {
4727         if (idx >= E1000_MAX_ETQF_FILTERS)
4728                 return -1;
4729         filter_info->ethertype_mask &= ~(1 << idx);
4730         filter_info->ethertype_filters[idx].ethertype = 0;
4731         filter_info->ethertype_filters[idx].etqf = 0;
4732         return idx;
4733 }
4734
4735
4736 int
4737 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4738                         struct rte_eth_ethertype_filter *filter,
4739                         bool add)
4740 {
4741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         struct e1000_filter_info *filter_info =
4743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4744         uint32_t etqf = 0;
4745         int ret;
4746
4747         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4748                 filter->ether_type == ETHER_TYPE_IPv6) {
4749                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4750                         " ethertype filter.", filter->ether_type);
4751                 return -EINVAL;
4752         }
4753
4754         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4755                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4756                 return -EINVAL;
4757         }
4758         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4759                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4760                 return -EINVAL;
4761         }
4762
4763         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4764         if (ret >= 0 && add) {
4765                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4766                             filter->ether_type);
4767                 return -EEXIST;
4768         }
4769         if (ret < 0 && !add) {
4770                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4771                             filter->ether_type);
4772                 return -ENOENT;
4773         }
4774
4775         if (add) {
4776                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4777                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4778                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4779                 ret = igb_ethertype_filter_insert(filter_info,
4780                                 filter->ether_type, etqf);
4781                 if (ret < 0) {
4782                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4783                         return -ENOSYS;
4784                 }
4785         } else {
4786                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4787                 if (ret < 0)
4788                         return -ENOSYS;
4789         }
4790         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4791         E1000_WRITE_FLUSH(hw);
4792
4793         return 0;
4794 }
4795
4796 static int
4797 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4798                         struct rte_eth_ethertype_filter *filter)
4799 {
4800         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801         struct e1000_filter_info *filter_info =
4802                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4803         uint32_t etqf;
4804         int ret;
4805
4806         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4807         if (ret < 0) {
4808                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4809                             filter->ether_type);
4810                 return -ENOENT;
4811         }
4812
4813         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4814         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4815                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4816                 filter->flags = 0;
4817                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4818                                 E1000_ETQF_QUEUE_SHIFT;
4819                 return 0;
4820         }
4821
4822         return -ENOENT;
4823 }
4824
4825 /*
4826  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4827  * @dev: pointer to rte_eth_dev structure
4828  * @filter_op:operation will be taken.
4829  * @arg: a pointer to specific structure corresponding to the filter_op
4830  */
4831 static int
4832 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4833                                 enum rte_filter_op filter_op,
4834                                 void *arg)
4835 {
4836         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837         int ret;
4838
4839         MAC_TYPE_FILTER_SUP(hw->mac.type);
4840
4841         if (filter_op == RTE_ETH_FILTER_NOP)
4842                 return 0;
4843
4844         if (arg == NULL) {
4845                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4846                             filter_op);
4847                 return -EINVAL;
4848         }
4849
4850         switch (filter_op) {
4851         case RTE_ETH_FILTER_ADD:
4852                 ret = igb_add_del_ethertype_filter(dev,
4853                         (struct rte_eth_ethertype_filter *)arg,
4854                         TRUE);
4855                 break;
4856         case RTE_ETH_FILTER_DELETE:
4857                 ret = igb_add_del_ethertype_filter(dev,
4858                         (struct rte_eth_ethertype_filter *)arg,
4859                         FALSE);
4860                 break;
4861         case RTE_ETH_FILTER_GET:
4862                 ret = igb_get_ethertype_filter(dev,
4863                         (struct rte_eth_ethertype_filter *)arg);
4864                 break;
4865         default:
4866                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4867                 ret = -EINVAL;
4868                 break;
4869         }
4870         return ret;
4871 }
4872
4873 static int
4874 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4875                      enum rte_filter_type filter_type,
4876                      enum rte_filter_op filter_op,
4877                      void *arg)
4878 {
4879         int ret = 0;
4880
4881         switch (filter_type) {
4882         case RTE_ETH_FILTER_NTUPLE:
4883                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4884                 break;
4885         case RTE_ETH_FILTER_ETHERTYPE:
4886                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4887                 break;
4888         case RTE_ETH_FILTER_SYN:
4889                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4890                 break;
4891         case RTE_ETH_FILTER_FLEXIBLE:
4892                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4893                 break;
4894         case RTE_ETH_FILTER_GENERIC:
4895                 if (filter_op != RTE_ETH_FILTER_GET)
4896                         return -EINVAL;
4897                 *(const void **)arg = &igb_flow_ops;
4898                 break;
4899         default:
4900                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4901                                                         filter_type);
4902                 break;
4903         }
4904
4905         return ret;
4906 }
4907
4908 static int
4909 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4910                          struct rte_ether_addr *mc_addr_set,
4911                          uint32_t nb_mc_addr)
4912 {
4913         struct e1000_hw *hw;
4914
4915         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4916         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4917         return 0;
4918 }
4919
4920 static uint64_t
4921 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4922 {
4923         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4924         uint64_t systime_cycles;
4925
4926         switch (hw->mac.type) {
4927         case e1000_i210:
4928         case e1000_i211:
4929                 /*
4930                  * Need to read System Time Residue Register to be able
4931                  * to read the other two registers.
4932                  */
4933                 E1000_READ_REG(hw, E1000_SYSTIMR);
4934                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4935                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4936                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4937                                 * NSEC_PER_SEC;
4938                 break;
4939         case e1000_82580:
4940         case e1000_i350:
4941         case e1000_i354:
4942                 /*
4943                  * Need to read System Time Residue Register to be able
4944                  * to read the other two registers.
4945                  */
4946                 E1000_READ_REG(hw, E1000_SYSTIMR);
4947                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4948                 /* Only the 8 LSB are valid. */
4949                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4950                                 & 0xff) << 32;
4951                 break;
4952         default:
4953                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4954                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4955                                 << 32;
4956                 break;
4957         }
4958
4959         return systime_cycles;
4960 }
4961
4962 static uint64_t
4963 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4964 {
4965         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966         uint64_t rx_tstamp_cycles;
4967
4968         switch (hw->mac.type) {
4969         case e1000_i210:
4970         case e1000_i211:
4971                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4972                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4973                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4974                                 * NSEC_PER_SEC;
4975                 break;
4976         case e1000_82580:
4977         case e1000_i350:
4978         case e1000_i354:
4979                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4980                 /* Only the 8 LSB are valid. */
4981                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4982                                 & 0xff) << 32;
4983                 break;
4984         default:
4985                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4986                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4987                                 << 32;
4988                 break;
4989         }
4990
4991         return rx_tstamp_cycles;
4992 }
4993
4994 static uint64_t
4995 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4996 {
4997         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998         uint64_t tx_tstamp_cycles;
4999
5000         switch (hw->mac.type) {
5001         case e1000_i210:
5002         case e1000_i211:
5003                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5004                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5005                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5006                                 * NSEC_PER_SEC;
5007                 break;
5008         case e1000_82580:
5009         case e1000_i350:
5010         case e1000_i354:
5011                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5012                 /* Only the 8 LSB are valid. */
5013                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
5014                                 & 0xff) << 32;
5015                 break;
5016         default:
5017                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
5018                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
5019                                 << 32;
5020                 break;
5021         }
5022
5023         return tx_tstamp_cycles;
5024 }
5025
5026 static void
5027 igb_start_timecounters(struct rte_eth_dev *dev)
5028 {
5029         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030         struct e1000_adapter *adapter =
5031                 (struct e1000_adapter *)dev->data->dev_private;
5032         uint32_t incval = 1;
5033         uint32_t shift = 0;
5034         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5035
5036         switch (hw->mac.type) {
5037         case e1000_82580:
5038         case e1000_i350:
5039         case e1000_i354:
5040                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5041                 mask = (1ULL << 40) - 1;
5042                 /* fall-through */
5043         case e1000_i210:
5044         case e1000_i211:
5045                 /*
5046                  * Start incrementing the register
5047                  * used to timestamp PTP packets.
5048                  */
5049                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5050                 break;
5051         case e1000_82576:
5052                 incval = E1000_INCVALUE_82576;
5053                 shift = IGB_82576_TSYNC_SHIFT;
5054                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5055                                 E1000_INCPERIOD_82576 | incval);
5056                 break;
5057         default:
5058                 /* Not supported */
5059                 return;
5060         }
5061
5062         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5063         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5064         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5065
5066         adapter->systime_tc.cc_mask = mask;
5067         adapter->systime_tc.cc_shift = shift;
5068         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5069
5070         adapter->rx_tstamp_tc.cc_mask = mask;
5071         adapter->rx_tstamp_tc.cc_shift = shift;
5072         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5073
5074         adapter->tx_tstamp_tc.cc_mask = mask;
5075         adapter->tx_tstamp_tc.cc_shift = shift;
5076         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5077 }
5078
5079 static int
5080 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5081 {
5082         struct e1000_adapter *adapter =
5083                         (struct e1000_adapter *)dev->data->dev_private;
5084
5085         adapter->systime_tc.nsec += delta;
5086         adapter->rx_tstamp_tc.nsec += delta;
5087         adapter->tx_tstamp_tc.nsec += delta;
5088
5089         return 0;
5090 }
5091
5092 static int
5093 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5094 {
5095         uint64_t ns;
5096         struct e1000_adapter *adapter =
5097                         (struct e1000_adapter *)dev->data->dev_private;
5098
5099         ns = rte_timespec_to_ns(ts);
5100
5101         /* Set the timecounters to a new value. */
5102         adapter->systime_tc.nsec = ns;
5103         adapter->rx_tstamp_tc.nsec = ns;
5104         adapter->tx_tstamp_tc.nsec = ns;
5105
5106         return 0;
5107 }
5108
5109 static int
5110 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5111 {
5112         uint64_t ns, systime_cycles;
5113         struct e1000_adapter *adapter =
5114                         (struct e1000_adapter *)dev->data->dev_private;
5115
5116         systime_cycles = igb_read_systime_cyclecounter(dev);
5117         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5118         *ts = rte_ns_to_timespec(ns);
5119
5120         return 0;
5121 }
5122
5123 static int
5124 igb_timesync_enable(struct rte_eth_dev *dev)
5125 {
5126         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5127         uint32_t tsync_ctl;
5128         uint32_t tsauxc;
5129
5130         /* Stop the timesync system time. */
5131         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5132         /* Reset the timesync system time value. */
5133         switch (hw->mac.type) {
5134         case e1000_82580:
5135         case e1000_i350:
5136         case e1000_i354:
5137         case e1000_i210:
5138         case e1000_i211:
5139                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5140                 /* fall-through */
5141         case e1000_82576:
5142                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5143                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5144                 break;
5145         default:
5146                 /* Not supported. */
5147                 return -ENOTSUP;
5148         }
5149
5150         /* Enable system time for it isn't on by default. */
5151         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5152         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5153         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5154
5155         igb_start_timecounters(dev);
5156
5157         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5158         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5159                         (ETHER_TYPE_1588 |
5160                          E1000_ETQF_FILTER_ENABLE |
5161                          E1000_ETQF_1588));
5162
5163         /* Enable timestamping of received PTP packets. */
5164         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5165         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5166         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5167
5168         /* Enable Timestamping of transmitted PTP packets. */
5169         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5170         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5171         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5172
5173         return 0;
5174 }
5175
5176 static int
5177 igb_timesync_disable(struct rte_eth_dev *dev)
5178 {
5179         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180         uint32_t tsync_ctl;
5181
5182         /* Disable timestamping of transmitted PTP packets. */
5183         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5184         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5185         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5186
5187         /* Disable timestamping of received PTP packets. */
5188         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5189         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5190         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5191
5192         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5193         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5194
5195         /* Stop incrementating the System Time registers. */
5196         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5197
5198         return 0;
5199 }
5200
5201 static int
5202 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5203                                struct timespec *timestamp,
5204                                uint32_t flags __rte_unused)
5205 {
5206         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207         struct e1000_adapter *adapter =
5208                         (struct e1000_adapter *)dev->data->dev_private;
5209         uint32_t tsync_rxctl;
5210         uint64_t rx_tstamp_cycles;
5211         uint64_t ns;
5212
5213         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5214         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5215                 return -EINVAL;
5216
5217         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5218         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5219         *timestamp = rte_ns_to_timespec(ns);
5220
5221         return  0;
5222 }
5223
5224 static int
5225 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5226                                struct timespec *timestamp)
5227 {
5228         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229         struct e1000_adapter *adapter =
5230                         (struct e1000_adapter *)dev->data->dev_private;
5231         uint32_t tsync_txctl;
5232         uint64_t tx_tstamp_cycles;
5233         uint64_t ns;
5234
5235         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5236         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5237                 return -EINVAL;
5238
5239         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5240         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5241         *timestamp = rte_ns_to_timespec(ns);
5242
5243         return  0;
5244 }
5245
5246 static int
5247 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5248 {
5249         int count = 0;
5250         int g_ind = 0;
5251         const struct reg_info *reg_group;
5252
5253         while ((reg_group = igb_regs[g_ind++]))
5254                 count += igb_reg_group_count(reg_group);
5255
5256         return count;
5257 }
5258
5259 static int
5260 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5261 {
5262         int count = 0;
5263         int g_ind = 0;
5264         const struct reg_info *reg_group;
5265
5266         while ((reg_group = igbvf_regs[g_ind++]))
5267                 count += igb_reg_group_count(reg_group);
5268
5269         return count;
5270 }
5271
5272 static int
5273 eth_igb_get_regs(struct rte_eth_dev *dev,
5274         struct rte_dev_reg_info *regs)
5275 {
5276         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277         uint32_t *data = regs->data;
5278         int g_ind = 0;
5279         int count = 0;
5280         const struct reg_info *reg_group;
5281
5282         if (data == NULL) {
5283                 regs->length = eth_igb_get_reg_length(dev);
5284                 regs->width = sizeof(uint32_t);
5285                 return 0;
5286         }
5287
5288         /* Support only full register dump */
5289         if ((regs->length == 0) ||
5290             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5291                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5292                         hw->device_id;
5293                 while ((reg_group = igb_regs[g_ind++]))
5294                         count += igb_read_regs_group(dev, &data[count],
5295                                                         reg_group);
5296                 return 0;
5297         }
5298
5299         return -ENOTSUP;
5300 }
5301
5302 static int
5303 igbvf_get_regs(struct rte_eth_dev *dev,
5304         struct rte_dev_reg_info *regs)
5305 {
5306         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307         uint32_t *data = regs->data;
5308         int g_ind = 0;
5309         int count = 0;
5310         const struct reg_info *reg_group;
5311
5312         if (data == NULL) {
5313                 regs->length = igbvf_get_reg_length(dev);
5314                 regs->width = sizeof(uint32_t);
5315                 return 0;
5316         }
5317
5318         /* Support only full register dump */
5319         if ((regs->length == 0) ||
5320             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5321                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5322                         hw->device_id;
5323                 while ((reg_group = igbvf_regs[g_ind++]))
5324                         count += igb_read_regs_group(dev, &data[count],
5325                                                         reg_group);
5326                 return 0;
5327         }
5328
5329         return -ENOTSUP;
5330 }
5331
5332 static int
5333 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5334 {
5335         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5336
5337         /* Return unit is byte count */
5338         return hw->nvm.word_size * 2;
5339 }
5340
5341 static int
5342 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5343         struct rte_dev_eeprom_info *in_eeprom)
5344 {
5345         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         struct e1000_nvm_info *nvm = &hw->nvm;
5347         uint16_t *data = in_eeprom->data;
5348         int first, length;
5349
5350         first = in_eeprom->offset >> 1;
5351         length = in_eeprom->length >> 1;
5352         if ((first >= hw->nvm.word_size) ||
5353             ((first + length) >= hw->nvm.word_size))
5354                 return -EINVAL;
5355
5356         in_eeprom->magic = hw->vendor_id |
5357                 ((uint32_t)hw->device_id << 16);
5358
5359         if ((nvm->ops.read) == NULL)
5360                 return -ENOTSUP;
5361
5362         return nvm->ops.read(hw, first, length, data);
5363 }
5364
5365 static int
5366 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5367         struct rte_dev_eeprom_info *in_eeprom)
5368 {
5369         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5370         struct e1000_nvm_info *nvm = &hw->nvm;
5371         uint16_t *data = in_eeprom->data;
5372         int first, length;
5373
5374         first = in_eeprom->offset >> 1;
5375         length = in_eeprom->length >> 1;
5376         if ((first >= hw->nvm.word_size) ||
5377             ((first + length) >= hw->nvm.word_size))
5378                 return -EINVAL;
5379
5380         in_eeprom->magic = (uint32_t)hw->vendor_id |
5381                 ((uint32_t)hw->device_id << 16);
5382
5383         if ((nvm->ops.write) == NULL)
5384                 return -ENOTSUP;
5385         return nvm->ops.write(hw,  first, length, data);
5386 }
5387
5388 static int
5389 eth_igb_get_module_info(struct rte_eth_dev *dev,
5390                         struct rte_eth_dev_module_info *modinfo)
5391 {
5392         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5393
5394         uint32_t status = 0;
5395         uint16_t sff8472_rev, addr_mode;
5396         bool page_swap = false;
5397
5398         if (hw->phy.media_type == e1000_media_type_copper ||
5399             hw->phy.media_type == e1000_media_type_unknown)
5400                 return -EOPNOTSUPP;
5401
5402         /* Check whether we support SFF-8472 or not */
5403         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5404         if (status)
5405                 return -EIO;
5406
5407         /* addressing mode is not supported */
5408         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5409         if (status)
5410                 return -EIO;
5411
5412         /* addressing mode is not supported */
5413         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5414                 PMD_DRV_LOG(ERR,
5415                             "Address change required to access page 0xA2, "
5416                             "but not supported. Please report the module "
5417                             "type to the driver maintainers.\n");
5418                 page_swap = true;
5419         }
5420
5421         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5422                 /* We have an SFP, but it does not support SFF-8472 */
5423                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5424                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5425         } else {
5426                 /* We have an SFP which supports a revision of SFF-8472 */
5427                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5428                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5429         }
5430
5431         return 0;
5432 }
5433
5434 static int
5435 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5436                           struct rte_dev_eeprom_info *info)
5437 {
5438         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5439
5440         uint32_t status = 0;
5441         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5442         u16 first_word, last_word;
5443         int i = 0;
5444
5445         if (info->length == 0)
5446                 return -EINVAL;
5447
5448         first_word = info->offset >> 1;
5449         last_word = (info->offset + info->length - 1) >> 1;
5450
5451         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5452         for (i = 0; i < last_word - first_word + 1; i++) {
5453                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5454                                                 &dataword[i]);
5455                 if (status) {
5456                         /* Error occurred while reading module */
5457                         return -EIO;
5458                 }
5459
5460                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5461         }
5462
5463         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5464
5465         return 0;
5466 }
5467
5468 static int
5469 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5470 {
5471         struct e1000_hw *hw =
5472                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5474         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5475         uint32_t vec = E1000_MISC_VEC_ID;
5476
5477         if (rte_intr_allow_others(intr_handle))
5478                 vec = E1000_RX_VEC_START;
5479
5480         uint32_t mask = 1 << (queue_id + vec);
5481
5482         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5483         E1000_WRITE_FLUSH(hw);
5484
5485         return 0;
5486 }
5487
5488 static int
5489 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5490 {
5491         struct e1000_hw *hw =
5492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5493         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5494         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5495         uint32_t vec = E1000_MISC_VEC_ID;
5496
5497         if (rte_intr_allow_others(intr_handle))
5498                 vec = E1000_RX_VEC_START;
5499
5500         uint32_t mask = 1 << (queue_id + vec);
5501         uint32_t regval;
5502
5503         regval = E1000_READ_REG(hw, E1000_EIMS);
5504         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5505         E1000_WRITE_FLUSH(hw);
5506
5507         rte_intr_enable(intr_handle);
5508
5509         return 0;
5510 }
5511
5512 static void
5513 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5514                    uint8_t index, uint8_t offset)
5515 {
5516         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5517
5518         /* clear bits */
5519         val &= ~((uint32_t)0xFF << offset);
5520
5521         /* write vector and valid bit */
5522         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5523
5524         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5525 }
5526
5527 static void
5528 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5529                            uint8_t queue, uint8_t msix_vector)
5530 {
5531         uint32_t tmp = 0;
5532
5533         if (hw->mac.type == e1000_82575) {
5534                 if (direction == 0)
5535                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5536                 else if (direction == 1)
5537                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5538                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5539         } else if (hw->mac.type == e1000_82576) {
5540                 if ((direction == 0) || (direction == 1))
5541                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5542                                            ((queue & 0x8) << 1) +
5543                                            8 * direction);
5544         } else if ((hw->mac.type == e1000_82580) ||
5545                         (hw->mac.type == e1000_i350) ||
5546                         (hw->mac.type == e1000_i354) ||
5547                         (hw->mac.type == e1000_i210) ||
5548                         (hw->mac.type == e1000_i211)) {
5549                 if ((direction == 0) || (direction == 1))
5550                         eth_igb_write_ivar(hw, msix_vector,
5551                                            queue >> 1,
5552                                            ((queue & 0x1) << 4) +
5553                                            8 * direction);
5554         }
5555 }
5556
5557 /* Sets up the hardware to generate MSI-X interrupts properly
5558  * @hw
5559  *  board private structure
5560  */
5561 static void
5562 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5563 {
5564         int queue_id;
5565         uint32_t tmpval, regval, intr_mask;
5566         struct e1000_hw *hw =
5567                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5568         uint32_t vec = E1000_MISC_VEC_ID;
5569         uint32_t base = E1000_MISC_VEC_ID;
5570         uint32_t misc_shift = 0;
5571         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5572         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5573
5574         /* won't configure msix register if no mapping is done
5575          * between intr vector and event fd
5576          */
5577         if (!rte_intr_dp_is_en(intr_handle))
5578                 return;
5579
5580         if (rte_intr_allow_others(intr_handle)) {
5581                 vec = base = E1000_RX_VEC_START;
5582                 misc_shift = 1;
5583         }
5584
5585         /* set interrupt vector for other causes */
5586         if (hw->mac.type == e1000_82575) {
5587                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5588                 /* enable MSI-X PBA support */
5589                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5590
5591                 /* Auto-Mask interrupts upon ICR read */
5592                 tmpval |= E1000_CTRL_EXT_EIAME;
5593                 tmpval |= E1000_CTRL_EXT_IRCA;
5594
5595                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5596
5597                 /* enable msix_other interrupt */
5598                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5599                 regval = E1000_READ_REG(hw, E1000_EIAC);
5600                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5601                 regval = E1000_READ_REG(hw, E1000_EIAM);
5602                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5603         } else if ((hw->mac.type == e1000_82576) ||
5604                         (hw->mac.type == e1000_82580) ||
5605                         (hw->mac.type == e1000_i350) ||
5606                         (hw->mac.type == e1000_i354) ||
5607                         (hw->mac.type == e1000_i210) ||
5608                         (hw->mac.type == e1000_i211)) {
5609                 /* turn on MSI-X capability first */
5610                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5611                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5612                                         E1000_GPIE_NSICR);
5613                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5614                         misc_shift;
5615
5616                 if (dev->data->dev_conf.intr_conf.lsc != 0)
5617                         intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5618
5619                 regval = E1000_READ_REG(hw, E1000_EIAC);
5620                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5621
5622                 /* enable msix_other interrupt */
5623                 regval = E1000_READ_REG(hw, E1000_EIMS);
5624                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5625                 tmpval = (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8;
5626                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5627         }
5628
5629         /* use EIAM to auto-mask when MSI-X interrupt
5630          * is asserted, this saves a register write for every interrupt
5631          */
5632         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5633                 misc_shift;
5634
5635         if (dev->data->dev_conf.intr_conf.lsc != 0)
5636                 intr_mask |= (1 << IGB_MSIX_OTHER_INTR_VEC);
5637
5638         regval = E1000_READ_REG(hw, E1000_EIAM);
5639         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5640
5641         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5642                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5643                 intr_handle->intr_vec[queue_id] = vec;
5644                 if (vec < base + intr_handle->nb_efd - 1)
5645                         vec++;
5646         }
5647
5648         E1000_WRITE_FLUSH(hw);
5649 }
5650
5651 /* restore n-tuple filter */
5652 static inline void
5653 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5654 {
5655         struct e1000_filter_info *filter_info =
5656                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5657         struct e1000_5tuple_filter *p_5tuple;
5658         struct e1000_2tuple_filter *p_2tuple;
5659
5660         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5661                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5662         }
5663
5664         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5665                 igb_inject_2uple_filter(dev, p_2tuple);
5666         }
5667 }
5668
5669 /* restore SYN filter */
5670 static inline void
5671 igb_syn_filter_restore(struct rte_eth_dev *dev)
5672 {
5673         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5674         struct e1000_filter_info *filter_info =
5675                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5676         uint32_t synqf;
5677
5678         synqf = filter_info->syn_info;
5679
5680         if (synqf & E1000_SYN_FILTER_ENABLE) {
5681                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5682                 E1000_WRITE_FLUSH(hw);
5683         }
5684 }
5685
5686 /* restore ethernet type filter */
5687 static inline void
5688 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5689 {
5690         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5691         struct e1000_filter_info *filter_info =
5692                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5693         int i;
5694
5695         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5696                 if (filter_info->ethertype_mask & (1 << i)) {
5697                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5698                                 filter_info->ethertype_filters[i].etqf);
5699                         E1000_WRITE_FLUSH(hw);
5700                 }
5701         }
5702 }
5703
5704 /* restore flex byte filter */
5705 static inline void
5706 igb_flex_filter_restore(struct rte_eth_dev *dev)
5707 {
5708         struct e1000_filter_info *filter_info =
5709                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5710         struct e1000_flex_filter *flex_filter;
5711
5712         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5713                 igb_inject_flex_filter(dev, flex_filter);
5714         }
5715 }
5716
5717 /* restore rss filter */
5718 static inline void
5719 igb_rss_filter_restore(struct rte_eth_dev *dev)
5720 {
5721         struct e1000_filter_info *filter_info =
5722                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5723
5724         if (filter_info->rss_info.conf.queue_num)
5725                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5726 }
5727
5728 /* restore all types filter */
5729 static int
5730 igb_filter_restore(struct rte_eth_dev *dev)
5731 {
5732         igb_ntuple_filter_restore(dev);
5733         igb_ethertype_filter_restore(dev);
5734         igb_syn_filter_restore(dev);
5735         igb_flex_filter_restore(dev);
5736         igb_rss_filter_restore(dev);
5737
5738         return 0;
5739 }
5740
5741 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5742 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5743 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5744 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5745 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5746 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");
5747
5748 /* see e1000_logs.c */
5749 RTE_INIT(e1000_init_log)
5750 {
5751         e1000_igb_init_log();
5752 }