drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  82 #define E1000_ETQF_FILTER_1588       3
  83 #define IGB_82576_TSYNC_SHIFT        16
  84 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  85 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  87
  88 static int  eth_igb_configure(struct rte_eth_dev *dev);
  89 static int  eth_igb_start(struct rte_eth_dev *dev);
  90 static void eth_igb_stop(struct rte_eth_dev *dev);
  91 static void eth_igb_close(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  96 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  99                                 struct rte_eth_stats *rte_stats);
 100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_xstats *xstats, unsigned n);
 102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 105                               struct rte_eth_dev_info *dev_info);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 117                                                         void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 129                                  enum rte_vlan_type vlan_type,
 130                                  uint16_t tpid_id);
 131 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 132
 133 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 139
 140 static int eth_igb_led_on(struct rte_eth_dev *dev);
 141 static int eth_igb_led_off(struct rte_eth_dev *dev);
 142
 143 static void igb_intr_disable(struct e1000_hw *hw);
 144 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 145 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 146                 struct ether_addr *mac_addr,
 147                 uint32_t index, uint32_t pool);
 148 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 149 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 150                 struct ether_addr *addr);
 151
 152 static void igbvf_intr_disable(struct e1000_hw *hw);
 153 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 154 static int igbvf_dev_start(struct rte_eth_dev *dev);
 155 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 156 static void igbvf_dev_close(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 158 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 160 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 161 static int eth_igbvf_link_update(struct e1000_hw *hw);
 162 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 163                                 struct rte_eth_stats *rte_stats);
 164 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_xstats *xstats, unsigned n);
 166 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 167 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 168                 uint16_t vlan_id, int on);
 169 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 170 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 171 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 172                 struct ether_addr *addr);
 173 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 174 static int igbvf_get_regs(struct rte_eth_dev *dev,
 175                 struct rte_dev_reg_info *regs);
 176
 177 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 178                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 179                                    uint16_t reta_size);
 180 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 181                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                   uint16_t reta_size);
 183
 184 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 185                         struct rte_eth_syn_filter *filter,
 186                         bool add);
 187 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 188                         struct rte_eth_syn_filter *filter);
 189 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 190                         enum rte_filter_op filter_op,
 191                         void *arg);
 192 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_ntuple_filter *ntuple_filter);
 194 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_flex_filter *filter,
 198                         bool add);
 199 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 200                         struct rte_eth_flex_filter *filter);
 201 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 202                         enum rte_filter_op filter_op,
 203                         void *arg);
 204 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *ntuple_filter);
 206 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 207                         struct rte_eth_ntuple_filter *ntuple_filter);
 208 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 209                         struct rte_eth_ntuple_filter *filter,
 210                         bool add);
 211 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 212                         struct rte_eth_ntuple_filter *filter);
 213 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ethertype_filter *filter,
 218                         bool add);
 219 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 220                                 enum rte_filter_op filter_op,
 221                                 void *arg);
 222 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_ethertype_filter *filter);
 224 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 225                      enum rte_filter_type filter_type,
 226                      enum rte_filter_op filter_op,
 227                      void *arg);
 228 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 229 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 230                 struct rte_dev_reg_info *regs);
 231 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 232 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 233                 struct rte_dev_eeprom_info *eeprom);
 234 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 235                 struct rte_dev_eeprom_info *eeprom);
 236 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 237                                     struct ether_addr *mc_addr_set,
 238                                     uint32_t nb_mc_addr);
 239 static int igb_timesync_enable(struct rte_eth_dev *dev);
 240 static int igb_timesync_disable(struct rte_eth_dev *dev);
 241 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 242                                           struct timespec *timestamp,
 243                                           uint32_t flags);
 244 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 245                                           struct timespec *timestamp);
 246 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 247 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 248                                   struct timespec *timestamp);
 249 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 250                                    const struct timespec *timestamp);
 251 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                         uint16_t queue_id);
 253 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                          uint16_t queue_id);
 255 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 256                                        uint8_t queue, uint8_t msix_vector);
 257 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 258                                uint8_t index, uint8_t offset);
 259 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 260
 261 /*
 262  * Define VF Stats MACRO for Non "cleared on read" register
 263  */
 264 #define UPDATE_VF_STAT(reg, last, cur)            \
 265 {                                                 \
 266         u32 latest = E1000_READ_REG(hw, reg);     \
 267         cur += (latest - last) & UINT_MAX;        \
 268         last = latest;                            \
 269 }
 270
 271 #define IGB_FC_PAUSE_TIME 0x0680
 272 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 273 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 274
 275 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 276
 277 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 278
 279 /*
 280  * The set of PCI devices this driver supports
 281  */
 282 static const struct rte_pci_id pci_id_igb_map[] = {
 283
 284 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 285 #include "rte_pci_dev_ids.h"
 286
 287 {0},
 288 };
 289
 290 /*
 291  * The set of PCI devices this driver supports (for 82576&I350 VF)
 292  */
 293 static const struct rte_pci_id pci_id_igbvf_map[] = {
 294
 295 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 296 #include "rte_pci_dev_ids.h"
 297
 298 {0},
 299 };
 300
 301 static const struct rte_eth_desc_lim rx_desc_lim = {
 302         .nb_max = E1000_MAX_RING_DESC,
 303         .nb_min = E1000_MIN_RING_DESC,
 304         .nb_align = IGB_RXD_ALIGN,
 305 };
 306
 307 static const struct rte_eth_desc_lim tx_desc_lim = {
 308         .nb_max = E1000_MAX_RING_DESC,
 309         .nb_min = E1000_MIN_RING_DESC,
 310         .nb_align = IGB_RXD_ALIGN,
 311 };
 312
 313 static const struct eth_dev_ops eth_igb_ops = {
 314         .dev_configure        = eth_igb_configure,
 315         .dev_start            = eth_igb_start,
 316         .dev_stop             = eth_igb_stop,
 317         .dev_close            = eth_igb_close,
 318         .promiscuous_enable   = eth_igb_promiscuous_enable,
 319         .promiscuous_disable  = eth_igb_promiscuous_disable,
 320         .allmulticast_enable  = eth_igb_allmulticast_enable,
 321         .allmulticast_disable = eth_igb_allmulticast_disable,
 322         .link_update          = eth_igb_link_update,
 323         .stats_get            = eth_igb_stats_get,
 324         .xstats_get           = eth_igb_xstats_get,
 325         .stats_reset          = eth_igb_stats_reset,
 326         .xstats_reset         = eth_igb_xstats_reset,
 327         .dev_infos_get        = eth_igb_infos_get,
 328         .mtu_set              = eth_igb_mtu_set,
 329         .vlan_filter_set      = eth_igb_vlan_filter_set,
 330         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 331         .vlan_offload_set     = eth_igb_vlan_offload_set,
 332         .rx_queue_setup       = eth_igb_rx_queue_setup,
 333         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 334         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 335         .rx_queue_release     = eth_igb_rx_queue_release,
 336         .rx_queue_count       = eth_igb_rx_queue_count,
 337         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 338         .tx_queue_setup       = eth_igb_tx_queue_setup,
 339         .tx_queue_release     = eth_igb_tx_queue_release,
 340         .dev_led_on           = eth_igb_led_on,
 341         .dev_led_off          = eth_igb_led_off,
 342         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 343         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 344         .mac_addr_add         = eth_igb_rar_set,
 345         .mac_addr_remove      = eth_igb_rar_clear,
 346         .mac_addr_set         = eth_igb_default_mac_addr_set,
 347         .reta_update          = eth_igb_rss_reta_update,
 348         .reta_query           = eth_igb_rss_reta_query,
 349         .rss_hash_update      = eth_igb_rss_hash_update,
 350         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 351         .filter_ctrl          = eth_igb_filter_ctrl,
 352         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 353         .rxq_info_get         = igb_rxq_info_get,
 354         .txq_info_get         = igb_txq_info_get,
 355         .timesync_enable      = igb_timesync_enable,
 356         .timesync_disable     = igb_timesync_disable,
 357         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 358         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 359         .get_reg_length       = eth_igb_get_reg_length,
 360         .get_reg              = eth_igb_get_regs,
 361         .get_eeprom_length    = eth_igb_get_eeprom_length,
 362         .get_eeprom           = eth_igb_get_eeprom,
 363         .set_eeprom           = eth_igb_set_eeprom,
 364         .timesync_adjust_time = igb_timesync_adjust_time,
 365         .timesync_read_time   = igb_timesync_read_time,
 366         .timesync_write_time  = igb_timesync_write_time,
 367 };
 368
 369 /*
 370  * dev_ops for virtual function, bare necessities for basic vf
 371  * operation have been implemented
 372  */
 373 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 374         .dev_configure        = igbvf_dev_configure,
 375         .dev_start            = igbvf_dev_start,
 376         .dev_stop             = igbvf_dev_stop,
 377         .dev_close            = igbvf_dev_close,
 378         .promiscuous_enable   = igbvf_promiscuous_enable,
 379         .promiscuous_disable  = igbvf_promiscuous_disable,
 380         .allmulticast_enable  = igbvf_allmulticast_enable,
 381         .allmulticast_disable = igbvf_allmulticast_disable,
 382         .link_update          = eth_igb_link_update,
 383         .stats_get            = eth_igbvf_stats_get,
 384         .xstats_get           = eth_igbvf_xstats_get,
 385         .stats_reset          = eth_igbvf_stats_reset,
 386         .xstats_reset         = eth_igbvf_stats_reset,
 387         .vlan_filter_set      = igbvf_vlan_filter_set,
 388         .dev_infos_get        = eth_igbvf_infos_get,
 389         .rx_queue_setup       = eth_igb_rx_queue_setup,
 390         .rx_queue_release     = eth_igb_rx_queue_release,
 391         .tx_queue_setup       = eth_igb_tx_queue_setup,
 392         .tx_queue_release     = eth_igb_tx_queue_release,
 393         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 394         .rxq_info_get         = igb_rxq_info_get,
 395         .txq_info_get         = igb_txq_info_get,
 396         .mac_addr_set         = igbvf_default_mac_addr_set,
 397         .get_reg_length       = igbvf_get_reg_length,
 398         .get_reg              = igbvf_get_regs,
 399 };
 400
 401 /* store statistics names and its offset in stats structure */
 402 struct rte_igb_xstats_name_off {
 403         char name[RTE_ETH_XSTATS_NAME_SIZE];
 404         unsigned offset;
 405 };
 406
 407 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 408         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 409         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 410         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 411         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 412         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 413         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 414         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 415                 ecol)},
 416         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 417         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 418         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 419         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 420         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 421         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 422         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 423         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 424         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 425         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 426         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 427                 fcruc)},
 428         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 429         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 430         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 431         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 432         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 433                 prc1023)},
 434         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 435                 prc1522)},
 436         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 437         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 438         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 439         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 440         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 441         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 442         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 443         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 444         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 445         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 446         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 447         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 448         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 449         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 450         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 451         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 452         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 453         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 454                 ptc1023)},
 455         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 456                 ptc1522)},
 457         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 458         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 459         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 460         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 461         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 462         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 463         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 464
 465         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 466 };
 467
 468 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 469                 sizeof(rte_igb_stats_strings[0]))
 470
 471 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 472         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 473         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 474         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 475         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 476         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 477 };
 478
 479 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 480                 sizeof(rte_igbvf_stats_strings[0]))
 481
 482 /**
 483  * Atomically reads the link status information from global
 484  * structure rte_eth_dev.
 485  *
 486  * @param dev
 487  *   - Pointer to the structure rte_eth_dev to read from.
 488  *   - Pointer to the buffer to be saved with the link status.
 489  *
 490  * @return
 491  *   - On success, zero.
 492  *   - On failure, negative value.
 493  */
 494 static inline int
 495 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 496                                 struct rte_eth_link *link)
 497 {
 498         struct rte_eth_link *dst = link;
 499         struct rte_eth_link *src = &(dev->data->dev_link);
 500
 501         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 502                                         *(uint64_t *)src) == 0)
 503                 return -1;
 504
 505         return 0;
 506 }
 507
 508 /**
 509  * Atomically writes the link status information into global
 510  * structure rte_eth_dev.
 511  *
 512  * @param dev
 513  *   - Pointer to the structure rte_eth_dev to read from.
 514  *   - Pointer to the buffer to be saved with the link status.
 515  *
 516  * @return
 517  *   - On success, zero.
 518  *   - On failure, negative value.
 519  */
 520 static inline int
 521 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 522                                 struct rte_eth_link *link)
 523 {
 524         struct rte_eth_link *dst = &(dev->data->dev_link);
 525         struct rte_eth_link *src = link;
 526
 527         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 528                                         *(uint64_t *)src) == 0)
 529                 return -1;
 530
 531         return 0;
 532 }
 533
 534 static inline void
 535 igb_intr_enable(struct rte_eth_dev *dev)
 536 {
 537         struct e1000_interrupt *intr =
 538                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 539         struct e1000_hw *hw =
 540                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 541
 542         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 543         E1000_WRITE_FLUSH(hw);
 544 }
 545
 546 static void
 547 igb_intr_disable(struct e1000_hw *hw)
 548 {
 549         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 550         E1000_WRITE_FLUSH(hw);
 551 }
 552
 553 static inline int32_t
 554 igb_pf_reset_hw(struct e1000_hw *hw)
 555 {
 556         uint32_t ctrl_ext;
 557         int32_t status;
 558
 559         status = e1000_reset_hw(hw);
 560
 561         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 562         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 563         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 564         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 565         E1000_WRITE_FLUSH(hw);
 566
 567         return status;
 568 }
 569
 570 static void
 571 igb_identify_hardware(struct rte_eth_dev *dev)
 572 {
 573         struct e1000_hw *hw =
 574                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         hw->vendor_id = dev->pci_dev->id.vendor_id;
 577         hw->device_id = dev->pci_dev->id.device_id;
 578         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 579         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 580
 581         e1000_set_mac_type(hw);
 582
 583         /* need to check if it is a vf device below */
 584 }
 585
 586 static int
 587 igb_reset_swfw_lock(struct e1000_hw *hw)
 588 {
 589         int ret_val;
 590
 591         /*
 592          * Do mac ops initialization manually here, since we will need
 593          * some function pointers set by this call.
 594          */
 595         ret_val = e1000_init_mac_params(hw);
 596         if (ret_val)
 597                 return ret_val;
 598
 599         /*
 600          * SMBI lock should not fail in this early stage. If this is the case,
 601          * it is due to an improper exit of the application.
 602          * So force the release of the faulty lock.
 603          */
 604         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 605                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 606         }
 607         e1000_put_hw_semaphore_generic(hw);
 608
 609         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 610                 uint16_t mask;
 611
 612                 /*
 613                  * Phy lock should not fail in this early stage. If this is the case,
 614                  * it is due to an improper exit of the application.
 615                  * So force the release of the faulty lock.
 616                  */
 617                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 618                 if (hw->bus.func > E1000_FUNC_1)
 619                         mask <<= 2;
 620                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 621                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 622                                     hw->bus.func);
 623                 }
 624                 hw->mac.ops.release_swfw_sync(hw, mask);
 625
 626                 /*
 627                  * This one is more tricky since it is common to all ports; but
 628                  * swfw_sync retries last long enough (1s) to be almost sure that if
 629                  * lock can not be taken it is due to an improper lock of the
 630                  * semaphore.
 631                  */
 632                 mask = E1000_SWFW_EEP_SM;
 633                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 634                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 635                 }
 636                 hw->mac.ops.release_swfw_sync(hw, mask);
 637         }
 638
 639         return E1000_SUCCESS;
 640 }
 641
 642 static int
 643 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 644 {
 645         int error = 0;
 646         struct rte_pci_device *pci_dev;
 647         struct e1000_hw *hw =
 648                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 649         struct e1000_vfta * shadow_vfta =
 650                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 651         struct e1000_filter_info *filter_info =
 652                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 653         struct e1000_adapter *adapter =
 654                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 655
 656         uint32_t ctrl_ext;
 657
 658         pci_dev = eth_dev->pci_dev;
 659
 660         eth_dev->dev_ops = &eth_igb_ops;
 661         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 662         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 663
 664         /* for secondary processes, we don't initialise any further as primary
 665          * has already done this work. Only check we don't need a different
 666          * RX function */
 667         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 668                 if (eth_dev->data->scattered_rx)
 669                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 670                 return 0;
 671         }
 672
 673         rte_eth_copy_pci_info(eth_dev, pci_dev);
 674
 675         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 676
 677         igb_identify_hardware(eth_dev);
 678         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 679                 error = -EIO;
 680                 goto err_late;
 681         }
 682
 683         e1000_get_bus_info(hw);
 684
 685         /* Reset any pending lock */
 686         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 687                 error = -EIO;
 688                 goto err_late;
 689         }
 690
 691         /* Finish initialization */
 692         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 693                 error = -EIO;
 694                 goto err_late;
 695         }
 696
 697         hw->mac.autoneg = 1;
 698         hw->phy.autoneg_wait_to_complete = 0;
 699         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 700
 701         /* Copper options */
 702         if (hw->phy.media_type == e1000_media_type_copper) {
 703                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 704                 hw->phy.disable_polarity_correction = 0;
 705                 hw->phy.ms_type = e1000_ms_hw_default;
 706         }
 707
 708         /*
 709          * Start from a known state, this is important in reading the nvm
 710          * and mac from that.
 711          */
 712         igb_pf_reset_hw(hw);
 713
 714         /* Make sure we have a good EEPROM before we read from it */
 715         if (e1000_validate_nvm_checksum(hw) < 0) {
 716                 /*
 717                  * Some PCI-E parts fail the first check due to
 718                  * the link being in sleep state, call it again,
 719                  * if it fails a second time its a real issue.
 720                  */
 721                 if (e1000_validate_nvm_checksum(hw) < 0) {
 722                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 723                         error = -EIO;
 724                         goto err_late;
 725                 }
 726         }
 727
 728         /* Read the permanent MAC address out of the EEPROM */
 729         if (e1000_read_mac_addr(hw) != 0) {
 730                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 731                 error = -EIO;
 732                 goto err_late;
 733         }
 734
 735         /* Allocate memory for storing MAC addresses */
 736         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 737                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 738         if (eth_dev->data->mac_addrs == NULL) {
 739                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 740                                                 "store MAC addresses",
 741                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 742                 error = -ENOMEM;
 743                 goto err_late;
 744         }
 745
 746         /* Copy the permanent MAC address */
 747         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 748
 749         /* initialize the vfta */
 750         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 751
 752         /* Now initialize the hardware */
 753         if (igb_hardware_init(hw) != 0) {
 754                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 755                 rte_free(eth_dev->data->mac_addrs);
 756                 eth_dev->data->mac_addrs = NULL;
 757                 error = -ENODEV;
 758                 goto err_late;
 759         }
 760         hw->mac.get_link_status = 1;
 761         adapter->stopped = 0;
 762
 763         /* Indicate SOL/IDER usage */
 764         if (e1000_check_reset_block(hw) < 0) {
 765                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 766                                         "SOL/IDER session");
 767         }
 768
 769         /* initialize PF if max_vfs not zero */
 770         igb_pf_host_init(eth_dev);
 771
 772         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 775         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 776         E1000_WRITE_FLUSH(hw);
 777
 778         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 779                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 780                      pci_dev->id.device_id);
 781
 782         rte_intr_callback_register(&pci_dev->intr_handle,
 783                                    eth_igb_interrupt_handler,
 784                                    (void *)eth_dev);
 785
 786         /* enable uio/vfio intr/eventfd mapping */
 787         rte_intr_enable(&pci_dev->intr_handle);
 788
 789         /* enable support intr */
 790         igb_intr_enable(eth_dev);
 791
 792         TAILQ_INIT(&filter_info->flex_list);
 793         filter_info->flex_mask = 0;
 794         TAILQ_INIT(&filter_info->twotuple_list);
 795         filter_info->twotuple_mask = 0;
 796         TAILQ_INIT(&filter_info->fivetuple_list);
 797         filter_info->fivetuple_mask = 0;
 798
 799         return 0;
 800
 801 err_late:
 802         igb_hw_control_release(hw);
 803
 804         return error;
 805 }
 806
 807 static int
 808 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 809 {
 810         struct rte_pci_device *pci_dev;
 811         struct e1000_hw *hw;
 812         struct e1000_adapter *adapter =
 813                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 814
 815         PMD_INIT_FUNC_TRACE();
 816
 817         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 818                 return -EPERM;
 819
 820         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 821         pci_dev = eth_dev->pci_dev;
 822
 823         if (adapter->stopped == 0)
 824                 eth_igb_close(eth_dev);
 825
 826         eth_dev->dev_ops = NULL;
 827         eth_dev->rx_pkt_burst = NULL;
 828         eth_dev->tx_pkt_burst = NULL;
 829
 830         /* Reset any pending lock */
 831         igb_reset_swfw_lock(hw);
 832
 833         rte_free(eth_dev->data->mac_addrs);
 834         eth_dev->data->mac_addrs = NULL;
 835
 836         /* uninitialize PF if max_vfs not zero */
 837         igb_pf_host_uninit(eth_dev);
 838
 839         /* disable uio intr before callback unregister */
 840         rte_intr_disable(&(pci_dev->intr_handle));
 841         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 842                 eth_igb_interrupt_handler, (void *)eth_dev);
 843
 844         return 0;
 845 }
 846
 847 /*
 848  * Virtual Function device init
 849  */
 850 static int
 851 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 852 {
 853         struct rte_pci_device *pci_dev;
 854         struct e1000_adapter *adapter =
 855                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 856         struct e1000_hw *hw =
 857                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 858         int diag;
 859         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 860
 861         PMD_INIT_FUNC_TRACE();
 862
 863         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 864         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 865         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 866
 867         /* for secondary processes, we don't initialise any further as primary
 868          * has already done this work. Only check we don't need a different
 869          * RX function */
 870         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 871                 if (eth_dev->data->scattered_rx)
 872                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 873                 return 0;
 874         }
 875
 876         pci_dev = eth_dev->pci_dev;
 877
 878         rte_eth_copy_pci_info(eth_dev, pci_dev);
 879
 880         hw->device_id = pci_dev->id.device_id;
 881         hw->vendor_id = pci_dev->id.vendor_id;
 882         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 883         adapter->stopped = 0;
 884
 885         /* Initialize the shared code (base driver) */
 886         diag = e1000_setup_init_funcs(hw, TRUE);
 887         if (diag != 0) {
 888                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 889                         diag);
 890                 return -EIO;
 891         }
 892
 893         /* init_mailbox_params */
 894         hw->mbx.ops.init_params(hw);
 895
 896         /* Disable the interrupts for VF */
 897         igbvf_intr_disable(hw);
 898
 899         diag = hw->mac.ops.reset_hw(hw);
 900
 901         /* Allocate memory for storing MAC addresses */
 902         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 903                 hw->mac.rar_entry_count, 0);
 904         if (eth_dev->data->mac_addrs == NULL) {
 905                 PMD_INIT_LOG(ERR,
 906                         "Failed to allocate %d bytes needed to store MAC "
 907                         "addresses",
 908                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 909                 return -ENOMEM;
 910         }
 911
 912         /* Generate a random MAC address, if none was assigned by PF. */
 913         if (is_zero_ether_addr(perm_addr)) {
 914                 eth_random_addr(perm_addr->addr_bytes);
 915                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 916                 if (diag) {
 917                         rte_free(eth_dev->data->mac_addrs);
 918                         eth_dev->data->mac_addrs = NULL;
 919                         return diag;
 920                 }
 921                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 922                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 923                              "%02x:%02x:%02x:%02x:%02x:%02x",
 924                              perm_addr->addr_bytes[0],
 925                              perm_addr->addr_bytes[1],
 926                              perm_addr->addr_bytes[2],
 927                              perm_addr->addr_bytes[3],
 928                              perm_addr->addr_bytes[4],
 929                              perm_addr->addr_bytes[5]);
 930         }
 931
 932         /* Copy the permanent MAC address */
 933         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 934                         &eth_dev->data->mac_addrs[0]);
 935
 936         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 937                      "mac.type=%s",
 938                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 939                      pci_dev->id.device_id, "igb_mac_82576_vf");
 940
 941         return 0;
 942 }
 943
 944 static int
 945 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 946 {
 947         struct e1000_adapter *adapter =
 948                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 953                 return -EPERM;
 954
 955         if (adapter->stopped == 0)
 956                 igbvf_dev_close(eth_dev);
 957
 958         eth_dev->dev_ops = NULL;
 959         eth_dev->rx_pkt_burst = NULL;
 960         eth_dev->tx_pkt_burst = NULL;
 961
 962         rte_free(eth_dev->data->mac_addrs);
 963         eth_dev->data->mac_addrs = NULL;
 964
 965         return 0;
 966 }
 967
 968 static struct eth_driver rte_igb_pmd = {
 969         .pci_drv = {
 970                 .name = "rte_igb_pmd",
 971                 .id_table = pci_id_igb_map,
 972                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 973                         RTE_PCI_DRV_DETACHABLE,
 974         },
 975         .eth_dev_init = eth_igb_dev_init,
 976         .eth_dev_uninit = eth_igb_dev_uninit,
 977         .dev_private_size = sizeof(struct e1000_adapter),
 978 };
 979
 980 /*
 981  * virtual function driver struct
 982  */
 983 static struct eth_driver rte_igbvf_pmd = {
 984         .pci_drv = {
 985                 .name = "rte_igbvf_pmd",
 986                 .id_table = pci_id_igbvf_map,
 987                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 988         },
 989         .eth_dev_init = eth_igbvf_dev_init,
 990         .eth_dev_uninit = eth_igbvf_dev_uninit,
 991         .dev_private_size = sizeof(struct e1000_adapter),
 992 };
 993
 994 static int
 995 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 996 {
 997         rte_eth_driver_register(&rte_igb_pmd);
 998         return 0;
 999 }
1000
1001 static void
1002 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1003 {
1004         struct e1000_hw *hw =
1005                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1007         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1008         rctl |= E1000_RCTL_VFE;
1009         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1010 }
1011
1012 /*
1013  * VF Driver initialization routine.
1014  * Invoked one at EAL init time.
1015  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1016  */
1017 static int
1018 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1019 {
1020         PMD_INIT_FUNC_TRACE();
1021
1022         rte_eth_driver_register(&rte_igbvf_pmd);
1023         return 0;
1024 }
1025
1026 static int
1027 igb_check_mq_mode(struct rte_eth_dev *dev)
1028 {
1029         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1030         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1031         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1032         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1033
1034         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1035             tx_mq_mode == ETH_MQ_TX_DCB ||
1036             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1037                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1038                 return -EINVAL;
1039         }
1040         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1041                 /* Check multi-queue mode.
1042                  * To no break software we accept ETH_MQ_RX_NONE as this might
1043                  * be used to turn off VLAN filter.
1044                  */
1045
1046                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1047                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1048                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1049                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1050                 } else {
1051                         /* Only support one queue on VFs.
1052                          * RSS together with SRIOV is not supported.
1053                          */
1054                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1055                                         " wrong mq_mode rx %d.",
1056                                         rx_mq_mode);
1057                         return -EINVAL;
1058                 }
1059                 /* TX mode is not used here, so mode might be ignored.*/
1060                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1061                         /* SRIOV only works in VMDq enable mode */
1062                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1063                                         " TX mode %d is not supported. "
1064                                         " Driver will behave as %d mode.",
1065                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1066                 }
1067
1068                 /* check valid queue number */
1069                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1070                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1071                                         " only support one queue on VFs.");
1072                         return -EINVAL;
1073                 }
1074         } else {
1075                 /* To no break software that set invalid mode, only display
1076                  * warning if invalid mode is used.
1077                  */
1078                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1079                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1080                     rx_mq_mode != ETH_MQ_RX_RSS) {
1081                         /* RSS together with VMDq not supported*/
1082                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1083                                      rx_mq_mode);
1084                         return -EINVAL;
1085                 }
1086
1087                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1088                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1089                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1090                                         " Due to txmode is meaningless in this"
1091                                         " driver, just ignore.",
1092                                         tx_mq_mode);
1093                 }
1094         }
1095         return 0;
1096 }
1097
1098 static int
1099 eth_igb_configure(struct rte_eth_dev *dev)
1100 {
1101         struct e1000_interrupt *intr =
1102                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1103         int ret;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         /* multipe queue mode checking */
1108         ret  = igb_check_mq_mode(dev);
1109         if (ret != 0) {
1110                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1111                             ret);
1112                 return ret;
1113         }
1114
1115         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1116         PMD_INIT_FUNC_TRACE();
1117
1118         return 0;
1119 }
1120
1121 static int
1122 eth_igb_start(struct rte_eth_dev *dev)
1123 {
1124         struct e1000_hw *hw =
1125                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1126         struct e1000_adapter *adapter =
1127                 E1000_DEV_PRIVATE(dev->data->dev_private);
1128         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1129         int ret, mask;
1130         uint32_t intr_vector = 0;
1131         uint32_t ctrl_ext;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         /* disable uio/vfio intr/eventfd mapping */
1136         rte_intr_disable(intr_handle);
1137
1138         /* Power up the phy. Needed to make the link go Up */
1139         e1000_power_up_phy(hw);
1140
1141         /*
1142          * Packet Buffer Allocation (PBA)
1143          * Writing PBA sets the receive portion of the buffer
1144          * the remainder is used for the transmit buffer.
1145          */
1146         if (hw->mac.type == e1000_82575) {
1147                 uint32_t pba;
1148
1149                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1150                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1151         }
1152
1153         /* Put the address into the Receive Address Array */
1154         e1000_rar_set(hw, hw->mac.addr, 0);
1155
1156         /* Initialize the hardware */
1157         if (igb_hardware_init(hw)) {
1158                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1159                 return -EIO;
1160         }
1161         adapter->stopped = 0;
1162
1163         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1164
1165         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1166         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1167         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1168         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1169         E1000_WRITE_FLUSH(hw);
1170
1171         /* configure PF module if SRIOV enabled */
1172         igb_pf_host_configure(dev);
1173
1174         /* check and configure queue intr-vector mapping */
1175         if ((rte_intr_cap_multiple(intr_handle) ||
1176              !RTE_ETH_DEV_SRIOV(dev).active) &&
1177             dev->data->dev_conf.intr_conf.rxq != 0) {
1178                 intr_vector = dev->data->nb_rx_queues;
1179                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1180                         return -1;
1181         }
1182
1183         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1184                 intr_handle->intr_vec =
1185                         rte_zmalloc("intr_vec",
1186                                     dev->data->nb_rx_queues * sizeof(int), 0);
1187                 if (intr_handle->intr_vec == NULL) {
1188                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1189                                      " intr_vec\n", dev->data->nb_rx_queues);
1190                         return -ENOMEM;
1191                 }
1192         }
1193
1194         /* confiugre msix for rx interrupt */
1195         eth_igb_configure_msix_intr(dev);
1196
1197         /* Configure for OS presence */
1198         igb_init_manageability(hw);
1199
1200         eth_igb_tx_init(dev);
1201
1202         /* This can fail when allocating mbufs for descriptor rings */
1203         ret = eth_igb_rx_init(dev);
1204         if (ret) {
1205                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1206                 igb_dev_clear_queues(dev);
1207                 return ret;
1208         }
1209
1210         e1000_clear_hw_cntrs_base_generic(hw);
1211
1212         /*
1213          * VLAN Offload Settings
1214          */
1215         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1216                         ETH_VLAN_EXTEND_MASK;
1217         eth_igb_vlan_offload_set(dev, mask);
1218
1219         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1220                 /* Enable VLAN filter since VMDq always use VLAN filter */
1221                 igb_vmdq_vlan_hw_filter_enable(dev);
1222         }
1223
1224         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1225                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1226                 (hw->mac.type == e1000_i211)) {
1227                 /* Configure EITR with the maximum possible value (0xFFFF) */
1228                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1229         }
1230
1231         /* Setup link speed and duplex */
1232         switch (dev->data->dev_conf.link_speed) {
1233         case ETH_LINK_SPEED_AUTONEG:
1234                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1235                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1236                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1237                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1238                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1239                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1240                 else
1241                         goto error_invalid_config;
1242                 break;
1243         case ETH_LINK_SPEED_10:
1244                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1245                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1246                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1247                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1248                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1249                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1250                 else
1251                         goto error_invalid_config;
1252                 break;
1253         case ETH_LINK_SPEED_100:
1254                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1255                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1256                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1257                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1258                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1259                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1260                 else
1261                         goto error_invalid_config;
1262                 break;
1263         case ETH_LINK_SPEED_1000:
1264                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1265                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1266                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1267                 else
1268                         goto error_invalid_config;
1269                 break;
1270         case ETH_LINK_SPEED_10000:
1271         default:
1272                 goto error_invalid_config;
1273         }
1274         e1000_setup_link(hw);
1275
1276         if (rte_intr_allow_others(intr_handle)) {
1277                 /* check if lsc interrupt is enabled */
1278                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1279                         eth_igb_lsc_interrupt_setup(dev);
1280         } else {
1281                 rte_intr_callback_unregister(intr_handle,
1282                                              eth_igb_interrupt_handler,
1283                                              (void *)dev);
1284                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1285                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1286                                      " no intr multiplex\n");
1287         }
1288
1289         /* check if rxq interrupt is enabled */
1290         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1291             rte_intr_dp_is_en(intr_handle))
1292                 eth_igb_rxq_interrupt_setup(dev);
1293
1294         /* enable uio/vfio intr/eventfd mapping */
1295         rte_intr_enable(intr_handle);
1296
1297         /* resume enabled intr since hw reset */
1298         igb_intr_enable(dev);
1299
1300         PMD_INIT_LOG(DEBUG, "<<");
1301
1302         return 0;
1303
1304 error_invalid_config:
1305         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1306                      dev->data->dev_conf.link_speed,
1307                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1308         igb_dev_clear_queues(dev);
1309         return -EINVAL;
1310 }
1311
1312 /*********************************************************************
1313  *
1314  *  This routine disables all traffic on the adapter by issuing a
1315  *  global reset on the MAC.
1316  *
1317  **********************************************************************/
1318 static void
1319 eth_igb_stop(struct rte_eth_dev *dev)
1320 {
1321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1322         struct e1000_filter_info *filter_info =
1323                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1324         struct rte_eth_link link;
1325         struct e1000_flex_filter *p_flex;
1326         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1327         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1328         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1329
1330         igb_intr_disable(hw);
1331
1332         /* disable intr eventfd mapping */
1333         rte_intr_disable(intr_handle);
1334
1335         igb_pf_reset_hw(hw);
1336         E1000_WRITE_REG(hw, E1000_WUC, 0);
1337
1338         /* Set bit for Go Link disconnect */
1339         if (hw->mac.type >= e1000_82580) {
1340                 uint32_t phpm_reg;
1341
1342                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1343                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1344                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1345         }
1346
1347         /* Power down the phy. Needed to make the link go Down */
1348         if (hw->phy.media_type == e1000_media_type_copper)
1349                 e1000_power_down_phy(hw);
1350         else
1351                 e1000_shutdown_fiber_serdes_link(hw);
1352
1353         igb_dev_clear_queues(dev);
1354
1355         /* clear the recorded link status */
1356         memset(&link, 0, sizeof(link));
1357         rte_igb_dev_atomic_write_link_status(dev, &link);
1358
1359         /* Remove all flex filters of the device */
1360         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1361                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1362                 rte_free(p_flex);
1363         }
1364         filter_info->flex_mask = 0;
1365
1366         /* Remove all ntuple filters of the device */
1367         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1368              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1369                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1370                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1371                              p_5tuple, entries);
1372                 rte_free(p_5tuple);
1373         }
1374         filter_info->fivetuple_mask = 0;
1375         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1376              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1377                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1378                 TAILQ_REMOVE(&filter_info->twotuple_list,
1379                              p_2tuple, entries);
1380                 rte_free(p_2tuple);
1381         }
1382         filter_info->twotuple_mask = 0;
1383
1384         if (!rte_intr_allow_others(intr_handle))
1385                 /* resume to the default handler */
1386                 rte_intr_callback_register(intr_handle,
1387                                            eth_igb_interrupt_handler,
1388                                            (void *)dev);
1389
1390         /* Clean datapath event and queue/vec mapping */
1391         rte_intr_efd_disable(intr_handle);
1392         if (intr_handle->intr_vec != NULL) {
1393                 rte_free(intr_handle->intr_vec);
1394                 intr_handle->intr_vec = NULL;
1395         }
1396 }
1397
1398 static void
1399 eth_igb_close(struct rte_eth_dev *dev)
1400 {
1401         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         struct e1000_adapter *adapter =
1403                 E1000_DEV_PRIVATE(dev->data->dev_private);
1404         struct rte_eth_link link;
1405         struct rte_pci_device *pci_dev;
1406
1407         eth_igb_stop(dev);
1408         adapter->stopped = 1;
1409
1410         e1000_phy_hw_reset(hw);
1411         igb_release_manageability(hw);
1412         igb_hw_control_release(hw);
1413
1414         /* Clear bit for Go Link disconnect */
1415         if (hw->mac.type >= e1000_82580) {
1416                 uint32_t phpm_reg;
1417
1418                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1419                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1420                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1421         }
1422
1423         igb_dev_free_queues(dev);
1424
1425         pci_dev = dev->pci_dev;
1426         if (pci_dev->intr_handle.intr_vec) {
1427                 rte_free(pci_dev->intr_handle.intr_vec);
1428                 pci_dev->intr_handle.intr_vec = NULL;
1429         }
1430
1431         memset(&link, 0, sizeof(link));
1432         rte_igb_dev_atomic_write_link_status(dev, &link);
1433 }
1434
1435 static int
1436 igb_get_rx_buffer_size(struct e1000_hw *hw)
1437 {
1438         uint32_t rx_buf_size;
1439         if (hw->mac.type == e1000_82576) {
1440                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1441         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1442                 /* PBS needs to be translated according to a lookup table */
1443                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1444                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1445                 rx_buf_size = (rx_buf_size << 10);
1446         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1447                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1448         } else {
1449                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1450         }
1451
1452         return rx_buf_size;
1453 }
1454
1455 /*********************************************************************
1456  *
1457  *  Initialize the hardware
1458  *
1459  **********************************************************************/
1460 static int
1461 igb_hardware_init(struct e1000_hw *hw)
1462 {
1463         uint32_t rx_buf_size;
1464         int diag;
1465
1466         /* Let the firmware know the OS is in control */
1467         igb_hw_control_acquire(hw);
1468
1469         /*
1470          * These parameters control the automatic generation (Tx) and
1471          * response (Rx) to Ethernet PAUSE frames.
1472          * - High water mark should allow for at least two standard size (1518)
1473          *   frames to be received after sending an XOFF.
1474          * - Low water mark works best when it is very near the high water mark.
1475          *   This allows the receiver to restart by sending XON when it has
1476          *   drained a bit. Here we use an arbitrary value of 1500 which will
1477          *   restart after one full frame is pulled from the buffer. There
1478          *   could be several smaller frames in the buffer and if so they will
1479          *   not trigger the XON until their total number reduces the buffer
1480          *   by 1500.
1481          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1482          */
1483         rx_buf_size = igb_get_rx_buffer_size(hw);
1484
1485         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1486         hw->fc.low_water = hw->fc.high_water - 1500;
1487         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1488         hw->fc.send_xon = 1;
1489
1490         /* Set Flow control, use the tunable location if sane */
1491         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1492                 hw->fc.requested_mode = igb_fc_setting;
1493         else
1494                 hw->fc.requested_mode = e1000_fc_none;
1495
1496         /* Issue a global reset */
1497         igb_pf_reset_hw(hw);
1498         E1000_WRITE_REG(hw, E1000_WUC, 0);
1499
1500         diag = e1000_init_hw(hw);
1501         if (diag < 0)
1502                 return diag;
1503
1504         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1505         e1000_get_phy_info(hw);
1506         e1000_check_for_link(hw);
1507
1508         return 0;
1509 }
1510
1511 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1512 static void
1513 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1514 {
1515         int pause_frames;
1516
1517         uint64_t old_gprc  = stats->gprc;
1518         uint64_t old_gptc  = stats->gptc;
1519         uint64_t old_tpr   = stats->tpr;
1520         uint64_t old_tpt   = stats->tpt;
1521         uint64_t old_rpthc = stats->rpthc;
1522         uint64_t old_hgptc = stats->hgptc;
1523
1524         if(hw->phy.media_type == e1000_media_type_copper ||
1525             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1526                 stats->symerrs +=
1527                     E1000_READ_REG(hw,E1000_SYMERRS);
1528                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1529         }
1530
1531         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1532         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1533         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1534         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1535
1536         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1537         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1538         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1539         stats->dc += E1000_READ_REG(hw, E1000_DC);
1540         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1541         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1542         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1543         /*
1544         ** For watchdog management we need to know if we have been
1545         ** paused during the last interval, so capture that here.
1546         */
1547         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1548         stats->xoffrxc += pause_frames;
1549         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1550         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1551         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1552         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1553         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1554         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1555         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1556         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1557         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1558         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1559         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1560         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1561
1562         /* For the 64-bit byte counters the low dword must be read first. */
1563         /* Both registers clear on the read of the high dword */
1564
1565         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1566         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1567         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1568         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1569         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1570         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1571         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1572
1573         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1574         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1575         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1576         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1577         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1578
1579         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1580         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1581
1582         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1583         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1584         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1585         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1586         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1587         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1588
1589         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1590         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1591         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1592         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1593         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1594         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1595         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1596         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1597
1598         /* Interrupt Counts */
1599
1600         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1601         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1602         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1603         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1604         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1605         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1606         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1607         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1608         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1609
1610         /* Host to Card Statistics */
1611
1612         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1613         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1614         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1615         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1616         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1617         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1618         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1619         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1620         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1621         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1622         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1623         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1624         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1625         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1626         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1627         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1628
1629         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1630         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1631         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1632         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1633         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1634         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1635 }
1636
1637 static void
1638 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1639 {
1640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1641         struct e1000_hw_stats *stats =
1642                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1643
1644         igb_read_stats_registers(hw, stats);
1645
1646         if (rte_stats == NULL)
1647                 return;
1648
1649         /* Rx Errors */
1650         rte_stats->imissed = stats->mpc;
1651         rte_stats->ierrors = stats->crcerrs +
1652                              stats->rlec + stats->ruc + stats->roc +
1653                              rte_stats->imissed +
1654                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1655
1656         /* Tx Errors */
1657         rte_stats->oerrors = stats->ecol + stats->latecol;
1658
1659         rte_stats->ipackets = stats->gprc;
1660         rte_stats->opackets = stats->gptc;
1661         rte_stats->ibytes   = stats->gorc;
1662         rte_stats->obytes   = stats->gotc;
1663 }
1664
1665 static void
1666 eth_igb_stats_reset(struct rte_eth_dev *dev)
1667 {
1668         struct e1000_hw_stats *hw_stats =
1669                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1670
1671         /* HW registers are cleared on read */
1672         eth_igb_stats_get(dev, NULL);
1673
1674         /* Reset software totals */
1675         memset(hw_stats, 0, sizeof(*hw_stats));
1676 }
1677
1678 static void
1679 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1680 {
1681         struct e1000_hw_stats *stats =
1682                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1683
1684         /* HW registers are cleared on read */
1685         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1686
1687         /* Reset software totals */
1688         memset(stats, 0, sizeof(*stats));
1689 }
1690
1691 static int
1692 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1693                    unsigned n)
1694 {
1695         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696         struct e1000_hw_stats *hw_stats =
1697                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1698         unsigned i;
1699
1700         if (n < IGB_NB_XSTATS)
1701                 return IGB_NB_XSTATS;
1702
1703         igb_read_stats_registers(hw, hw_stats);
1704
1705         /* If this is a reset xstats is NULL, and we have cleared the
1706          * registers by reading them.
1707          */
1708         if (!xstats)
1709                 return 0;
1710
1711         /* Extended stats */
1712         for (i = 0; i < IGB_NB_XSTATS; i++) {
1713                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1714                          "%s", rte_igb_stats_strings[i].name);
1715                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1716                         rte_igb_stats_strings[i].offset);
1717         }
1718
1719         return IGB_NB_XSTATS;
1720 }
1721
1722 static void
1723 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1724 {
1725         /* Good Rx packets, include VF loopback */
1726         UPDATE_VF_STAT(E1000_VFGPRC,
1727             hw_stats->last_gprc, hw_stats->gprc);
1728
1729         /* Good Rx octets, include VF loopback */
1730         UPDATE_VF_STAT(E1000_VFGORC,
1731             hw_stats->last_gorc, hw_stats->gorc);
1732
1733         /* Good Tx packets, include VF loopback */
1734         UPDATE_VF_STAT(E1000_VFGPTC,
1735             hw_stats->last_gptc, hw_stats->gptc);
1736
1737         /* Good Tx octets, include VF loopback */
1738         UPDATE_VF_STAT(E1000_VFGOTC,
1739             hw_stats->last_gotc, hw_stats->gotc);
1740
1741         /* Rx Multicst packets */
1742         UPDATE_VF_STAT(E1000_VFMPRC,
1743             hw_stats->last_mprc, hw_stats->mprc);
1744
1745         /* Good Rx loopback packets */
1746         UPDATE_VF_STAT(E1000_VFGPRLBC,
1747             hw_stats->last_gprlbc, hw_stats->gprlbc);
1748
1749         /* Good Rx loopback octets */
1750         UPDATE_VF_STAT(E1000_VFGORLBC,
1751             hw_stats->last_gorlbc, hw_stats->gorlbc);
1752
1753         /* Good Tx loopback packets */
1754         UPDATE_VF_STAT(E1000_VFGPTLBC,
1755             hw_stats->last_gptlbc, hw_stats->gptlbc);
1756
1757         /* Good Tx loopback octets */
1758         UPDATE_VF_STAT(E1000_VFGOTLBC,
1759             hw_stats->last_gotlbc, hw_stats->gotlbc);
1760 }
1761
1762 static int
1763 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1764                      unsigned n)
1765 {
1766         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1768                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1769         unsigned i;
1770
1771         if (n < IGBVF_NB_XSTATS)
1772                 return IGBVF_NB_XSTATS;
1773
1774         igbvf_read_stats_registers(hw, hw_stats);
1775
1776         if (!xstats)
1777                 return 0;
1778
1779         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1780                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1781                          rte_igbvf_stats_strings[i].name);
1782                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1783                         rte_igbvf_stats_strings[i].offset);
1784         }
1785
1786         return IGBVF_NB_XSTATS;
1787 }
1788
1789 static void
1790 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1791 {
1792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1794                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1795
1796         igbvf_read_stats_registers(hw, hw_stats);
1797
1798         if (rte_stats == NULL)
1799                 return;
1800
1801         rte_stats->ipackets = hw_stats->gprc;
1802         rte_stats->ibytes = hw_stats->gorc;
1803         rte_stats->opackets = hw_stats->gptc;
1804         rte_stats->obytes = hw_stats->gotc;
1805         rte_stats->imcasts = hw_stats->mprc;
1806         rte_stats->ilbpackets = hw_stats->gprlbc;
1807         rte_stats->ilbbytes = hw_stats->gorlbc;
1808         rte_stats->olbpackets = hw_stats->gptlbc;
1809         rte_stats->olbbytes = hw_stats->gotlbc;
1810 }
1811
1812 static void
1813 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1814 {
1815         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1816                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1817
1818         /* Sync HW register to the last stats */
1819         eth_igbvf_stats_get(dev, NULL);
1820
1821         /* reset HW current stats*/
1822         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1823                offsetof(struct e1000_vf_stats, gprc));
1824 }
1825
1826 static void
1827 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1828 {
1829         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830
1831         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1832         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1833         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1834         dev_info->rx_offload_capa =
1835                 DEV_RX_OFFLOAD_VLAN_STRIP |
1836                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1837                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1838                 DEV_RX_OFFLOAD_TCP_CKSUM;
1839         dev_info->tx_offload_capa =
1840                 DEV_TX_OFFLOAD_VLAN_INSERT |
1841                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1842                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1843                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1844                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1845                 DEV_TX_OFFLOAD_TCP_TSO;
1846
1847         switch (hw->mac.type) {
1848         case e1000_82575:
1849                 dev_info->max_rx_queues = 4;
1850                 dev_info->max_tx_queues = 4;
1851                 dev_info->max_vmdq_pools = 0;
1852                 break;
1853
1854         case e1000_82576:
1855                 dev_info->max_rx_queues = 16;
1856                 dev_info->max_tx_queues = 16;
1857                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1858                 dev_info->vmdq_queue_num = 16;
1859                 break;
1860
1861         case e1000_82580:
1862                 dev_info->max_rx_queues = 8;
1863                 dev_info->max_tx_queues = 8;
1864                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1865                 dev_info->vmdq_queue_num = 8;
1866                 break;
1867
1868         case e1000_i350:
1869                 dev_info->max_rx_queues = 8;
1870                 dev_info->max_tx_queues = 8;
1871                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1872                 dev_info->vmdq_queue_num = 8;
1873                 break;
1874
1875         case e1000_i354:
1876                 dev_info->max_rx_queues = 8;
1877                 dev_info->max_tx_queues = 8;
1878                 break;
1879
1880         case e1000_i210:
1881                 dev_info->max_rx_queues = 4;
1882                 dev_info->max_tx_queues = 4;
1883                 dev_info->max_vmdq_pools = 0;
1884                 break;
1885
1886         case e1000_i211:
1887                 dev_info->max_rx_queues = 2;
1888                 dev_info->max_tx_queues = 2;
1889                 dev_info->max_vmdq_pools = 0;
1890                 break;
1891
1892         default:
1893                 /* Should not happen */
1894                 break;
1895         }
1896         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1897         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1898         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1899
1900         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1901                 .rx_thresh = {
1902                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1903                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1904                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1905                 },
1906                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1907                 .rx_drop_en = 0,
1908         };
1909
1910         dev_info->default_txconf = (struct rte_eth_txconf) {
1911                 .tx_thresh = {
1912                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1913                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1914                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1915                 },
1916                 .txq_flags = 0,
1917         };
1918
1919         dev_info->rx_desc_lim = rx_desc_lim;
1920         dev_info->tx_desc_lim = tx_desc_lim;
1921 }
1922
1923 static void
1924 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1925 {
1926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927
1928         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1929         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1930         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1931         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1932                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1933                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1934                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1935         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1936                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1937                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1938                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1939                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1940                                 DEV_TX_OFFLOAD_TCP_TSO;
1941         switch (hw->mac.type) {
1942         case e1000_vfadapt:
1943                 dev_info->max_rx_queues = 2;
1944                 dev_info->max_tx_queues = 2;
1945                 break;
1946         case e1000_vfadapt_i350:
1947                 dev_info->max_rx_queues = 1;
1948                 dev_info->max_tx_queues = 1;
1949                 break;
1950         default:
1951                 /* Should not happen */
1952                 break;
1953         }
1954
1955         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1956                 .rx_thresh = {
1957                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1958                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1959                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1960                 },
1961                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1962                 .rx_drop_en = 0,
1963         };
1964
1965         dev_info->default_txconf = (struct rte_eth_txconf) {
1966                 .tx_thresh = {
1967                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1968                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1969                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1970                 },
1971                 .txq_flags = 0,
1972         };
1973
1974         dev_info->rx_desc_lim = rx_desc_lim;
1975         dev_info->tx_desc_lim = tx_desc_lim;
1976 }
1977
1978 /* return 0 means link status changed, -1 means not changed */
1979 static int
1980 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1981 {
1982         struct e1000_hw *hw =
1983                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984         struct rte_eth_link link, old;
1985         int link_check, count;
1986
1987         link_check = 0;
1988         hw->mac.get_link_status = 1;
1989
1990         /* possible wait-to-complete in up to 9 seconds */
1991         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1992                 /* Read the real link status */
1993                 switch (hw->phy.media_type) {
1994                 case e1000_media_type_copper:
1995                         /* Do the work to read phy */
1996                         e1000_check_for_link(hw);
1997                         link_check = !hw->mac.get_link_status;
1998                         break;
1999
2000                 case e1000_media_type_fiber:
2001                         e1000_check_for_link(hw);
2002                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2003                                       E1000_STATUS_LU);
2004                         break;
2005
2006                 case e1000_media_type_internal_serdes:
2007                         e1000_check_for_link(hw);
2008                         link_check = hw->mac.serdes_has_link;
2009                         break;
2010
2011                 /* VF device is type_unknown */
2012                 case e1000_media_type_unknown:
2013                         eth_igbvf_link_update(hw);
2014                         link_check = !hw->mac.get_link_status;
2015                         break;
2016
2017                 default:
2018                         break;
2019                 }
2020                 if (link_check || wait_to_complete == 0)
2021                         break;
2022                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2023         }
2024         memset(&link, 0, sizeof(link));
2025         rte_igb_dev_atomic_read_link_status(dev, &link);
2026         old = link;
2027
2028         /* Now we check if a transition has happened */
2029         if (link_check) {
2030                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2031                                           &link.link_duplex);
2032                 link.link_status = 1;
2033         } else if (!link_check) {
2034                 link.link_speed = 0;
2035                 link.link_duplex = 0;
2036                 link.link_status = 0;
2037         }
2038         rte_igb_dev_atomic_write_link_status(dev, &link);
2039
2040         /* not changed */
2041         if (old.link_status == link.link_status)
2042                 return -1;
2043
2044         /* changed */
2045         return 0;
2046 }
2047
2048 /*
2049  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2050  * For ASF and Pass Through versions of f/w this means
2051  * that the driver is loaded.
2052  */
2053 static void
2054 igb_hw_control_acquire(struct e1000_hw *hw)
2055 {
2056         uint32_t ctrl_ext;
2057
2058         /* Let firmware know the driver has taken over */
2059         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2060         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2061 }
2062
2063 /*
2064  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2065  * For ASF and Pass Through versions of f/w this means that the
2066  * driver is no longer loaded.
2067  */
2068 static void
2069 igb_hw_control_release(struct e1000_hw *hw)
2070 {
2071         uint32_t ctrl_ext;
2072
2073         /* Let firmware taken over control of h/w */
2074         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2075         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2076                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2077 }
2078
2079 /*
2080  * Bit of a misnomer, what this really means is
2081  * to enable OS management of the system... aka
2082  * to disable special hardware management features.
2083  */
2084 static void
2085 igb_init_manageability(struct e1000_hw *hw)
2086 {
2087         if (e1000_enable_mng_pass_thru(hw)) {
2088                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2089                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2090
2091                 /* disable hardware interception of ARP */
2092                 manc &= ~(E1000_MANC_ARP_EN);
2093
2094                 /* enable receiving management packets to the host */
2095                 manc |= E1000_MANC_EN_MNG2HOST;
2096                 manc2h |= 1 << 5;  /* Mng Port 623 */
2097                 manc2h |= 1 << 6;  /* Mng Port 664 */
2098                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2099                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2100         }
2101 }
2102
2103 static void
2104 igb_release_manageability(struct e1000_hw *hw)
2105 {
2106         if (e1000_enable_mng_pass_thru(hw)) {
2107                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2108
2109                 manc |= E1000_MANC_ARP_EN;
2110                 manc &= ~E1000_MANC_EN_MNG2HOST;
2111
2112                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2113         }
2114 }
2115
2116 static void
2117 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2118 {
2119         struct e1000_hw *hw =
2120                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2121         uint32_t rctl;
2122
2123         rctl = E1000_READ_REG(hw, E1000_RCTL);
2124         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2125         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2126 }
2127
2128 static void
2129 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2130 {
2131         struct e1000_hw *hw =
2132                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2133         uint32_t rctl;
2134
2135         rctl = E1000_READ_REG(hw, E1000_RCTL);
2136         rctl &= (~E1000_RCTL_UPE);
2137         if (dev->data->all_multicast == 1)
2138                 rctl |= E1000_RCTL_MPE;
2139         else
2140                 rctl &= (~E1000_RCTL_MPE);
2141         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2142 }
2143
2144 static void
2145 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2146 {
2147         struct e1000_hw *hw =
2148                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         uint32_t rctl;
2150
2151         rctl = E1000_READ_REG(hw, E1000_RCTL);
2152         rctl |= E1000_RCTL_MPE;
2153         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2154 }
2155
2156 static void
2157 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2158 {
2159         struct e1000_hw *hw =
2160                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         uint32_t rctl;
2162
2163         if (dev->data->promiscuous == 1)
2164                 return; /* must remain in all_multicast mode */
2165         rctl = E1000_READ_REG(hw, E1000_RCTL);
2166         rctl &= (~E1000_RCTL_MPE);
2167         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2168 }
2169
2170 static int
2171 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2172 {
2173         struct e1000_hw *hw =
2174                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct e1000_vfta * shadow_vfta =
2176                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2177         uint32_t vfta;
2178         uint32_t vid_idx;
2179         uint32_t vid_bit;
2180
2181         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2182                               E1000_VFTA_ENTRY_MASK);
2183         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2184         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2185         if (on)
2186                 vfta |= vid_bit;
2187         else
2188                 vfta &= ~vid_bit;
2189         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2190
2191         /* update local VFTA copy */
2192         shadow_vfta->vfta[vid_idx] = vfta;
2193
2194         return 0;
2195 }
2196
2197 static int
2198 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2199                       enum rte_vlan_type vlan_type,
2200                       uint16_t tpid)
2201 {
2202         struct e1000_hw *hw =
2203                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t reg = ETHER_TYPE_VLAN;
2205         int ret = 0;
2206
2207         switch (vlan_type) {
2208         case ETH_VLAN_TYPE_INNER:
2209                 reg |= (tpid << 16);
2210                 E1000_WRITE_REG(hw, E1000_VET, reg);
2211                 break;
2212         default:
2213                 ret = -EINVAL;
2214                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2215                 break;
2216         }
2217
2218         return ret;
2219 }
2220
2221 static void
2222 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2223 {
2224         struct e1000_hw *hw =
2225                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         uint32_t reg;
2227
2228         /* Filter Table Disable */
2229         reg = E1000_READ_REG(hw, E1000_RCTL);
2230         reg &= ~E1000_RCTL_CFIEN;
2231         reg &= ~E1000_RCTL_VFE;
2232         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2233 }
2234
2235 static void
2236 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2237 {
2238         struct e1000_hw *hw =
2239                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct e1000_vfta * shadow_vfta =
2241                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2242         uint32_t reg;
2243         int i;
2244
2245         /* Filter Table Enable, CFI not used for packet acceptance */
2246         reg = E1000_READ_REG(hw, E1000_RCTL);
2247         reg &= ~E1000_RCTL_CFIEN;
2248         reg |= E1000_RCTL_VFE;
2249         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2250
2251         /* restore VFTA table */
2252         for (i = 0; i < IGB_VFTA_SIZE; i++)
2253                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2254 }
2255
2256 static void
2257 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2258 {
2259         struct e1000_hw *hw =
2260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         uint32_t reg;
2262
2263         /* VLAN Mode Disable */
2264         reg = E1000_READ_REG(hw, E1000_CTRL);
2265         reg &= ~E1000_CTRL_VME;
2266         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2267 }
2268
2269 static void
2270 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2271 {
2272         struct e1000_hw *hw =
2273                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         uint32_t reg;
2275
2276         /* VLAN Mode Enable */
2277         reg = E1000_READ_REG(hw, E1000_CTRL);
2278         reg |= E1000_CTRL_VME;
2279         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2280 }
2281
2282 static void
2283 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2284 {
2285         struct e1000_hw *hw =
2286                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         uint32_t reg;
2288
2289         /* CTRL_EXT: Extended VLAN */
2290         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2291         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2292         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2293
2294         /* Update maximum packet length */
2295         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2296                 E1000_WRITE_REG(hw, E1000_RLPML,
2297                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2298                                                 VLAN_TAG_SIZE);
2299 }
2300
2301 static void
2302 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2303 {
2304         struct e1000_hw *hw =
2305                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306         uint32_t reg;
2307
2308         /* CTRL_EXT: Extended VLAN */
2309         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2310         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2311         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2312
2313         /* Update maximum packet length */
2314         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2315                 E1000_WRITE_REG(hw, E1000_RLPML,
2316                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2317                                                 2 * VLAN_TAG_SIZE);
2318 }
2319
2320 static void
2321 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2322 {
2323         if(mask & ETH_VLAN_STRIP_MASK){
2324                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2325                         igb_vlan_hw_strip_enable(dev);
2326                 else
2327                         igb_vlan_hw_strip_disable(dev);
2328         }
2329
2330         if(mask & ETH_VLAN_FILTER_MASK){
2331                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2332                         igb_vlan_hw_filter_enable(dev);
2333                 else
2334                         igb_vlan_hw_filter_disable(dev);
2335         }
2336
2337         if(mask & ETH_VLAN_EXTEND_MASK){
2338                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2339                         igb_vlan_hw_extend_enable(dev);
2340                 else
2341                         igb_vlan_hw_extend_disable(dev);
2342         }
2343 }
2344
2345
2346 /**
2347  * It enables the interrupt mask and then enable the interrupt.
2348  *
2349  * @param dev
2350  *  Pointer to struct rte_eth_dev.
2351  *
2352  * @return
2353  *  - On success, zero.
2354  *  - On failure, a negative value.
2355  */
2356 static int
2357 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2358 {
2359         struct e1000_interrupt *intr =
2360                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2361
2362         intr->mask |= E1000_ICR_LSC;
2363
2364         return 0;
2365 }
2366
2367 /* It clears the interrupt causes and enables the interrupt.
2368  * It will be called once only during nic initialized.
2369  *
2370  * @param dev
2371  *  Pointer to struct rte_eth_dev.
2372  *
2373  * @return
2374  *  - On success, zero.
2375  *  - On failure, a negative value.
2376  */
2377 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2378 {
2379         uint32_t mask, regval;
2380         struct e1000_hw *hw =
2381                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         struct rte_eth_dev_info dev_info;
2383
2384         memset(&dev_info, 0, sizeof(dev_info));
2385         eth_igb_infos_get(dev, &dev_info);
2386
2387         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2388         regval = E1000_READ_REG(hw, E1000_EIMS);
2389         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2390
2391         return 0;
2392 }
2393
2394 /*
2395  * It reads ICR and gets interrupt causes, check it and set a bit flag
2396  * to update link status.
2397  *
2398  * @param dev
2399  *  Pointer to struct rte_eth_dev.
2400  *
2401  * @return
2402  *  - On success, zero.
2403  *  - On failure, a negative value.
2404  */
2405 static int
2406 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2407 {
2408         uint32_t icr;
2409         struct e1000_hw *hw =
2410                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2411         struct e1000_interrupt *intr =
2412                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2413
2414         igb_intr_disable(hw);
2415
2416         /* read-on-clear nic registers here */
2417         icr = E1000_READ_REG(hw, E1000_ICR);
2418
2419         intr->flags = 0;
2420         if (icr & E1000_ICR_LSC) {
2421                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2422         }
2423
2424         if (icr & E1000_ICR_VMMB)
2425                 intr->flags |= E1000_FLAG_MAILBOX;
2426
2427         return 0;
2428 }
2429
2430 /*
2431  * It executes link_update after knowing an interrupt is prsent.
2432  *
2433  * @param dev
2434  *  Pointer to struct rte_eth_dev.
2435  *
2436  * @return
2437  *  - On success, zero.
2438  *  - On failure, a negative value.
2439  */
2440 static int
2441 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2442 {
2443         struct e1000_hw *hw =
2444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445         struct e1000_interrupt *intr =
2446                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2447         uint32_t tctl, rctl;
2448         struct rte_eth_link link;
2449         int ret;
2450
2451         if (intr->flags & E1000_FLAG_MAILBOX) {
2452                 igb_pf_mbx_process(dev);
2453                 intr->flags &= ~E1000_FLAG_MAILBOX;
2454         }
2455
2456         igb_intr_enable(dev);
2457         rte_intr_enable(&(dev->pci_dev->intr_handle));
2458
2459         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2460                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2461
2462                 /* set get_link_status to check register later */
2463                 hw->mac.get_link_status = 1;
2464                 ret = eth_igb_link_update(dev, 0);
2465
2466                 /* check if link has changed */
2467                 if (ret < 0)
2468                         return 0;
2469
2470                 memset(&link, 0, sizeof(link));
2471                 rte_igb_dev_atomic_read_link_status(dev, &link);
2472                 if (link.link_status) {
2473                         PMD_INIT_LOG(INFO,
2474                                      " Port %d: Link Up - speed %u Mbps - %s",
2475                                      dev->data->port_id,
2476                                      (unsigned)link.link_speed,
2477                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2478                                      "full-duplex" : "half-duplex");
2479                 } else {
2480                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2481                                      dev->data->port_id);
2482                 }
2483
2484                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2485                              dev->pci_dev->addr.domain,
2486                              dev->pci_dev->addr.bus,
2487                              dev->pci_dev->addr.devid,
2488                              dev->pci_dev->addr.function);
2489                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2490                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2491                 if (link.link_status) {
2492                         /* enable Tx/Rx */
2493                         tctl |= E1000_TCTL_EN;
2494                         rctl |= E1000_RCTL_EN;
2495                 } else {
2496                         /* disable Tx/Rx */
2497                         tctl &= ~E1000_TCTL_EN;
2498                         rctl &= ~E1000_RCTL_EN;
2499                 }
2500                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2501                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2502                 E1000_WRITE_FLUSH(hw);
2503                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2504         }
2505
2506         return 0;
2507 }
2508
2509 /**
2510  * Interrupt handler which shall be registered at first.
2511  *
2512  * @param handle
2513  *  Pointer to interrupt handle.
2514  * @param param
2515  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2516  *
2517  * @return
2518  *  void
2519  */
2520 static void
2521 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2522                                                         void *param)
2523 {
2524         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2525
2526         eth_igb_interrupt_get_status(dev);
2527         eth_igb_interrupt_action(dev);
2528 }
2529
2530 static int
2531 eth_igb_led_on(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw;
2534
2535         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2537 }
2538
2539 static int
2540 eth_igb_led_off(struct rte_eth_dev *dev)
2541 {
2542         struct e1000_hw *hw;
2543
2544         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2545         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2546 }
2547
2548 static int
2549 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2550 {
2551         struct e1000_hw *hw;
2552         uint32_t ctrl;
2553         int tx_pause;
2554         int rx_pause;
2555
2556         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2557         fc_conf->pause_time = hw->fc.pause_time;
2558         fc_conf->high_water = hw->fc.high_water;
2559         fc_conf->low_water = hw->fc.low_water;
2560         fc_conf->send_xon = hw->fc.send_xon;
2561         fc_conf->autoneg = hw->mac.autoneg;
2562
2563         /*
2564          * Return rx_pause and tx_pause status according to actual setting of
2565          * the TFCE and RFCE bits in the CTRL register.
2566          */
2567         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2568         if (ctrl & E1000_CTRL_TFCE)
2569                 tx_pause = 1;
2570         else
2571                 tx_pause = 0;
2572
2573         if (ctrl & E1000_CTRL_RFCE)
2574                 rx_pause = 1;
2575         else
2576                 rx_pause = 0;
2577
2578         if (rx_pause && tx_pause)
2579                 fc_conf->mode = RTE_FC_FULL;
2580         else if (rx_pause)
2581                 fc_conf->mode = RTE_FC_RX_PAUSE;
2582         else if (tx_pause)
2583                 fc_conf->mode = RTE_FC_TX_PAUSE;
2584         else
2585                 fc_conf->mode = RTE_FC_NONE;
2586
2587         return 0;
2588 }
2589
2590 static int
2591 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2592 {
2593         struct e1000_hw *hw;
2594         int err;
2595         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2596                 e1000_fc_none,
2597                 e1000_fc_rx_pause,
2598                 e1000_fc_tx_pause,
2599                 e1000_fc_full
2600         };
2601         uint32_t rx_buf_size;
2602         uint32_t max_high_water;
2603         uint32_t rctl;
2604
2605         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         if (fc_conf->autoneg != hw->mac.autoneg)
2607                 return -ENOTSUP;
2608         rx_buf_size = igb_get_rx_buffer_size(hw);
2609         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2610
2611         /* At least reserve one Ethernet frame for watermark */
2612         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2613         if ((fc_conf->high_water > max_high_water) ||
2614             (fc_conf->high_water < fc_conf->low_water)) {
2615                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2616                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2617                 return -EINVAL;
2618         }
2619
2620         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2621         hw->fc.pause_time     = fc_conf->pause_time;
2622         hw->fc.high_water     = fc_conf->high_water;
2623         hw->fc.low_water      = fc_conf->low_water;
2624         hw->fc.send_xon       = fc_conf->send_xon;
2625
2626         err = e1000_setup_link_generic(hw);
2627         if (err == E1000_SUCCESS) {
2628
2629                 /* check if we want to forward MAC frames - driver doesn't have native
2630                  * capability to do that, so we'll write the registers ourselves */
2631
2632                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2633
2634                 /* set or clear MFLCN.PMCF bit depending on configuration */
2635                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2636                         rctl |= E1000_RCTL_PMCF;
2637                 else
2638                         rctl &= ~E1000_RCTL_PMCF;
2639
2640                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2641                 E1000_WRITE_FLUSH(hw);
2642
2643                 return 0;
2644         }
2645
2646         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2647         return -EIO;
2648 }
2649
2650 #define E1000_RAH_POOLSEL_SHIFT      (18)
2651 static void
2652 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2653                 uint32_t index, __rte_unused uint32_t pool)
2654 {
2655         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         uint32_t rah;
2657
2658         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2659         rah = E1000_READ_REG(hw, E1000_RAH(index));
2660         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2661         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2662 }
2663
2664 static void
2665 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2666 {
2667         uint8_t addr[ETHER_ADDR_LEN];
2668         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669
2670         memset(addr, 0, sizeof(addr));
2671
2672         e1000_rar_set(hw, addr, index);
2673 }
2674
2675 static void
2676 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2677                                 struct ether_addr *addr)
2678 {
2679         eth_igb_rar_clear(dev, 0);
2680
2681         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2682 }
2683 /*
2684  * Virtual Function operations
2685  */
2686 static void
2687 igbvf_intr_disable(struct e1000_hw *hw)
2688 {
2689         PMD_INIT_FUNC_TRACE();
2690
2691         /* Clear interrupt mask to stop from interrupts being generated */
2692         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2693
2694         E1000_WRITE_FLUSH(hw);
2695 }
2696
2697 static void
2698 igbvf_stop_adapter(struct rte_eth_dev *dev)
2699 {
2700         u32 reg_val;
2701         u16 i;
2702         struct rte_eth_dev_info dev_info;
2703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704
2705         memset(&dev_info, 0, sizeof(dev_info));
2706         eth_igbvf_infos_get(dev, &dev_info);
2707
2708         /* Clear interrupt mask to stop from interrupts being generated */
2709         igbvf_intr_disable(hw);
2710
2711         /* Clear any pending interrupts, flush previous writes */
2712         E1000_READ_REG(hw, E1000_EICR);
2713
2714         /* Disable the transmit unit.  Each queue must be disabled. */
2715         for (i = 0; i < dev_info.max_tx_queues; i++)
2716                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2717
2718         /* Disable the receive unit by stopping each queue */
2719         for (i = 0; i < dev_info.max_rx_queues; i++) {
2720                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2721                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2722                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2723                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2724                         ;
2725         }
2726
2727         /* flush all queues disables */
2728         E1000_WRITE_FLUSH(hw);
2729         msec_delay(2);
2730 }
2731
2732 static int eth_igbvf_link_update(struct e1000_hw *hw)
2733 {
2734         struct e1000_mbx_info *mbx = &hw->mbx;
2735         struct e1000_mac_info *mac = &hw->mac;
2736         int ret_val = E1000_SUCCESS;
2737
2738         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2739
2740         /*
2741          * We only want to run this if there has been a rst asserted.
2742          * in this case that could mean a link change, device reset,
2743          * or a virtual function reset
2744          */
2745
2746         /* If we were hit with a reset or timeout drop the link */
2747         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2748                 mac->get_link_status = TRUE;
2749
2750         if (!mac->get_link_status)
2751                 goto out;
2752
2753         /* if link status is down no point in checking to see if pf is up */
2754         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2755                 goto out;
2756
2757         /* if we passed all the tests above then the link is up and we no
2758          * longer need to check for link */
2759         mac->get_link_status = FALSE;
2760
2761 out:
2762         return ret_val;
2763 }
2764
2765
2766 static int
2767 igbvf_dev_configure(struct rte_eth_dev *dev)
2768 {
2769         struct rte_eth_conf* conf = &dev->data->dev_conf;
2770
2771         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2772                      dev->data->port_id);
2773
2774         /*
2775          * VF has no ability to enable/disable HW CRC
2776          * Keep the persistent behavior the same as Host PF
2777          */
2778 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2779         if (!conf->rxmode.hw_strip_crc) {
2780                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2781                 conf->rxmode.hw_strip_crc = 1;
2782         }
2783 #else
2784         if (conf->rxmode.hw_strip_crc) {
2785                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2786                 conf->rxmode.hw_strip_crc = 0;
2787         }
2788 #endif
2789
2790         return 0;
2791 }
2792
2793 static int
2794 igbvf_dev_start(struct rte_eth_dev *dev)
2795 {
2796         struct e1000_hw *hw =
2797                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         struct e1000_adapter *adapter =
2799                 E1000_DEV_PRIVATE(dev->data->dev_private);
2800         int ret;
2801
2802         PMD_INIT_FUNC_TRACE();
2803
2804         hw->mac.ops.reset_hw(hw);
2805         adapter->stopped = 0;
2806
2807         /* Set all vfta */
2808         igbvf_set_vfta_all(dev,1);
2809
2810         eth_igbvf_tx_init(dev);
2811
2812         /* This can fail when allocating mbufs for descriptor rings */
2813         ret = eth_igbvf_rx_init(dev);
2814         if (ret) {
2815                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2816                 igb_dev_clear_queues(dev);
2817                 return ret;
2818         }
2819
2820         return 0;
2821 }
2822
2823 static void
2824 igbvf_dev_stop(struct rte_eth_dev *dev)
2825 {
2826         PMD_INIT_FUNC_TRACE();
2827
2828         igbvf_stop_adapter(dev);
2829
2830         /*
2831           * Clear what we set, but we still keep shadow_vfta to
2832           * restore after device starts
2833           */
2834         igbvf_set_vfta_all(dev,0);
2835
2836         igb_dev_clear_queues(dev);
2837 }
2838
2839 static void
2840 igbvf_dev_close(struct rte_eth_dev *dev)
2841 {
2842         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct e1000_adapter *adapter =
2844                 E1000_DEV_PRIVATE(dev->data->dev_private);
2845         struct ether_addr addr;
2846
2847         PMD_INIT_FUNC_TRACE();
2848
2849         e1000_reset_hw(hw);
2850
2851         igbvf_dev_stop(dev);
2852         adapter->stopped = 1;
2853         igb_dev_free_queues(dev);
2854
2855         /**
2856          * reprogram the RAR with a zero mac address,
2857          * to ensure that the VF traffic goes to the PF
2858          * after stop, close and detach of the VF.
2859          **/
2860
2861         memset(&addr, 0, sizeof(addr));
2862         igbvf_default_mac_addr_set(dev, &addr);
2863 }
2864
2865 static void
2866 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2867 {
2868         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2869
2870         /* Set both unicast and multicast promisc */
2871         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2872 }
2873
2874 static void
2875 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2876 {
2877         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878
2879         /* If in allmulticast mode leave multicast promisc */
2880         if (dev->data->all_multicast == 1)
2881                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2882         else
2883                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2884 }
2885
2886 static void
2887 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2888 {
2889         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890
2891         /* In promiscuous mode multicast promisc already set */
2892         if (dev->data->promiscuous == 0)
2893                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2894 }
2895
2896 static void
2897 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2898 {
2899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900
2901         /* In promiscuous mode leave multicast promisc enabled */
2902         if (dev->data->promiscuous == 0)
2903                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2904 }
2905
2906 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2907 {
2908         struct e1000_mbx_info *mbx = &hw->mbx;
2909         uint32_t msgbuf[2];
2910         s32 err;
2911
2912         /* After set vlan, vlan strip will also be enabled in igb driver*/
2913         msgbuf[0] = E1000_VF_SET_VLAN;
2914         msgbuf[1] = vid;
2915         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2916         if (on)
2917                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2918
2919         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2920         if (err)
2921                 goto mbx_err;
2922
2923         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2924         if (err)
2925                 goto mbx_err;
2926
2927         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2928         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2929                 err = -EINVAL;
2930
2931 mbx_err:
2932         return err;
2933 }
2934
2935 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2936 {
2937         struct e1000_hw *hw =
2938                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939         struct e1000_vfta * shadow_vfta =
2940                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2941         int i = 0, j = 0, vfta = 0, mask = 1;
2942
2943         for (i = 0; i < IGB_VFTA_SIZE; i++){
2944                 vfta = shadow_vfta->vfta[i];
2945                 if(vfta){
2946                         mask = 1;
2947                         for (j = 0; j < 32; j++){
2948                                 if(vfta & mask)
2949                                         igbvf_set_vfta(hw,
2950                                                 (uint16_t)((i<<5)+j), on);
2951                                 mask<<=1;
2952                         }
2953                 }
2954         }
2955
2956 }
2957
2958 static int
2959 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2960 {
2961         struct e1000_hw *hw =
2962                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963         struct e1000_vfta * shadow_vfta =
2964                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2965         uint32_t vid_idx = 0;
2966         uint32_t vid_bit = 0;
2967         int ret = 0;
2968
2969         PMD_INIT_FUNC_TRACE();
2970
2971         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2972         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2973         if(ret){
2974                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2975                 return ret;
2976         }
2977         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2978         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2979
2980         /*Save what we set and retore it after device reset*/
2981         if (on)
2982                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2983         else
2984                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2985
2986         return 0;
2987 }
2988
2989 static void
2990 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2991 {
2992         struct e1000_hw *hw =
2993                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994
2995         /* index is not used by rar_set() */
2996         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2997 }
2998
2999
3000 static int
3001 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3002                         struct rte_eth_rss_reta_entry64 *reta_conf,
3003                         uint16_t reta_size)
3004 {
3005         uint8_t i, j, mask;
3006         uint32_t reta, r;
3007         uint16_t idx, shift;
3008         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009
3010         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3011                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3012                         "(%d) doesn't match the number hardware can supported "
3013                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3014                 return -EINVAL;
3015         }
3016
3017         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3018                 idx = i / RTE_RETA_GROUP_SIZE;
3019                 shift = i % RTE_RETA_GROUP_SIZE;
3020                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3021                                                 IGB_4_BIT_MASK);
3022                 if (!mask)
3023                         continue;
3024                 if (mask == IGB_4_BIT_MASK)
3025                         r = 0;
3026                 else
3027                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3028                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3029                         if (mask & (0x1 << j))
3030                                 reta |= reta_conf[idx].reta[shift + j] <<
3031                                                         (CHAR_BIT * j);
3032                         else
3033                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3034                 }
3035                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3036         }
3037
3038         return 0;
3039 }
3040
3041 static int
3042 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3043                        struct rte_eth_rss_reta_entry64 *reta_conf,
3044                        uint16_t reta_size)
3045 {
3046         uint8_t i, j, mask;
3047         uint32_t reta;
3048         uint16_t idx, shift;
3049         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050
3051         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3052                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3053                         "(%d) doesn't match the number hardware can supported "
3054                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3055                 return -EINVAL;
3056         }
3057
3058         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3059                 idx = i / RTE_RETA_GROUP_SIZE;
3060                 shift = i % RTE_RETA_GROUP_SIZE;
3061                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3062                                                 IGB_4_BIT_MASK);
3063                 if (!mask)
3064                         continue;
3065                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3066                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3067                         if (mask & (0x1 << j))
3068                                 reta_conf[idx].reta[shift + j] =
3069                                         ((reta >> (CHAR_BIT * j)) &
3070                                                 IGB_8_BIT_MASK);
3071                 }
3072         }
3073
3074         return 0;
3075 }
3076
3077 #define MAC_TYPE_FILTER_SUP(type)    do {\
3078         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3079                 (type) != e1000_82576)\
3080                 return -ENOTSUP;\
3081 } while (0)
3082
3083 static int
3084 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3085                         struct rte_eth_syn_filter *filter,
3086                         bool add)
3087 {
3088         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089         uint32_t synqf, rfctl;
3090
3091         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3092                 return -EINVAL;
3093
3094         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3095
3096         if (add) {
3097                 if (synqf & E1000_SYN_FILTER_ENABLE)
3098                         return -EINVAL;
3099
3100                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3101                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3102
3103                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3104                 if (filter->hig_pri)
3105                         rfctl |= E1000_RFCTL_SYNQFP;
3106                 else
3107                         rfctl &= ~E1000_RFCTL_SYNQFP;
3108
3109                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3110         } else {
3111                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3112                         return -ENOENT;
3113                 synqf = 0;
3114         }
3115
3116         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3117         E1000_WRITE_FLUSH(hw);
3118         return 0;
3119 }
3120
3121 static int
3122 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3123                         struct rte_eth_syn_filter *filter)
3124 {
3125         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126         uint32_t synqf, rfctl;
3127
3128         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3129         if (synqf & E1000_SYN_FILTER_ENABLE) {
3130                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3131                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3132                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3133                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3134                 return 0;
3135         }
3136
3137         return -ENOENT;
3138 }
3139
3140 static int
3141 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3142                         enum rte_filter_op filter_op,
3143                         void *arg)
3144 {
3145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146         int ret;
3147
3148         MAC_TYPE_FILTER_SUP(hw->mac.type);
3149
3150         if (filter_op == RTE_ETH_FILTER_NOP)
3151                 return 0;
3152
3153         if (arg == NULL) {
3154                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3155                             filter_op);
3156                 return -EINVAL;
3157         }
3158
3159         switch (filter_op) {
3160         case RTE_ETH_FILTER_ADD:
3161                 ret = eth_igb_syn_filter_set(dev,
3162                                 (struct rte_eth_syn_filter *)arg,
3163                                 TRUE);
3164                 break;
3165         case RTE_ETH_FILTER_DELETE:
3166                 ret = eth_igb_syn_filter_set(dev,
3167                                 (struct rte_eth_syn_filter *)arg,
3168                                 FALSE);
3169                 break;
3170         case RTE_ETH_FILTER_GET:
3171                 ret = eth_igb_syn_filter_get(dev,
3172                                 (struct rte_eth_syn_filter *)arg);
3173                 break;
3174         default:
3175                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3176                 ret = -EINVAL;
3177                 break;
3178         }
3179
3180         return ret;
3181 }
3182
3183 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3184         if ((type) != e1000_82580 && (type) != e1000_i350)\
3185                 return -ENOSYS; \
3186 } while (0)
3187
3188 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3189 static inline int
3190 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3191                         struct e1000_2tuple_filter_info *filter_info)
3192 {
3193         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3194                 return -EINVAL;
3195         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3196                 return -EINVAL;  /* filter index is out of range. */
3197         if (filter->tcp_flags > TCP_FLAG_ALL)
3198                 return -EINVAL;  /* flags is invalid. */
3199
3200         switch (filter->dst_port_mask) {
3201         case UINT16_MAX:
3202                 filter_info->dst_port_mask = 0;
3203                 filter_info->dst_port = filter->dst_port;
3204                 break;
3205         case 0:
3206                 filter_info->dst_port_mask = 1;
3207                 break;
3208         default:
3209                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3210                 return -EINVAL;
3211         }
3212
3213         switch (filter->proto_mask) {
3214         case UINT8_MAX:
3215                 filter_info->proto_mask = 0;
3216                 filter_info->proto = filter->proto;
3217                 break;
3218         case 0:
3219                 filter_info->proto_mask = 1;
3220                 break;
3221         default:
3222                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3223                 return -EINVAL;
3224         }
3225
3226         filter_info->priority = (uint8_t)filter->priority;
3227         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3228                 filter_info->tcp_flags = filter->tcp_flags;
3229         else
3230                 filter_info->tcp_flags = 0;
3231
3232         return 0;
3233 }
3234
3235 static inline struct e1000_2tuple_filter *
3236 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3237                         struct e1000_2tuple_filter_info *key)
3238 {
3239         struct e1000_2tuple_filter *it;
3240
3241         TAILQ_FOREACH(it, filter_list, entries) {
3242                 if (memcmp(key, &it->filter_info,
3243                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3244                         return it;
3245                 }
3246         }
3247         return NULL;
3248 }
3249
3250 /*
3251  * igb_add_2tuple_filter - add a 2tuple filter
3252  *
3253  * @param
3254  * dev: Pointer to struct rte_eth_dev.
3255  * ntuple_filter: ponter to the filter that will be added.
3256  *
3257  * @return
3258  *    - On success, zero.
3259  *    - On failure, a negative value.
3260  */
3261 static int
3262 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3263                         struct rte_eth_ntuple_filter *ntuple_filter)
3264 {
3265         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3266         struct e1000_filter_info *filter_info =
3267                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3268         struct e1000_2tuple_filter *filter;
3269         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3270         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3271         int i, ret;
3272
3273         filter = rte_zmalloc("e1000_2tuple_filter",
3274                         sizeof(struct e1000_2tuple_filter), 0);
3275         if (filter == NULL)
3276                 return -ENOMEM;
3277
3278         ret = ntuple_filter_to_2tuple(ntuple_filter,
3279                                       &filter->filter_info);
3280         if (ret < 0) {
3281                 rte_free(filter);
3282                 return ret;
3283         }
3284         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3285                                          &filter->filter_info) != NULL) {
3286                 PMD_DRV_LOG(ERR, "filter exists.");
3287                 rte_free(filter);
3288                 return -EEXIST;
3289         }
3290         filter->queue = ntuple_filter->queue;
3291
3292         /*
3293          * look for an unused 2tuple filter index,
3294          * and insert the filter to list.
3295          */
3296         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3297                 if (!(filter_info->twotuple_mask & (1 << i))) {
3298                         filter_info->twotuple_mask |= 1 << i;
3299                         filter->index = i;
3300                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3301                                           filter,
3302                                           entries);
3303                         break;
3304                 }
3305         }
3306         if (i >= E1000_MAX_TTQF_FILTERS) {
3307                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3308                 rte_free(filter);
3309                 return -ENOSYS;
3310         }
3311
3312         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3313         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3314                 imir |= E1000_IMIR_PORT_BP;
3315         else
3316                 imir &= ~E1000_IMIR_PORT_BP;
3317
3318         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3319
3320         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3321         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3322         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3323         if (filter->filter_info.proto_mask == 0)
3324                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3325
3326         /* tcp flags bits setting. */
3327         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3328                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3329                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3330                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3331                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3332                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3333                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3334                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3335                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3336                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3337                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3338                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3339                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3340         } else
3341                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3342         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3343         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3344         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3345         return 0;
3346 }
3347
3348 /*
3349  * igb_remove_2tuple_filter - remove a 2tuple filter
3350  *
3351  * @param
3352  * dev: Pointer to struct rte_eth_dev.
3353  * ntuple_filter: ponter to the filter that will be removed.
3354  *
3355  * @return
3356  *    - On success, zero.
3357  *    - On failure, a negative value.
3358  */
3359 static int
3360 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3361                         struct rte_eth_ntuple_filter *ntuple_filter)
3362 {
3363         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364         struct e1000_filter_info *filter_info =
3365                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3366         struct e1000_2tuple_filter_info filter_2tuple;
3367         struct e1000_2tuple_filter *filter;
3368         int ret;
3369
3370         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3371         ret = ntuple_filter_to_2tuple(ntuple_filter,
3372                                       &filter_2tuple);
3373         if (ret < 0)
3374                 return ret;
3375
3376         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3377                                          &filter_2tuple);
3378         if (filter == NULL) {
3379                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3380                 return -ENOENT;
3381         }
3382
3383         filter_info->twotuple_mask &= ~(1 << filter->index);
3384         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3385         rte_free(filter);
3386
3387         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3388         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3389         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3390         return 0;
3391 }
3392
3393 static inline struct e1000_flex_filter *
3394 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3395                         struct e1000_flex_filter_info *key)
3396 {
3397         struct e1000_flex_filter *it;
3398
3399         TAILQ_FOREACH(it, filter_list, entries) {
3400                 if (memcmp(key, &it->filter_info,
3401                         sizeof(struct e1000_flex_filter_info)) == 0)
3402                         return it;
3403         }
3404
3405         return NULL;
3406 }
3407
3408 static int
3409 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3410                         struct rte_eth_flex_filter *filter,
3411                         bool add)
3412 {
3413         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414         struct e1000_filter_info *filter_info =
3415                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3416         struct e1000_flex_filter *flex_filter, *it;
3417         uint32_t wufc, queueing, mask;
3418         uint32_t reg_off;
3419         uint8_t shift, i, j = 0;
3420
3421         flex_filter = rte_zmalloc("e1000_flex_filter",
3422                         sizeof(struct e1000_flex_filter), 0);
3423         if (flex_filter == NULL)
3424                 return -ENOMEM;
3425
3426         flex_filter->filter_info.len = filter->len;
3427         flex_filter->filter_info.priority = filter->priority;
3428         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3429         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3430                 mask = 0;
3431                 /* reverse bits in flex filter's mask*/
3432                 for (shift = 0; shift < CHAR_BIT; shift++) {
3433                         if (filter->mask[i] & (0x01 << shift))
3434                                 mask |= (0x80 >> shift);
3435                 }
3436                 flex_filter->filter_info.mask[i] = mask;
3437         }
3438
3439         wufc = E1000_READ_REG(hw, E1000_WUFC);
3440         if (flex_filter->index < E1000_MAX_FHFT)
3441                 reg_off = E1000_FHFT(flex_filter->index);
3442         else
3443                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3444
3445         if (add) {
3446                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3447                                 &flex_filter->filter_info) != NULL) {
3448                         PMD_DRV_LOG(ERR, "filter exists.");
3449                         rte_free(flex_filter);
3450                         return -EEXIST;
3451                 }
3452                 flex_filter->queue = filter->queue;
3453                 /*
3454                  * look for an unused flex filter index
3455                  * and insert the filter into the list.
3456                  */
3457                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3458                         if (!(filter_info->flex_mask & (1 << i))) {
3459                                 filter_info->flex_mask |= 1 << i;
3460                                 flex_filter->index = i;
3461                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3462                                         flex_filter,
3463                                         entries);
3464                                 break;
3465                         }
3466                 }
3467                 if (i >= E1000_MAX_FLEX_FILTERS) {
3468                         PMD_DRV_LOG(ERR, "flex filters are full.");
3469                         rte_free(flex_filter);
3470                         return -ENOSYS;
3471                 }
3472
3473                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3474                                 (E1000_WUFC_FLX0 << flex_filter->index));
3475                 queueing = filter->len |
3476                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3477                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3478                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3479                                 queueing);
3480                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3481                         E1000_WRITE_REG(hw, reg_off,
3482                                         flex_filter->filter_info.dwords[j]);
3483                         reg_off += sizeof(uint32_t);
3484                         E1000_WRITE_REG(hw, reg_off,
3485                                         flex_filter->filter_info.dwords[++j]);
3486                         reg_off += sizeof(uint32_t);
3487                         E1000_WRITE_REG(hw, reg_off,
3488                                 (uint32_t)flex_filter->filter_info.mask[i]);
3489                         reg_off += sizeof(uint32_t) * 2;
3490                         ++j;
3491                 }
3492         } else {
3493                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3494                                 &flex_filter->filter_info);
3495                 if (it == NULL) {
3496                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3497                         rte_free(flex_filter);
3498                         return -ENOENT;
3499                 }
3500
3501                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3502                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3503                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3504                         (~(E1000_WUFC_FLX0 << it->index)));
3505
3506                 filter_info->flex_mask &= ~(1 << it->index);
3507                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3508                 rte_free(it);
3509                 rte_free(flex_filter);
3510         }
3511
3512         return 0;
3513 }
3514
3515 static int
3516 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3517                         struct rte_eth_flex_filter *filter)
3518 {
3519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520         struct e1000_filter_info *filter_info =
3521                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3522         struct e1000_flex_filter flex_filter, *it;
3523         uint32_t wufc, queueing, wufc_en = 0;
3524
3525         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3526         flex_filter.filter_info.len = filter->len;
3527         flex_filter.filter_info.priority = filter->priority;
3528         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3529         memcpy(flex_filter.filter_info.mask, filter->mask,
3530                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3531
3532         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3533                                 &flex_filter.filter_info);
3534         if (it == NULL) {
3535                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3536                 return -ENOENT;
3537         }
3538
3539         wufc = E1000_READ_REG(hw, E1000_WUFC);
3540         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3541
3542         if ((wufc & wufc_en) == wufc_en) {
3543                 uint32_t reg_off = 0;
3544                 if (it->index < E1000_MAX_FHFT)
3545                         reg_off = E1000_FHFT(it->index);
3546                 else
3547                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3548
3549                 queueing = E1000_READ_REG(hw,
3550                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3551                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3552                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3553                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3554                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3555                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3556                 return 0;
3557         }
3558         return -ENOENT;
3559 }
3560
3561 static int
3562 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3563                         enum rte_filter_op filter_op,
3564                         void *arg)
3565 {
3566         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567         struct rte_eth_flex_filter *filter;
3568         int ret = 0;
3569
3570         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3571
3572         if (filter_op == RTE_ETH_FILTER_NOP)
3573                 return ret;
3574
3575         if (arg == NULL) {
3576                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3577                             filter_op);
3578                 return -EINVAL;
3579         }
3580
3581         filter = (struct rte_eth_flex_filter *)arg;
3582         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3583             || filter->len % sizeof(uint64_t) != 0) {
3584                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3585                 return -EINVAL;
3586         }
3587         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3588                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3589                 return -EINVAL;
3590         }
3591
3592         switch (filter_op) {
3593         case RTE_ETH_FILTER_ADD:
3594                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3595                 break;
3596         case RTE_ETH_FILTER_DELETE:
3597                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3598                 break;
3599         case RTE_ETH_FILTER_GET:
3600                 ret = eth_igb_get_flex_filter(dev, filter);
3601                 break;
3602         default:
3603                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3604                 ret = -EINVAL;
3605                 break;
3606         }
3607
3608         return ret;
3609 }
3610
3611 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3612 static inline int
3613 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3614                         struct e1000_5tuple_filter_info *filter_info)
3615 {
3616         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3617                 return -EINVAL;
3618         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3619                 return -EINVAL;  /* filter index is out of range. */
3620         if (filter->tcp_flags > TCP_FLAG_ALL)
3621                 return -EINVAL;  /* flags is invalid. */
3622
3623         switch (filter->dst_ip_mask) {
3624         case UINT32_MAX:
3625                 filter_info->dst_ip_mask = 0;
3626                 filter_info->dst_ip = filter->dst_ip;
3627                 break;
3628         case 0:
3629                 filter_info->dst_ip_mask = 1;
3630                 break;
3631         default:
3632                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3633                 return -EINVAL;
3634         }
3635
3636         switch (filter->src_ip_mask) {
3637         case UINT32_MAX:
3638                 filter_info->src_ip_mask = 0;
3639                 filter_info->src_ip = filter->src_ip;
3640                 break;
3641         case 0:
3642                 filter_info->src_ip_mask = 1;
3643                 break;
3644         default:
3645                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3646                 return -EINVAL;
3647         }
3648
3649         switch (filter->dst_port_mask) {
3650         case UINT16_MAX:
3651                 filter_info->dst_port_mask = 0;
3652                 filter_info->dst_port = filter->dst_port;
3653                 break;
3654         case 0:
3655                 filter_info->dst_port_mask = 1;
3656                 break;
3657         default:
3658                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3659                 return -EINVAL;
3660         }
3661
3662         switch (filter->src_port_mask) {
3663         case UINT16_MAX:
3664                 filter_info->src_port_mask = 0;
3665                 filter_info->src_port = filter->src_port;
3666                 break;
3667         case 0:
3668                 filter_info->src_port_mask = 1;
3669                 break;
3670         default:
3671                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3672                 return -EINVAL;
3673         }
3674
3675         switch (filter->proto_mask) {
3676         case UINT8_MAX:
3677                 filter_info->proto_mask = 0;
3678                 filter_info->proto = filter->proto;
3679                 break;
3680         case 0:
3681                 filter_info->proto_mask = 1;
3682                 break;
3683         default:
3684                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3685                 return -EINVAL;
3686         }
3687
3688         filter_info->priority = (uint8_t)filter->priority;
3689         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3690                 filter_info->tcp_flags = filter->tcp_flags;
3691         else
3692                 filter_info->tcp_flags = 0;
3693
3694         return 0;
3695 }
3696
3697 static inline struct e1000_5tuple_filter *
3698 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3699                         struct e1000_5tuple_filter_info *key)
3700 {
3701         struct e1000_5tuple_filter *it;
3702
3703         TAILQ_FOREACH(it, filter_list, entries) {
3704                 if (memcmp(key, &it->filter_info,
3705                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3706                         return it;
3707                 }
3708         }
3709         return NULL;
3710 }
3711
3712 /*
3713  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3714  *
3715  * @param
3716  * dev: Pointer to struct rte_eth_dev.
3717  * ntuple_filter: ponter to the filter that will be added.
3718  *
3719  * @return
3720  *    - On success, zero.
3721  *    - On failure, a negative value.
3722  */
3723 static int
3724 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3725                         struct rte_eth_ntuple_filter *ntuple_filter)
3726 {
3727         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         struct e1000_filter_info *filter_info =
3729                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3730         struct e1000_5tuple_filter *filter;
3731         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3732         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3733         uint8_t i;
3734         int ret;
3735
3736         filter = rte_zmalloc("e1000_5tuple_filter",
3737                         sizeof(struct e1000_5tuple_filter), 0);
3738         if (filter == NULL)
3739                 return -ENOMEM;
3740
3741         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3742                                             &filter->filter_info);
3743         if (ret < 0) {
3744                 rte_free(filter);
3745                 return ret;
3746         }
3747
3748         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3749                                          &filter->filter_info) != NULL) {
3750                 PMD_DRV_LOG(ERR, "filter exists.");
3751                 rte_free(filter);
3752                 return -EEXIST;
3753         }
3754         filter->queue = ntuple_filter->queue;
3755
3756         /*
3757          * look for an unused 5tuple filter index,
3758          * and insert the filter to list.
3759          */
3760         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3761                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3762                         filter_info->fivetuple_mask |= 1 << i;
3763                         filter->index = i;
3764                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3765                                           filter,
3766                                           entries);
3767                         break;
3768                 }
3769         }
3770         if (i >= E1000_MAX_FTQF_FILTERS) {
3771                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3772                 rte_free(filter);
3773                 return -ENOSYS;
3774         }
3775
3776         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3777         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3778                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3779         if (filter->filter_info.dst_ip_mask == 0)
3780                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3781         if (filter->filter_info.src_port_mask == 0)
3782                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3783         if (filter->filter_info.proto_mask == 0)
3784                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3785         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3786                 E1000_FTQF_QUEUE_MASK;
3787         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3788         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3789         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3790         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3791
3792         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3793         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3794
3795         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3796         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3797                 imir |= E1000_IMIR_PORT_BP;
3798         else
3799                 imir &= ~E1000_IMIR_PORT_BP;
3800         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3801
3802         /* tcp flags bits setting. */
3803         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3804                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3805                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3806                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3807                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3808                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3809                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3810                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3811                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3812                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3813                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3814                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3815                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3816         } else
3817                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3818         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3819         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3820         return 0;
3821 }
3822
3823 /*
3824  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3825  *
3826  * @param
3827  * dev: Pointer to struct rte_eth_dev.
3828  * ntuple_filter: ponter to the filter that will be removed.
3829  *
3830  * @return
3831  *    - On success, zero.
3832  *    - On failure, a negative value.
3833  */
3834 static int
3835 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3836                                 struct rte_eth_ntuple_filter *ntuple_filter)
3837 {
3838         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3839         struct e1000_filter_info *filter_info =
3840                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3841         struct e1000_5tuple_filter_info filter_5tuple;
3842         struct e1000_5tuple_filter *filter;
3843         int ret;
3844
3845         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3846         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3847                                             &filter_5tuple);
3848         if (ret < 0)
3849                 return ret;
3850
3851         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3852                                          &filter_5tuple);
3853         if (filter == NULL) {
3854                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3855                 return -ENOENT;
3856         }
3857
3858         filter_info->fivetuple_mask &= ~(1 << filter->index);
3859         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3860         rte_free(filter);
3861
3862         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3863                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3864         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3865         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3866         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3867         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3868         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3869         return 0;
3870 }
3871
3872 static int
3873 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3874 {
3875         uint32_t rctl;
3876         struct e1000_hw *hw;
3877         struct rte_eth_dev_info dev_info;
3878         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3879                                      VLAN_TAG_SIZE);
3880
3881         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882
3883 #ifdef RTE_LIBRTE_82571_SUPPORT
3884         /* XXX: not bigger than max_rx_pktlen */
3885         if (hw->mac.type == e1000_82571)
3886                 return -ENOTSUP;
3887 #endif
3888         eth_igb_infos_get(dev, &dev_info);
3889
3890         /* check that mtu is within the allowed range */
3891         if ((mtu < ETHER_MIN_MTU) ||
3892             (frame_size > dev_info.max_rx_pktlen))
3893                 return -EINVAL;
3894
3895         /* refuse mtu that requires the support of scattered packets when this
3896          * feature has not been enabled before. */
3897         if (!dev->data->scattered_rx &&
3898             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3899                 return -EINVAL;
3900
3901         rctl = E1000_READ_REG(hw, E1000_RCTL);
3902
3903         /* switch to jumbo mode if needed */
3904         if (frame_size > ETHER_MAX_LEN) {
3905                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3906                 rctl |= E1000_RCTL_LPE;
3907         } else {
3908                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3909                 rctl &= ~E1000_RCTL_LPE;
3910         }
3911         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3912
3913         /* update max frame size */
3914         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3915
3916         E1000_WRITE_REG(hw, E1000_RLPML,
3917                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3918
3919         return 0;
3920 }
3921
3922 /*
3923  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3924  *
3925  * @param
3926  * dev: Pointer to struct rte_eth_dev.
3927  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3928  * add: if true, add filter, if false, remove filter
3929  *
3930  * @return
3931  *    - On success, zero.
3932  *    - On failure, a negative value.
3933  */
3934 static int
3935 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3936                         struct rte_eth_ntuple_filter *ntuple_filter,
3937                         bool add)
3938 {
3939         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940         int ret;
3941
3942         switch (ntuple_filter->flags) {
3943         case RTE_5TUPLE_FLAGS:
3944         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3945                 if (hw->mac.type != e1000_82576)
3946                         return -ENOTSUP;
3947                 if (add)
3948                         ret = igb_add_5tuple_filter_82576(dev,
3949                                                           ntuple_filter);
3950                 else
3951                         ret = igb_remove_5tuple_filter_82576(dev,
3952                                                              ntuple_filter);
3953                 break;
3954         case RTE_2TUPLE_FLAGS:
3955         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3956                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3957                         return -ENOTSUP;
3958                 if (add)
3959                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3960                 else
3961                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3962                 break;
3963         default:
3964                 ret = -EINVAL;
3965                 break;
3966         }
3967
3968         return ret;
3969 }
3970
3971 /*
3972  * igb_get_ntuple_filter - get a ntuple filter
3973  *
3974  * @param
3975  * dev: Pointer to struct rte_eth_dev.
3976  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3977  *
3978  * @return
3979  *    - On success, zero.
3980  *    - On failure, a negative value.
3981  */
3982 static int
3983 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3984                         struct rte_eth_ntuple_filter *ntuple_filter)
3985 {
3986         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3987         struct e1000_filter_info *filter_info =
3988                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3989         struct e1000_5tuple_filter_info filter_5tuple;
3990         struct e1000_2tuple_filter_info filter_2tuple;
3991         struct e1000_5tuple_filter *p_5tuple_filter;
3992         struct e1000_2tuple_filter *p_2tuple_filter;
3993         int ret;
3994
3995         switch (ntuple_filter->flags) {
3996         case RTE_5TUPLE_FLAGS:
3997         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3998                 if (hw->mac.type != e1000_82576)
3999                         return -ENOTSUP;
4000                 memset(&filter_5tuple,
4001                         0,
4002                         sizeof(struct e1000_5tuple_filter_info));
4003                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4004                                                     &filter_5tuple);
4005                 if (ret < 0)
4006                         return ret;
4007                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4008                                         &filter_info->fivetuple_list,
4009                                         &filter_5tuple);
4010                 if (p_5tuple_filter == NULL) {
4011                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4012                         return -ENOENT;
4013                 }
4014                 ntuple_filter->queue = p_5tuple_filter->queue;
4015                 break;
4016         case RTE_2TUPLE_FLAGS:
4017         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4018                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4019                         return -ENOTSUP;
4020                 memset(&filter_2tuple,
4021                         0,
4022                         sizeof(struct e1000_2tuple_filter_info));
4023                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4024                 if (ret < 0)
4025                         return ret;
4026                 p_2tuple_filter = igb_2tuple_filter_lookup(
4027                                         &filter_info->twotuple_list,
4028                                         &filter_2tuple);
4029                 if (p_2tuple_filter == NULL) {
4030                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4031                         return -ENOENT;
4032                 }
4033                 ntuple_filter->queue = p_2tuple_filter->queue;
4034                 break;
4035         default:
4036                 ret = -EINVAL;
4037                 break;
4038         }
4039
4040         return 0;
4041 }
4042
4043 /*
4044  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4045  * @dev: pointer to rte_eth_dev structure
4046  * @filter_op:operation will be taken.
4047  * @arg: a pointer to specific structure corresponding to the filter_op
4048  */
4049 static int
4050 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4051                                 enum rte_filter_op filter_op,
4052                                 void *arg)
4053 {
4054         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         int ret;
4056
4057         MAC_TYPE_FILTER_SUP(hw->mac.type);
4058
4059         if (filter_op == RTE_ETH_FILTER_NOP)
4060                 return 0;
4061
4062         if (arg == NULL) {
4063                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4064                             filter_op);
4065                 return -EINVAL;
4066         }
4067
4068         switch (filter_op) {
4069         case RTE_ETH_FILTER_ADD:
4070                 ret = igb_add_del_ntuple_filter(dev,
4071                         (struct rte_eth_ntuple_filter *)arg,
4072                         TRUE);
4073                 break;
4074         case RTE_ETH_FILTER_DELETE:
4075                 ret = igb_add_del_ntuple_filter(dev,
4076                         (struct rte_eth_ntuple_filter *)arg,
4077                         FALSE);
4078                 break;
4079         case RTE_ETH_FILTER_GET:
4080                 ret = igb_get_ntuple_filter(dev,
4081                         (struct rte_eth_ntuple_filter *)arg);
4082                 break;
4083         default:
4084                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4085                 ret = -EINVAL;
4086                 break;
4087         }
4088         return ret;
4089 }
4090
4091 static inline int
4092 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4093                         uint16_t ethertype)
4094 {
4095         int i;
4096
4097         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4098                 if (filter_info->ethertype_filters[i] == ethertype &&
4099                     (filter_info->ethertype_mask & (1 << i)))
4100                         return i;
4101         }
4102         return -1;
4103 }
4104
4105 static inline int
4106 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4107                         uint16_t ethertype)
4108 {
4109         int i;
4110
4111         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4112                 if (!(filter_info->ethertype_mask & (1 << i))) {
4113                         filter_info->ethertype_mask |= 1 << i;
4114                         filter_info->ethertype_filters[i] = ethertype;
4115                         return i;
4116                 }
4117         }
4118         return -1;
4119 }
4120
4121 static inline int
4122 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4123                         uint8_t idx)
4124 {
4125         if (idx >= E1000_MAX_ETQF_FILTERS)
4126                 return -1;
4127         filter_info->ethertype_mask &= ~(1 << idx);
4128         filter_info->ethertype_filters[idx] = 0;
4129         return idx;
4130 }
4131
4132
4133 static int
4134 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4135                         struct rte_eth_ethertype_filter *filter,
4136                         bool add)
4137 {
4138         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139         struct e1000_filter_info *filter_info =
4140                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4141         uint32_t etqf = 0;
4142         int ret;
4143
4144         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4145                 filter->ether_type == ETHER_TYPE_IPv6) {
4146                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4147                         " ethertype filter.", filter->ether_type);
4148                 return -EINVAL;
4149         }
4150
4151         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4152                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4153                 return -EINVAL;
4154         }
4155         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4156                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4157                 return -EINVAL;
4158         }
4159
4160         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4161         if (ret >= 0 && add) {
4162                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4163                             filter->ether_type);
4164                 return -EEXIST;
4165         }
4166         if (ret < 0 && !add) {
4167                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4168                             filter->ether_type);
4169                 return -ENOENT;
4170         }
4171
4172         if (add) {
4173                 ret = igb_ethertype_filter_insert(filter_info,
4174                         filter->ether_type);
4175                 if (ret < 0) {
4176                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4177                         return -ENOSYS;
4178                 }
4179
4180                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4181                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4182                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4183         } else {
4184                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4185                 if (ret < 0)
4186                         return -ENOSYS;
4187         }
4188         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4189         E1000_WRITE_FLUSH(hw);
4190
4191         return 0;
4192 }
4193
4194 static int
4195 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4196                         struct rte_eth_ethertype_filter *filter)
4197 {
4198         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199         struct e1000_filter_info *filter_info =
4200                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4201         uint32_t etqf;
4202         int ret;
4203
4204         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4205         if (ret < 0) {
4206                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4207                             filter->ether_type);
4208                 return -ENOENT;
4209         }
4210
4211         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4212         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4213                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4214                 filter->flags = 0;
4215                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4216                                 E1000_ETQF_QUEUE_SHIFT;
4217                 return 0;
4218         }
4219
4220         return -ENOENT;
4221 }
4222
4223 /*
4224  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4225  * @dev: pointer to rte_eth_dev structure
4226  * @filter_op:operation will be taken.
4227  * @arg: a pointer to specific structure corresponding to the filter_op
4228  */
4229 static int
4230 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4231                                 enum rte_filter_op filter_op,
4232                                 void *arg)
4233 {
4234         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235         int ret;
4236
4237         MAC_TYPE_FILTER_SUP(hw->mac.type);
4238
4239         if (filter_op == RTE_ETH_FILTER_NOP)
4240                 return 0;
4241
4242         if (arg == NULL) {
4243                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4244                             filter_op);
4245                 return -EINVAL;
4246         }
4247
4248         switch (filter_op) {
4249         case RTE_ETH_FILTER_ADD:
4250                 ret = igb_add_del_ethertype_filter(dev,
4251                         (struct rte_eth_ethertype_filter *)arg,
4252                         TRUE);
4253                 break;
4254         case RTE_ETH_FILTER_DELETE:
4255                 ret = igb_add_del_ethertype_filter(dev,
4256                         (struct rte_eth_ethertype_filter *)arg,
4257                         FALSE);
4258                 break;
4259         case RTE_ETH_FILTER_GET:
4260                 ret = igb_get_ethertype_filter(dev,
4261                         (struct rte_eth_ethertype_filter *)arg);
4262                 break;
4263         default:
4264                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4265                 ret = -EINVAL;
4266                 break;
4267         }
4268         return ret;
4269 }
4270
4271 static int
4272 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4273                      enum rte_filter_type filter_type,
4274                      enum rte_filter_op filter_op,
4275                      void *arg)
4276 {
4277         int ret = -EINVAL;
4278
4279         switch (filter_type) {
4280         case RTE_ETH_FILTER_NTUPLE:
4281                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4282                 break;
4283         case RTE_ETH_FILTER_ETHERTYPE:
4284                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4285                 break;
4286         case RTE_ETH_FILTER_SYN:
4287                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4288                 break;
4289         case RTE_ETH_FILTER_FLEXIBLE:
4290                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4291                 break;
4292         default:
4293                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4294                                                         filter_type);
4295                 break;
4296         }
4297
4298         return ret;
4299 }
4300
4301 static int
4302 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4303                          struct ether_addr *mc_addr_set,
4304                          uint32_t nb_mc_addr)
4305 {
4306         struct e1000_hw *hw;
4307
4308         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4309         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4310         return 0;
4311 }
4312
4313 static uint64_t
4314 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4315 {
4316         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317         uint64_t systime_cycles;
4318
4319         switch (hw->mac.type) {
4320         case e1000_i210:
4321         case e1000_i211:
4322                 /*
4323                  * Need to read System Time Residue Register to be able
4324                  * to read the other two registers.
4325                  */
4326                 E1000_READ_REG(hw, E1000_SYSTIMR);
4327                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4328                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4329                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4330                                 * NSEC_PER_SEC;
4331                 break;
4332         case e1000_82580:
4333         case e1000_i350:
4334         case e1000_i354:
4335                 /*
4336                  * Need to read System Time Residue Register to be able
4337                  * to read the other two registers.
4338                  */
4339                 E1000_READ_REG(hw, E1000_SYSTIMR);
4340                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4341                 /* Only the 8 LSB are valid. */
4342                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4343                                 & 0xff) << 32;
4344                 break;
4345         default:
4346                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4347                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4348                                 << 32;
4349                 break;
4350         }
4351
4352         return systime_cycles;
4353 }
4354
4355 static uint64_t
4356 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4357 {
4358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359         uint64_t rx_tstamp_cycles;
4360
4361         switch (hw->mac.type) {
4362         case e1000_i210:
4363         case e1000_i211:
4364                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4365                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4366                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4367                                 * NSEC_PER_SEC;
4368                 break;
4369         case e1000_82580:
4370         case e1000_i350:
4371         case e1000_i354:
4372                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4373                 /* Only the 8 LSB are valid. */
4374                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4375                                 & 0xff) << 32;
4376                 break;
4377         default:
4378                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4379                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4380                                 << 32;
4381                 break;
4382         }
4383
4384         return rx_tstamp_cycles;
4385 }
4386
4387 static uint64_t
4388 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4389 {
4390         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391         uint64_t tx_tstamp_cycles;
4392
4393         switch (hw->mac.type) {
4394         case e1000_i210:
4395         case e1000_i211:
4396                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4397                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4398                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4399                                 * NSEC_PER_SEC;
4400                 break;
4401         case e1000_82580:
4402         case e1000_i350:
4403         case e1000_i354:
4404                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4405                 /* Only the 8 LSB are valid. */
4406                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4407                                 & 0xff) << 32;
4408                 break;
4409         default:
4410                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4411                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4412                                 << 32;
4413                 break;
4414         }
4415
4416         return tx_tstamp_cycles;
4417 }
4418
4419 static void
4420 igb_start_timecounters(struct rte_eth_dev *dev)
4421 {
4422         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423         struct e1000_adapter *adapter =
4424                 (struct e1000_adapter *)dev->data->dev_private;
4425         uint32_t incval = 1;
4426         uint32_t shift = 0;
4427         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4428
4429         switch (hw->mac.type) {
4430         case e1000_82580:
4431         case e1000_i350:
4432         case e1000_i354:
4433                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4434                 mask = (1ULL << 40) - 1;
4435                 /* fall-through */
4436         case e1000_i210:
4437         case e1000_i211:
4438                 /*
4439                  * Start incrementing the register
4440                  * used to timestamp PTP packets.
4441                  */
4442                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4443                 break;
4444         case e1000_82576:
4445                 incval = E1000_INCVALUE_82576;
4446                 shift = IGB_82576_TSYNC_SHIFT;
4447                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4448                                 E1000_INCPERIOD_82576 | incval);
4449                 break;
4450         default:
4451                 /* Not supported */
4452                 return;
4453         }
4454
4455         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4456         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4457         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4458
4459         adapter->systime_tc.cc_mask = mask;
4460         adapter->systime_tc.cc_shift = shift;
4461         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4462
4463         adapter->rx_tstamp_tc.cc_mask = mask;
4464         adapter->rx_tstamp_tc.cc_shift = shift;
4465         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4466
4467         adapter->tx_tstamp_tc.cc_mask = mask;
4468         adapter->tx_tstamp_tc.cc_shift = shift;
4469         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4470 }
4471
4472 static int
4473 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4474 {
4475         struct e1000_adapter *adapter =
4476                         (struct e1000_adapter *)dev->data->dev_private;
4477
4478         adapter->systime_tc.nsec += delta;
4479         adapter->rx_tstamp_tc.nsec += delta;
4480         adapter->tx_tstamp_tc.nsec += delta;
4481
4482         return 0;
4483 }
4484
4485 static int
4486 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4487 {
4488         uint64_t ns;
4489         struct e1000_adapter *adapter =
4490                         (struct e1000_adapter *)dev->data->dev_private;
4491
4492         ns = rte_timespec_to_ns(ts);
4493
4494         /* Set the timecounters to a new value. */
4495         adapter->systime_tc.nsec = ns;
4496         adapter->rx_tstamp_tc.nsec = ns;
4497         adapter->tx_tstamp_tc.nsec = ns;
4498
4499         return 0;
4500 }
4501
4502 static int
4503 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4504 {
4505         uint64_t ns, systime_cycles;
4506         struct e1000_adapter *adapter =
4507                         (struct e1000_adapter *)dev->data->dev_private;
4508
4509         systime_cycles = igb_read_systime_cyclecounter(dev);
4510         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4511         *ts = rte_ns_to_timespec(ns);
4512
4513         return 0;
4514 }
4515
4516 static int
4517 igb_timesync_enable(struct rte_eth_dev *dev)
4518 {
4519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4520         uint32_t tsync_ctl;
4521         uint32_t tsauxc;
4522
4523         /* Stop the timesync system time. */
4524         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4525         /* Reset the timesync system time value. */
4526         switch (hw->mac.type) {
4527         case e1000_82580:
4528         case e1000_i350:
4529         case e1000_i354:
4530         case e1000_i210:
4531         case e1000_i211:
4532                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4533                 /* fall-through */
4534         case e1000_82576:
4535                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4536                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4537                 break;
4538         default:
4539                 /* Not supported. */
4540                 return -ENOTSUP;
4541         }
4542
4543         /* Enable system time for it isn't on by default. */
4544         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4545         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4546         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4547
4548         igb_start_timecounters(dev);
4549
4550         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4551         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4552                         (ETHER_TYPE_1588 |
4553                          E1000_ETQF_FILTER_ENABLE |
4554                          E1000_ETQF_1588));
4555
4556         /* Enable timestamping of received PTP packets. */
4557         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4558         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4559         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4560
4561         /* Enable Timestamping of transmitted PTP packets. */
4562         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4563         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4564         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4565
4566         return 0;
4567 }
4568
4569 static int
4570 igb_timesync_disable(struct rte_eth_dev *dev)
4571 {
4572         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         uint32_t tsync_ctl;
4574
4575         /* Disable timestamping of transmitted PTP packets. */
4576         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4577         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4578         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4579
4580         /* Disable timestamping of received PTP packets. */
4581         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4582         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4583         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4584
4585         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4586         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4587
4588         /* Stop incrementating the System Time registers. */
4589         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4590
4591         return 0;
4592 }
4593
4594 static int
4595 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4596                                struct timespec *timestamp,
4597                                uint32_t flags __rte_unused)
4598 {
4599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600         struct e1000_adapter *adapter =
4601                         (struct e1000_adapter *)dev->data->dev_private;
4602         uint32_t tsync_rxctl;
4603         uint64_t rx_tstamp_cycles;
4604         uint64_t ns;
4605
4606         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4607         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4608                 return -EINVAL;
4609
4610         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4611         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4612         *timestamp = rte_ns_to_timespec(ns);
4613
4614         return  0;
4615 }
4616
4617 static int
4618 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4619                                struct timespec *timestamp)
4620 {
4621         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4622         struct e1000_adapter *adapter =
4623                         (struct e1000_adapter *)dev->data->dev_private;
4624         uint32_t tsync_txctl;
4625         uint64_t tx_tstamp_cycles;
4626         uint64_t ns;
4627
4628         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4629         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4630                 return -EINVAL;
4631
4632         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4633         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4634         *timestamp = rte_ns_to_timespec(ns);
4635
4636         return  0;
4637 }
4638
4639 static int
4640 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4641 {
4642         int count = 0;
4643         int g_ind = 0;
4644         const struct reg_info *reg_group;
4645
4646         while ((reg_group = igb_regs[g_ind++]))
4647                 count += igb_reg_group_count(reg_group);
4648
4649         return count;
4650 }
4651
4652 static int
4653 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4654 {
4655         int count = 0;
4656         int g_ind = 0;
4657         const struct reg_info *reg_group;
4658
4659         while ((reg_group = igbvf_regs[g_ind++]))
4660                 count += igb_reg_group_count(reg_group);
4661
4662         return count;
4663 }
4664
4665 static int
4666 eth_igb_get_regs(struct rte_eth_dev *dev,
4667         struct rte_dev_reg_info *regs)
4668 {
4669         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4670         uint32_t *data = regs->data;
4671         int g_ind = 0;
4672         int count = 0;
4673         const struct reg_info *reg_group;
4674
4675         /* Support only full register dump */
4676         if ((regs->length == 0) ||
4677             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4678                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4679                         hw->device_id;
4680                 while ((reg_group = igb_regs[g_ind++]))
4681                         count += igb_read_regs_group(dev, &data[count],
4682                                                         reg_group);
4683                 return 0;
4684         }
4685
4686         return -ENOTSUP;
4687 }
4688
4689 static int
4690 igbvf_get_regs(struct rte_eth_dev *dev,
4691         struct rte_dev_reg_info *regs)
4692 {
4693         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694         uint32_t *data = regs->data;
4695         int g_ind = 0;
4696         int count = 0;
4697         const struct reg_info *reg_group;
4698
4699         /* Support only full register dump */
4700         if ((regs->length == 0) ||
4701             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4702                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4703                         hw->device_id;
4704                 while ((reg_group = igbvf_regs[g_ind++]))
4705                         count += igb_read_regs_group(dev, &data[count],
4706                                                         reg_group);
4707                 return 0;
4708         }
4709
4710         return -ENOTSUP;
4711 }
4712
4713 static int
4714 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4715 {
4716         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4717
4718         /* Return unit is byte count */
4719         return hw->nvm.word_size * 2;
4720 }
4721
4722 static int
4723 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4724         struct rte_dev_eeprom_info *in_eeprom)
4725 {
4726         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4727         struct e1000_nvm_info *nvm = &hw->nvm;
4728         uint16_t *data = in_eeprom->data;
4729         int first, length;
4730
4731         first = in_eeprom->offset >> 1;
4732         length = in_eeprom->length >> 1;
4733         if ((first >= hw->nvm.word_size) ||
4734             ((first + length) >= hw->nvm.word_size))
4735                 return -EINVAL;
4736
4737         in_eeprom->magic = hw->vendor_id |
4738                 ((uint32_t)hw->device_id << 16);
4739
4740         if ((nvm->ops.read) == NULL)
4741                 return -ENOTSUP;
4742
4743         return nvm->ops.read(hw, first, length, data);
4744 }
4745
4746 static int
4747 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4748         struct rte_dev_eeprom_info *in_eeprom)
4749 {
4750         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4751         struct e1000_nvm_info *nvm = &hw->nvm;
4752         uint16_t *data = in_eeprom->data;
4753         int first, length;
4754
4755         first = in_eeprom->offset >> 1;
4756         length = in_eeprom->length >> 1;
4757         if ((first >= hw->nvm.word_size) ||
4758             ((first + length) >= hw->nvm.word_size))
4759                 return -EINVAL;
4760
4761         in_eeprom->magic = (uint32_t)hw->vendor_id |
4762                 ((uint32_t)hw->device_id << 16);
4763
4764         if ((nvm->ops.write) == NULL)
4765                 return -ENOTSUP;
4766         return nvm->ops.write(hw,  first, length, data);
4767 }
4768
4769 static struct rte_driver pmd_igb_drv = {
4770         .type = PMD_PDEV,
4771         .init = rte_igb_pmd_init,
4772 };
4773
4774 static struct rte_driver pmd_igbvf_drv = {
4775         .type = PMD_PDEV,
4776         .init = rte_igbvf_pmd_init,
4777 };
4778
4779 static int
4780 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4781 {
4782         struct e1000_hw *hw =
4783                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         uint32_t mask = 1 << queue_id;
4785
4786         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4787         E1000_WRITE_FLUSH(hw);
4788
4789         return 0;
4790 }
4791
4792 static int
4793 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4794 {
4795         struct e1000_hw *hw =
4796                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797         uint32_t mask = 1 << queue_id;
4798         uint32_t regval;
4799
4800         regval = E1000_READ_REG(hw, E1000_EIMS);
4801         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4802         E1000_WRITE_FLUSH(hw);
4803
4804         rte_intr_enable(&dev->pci_dev->intr_handle);
4805
4806         return 0;
4807 }
4808
4809 static void
4810 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4811                    uint8_t index, uint8_t offset)
4812 {
4813         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4814
4815         /* clear bits */
4816         val &= ~((uint32_t)0xFF << offset);
4817
4818         /* write vector and valid bit */
4819         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4820
4821         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4822 }
4823
4824 static void
4825 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4826                            uint8_t queue, uint8_t msix_vector)
4827 {
4828         uint32_t tmp = 0;
4829
4830         if (hw->mac.type == e1000_82575) {
4831                 if (direction == 0)
4832                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4833                 else if (direction == 1)
4834                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4835                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4836         } else if (hw->mac.type == e1000_82576) {
4837                 if ((direction == 0) || (direction == 1))
4838                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4839                                            ((queue & 0x8) << 1) +
4840                                            8 * direction);
4841         } else if ((hw->mac.type == e1000_82580) ||
4842                         (hw->mac.type == e1000_i350) ||
4843                         (hw->mac.type == e1000_i354) ||
4844                         (hw->mac.type == e1000_i210) ||
4845                         (hw->mac.type == e1000_i211)) {
4846                 if ((direction == 0) || (direction == 1))
4847                         eth_igb_write_ivar(hw, msix_vector,
4848                                            queue >> 1,
4849                                            ((queue & 0x1) << 4) +
4850                                            8 * direction);
4851         }
4852 }
4853
4854 /* Sets up the hardware to generate MSI-X interrupts properly
4855  * @hw
4856  *  board private structure
4857  */
4858 static void
4859 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4860 {
4861         int queue_id;
4862         uint32_t tmpval, regval, intr_mask;
4863         struct e1000_hw *hw =
4864                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865         uint32_t vec = E1000_MISC_VEC_ID;
4866         uint32_t base = E1000_MISC_VEC_ID;
4867         uint32_t misc_shift = 0;
4868
4869         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4870
4871         /* won't configure msix register if no mapping is done
4872          * between intr vector and event fd
4873          */
4874         if (!rte_intr_dp_is_en(intr_handle))
4875                 return;
4876
4877         if (rte_intr_allow_others(intr_handle)) {
4878                 vec = base = E1000_RX_VEC_START;
4879                 misc_shift = 1;
4880         }
4881
4882         /* set interrupt vector for other causes */
4883         if (hw->mac.type == e1000_82575) {
4884                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4885                 /* enable MSI-X PBA support */
4886                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4887
4888                 /* Auto-Mask interrupts upon ICR read */
4889                 tmpval |= E1000_CTRL_EXT_EIAME;
4890                 tmpval |= E1000_CTRL_EXT_IRCA;
4891
4892                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4893
4894                 /* enable msix_other interrupt */
4895                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4896                 regval = E1000_READ_REG(hw, E1000_EIAC);
4897                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4898                 regval = E1000_READ_REG(hw, E1000_EIAM);
4899                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4900         } else if ((hw->mac.type == e1000_82576) ||
4901                         (hw->mac.type == e1000_82580) ||
4902                         (hw->mac.type == e1000_i350) ||
4903                         (hw->mac.type == e1000_i354) ||
4904                         (hw->mac.type == e1000_i210) ||
4905                         (hw->mac.type == e1000_i211)) {
4906                 /* turn on MSI-X capability first */
4907                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4908                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4909                                         E1000_GPIE_NSICR);
4910                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4911                         misc_shift;
4912                 regval = E1000_READ_REG(hw, E1000_EIAC);
4913                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4914
4915                 /* enable msix_other interrupt */
4916                 regval = E1000_READ_REG(hw, E1000_EIMS);
4917                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4918                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4919                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4920         }
4921
4922         /* use EIAM to auto-mask when MSI-X interrupt
4923          * is asserted, this saves a register write for every interrupt
4924          */
4925         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4926                 misc_shift;
4927         regval = E1000_READ_REG(hw, E1000_EIAM);
4928         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4929
4930         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4931                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4932                 intr_handle->intr_vec[queue_id] = vec;
4933                 if (vec < base + intr_handle->nb_efd - 1)
4934                         vec++;
4935         }
4936
4937         E1000_WRITE_FLUSH(hw);
4938 }
4939
4940 PMD_REGISTER_DRIVER(pmd_igb_drv);
4941 PMD_REGISTER_DRIVER(pmd_igbvf_drv);