drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter);
 218 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 219                         enum rte_filter_op filter_op,
 220                         void *arg);
 221 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 222                         struct rte_eth_ntuple_filter *ntuple_filter);
 223 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ntuple_filter *ntuple_filter);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter);
 244 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 245                      enum rte_filter_type filter_type,
 246                      enum rte_filter_op filter_op,
 247                      void *arg);
 248 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 249 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 250                 struct rte_dev_reg_info *regs);
 251 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 253                 struct rte_dev_eeprom_info *eeprom);
 254 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 255                 struct rte_dev_eeprom_info *eeprom);
 256 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 257                                     struct ether_addr *mc_addr_set,
 258                                     uint32_t nb_mc_addr);
 259 static int igb_timesync_enable(struct rte_eth_dev *dev);
 260 static int igb_timesync_disable(struct rte_eth_dev *dev);
 261 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 262                                           struct timespec *timestamp,
 263                                           uint32_t flags);
 264 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp);
 266 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 267 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 268                                   struct timespec *timestamp);
 269 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 270                                    const struct timespec *timestamp);
 271 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                         uint16_t queue_id);
 273 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                          uint16_t queue_id);
 275 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 276                                        uint8_t queue, uint8_t msix_vector);
 277 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 278                                uint8_t index, uint8_t offset);
 279 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 280 static void eth_igbvf_interrupt_handler(void *param);
 281 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 282 static int igb_filter_restore(struct rte_eth_dev *dev);
 283
 284 /*
 285  * Define VF Stats MACRO for Non "cleared on read" register
 286  */
 287 #define UPDATE_VF_STAT(reg, last, cur)            \
 288 {                                                 \
 289         u32 latest = E1000_READ_REG(hw, reg);     \
 290         cur += (latest - last) & UINT_MAX;        \
 291         last = latest;                            \
 292 }
 293
 294 #define IGB_FC_PAUSE_TIME 0x0680
 295 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 296 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 297
 298 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 299
 300 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 301
 302 /*
 303  * The set of PCI devices this driver supports
 304  */
 305 static const struct rte_pci_id pci_id_igb_map[] = {
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 314
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 318
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 325
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 345         { .vendor_id = 0, /* sentinel */ },
 346 };
 347
 348 /*
 349  * The set of PCI devices this driver supports (for 82576&I350 VF)
 350  */
 351 static const struct rte_pci_id pci_id_igbvf_map[] = {
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 356         { .vendor_id = 0, /* sentinel */ },
 357 };
 358
 359 static const struct rte_eth_desc_lim rx_desc_lim = {
 360         .nb_max = E1000_MAX_RING_DESC,
 361         .nb_min = E1000_MIN_RING_DESC,
 362         .nb_align = IGB_RXD_ALIGN,
 363 };
 364
 365 static const struct rte_eth_desc_lim tx_desc_lim = {
 366         .nb_max = E1000_MAX_RING_DESC,
 367         .nb_min = E1000_MIN_RING_DESC,
 368         .nb_align = IGB_RXD_ALIGN,
 369         .nb_seg_max = IGB_TX_MAX_SEG,
 370         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 371 };
 372
 373 static const struct eth_dev_ops eth_igb_ops = {
 374         .dev_configure        = eth_igb_configure,
 375         .dev_start            = eth_igb_start,
 376         .dev_stop             = eth_igb_stop,
 377         .dev_set_link_up      = eth_igb_dev_set_link_up,
 378         .dev_set_link_down    = eth_igb_dev_set_link_down,
 379         .dev_close            = eth_igb_close,
 380         .promiscuous_enable   = eth_igb_promiscuous_enable,
 381         .promiscuous_disable  = eth_igb_promiscuous_disable,
 382         .allmulticast_enable  = eth_igb_allmulticast_enable,
 383         .allmulticast_disable = eth_igb_allmulticast_disable,
 384         .link_update          = eth_igb_link_update,
 385         .stats_get            = eth_igb_stats_get,
 386         .xstats_get           = eth_igb_xstats_get,
 387         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 388         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 389         .xstats_get_names     = eth_igb_xstats_get_names,
 390         .stats_reset          = eth_igb_stats_reset,
 391         .xstats_reset         = eth_igb_xstats_reset,
 392         .fw_version_get       = eth_igb_fw_version_get,
 393         .dev_infos_get        = eth_igb_infos_get,
 394         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 395         .mtu_set              = eth_igb_mtu_set,
 396         .vlan_filter_set      = eth_igb_vlan_filter_set,
 397         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 398         .vlan_offload_set     = eth_igb_vlan_offload_set,
 399         .rx_queue_setup       = eth_igb_rx_queue_setup,
 400         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 401         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 402         .rx_queue_release     = eth_igb_rx_queue_release,
 403         .rx_queue_count       = eth_igb_rx_queue_count,
 404         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 405         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 406         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 407         .tx_queue_setup       = eth_igb_tx_queue_setup,
 408         .tx_queue_release     = eth_igb_tx_queue_release,
 409         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 410         .dev_led_on           = eth_igb_led_on,
 411         .dev_led_off          = eth_igb_led_off,
 412         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 413         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 414         .mac_addr_add         = eth_igb_rar_set,
 415         .mac_addr_remove      = eth_igb_rar_clear,
 416         .mac_addr_set         = eth_igb_default_mac_addr_set,
 417         .reta_update          = eth_igb_rss_reta_update,
 418         .reta_query           = eth_igb_rss_reta_query,
 419         .rss_hash_update      = eth_igb_rss_hash_update,
 420         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 421         .filter_ctrl          = eth_igb_filter_ctrl,
 422         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 423         .rxq_info_get         = igb_rxq_info_get,
 424         .txq_info_get         = igb_txq_info_get,
 425         .timesync_enable      = igb_timesync_enable,
 426         .timesync_disable     = igb_timesync_disable,
 427         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 428         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 429         .get_reg              = eth_igb_get_regs,
 430         .get_eeprom_length    = eth_igb_get_eeprom_length,
 431         .get_eeprom           = eth_igb_get_eeprom,
 432         .set_eeprom           = eth_igb_set_eeprom,
 433         .timesync_adjust_time = igb_timesync_adjust_time,
 434         .timesync_read_time   = igb_timesync_read_time,
 435         .timesync_write_time  = igb_timesync_write_time,
 436 };
 437
 438 /*
 439  * dev_ops for virtual function, bare necessities for basic vf
 440  * operation have been implemented
 441  */
 442 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 443         .dev_configure        = igbvf_dev_configure,
 444         .dev_start            = igbvf_dev_start,
 445         .dev_stop             = igbvf_dev_stop,
 446         .dev_close            = igbvf_dev_close,
 447         .promiscuous_enable   = igbvf_promiscuous_enable,
 448         .promiscuous_disable  = igbvf_promiscuous_disable,
 449         .allmulticast_enable  = igbvf_allmulticast_enable,
 450         .allmulticast_disable = igbvf_allmulticast_disable,
 451         .link_update          = eth_igb_link_update,
 452         .stats_get            = eth_igbvf_stats_get,
 453         .xstats_get           = eth_igbvf_xstats_get,
 454         .xstats_get_names     = eth_igbvf_xstats_get_names,
 455         .stats_reset          = eth_igbvf_stats_reset,
 456         .xstats_reset         = eth_igbvf_stats_reset,
 457         .vlan_filter_set      = igbvf_vlan_filter_set,
 458         .dev_infos_get        = eth_igbvf_infos_get,
 459         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 460         .rx_queue_setup       = eth_igb_rx_queue_setup,
 461         .rx_queue_release     = eth_igb_rx_queue_release,
 462         .tx_queue_setup       = eth_igb_tx_queue_setup,
 463         .tx_queue_release     = eth_igb_tx_queue_release,
 464         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 465         .rxq_info_get         = igb_rxq_info_get,
 466         .txq_info_get         = igb_txq_info_get,
 467         .mac_addr_set         = igbvf_default_mac_addr_set,
 468         .get_reg              = igbvf_get_regs,
 469 };
 470
 471 /* store statistics names and its offset in stats structure */
 472 struct rte_igb_xstats_name_off {
 473         char name[RTE_ETH_XSTATS_NAME_SIZE];
 474         unsigned offset;
 475 };
 476
 477 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 478         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 479         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 480         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 481         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 482         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 483         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 484         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 485                 ecol)},
 486         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 487         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 488         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 489         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 490         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 491         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 492         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 493         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 494         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 495         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 496         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 497                 fcruc)},
 498         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 499         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 500         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 501         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 502         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 503                 prc1023)},
 504         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 505                 prc1522)},
 506         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 507         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 508         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 509         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 510         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 511         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 512         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 513         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 514         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 515         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 516         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 517         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 518         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 519         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 520         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 521         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 522         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 523         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 524                 ptc1023)},
 525         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1522)},
 527         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 528         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 529         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 530         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 531         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 532         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 533         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 534
 535         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 536 };
 537
 538 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 539                 sizeof(rte_igb_stats_strings[0]))
 540
 541 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 542         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 543         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 544         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 545         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 546         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 547 };
 548
 549 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 550                 sizeof(rte_igbvf_stats_strings[0]))
 551
 552 /**
 553  * Atomically reads the link status information from global
 554  * structure rte_eth_dev.
 555  *
 556  * @param dev
 557  *   - Pointer to the structure rte_eth_dev to read from.
 558  *   - Pointer to the buffer to be saved with the link status.
 559  *
 560  * @return
 561  *   - On success, zero.
 562  *   - On failure, negative value.
 563  */
 564 static inline int
 565 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 566                                 struct rte_eth_link *link)
 567 {
 568         struct rte_eth_link *dst = link;
 569         struct rte_eth_link *src = &(dev->data->dev_link);
 570
 571         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 572                                         *(uint64_t *)src) == 0)
 573                 return -1;
 574
 575         return 0;
 576 }
 577
 578 /**
 579  * Atomically writes the link status information into global
 580  * structure rte_eth_dev.
 581  *
 582  * @param dev
 583  *   - Pointer to the structure rte_eth_dev to read from.
 584  *   - Pointer to the buffer to be saved with the link status.
 585  *
 586  * @return
 587  *   - On success, zero.
 588  *   - On failure, negative value.
 589  */
 590 static inline int
 591 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 592                                 struct rte_eth_link *link)
 593 {
 594         struct rte_eth_link *dst = &(dev->data->dev_link);
 595         struct rte_eth_link *src = link;
 596
 597         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 598                                         *(uint64_t *)src) == 0)
 599                 return -1;
 600
 601         return 0;
 602 }
 603
 604 static inline void
 605 igb_intr_enable(struct rte_eth_dev *dev)
 606 {
 607         struct e1000_interrupt *intr =
 608                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 609         struct e1000_hw *hw =
 610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 611
 612         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 613         E1000_WRITE_FLUSH(hw);
 614 }
 615
 616 static void
 617 igb_intr_disable(struct e1000_hw *hw)
 618 {
 619         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 620         E1000_WRITE_FLUSH(hw);
 621 }
 622
 623 static inline void
 624 igbvf_intr_enable(struct rte_eth_dev *dev)
 625 {
 626         struct e1000_hw *hw =
 627                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 628
 629         /* only for mailbox */
 630         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 631         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 632         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_FLUSH(hw);
 634 }
 635
 636 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 637 static void
 638 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 639 {
 640         uint32_t tmp = 0;
 641
 642         /* mailbox */
 643         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 644         tmp |= E1000_VTIVAR_VALID;
 645         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 646 }
 647
 648 static void
 649 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 650 {
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653
 654         /* Configure VF other cause ivar */
 655         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 656 }
 657
 658 static inline int32_t
 659 igb_pf_reset_hw(struct e1000_hw *hw)
 660 {
 661         uint32_t ctrl_ext;
 662         int32_t status;
 663
 664         status = e1000_reset_hw(hw);
 665
 666         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 667         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 668         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 669         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 670         E1000_WRITE_FLUSH(hw);
 671
 672         return status;
 673 }
 674
 675 static void
 676 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 677 {
 678         struct e1000_hw *hw =
 679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 680
 681
 682         hw->vendor_id = pci_dev->id.vendor_id;
 683         hw->device_id = pci_dev->id.device_id;
 684         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 685         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 686
 687         e1000_set_mac_type(hw);
 688
 689         /* need to check if it is a vf device below */
 690 }
 691
 692 static int
 693 igb_reset_swfw_lock(struct e1000_hw *hw)
 694 {
 695         int ret_val;
 696
 697         /*
 698          * Do mac ops initialization manually here, since we will need
 699          * some function pointers set by this call.
 700          */
 701         ret_val = e1000_init_mac_params(hw);
 702         if (ret_val)
 703                 return ret_val;
 704
 705         /*
 706          * SMBI lock should not fail in this early stage. If this is the case,
 707          * it is due to an improper exit of the application.
 708          * So force the release of the faulty lock.
 709          */
 710         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 711                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 712         }
 713         e1000_put_hw_semaphore_generic(hw);
 714
 715         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 716                 uint16_t mask;
 717
 718                 /*
 719                  * Phy lock should not fail in this early stage. If this is the case,
 720                  * it is due to an improper exit of the application.
 721                  * So force the release of the faulty lock.
 722                  */
 723                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 724                 if (hw->bus.func > E1000_FUNC_1)
 725                         mask <<= 2;
 726                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 727                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 728                                     hw->bus.func);
 729                 }
 730                 hw->mac.ops.release_swfw_sync(hw, mask);
 731
 732                 /*
 733                  * This one is more tricky since it is common to all ports; but
 734                  * swfw_sync retries last long enough (1s) to be almost sure that if
 735                  * lock can not be taken it is due to an improper lock of the
 736                  * semaphore.
 737                  */
 738                 mask = E1000_SWFW_EEP_SM;
 739                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 740                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743         }
 744
 745         return E1000_SUCCESS;
 746 }
 747
 748 /* Remove all ntuple filters of the device */
 749 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 750 {
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_5tuple_filter *p_5tuple;
 754         struct e1000_2tuple_filter *p_2tuple;
 755
 756         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 757                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 758                         p_5tuple, entries);
 759                         rte_free(p_5tuple);
 760         }
 761         filter_info->fivetuple_mask = 0;
 762         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 763                 TAILQ_REMOVE(&filter_info->twotuple_list,
 764                         p_2tuple, entries);
 765                         rte_free(p_2tuple);
 766         }
 767         filter_info->twotuple_mask = 0;
 768
 769         return 0;
 770 }
 771
 772 /* Remove all flex filters of the device */
 773 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 774 {
 775         struct e1000_filter_info *filter_info =
 776                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 777         struct e1000_flex_filter *p_flex;
 778
 779         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 780                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 781                 rte_free(p_flex);
 782         }
 783         filter_info->flex_mask = 0;
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 790 {
 791         int error = 0;
 792         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 793         struct e1000_hw *hw =
 794                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 795         struct e1000_vfta * shadow_vfta =
 796                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 797         struct e1000_filter_info *filter_info =
 798                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 799         struct e1000_adapter *adapter =
 800                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 801
 802         uint32_t ctrl_ext;
 803
 804         eth_dev->dev_ops = &eth_igb_ops;
 805         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 806         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 807         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 808
 809         /* for secondary processes, we don't initialise any further as primary
 810          * has already done this work. Only check we don't need a different
 811          * RX function */
 812         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 813                 if (eth_dev->data->scattered_rx)
 814                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 815                 return 0;
 816         }
 817
 818         rte_eth_copy_pci_info(eth_dev, pci_dev);
 819         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 820
 821         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 822
 823         igb_identify_hardware(eth_dev, pci_dev);
 824         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 825                 error = -EIO;
 826                 goto err_late;
 827         }
 828
 829         e1000_get_bus_info(hw);
 830
 831         /* Reset any pending lock */
 832         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 833                 error = -EIO;
 834                 goto err_late;
 835         }
 836
 837         /* Finish initialization */
 838         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 839                 error = -EIO;
 840                 goto err_late;
 841         }
 842
 843         hw->mac.autoneg = 1;
 844         hw->phy.autoneg_wait_to_complete = 0;
 845         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 846
 847         /* Copper options */
 848         if (hw->phy.media_type == e1000_media_type_copper) {
 849                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 850                 hw->phy.disable_polarity_correction = 0;
 851                 hw->phy.ms_type = e1000_ms_hw_default;
 852         }
 853
 854         /*
 855          * Start from a known state, this is important in reading the nvm
 856          * and mac from that.
 857          */
 858         igb_pf_reset_hw(hw);
 859
 860         /* Make sure we have a good EEPROM before we read from it */
 861         if (e1000_validate_nvm_checksum(hw) < 0) {
 862                 /*
 863                  * Some PCI-E parts fail the first check due to
 864                  * the link being in sleep state, call it again,
 865                  * if it fails a second time its a real issue.
 866                  */
 867                 if (e1000_validate_nvm_checksum(hw) < 0) {
 868                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 869                         error = -EIO;
 870                         goto err_late;
 871                 }
 872         }
 873
 874         /* Read the permanent MAC address out of the EEPROM */
 875         if (e1000_read_mac_addr(hw) != 0) {
 876                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 877                 error = -EIO;
 878                 goto err_late;
 879         }
 880
 881         /* Allocate memory for storing MAC addresses */
 882         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 883                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 884         if (eth_dev->data->mac_addrs == NULL) {
 885                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 886                                                 "store MAC addresses",
 887                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 888                 error = -ENOMEM;
 889                 goto err_late;
 890         }
 891
 892         /* Copy the permanent MAC address */
 893         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 894
 895         /* initialize the vfta */
 896         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 897
 898         /* Now initialize the hardware */
 899         if (igb_hardware_init(hw) != 0) {
 900                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 901                 rte_free(eth_dev->data->mac_addrs);
 902                 eth_dev->data->mac_addrs = NULL;
 903                 error = -ENODEV;
 904                 goto err_late;
 905         }
 906         hw->mac.get_link_status = 1;
 907         adapter->stopped = 0;
 908
 909         /* Indicate SOL/IDER usage */
 910         if (e1000_check_reset_block(hw) < 0) {
 911                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 912                                         "SOL/IDER session");
 913         }
 914
 915         /* initialize PF if max_vfs not zero */
 916         igb_pf_host_init(eth_dev);
 917
 918         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 919         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 920         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 921         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 922         E1000_WRITE_FLUSH(hw);
 923
 924         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 925                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 926                      pci_dev->id.device_id);
 927
 928         rte_intr_callback_register(&pci_dev->intr_handle,
 929                                    eth_igb_interrupt_handler,
 930                                    (void *)eth_dev);
 931
 932         /* enable uio/vfio intr/eventfd mapping */
 933         rte_intr_enable(&pci_dev->intr_handle);
 934
 935         /* enable support intr */
 936         igb_intr_enable(eth_dev);
 937
 938         /* initialize filter info */
 939         memset(filter_info, 0,
 940                sizeof(struct e1000_filter_info));
 941
 942         TAILQ_INIT(&filter_info->flex_list);
 943         TAILQ_INIT(&filter_info->twotuple_list);
 944         TAILQ_INIT(&filter_info->fivetuple_list);
 945
 946         TAILQ_INIT(&igb_filter_ntuple_list);
 947         TAILQ_INIT(&igb_filter_ethertype_list);
 948         TAILQ_INIT(&igb_filter_syn_list);
 949         TAILQ_INIT(&igb_filter_flex_list);
 950         TAILQ_INIT(&igb_flow_list);
 951
 952         return 0;
 953
 954 err_late:
 955         igb_hw_control_release(hw);
 956
 957         return error;
 958 }
 959
 960 static int
 961 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 962 {
 963         struct rte_pci_device *pci_dev;
 964         struct rte_intr_handle *intr_handle;
 965         struct e1000_hw *hw;
 966         struct e1000_adapter *adapter =
 967                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 968         struct e1000_filter_info *filter_info =
 969                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 970
 971         PMD_INIT_FUNC_TRACE();
 972
 973         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 974                 return -EPERM;
 975
 976         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         intr_handle = &pci_dev->intr_handle;
 979
 980         if (adapter->stopped == 0)
 981                 eth_igb_close(eth_dev);
 982
 983         eth_dev->dev_ops = NULL;
 984         eth_dev->rx_pkt_burst = NULL;
 985         eth_dev->tx_pkt_burst = NULL;
 986
 987         /* Reset any pending lock */
 988         igb_reset_swfw_lock(hw);
 989
 990         rte_free(eth_dev->data->mac_addrs);
 991         eth_dev->data->mac_addrs = NULL;
 992
 993         /* uninitialize PF if max_vfs not zero */
 994         igb_pf_host_uninit(eth_dev);
 995
 996         /* disable uio intr before callback unregister */
 997         rte_intr_disable(intr_handle);
 998         rte_intr_callback_unregister(intr_handle,
 999                                      eth_igb_interrupt_handler, eth_dev);
1000
1001         /* clear the SYN filter info */
1002         filter_info->syn_info = 0;
1003
1004         /* clear the ethertype filters info */
1005         filter_info->ethertype_mask = 0;
1006         memset(filter_info->ethertype_filters, 0,
1007                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1008
1009         /* remove all ntuple filters of the device */
1010         igb_ntuple_filter_uninit(eth_dev);
1011
1012         /* remove all flex filters of the device */
1013         igb_flex_filter_uninit(eth_dev);
1014
1015         return 0;
1016 }
1017
1018 /*
1019  * Virtual Function device init
1020  */
1021 static int
1022 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1023 {
1024         struct rte_pci_device *pci_dev;
1025         struct rte_intr_handle *intr_handle;
1026         struct e1000_adapter *adapter =
1027                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1028         struct e1000_hw *hw =
1029                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1030         int diag;
1031         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1032
1033         PMD_INIT_FUNC_TRACE();
1034
1035         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1036         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1037         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1038         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1039
1040         /* for secondary processes, we don't initialise any further as primary
1041          * has already done this work. Only check we don't need a different
1042          * RX function */
1043         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1044                 if (eth_dev->data->scattered_rx)
1045                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1046                 return 0;
1047         }
1048
1049         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050         rte_eth_copy_pci_info(eth_dev, pci_dev);
1051         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1052
1053         hw->device_id = pci_dev->id.device_id;
1054         hw->vendor_id = pci_dev->id.vendor_id;
1055         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1056         adapter->stopped = 0;
1057
1058         /* Initialize the shared code (base driver) */
1059         diag = e1000_setup_init_funcs(hw, TRUE);
1060         if (diag != 0) {
1061                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1062                         diag);
1063                 return -EIO;
1064         }
1065
1066         /* init_mailbox_params */
1067         hw->mbx.ops.init_params(hw);
1068
1069         /* Disable the interrupts for VF */
1070         igbvf_intr_disable(hw);
1071
1072         diag = hw->mac.ops.reset_hw(hw);
1073
1074         /* Allocate memory for storing MAC addresses */
1075         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1076                 hw->mac.rar_entry_count, 0);
1077         if (eth_dev->data->mac_addrs == NULL) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Failed to allocate %d bytes needed to store MAC "
1080                         "addresses",
1081                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1082                 return -ENOMEM;
1083         }
1084
1085         /* Generate a random MAC address, if none was assigned by PF. */
1086         if (is_zero_ether_addr(perm_addr)) {
1087                 eth_random_addr(perm_addr->addr_bytes);
1088                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1089                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1090                              "%02x:%02x:%02x:%02x:%02x:%02x",
1091                              perm_addr->addr_bytes[0],
1092                              perm_addr->addr_bytes[1],
1093                              perm_addr->addr_bytes[2],
1094                              perm_addr->addr_bytes[3],
1095                              perm_addr->addr_bytes[4],
1096                              perm_addr->addr_bytes[5]);
1097         }
1098
1099         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1100         if (diag) {
1101                 rte_free(eth_dev->data->mac_addrs);
1102                 eth_dev->data->mac_addrs = NULL;
1103                 return diag;
1104         }
1105         /* Copy the permanent MAC address */
1106         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1107                         &eth_dev->data->mac_addrs[0]);
1108
1109         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1110                      "mac.type=%s",
1111                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1112                      pci_dev->id.device_id, "igb_mac_82576_vf");
1113
1114         intr_handle = &pci_dev->intr_handle;
1115         rte_intr_callback_register(intr_handle,
1116                                    eth_igbvf_interrupt_handler, eth_dev);
1117
1118         return 0;
1119 }
1120
1121 static int
1122 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1123 {
1124         struct e1000_adapter *adapter =
1125                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1127
1128         PMD_INIT_FUNC_TRACE();
1129
1130         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1131                 return -EPERM;
1132
1133         if (adapter->stopped == 0)
1134                 igbvf_dev_close(eth_dev);
1135
1136         eth_dev->dev_ops = NULL;
1137         eth_dev->rx_pkt_burst = NULL;
1138         eth_dev->tx_pkt_burst = NULL;
1139
1140         rte_free(eth_dev->data->mac_addrs);
1141         eth_dev->data->mac_addrs = NULL;
1142
1143         /* disable uio intr before callback unregister */
1144         rte_intr_disable(&pci_dev->intr_handle);
1145         rte_intr_callback_unregister(&pci_dev->intr_handle,
1146                                      eth_igbvf_interrupt_handler,
1147                                      (void *)eth_dev);
1148
1149         return 0;
1150 }
1151
1152 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1153         struct rte_pci_device *pci_dev)
1154 {
1155         return rte_eth_dev_pci_generic_probe(pci_dev,
1156                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1157 }
1158
1159 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1160 {
1161         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1162 }
1163
1164 static struct rte_pci_driver rte_igb_pmd = {
1165         .id_table = pci_id_igb_map,
1166         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1167         .probe = eth_igb_pci_probe,
1168         .remove = eth_igb_pci_remove,
1169 };
1170
1171
1172 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1173         struct rte_pci_device *pci_dev)
1174 {
1175         return rte_eth_dev_pci_generic_probe(pci_dev,
1176                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1177 }
1178
1179 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1180 {
1181         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1182 }
1183
1184 /*
1185  * virtual function driver struct
1186  */
1187 static struct rte_pci_driver rte_igbvf_pmd = {
1188         .id_table = pci_id_igbvf_map,
1189         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1190         .probe = eth_igbvf_pci_probe,
1191         .remove = eth_igbvf_pci_remove,
1192 };
1193
1194 static void
1195 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1196 {
1197         struct e1000_hw *hw =
1198                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1200         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1201         rctl |= E1000_RCTL_VFE;
1202         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1203 }
1204
1205 static int
1206 igb_check_mq_mode(struct rte_eth_dev *dev)
1207 {
1208         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1209         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1210         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1211         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1212
1213         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1214             tx_mq_mode == ETH_MQ_TX_DCB ||
1215             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1216                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1217                 return -EINVAL;
1218         }
1219         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1220                 /* Check multi-queue mode.
1221                  * To no break software we accept ETH_MQ_RX_NONE as this might
1222                  * be used to turn off VLAN filter.
1223                  */
1224
1225                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1226                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1227                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1228                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1229                 } else {
1230                         /* Only support one queue on VFs.
1231                          * RSS together with SRIOV is not supported.
1232                          */
1233                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1234                                         " wrong mq_mode rx %d.",
1235                                         rx_mq_mode);
1236                         return -EINVAL;
1237                 }
1238                 /* TX mode is not used here, so mode might be ignored.*/
1239                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1240                         /* SRIOV only works in VMDq enable mode */
1241                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1242                                         " TX mode %d is not supported. "
1243                                         " Driver will behave as %d mode.",
1244                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1245                 }
1246
1247                 /* check valid queue number */
1248                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1249                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1250                                         " only support one queue on VFs.");
1251                         return -EINVAL;
1252                 }
1253         } else {
1254                 /* To no break software that set invalid mode, only display
1255                  * warning if invalid mode is used.
1256                  */
1257                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1258                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1259                     rx_mq_mode != ETH_MQ_RX_RSS) {
1260                         /* RSS together with VMDq not supported*/
1261                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1262                                      rx_mq_mode);
1263                         return -EINVAL;
1264                 }
1265
1266                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1267                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1268                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1269                                         " Due to txmode is meaningless in this"
1270                                         " driver, just ignore.",
1271                                         tx_mq_mode);
1272                 }
1273         }
1274         return 0;
1275 }
1276
1277 static int
1278 eth_igb_configure(struct rte_eth_dev *dev)
1279 {
1280         struct e1000_interrupt *intr =
1281                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1282         int ret;
1283
1284         PMD_INIT_FUNC_TRACE();
1285
1286         /* multipe queue mode checking */
1287         ret  = igb_check_mq_mode(dev);
1288         if (ret != 0) {
1289                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1290                             ret);
1291                 return ret;
1292         }
1293
1294         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1295         PMD_INIT_FUNC_TRACE();
1296
1297         return 0;
1298 }
1299
1300 static int
1301 eth_igb_start(struct rte_eth_dev *dev)
1302 {
1303         struct e1000_hw *hw =
1304                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         struct e1000_adapter *adapter =
1306                 E1000_DEV_PRIVATE(dev->data->dev_private);
1307         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1308         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1309         int ret, mask;
1310         uint32_t intr_vector = 0;
1311         uint32_t ctrl_ext;
1312         uint32_t *speeds;
1313         int num_speeds;
1314         bool autoneg;
1315
1316         PMD_INIT_FUNC_TRACE();
1317
1318         /* disable uio/vfio intr/eventfd mapping */
1319         rte_intr_disable(intr_handle);
1320
1321         /* Power up the phy. Needed to make the link go Up */
1322         eth_igb_dev_set_link_up(dev);
1323
1324         /*
1325          * Packet Buffer Allocation (PBA)
1326          * Writing PBA sets the receive portion of the buffer
1327          * the remainder is used for the transmit buffer.
1328          */
1329         if (hw->mac.type == e1000_82575) {
1330                 uint32_t pba;
1331
1332                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1333                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1334         }
1335
1336         /* Put the address into the Receive Address Array */
1337         e1000_rar_set(hw, hw->mac.addr, 0);
1338
1339         /* Initialize the hardware */
1340         if (igb_hardware_init(hw)) {
1341                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1342                 return -EIO;
1343         }
1344         adapter->stopped = 0;
1345
1346         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1347
1348         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1349         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1350         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1351         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1352         E1000_WRITE_FLUSH(hw);
1353
1354         /* configure PF module if SRIOV enabled */
1355         igb_pf_host_configure(dev);
1356
1357         /* check and configure queue intr-vector mapping */
1358         if ((rte_intr_cap_multiple(intr_handle) ||
1359              !RTE_ETH_DEV_SRIOV(dev).active) &&
1360             dev->data->dev_conf.intr_conf.rxq != 0) {
1361                 intr_vector = dev->data->nb_rx_queues;
1362                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1363                         return -1;
1364         }
1365
1366         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1367                 intr_handle->intr_vec =
1368                         rte_zmalloc("intr_vec",
1369                                     dev->data->nb_rx_queues * sizeof(int), 0);
1370                 if (intr_handle->intr_vec == NULL) {
1371                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1372                                      " intr_vec", dev->data->nb_rx_queues);
1373                         return -ENOMEM;
1374                 }
1375         }
1376
1377         /* confiugre msix for rx interrupt */
1378         eth_igb_configure_msix_intr(dev);
1379
1380         /* Configure for OS presence */
1381         igb_init_manageability(hw);
1382
1383         eth_igb_tx_init(dev);
1384
1385         /* This can fail when allocating mbufs for descriptor rings */
1386         ret = eth_igb_rx_init(dev);
1387         if (ret) {
1388                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1389                 igb_dev_clear_queues(dev);
1390                 return ret;
1391         }
1392
1393         e1000_clear_hw_cntrs_base_generic(hw);
1394
1395         /*
1396          * VLAN Offload Settings
1397          */
1398         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1399                         ETH_VLAN_EXTEND_MASK;
1400         eth_igb_vlan_offload_set(dev, mask);
1401
1402         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1403                 /* Enable VLAN filter since VMDq always use VLAN filter */
1404                 igb_vmdq_vlan_hw_filter_enable(dev);
1405         }
1406
1407         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1408                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1409                 (hw->mac.type == e1000_i211)) {
1410                 /* Configure EITR with the maximum possible value (0xFFFF) */
1411                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1412         }
1413
1414         /* Setup link speed and duplex */
1415         speeds = &dev->data->dev_conf.link_speeds;
1416         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1417                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1418                 hw->mac.autoneg = 1;
1419         } else {
1420                 num_speeds = 0;
1421                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1422
1423                 /* Reset */
1424                 hw->phy.autoneg_advertised = 0;
1425
1426                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1427                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1428                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1429                         num_speeds = -1;
1430                         goto error_invalid_config;
1431                 }
1432                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1433                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1434                         num_speeds++;
1435                 }
1436                 if (*speeds & ETH_LINK_SPEED_10M) {
1437                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1438                         num_speeds++;
1439                 }
1440                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1441                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1442                         num_speeds++;
1443                 }
1444                 if (*speeds & ETH_LINK_SPEED_100M) {
1445                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1446                         num_speeds++;
1447                 }
1448                 if (*speeds & ETH_LINK_SPEED_1G) {
1449                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1450                         num_speeds++;
1451                 }
1452                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1453                         goto error_invalid_config;
1454
1455                 /* Set/reset the mac.autoneg based on the link speed,
1456                  * fixed or not
1457                  */
1458                 if (!autoneg) {
1459                         hw->mac.autoneg = 0;
1460                         hw->mac.forced_speed_duplex =
1461                                         hw->phy.autoneg_advertised;
1462                 } else {
1463                         hw->mac.autoneg = 1;
1464                 }
1465         }
1466
1467         e1000_setup_link(hw);
1468
1469         if (rte_intr_allow_others(intr_handle)) {
1470                 /* check if lsc interrupt is enabled */
1471                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1472                         eth_igb_lsc_interrupt_setup(dev);
1473         } else {
1474                 rte_intr_callback_unregister(intr_handle,
1475                                              eth_igb_interrupt_handler,
1476                                              (void *)dev);
1477                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1478                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1479                                      " no intr multiplex");
1480         }
1481
1482         /* check if rxq interrupt is enabled */
1483         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1484             rte_intr_dp_is_en(intr_handle))
1485                 eth_igb_rxq_interrupt_setup(dev);
1486
1487         /* enable uio/vfio intr/eventfd mapping */
1488         rte_intr_enable(intr_handle);
1489
1490         /* resume enabled intr since hw reset */
1491         igb_intr_enable(dev);
1492
1493         /* restore all types filter */
1494         igb_filter_restore(dev);
1495
1496         PMD_INIT_LOG(DEBUG, "<<");
1497
1498         return 0;
1499
1500 error_invalid_config:
1501         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1502                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1503         igb_dev_clear_queues(dev);
1504         return -EINVAL;
1505 }
1506
1507 /*********************************************************************
1508  *
1509  *  This routine disables all traffic on the adapter by issuing a
1510  *  global reset on the MAC.
1511  *
1512  **********************************************************************/
1513 static void
1514 eth_igb_stop(struct rte_eth_dev *dev)
1515 {
1516         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1518         struct rte_eth_link link;
1519         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1520
1521         igb_intr_disable(hw);
1522
1523         /* disable intr eventfd mapping */
1524         rte_intr_disable(intr_handle);
1525
1526         igb_pf_reset_hw(hw);
1527         E1000_WRITE_REG(hw, E1000_WUC, 0);
1528
1529         /* Set bit for Go Link disconnect */
1530         if (hw->mac.type >= e1000_82580) {
1531                 uint32_t phpm_reg;
1532
1533                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1534                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1535                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1536         }
1537
1538         /* Power down the phy. Needed to make the link go Down */
1539         eth_igb_dev_set_link_down(dev);
1540
1541         igb_dev_clear_queues(dev);
1542
1543         /* clear the recorded link status */
1544         memset(&link, 0, sizeof(link));
1545         rte_igb_dev_atomic_write_link_status(dev, &link);
1546
1547         if (!rte_intr_allow_others(intr_handle))
1548                 /* resume to the default handler */
1549                 rte_intr_callback_register(intr_handle,
1550                                            eth_igb_interrupt_handler,
1551                                            (void *)dev);
1552
1553         /* Clean datapath event and queue/vec mapping */
1554         rte_intr_efd_disable(intr_handle);
1555         if (intr_handle->intr_vec != NULL) {
1556                 rte_free(intr_handle->intr_vec);
1557                 intr_handle->intr_vec = NULL;
1558         }
1559 }
1560
1561 static int
1562 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1563 {
1564         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565
1566         if (hw->phy.media_type == e1000_media_type_copper)
1567                 e1000_power_up_phy(hw);
1568         else
1569                 e1000_power_up_fiber_serdes_link(hw);
1570
1571         return 0;
1572 }
1573
1574 static int
1575 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1576 {
1577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578
1579         if (hw->phy.media_type == e1000_media_type_copper)
1580                 e1000_power_down_phy(hw);
1581         else
1582                 e1000_shutdown_fiber_serdes_link(hw);
1583
1584         return 0;
1585 }
1586
1587 static void
1588 eth_igb_close(struct rte_eth_dev *dev)
1589 {
1590         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         struct e1000_adapter *adapter =
1592                 E1000_DEV_PRIVATE(dev->data->dev_private);
1593         struct rte_eth_link link;
1594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1596
1597         eth_igb_stop(dev);
1598         adapter->stopped = 1;
1599
1600         e1000_phy_hw_reset(hw);
1601         igb_release_manageability(hw);
1602         igb_hw_control_release(hw);
1603
1604         /* Clear bit for Go Link disconnect */
1605         if (hw->mac.type >= e1000_82580) {
1606                 uint32_t phpm_reg;
1607
1608                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1609                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1610                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1611         }
1612
1613         igb_dev_free_queues(dev);
1614
1615         if (intr_handle->intr_vec) {
1616                 rte_free(intr_handle->intr_vec);
1617                 intr_handle->intr_vec = NULL;
1618         }
1619
1620         memset(&link, 0, sizeof(link));
1621         rte_igb_dev_atomic_write_link_status(dev, &link);
1622 }
1623
1624 static int
1625 igb_get_rx_buffer_size(struct e1000_hw *hw)
1626 {
1627         uint32_t rx_buf_size;
1628         if (hw->mac.type == e1000_82576) {
1629                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1630         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1631                 /* PBS needs to be translated according to a lookup table */
1632                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1633                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1634                 rx_buf_size = (rx_buf_size << 10);
1635         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1636                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1637         } else {
1638                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1639         }
1640
1641         return rx_buf_size;
1642 }
1643
1644 /*********************************************************************
1645  *
1646  *  Initialize the hardware
1647  *
1648  **********************************************************************/
1649 static int
1650 igb_hardware_init(struct e1000_hw *hw)
1651 {
1652         uint32_t rx_buf_size;
1653         int diag;
1654
1655         /* Let the firmware know the OS is in control */
1656         igb_hw_control_acquire(hw);
1657
1658         /*
1659          * These parameters control the automatic generation (Tx) and
1660          * response (Rx) to Ethernet PAUSE frames.
1661          * - High water mark should allow for at least two standard size (1518)
1662          *   frames to be received after sending an XOFF.
1663          * - Low water mark works best when it is very near the high water mark.
1664          *   This allows the receiver to restart by sending XON when it has
1665          *   drained a bit. Here we use an arbitrary value of 1500 which will
1666          *   restart after one full frame is pulled from the buffer. There
1667          *   could be several smaller frames in the buffer and if so they will
1668          *   not trigger the XON until their total number reduces the buffer
1669          *   by 1500.
1670          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1671          */
1672         rx_buf_size = igb_get_rx_buffer_size(hw);
1673
1674         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1675         hw->fc.low_water = hw->fc.high_water - 1500;
1676         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1677         hw->fc.send_xon = 1;
1678
1679         /* Set Flow control, use the tunable location if sane */
1680         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1681                 hw->fc.requested_mode = igb_fc_setting;
1682         else
1683                 hw->fc.requested_mode = e1000_fc_none;
1684
1685         /* Issue a global reset */
1686         igb_pf_reset_hw(hw);
1687         E1000_WRITE_REG(hw, E1000_WUC, 0);
1688
1689         diag = e1000_init_hw(hw);
1690         if (diag < 0)
1691                 return diag;
1692
1693         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1694         e1000_get_phy_info(hw);
1695         e1000_check_for_link(hw);
1696
1697         return 0;
1698 }
1699
1700 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1701 static void
1702 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1703 {
1704         int pause_frames;
1705
1706         uint64_t old_gprc  = stats->gprc;
1707         uint64_t old_gptc  = stats->gptc;
1708         uint64_t old_tpr   = stats->tpr;
1709         uint64_t old_tpt   = stats->tpt;
1710         uint64_t old_rpthc = stats->rpthc;
1711         uint64_t old_hgptc = stats->hgptc;
1712
1713         if(hw->phy.media_type == e1000_media_type_copper ||
1714             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1715                 stats->symerrs +=
1716                     E1000_READ_REG(hw,E1000_SYMERRS);
1717                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1718         }
1719
1720         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1721         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1722         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1723         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1724
1725         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1726         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1727         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1728         stats->dc += E1000_READ_REG(hw, E1000_DC);
1729         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1730         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1731         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1732         /*
1733         ** For watchdog management we need to know if we have been
1734         ** paused during the last interval, so capture that here.
1735         */
1736         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1737         stats->xoffrxc += pause_frames;
1738         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1739         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1740         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1741         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1742         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1743         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1744         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1745         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1746         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1747         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1748         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1749         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1750
1751         /* For the 64-bit byte counters the low dword must be read first. */
1752         /* Both registers clear on the read of the high dword */
1753
1754         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1755         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1756         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1757         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1758         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1759         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1760         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1761
1762         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1763         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1764         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1765         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1766         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1767
1768         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1769         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1770
1771         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1772         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1773         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1774         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1775         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1776         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1777
1778         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1779         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1780         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1781         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1782         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1783         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1784         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1785         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1786
1787         /* Interrupt Counts */
1788
1789         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1790         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1791         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1792         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1793         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1794         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1795         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1796         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1797         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1798
1799         /* Host to Card Statistics */
1800
1801         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1802         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1803         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1804         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1805         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1806         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1807         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1808         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1809         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1810         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1811         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1812         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1813         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1814         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1815         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1816         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1817
1818         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1819         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1820         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1821         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1822         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1823         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1824 }
1825
1826 static void
1827 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1828 {
1829         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830         struct e1000_hw_stats *stats =
1831                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1832
1833         igb_read_stats_registers(hw, stats);
1834
1835         if (rte_stats == NULL)
1836                 return;
1837
1838         /* Rx Errors */
1839         rte_stats->imissed = stats->mpc;
1840         rte_stats->ierrors = stats->crcerrs +
1841                              stats->rlec + stats->ruc + stats->roc +
1842                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1843
1844         /* Tx Errors */
1845         rte_stats->oerrors = stats->ecol + stats->latecol;
1846
1847         rte_stats->ipackets = stats->gprc;
1848         rte_stats->opackets = stats->gptc;
1849         rte_stats->ibytes   = stats->gorc;
1850         rte_stats->obytes   = stats->gotc;
1851 }
1852
1853 static void
1854 eth_igb_stats_reset(struct rte_eth_dev *dev)
1855 {
1856         struct e1000_hw_stats *hw_stats =
1857                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1858
1859         /* HW registers are cleared on read */
1860         eth_igb_stats_get(dev, NULL);
1861
1862         /* Reset software totals */
1863         memset(hw_stats, 0, sizeof(*hw_stats));
1864 }
1865
1866 static void
1867 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1868 {
1869         struct e1000_hw_stats *stats =
1870                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1871
1872         /* HW registers are cleared on read */
1873         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1874
1875         /* Reset software totals */
1876         memset(stats, 0, sizeof(*stats));
1877 }
1878
1879 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1880         struct rte_eth_xstat_name *xstats_names,
1881         __rte_unused unsigned int size)
1882 {
1883         unsigned i;
1884
1885         if (xstats_names == NULL)
1886                 return IGB_NB_XSTATS;
1887
1888         /* Note: limit checked in rte_eth_xstats_names() */
1889
1890         for (i = 0; i < IGB_NB_XSTATS; i++) {
1891                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1892                          "%s", rte_igb_stats_strings[i].name);
1893         }
1894
1895         return IGB_NB_XSTATS;
1896 }
1897
1898 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1899                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1900                 unsigned int limit)
1901 {
1902         unsigned int i;
1903
1904         if (!ids) {
1905                 if (xstats_names == NULL)
1906                         return IGB_NB_XSTATS;
1907
1908                 for (i = 0; i < IGB_NB_XSTATS; i++)
1909                         snprintf(xstats_names[i].name,
1910                                         sizeof(xstats_names[i].name),
1911                                         "%s", rte_igb_stats_strings[i].name);
1912
1913                 return IGB_NB_XSTATS;
1914
1915         } else {
1916                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1917
1918                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1919                                 IGB_NB_XSTATS);
1920
1921                 for (i = 0; i < limit; i++) {
1922                         if (ids[i] >= IGB_NB_XSTATS) {
1923                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1924                                 return -1;
1925                         }
1926                         strcpy(xstats_names[i].name,
1927                                         xstats_names_copy[ids[i]].name);
1928                 }
1929                 return limit;
1930         }
1931 }
1932
1933 static int
1934 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1935                    unsigned n)
1936 {
1937         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct e1000_hw_stats *hw_stats =
1939                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1940         unsigned i;
1941
1942         if (n < IGB_NB_XSTATS)
1943                 return IGB_NB_XSTATS;
1944
1945         igb_read_stats_registers(hw, hw_stats);
1946
1947         /* If this is a reset xstats is NULL, and we have cleared the
1948          * registers by reading them.
1949          */
1950         if (!xstats)
1951                 return 0;
1952
1953         /* Extended stats */
1954         for (i = 0; i < IGB_NB_XSTATS; i++) {
1955                 xstats[i].id = i;
1956                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1957                         rte_igb_stats_strings[i].offset);
1958         }
1959
1960         return IGB_NB_XSTATS;
1961 }
1962
1963 static int
1964 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1965                 uint64_t *values, unsigned int n)
1966 {
1967         unsigned int i;
1968
1969         if (!ids) {
1970                 struct e1000_hw *hw =
1971                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972                 struct e1000_hw_stats *hw_stats =
1973                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1974
1975                 if (n < IGB_NB_XSTATS)
1976                         return IGB_NB_XSTATS;
1977
1978                 igb_read_stats_registers(hw, hw_stats);
1979
1980                 /* If this is a reset xstats is NULL, and we have cleared the
1981                  * registers by reading them.
1982                  */
1983                 if (!values)
1984                         return 0;
1985
1986                 /* Extended stats */
1987                 for (i = 0; i < IGB_NB_XSTATS; i++)
1988                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1989                                         rte_igb_stats_strings[i].offset);
1990
1991                 return IGB_NB_XSTATS;
1992
1993         } else {
1994                 uint64_t values_copy[IGB_NB_XSTATS];
1995
1996                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1997                                 IGB_NB_XSTATS);
1998
1999                 for (i = 0; i < n; i++) {
2000                         if (ids[i] >= IGB_NB_XSTATS) {
2001                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2002                                 return -1;
2003                         }
2004                         values[i] = values_copy[ids[i]];
2005                 }
2006                 return n;
2007         }
2008 }
2009
2010 static void
2011 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2012 {
2013         /* Good Rx packets, include VF loopback */
2014         UPDATE_VF_STAT(E1000_VFGPRC,
2015             hw_stats->last_gprc, hw_stats->gprc);
2016
2017         /* Good Rx octets, include VF loopback */
2018         UPDATE_VF_STAT(E1000_VFGORC,
2019             hw_stats->last_gorc, hw_stats->gorc);
2020
2021         /* Good Tx packets, include VF loopback */
2022         UPDATE_VF_STAT(E1000_VFGPTC,
2023             hw_stats->last_gptc, hw_stats->gptc);
2024
2025         /* Good Tx octets, include VF loopback */
2026         UPDATE_VF_STAT(E1000_VFGOTC,
2027             hw_stats->last_gotc, hw_stats->gotc);
2028
2029         /* Rx Multicst packets */
2030         UPDATE_VF_STAT(E1000_VFMPRC,
2031             hw_stats->last_mprc, hw_stats->mprc);
2032
2033         /* Good Rx loopback packets */
2034         UPDATE_VF_STAT(E1000_VFGPRLBC,
2035             hw_stats->last_gprlbc, hw_stats->gprlbc);
2036
2037         /* Good Rx loopback octets */
2038         UPDATE_VF_STAT(E1000_VFGORLBC,
2039             hw_stats->last_gorlbc, hw_stats->gorlbc);
2040
2041         /* Good Tx loopback packets */
2042         UPDATE_VF_STAT(E1000_VFGPTLBC,
2043             hw_stats->last_gptlbc, hw_stats->gptlbc);
2044
2045         /* Good Tx loopback octets */
2046         UPDATE_VF_STAT(E1000_VFGOTLBC,
2047             hw_stats->last_gotlbc, hw_stats->gotlbc);
2048 }
2049
2050 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2051                                      struct rte_eth_xstat_name *xstats_names,
2052                                      __rte_unused unsigned limit)
2053 {
2054         unsigned i;
2055
2056         if (xstats_names != NULL)
2057                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2058                         snprintf(xstats_names[i].name,
2059                                 sizeof(xstats_names[i].name), "%s",
2060                                 rte_igbvf_stats_strings[i].name);
2061                 }
2062         return IGBVF_NB_XSTATS;
2063 }
2064
2065 static int
2066 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2067                      unsigned n)
2068 {
2069         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2071                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2072         unsigned i;
2073
2074         if (n < IGBVF_NB_XSTATS)
2075                 return IGBVF_NB_XSTATS;
2076
2077         igbvf_read_stats_registers(hw, hw_stats);
2078
2079         if (!xstats)
2080                 return 0;
2081
2082         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2083                 xstats[i].id = i;
2084                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2085                         rte_igbvf_stats_strings[i].offset);
2086         }
2087
2088         return IGBVF_NB_XSTATS;
2089 }
2090
2091 static void
2092 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2093 {
2094         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2096                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2097
2098         igbvf_read_stats_registers(hw, hw_stats);
2099
2100         if (rte_stats == NULL)
2101                 return;
2102
2103         rte_stats->ipackets = hw_stats->gprc;
2104         rte_stats->ibytes = hw_stats->gorc;
2105         rte_stats->opackets = hw_stats->gptc;
2106         rte_stats->obytes = hw_stats->gotc;
2107 }
2108
2109 static void
2110 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2111 {
2112         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2113                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2114
2115         /* Sync HW register to the last stats */
2116         eth_igbvf_stats_get(dev, NULL);
2117
2118         /* reset HW current stats*/
2119         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2120                offsetof(struct e1000_vf_stats, gprc));
2121 }
2122
2123 static int
2124 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2125                        size_t fw_size)
2126 {
2127         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128         struct e1000_fw_version fw;
2129         int ret;
2130
2131         e1000_get_fw_version(hw, &fw);
2132
2133         switch (hw->mac.type) {
2134         case e1000_i210:
2135         case e1000_i211:
2136                 if (!(e1000_get_flash_presence_i210(hw))) {
2137                         ret = snprintf(fw_version, fw_size,
2138                                  "%2d.%2d-%d",
2139                                  fw.invm_major, fw.invm_minor,
2140                                  fw.invm_img_type);
2141                         break;
2142                 }
2143                 /* fall through */
2144         default:
2145                 /* if option rom is valid, display its version too */
2146                 if (fw.or_valid) {
2147                         ret = snprintf(fw_version, fw_size,
2148                                  "%d.%d, 0x%08x, %d.%d.%d",
2149                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2150                                  fw.or_major, fw.or_build, fw.or_patch);
2151                 /* no option rom */
2152                 } else {
2153                         if (fw.etrack_id != 0X0000) {
2154                                 ret = snprintf(fw_version, fw_size,
2155                                          "%d.%d, 0x%08x",
2156                                          fw.eep_major, fw.eep_minor,
2157                                          fw.etrack_id);
2158                         } else {
2159                                 ret = snprintf(fw_version, fw_size,
2160                                          "%d.%d.%d",
2161                                          fw.eep_major, fw.eep_minor,
2162                                          fw.eep_build);
2163                         }
2164                 }
2165                 break;
2166         }
2167
2168         ret += 1; /* add the size of '\0' */
2169         if (fw_size < (u32)ret)
2170                 return ret;
2171         else
2172                 return 0;
2173 }
2174
2175 static void
2176 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2177 {
2178         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179
2180         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2181         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2182         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2183         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2184         dev_info->rx_offload_capa =
2185                 DEV_RX_OFFLOAD_VLAN_STRIP |
2186                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2187                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2188                 DEV_RX_OFFLOAD_TCP_CKSUM;
2189         dev_info->tx_offload_capa =
2190                 DEV_TX_OFFLOAD_VLAN_INSERT |
2191                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2192                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2193                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2194                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2195                 DEV_TX_OFFLOAD_TCP_TSO;
2196
2197         switch (hw->mac.type) {
2198         case e1000_82575:
2199                 dev_info->max_rx_queues = 4;
2200                 dev_info->max_tx_queues = 4;
2201                 dev_info->max_vmdq_pools = 0;
2202                 break;
2203
2204         case e1000_82576:
2205                 dev_info->max_rx_queues = 16;
2206                 dev_info->max_tx_queues = 16;
2207                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2208                 dev_info->vmdq_queue_num = 16;
2209                 break;
2210
2211         case e1000_82580:
2212                 dev_info->max_rx_queues = 8;
2213                 dev_info->max_tx_queues = 8;
2214                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2215                 dev_info->vmdq_queue_num = 8;
2216                 break;
2217
2218         case e1000_i350:
2219                 dev_info->max_rx_queues = 8;
2220                 dev_info->max_tx_queues = 8;
2221                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2222                 dev_info->vmdq_queue_num = 8;
2223                 break;
2224
2225         case e1000_i354:
2226                 dev_info->max_rx_queues = 8;
2227                 dev_info->max_tx_queues = 8;
2228                 break;
2229
2230         case e1000_i210:
2231                 dev_info->max_rx_queues = 4;
2232                 dev_info->max_tx_queues = 4;
2233                 dev_info->max_vmdq_pools = 0;
2234                 break;
2235
2236         case e1000_i211:
2237                 dev_info->max_rx_queues = 2;
2238                 dev_info->max_tx_queues = 2;
2239                 dev_info->max_vmdq_pools = 0;
2240                 break;
2241
2242         default:
2243                 /* Should not happen */
2244                 break;
2245         }
2246         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2247         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2248         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2249
2250         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2251                 .rx_thresh = {
2252                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2253                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2254                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2255                 },
2256                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2257                 .rx_drop_en = 0,
2258         };
2259
2260         dev_info->default_txconf = (struct rte_eth_txconf) {
2261                 .tx_thresh = {
2262                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2263                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2264                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2265                 },
2266                 .txq_flags = 0,
2267         };
2268
2269         dev_info->rx_desc_lim = rx_desc_lim;
2270         dev_info->tx_desc_lim = tx_desc_lim;
2271
2272         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2273                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2274                         ETH_LINK_SPEED_1G;
2275 }
2276
2277 static const uint32_t *
2278 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2279 {
2280         static const uint32_t ptypes[] = {
2281                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2282                 RTE_PTYPE_L2_ETHER,
2283                 RTE_PTYPE_L3_IPV4,
2284                 RTE_PTYPE_L3_IPV4_EXT,
2285                 RTE_PTYPE_L3_IPV6,
2286                 RTE_PTYPE_L3_IPV6_EXT,
2287                 RTE_PTYPE_L4_TCP,
2288                 RTE_PTYPE_L4_UDP,
2289                 RTE_PTYPE_L4_SCTP,
2290                 RTE_PTYPE_TUNNEL_IP,
2291                 RTE_PTYPE_INNER_L3_IPV6,
2292                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2293                 RTE_PTYPE_INNER_L4_TCP,
2294                 RTE_PTYPE_INNER_L4_UDP,
2295                 RTE_PTYPE_UNKNOWN
2296         };
2297
2298         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2299             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2300                 return ptypes;
2301         return NULL;
2302 }
2303
2304 static void
2305 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2306 {
2307         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308
2309         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2310         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2311         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2312         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2313         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2314                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2315                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2316                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2317         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2318                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2319                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2320                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2321                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2322                                 DEV_TX_OFFLOAD_TCP_TSO;
2323         switch (hw->mac.type) {
2324         case e1000_vfadapt:
2325                 dev_info->max_rx_queues = 2;
2326                 dev_info->max_tx_queues = 2;
2327                 break;
2328         case e1000_vfadapt_i350:
2329                 dev_info->max_rx_queues = 1;
2330                 dev_info->max_tx_queues = 1;
2331                 break;
2332         default:
2333                 /* Should not happen */
2334                 break;
2335         }
2336
2337         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2338                 .rx_thresh = {
2339                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2340                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2341                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2342                 },
2343                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2344                 .rx_drop_en = 0,
2345         };
2346
2347         dev_info->default_txconf = (struct rte_eth_txconf) {
2348                 .tx_thresh = {
2349                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2350                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2351                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2352                 },
2353                 .txq_flags = 0,
2354         };
2355
2356         dev_info->rx_desc_lim = rx_desc_lim;
2357         dev_info->tx_desc_lim = tx_desc_lim;
2358 }
2359
2360 /* return 0 means link status changed, -1 means not changed */
2361 static int
2362 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2363 {
2364         struct e1000_hw *hw =
2365                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2366         struct rte_eth_link link, old;
2367         int link_check, count;
2368
2369         link_check = 0;
2370         hw->mac.get_link_status = 1;
2371
2372         /* possible wait-to-complete in up to 9 seconds */
2373         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2374                 /* Read the real link status */
2375                 switch (hw->phy.media_type) {
2376                 case e1000_media_type_copper:
2377                         /* Do the work to read phy */
2378                         e1000_check_for_link(hw);
2379                         link_check = !hw->mac.get_link_status;
2380                         break;
2381
2382                 case e1000_media_type_fiber:
2383                         e1000_check_for_link(hw);
2384                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2385                                       E1000_STATUS_LU);
2386                         break;
2387
2388                 case e1000_media_type_internal_serdes:
2389                         e1000_check_for_link(hw);
2390                         link_check = hw->mac.serdes_has_link;
2391                         break;
2392
2393                 /* VF device is type_unknown */
2394                 case e1000_media_type_unknown:
2395                         eth_igbvf_link_update(hw);
2396                         link_check = !hw->mac.get_link_status;
2397                         break;
2398
2399                 default:
2400                         break;
2401                 }
2402                 if (link_check || wait_to_complete == 0)
2403                         break;
2404                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2405         }
2406         memset(&link, 0, sizeof(link));
2407         rte_igb_dev_atomic_read_link_status(dev, &link);
2408         old = link;
2409
2410         /* Now we check if a transition has happened */
2411         if (link_check) {
2412                 uint16_t duplex, speed;
2413                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2414                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2415                                 ETH_LINK_FULL_DUPLEX :
2416                                 ETH_LINK_HALF_DUPLEX;
2417                 link.link_speed = speed;
2418                 link.link_status = ETH_LINK_UP;
2419                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2420                                 ETH_LINK_SPEED_FIXED);
2421         } else if (!link_check) {
2422                 link.link_speed = 0;
2423                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2424                 link.link_status = ETH_LINK_DOWN;
2425                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2426         }
2427         rte_igb_dev_atomic_write_link_status(dev, &link);
2428
2429         /* not changed */
2430         if (old.link_status == link.link_status)
2431                 return -1;
2432
2433         /* changed */
2434         return 0;
2435 }
2436
2437 /*
2438  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2439  * For ASF and Pass Through versions of f/w this means
2440  * that the driver is loaded.
2441  */
2442 static void
2443 igb_hw_control_acquire(struct e1000_hw *hw)
2444 {
2445         uint32_t ctrl_ext;
2446
2447         /* Let firmware know the driver has taken over */
2448         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2449         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2450 }
2451
2452 /*
2453  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2454  * For ASF and Pass Through versions of f/w this means that the
2455  * driver is no longer loaded.
2456  */
2457 static void
2458 igb_hw_control_release(struct e1000_hw *hw)
2459 {
2460         uint32_t ctrl_ext;
2461
2462         /* Let firmware taken over control of h/w */
2463         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2464         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2465                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2466 }
2467
2468 /*
2469  * Bit of a misnomer, what this really means is
2470  * to enable OS management of the system... aka
2471  * to disable special hardware management features.
2472  */
2473 static void
2474 igb_init_manageability(struct e1000_hw *hw)
2475 {
2476         if (e1000_enable_mng_pass_thru(hw)) {
2477                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2478                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2479
2480                 /* disable hardware interception of ARP */
2481                 manc &= ~(E1000_MANC_ARP_EN);
2482
2483                 /* enable receiving management packets to the host */
2484                 manc |= E1000_MANC_EN_MNG2HOST;
2485                 manc2h |= 1 << 5;  /* Mng Port 623 */
2486                 manc2h |= 1 << 6;  /* Mng Port 664 */
2487                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2488                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2489         }
2490 }
2491
2492 static void
2493 igb_release_manageability(struct e1000_hw *hw)
2494 {
2495         if (e1000_enable_mng_pass_thru(hw)) {
2496                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2497
2498                 manc |= E1000_MANC_ARP_EN;
2499                 manc &= ~E1000_MANC_EN_MNG2HOST;
2500
2501                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2502         }
2503 }
2504
2505 static void
2506 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2507 {
2508         struct e1000_hw *hw =
2509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         uint32_t rctl;
2511
2512         rctl = E1000_READ_REG(hw, E1000_RCTL);
2513         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2514         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2515 }
2516
2517 static void
2518 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2519 {
2520         struct e1000_hw *hw =
2521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         uint32_t rctl;
2523
2524         rctl = E1000_READ_REG(hw, E1000_RCTL);
2525         rctl &= (~E1000_RCTL_UPE);
2526         if (dev->data->all_multicast == 1)
2527                 rctl |= E1000_RCTL_MPE;
2528         else
2529                 rctl &= (~E1000_RCTL_MPE);
2530         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2531 }
2532
2533 static void
2534 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2535 {
2536         struct e1000_hw *hw =
2537                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t rctl;
2539
2540         rctl = E1000_READ_REG(hw, E1000_RCTL);
2541         rctl |= E1000_RCTL_MPE;
2542         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2543 }
2544
2545 static void
2546 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2547 {
2548         struct e1000_hw *hw =
2549                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2550         uint32_t rctl;
2551
2552         if (dev->data->promiscuous == 1)
2553                 return; /* must remain in all_multicast mode */
2554         rctl = E1000_READ_REG(hw, E1000_RCTL);
2555         rctl &= (~E1000_RCTL_MPE);
2556         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2557 }
2558
2559 static int
2560 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2561 {
2562         struct e1000_hw *hw =
2563                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564         struct e1000_vfta * shadow_vfta =
2565                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2566         uint32_t vfta;
2567         uint32_t vid_idx;
2568         uint32_t vid_bit;
2569
2570         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2571                               E1000_VFTA_ENTRY_MASK);
2572         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2573         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2574         if (on)
2575                 vfta |= vid_bit;
2576         else
2577                 vfta &= ~vid_bit;
2578         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2579
2580         /* update local VFTA copy */
2581         shadow_vfta->vfta[vid_idx] = vfta;
2582
2583         return 0;
2584 }
2585
2586 static int
2587 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2588                       enum rte_vlan_type vlan_type,
2589                       uint16_t tpid)
2590 {
2591         struct e1000_hw *hw =
2592                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         uint32_t reg, qinq;
2594
2595         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2596         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2597
2598         /* only outer TPID of double VLAN can be configured*/
2599         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2600                 reg = E1000_READ_REG(hw, E1000_VET);
2601                 reg = (reg & (~E1000_VET_VET_EXT)) |
2602                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2603                 E1000_WRITE_REG(hw, E1000_VET, reg);
2604
2605                 return 0;
2606         }
2607
2608         /* all other TPID values are read-only*/
2609         PMD_DRV_LOG(ERR, "Not supported");
2610
2611         return -ENOTSUP;
2612 }
2613
2614 static void
2615 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2616 {
2617         struct e1000_hw *hw =
2618                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619         uint32_t reg;
2620
2621         /* Filter Table Disable */
2622         reg = E1000_READ_REG(hw, E1000_RCTL);
2623         reg &= ~E1000_RCTL_CFIEN;
2624         reg &= ~E1000_RCTL_VFE;
2625         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2626 }
2627
2628 static void
2629 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2630 {
2631         struct e1000_hw *hw =
2632                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2633         struct e1000_vfta * shadow_vfta =
2634                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2635         uint32_t reg;
2636         int i;
2637
2638         /* Filter Table Enable, CFI not used for packet acceptance */
2639         reg = E1000_READ_REG(hw, E1000_RCTL);
2640         reg &= ~E1000_RCTL_CFIEN;
2641         reg |= E1000_RCTL_VFE;
2642         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2643
2644         /* restore VFTA table */
2645         for (i = 0; i < IGB_VFTA_SIZE; i++)
2646                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2647 }
2648
2649 static void
2650 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2651 {
2652         struct e1000_hw *hw =
2653                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2654         uint32_t reg;
2655
2656         /* VLAN Mode Disable */
2657         reg = E1000_READ_REG(hw, E1000_CTRL);
2658         reg &= ~E1000_CTRL_VME;
2659         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2660 }
2661
2662 static void
2663 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2664 {
2665         struct e1000_hw *hw =
2666                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667         uint32_t reg;
2668
2669         /* VLAN Mode Enable */
2670         reg = E1000_READ_REG(hw, E1000_CTRL);
2671         reg |= E1000_CTRL_VME;
2672         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2673 }
2674
2675 static void
2676 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2677 {
2678         struct e1000_hw *hw =
2679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         uint32_t reg;
2681
2682         /* CTRL_EXT: Extended VLAN */
2683         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2684         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2685         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2686
2687         /* Update maximum packet length */
2688         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2689                 E1000_WRITE_REG(hw, E1000_RLPML,
2690                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2691                                                 VLAN_TAG_SIZE);
2692 }
2693
2694 static void
2695 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2696 {
2697         struct e1000_hw *hw =
2698                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699         uint32_t reg;
2700
2701         /* CTRL_EXT: Extended VLAN */
2702         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2703         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2704         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2705
2706         /* Update maximum packet length */
2707         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2708                 E1000_WRITE_REG(hw, E1000_RLPML,
2709                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2710                                                 2 * VLAN_TAG_SIZE);
2711 }
2712
2713 static void
2714 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2715 {
2716         if(mask & ETH_VLAN_STRIP_MASK){
2717                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2718                         igb_vlan_hw_strip_enable(dev);
2719                 else
2720                         igb_vlan_hw_strip_disable(dev);
2721         }
2722
2723         if(mask & ETH_VLAN_FILTER_MASK){
2724                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2725                         igb_vlan_hw_filter_enable(dev);
2726                 else
2727                         igb_vlan_hw_filter_disable(dev);
2728         }
2729
2730         if(mask & ETH_VLAN_EXTEND_MASK){
2731                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2732                         igb_vlan_hw_extend_enable(dev);
2733                 else
2734                         igb_vlan_hw_extend_disable(dev);
2735         }
2736 }
2737
2738
2739 /**
2740  * It enables the interrupt mask and then enable the interrupt.
2741  *
2742  * @param dev
2743  *  Pointer to struct rte_eth_dev.
2744  *
2745  * @return
2746  *  - On success, zero.
2747  *  - On failure, a negative value.
2748  */
2749 static int
2750 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2751 {
2752         struct e1000_interrupt *intr =
2753                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2754
2755         intr->mask |= E1000_ICR_LSC;
2756
2757         return 0;
2758 }
2759
2760 /* It clears the interrupt causes and enables the interrupt.
2761  * It will be called once only during nic initialized.
2762  *
2763  * @param dev
2764  *  Pointer to struct rte_eth_dev.
2765  *
2766  * @return
2767  *  - On success, zero.
2768  *  - On failure, a negative value.
2769  */
2770 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2771 {
2772         uint32_t mask, regval;
2773         struct e1000_hw *hw =
2774                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775         struct rte_eth_dev_info dev_info;
2776
2777         memset(&dev_info, 0, sizeof(dev_info));
2778         eth_igb_infos_get(dev, &dev_info);
2779
2780         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2781         regval = E1000_READ_REG(hw, E1000_EIMS);
2782         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2783
2784         return 0;
2785 }
2786
2787 /*
2788  * It reads ICR and gets interrupt causes, check it and set a bit flag
2789  * to update link status.
2790  *
2791  * @param dev
2792  *  Pointer to struct rte_eth_dev.
2793  *
2794  * @return
2795  *  - On success, zero.
2796  *  - On failure, a negative value.
2797  */
2798 static int
2799 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2800 {
2801         uint32_t icr;
2802         struct e1000_hw *hw =
2803                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2804         struct e1000_interrupt *intr =
2805                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2806
2807         igb_intr_disable(hw);
2808
2809         /* read-on-clear nic registers here */
2810         icr = E1000_READ_REG(hw, E1000_ICR);
2811
2812         intr->flags = 0;
2813         if (icr & E1000_ICR_LSC) {
2814                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2815         }
2816
2817         if (icr & E1000_ICR_VMMB)
2818                 intr->flags |= E1000_FLAG_MAILBOX;
2819
2820         return 0;
2821 }
2822
2823 /*
2824  * It executes link_update after knowing an interrupt is prsent.
2825  *
2826  * @param dev
2827  *  Pointer to struct rte_eth_dev.
2828  *
2829  * @return
2830  *  - On success, zero.
2831  *  - On failure, a negative value.
2832  */
2833 static int
2834 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2835                          struct rte_intr_handle *intr_handle)
2836 {
2837         struct e1000_hw *hw =
2838                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct e1000_interrupt *intr =
2840                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2841         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2842         uint32_t tctl, rctl;
2843         struct rte_eth_link link;
2844         int ret;
2845
2846         if (intr->flags & E1000_FLAG_MAILBOX) {
2847                 igb_pf_mbx_process(dev);
2848                 intr->flags &= ~E1000_FLAG_MAILBOX;
2849         }
2850
2851         igb_intr_enable(dev);
2852         rte_intr_enable(intr_handle);
2853
2854         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2855                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2856
2857                 /* set get_link_status to check register later */
2858                 hw->mac.get_link_status = 1;
2859                 ret = eth_igb_link_update(dev, 0);
2860
2861                 /* check if link has changed */
2862                 if (ret < 0)
2863                         return 0;
2864
2865                 memset(&link, 0, sizeof(link));
2866                 rte_igb_dev_atomic_read_link_status(dev, &link);
2867                 if (link.link_status) {
2868                         PMD_INIT_LOG(INFO,
2869                                      " Port %d: Link Up - speed %u Mbps - %s",
2870                                      dev->data->port_id,
2871                                      (unsigned)link.link_speed,
2872                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2873                                      "full-duplex" : "half-duplex");
2874                 } else {
2875                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2876                                      dev->data->port_id);
2877                 }
2878
2879                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2880                              pci_dev->addr.domain,
2881                              pci_dev->addr.bus,
2882                              pci_dev->addr.devid,
2883                              pci_dev->addr.function);
2884                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2885                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2886                 if (link.link_status) {
2887                         /* enable Tx/Rx */
2888                         tctl |= E1000_TCTL_EN;
2889                         rctl |= E1000_RCTL_EN;
2890                 } else {
2891                         /* disable Tx/Rx */
2892                         tctl &= ~E1000_TCTL_EN;
2893                         rctl &= ~E1000_RCTL_EN;
2894                 }
2895                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2896                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2897                 E1000_WRITE_FLUSH(hw);
2898                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2899         }
2900
2901         return 0;
2902 }
2903
2904 /**
2905  * Interrupt handler which shall be registered at first.
2906  *
2907  * @param handle
2908  *  Pointer to interrupt handle.
2909  * @param param
2910  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2911  *
2912  * @return
2913  *  void
2914  */
2915 static void
2916 eth_igb_interrupt_handler(void *param)
2917 {
2918         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2919
2920         eth_igb_interrupt_get_status(dev);
2921         eth_igb_interrupt_action(dev, dev->intr_handle);
2922 }
2923
2924 static int
2925 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2926 {
2927         uint32_t eicr;
2928         struct e1000_hw *hw =
2929                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2930         struct e1000_interrupt *intr =
2931                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2932
2933         igbvf_intr_disable(hw);
2934
2935         /* read-on-clear nic registers here */
2936         eicr = E1000_READ_REG(hw, E1000_EICR);
2937         intr->flags = 0;
2938
2939         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2940                 intr->flags |= E1000_FLAG_MAILBOX;
2941
2942         return 0;
2943 }
2944
2945 void igbvf_mbx_process(struct rte_eth_dev *dev)
2946 {
2947         struct e1000_hw *hw =
2948                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         struct e1000_mbx_info *mbx = &hw->mbx;
2950         u32 in_msg = 0;
2951
2952         if (mbx->ops.read(hw, &in_msg, 1, 0))
2953                 return;
2954
2955         /* PF reset VF event */
2956         if (in_msg == E1000_PF_CONTROL_MSG)
2957                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2958 }
2959
2960 static int
2961 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2962 {
2963         struct e1000_interrupt *intr =
2964                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2965
2966         if (intr->flags & E1000_FLAG_MAILBOX) {
2967                 igbvf_mbx_process(dev);
2968                 intr->flags &= ~E1000_FLAG_MAILBOX;
2969         }
2970
2971         igbvf_intr_enable(dev);
2972         rte_intr_enable(intr_handle);
2973
2974         return 0;
2975 }
2976
2977 static void
2978 eth_igbvf_interrupt_handler(void *param)
2979 {
2980         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2981
2982         eth_igbvf_interrupt_get_status(dev);
2983         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2984 }
2985
2986 static int
2987 eth_igb_led_on(struct rte_eth_dev *dev)
2988 {
2989         struct e1000_hw *hw;
2990
2991         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2992         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2993 }
2994
2995 static int
2996 eth_igb_led_off(struct rte_eth_dev *dev)
2997 {
2998         struct e1000_hw *hw;
2999
3000         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3002 }
3003
3004 static int
3005 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3006 {
3007         struct e1000_hw *hw;
3008         uint32_t ctrl;
3009         int tx_pause;
3010         int rx_pause;
3011
3012         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         fc_conf->pause_time = hw->fc.pause_time;
3014         fc_conf->high_water = hw->fc.high_water;
3015         fc_conf->low_water = hw->fc.low_water;
3016         fc_conf->send_xon = hw->fc.send_xon;
3017         fc_conf->autoneg = hw->mac.autoneg;
3018
3019         /*
3020          * Return rx_pause and tx_pause status according to actual setting of
3021          * the TFCE and RFCE bits in the CTRL register.
3022          */
3023         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3024         if (ctrl & E1000_CTRL_TFCE)
3025                 tx_pause = 1;
3026         else
3027                 tx_pause = 0;
3028
3029         if (ctrl & E1000_CTRL_RFCE)
3030                 rx_pause = 1;
3031         else
3032                 rx_pause = 0;
3033
3034         if (rx_pause && tx_pause)
3035                 fc_conf->mode = RTE_FC_FULL;
3036         else if (rx_pause)
3037                 fc_conf->mode = RTE_FC_RX_PAUSE;
3038         else if (tx_pause)
3039                 fc_conf->mode = RTE_FC_TX_PAUSE;
3040         else
3041                 fc_conf->mode = RTE_FC_NONE;
3042
3043         return 0;
3044 }
3045
3046 static int
3047 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3048 {
3049         struct e1000_hw *hw;
3050         int err;
3051         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3052                 e1000_fc_none,
3053                 e1000_fc_rx_pause,
3054                 e1000_fc_tx_pause,
3055                 e1000_fc_full
3056         };
3057         uint32_t rx_buf_size;
3058         uint32_t max_high_water;
3059         uint32_t rctl;
3060
3061         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062         if (fc_conf->autoneg != hw->mac.autoneg)
3063                 return -ENOTSUP;
3064         rx_buf_size = igb_get_rx_buffer_size(hw);
3065         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3066
3067         /* At least reserve one Ethernet frame for watermark */
3068         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3069         if ((fc_conf->high_water > max_high_water) ||
3070             (fc_conf->high_water < fc_conf->low_water)) {
3071                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3072                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3073                 return -EINVAL;
3074         }
3075
3076         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3077         hw->fc.pause_time     = fc_conf->pause_time;
3078         hw->fc.high_water     = fc_conf->high_water;
3079         hw->fc.low_water      = fc_conf->low_water;
3080         hw->fc.send_xon       = fc_conf->send_xon;
3081
3082         err = e1000_setup_link_generic(hw);
3083         if (err == E1000_SUCCESS) {
3084
3085                 /* check if we want to forward MAC frames - driver doesn't have native
3086                  * capability to do that, so we'll write the registers ourselves */
3087
3088                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3089
3090                 /* set or clear MFLCN.PMCF bit depending on configuration */
3091                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3092                         rctl |= E1000_RCTL_PMCF;
3093                 else
3094                         rctl &= ~E1000_RCTL_PMCF;
3095
3096                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3097                 E1000_WRITE_FLUSH(hw);
3098
3099                 return 0;
3100         }
3101
3102         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3103         return -EIO;
3104 }
3105
3106 #define E1000_RAH_POOLSEL_SHIFT      (18)
3107 static int
3108 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3109                 uint32_t index, uint32_t pool)
3110 {
3111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3112         uint32_t rah;
3113
3114         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3115         rah = E1000_READ_REG(hw, E1000_RAH(index));
3116         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3117         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3118         return 0;
3119 }
3120
3121 static void
3122 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3123 {
3124         uint8_t addr[ETHER_ADDR_LEN];
3125         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126
3127         memset(addr, 0, sizeof(addr));
3128
3129         e1000_rar_set(hw, addr, index);
3130 }
3131
3132 static void
3133 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3134                                 struct ether_addr *addr)
3135 {
3136         eth_igb_rar_clear(dev, 0);
3137
3138         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3139 }
3140 /*
3141  * Virtual Function operations
3142  */
3143 static void
3144 igbvf_intr_disable(struct e1000_hw *hw)
3145 {
3146         PMD_INIT_FUNC_TRACE();
3147
3148         /* Clear interrupt mask to stop from interrupts being generated */
3149         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3150
3151         E1000_WRITE_FLUSH(hw);
3152 }
3153
3154 static void
3155 igbvf_stop_adapter(struct rte_eth_dev *dev)
3156 {
3157         u32 reg_val;
3158         u16 i;
3159         struct rte_eth_dev_info dev_info;
3160         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161
3162         memset(&dev_info, 0, sizeof(dev_info));
3163         eth_igbvf_infos_get(dev, &dev_info);
3164
3165         /* Clear interrupt mask to stop from interrupts being generated */
3166         igbvf_intr_disable(hw);
3167
3168         /* Clear any pending interrupts, flush previous writes */
3169         E1000_READ_REG(hw, E1000_EICR);
3170
3171         /* Disable the transmit unit.  Each queue must be disabled. */
3172         for (i = 0; i < dev_info.max_tx_queues; i++)
3173                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3174
3175         /* Disable the receive unit by stopping each queue */
3176         for (i = 0; i < dev_info.max_rx_queues; i++) {
3177                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3178                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3179                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3180                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3181                         ;
3182         }
3183
3184         /* flush all queues disables */
3185         E1000_WRITE_FLUSH(hw);
3186         msec_delay(2);
3187 }
3188
3189 static int eth_igbvf_link_update(struct e1000_hw *hw)
3190 {
3191         struct e1000_mbx_info *mbx = &hw->mbx;
3192         struct e1000_mac_info *mac = &hw->mac;
3193         int ret_val = E1000_SUCCESS;
3194
3195         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3196
3197         /*
3198          * We only want to run this if there has been a rst asserted.
3199          * in this case that could mean a link change, device reset,
3200          * or a virtual function reset
3201          */
3202
3203         /* If we were hit with a reset or timeout drop the link */
3204         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3205                 mac->get_link_status = TRUE;
3206
3207         if (!mac->get_link_status)
3208                 goto out;
3209
3210         /* if link status is down no point in checking to see if pf is up */
3211         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3212                 goto out;
3213
3214         /* if we passed all the tests above then the link is up and we no
3215          * longer need to check for link */
3216         mac->get_link_status = FALSE;
3217
3218 out:
3219         return ret_val;
3220 }
3221
3222
3223 static int
3224 igbvf_dev_configure(struct rte_eth_dev *dev)
3225 {
3226         struct rte_eth_conf* conf = &dev->data->dev_conf;
3227
3228         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3229                      dev->data->port_id);
3230
3231         /*
3232          * VF has no ability to enable/disable HW CRC
3233          * Keep the persistent behavior the same as Host PF
3234          */
3235 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3236         if (!conf->rxmode.hw_strip_crc) {
3237                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3238                 conf->rxmode.hw_strip_crc = 1;
3239         }
3240 #else
3241         if (conf->rxmode.hw_strip_crc) {
3242                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3243                 conf->rxmode.hw_strip_crc = 0;
3244         }
3245 #endif
3246
3247         return 0;
3248 }
3249
3250 static int
3251 igbvf_dev_start(struct rte_eth_dev *dev)
3252 {
3253         struct e1000_hw *hw =
3254                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3255         struct e1000_adapter *adapter =
3256                 E1000_DEV_PRIVATE(dev->data->dev_private);
3257         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3258         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3259         int ret;
3260         uint32_t intr_vector = 0;
3261
3262         PMD_INIT_FUNC_TRACE();
3263
3264         hw->mac.ops.reset_hw(hw);
3265         adapter->stopped = 0;
3266
3267         /* Set all vfta */
3268         igbvf_set_vfta_all(dev,1);
3269
3270         eth_igbvf_tx_init(dev);
3271
3272         /* This can fail when allocating mbufs for descriptor rings */
3273         ret = eth_igbvf_rx_init(dev);
3274         if (ret) {
3275                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3276                 igb_dev_clear_queues(dev);
3277                 return ret;
3278         }
3279
3280         /* check and configure queue intr-vector mapping */
3281         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3282                 intr_vector = dev->data->nb_rx_queues;
3283                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3284                 if (ret)
3285                         return ret;
3286         }
3287
3288         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3289                 intr_handle->intr_vec =
3290                         rte_zmalloc("intr_vec",
3291                                     dev->data->nb_rx_queues * sizeof(int), 0);
3292                 if (!intr_handle->intr_vec) {
3293                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3294                                      " intr_vec", dev->data->nb_rx_queues);
3295                         return -ENOMEM;
3296                 }
3297         }
3298
3299         eth_igbvf_configure_msix_intr(dev);
3300
3301         /* enable uio/vfio intr/eventfd mapping */
3302         rte_intr_enable(intr_handle);
3303
3304         /* resume enabled intr since hw reset */
3305         igbvf_intr_enable(dev);
3306
3307         return 0;
3308 }
3309
3310 static void
3311 igbvf_dev_stop(struct rte_eth_dev *dev)
3312 {
3313         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3315
3316         PMD_INIT_FUNC_TRACE();
3317
3318         igbvf_stop_adapter(dev);
3319
3320         /*
3321           * Clear what we set, but we still keep shadow_vfta to
3322           * restore after device starts
3323           */
3324         igbvf_set_vfta_all(dev,0);
3325
3326         igb_dev_clear_queues(dev);
3327
3328         /* disable intr eventfd mapping */
3329         rte_intr_disable(intr_handle);
3330
3331         /* Clean datapath event and queue/vec mapping */
3332         rte_intr_efd_disable(intr_handle);
3333         if (intr_handle->intr_vec) {
3334                 rte_free(intr_handle->intr_vec);
3335                 intr_handle->intr_vec = NULL;
3336         }
3337 }
3338
3339 static void
3340 igbvf_dev_close(struct rte_eth_dev *dev)
3341 {
3342         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343         struct e1000_adapter *adapter =
3344                 E1000_DEV_PRIVATE(dev->data->dev_private);
3345         struct ether_addr addr;
3346
3347         PMD_INIT_FUNC_TRACE();
3348
3349         e1000_reset_hw(hw);
3350
3351         igbvf_dev_stop(dev);
3352         adapter->stopped = 1;
3353         igb_dev_free_queues(dev);
3354
3355         /**
3356          * reprogram the RAR with a zero mac address,
3357          * to ensure that the VF traffic goes to the PF
3358          * after stop, close and detach of the VF.
3359          **/
3360
3361         memset(&addr, 0, sizeof(addr));
3362         igbvf_default_mac_addr_set(dev, &addr);
3363 }
3364
3365 static void
3366 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3367 {
3368         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369
3370         /* Set both unicast and multicast promisc */
3371         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3372 }
3373
3374 static void
3375 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3376 {
3377         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378
3379         /* If in allmulticast mode leave multicast promisc */
3380         if (dev->data->all_multicast == 1)
3381                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3382         else
3383                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3384 }
3385
3386 static void
3387 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3388 {
3389         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3390
3391         /* In promiscuous mode multicast promisc already set */
3392         if (dev->data->promiscuous == 0)
3393                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3394 }
3395
3396 static void
3397 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3398 {
3399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400
3401         /* In promiscuous mode leave multicast promisc enabled */
3402         if (dev->data->promiscuous == 0)
3403                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3404 }
3405
3406 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3407 {
3408         struct e1000_mbx_info *mbx = &hw->mbx;
3409         uint32_t msgbuf[2];
3410         s32 err;
3411
3412         /* After set vlan, vlan strip will also be enabled in igb driver*/
3413         msgbuf[0] = E1000_VF_SET_VLAN;
3414         msgbuf[1] = vid;
3415         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3416         if (on)
3417                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3418
3419         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3420         if (err)
3421                 goto mbx_err;
3422
3423         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3424         if (err)
3425                 goto mbx_err;
3426
3427         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3428         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3429                 err = -EINVAL;
3430
3431 mbx_err:
3432         return err;
3433 }
3434
3435 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3436 {
3437         struct e1000_hw *hw =
3438                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         struct e1000_vfta * shadow_vfta =
3440                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3441         int i = 0, j = 0, vfta = 0, mask = 1;
3442
3443         for (i = 0; i < IGB_VFTA_SIZE; i++){
3444                 vfta = shadow_vfta->vfta[i];
3445                 if(vfta){
3446                         mask = 1;
3447                         for (j = 0; j < 32; j++){
3448                                 if(vfta & mask)
3449                                         igbvf_set_vfta(hw,
3450                                                 (uint16_t)((i<<5)+j), on);
3451                                 mask<<=1;
3452                         }
3453                 }
3454         }
3455
3456 }
3457
3458 static int
3459 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3460 {
3461         struct e1000_hw *hw =
3462                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463         struct e1000_vfta * shadow_vfta =
3464                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3465         uint32_t vid_idx = 0;
3466         uint32_t vid_bit = 0;
3467         int ret = 0;
3468
3469         PMD_INIT_FUNC_TRACE();
3470
3471         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3472         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3473         if(ret){
3474                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3475                 return ret;
3476         }
3477         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3478         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3479
3480         /*Save what we set and retore it after device reset*/
3481         if (on)
3482                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3483         else
3484                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3485
3486         return 0;
3487 }
3488
3489 static void
3490 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3491 {
3492         struct e1000_hw *hw =
3493                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494
3495         /* index is not used by rar_set() */
3496         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3497 }
3498
3499
3500 static int
3501 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3502                         struct rte_eth_rss_reta_entry64 *reta_conf,
3503                         uint16_t reta_size)
3504 {
3505         uint8_t i, j, mask;
3506         uint32_t reta, r;
3507         uint16_t idx, shift;
3508         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509
3510         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3511                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3512                         "(%d) doesn't match the number hardware can supported "
3513                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3514                 return -EINVAL;
3515         }
3516
3517         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3518                 idx = i / RTE_RETA_GROUP_SIZE;
3519                 shift = i % RTE_RETA_GROUP_SIZE;
3520                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3521                                                 IGB_4_BIT_MASK);
3522                 if (!mask)
3523                         continue;
3524                 if (mask == IGB_4_BIT_MASK)
3525                         r = 0;
3526                 else
3527                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3528                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3529                         if (mask & (0x1 << j))
3530                                 reta |= reta_conf[idx].reta[shift + j] <<
3531                                                         (CHAR_BIT * j);
3532                         else
3533                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3534                 }
3535                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3536         }
3537
3538         return 0;
3539 }
3540
3541 static int
3542 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3543                        struct rte_eth_rss_reta_entry64 *reta_conf,
3544                        uint16_t reta_size)
3545 {
3546         uint8_t i, j, mask;
3547         uint32_t reta;
3548         uint16_t idx, shift;
3549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550
3551         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3552                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3553                         "(%d) doesn't match the number hardware can supported "
3554                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3555                 return -EINVAL;
3556         }
3557
3558         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3559                 idx = i / RTE_RETA_GROUP_SIZE;
3560                 shift = i % RTE_RETA_GROUP_SIZE;
3561                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3562                                                 IGB_4_BIT_MASK);
3563                 if (!mask)
3564                         continue;
3565                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3566                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3567                         if (mask & (0x1 << j))
3568                                 reta_conf[idx].reta[shift + j] =
3569                                         ((reta >> (CHAR_BIT * j)) &
3570                                                 IGB_8_BIT_MASK);
3571                 }
3572         }
3573
3574         return 0;
3575 }
3576
3577 int
3578 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3579                         struct rte_eth_syn_filter *filter,
3580                         bool add)
3581 {
3582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3583         struct e1000_filter_info *filter_info =
3584                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3585         uint32_t synqf, rfctl;
3586
3587         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3588                 return -EINVAL;
3589
3590         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3591
3592         if (add) {
3593                 if (synqf & E1000_SYN_FILTER_ENABLE)
3594                         return -EINVAL;
3595
3596                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3597                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3598
3599                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3600                 if (filter->hig_pri)
3601                         rfctl |= E1000_RFCTL_SYNQFP;
3602                 else
3603                         rfctl &= ~E1000_RFCTL_SYNQFP;
3604
3605                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3606         } else {
3607                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3608                         return -ENOENT;
3609                 synqf = 0;
3610         }
3611
3612         filter_info->syn_info = synqf;
3613         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3614         E1000_WRITE_FLUSH(hw);
3615         return 0;
3616 }
3617
3618 static int
3619 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3620                         struct rte_eth_syn_filter *filter)
3621 {
3622         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623         uint32_t synqf, rfctl;
3624
3625         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3626         if (synqf & E1000_SYN_FILTER_ENABLE) {
3627                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3628                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3629                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3630                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3631                 return 0;
3632         }
3633
3634         return -ENOENT;
3635 }
3636
3637 static int
3638 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3639                         enum rte_filter_op filter_op,
3640                         void *arg)
3641 {
3642         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         int ret;
3644
3645         MAC_TYPE_FILTER_SUP(hw->mac.type);
3646
3647         if (filter_op == RTE_ETH_FILTER_NOP)
3648                 return 0;
3649
3650         if (arg == NULL) {
3651                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3652                             filter_op);
3653                 return -EINVAL;
3654         }
3655
3656         switch (filter_op) {
3657         case RTE_ETH_FILTER_ADD:
3658                 ret = eth_igb_syn_filter_set(dev,
3659                                 (struct rte_eth_syn_filter *)arg,
3660                                 TRUE);
3661                 break;
3662         case RTE_ETH_FILTER_DELETE:
3663                 ret = eth_igb_syn_filter_set(dev,
3664                                 (struct rte_eth_syn_filter *)arg,
3665                                 FALSE);
3666                 break;
3667         case RTE_ETH_FILTER_GET:
3668                 ret = eth_igb_syn_filter_get(dev,
3669                                 (struct rte_eth_syn_filter *)arg);
3670                 break;
3671         default:
3672                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3673                 ret = -EINVAL;
3674                 break;
3675         }
3676
3677         return ret;
3678 }
3679
3680 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3681 static inline int
3682 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3683                         struct e1000_2tuple_filter_info *filter_info)
3684 {
3685         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3686                 return -EINVAL;
3687         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3688                 return -EINVAL;  /* filter index is out of range. */
3689         if (filter->tcp_flags > TCP_FLAG_ALL)
3690                 return -EINVAL;  /* flags is invalid. */
3691
3692         switch (filter->dst_port_mask) {
3693         case UINT16_MAX:
3694                 filter_info->dst_port_mask = 0;
3695                 filter_info->dst_port = filter->dst_port;
3696                 break;
3697         case 0:
3698                 filter_info->dst_port_mask = 1;
3699                 break;
3700         default:
3701                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3702                 return -EINVAL;
3703         }
3704
3705         switch (filter->proto_mask) {
3706         case UINT8_MAX:
3707                 filter_info->proto_mask = 0;
3708                 filter_info->proto = filter->proto;
3709                 break;
3710         case 0:
3711                 filter_info->proto_mask = 1;
3712                 break;
3713         default:
3714                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3715                 return -EINVAL;
3716         }
3717
3718         filter_info->priority = (uint8_t)filter->priority;
3719         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3720                 filter_info->tcp_flags = filter->tcp_flags;
3721         else
3722                 filter_info->tcp_flags = 0;
3723
3724         return 0;
3725 }
3726
3727 static inline struct e1000_2tuple_filter *
3728 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3729                         struct e1000_2tuple_filter_info *key)
3730 {
3731         struct e1000_2tuple_filter *it;
3732
3733         TAILQ_FOREACH(it, filter_list, entries) {
3734                 if (memcmp(key, &it->filter_info,
3735                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3736                         return it;
3737                 }
3738         }
3739         return NULL;
3740 }
3741
3742 /* inject a igb 2tuple filter to HW */
3743 static inline void
3744 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3745                            struct e1000_2tuple_filter *filter)
3746 {
3747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3749         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3750         int i;
3751
3752         i = filter->index;
3753         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3754         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3755                 imir |= E1000_IMIR_PORT_BP;
3756         else
3757                 imir &= ~E1000_IMIR_PORT_BP;
3758
3759         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3760
3761         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3762         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3763         ttqf |= (uint32_t)(filter->filter_info.proto &
3764                                                 E1000_TTQF_PROTOCOL_MASK);
3765         if (filter->filter_info.proto_mask == 0)
3766                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3767
3768         /* tcp flags bits setting. */
3769         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3770                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3771                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3772                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3773                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3774                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3775                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3776                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3777                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3778                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3779                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3780                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3781                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3782         } else {
3783                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3784         }
3785         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3786         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3787         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3788 }
3789
3790 /*
3791  * igb_add_2tuple_filter - add a 2tuple filter
3792  *
3793  * @param
3794  * dev: Pointer to struct rte_eth_dev.
3795  * ntuple_filter: ponter to the filter that will be added.
3796  *
3797  * @return
3798  *    - On success, zero.
3799  *    - On failure, a negative value.
3800  */
3801 static int
3802 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3803                         struct rte_eth_ntuple_filter *ntuple_filter)
3804 {
3805         struct e1000_filter_info *filter_info =
3806                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3807         struct e1000_2tuple_filter *filter;
3808         int i, ret;
3809
3810         filter = rte_zmalloc("e1000_2tuple_filter",
3811                         sizeof(struct e1000_2tuple_filter), 0);
3812         if (filter == NULL)
3813                 return -ENOMEM;
3814
3815         ret = ntuple_filter_to_2tuple(ntuple_filter,
3816                                       &filter->filter_info);
3817         if (ret < 0) {
3818                 rte_free(filter);
3819                 return ret;
3820         }
3821         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3822                                          &filter->filter_info) != NULL) {
3823                 PMD_DRV_LOG(ERR, "filter exists.");
3824                 rte_free(filter);
3825                 return -EEXIST;
3826         }
3827         filter->queue = ntuple_filter->queue;
3828
3829         /*
3830          * look for an unused 2tuple filter index,
3831          * and insert the filter to list.
3832          */
3833         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3834                 if (!(filter_info->twotuple_mask & (1 << i))) {
3835                         filter_info->twotuple_mask |= 1 << i;
3836                         filter->index = i;
3837                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3838                                           filter,
3839                                           entries);
3840                         break;
3841                 }
3842         }
3843         if (i >= E1000_MAX_TTQF_FILTERS) {
3844                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3845                 rte_free(filter);
3846                 return -ENOSYS;
3847         }
3848
3849         igb_inject_2uple_filter(dev, filter);
3850         return 0;
3851 }
3852
3853 /*
3854  * igb_remove_2tuple_filter - remove a 2tuple filter
3855  *
3856  * @param
3857  * dev: Pointer to struct rte_eth_dev.
3858  * ntuple_filter: ponter to the filter that will be removed.
3859  *
3860  * @return
3861  *    - On success, zero.
3862  *    - On failure, a negative value.
3863  */
3864 static int
3865 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3866                         struct rte_eth_ntuple_filter *ntuple_filter)
3867 {
3868         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3869         struct e1000_filter_info *filter_info =
3870                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3871         struct e1000_2tuple_filter_info filter_2tuple;
3872         struct e1000_2tuple_filter *filter;
3873         int ret;
3874
3875         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3876         ret = ntuple_filter_to_2tuple(ntuple_filter,
3877                                       &filter_2tuple);
3878         if (ret < 0)
3879                 return ret;
3880
3881         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3882                                          &filter_2tuple);
3883         if (filter == NULL) {
3884                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3885                 return -ENOENT;
3886         }
3887
3888         filter_info->twotuple_mask &= ~(1 << filter->index);
3889         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3890         rte_free(filter);
3891
3892         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3893         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3894         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3895         return 0;
3896 }
3897
3898 /* inject a igb flex filter to HW */
3899 static inline void
3900 igb_inject_flex_filter(struct rte_eth_dev *dev,
3901                            struct e1000_flex_filter *filter)
3902 {
3903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         uint32_t wufc, queueing;
3905         uint32_t reg_off;
3906         uint8_t i, j = 0;
3907
3908         wufc = E1000_READ_REG(hw, E1000_WUFC);
3909         if (filter->index < E1000_MAX_FHFT)
3910                 reg_off = E1000_FHFT(filter->index);
3911         else
3912                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3913
3914         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3915                         (E1000_WUFC_FLX0 << filter->index));
3916         queueing = filter->filter_info.len |
3917                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3918                 (filter->filter_info.priority <<
3919                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3920         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3921                         queueing);
3922
3923         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3924                 E1000_WRITE_REG(hw, reg_off,
3925                                 filter->filter_info.dwords[j]);
3926                 reg_off += sizeof(uint32_t);
3927                 E1000_WRITE_REG(hw, reg_off,
3928                                 filter->filter_info.dwords[++j]);
3929                 reg_off += sizeof(uint32_t);
3930                 E1000_WRITE_REG(hw, reg_off,
3931                         (uint32_t)filter->filter_info.mask[i]);
3932                 reg_off += sizeof(uint32_t) * 2;
3933                 ++j;
3934         }
3935 }
3936
3937 static inline struct e1000_flex_filter *
3938 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3939                         struct e1000_flex_filter_info *key)
3940 {
3941         struct e1000_flex_filter *it;
3942
3943         TAILQ_FOREACH(it, filter_list, entries) {
3944                 if (memcmp(key, &it->filter_info,
3945                         sizeof(struct e1000_flex_filter_info)) == 0)
3946                         return it;
3947         }
3948
3949         return NULL;
3950 }
3951
3952 /* remove a flex byte filter
3953  * @param
3954  * dev: Pointer to struct rte_eth_dev.
3955  * filter: the pointer of the filter will be removed.
3956  */
3957 static void
3958 igb_remove_flex_filter(struct rte_eth_dev *dev,
3959                         struct e1000_flex_filter *filter)
3960 {
3961         struct e1000_filter_info *filter_info =
3962                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3963         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964         uint32_t wufc, i;
3965         uint32_t reg_off;
3966
3967         wufc = E1000_READ_REG(hw, E1000_WUFC);
3968         if (filter->index < E1000_MAX_FHFT)
3969                 reg_off = E1000_FHFT(filter->index);
3970         else
3971                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3972
3973         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3974                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3975
3976         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3977                 (~(E1000_WUFC_FLX0 << filter->index)));
3978
3979         filter_info->flex_mask &= ~(1 << filter->index);
3980         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3981         rte_free(filter);
3982 }
3983
3984 int
3985 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3986                         struct rte_eth_flex_filter *filter,
3987                         bool add)
3988 {
3989         struct e1000_filter_info *filter_info =
3990                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3991         struct e1000_flex_filter *flex_filter, *it;
3992         uint32_t mask;
3993         uint8_t shift, i;
3994
3995         flex_filter = rte_zmalloc("e1000_flex_filter",
3996                         sizeof(struct e1000_flex_filter), 0);
3997         if (flex_filter == NULL)
3998                 return -ENOMEM;
3999
4000         flex_filter->filter_info.len = filter->len;
4001         flex_filter->filter_info.priority = filter->priority;
4002         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4003         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4004                 mask = 0;
4005                 /* reverse bits in flex filter's mask*/
4006                 for (shift = 0; shift < CHAR_BIT; shift++) {
4007                         if (filter->mask[i] & (0x01 << shift))
4008                                 mask |= (0x80 >> shift);
4009                 }
4010                 flex_filter->filter_info.mask[i] = mask;
4011         }
4012
4013         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4014                                 &flex_filter->filter_info);
4015         if (it == NULL && !add) {
4016                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4017                 rte_free(flex_filter);
4018                 return -ENOENT;
4019         }
4020         if (it != NULL && add) {
4021                 PMD_DRV_LOG(ERR, "filter exists.");
4022                 rte_free(flex_filter);
4023                 return -EEXIST;
4024         }
4025
4026         if (add) {
4027                 flex_filter->queue = filter->queue;
4028                 /*
4029                  * look for an unused flex filter index
4030                  * and insert the filter into the list.
4031                  */
4032                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4033                         if (!(filter_info->flex_mask & (1 << i))) {
4034                                 filter_info->flex_mask |= 1 << i;
4035                                 flex_filter->index = i;
4036                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4037                                         flex_filter,
4038                                         entries);
4039                                 break;
4040                         }
4041                 }
4042                 if (i >= E1000_MAX_FLEX_FILTERS) {
4043                         PMD_DRV_LOG(ERR, "flex filters are full.");
4044                         rte_free(flex_filter);
4045                         return -ENOSYS;
4046                 }
4047
4048                 igb_inject_flex_filter(dev, flex_filter);
4049
4050         } else {
4051                 igb_remove_flex_filter(dev, it);
4052                 rte_free(flex_filter);
4053         }
4054
4055         return 0;
4056 }
4057
4058 static int
4059 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4060                         struct rte_eth_flex_filter *filter)
4061 {
4062         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         struct e1000_filter_info *filter_info =
4064                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4065         struct e1000_flex_filter flex_filter, *it;
4066         uint32_t wufc, queueing, wufc_en = 0;
4067
4068         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4069         flex_filter.filter_info.len = filter->len;
4070         flex_filter.filter_info.priority = filter->priority;
4071         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4072         memcpy(flex_filter.filter_info.mask, filter->mask,
4073                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4074
4075         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4076                                 &flex_filter.filter_info);
4077         if (it == NULL) {
4078                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4079                 return -ENOENT;
4080         }
4081
4082         wufc = E1000_READ_REG(hw, E1000_WUFC);
4083         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4084
4085         if ((wufc & wufc_en) == wufc_en) {
4086                 uint32_t reg_off = 0;
4087                 if (it->index < E1000_MAX_FHFT)
4088                         reg_off = E1000_FHFT(it->index);
4089                 else
4090                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4091
4092                 queueing = E1000_READ_REG(hw,
4093                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4094                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4095                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4096                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4097                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4098                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4099                 return 0;
4100         }
4101         return -ENOENT;
4102 }
4103
4104 static int
4105 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4106                         enum rte_filter_op filter_op,
4107                         void *arg)
4108 {
4109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4110         struct rte_eth_flex_filter *filter;
4111         int ret = 0;
4112
4113         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4114
4115         if (filter_op == RTE_ETH_FILTER_NOP)
4116                 return ret;
4117
4118         if (arg == NULL) {
4119                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4120                             filter_op);
4121                 return -EINVAL;
4122         }
4123
4124         filter = (struct rte_eth_flex_filter *)arg;
4125         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4126             || filter->len % sizeof(uint64_t) != 0) {
4127                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4128                 return -EINVAL;
4129         }
4130         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4131                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4132                 return -EINVAL;
4133         }
4134
4135         switch (filter_op) {
4136         case RTE_ETH_FILTER_ADD:
4137                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4138                 break;
4139         case RTE_ETH_FILTER_DELETE:
4140                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4141                 break;
4142         case RTE_ETH_FILTER_GET:
4143                 ret = eth_igb_get_flex_filter(dev, filter);
4144                 break;
4145         default:
4146                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4147                 ret = -EINVAL;
4148                 break;
4149         }
4150
4151         return ret;
4152 }
4153
4154 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4155 static inline int
4156 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4157                         struct e1000_5tuple_filter_info *filter_info)
4158 {
4159         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4160                 return -EINVAL;
4161         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4162                 return -EINVAL;  /* filter index is out of range. */
4163         if (filter->tcp_flags > TCP_FLAG_ALL)
4164                 return -EINVAL;  /* flags is invalid. */
4165
4166         switch (filter->dst_ip_mask) {
4167         case UINT32_MAX:
4168                 filter_info->dst_ip_mask = 0;
4169                 filter_info->dst_ip = filter->dst_ip;
4170                 break;
4171         case 0:
4172                 filter_info->dst_ip_mask = 1;
4173                 break;
4174         default:
4175                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4176                 return -EINVAL;
4177         }
4178
4179         switch (filter->src_ip_mask) {
4180         case UINT32_MAX:
4181                 filter_info->src_ip_mask = 0;
4182                 filter_info->src_ip = filter->src_ip;
4183                 break;
4184         case 0:
4185                 filter_info->src_ip_mask = 1;
4186                 break;
4187         default:
4188                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4189                 return -EINVAL;
4190         }
4191
4192         switch (filter->dst_port_mask) {
4193         case UINT16_MAX:
4194                 filter_info->dst_port_mask = 0;
4195                 filter_info->dst_port = filter->dst_port;
4196                 break;
4197         case 0:
4198                 filter_info->dst_port_mask = 1;
4199                 break;
4200         default:
4201                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4202                 return -EINVAL;
4203         }
4204
4205         switch (filter->src_port_mask) {
4206         case UINT16_MAX:
4207                 filter_info->src_port_mask = 0;
4208                 filter_info->src_port = filter->src_port;
4209                 break;
4210         case 0:
4211                 filter_info->src_port_mask = 1;
4212                 break;
4213         default:
4214                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4215                 return -EINVAL;
4216         }
4217
4218         switch (filter->proto_mask) {
4219         case UINT8_MAX:
4220                 filter_info->proto_mask = 0;
4221                 filter_info->proto = filter->proto;
4222                 break;
4223         case 0:
4224                 filter_info->proto_mask = 1;
4225                 break;
4226         default:
4227                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4228                 return -EINVAL;
4229         }
4230
4231         filter_info->priority = (uint8_t)filter->priority;
4232         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4233                 filter_info->tcp_flags = filter->tcp_flags;
4234         else
4235                 filter_info->tcp_flags = 0;
4236
4237         return 0;
4238 }
4239
4240 static inline struct e1000_5tuple_filter *
4241 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4242                         struct e1000_5tuple_filter_info *key)
4243 {
4244         struct e1000_5tuple_filter *it;
4245
4246         TAILQ_FOREACH(it, filter_list, entries) {
4247                 if (memcmp(key, &it->filter_info,
4248                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4249                         return it;
4250                 }
4251         }
4252         return NULL;
4253 }
4254
4255 /* inject a igb 5-tuple filter to HW */
4256 static inline void
4257 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4258                            struct e1000_5tuple_filter *filter)
4259 {
4260         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4262         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4263         uint8_t i;
4264
4265         i = filter->index;
4266         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4267         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4268                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4269         if (filter->filter_info.dst_ip_mask == 0)
4270                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4271         if (filter->filter_info.src_port_mask == 0)
4272                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4273         if (filter->filter_info.proto_mask == 0)
4274                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4275         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4276                 E1000_FTQF_QUEUE_MASK;
4277         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4278         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4279         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4280         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4281
4282         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4283         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4284
4285         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4286         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4287                 imir |= E1000_IMIR_PORT_BP;
4288         else
4289                 imir &= ~E1000_IMIR_PORT_BP;
4290         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4291
4292         /* tcp flags bits setting. */
4293         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4294                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4295                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4296                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4297                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4298                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4299                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4300                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4301                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4302                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4303                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4304                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4305                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4306         } else {
4307                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4308         }
4309         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4310         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4311 }
4312
4313 /*
4314  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4315  *
4316  * @param
4317  * dev: Pointer to struct rte_eth_dev.
4318  * ntuple_filter: ponter to the filter that will be added.
4319  *
4320  * @return
4321  *    - On success, zero.
4322  *    - On failure, a negative value.
4323  */
4324 static int
4325 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4326                         struct rte_eth_ntuple_filter *ntuple_filter)
4327 {
4328         struct e1000_filter_info *filter_info =
4329                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4330         struct e1000_5tuple_filter *filter;
4331         uint8_t i;
4332         int ret;
4333
4334         filter = rte_zmalloc("e1000_5tuple_filter",
4335                         sizeof(struct e1000_5tuple_filter), 0);
4336         if (filter == NULL)
4337                 return -ENOMEM;
4338
4339         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4340                                             &filter->filter_info);
4341         if (ret < 0) {
4342                 rte_free(filter);
4343                 return ret;
4344         }
4345
4346         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4347                                          &filter->filter_info) != NULL) {
4348                 PMD_DRV_LOG(ERR, "filter exists.");
4349                 rte_free(filter);
4350                 return -EEXIST;
4351         }
4352         filter->queue = ntuple_filter->queue;
4353
4354         /*
4355          * look for an unused 5tuple filter index,
4356          * and insert the filter to list.
4357          */
4358         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4359                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4360                         filter_info->fivetuple_mask |= 1 << i;
4361                         filter->index = i;
4362                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4363                                           filter,
4364                                           entries);
4365                         break;
4366                 }
4367         }
4368         if (i >= E1000_MAX_FTQF_FILTERS) {
4369                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4370                 rte_free(filter);
4371                 return -ENOSYS;
4372         }
4373
4374         igb_inject_5tuple_filter_82576(dev, filter);
4375         return 0;
4376 }
4377
4378 /*
4379  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4380  *
4381  * @param
4382  * dev: Pointer to struct rte_eth_dev.
4383  * ntuple_filter: ponter to the filter that will be removed.
4384  *
4385  * @return
4386  *    - On success, zero.
4387  *    - On failure, a negative value.
4388  */
4389 static int
4390 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4391                                 struct rte_eth_ntuple_filter *ntuple_filter)
4392 {
4393         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394         struct e1000_filter_info *filter_info =
4395                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4396         struct e1000_5tuple_filter_info filter_5tuple;
4397         struct e1000_5tuple_filter *filter;
4398         int ret;
4399
4400         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4401         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4402                                             &filter_5tuple);
4403         if (ret < 0)
4404                 return ret;
4405
4406         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4407                                          &filter_5tuple);
4408         if (filter == NULL) {
4409                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4410                 return -ENOENT;
4411         }
4412
4413         filter_info->fivetuple_mask &= ~(1 << filter->index);
4414         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4415         rte_free(filter);
4416
4417         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4418                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4419         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4420         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4421         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4422         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4423         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4424         return 0;
4425 }
4426
4427 static int
4428 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4429 {
4430         uint32_t rctl;
4431         struct e1000_hw *hw;
4432         struct rte_eth_dev_info dev_info;
4433         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4434                                      VLAN_TAG_SIZE);
4435
4436         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4437
4438 #ifdef RTE_LIBRTE_82571_SUPPORT
4439         /* XXX: not bigger than max_rx_pktlen */
4440         if (hw->mac.type == e1000_82571)
4441                 return -ENOTSUP;
4442 #endif
4443         eth_igb_infos_get(dev, &dev_info);
4444
4445         /* check that mtu is within the allowed range */
4446         if ((mtu < ETHER_MIN_MTU) ||
4447             (frame_size > dev_info.max_rx_pktlen))
4448                 return -EINVAL;
4449
4450         /* refuse mtu that requires the support of scattered packets when this
4451          * feature has not been enabled before. */
4452         if (!dev->data->scattered_rx &&
4453             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4454                 return -EINVAL;
4455
4456         rctl = E1000_READ_REG(hw, E1000_RCTL);
4457
4458         /* switch to jumbo mode if needed */
4459         if (frame_size > ETHER_MAX_LEN) {
4460                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4461                 rctl |= E1000_RCTL_LPE;
4462         } else {
4463                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4464                 rctl &= ~E1000_RCTL_LPE;
4465         }
4466         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4467
4468         /* update max frame size */
4469         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4470
4471         E1000_WRITE_REG(hw, E1000_RLPML,
4472                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4473
4474         return 0;
4475 }
4476
4477 /*
4478  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4479  *
4480  * @param
4481  * dev: Pointer to struct rte_eth_dev.
4482  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4483  * add: if true, add filter, if false, remove filter
4484  *
4485  * @return
4486  *    - On success, zero.
4487  *    - On failure, a negative value.
4488  */
4489 int
4490 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4491                         struct rte_eth_ntuple_filter *ntuple_filter,
4492                         bool add)
4493 {
4494         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4495         int ret;
4496
4497         switch (ntuple_filter->flags) {
4498         case RTE_5TUPLE_FLAGS:
4499         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4500                 if (hw->mac.type != e1000_82576)
4501                         return -ENOTSUP;
4502                 if (add)
4503                         ret = igb_add_5tuple_filter_82576(dev,
4504                                                           ntuple_filter);
4505                 else
4506                         ret = igb_remove_5tuple_filter_82576(dev,
4507                                                              ntuple_filter);
4508                 break;
4509         case RTE_2TUPLE_FLAGS:
4510         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4511                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4512                         hw->mac.type != e1000_i210 &&
4513                         hw->mac.type != e1000_i211)
4514                         return -ENOTSUP;
4515                 if (add)
4516                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4517                 else
4518                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4519                 break;
4520         default:
4521                 ret = -EINVAL;
4522                 break;
4523         }
4524
4525         return ret;
4526 }
4527
4528 /*
4529  * igb_get_ntuple_filter - get a ntuple filter
4530  *
4531  * @param
4532  * dev: Pointer to struct rte_eth_dev.
4533  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4534  *
4535  * @return
4536  *    - On success, zero.
4537  *    - On failure, a negative value.
4538  */
4539 static int
4540 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4541                         struct rte_eth_ntuple_filter *ntuple_filter)
4542 {
4543         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544         struct e1000_filter_info *filter_info =
4545                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4546         struct e1000_5tuple_filter_info filter_5tuple;
4547         struct e1000_2tuple_filter_info filter_2tuple;
4548         struct e1000_5tuple_filter *p_5tuple_filter;
4549         struct e1000_2tuple_filter *p_2tuple_filter;
4550         int ret;
4551
4552         switch (ntuple_filter->flags) {
4553         case RTE_5TUPLE_FLAGS:
4554         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4555                 if (hw->mac.type != e1000_82576)
4556                         return -ENOTSUP;
4557                 memset(&filter_5tuple,
4558                         0,
4559                         sizeof(struct e1000_5tuple_filter_info));
4560                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4561                                                     &filter_5tuple);
4562                 if (ret < 0)
4563                         return ret;
4564                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4565                                         &filter_info->fivetuple_list,
4566                                         &filter_5tuple);
4567                 if (p_5tuple_filter == NULL) {
4568                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4569                         return -ENOENT;
4570                 }
4571                 ntuple_filter->queue = p_5tuple_filter->queue;
4572                 break;
4573         case RTE_2TUPLE_FLAGS:
4574         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4575                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4576                         return -ENOTSUP;
4577                 memset(&filter_2tuple,
4578                         0,
4579                         sizeof(struct e1000_2tuple_filter_info));
4580                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4581                 if (ret < 0)
4582                         return ret;
4583                 p_2tuple_filter = igb_2tuple_filter_lookup(
4584                                         &filter_info->twotuple_list,
4585                                         &filter_2tuple);
4586                 if (p_2tuple_filter == NULL) {
4587                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4588                         return -ENOENT;
4589                 }
4590                 ntuple_filter->queue = p_2tuple_filter->queue;
4591                 break;
4592         default:
4593                 ret = -EINVAL;
4594                 break;
4595         }
4596
4597         return 0;
4598 }
4599
4600 /*
4601  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4602  * @dev: pointer to rte_eth_dev structure
4603  * @filter_op:operation will be taken.
4604  * @arg: a pointer to specific structure corresponding to the filter_op
4605  */
4606 static int
4607 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4608                                 enum rte_filter_op filter_op,
4609                                 void *arg)
4610 {
4611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         int ret;
4613
4614         MAC_TYPE_FILTER_SUP(hw->mac.type);
4615
4616         if (filter_op == RTE_ETH_FILTER_NOP)
4617                 return 0;
4618
4619         if (arg == NULL) {
4620                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4621                             filter_op);
4622                 return -EINVAL;
4623         }
4624
4625         switch (filter_op) {
4626         case RTE_ETH_FILTER_ADD:
4627                 ret = igb_add_del_ntuple_filter(dev,
4628                         (struct rte_eth_ntuple_filter *)arg,
4629                         TRUE);
4630                 break;
4631         case RTE_ETH_FILTER_DELETE:
4632                 ret = igb_add_del_ntuple_filter(dev,
4633                         (struct rte_eth_ntuple_filter *)arg,
4634                         FALSE);
4635                 break;
4636         case RTE_ETH_FILTER_GET:
4637                 ret = igb_get_ntuple_filter(dev,
4638                         (struct rte_eth_ntuple_filter *)arg);
4639                 break;
4640         default:
4641                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4642                 ret = -EINVAL;
4643                 break;
4644         }
4645         return ret;
4646 }
4647
4648 static inline int
4649 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4650                         uint16_t ethertype)
4651 {
4652         int i;
4653
4654         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4655                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4656                     (filter_info->ethertype_mask & (1 << i)))
4657                         return i;
4658         }
4659         return -1;
4660 }
4661
4662 static inline int
4663 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4664                         uint16_t ethertype, uint32_t etqf)
4665 {
4666         int i;
4667
4668         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4669                 if (!(filter_info->ethertype_mask & (1 << i))) {
4670                         filter_info->ethertype_mask |= 1 << i;
4671                         filter_info->ethertype_filters[i].ethertype = ethertype;
4672                         filter_info->ethertype_filters[i].etqf = etqf;
4673                         return i;
4674                 }
4675         }
4676         return -1;
4677 }
4678
4679 static int
4680 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4681                         uint8_t idx)
4682 {
4683         if (idx >= E1000_MAX_ETQF_FILTERS)
4684                 return -1;
4685         filter_info->ethertype_mask &= ~(1 << idx);
4686         filter_info->ethertype_filters[idx].ethertype = 0;
4687         filter_info->ethertype_filters[idx].etqf = 0;
4688         return idx;
4689 }
4690
4691
4692 int
4693 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4694                         struct rte_eth_ethertype_filter *filter,
4695                         bool add)
4696 {
4697         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct e1000_filter_info *filter_info =
4699                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4700         uint32_t etqf = 0;
4701         int ret;
4702
4703         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4704                 filter->ether_type == ETHER_TYPE_IPv6) {
4705                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4706                         " ethertype filter.", filter->ether_type);
4707                 return -EINVAL;
4708         }
4709
4710         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4711                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4712                 return -EINVAL;
4713         }
4714         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4715                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4716                 return -EINVAL;
4717         }
4718
4719         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4720         if (ret >= 0 && add) {
4721                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4722                             filter->ether_type);
4723                 return -EEXIST;
4724         }
4725         if (ret < 0 && !add) {
4726                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4727                             filter->ether_type);
4728                 return -ENOENT;
4729         }
4730
4731         if (add) {
4732                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4733                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4734                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4735                 ret = igb_ethertype_filter_insert(filter_info,
4736                                 filter->ether_type, etqf);
4737                 if (ret < 0) {
4738                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4739                         return -ENOSYS;
4740                 }
4741         } else {
4742                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4743                 if (ret < 0)
4744                         return -ENOSYS;
4745         }
4746         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4747         E1000_WRITE_FLUSH(hw);
4748
4749         return 0;
4750 }
4751
4752 static int
4753 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4754                         struct rte_eth_ethertype_filter *filter)
4755 {
4756         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4757         struct e1000_filter_info *filter_info =
4758                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4759         uint32_t etqf;
4760         int ret;
4761
4762         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4763         if (ret < 0) {
4764                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4765                             filter->ether_type);
4766                 return -ENOENT;
4767         }
4768
4769         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4770         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4771                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4772                 filter->flags = 0;
4773                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4774                                 E1000_ETQF_QUEUE_SHIFT;
4775                 return 0;
4776         }
4777
4778         return -ENOENT;
4779 }
4780
4781 /*
4782  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4783  * @dev: pointer to rte_eth_dev structure
4784  * @filter_op:operation will be taken.
4785  * @arg: a pointer to specific structure corresponding to the filter_op
4786  */
4787 static int
4788 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4789                                 enum rte_filter_op filter_op,
4790                                 void *arg)
4791 {
4792         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         int ret;
4794
4795         MAC_TYPE_FILTER_SUP(hw->mac.type);
4796
4797         if (filter_op == RTE_ETH_FILTER_NOP)
4798                 return 0;
4799
4800         if (arg == NULL) {
4801                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4802                             filter_op);
4803                 return -EINVAL;
4804         }
4805
4806         switch (filter_op) {
4807         case RTE_ETH_FILTER_ADD:
4808                 ret = igb_add_del_ethertype_filter(dev,
4809                         (struct rte_eth_ethertype_filter *)arg,
4810                         TRUE);
4811                 break;
4812         case RTE_ETH_FILTER_DELETE:
4813                 ret = igb_add_del_ethertype_filter(dev,
4814                         (struct rte_eth_ethertype_filter *)arg,
4815                         FALSE);
4816                 break;
4817         case RTE_ETH_FILTER_GET:
4818                 ret = igb_get_ethertype_filter(dev,
4819                         (struct rte_eth_ethertype_filter *)arg);
4820                 break;
4821         default:
4822                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4823                 ret = -EINVAL;
4824                 break;
4825         }
4826         return ret;
4827 }
4828
4829 static int
4830 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4831                      enum rte_filter_type filter_type,
4832                      enum rte_filter_op filter_op,
4833                      void *arg)
4834 {
4835         int ret = 0;
4836
4837         switch (filter_type) {
4838         case RTE_ETH_FILTER_NTUPLE:
4839                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4840                 break;
4841         case RTE_ETH_FILTER_ETHERTYPE:
4842                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4843                 break;
4844         case RTE_ETH_FILTER_SYN:
4845                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4846                 break;
4847         case RTE_ETH_FILTER_FLEXIBLE:
4848                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4849                 break;
4850         case RTE_ETH_FILTER_GENERIC:
4851                 if (filter_op != RTE_ETH_FILTER_GET)
4852                         return -EINVAL;
4853                 *(const void **)arg = &igb_flow_ops;
4854                 break;
4855         default:
4856                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4857                                                         filter_type);
4858                 break;
4859         }
4860
4861         return ret;
4862 }
4863
4864 static int
4865 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4866                          struct ether_addr *mc_addr_set,
4867                          uint32_t nb_mc_addr)
4868 {
4869         struct e1000_hw *hw;
4870
4871         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4872         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4873         return 0;
4874 }
4875
4876 static uint64_t
4877 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4878 {
4879         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880         uint64_t systime_cycles;
4881
4882         switch (hw->mac.type) {
4883         case e1000_i210:
4884         case e1000_i211:
4885                 /*
4886                  * Need to read System Time Residue Register to be able
4887                  * to read the other two registers.
4888                  */
4889                 E1000_READ_REG(hw, E1000_SYSTIMR);
4890                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4891                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4892                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4893                                 * NSEC_PER_SEC;
4894                 break;
4895         case e1000_82580:
4896         case e1000_i350:
4897         case e1000_i354:
4898                 /*
4899                  * Need to read System Time Residue Register to be able
4900                  * to read the other two registers.
4901                  */
4902                 E1000_READ_REG(hw, E1000_SYSTIMR);
4903                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4904                 /* Only the 8 LSB are valid. */
4905                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4906                                 & 0xff) << 32;
4907                 break;
4908         default:
4909                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4910                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4911                                 << 32;
4912                 break;
4913         }
4914
4915         return systime_cycles;
4916 }
4917
4918 static uint64_t
4919 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4920 {
4921         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922         uint64_t rx_tstamp_cycles;
4923
4924         switch (hw->mac.type) {
4925         case e1000_i210:
4926         case e1000_i211:
4927                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4928                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4929                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4930                                 * NSEC_PER_SEC;
4931                 break;
4932         case e1000_82580:
4933         case e1000_i350:
4934         case e1000_i354:
4935                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4936                 /* Only the 8 LSB are valid. */
4937                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4938                                 & 0xff) << 32;
4939                 break;
4940         default:
4941                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4942                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4943                                 << 32;
4944                 break;
4945         }
4946
4947         return rx_tstamp_cycles;
4948 }
4949
4950 static uint64_t
4951 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4952 {
4953         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         uint64_t tx_tstamp_cycles;
4955
4956         switch (hw->mac.type) {
4957         case e1000_i210:
4958         case e1000_i211:
4959                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4960                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4961                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4962                                 * NSEC_PER_SEC;
4963                 break;
4964         case e1000_82580:
4965         case e1000_i350:
4966         case e1000_i354:
4967                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4968                 /* Only the 8 LSB are valid. */
4969                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4970                                 & 0xff) << 32;
4971                 break;
4972         default:
4973                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4974                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4975                                 << 32;
4976                 break;
4977         }
4978
4979         return tx_tstamp_cycles;
4980 }
4981
4982 static void
4983 igb_start_timecounters(struct rte_eth_dev *dev)
4984 {
4985         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         struct e1000_adapter *adapter =
4987                 (struct e1000_adapter *)dev->data->dev_private;
4988         uint32_t incval = 1;
4989         uint32_t shift = 0;
4990         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4991
4992         switch (hw->mac.type) {
4993         case e1000_82580:
4994         case e1000_i350:
4995         case e1000_i354:
4996                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4997                 mask = (1ULL << 40) - 1;
4998                 /* fall-through */
4999         case e1000_i210:
5000         case e1000_i211:
5001                 /*
5002                  * Start incrementing the register
5003                  * used to timestamp PTP packets.
5004                  */
5005                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5006                 break;
5007         case e1000_82576:
5008                 incval = E1000_INCVALUE_82576;
5009                 shift = IGB_82576_TSYNC_SHIFT;
5010                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5011                                 E1000_INCPERIOD_82576 | incval);
5012                 break;
5013         default:
5014                 /* Not supported */
5015                 return;
5016         }
5017
5018         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5019         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5020         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5021
5022         adapter->systime_tc.cc_mask = mask;
5023         adapter->systime_tc.cc_shift = shift;
5024         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5025
5026         adapter->rx_tstamp_tc.cc_mask = mask;
5027         adapter->rx_tstamp_tc.cc_shift = shift;
5028         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5029
5030         adapter->tx_tstamp_tc.cc_mask = mask;
5031         adapter->tx_tstamp_tc.cc_shift = shift;
5032         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5033 }
5034
5035 static int
5036 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5037 {
5038         struct e1000_adapter *adapter =
5039                         (struct e1000_adapter *)dev->data->dev_private;
5040
5041         adapter->systime_tc.nsec += delta;
5042         adapter->rx_tstamp_tc.nsec += delta;
5043         adapter->tx_tstamp_tc.nsec += delta;
5044
5045         return 0;
5046 }
5047
5048 static int
5049 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5050 {
5051         uint64_t ns;
5052         struct e1000_adapter *adapter =
5053                         (struct e1000_adapter *)dev->data->dev_private;
5054
5055         ns = rte_timespec_to_ns(ts);
5056
5057         /* Set the timecounters to a new value. */
5058         adapter->systime_tc.nsec = ns;
5059         adapter->rx_tstamp_tc.nsec = ns;
5060         adapter->tx_tstamp_tc.nsec = ns;
5061
5062         return 0;
5063 }
5064
5065 static int
5066 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5067 {
5068         uint64_t ns, systime_cycles;
5069         struct e1000_adapter *adapter =
5070                         (struct e1000_adapter *)dev->data->dev_private;
5071
5072         systime_cycles = igb_read_systime_cyclecounter(dev);
5073         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5074         *ts = rte_ns_to_timespec(ns);
5075
5076         return 0;
5077 }
5078
5079 static int
5080 igb_timesync_enable(struct rte_eth_dev *dev)
5081 {
5082         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083         uint32_t tsync_ctl;
5084         uint32_t tsauxc;
5085
5086         /* Stop the timesync system time. */
5087         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5088         /* Reset the timesync system time value. */
5089         switch (hw->mac.type) {
5090         case e1000_82580:
5091         case e1000_i350:
5092         case e1000_i354:
5093         case e1000_i210:
5094         case e1000_i211:
5095                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5096                 /* fall-through */
5097         case e1000_82576:
5098                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5099                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5100                 break;
5101         default:
5102                 /* Not supported. */
5103                 return -ENOTSUP;
5104         }
5105
5106         /* Enable system time for it isn't on by default. */
5107         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5108         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5109         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5110
5111         igb_start_timecounters(dev);
5112
5113         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5114         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5115                         (ETHER_TYPE_1588 |
5116                          E1000_ETQF_FILTER_ENABLE |
5117                          E1000_ETQF_1588));
5118
5119         /* Enable timestamping of received PTP packets. */
5120         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5121         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5122         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5123
5124         /* Enable Timestamping of transmitted PTP packets. */
5125         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5126         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5127         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5128
5129         return 0;
5130 }
5131
5132 static int
5133 igb_timesync_disable(struct rte_eth_dev *dev)
5134 {
5135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136         uint32_t tsync_ctl;
5137
5138         /* Disable timestamping of transmitted PTP packets. */
5139         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5140         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5141         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5142
5143         /* Disable timestamping of received PTP packets. */
5144         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5145         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5146         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5147
5148         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5149         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5150
5151         /* Stop incrementating the System Time registers. */
5152         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5153
5154         return 0;
5155 }
5156
5157 static int
5158 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5159                                struct timespec *timestamp,
5160                                uint32_t flags __rte_unused)
5161 {
5162         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5163         struct e1000_adapter *adapter =
5164                         (struct e1000_adapter *)dev->data->dev_private;
5165         uint32_t tsync_rxctl;
5166         uint64_t rx_tstamp_cycles;
5167         uint64_t ns;
5168
5169         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5170         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5171                 return -EINVAL;
5172
5173         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5174         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5175         *timestamp = rte_ns_to_timespec(ns);
5176
5177         return  0;
5178 }
5179
5180 static int
5181 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5182                                struct timespec *timestamp)
5183 {
5184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185         struct e1000_adapter *adapter =
5186                         (struct e1000_adapter *)dev->data->dev_private;
5187         uint32_t tsync_txctl;
5188         uint64_t tx_tstamp_cycles;
5189         uint64_t ns;
5190
5191         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5192         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5193                 return -EINVAL;
5194
5195         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5196         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5197         *timestamp = rte_ns_to_timespec(ns);
5198
5199         return  0;
5200 }
5201
5202 static int
5203 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5204 {
5205         int count = 0;
5206         int g_ind = 0;
5207         const struct reg_info *reg_group;
5208
5209         while ((reg_group = igb_regs[g_ind++]))
5210                 count += igb_reg_group_count(reg_group);
5211
5212         return count;
5213 }
5214
5215 static int
5216 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5217 {
5218         int count = 0;
5219         int g_ind = 0;
5220         const struct reg_info *reg_group;
5221
5222         while ((reg_group = igbvf_regs[g_ind++]))
5223                 count += igb_reg_group_count(reg_group);
5224
5225         return count;
5226 }
5227
5228 static int
5229 eth_igb_get_regs(struct rte_eth_dev *dev,
5230         struct rte_dev_reg_info *regs)
5231 {
5232         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233         uint32_t *data = regs->data;
5234         int g_ind = 0;
5235         int count = 0;
5236         const struct reg_info *reg_group;
5237
5238         if (data == NULL) {
5239                 regs->length = eth_igb_get_reg_length(dev);
5240                 regs->width = sizeof(uint32_t);
5241                 return 0;
5242         }
5243
5244         /* Support only full register dump */
5245         if ((regs->length == 0) ||
5246             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5247                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5248                         hw->device_id;
5249                 while ((reg_group = igb_regs[g_ind++]))
5250                         count += igb_read_regs_group(dev, &data[count],
5251                                                         reg_group);
5252                 return 0;
5253         }
5254
5255         return -ENOTSUP;
5256 }
5257
5258 static int
5259 igbvf_get_regs(struct rte_eth_dev *dev,
5260         struct rte_dev_reg_info *regs)
5261 {
5262         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5263         uint32_t *data = regs->data;
5264         int g_ind = 0;
5265         int count = 0;
5266         const struct reg_info *reg_group;
5267
5268         if (data == NULL) {
5269                 regs->length = igbvf_get_reg_length(dev);
5270                 regs->width = sizeof(uint32_t);
5271                 return 0;
5272         }
5273
5274         /* Support only full register dump */
5275         if ((regs->length == 0) ||
5276             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5277                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5278                         hw->device_id;
5279                 while ((reg_group = igbvf_regs[g_ind++]))
5280                         count += igb_read_regs_group(dev, &data[count],
5281                                                         reg_group);
5282                 return 0;
5283         }
5284
5285         return -ENOTSUP;
5286 }
5287
5288 static int
5289 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5290 {
5291         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292
5293         /* Return unit is byte count */
5294         return hw->nvm.word_size * 2;
5295 }
5296
5297 static int
5298 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5299         struct rte_dev_eeprom_info *in_eeprom)
5300 {
5301         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5302         struct e1000_nvm_info *nvm = &hw->nvm;
5303         uint16_t *data = in_eeprom->data;
5304         int first, length;
5305
5306         first = in_eeprom->offset >> 1;
5307         length = in_eeprom->length >> 1;
5308         if ((first >= hw->nvm.word_size) ||
5309             ((first + length) >= hw->nvm.word_size))
5310                 return -EINVAL;
5311
5312         in_eeprom->magic = hw->vendor_id |
5313                 ((uint32_t)hw->device_id << 16);
5314
5315         if ((nvm->ops.read) == NULL)
5316                 return -ENOTSUP;
5317
5318         return nvm->ops.read(hw, first, length, data);
5319 }
5320
5321 static int
5322 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5323         struct rte_dev_eeprom_info *in_eeprom)
5324 {
5325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5326         struct e1000_nvm_info *nvm = &hw->nvm;
5327         uint16_t *data = in_eeprom->data;
5328         int first, length;
5329
5330         first = in_eeprom->offset >> 1;
5331         length = in_eeprom->length >> 1;
5332         if ((first >= hw->nvm.word_size) ||
5333             ((first + length) >= hw->nvm.word_size))
5334                 return -EINVAL;
5335
5336         in_eeprom->magic = (uint32_t)hw->vendor_id |
5337                 ((uint32_t)hw->device_id << 16);
5338
5339         if ((nvm->ops.write) == NULL)
5340                 return -ENOTSUP;
5341         return nvm->ops.write(hw,  first, length, data);
5342 }
5343
5344 static int
5345 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5346 {
5347         struct e1000_hw *hw =
5348                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5349         uint32_t mask = 1 << queue_id;
5350
5351         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5352         E1000_WRITE_FLUSH(hw);
5353
5354         return 0;
5355 }
5356
5357 static int
5358 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5359 {
5360         struct e1000_hw *hw =
5361                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5362         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5363         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5364         uint32_t mask = 1 << queue_id;
5365         uint32_t regval;
5366
5367         regval = E1000_READ_REG(hw, E1000_EIMS);
5368         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5369         E1000_WRITE_FLUSH(hw);
5370
5371         rte_intr_enable(intr_handle);
5372
5373         return 0;
5374 }
5375
5376 static void
5377 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5378                    uint8_t index, uint8_t offset)
5379 {
5380         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5381
5382         /* clear bits */
5383         val &= ~((uint32_t)0xFF << offset);
5384
5385         /* write vector and valid bit */
5386         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5387
5388         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5389 }
5390
5391 static void
5392 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5393                            uint8_t queue, uint8_t msix_vector)
5394 {
5395         uint32_t tmp = 0;
5396
5397         if (hw->mac.type == e1000_82575) {
5398                 if (direction == 0)
5399                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5400                 else if (direction == 1)
5401                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5402                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5403         } else if (hw->mac.type == e1000_82576) {
5404                 if ((direction == 0) || (direction == 1))
5405                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5406                                            ((queue & 0x8) << 1) +
5407                                            8 * direction);
5408         } else if ((hw->mac.type == e1000_82580) ||
5409                         (hw->mac.type == e1000_i350) ||
5410                         (hw->mac.type == e1000_i354) ||
5411                         (hw->mac.type == e1000_i210) ||
5412                         (hw->mac.type == e1000_i211)) {
5413                 if ((direction == 0) || (direction == 1))
5414                         eth_igb_write_ivar(hw, msix_vector,
5415                                            queue >> 1,
5416                                            ((queue & 0x1) << 4) +
5417                                            8 * direction);
5418         }
5419 }
5420
5421 /* Sets up the hardware to generate MSI-X interrupts properly
5422  * @hw
5423  *  board private structure
5424  */
5425 static void
5426 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5427 {
5428         int queue_id;
5429         uint32_t tmpval, regval, intr_mask;
5430         struct e1000_hw *hw =
5431                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5432         uint32_t vec = E1000_MISC_VEC_ID;
5433         uint32_t base = E1000_MISC_VEC_ID;
5434         uint32_t misc_shift = 0;
5435         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5436         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5437
5438         /* won't configure msix register if no mapping is done
5439          * between intr vector and event fd
5440          */
5441         if (!rte_intr_dp_is_en(intr_handle))
5442                 return;
5443
5444         if (rte_intr_allow_others(intr_handle)) {
5445                 vec = base = E1000_RX_VEC_START;
5446                 misc_shift = 1;
5447         }
5448
5449         /* set interrupt vector for other causes */
5450         if (hw->mac.type == e1000_82575) {
5451                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5452                 /* enable MSI-X PBA support */
5453                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5454
5455                 /* Auto-Mask interrupts upon ICR read */
5456                 tmpval |= E1000_CTRL_EXT_EIAME;
5457                 tmpval |= E1000_CTRL_EXT_IRCA;
5458
5459                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5460
5461                 /* enable msix_other interrupt */
5462                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5463                 regval = E1000_READ_REG(hw, E1000_EIAC);
5464                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5465                 regval = E1000_READ_REG(hw, E1000_EIAM);
5466                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5467         } else if ((hw->mac.type == e1000_82576) ||
5468                         (hw->mac.type == e1000_82580) ||
5469                         (hw->mac.type == e1000_i350) ||
5470                         (hw->mac.type == e1000_i354) ||
5471                         (hw->mac.type == e1000_i210) ||
5472                         (hw->mac.type == e1000_i211)) {
5473                 /* turn on MSI-X capability first */
5474                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5475                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5476                                         E1000_GPIE_NSICR);
5477                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5478                         misc_shift;
5479                 regval = E1000_READ_REG(hw, E1000_EIAC);
5480                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5481
5482                 /* enable msix_other interrupt */
5483                 regval = E1000_READ_REG(hw, E1000_EIMS);
5484                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5485                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5486                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5487         }
5488
5489         /* use EIAM to auto-mask when MSI-X interrupt
5490          * is asserted, this saves a register write for every interrupt
5491          */
5492         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5493                 misc_shift;
5494         regval = E1000_READ_REG(hw, E1000_EIAM);
5495         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5496
5497         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5498                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5499                 intr_handle->intr_vec[queue_id] = vec;
5500                 if (vec < base + intr_handle->nb_efd - 1)
5501                         vec++;
5502         }
5503
5504         E1000_WRITE_FLUSH(hw);
5505 }
5506
5507 /* restore n-tuple filter */
5508 static inline void
5509 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5510 {
5511         struct e1000_filter_info *filter_info =
5512                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5513         struct e1000_5tuple_filter *p_5tuple;
5514         struct e1000_2tuple_filter *p_2tuple;
5515
5516         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5517                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5518         }
5519
5520         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5521                 igb_inject_2uple_filter(dev, p_2tuple);
5522         }
5523 }
5524
5525 /* restore SYN filter */
5526 static inline void
5527 igb_syn_filter_restore(struct rte_eth_dev *dev)
5528 {
5529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5530         struct e1000_filter_info *filter_info =
5531                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5532         uint32_t synqf;
5533
5534         synqf = filter_info->syn_info;
5535
5536         if (synqf & E1000_SYN_FILTER_ENABLE) {
5537                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5538                 E1000_WRITE_FLUSH(hw);
5539         }
5540 }
5541
5542 /* restore ethernet type filter */
5543 static inline void
5544 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5545 {
5546         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5547         struct e1000_filter_info *filter_info =
5548                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5549         int i;
5550
5551         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5552                 if (filter_info->ethertype_mask & (1 << i)) {
5553                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5554                                 filter_info->ethertype_filters[i].etqf);
5555                         E1000_WRITE_FLUSH(hw);
5556                 }
5557         }
5558 }
5559
5560 /* restore flex byte filter */
5561 static inline void
5562 igb_flex_filter_restore(struct rte_eth_dev *dev)
5563 {
5564         struct e1000_filter_info *filter_info =
5565                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5566         struct e1000_flex_filter *flex_filter;
5567
5568         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5569                 igb_inject_flex_filter(dev, flex_filter);
5570         }
5571 }
5572
5573 /* restore all types filter */
5574 static int
5575 igb_filter_restore(struct rte_eth_dev *dev)
5576 {
5577         igb_ntuple_filter_restore(dev);
5578         igb_ethertype_filter_restore(dev);
5579         igb_syn_filter_restore(dev);
5580         igb_flex_filter_restore(dev);
5581
5582         return 0;
5583 }
5584
5585 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5586 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5587 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5588 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5589 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5590 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");