drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 124                               struct rte_eth_dev_info *dev_info);
 125 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 126 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_dev_info *dev_info);
 128 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 133 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 134 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 135 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 136 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 137                                                         void *param);
 138 static int  igb_hardware_init(struct e1000_hw *hw);
 139 static void igb_hw_control_acquire(struct e1000_hw *hw);
 140 static void igb_hw_control_release(struct e1000_hw *hw);
 141 static void igb_init_manageability(struct e1000_hw *hw);
 142 static void igb_release_manageability(struct e1000_hw *hw);
 143
 144 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 145
 146 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 147                 uint16_t vlan_id, int on);
 148 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 149                                  enum rte_vlan_type vlan_type,
 150                                  uint16_t tpid_id);
 151 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 152
 153 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 159
 160 static int eth_igb_led_on(struct rte_eth_dev *dev);
 161 static int eth_igb_led_off(struct rte_eth_dev *dev);
 162
 163 static void igb_intr_disable(struct e1000_hw *hw);
 164 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 165 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *mac_addr,
 167                 uint32_t index, uint32_t pool);
 168 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 169 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 170                 struct ether_addr *addr);
 171
 172 static void igbvf_intr_disable(struct e1000_hw *hw);
 173 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 174 static int igbvf_dev_start(struct rte_eth_dev *dev);
 175 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 176 static void igbvf_dev_close(struct rte_eth_dev *dev);
 177 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 178 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 179 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 180 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 181 static int eth_igbvf_link_update(struct e1000_hw *hw);
 182 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_stats *rte_stats);
 184 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 185                                 struct rte_eth_xstat *xstats, unsigned n);
 186 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 187                                       struct rte_eth_xstat_name *xstats_names,
 188                                       unsigned limit);
 189 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 190 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 191                 uint16_t vlan_id, int on);
 192 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 193 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 194 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 195                 struct ether_addr *addr);
 196 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 197 static int igbvf_get_regs(struct rte_eth_dev *dev,
 198                 struct rte_dev_reg_info *regs);
 199
 200 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 201                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 202                                    uint16_t reta_size);
 203 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 204                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                   uint16_t reta_size);
 206
 207 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 208                         struct rte_eth_syn_filter *filter,
 209                         bool add);
 210 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter);
 212 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 213                         enum rte_filter_op filter_op,
 214                         void *arg);
 215 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ntuple_filter *ntuple_filter);
 219 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 220                         struct rte_eth_flex_filter *filter,
 221                         bool add);
 222 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter);
 224 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 225                         enum rte_filter_op filter_op,
 226                         void *arg);
 227 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *ntuple_filter);
 231 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_ntuple_filter *filter,
 233                         bool add);
 234 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter);
 236 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 240                         struct rte_eth_ethertype_filter *filter,
 241                         bool add);
 242 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 243                                 enum rte_filter_op filter_op,
 244                                 void *arg);
 245 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 246                         struct rte_eth_ethertype_filter *filter);
 247 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 248                      enum rte_filter_type filter_type,
 249                      enum rte_filter_op filter_op,
 250                      void *arg);
 251 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 252 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 253                 struct rte_dev_reg_info *regs);
 254 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 258                 struct rte_dev_eeprom_info *eeprom);
 259 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 260                                     struct ether_addr *mc_addr_set,
 261                                     uint32_t nb_mc_addr);
 262 static int igb_timesync_enable(struct rte_eth_dev *dev);
 263 static int igb_timesync_disable(struct rte_eth_dev *dev);
 264 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 265                                           struct timespec *timestamp,
 266                                           uint32_t flags);
 267 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp);
 269 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 270 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 271                                   struct timespec *timestamp);
 272 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 273                                    const struct timespec *timestamp);
 274 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                         uint16_t queue_id);
 276 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                          uint16_t queue_id);
 278 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 279                                        uint8_t queue, uint8_t msix_vector);
 280 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 281                                uint8_t index, uint8_t offset);
 282 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 283 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 284                                         void *param);
 285 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 286
 287 /*
 288  * Define VF Stats MACRO for Non "cleared on read" register
 289  */
 290 #define UPDATE_VF_STAT(reg, last, cur)            \
 291 {                                                 \
 292         u32 latest = E1000_READ_REG(hw, reg);     \
 293         cur += (latest - last) & UINT_MAX;        \
 294         last = latest;                            \
 295 }
 296
 297 #define IGB_FC_PAUSE_TIME 0x0680
 298 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 299 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 300
 301 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 302
 303 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 304
 305 /*
 306  * The set of PCI devices this driver supports
 307  */
 308 static const struct rte_pci_id pci_id_igb_map[] = {
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 317
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 321
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 328
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 348         { .vendor_id = 0, /* sentinel */ },
 349 };
 350
 351 /*
 352  * The set of PCI devices this driver supports (for 82576&I350 VF)
 353  */
 354 static const struct rte_pci_id pci_id_igbvf_map[] = {
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 359         { .vendor_id = 0, /* sentinel */ },
 360 };
 361
 362 static const struct rte_eth_desc_lim rx_desc_lim = {
 363         .nb_max = E1000_MAX_RING_DESC,
 364         .nb_min = E1000_MIN_RING_DESC,
 365         .nb_align = IGB_RXD_ALIGN,
 366 };
 367
 368 static const struct rte_eth_desc_lim tx_desc_lim = {
 369         .nb_max = E1000_MAX_RING_DESC,
 370         .nb_min = E1000_MIN_RING_DESC,
 371         .nb_align = IGB_RXD_ALIGN,
 372 };
 373
 374 static const struct eth_dev_ops eth_igb_ops = {
 375         .dev_configure        = eth_igb_configure,
 376         .dev_start            = eth_igb_start,
 377         .dev_stop             = eth_igb_stop,
 378         .dev_set_link_up      = eth_igb_dev_set_link_up,
 379         .dev_set_link_down    = eth_igb_dev_set_link_down,
 380         .dev_close            = eth_igb_close,
 381         .promiscuous_enable   = eth_igb_promiscuous_enable,
 382         .promiscuous_disable  = eth_igb_promiscuous_disable,
 383         .allmulticast_enable  = eth_igb_allmulticast_enable,
 384         .allmulticast_disable = eth_igb_allmulticast_disable,
 385         .link_update          = eth_igb_link_update,
 386         .stats_get            = eth_igb_stats_get,
 387         .xstats_get           = eth_igb_xstats_get,
 388         .xstats_get_names     = eth_igb_xstats_get_names,
 389         .stats_reset          = eth_igb_stats_reset,
 390         .xstats_reset         = eth_igb_xstats_reset,
 391         .dev_infos_get        = eth_igb_infos_get,
 392         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 393         .mtu_set              = eth_igb_mtu_set,
 394         .vlan_filter_set      = eth_igb_vlan_filter_set,
 395         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 396         .vlan_offload_set     = eth_igb_vlan_offload_set,
 397         .rx_queue_setup       = eth_igb_rx_queue_setup,
 398         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 399         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 400         .rx_queue_release     = eth_igb_rx_queue_release,
 401         .rx_queue_count       = eth_igb_rx_queue_count,
 402         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 403         .tx_queue_setup       = eth_igb_tx_queue_setup,
 404         .tx_queue_release     = eth_igb_tx_queue_release,
 405         .dev_led_on           = eth_igb_led_on,
 406         .dev_led_off          = eth_igb_led_off,
 407         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 408         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 409         .mac_addr_add         = eth_igb_rar_set,
 410         .mac_addr_remove      = eth_igb_rar_clear,
 411         .mac_addr_set         = eth_igb_default_mac_addr_set,
 412         .reta_update          = eth_igb_rss_reta_update,
 413         .reta_query           = eth_igb_rss_reta_query,
 414         .rss_hash_update      = eth_igb_rss_hash_update,
 415         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 416         .filter_ctrl          = eth_igb_filter_ctrl,
 417         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 418         .rxq_info_get         = igb_rxq_info_get,
 419         .txq_info_get         = igb_txq_info_get,
 420         .timesync_enable      = igb_timesync_enable,
 421         .timesync_disable     = igb_timesync_disable,
 422         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 423         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 424         .get_reg              = eth_igb_get_regs,
 425         .get_eeprom_length    = eth_igb_get_eeprom_length,
 426         .get_eeprom           = eth_igb_get_eeprom,
 427         .set_eeprom           = eth_igb_set_eeprom,
 428         .timesync_adjust_time = igb_timesync_adjust_time,
 429         .timesync_read_time   = igb_timesync_read_time,
 430         .timesync_write_time  = igb_timesync_write_time,
 431 };
 432
 433 /*
 434  * dev_ops for virtual function, bare necessities for basic vf
 435  * operation have been implemented
 436  */
 437 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 438         .dev_configure        = igbvf_dev_configure,
 439         .dev_start            = igbvf_dev_start,
 440         .dev_stop             = igbvf_dev_stop,
 441         .dev_close            = igbvf_dev_close,
 442         .promiscuous_enable   = igbvf_promiscuous_enable,
 443         .promiscuous_disable  = igbvf_promiscuous_disable,
 444         .allmulticast_enable  = igbvf_allmulticast_enable,
 445         .allmulticast_disable = igbvf_allmulticast_disable,
 446         .link_update          = eth_igb_link_update,
 447         .stats_get            = eth_igbvf_stats_get,
 448         .xstats_get           = eth_igbvf_xstats_get,
 449         .xstats_get_names     = eth_igbvf_xstats_get_names,
 450         .stats_reset          = eth_igbvf_stats_reset,
 451         .xstats_reset         = eth_igbvf_stats_reset,
 452         .vlan_filter_set      = igbvf_vlan_filter_set,
 453         .dev_infos_get        = eth_igbvf_infos_get,
 454         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 455         .rx_queue_setup       = eth_igb_rx_queue_setup,
 456         .rx_queue_release     = eth_igb_rx_queue_release,
 457         .tx_queue_setup       = eth_igb_tx_queue_setup,
 458         .tx_queue_release     = eth_igb_tx_queue_release,
 459         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 460         .rxq_info_get         = igb_rxq_info_get,
 461         .txq_info_get         = igb_txq_info_get,
 462         .mac_addr_set         = igbvf_default_mac_addr_set,
 463         .get_reg              = igbvf_get_regs,
 464 };
 465
 466 /* store statistics names and its offset in stats structure */
 467 struct rte_igb_xstats_name_off {
 468         char name[RTE_ETH_XSTATS_NAME_SIZE];
 469         unsigned offset;
 470 };
 471
 472 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 473         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 474         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 475         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 476         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 477         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 478         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 479         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 480                 ecol)},
 481         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 482         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 483         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 484         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 485         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 486         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 487         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 488         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 489         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 490         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 491         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 492                 fcruc)},
 493         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 494         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 495         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 496         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 497         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 498                 prc1023)},
 499         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 500                 prc1522)},
 501         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 502         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 503         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 504         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 505         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 506         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 507         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 508         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 509         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 510         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 511         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 512         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 513         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 514         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 515         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 516         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 517         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 518         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 519                 ptc1023)},
 520         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 521                 ptc1522)},
 522         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 523         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 524         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 525         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 526         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 527         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 528         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 529
 530         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 531 };
 532
 533 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 534                 sizeof(rte_igb_stats_strings[0]))
 535
 536 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 537         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 538         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 539         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 540         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 541         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 542 };
 543
 544 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 545                 sizeof(rte_igbvf_stats_strings[0]))
 546
 547 /**
 548  * Atomically reads the link status information from global
 549  * structure rte_eth_dev.
 550  *
 551  * @param dev
 552  *   - Pointer to the structure rte_eth_dev to read from.
 553  *   - Pointer to the buffer to be saved with the link status.
 554  *
 555  * @return
 556  *   - On success, zero.
 557  *   - On failure, negative value.
 558  */
 559 static inline int
 560 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 561                                 struct rte_eth_link *link)
 562 {
 563         struct rte_eth_link *dst = link;
 564         struct rte_eth_link *src = &(dev->data->dev_link);
 565
 566         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 567                                         *(uint64_t *)src) == 0)
 568                 return -1;
 569
 570         return 0;
 571 }
 572
 573 /**
 574  * Atomically writes the link status information into global
 575  * structure rte_eth_dev.
 576  *
 577  * @param dev
 578  *   - Pointer to the structure rte_eth_dev to read from.
 579  *   - Pointer to the buffer to be saved with the link status.
 580  *
 581  * @return
 582  *   - On success, zero.
 583  *   - On failure, negative value.
 584  */
 585 static inline int
 586 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 587                                 struct rte_eth_link *link)
 588 {
 589         struct rte_eth_link *dst = &(dev->data->dev_link);
 590         struct rte_eth_link *src = link;
 591
 592         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 593                                         *(uint64_t *)src) == 0)
 594                 return -1;
 595
 596         return 0;
 597 }
 598
 599 static inline void
 600 igb_intr_enable(struct rte_eth_dev *dev)
 601 {
 602         struct e1000_interrupt *intr =
 603                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 604         struct e1000_hw *hw =
 605                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 606
 607         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 608         E1000_WRITE_FLUSH(hw);
 609 }
 610
 611 static void
 612 igb_intr_disable(struct e1000_hw *hw)
 613 {
 614         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static inline void
 619 igbvf_intr_enable(struct rte_eth_dev *dev)
 620 {
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         /* only for mailbox */
 625         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 626         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 627         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 628         E1000_WRITE_FLUSH(hw);
 629 }
 630
 631 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 632 static void
 633 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 634 {
 635         uint32_t tmp = 0;
 636
 637         /* mailbox */
 638         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 639         tmp |= E1000_VTIVAR_VALID;
 640         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 641 }
 642
 643 static void
 644 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 645 {
 646         struct e1000_hw *hw =
 647                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 648
 649         /* Configure VF other cause ivar */
 650         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 651 }
 652
 653 static inline int32_t
 654 igb_pf_reset_hw(struct e1000_hw *hw)
 655 {
 656         uint32_t ctrl_ext;
 657         int32_t status;
 658
 659         status = e1000_reset_hw(hw);
 660
 661         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 665         E1000_WRITE_FLUSH(hw);
 666
 667         return status;
 668 }
 669
 670 static void
 671 igb_identify_hardware(struct rte_eth_dev *dev)
 672 {
 673         struct e1000_hw *hw =
 674                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 675
 676         hw->vendor_id = dev->pci_dev->id.vendor_id;
 677         hw->device_id = dev->pci_dev->id.device_id;
 678         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 679         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 680
 681         e1000_set_mac_type(hw);
 682
 683         /* need to check if it is a vf device below */
 684 }
 685
 686 static int
 687 igb_reset_swfw_lock(struct e1000_hw *hw)
 688 {
 689         int ret_val;
 690
 691         /*
 692          * Do mac ops initialization manually here, since we will need
 693          * some function pointers set by this call.
 694          */
 695         ret_val = e1000_init_mac_params(hw);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         /*
 700          * SMBI lock should not fail in this early stage. If this is the case,
 701          * it is due to an improper exit of the application.
 702          * So force the release of the faulty lock.
 703          */
 704         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 705                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 706         }
 707         e1000_put_hw_semaphore_generic(hw);
 708
 709         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 710                 uint16_t mask;
 711
 712                 /*
 713                  * Phy lock should not fail in this early stage. If this is the case,
 714                  * it is due to an improper exit of the application.
 715                  * So force the release of the faulty lock.
 716                  */
 717                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 718                 if (hw->bus.func > E1000_FUNC_1)
 719                         mask <<= 2;
 720                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 721                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 722                                     hw->bus.func);
 723                 }
 724                 hw->mac.ops.release_swfw_sync(hw, mask);
 725
 726                 /*
 727                  * This one is more tricky since it is common to all ports; but
 728                  * swfw_sync retries last long enough (1s) to be almost sure that if
 729                  * lock can not be taken it is due to an improper lock of the
 730                  * semaphore.
 731                  */
 732                 mask = E1000_SWFW_EEP_SM;
 733                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 734                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 735                 }
 736                 hw->mac.ops.release_swfw_sync(hw, mask);
 737         }
 738
 739         return E1000_SUCCESS;
 740 }
 741
 742 static int
 743 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         int error = 0;
 746         struct rte_pci_device *pci_dev;
 747         struct e1000_hw *hw =
 748                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 749         struct e1000_vfta * shadow_vfta =
 750                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 751         struct e1000_filter_info *filter_info =
 752                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 753         struct e1000_adapter *adapter =
 754                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 755
 756         uint32_t ctrl_ext;
 757
 758         pci_dev = eth_dev->pci_dev;
 759
 760         eth_dev->dev_ops = &eth_igb_ops;
 761         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 762         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 763
 764         /* for secondary processes, we don't initialise any further as primary
 765          * has already done this work. Only check we don't need a different
 766          * RX function */
 767         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 768                 if (eth_dev->data->scattered_rx)
 769                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 770                 return 0;
 771         }
 772
 773         rte_eth_copy_pci_info(eth_dev, pci_dev);
 774
 775         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 776
 777         igb_identify_hardware(eth_dev);
 778         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 779                 error = -EIO;
 780                 goto err_late;
 781         }
 782
 783         e1000_get_bus_info(hw);
 784
 785         /* Reset any pending lock */
 786         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         /* Finish initialization */
 792         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 793                 error = -EIO;
 794                 goto err_late;
 795         }
 796
 797         hw->mac.autoneg = 1;
 798         hw->phy.autoneg_wait_to_complete = 0;
 799         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 800
 801         /* Copper options */
 802         if (hw->phy.media_type == e1000_media_type_copper) {
 803                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 804                 hw->phy.disable_polarity_correction = 0;
 805                 hw->phy.ms_type = e1000_ms_hw_default;
 806         }
 807
 808         /*
 809          * Start from a known state, this is important in reading the nvm
 810          * and mac from that.
 811          */
 812         igb_pf_reset_hw(hw);
 813
 814         /* Make sure we have a good EEPROM before we read from it */
 815         if (e1000_validate_nvm_checksum(hw) < 0) {
 816                 /*
 817                  * Some PCI-E parts fail the first check due to
 818                  * the link being in sleep state, call it again,
 819                  * if it fails a second time its a real issue.
 820                  */
 821                 if (e1000_validate_nvm_checksum(hw) < 0) {
 822                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 823                         error = -EIO;
 824                         goto err_late;
 825                 }
 826         }
 827
 828         /* Read the permanent MAC address out of the EEPROM */
 829         if (e1000_read_mac_addr(hw) != 0) {
 830                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 831                 error = -EIO;
 832                 goto err_late;
 833         }
 834
 835         /* Allocate memory for storing MAC addresses */
 836         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 837                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 838         if (eth_dev->data->mac_addrs == NULL) {
 839                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 840                                                 "store MAC addresses",
 841                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 842                 error = -ENOMEM;
 843                 goto err_late;
 844         }
 845
 846         /* Copy the permanent MAC address */
 847         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 848
 849         /* initialize the vfta */
 850         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 851
 852         /* Now initialize the hardware */
 853         if (igb_hardware_init(hw) != 0) {
 854                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 855                 rte_free(eth_dev->data->mac_addrs);
 856                 eth_dev->data->mac_addrs = NULL;
 857                 error = -ENODEV;
 858                 goto err_late;
 859         }
 860         hw->mac.get_link_status = 1;
 861         adapter->stopped = 0;
 862
 863         /* Indicate SOL/IDER usage */
 864         if (e1000_check_reset_block(hw) < 0) {
 865                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 866                                         "SOL/IDER session");
 867         }
 868
 869         /* initialize PF if max_vfs not zero */
 870         igb_pf_host_init(eth_dev);
 871
 872         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 873         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 874         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 875         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 876         E1000_WRITE_FLUSH(hw);
 877
 878         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 879                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 880                      pci_dev->id.device_id);
 881
 882         rte_intr_callback_register(&pci_dev->intr_handle,
 883                                    eth_igb_interrupt_handler,
 884                                    (void *)eth_dev);
 885
 886         /* enable uio/vfio intr/eventfd mapping */
 887         rte_intr_enable(&pci_dev->intr_handle);
 888
 889         /* enable support intr */
 890         igb_intr_enable(eth_dev);
 891
 892         TAILQ_INIT(&filter_info->flex_list);
 893         filter_info->flex_mask = 0;
 894         TAILQ_INIT(&filter_info->twotuple_list);
 895         filter_info->twotuple_mask = 0;
 896         TAILQ_INIT(&filter_info->fivetuple_list);
 897         filter_info->fivetuple_mask = 0;
 898
 899         return 0;
 900
 901 err_late:
 902         igb_hw_control_release(hw);
 903
 904         return error;
 905 }
 906
 907 static int
 908 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 909 {
 910         struct rte_pci_device *pci_dev;
 911         struct e1000_hw *hw;
 912         struct e1000_adapter *adapter =
 913                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 914
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 918                 return -EPERM;
 919
 920         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         pci_dev = eth_dev->pci_dev;
 922
 923         if (adapter->stopped == 0)
 924                 eth_igb_close(eth_dev);
 925
 926         eth_dev->dev_ops = NULL;
 927         eth_dev->rx_pkt_burst = NULL;
 928         eth_dev->tx_pkt_burst = NULL;
 929
 930         /* Reset any pending lock */
 931         igb_reset_swfw_lock(hw);
 932
 933         rte_free(eth_dev->data->mac_addrs);
 934         eth_dev->data->mac_addrs = NULL;
 935
 936         /* uninitialize PF if max_vfs not zero */
 937         igb_pf_host_uninit(eth_dev);
 938
 939         /* disable uio intr before callback unregister */
 940         rte_intr_disable(&(pci_dev->intr_handle));
 941         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 942                 eth_igb_interrupt_handler, (void *)eth_dev);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * Virtual Function device init
 949  */
 950 static int
 951 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966
 967         /* for secondary processes, we don't initialise any further as primary
 968          * has already done this work. Only check we don't need a different
 969          * RX function */
 970         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 971                 if (eth_dev->data->scattered_rx)
 972                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 973                 return 0;
 974         }
 975
 976         pci_dev = eth_dev->pci_dev;
 977
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1016                 if (diag) {
1017                         rte_free(eth_dev->data->mac_addrs);
1018                         eth_dev->data->mac_addrs = NULL;
1019                         return diag;
1020                 }
1021                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1022                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1023                              "%02x:%02x:%02x:%02x:%02x:%02x",
1024                              perm_addr->addr_bytes[0],
1025                              perm_addr->addr_bytes[1],
1026                              perm_addr->addr_bytes[2],
1027                              perm_addr->addr_bytes[3],
1028                              perm_addr->addr_bytes[4],
1029                              perm_addr->addr_bytes[5]);
1030         }
1031
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         rte_intr_callback_register(&pci_dev->intr_handle,
1042                                    eth_igbvf_interrupt_handler,
1043                                    (void *)eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static struct eth_driver rte_igb_pmd = {
1080         .pci_drv = {
1081                 .name = "rte_igb_pmd",
1082                 .id_table = pci_id_igb_map,
1083                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1084                         RTE_PCI_DRV_DETACHABLE,
1085         },
1086         .eth_dev_init = eth_igb_dev_init,
1087         .eth_dev_uninit = eth_igb_dev_uninit,
1088         .dev_private_size = sizeof(struct e1000_adapter),
1089 };
1090
1091 /*
1092  * virtual function driver struct
1093  */
1094 static struct eth_driver rte_igbvf_pmd = {
1095         .pci_drv = {
1096                 .name = "rte_igbvf_pmd",
1097                 .id_table = pci_id_igbvf_map,
1098                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1099         },
1100         .eth_dev_init = eth_igbvf_dev_init,
1101         .eth_dev_uninit = eth_igbvf_dev_uninit,
1102         .dev_private_size = sizeof(struct e1000_adapter),
1103 };
1104
1105 static int
1106 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1107 {
1108         rte_eth_driver_register(&rte_igb_pmd);
1109         return 0;
1110 }
1111
1112 static void
1113 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1114 {
1115         struct e1000_hw *hw =
1116                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1118         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1119         rctl |= E1000_RCTL_VFE;
1120         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1121 }
1122
1123 /*
1124  * VF Driver initialization routine.
1125  * Invoked one at EAL init time.
1126  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1127  */
1128 static int
1129 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1130 {
1131         PMD_INIT_FUNC_TRACE();
1132
1133         rte_eth_driver_register(&rte_igbvf_pmd);
1134         return 0;
1135 }
1136
1137 static int
1138 igb_check_mq_mode(struct rte_eth_dev *dev)
1139 {
1140         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1141         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1142         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1143         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1144
1145         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1146             tx_mq_mode == ETH_MQ_TX_DCB ||
1147             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1148                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1149                 return -EINVAL;
1150         }
1151         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1152                 /* Check multi-queue mode.
1153                  * To no break software we accept ETH_MQ_RX_NONE as this might
1154                  * be used to turn off VLAN filter.
1155                  */
1156
1157                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1158                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1159                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1160                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1161                 } else {
1162                         /* Only support one queue on VFs.
1163                          * RSS together with SRIOV is not supported.
1164                          */
1165                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1166                                         " wrong mq_mode rx %d.",
1167                                         rx_mq_mode);
1168                         return -EINVAL;
1169                 }
1170                 /* TX mode is not used here, so mode might be ignored.*/
1171                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1172                         /* SRIOV only works in VMDq enable mode */
1173                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1174                                         " TX mode %d is not supported. "
1175                                         " Driver will behave as %d mode.",
1176                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1177                 }
1178
1179                 /* check valid queue number */
1180                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1181                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1182                                         " only support one queue on VFs.");
1183                         return -EINVAL;
1184                 }
1185         } else {
1186                 /* To no break software that set invalid mode, only display
1187                  * warning if invalid mode is used.
1188                  */
1189                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1190                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1191                     rx_mq_mode != ETH_MQ_RX_RSS) {
1192                         /* RSS together with VMDq not supported*/
1193                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1194                                      rx_mq_mode);
1195                         return -EINVAL;
1196                 }
1197
1198                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1199                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1200                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1201                                         " Due to txmode is meaningless in this"
1202                                         " driver, just ignore.",
1203                                         tx_mq_mode);
1204                 }
1205         }
1206         return 0;
1207 }
1208
1209 static int
1210 eth_igb_configure(struct rte_eth_dev *dev)
1211 {
1212         struct e1000_interrupt *intr =
1213                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1214         int ret;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* multipe queue mode checking */
1219         ret  = igb_check_mq_mode(dev);
1220         if (ret != 0) {
1221                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1222                             ret);
1223                 return ret;
1224         }
1225
1226         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1227         PMD_INIT_FUNC_TRACE();
1228
1229         return 0;
1230 }
1231
1232 static int
1233 eth_igb_start(struct rte_eth_dev *dev)
1234 {
1235         struct e1000_hw *hw =
1236                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1237         struct e1000_adapter *adapter =
1238                 E1000_DEV_PRIVATE(dev->data->dev_private);
1239         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1240         int ret, mask;
1241         uint32_t intr_vector = 0;
1242         uint32_t ctrl_ext;
1243         uint32_t *speeds;
1244         int num_speeds;
1245         bool autoneg;
1246
1247         PMD_INIT_FUNC_TRACE();
1248
1249         /* disable uio/vfio intr/eventfd mapping */
1250         rte_intr_disable(intr_handle);
1251
1252         /* Power up the phy. Needed to make the link go Up */
1253         eth_igb_dev_set_link_up(dev);
1254
1255         /*
1256          * Packet Buffer Allocation (PBA)
1257          * Writing PBA sets the receive portion of the buffer
1258          * the remainder is used for the transmit buffer.
1259          */
1260         if (hw->mac.type == e1000_82575) {
1261                 uint32_t pba;
1262
1263                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1264                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1265         }
1266
1267         /* Put the address into the Receive Address Array */
1268         e1000_rar_set(hw, hw->mac.addr, 0);
1269
1270         /* Initialize the hardware */
1271         if (igb_hardware_init(hw)) {
1272                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1273                 return -EIO;
1274         }
1275         adapter->stopped = 0;
1276
1277         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1278
1279         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1280         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1281         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1282         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1283         E1000_WRITE_FLUSH(hw);
1284
1285         /* configure PF module if SRIOV enabled */
1286         igb_pf_host_configure(dev);
1287
1288         /* check and configure queue intr-vector mapping */
1289         if ((rte_intr_cap_multiple(intr_handle) ||
1290              !RTE_ETH_DEV_SRIOV(dev).active) &&
1291             dev->data->dev_conf.intr_conf.rxq != 0) {
1292                 intr_vector = dev->data->nb_rx_queues;
1293                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1294                         return -1;
1295         }
1296
1297         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1298                 intr_handle->intr_vec =
1299                         rte_zmalloc("intr_vec",
1300                                     dev->data->nb_rx_queues * sizeof(int), 0);
1301                 if (intr_handle->intr_vec == NULL) {
1302                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1303                                      " intr_vec\n", dev->data->nb_rx_queues);
1304                         return -ENOMEM;
1305                 }
1306         }
1307
1308         /* confiugre msix for rx interrupt */
1309         eth_igb_configure_msix_intr(dev);
1310
1311         /* Configure for OS presence */
1312         igb_init_manageability(hw);
1313
1314         eth_igb_tx_init(dev);
1315
1316         /* This can fail when allocating mbufs for descriptor rings */
1317         ret = eth_igb_rx_init(dev);
1318         if (ret) {
1319                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1320                 igb_dev_clear_queues(dev);
1321                 return ret;
1322         }
1323
1324         e1000_clear_hw_cntrs_base_generic(hw);
1325
1326         /*
1327          * VLAN Offload Settings
1328          */
1329         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1330                         ETH_VLAN_EXTEND_MASK;
1331         eth_igb_vlan_offload_set(dev, mask);
1332
1333         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1334                 /* Enable VLAN filter since VMDq always use VLAN filter */
1335                 igb_vmdq_vlan_hw_filter_enable(dev);
1336         }
1337
1338         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1339                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1340                 (hw->mac.type == e1000_i211)) {
1341                 /* Configure EITR with the maximum possible value (0xFFFF) */
1342                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1343         }
1344
1345         /* Setup link speed and duplex */
1346         speeds = &dev->data->dev_conf.link_speeds;
1347         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1348                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1349         } else {
1350                 num_speeds = 0;
1351                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1352
1353                 /* Reset */
1354                 hw->phy.autoneg_advertised = 0;
1355
1356                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1357                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1358                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1359                         num_speeds = -1;
1360                         goto error_invalid_config;
1361                 }
1362                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1363                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1364                         num_speeds++;
1365                 }
1366                 if (*speeds & ETH_LINK_SPEED_10M) {
1367                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1368                         num_speeds++;
1369                 }
1370                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1371                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1372                         num_speeds++;
1373                 }
1374                 if (*speeds & ETH_LINK_SPEED_100M) {
1375                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1376                         num_speeds++;
1377                 }
1378                 if (*speeds & ETH_LINK_SPEED_1G) {
1379                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1380                         num_speeds++;
1381                 }
1382                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1383                         goto error_invalid_config;
1384         }
1385
1386         e1000_setup_link(hw);
1387
1388         if (rte_intr_allow_others(intr_handle)) {
1389                 /* check if lsc interrupt is enabled */
1390                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1391                         eth_igb_lsc_interrupt_setup(dev);
1392         } else {
1393                 rte_intr_callback_unregister(intr_handle,
1394                                              eth_igb_interrupt_handler,
1395                                              (void *)dev);
1396                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1397                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1398                                      " no intr multiplex\n");
1399         }
1400
1401         /* check if rxq interrupt is enabled */
1402         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1403             rte_intr_dp_is_en(intr_handle))
1404                 eth_igb_rxq_interrupt_setup(dev);
1405
1406         /* enable uio/vfio intr/eventfd mapping */
1407         rte_intr_enable(intr_handle);
1408
1409         /* resume enabled intr since hw reset */
1410         igb_intr_enable(dev);
1411
1412         PMD_INIT_LOG(DEBUG, "<<");
1413
1414         return 0;
1415
1416 error_invalid_config:
1417         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1418                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1419         igb_dev_clear_queues(dev);
1420         return -EINVAL;
1421 }
1422
1423 /*********************************************************************
1424  *
1425  *  This routine disables all traffic on the adapter by issuing a
1426  *  global reset on the MAC.
1427  *
1428  **********************************************************************/
1429 static void
1430 eth_igb_stop(struct rte_eth_dev *dev)
1431 {
1432         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1433         struct e1000_filter_info *filter_info =
1434                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1435         struct rte_eth_link link;
1436         struct e1000_flex_filter *p_flex;
1437         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1438         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1439         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1440
1441         igb_intr_disable(hw);
1442
1443         /* disable intr eventfd mapping */
1444         rte_intr_disable(intr_handle);
1445
1446         igb_pf_reset_hw(hw);
1447         E1000_WRITE_REG(hw, E1000_WUC, 0);
1448
1449         /* Set bit for Go Link disconnect */
1450         if (hw->mac.type >= e1000_82580) {
1451                 uint32_t phpm_reg;
1452
1453                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1454                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1455                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1456         }
1457
1458         /* Power down the phy. Needed to make the link go Down */
1459         eth_igb_dev_set_link_down(dev);
1460
1461         igb_dev_clear_queues(dev);
1462
1463         /* clear the recorded link status */
1464         memset(&link, 0, sizeof(link));
1465         rte_igb_dev_atomic_write_link_status(dev, &link);
1466
1467         /* Remove all flex filters of the device */
1468         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1469                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1470                 rte_free(p_flex);
1471         }
1472         filter_info->flex_mask = 0;
1473
1474         /* Remove all ntuple filters of the device */
1475         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1476              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1477                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1478                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1479                              p_5tuple, entries);
1480                 rte_free(p_5tuple);
1481         }
1482         filter_info->fivetuple_mask = 0;
1483         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1484              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1485                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1486                 TAILQ_REMOVE(&filter_info->twotuple_list,
1487                              p_2tuple, entries);
1488                 rte_free(p_2tuple);
1489         }
1490         filter_info->twotuple_mask = 0;
1491
1492         if (!rte_intr_allow_others(intr_handle))
1493                 /* resume to the default handler */
1494                 rte_intr_callback_register(intr_handle,
1495                                            eth_igb_interrupt_handler,
1496                                            (void *)dev);
1497
1498         /* Clean datapath event and queue/vec mapping */
1499         rte_intr_efd_disable(intr_handle);
1500         if (intr_handle->intr_vec != NULL) {
1501                 rte_free(intr_handle->intr_vec);
1502                 intr_handle->intr_vec = NULL;
1503         }
1504 }
1505
1506 static int
1507 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1508 {
1509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1510
1511         if (hw->phy.media_type == e1000_media_type_copper)
1512                 e1000_power_up_phy(hw);
1513         else
1514                 e1000_power_up_fiber_serdes_link(hw);
1515
1516         return 0;
1517 }
1518
1519 static int
1520 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1521 {
1522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523
1524         if (hw->phy.media_type == e1000_media_type_copper)
1525                 e1000_power_down_phy(hw);
1526         else
1527                 e1000_shutdown_fiber_serdes_link(hw);
1528
1529         return 0;
1530 }
1531
1532 static void
1533 eth_igb_close(struct rte_eth_dev *dev)
1534 {
1535         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536         struct e1000_adapter *adapter =
1537                 E1000_DEV_PRIVATE(dev->data->dev_private);
1538         struct rte_eth_link link;
1539         struct rte_pci_device *pci_dev;
1540
1541         eth_igb_stop(dev);
1542         adapter->stopped = 1;
1543
1544         e1000_phy_hw_reset(hw);
1545         igb_release_manageability(hw);
1546         igb_hw_control_release(hw);
1547
1548         /* Clear bit for Go Link disconnect */
1549         if (hw->mac.type >= e1000_82580) {
1550                 uint32_t phpm_reg;
1551
1552                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1553                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1554                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1555         }
1556
1557         igb_dev_free_queues(dev);
1558
1559         pci_dev = dev->pci_dev;
1560         if (pci_dev->intr_handle.intr_vec) {
1561                 rte_free(pci_dev->intr_handle.intr_vec);
1562                 pci_dev->intr_handle.intr_vec = NULL;
1563         }
1564
1565         memset(&link, 0, sizeof(link));
1566         rte_igb_dev_atomic_write_link_status(dev, &link);
1567 }
1568
1569 static int
1570 igb_get_rx_buffer_size(struct e1000_hw *hw)
1571 {
1572         uint32_t rx_buf_size;
1573         if (hw->mac.type == e1000_82576) {
1574                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1575         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1576                 /* PBS needs to be translated according to a lookup table */
1577                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1578                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1579                 rx_buf_size = (rx_buf_size << 10);
1580         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1581                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1582         } else {
1583                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1584         }
1585
1586         return rx_buf_size;
1587 }
1588
1589 /*********************************************************************
1590  *
1591  *  Initialize the hardware
1592  *
1593  **********************************************************************/
1594 static int
1595 igb_hardware_init(struct e1000_hw *hw)
1596 {
1597         uint32_t rx_buf_size;
1598         int diag;
1599
1600         /* Let the firmware know the OS is in control */
1601         igb_hw_control_acquire(hw);
1602
1603         /*
1604          * These parameters control the automatic generation (Tx) and
1605          * response (Rx) to Ethernet PAUSE frames.
1606          * - High water mark should allow for at least two standard size (1518)
1607          *   frames to be received after sending an XOFF.
1608          * - Low water mark works best when it is very near the high water mark.
1609          *   This allows the receiver to restart by sending XON when it has
1610          *   drained a bit. Here we use an arbitrary value of 1500 which will
1611          *   restart after one full frame is pulled from the buffer. There
1612          *   could be several smaller frames in the buffer and if so they will
1613          *   not trigger the XON until their total number reduces the buffer
1614          *   by 1500.
1615          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1616          */
1617         rx_buf_size = igb_get_rx_buffer_size(hw);
1618
1619         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1620         hw->fc.low_water = hw->fc.high_water - 1500;
1621         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1622         hw->fc.send_xon = 1;
1623
1624         /* Set Flow control, use the tunable location if sane */
1625         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1626                 hw->fc.requested_mode = igb_fc_setting;
1627         else
1628                 hw->fc.requested_mode = e1000_fc_none;
1629
1630         /* Issue a global reset */
1631         igb_pf_reset_hw(hw);
1632         E1000_WRITE_REG(hw, E1000_WUC, 0);
1633
1634         diag = e1000_init_hw(hw);
1635         if (diag < 0)
1636                 return diag;
1637
1638         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1639         e1000_get_phy_info(hw);
1640         e1000_check_for_link(hw);
1641
1642         return 0;
1643 }
1644
1645 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1646 static void
1647 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1648 {
1649         int pause_frames;
1650
1651         uint64_t old_gprc  = stats->gprc;
1652         uint64_t old_gptc  = stats->gptc;
1653         uint64_t old_tpr   = stats->tpr;
1654         uint64_t old_tpt   = stats->tpt;
1655         uint64_t old_rpthc = stats->rpthc;
1656         uint64_t old_hgptc = stats->hgptc;
1657
1658         if(hw->phy.media_type == e1000_media_type_copper ||
1659             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1660                 stats->symerrs +=
1661                     E1000_READ_REG(hw,E1000_SYMERRS);
1662                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1663         }
1664
1665         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1666         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1667         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1668         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1669
1670         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1671         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1672         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1673         stats->dc += E1000_READ_REG(hw, E1000_DC);
1674         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1675         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1676         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1677         /*
1678         ** For watchdog management we need to know if we have been
1679         ** paused during the last interval, so capture that here.
1680         */
1681         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1682         stats->xoffrxc += pause_frames;
1683         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1684         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1685         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1686         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1687         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1688         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1689         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1690         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1691         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1692         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1693         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1694         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1695
1696         /* For the 64-bit byte counters the low dword must be read first. */
1697         /* Both registers clear on the read of the high dword */
1698
1699         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1700         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1701         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1702         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1703         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1704         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1705         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1706
1707         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1708         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1709         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1710         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1711         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1712
1713         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1714         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1715
1716         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1717         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1718         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1719         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1720         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1721         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1722
1723         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1724         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1725         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1726         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1727         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1728         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1729         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1730         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1731
1732         /* Interrupt Counts */
1733
1734         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1735         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1736         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1737         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1738         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1739         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1740         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1741         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1742         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1743
1744         /* Host to Card Statistics */
1745
1746         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1747         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1748         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1749         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1750         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1751         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1752         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1753         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1754         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1755         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1756         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1757         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1758         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1759         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1760         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1761         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1762
1763         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1764         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1765         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1766         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1767         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1768         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1769 }
1770
1771 static void
1772 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1773 {
1774         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         struct e1000_hw_stats *stats =
1776                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1777
1778         igb_read_stats_registers(hw, stats);
1779
1780         if (rte_stats == NULL)
1781                 return;
1782
1783         /* Rx Errors */
1784         rte_stats->imissed = stats->mpc;
1785         rte_stats->ierrors = stats->crcerrs +
1786                              stats->rlec + stats->ruc + stats->roc +
1787                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1788
1789         /* Tx Errors */
1790         rte_stats->oerrors = stats->ecol + stats->latecol;
1791
1792         rte_stats->ipackets = stats->gprc;
1793         rte_stats->opackets = stats->gptc;
1794         rte_stats->ibytes   = stats->gorc;
1795         rte_stats->obytes   = stats->gotc;
1796 }
1797
1798 static void
1799 eth_igb_stats_reset(struct rte_eth_dev *dev)
1800 {
1801         struct e1000_hw_stats *hw_stats =
1802                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1803
1804         /* HW registers are cleared on read */
1805         eth_igb_stats_get(dev, NULL);
1806
1807         /* Reset software totals */
1808         memset(hw_stats, 0, sizeof(*hw_stats));
1809 }
1810
1811 static void
1812 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1813 {
1814         struct e1000_hw_stats *stats =
1815                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1816
1817         /* HW registers are cleared on read */
1818         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1819
1820         /* Reset software totals */
1821         memset(stats, 0, sizeof(*stats));
1822 }
1823
1824 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1825         struct rte_eth_xstat_name *xstats_names,
1826         __rte_unused unsigned limit)
1827 {
1828         unsigned i;
1829
1830         if (xstats_names == NULL)
1831                 return IGB_NB_XSTATS;
1832
1833         /* Note: limit checked in rte_eth_xstats_names() */
1834
1835         for (i = 0; i < IGB_NB_XSTATS; i++) {
1836                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1837                          "%s", rte_igb_stats_strings[i].name);
1838         }
1839
1840         return IGB_NB_XSTATS;
1841 }
1842
1843 static int
1844 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1845                    unsigned n)
1846 {
1847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct e1000_hw_stats *hw_stats =
1849                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1850         unsigned i;
1851
1852         if (n < IGB_NB_XSTATS)
1853                 return IGB_NB_XSTATS;
1854
1855         igb_read_stats_registers(hw, hw_stats);
1856
1857         /* If this is a reset xstats is NULL, and we have cleared the
1858          * registers by reading them.
1859          */
1860         if (!xstats)
1861                 return 0;
1862
1863         /* Extended stats */
1864         for (i = 0; i < IGB_NB_XSTATS; i++) {
1865                 xstats[i].id = i;
1866                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1867                         rte_igb_stats_strings[i].offset);
1868         }
1869
1870         return IGB_NB_XSTATS;
1871 }
1872
1873 static void
1874 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1875 {
1876         /* Good Rx packets, include VF loopback */
1877         UPDATE_VF_STAT(E1000_VFGPRC,
1878             hw_stats->last_gprc, hw_stats->gprc);
1879
1880         /* Good Rx octets, include VF loopback */
1881         UPDATE_VF_STAT(E1000_VFGORC,
1882             hw_stats->last_gorc, hw_stats->gorc);
1883
1884         /* Good Tx packets, include VF loopback */
1885         UPDATE_VF_STAT(E1000_VFGPTC,
1886             hw_stats->last_gptc, hw_stats->gptc);
1887
1888         /* Good Tx octets, include VF loopback */
1889         UPDATE_VF_STAT(E1000_VFGOTC,
1890             hw_stats->last_gotc, hw_stats->gotc);
1891
1892         /* Rx Multicst packets */
1893         UPDATE_VF_STAT(E1000_VFMPRC,
1894             hw_stats->last_mprc, hw_stats->mprc);
1895
1896         /* Good Rx loopback packets */
1897         UPDATE_VF_STAT(E1000_VFGPRLBC,
1898             hw_stats->last_gprlbc, hw_stats->gprlbc);
1899
1900         /* Good Rx loopback octets */
1901         UPDATE_VF_STAT(E1000_VFGORLBC,
1902             hw_stats->last_gorlbc, hw_stats->gorlbc);
1903
1904         /* Good Tx loopback packets */
1905         UPDATE_VF_STAT(E1000_VFGPTLBC,
1906             hw_stats->last_gptlbc, hw_stats->gptlbc);
1907
1908         /* Good Tx loopback octets */
1909         UPDATE_VF_STAT(E1000_VFGOTLBC,
1910             hw_stats->last_gotlbc, hw_stats->gotlbc);
1911 }
1912
1913 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1914                                      struct rte_eth_xstat_name *xstats_names,
1915                                      __rte_unused unsigned limit)
1916 {
1917         unsigned i;
1918
1919         if (xstats_names != NULL)
1920                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1921                         snprintf(xstats_names[i].name,
1922                                 sizeof(xstats_names[i].name), "%s",
1923                                 rte_igbvf_stats_strings[i].name);
1924                 }
1925         return IGBVF_NB_XSTATS;
1926 }
1927
1928 static int
1929 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1930                      unsigned n)
1931 {
1932         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1934                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1935         unsigned i;
1936
1937         if (n < IGBVF_NB_XSTATS)
1938                 return IGBVF_NB_XSTATS;
1939
1940         igbvf_read_stats_registers(hw, hw_stats);
1941
1942         if (!xstats)
1943                 return 0;
1944
1945         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1946                 xstats[i].id = i;
1947                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1948                         rte_igbvf_stats_strings[i].offset);
1949         }
1950
1951         return IGBVF_NB_XSTATS;
1952 }
1953
1954 static void
1955 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1956 {
1957         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1959                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1960
1961         igbvf_read_stats_registers(hw, hw_stats);
1962
1963         if (rte_stats == NULL)
1964                 return;
1965
1966         rte_stats->ipackets = hw_stats->gprc;
1967         rte_stats->ibytes = hw_stats->gorc;
1968         rte_stats->opackets = hw_stats->gptc;
1969         rte_stats->obytes = hw_stats->gotc;
1970 }
1971
1972 static void
1973 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1974 {
1975         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1976                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1977
1978         /* Sync HW register to the last stats */
1979         eth_igbvf_stats_get(dev, NULL);
1980
1981         /* reset HW current stats*/
1982         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1983                offsetof(struct e1000_vf_stats, gprc));
1984 }
1985
1986 static void
1987 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1988 {
1989         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990
1991         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1992         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1993         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1994         dev_info->rx_offload_capa =
1995                 DEV_RX_OFFLOAD_VLAN_STRIP |
1996                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1997                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1998                 DEV_RX_OFFLOAD_TCP_CKSUM;
1999         dev_info->tx_offload_capa =
2000                 DEV_TX_OFFLOAD_VLAN_INSERT |
2001                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2002                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2003                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2004                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2005                 DEV_TX_OFFLOAD_TCP_TSO;
2006
2007         switch (hw->mac.type) {
2008         case e1000_82575:
2009                 dev_info->max_rx_queues = 4;
2010                 dev_info->max_tx_queues = 4;
2011                 dev_info->max_vmdq_pools = 0;
2012                 break;
2013
2014         case e1000_82576:
2015                 dev_info->max_rx_queues = 16;
2016                 dev_info->max_tx_queues = 16;
2017                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2018                 dev_info->vmdq_queue_num = 16;
2019                 break;
2020
2021         case e1000_82580:
2022                 dev_info->max_rx_queues = 8;
2023                 dev_info->max_tx_queues = 8;
2024                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2025                 dev_info->vmdq_queue_num = 8;
2026                 break;
2027
2028         case e1000_i350:
2029                 dev_info->max_rx_queues = 8;
2030                 dev_info->max_tx_queues = 8;
2031                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2032                 dev_info->vmdq_queue_num = 8;
2033                 break;
2034
2035         case e1000_i354:
2036                 dev_info->max_rx_queues = 8;
2037                 dev_info->max_tx_queues = 8;
2038                 break;
2039
2040         case e1000_i210:
2041                 dev_info->max_rx_queues = 4;
2042                 dev_info->max_tx_queues = 4;
2043                 dev_info->max_vmdq_pools = 0;
2044                 break;
2045
2046         case e1000_i211:
2047                 dev_info->max_rx_queues = 2;
2048                 dev_info->max_tx_queues = 2;
2049                 dev_info->max_vmdq_pools = 0;
2050                 break;
2051
2052         default:
2053                 /* Should not happen */
2054                 break;
2055         }
2056         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2057         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2058         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2059
2060         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2061                 .rx_thresh = {
2062                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2063                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2064                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2065                 },
2066                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2067                 .rx_drop_en = 0,
2068         };
2069
2070         dev_info->default_txconf = (struct rte_eth_txconf) {
2071                 .tx_thresh = {
2072                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2073                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2074                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2075                 },
2076                 .txq_flags = 0,
2077         };
2078
2079         dev_info->rx_desc_lim = rx_desc_lim;
2080         dev_info->tx_desc_lim = tx_desc_lim;
2081
2082         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2083                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2084                         ETH_LINK_SPEED_1G;
2085 }
2086
2087 static const uint32_t *
2088 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2089 {
2090         static const uint32_t ptypes[] = {
2091                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2092                 RTE_PTYPE_L2_ETHER,
2093                 RTE_PTYPE_L3_IPV4,
2094                 RTE_PTYPE_L3_IPV4_EXT,
2095                 RTE_PTYPE_L3_IPV6,
2096                 RTE_PTYPE_L3_IPV6_EXT,
2097                 RTE_PTYPE_L4_TCP,
2098                 RTE_PTYPE_L4_UDP,
2099                 RTE_PTYPE_L4_SCTP,
2100                 RTE_PTYPE_TUNNEL_IP,
2101                 RTE_PTYPE_INNER_L3_IPV6,
2102                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2103                 RTE_PTYPE_INNER_L4_TCP,
2104                 RTE_PTYPE_INNER_L4_UDP,
2105                 RTE_PTYPE_UNKNOWN
2106         };
2107
2108         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2109             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2110                 return ptypes;
2111         return NULL;
2112 }
2113
2114 static void
2115 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2116 {
2117         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2118
2119         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2120         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2121         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2122         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2123                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2124                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2125                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2126         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2127                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2128                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2129                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2130                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2131                                 DEV_TX_OFFLOAD_TCP_TSO;
2132         switch (hw->mac.type) {
2133         case e1000_vfadapt:
2134                 dev_info->max_rx_queues = 2;
2135                 dev_info->max_tx_queues = 2;
2136                 break;
2137         case e1000_vfadapt_i350:
2138                 dev_info->max_rx_queues = 1;
2139                 dev_info->max_tx_queues = 1;
2140                 break;
2141         default:
2142                 /* Should not happen */
2143                 break;
2144         }
2145
2146         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2147                 .rx_thresh = {
2148                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2149                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2150                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2151                 },
2152                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2153                 .rx_drop_en = 0,
2154         };
2155
2156         dev_info->default_txconf = (struct rte_eth_txconf) {
2157                 .tx_thresh = {
2158                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2159                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2160                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2161                 },
2162                 .txq_flags = 0,
2163         };
2164
2165         dev_info->rx_desc_lim = rx_desc_lim;
2166         dev_info->tx_desc_lim = tx_desc_lim;
2167 }
2168
2169 /* return 0 means link status changed, -1 means not changed */
2170 static int
2171 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2172 {
2173         struct e1000_hw *hw =
2174                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct rte_eth_link link, old;
2176         int link_check, count;
2177
2178         link_check = 0;
2179         hw->mac.get_link_status = 1;
2180
2181         /* possible wait-to-complete in up to 9 seconds */
2182         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2183                 /* Read the real link status */
2184                 switch (hw->phy.media_type) {
2185                 case e1000_media_type_copper:
2186                         /* Do the work to read phy */
2187                         e1000_check_for_link(hw);
2188                         link_check = !hw->mac.get_link_status;
2189                         break;
2190
2191                 case e1000_media_type_fiber:
2192                         e1000_check_for_link(hw);
2193                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2194                                       E1000_STATUS_LU);
2195                         break;
2196
2197                 case e1000_media_type_internal_serdes:
2198                         e1000_check_for_link(hw);
2199                         link_check = hw->mac.serdes_has_link;
2200                         break;
2201
2202                 /* VF device is type_unknown */
2203                 case e1000_media_type_unknown:
2204                         eth_igbvf_link_update(hw);
2205                         link_check = !hw->mac.get_link_status;
2206                         break;
2207
2208                 default:
2209                         break;
2210                 }
2211                 if (link_check || wait_to_complete == 0)
2212                         break;
2213                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2214         }
2215         memset(&link, 0, sizeof(link));
2216         rte_igb_dev_atomic_read_link_status(dev, &link);
2217         old = link;
2218
2219         /* Now we check if a transition has happened */
2220         if (link_check) {
2221                 uint16_t duplex, speed;
2222                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2223                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2224                                 ETH_LINK_FULL_DUPLEX :
2225                                 ETH_LINK_HALF_DUPLEX;
2226                 link.link_speed = speed;
2227                 link.link_status = ETH_LINK_UP;
2228                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2229                                 ETH_LINK_SPEED_FIXED);
2230         } else if (!link_check) {
2231                 link.link_speed = 0;
2232                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2233                 link.link_status = ETH_LINK_DOWN;
2234                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2235         }
2236         rte_igb_dev_atomic_write_link_status(dev, &link);
2237
2238         /* not changed */
2239         if (old.link_status == link.link_status)
2240                 return -1;
2241
2242         /* changed */
2243         return 0;
2244 }
2245
2246 /*
2247  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2248  * For ASF and Pass Through versions of f/w this means
2249  * that the driver is loaded.
2250  */
2251 static void
2252 igb_hw_control_acquire(struct e1000_hw *hw)
2253 {
2254         uint32_t ctrl_ext;
2255
2256         /* Let firmware know the driver has taken over */
2257         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2258         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2259 }
2260
2261 /*
2262  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2263  * For ASF and Pass Through versions of f/w this means that the
2264  * driver is no longer loaded.
2265  */
2266 static void
2267 igb_hw_control_release(struct e1000_hw *hw)
2268 {
2269         uint32_t ctrl_ext;
2270
2271         /* Let firmware taken over control of h/w */
2272         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2273         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2274                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2275 }
2276
2277 /*
2278  * Bit of a misnomer, what this really means is
2279  * to enable OS management of the system... aka
2280  * to disable special hardware management features.
2281  */
2282 static void
2283 igb_init_manageability(struct e1000_hw *hw)
2284 {
2285         if (e1000_enable_mng_pass_thru(hw)) {
2286                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2287                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2288
2289                 /* disable hardware interception of ARP */
2290                 manc &= ~(E1000_MANC_ARP_EN);
2291
2292                 /* enable receiving management packets to the host */
2293                 manc |= E1000_MANC_EN_MNG2HOST;
2294                 manc2h |= 1 << 5;  /* Mng Port 623 */
2295                 manc2h |= 1 << 6;  /* Mng Port 664 */
2296                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2297                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2298         }
2299 }
2300
2301 static void
2302 igb_release_manageability(struct e1000_hw *hw)
2303 {
2304         if (e1000_enable_mng_pass_thru(hw)) {
2305                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2306
2307                 manc |= E1000_MANC_ARP_EN;
2308                 manc &= ~E1000_MANC_EN_MNG2HOST;
2309
2310                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2311         }
2312 }
2313
2314 static void
2315 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2316 {
2317         struct e1000_hw *hw =
2318                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2319         uint32_t rctl;
2320
2321         rctl = E1000_READ_REG(hw, E1000_RCTL);
2322         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2323         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2324 }
2325
2326 static void
2327 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2328 {
2329         struct e1000_hw *hw =
2330                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2331         uint32_t rctl;
2332
2333         rctl = E1000_READ_REG(hw, E1000_RCTL);
2334         rctl &= (~E1000_RCTL_UPE);
2335         if (dev->data->all_multicast == 1)
2336                 rctl |= E1000_RCTL_MPE;
2337         else
2338                 rctl &= (~E1000_RCTL_MPE);
2339         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2340 }
2341
2342 static void
2343 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2344 {
2345         struct e1000_hw *hw =
2346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         uint32_t rctl;
2348
2349         rctl = E1000_READ_REG(hw, E1000_RCTL);
2350         rctl |= E1000_RCTL_MPE;
2351         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2352 }
2353
2354 static void
2355 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2356 {
2357         struct e1000_hw *hw =
2358                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359         uint32_t rctl;
2360
2361         if (dev->data->promiscuous == 1)
2362                 return; /* must remain in all_multicast mode */
2363         rctl = E1000_READ_REG(hw, E1000_RCTL);
2364         rctl &= (~E1000_RCTL_MPE);
2365         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2366 }
2367
2368 static int
2369 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2370 {
2371         struct e1000_hw *hw =
2372                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         struct e1000_vfta * shadow_vfta =
2374                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2375         uint32_t vfta;
2376         uint32_t vid_idx;
2377         uint32_t vid_bit;
2378
2379         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2380                               E1000_VFTA_ENTRY_MASK);
2381         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2382         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2383         if (on)
2384                 vfta |= vid_bit;
2385         else
2386                 vfta &= ~vid_bit;
2387         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2388
2389         /* update local VFTA copy */
2390         shadow_vfta->vfta[vid_idx] = vfta;
2391
2392         return 0;
2393 }
2394
2395 static int
2396 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2397                       enum rte_vlan_type vlan_type,
2398                       uint16_t tpid)
2399 {
2400         struct e1000_hw *hw =
2401                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2402         uint32_t reg, qinq;
2403
2404         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2405         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2406
2407         /* only outer TPID of double VLAN can be configured*/
2408         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2409                 reg = E1000_READ_REG(hw, E1000_VET);
2410                 reg = (reg & (~E1000_VET_VET_EXT)) |
2411                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2412                 E1000_WRITE_REG(hw, E1000_VET, reg);
2413
2414                 return 0;
2415         }
2416
2417         /* all other TPID values are read-only*/
2418         PMD_DRV_LOG(ERR, "Not supported");
2419
2420         return -ENOTSUP;
2421 }
2422
2423 static void
2424 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2425 {
2426         struct e1000_hw *hw =
2427                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428         uint32_t reg;
2429
2430         /* Filter Table Disable */
2431         reg = E1000_READ_REG(hw, E1000_RCTL);
2432         reg &= ~E1000_RCTL_CFIEN;
2433         reg &= ~E1000_RCTL_VFE;
2434         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2435 }
2436
2437 static void
2438 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2439 {
2440         struct e1000_hw *hw =
2441                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442         struct e1000_vfta * shadow_vfta =
2443                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2444         uint32_t reg;
2445         int i;
2446
2447         /* Filter Table Enable, CFI not used for packet acceptance */
2448         reg = E1000_READ_REG(hw, E1000_RCTL);
2449         reg &= ~E1000_RCTL_CFIEN;
2450         reg |= E1000_RCTL_VFE;
2451         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2452
2453         /* restore VFTA table */
2454         for (i = 0; i < IGB_VFTA_SIZE; i++)
2455                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2456 }
2457
2458 static void
2459 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2460 {
2461         struct e1000_hw *hw =
2462                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463         uint32_t reg;
2464
2465         /* VLAN Mode Disable */
2466         reg = E1000_READ_REG(hw, E1000_CTRL);
2467         reg &= ~E1000_CTRL_VME;
2468         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2469 }
2470
2471 static void
2472 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2473 {
2474         struct e1000_hw *hw =
2475                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         uint32_t reg;
2477
2478         /* VLAN Mode Enable */
2479         reg = E1000_READ_REG(hw, E1000_CTRL);
2480         reg |= E1000_CTRL_VME;
2481         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2482 }
2483
2484 static void
2485 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2486 {
2487         struct e1000_hw *hw =
2488                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         uint32_t reg;
2490
2491         /* CTRL_EXT: Extended VLAN */
2492         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2493         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2494         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2495
2496         /* Update maximum packet length */
2497         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2498                 E1000_WRITE_REG(hw, E1000_RLPML,
2499                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2500                                                 VLAN_TAG_SIZE);
2501 }
2502
2503 static void
2504 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2505 {
2506         struct e1000_hw *hw =
2507                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2508         uint32_t reg;
2509
2510         /* CTRL_EXT: Extended VLAN */
2511         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2512         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2513         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2514
2515         /* Update maximum packet length */
2516         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2517                 E1000_WRITE_REG(hw, E1000_RLPML,
2518                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2519                                                 2 * VLAN_TAG_SIZE);
2520 }
2521
2522 static void
2523 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2524 {
2525         if(mask & ETH_VLAN_STRIP_MASK){
2526                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2527                         igb_vlan_hw_strip_enable(dev);
2528                 else
2529                         igb_vlan_hw_strip_disable(dev);
2530         }
2531
2532         if(mask & ETH_VLAN_FILTER_MASK){
2533                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2534                         igb_vlan_hw_filter_enable(dev);
2535                 else
2536                         igb_vlan_hw_filter_disable(dev);
2537         }
2538
2539         if(mask & ETH_VLAN_EXTEND_MASK){
2540                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2541                         igb_vlan_hw_extend_enable(dev);
2542                 else
2543                         igb_vlan_hw_extend_disable(dev);
2544         }
2545 }
2546
2547
2548 /**
2549  * It enables the interrupt mask and then enable the interrupt.
2550  *
2551  * @param dev
2552  *  Pointer to struct rte_eth_dev.
2553  *
2554  * @return
2555  *  - On success, zero.
2556  *  - On failure, a negative value.
2557  */
2558 static int
2559 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2560 {
2561         struct e1000_interrupt *intr =
2562                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2563
2564         intr->mask |= E1000_ICR_LSC;
2565
2566         return 0;
2567 }
2568
2569 /* It clears the interrupt causes and enables the interrupt.
2570  * It will be called once only during nic initialized.
2571  *
2572  * @param dev
2573  *  Pointer to struct rte_eth_dev.
2574  *
2575  * @return
2576  *  - On success, zero.
2577  *  - On failure, a negative value.
2578  */
2579 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2580 {
2581         uint32_t mask, regval;
2582         struct e1000_hw *hw =
2583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         struct rte_eth_dev_info dev_info;
2585
2586         memset(&dev_info, 0, sizeof(dev_info));
2587         eth_igb_infos_get(dev, &dev_info);
2588
2589         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2590         regval = E1000_READ_REG(hw, E1000_EIMS);
2591         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2592
2593         return 0;
2594 }
2595
2596 /*
2597  * It reads ICR and gets interrupt causes, check it and set a bit flag
2598  * to update link status.
2599  *
2600  * @param dev
2601  *  Pointer to struct rte_eth_dev.
2602  *
2603  * @return
2604  *  - On success, zero.
2605  *  - On failure, a negative value.
2606  */
2607 static int
2608 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2609 {
2610         uint32_t icr;
2611         struct e1000_hw *hw =
2612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         struct e1000_interrupt *intr =
2614                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2615
2616         igb_intr_disable(hw);
2617
2618         /* read-on-clear nic registers here */
2619         icr = E1000_READ_REG(hw, E1000_ICR);
2620
2621         intr->flags = 0;
2622         if (icr & E1000_ICR_LSC) {
2623                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2624         }
2625
2626         if (icr & E1000_ICR_VMMB)
2627                 intr->flags |= E1000_FLAG_MAILBOX;
2628
2629         return 0;
2630 }
2631
2632 /*
2633  * It executes link_update after knowing an interrupt is prsent.
2634  *
2635  * @param dev
2636  *  Pointer to struct rte_eth_dev.
2637  *
2638  * @return
2639  *  - On success, zero.
2640  *  - On failure, a negative value.
2641  */
2642 static int
2643 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2644 {
2645         struct e1000_hw *hw =
2646                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct e1000_interrupt *intr =
2648                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2649         uint32_t tctl, rctl;
2650         struct rte_eth_link link;
2651         int ret;
2652
2653         if (intr->flags & E1000_FLAG_MAILBOX) {
2654                 igb_pf_mbx_process(dev);
2655                 intr->flags &= ~E1000_FLAG_MAILBOX;
2656         }
2657
2658         igb_intr_enable(dev);
2659         rte_intr_enable(&(dev->pci_dev->intr_handle));
2660
2661         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2662                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2663
2664                 /* set get_link_status to check register later */
2665                 hw->mac.get_link_status = 1;
2666                 ret = eth_igb_link_update(dev, 0);
2667
2668                 /* check if link has changed */
2669                 if (ret < 0)
2670                         return 0;
2671
2672                 memset(&link, 0, sizeof(link));
2673                 rte_igb_dev_atomic_read_link_status(dev, &link);
2674                 if (link.link_status) {
2675                         PMD_INIT_LOG(INFO,
2676                                      " Port %d: Link Up - speed %u Mbps - %s",
2677                                      dev->data->port_id,
2678                                      (unsigned)link.link_speed,
2679                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2680                                      "full-duplex" : "half-duplex");
2681                 } else {
2682                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2683                                      dev->data->port_id);
2684                 }
2685
2686                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2687                              dev->pci_dev->addr.domain,
2688                              dev->pci_dev->addr.bus,
2689                              dev->pci_dev->addr.devid,
2690                              dev->pci_dev->addr.function);
2691                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2692                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2693                 if (link.link_status) {
2694                         /* enable Tx/Rx */
2695                         tctl |= E1000_TCTL_EN;
2696                         rctl |= E1000_RCTL_EN;
2697                 } else {
2698                         /* disable Tx/Rx */
2699                         tctl &= ~E1000_TCTL_EN;
2700                         rctl &= ~E1000_RCTL_EN;
2701                 }
2702                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2703                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2704                 E1000_WRITE_FLUSH(hw);
2705                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2706         }
2707
2708         return 0;
2709 }
2710
2711 /**
2712  * Interrupt handler which shall be registered at first.
2713  *
2714  * @param handle
2715  *  Pointer to interrupt handle.
2716  * @param param
2717  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2718  *
2719  * @return
2720  *  void
2721  */
2722 static void
2723 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2724                                                         void *param)
2725 {
2726         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2727
2728         eth_igb_interrupt_get_status(dev);
2729         eth_igb_interrupt_action(dev);
2730 }
2731
2732 static int
2733 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2734 {
2735         uint32_t eicr;
2736         struct e1000_hw *hw =
2737                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct e1000_interrupt *intr =
2739                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740
2741         igbvf_intr_disable(hw);
2742
2743         /* read-on-clear nic registers here */
2744         eicr = E1000_READ_REG(hw, E1000_EICR);
2745         intr->flags = 0;
2746
2747         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2748                 intr->flags |= E1000_FLAG_MAILBOX;
2749
2750         return 0;
2751 }
2752
2753 void igbvf_mbx_process(struct rte_eth_dev *dev)
2754 {
2755         struct e1000_hw *hw =
2756                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757         struct e1000_mbx_info *mbx = &hw->mbx;
2758         u32 in_msg = 0;
2759
2760         if (mbx->ops.read(hw, &in_msg, 1, 0))
2761                 return;
2762
2763         /* PF reset VF event */
2764         if (in_msg == E1000_PF_CONTROL_MSG)
2765                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2766 }
2767
2768 static int
2769 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2770 {
2771         struct e1000_interrupt *intr =
2772                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2773
2774         if (intr->flags & E1000_FLAG_MAILBOX) {
2775                 igbvf_mbx_process(dev);
2776                 intr->flags &= ~E1000_FLAG_MAILBOX;
2777         }
2778
2779         igbvf_intr_enable(dev);
2780         rte_intr_enable(&dev->pci_dev->intr_handle);
2781
2782         return 0;
2783 }
2784
2785 static void
2786 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2787                             void *param)
2788 {
2789         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2790
2791         eth_igbvf_interrupt_get_status(dev);
2792         eth_igbvf_interrupt_action(dev);
2793 }
2794
2795 static int
2796 eth_igb_led_on(struct rte_eth_dev *dev)
2797 {
2798         struct e1000_hw *hw;
2799
2800         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2802 }
2803
2804 static int
2805 eth_igb_led_off(struct rte_eth_dev *dev)
2806 {
2807         struct e1000_hw *hw;
2808
2809         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2811 }
2812
2813 static int
2814 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2815 {
2816         struct e1000_hw *hw;
2817         uint32_t ctrl;
2818         int tx_pause;
2819         int rx_pause;
2820
2821         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822         fc_conf->pause_time = hw->fc.pause_time;
2823         fc_conf->high_water = hw->fc.high_water;
2824         fc_conf->low_water = hw->fc.low_water;
2825         fc_conf->send_xon = hw->fc.send_xon;
2826         fc_conf->autoneg = hw->mac.autoneg;
2827
2828         /*
2829          * Return rx_pause and tx_pause status according to actual setting of
2830          * the TFCE and RFCE bits in the CTRL register.
2831          */
2832         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2833         if (ctrl & E1000_CTRL_TFCE)
2834                 tx_pause = 1;
2835         else
2836                 tx_pause = 0;
2837
2838         if (ctrl & E1000_CTRL_RFCE)
2839                 rx_pause = 1;
2840         else
2841                 rx_pause = 0;
2842
2843         if (rx_pause && tx_pause)
2844                 fc_conf->mode = RTE_FC_FULL;
2845         else if (rx_pause)
2846                 fc_conf->mode = RTE_FC_RX_PAUSE;
2847         else if (tx_pause)
2848                 fc_conf->mode = RTE_FC_TX_PAUSE;
2849         else
2850                 fc_conf->mode = RTE_FC_NONE;
2851
2852         return 0;
2853 }
2854
2855 static int
2856 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2857 {
2858         struct e1000_hw *hw;
2859         int err;
2860         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2861                 e1000_fc_none,
2862                 e1000_fc_rx_pause,
2863                 e1000_fc_tx_pause,
2864                 e1000_fc_full
2865         };
2866         uint32_t rx_buf_size;
2867         uint32_t max_high_water;
2868         uint32_t rctl;
2869
2870         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         if (fc_conf->autoneg != hw->mac.autoneg)
2872                 return -ENOTSUP;
2873         rx_buf_size = igb_get_rx_buffer_size(hw);
2874         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2875
2876         /* At least reserve one Ethernet frame for watermark */
2877         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2878         if ((fc_conf->high_water > max_high_water) ||
2879             (fc_conf->high_water < fc_conf->low_water)) {
2880                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2881                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2882                 return -EINVAL;
2883         }
2884
2885         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2886         hw->fc.pause_time     = fc_conf->pause_time;
2887         hw->fc.high_water     = fc_conf->high_water;
2888         hw->fc.low_water      = fc_conf->low_water;
2889         hw->fc.send_xon       = fc_conf->send_xon;
2890
2891         err = e1000_setup_link_generic(hw);
2892         if (err == E1000_SUCCESS) {
2893
2894                 /* check if we want to forward MAC frames - driver doesn't have native
2895                  * capability to do that, so we'll write the registers ourselves */
2896
2897                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2898
2899                 /* set or clear MFLCN.PMCF bit depending on configuration */
2900                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2901                         rctl |= E1000_RCTL_PMCF;
2902                 else
2903                         rctl &= ~E1000_RCTL_PMCF;
2904
2905                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2906                 E1000_WRITE_FLUSH(hw);
2907
2908                 return 0;
2909         }
2910
2911         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2912         return -EIO;
2913 }
2914
2915 #define E1000_RAH_POOLSEL_SHIFT      (18)
2916 static void
2917 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2918                 uint32_t index, __rte_unused uint32_t pool)
2919 {
2920         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         uint32_t rah;
2922
2923         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2924         rah = E1000_READ_REG(hw, E1000_RAH(index));
2925         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2926         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2927 }
2928
2929 static void
2930 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2931 {
2932         uint8_t addr[ETHER_ADDR_LEN];
2933         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934
2935         memset(addr, 0, sizeof(addr));
2936
2937         e1000_rar_set(hw, addr, index);
2938 }
2939
2940 static void
2941 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2942                                 struct ether_addr *addr)
2943 {
2944         eth_igb_rar_clear(dev, 0);
2945
2946         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2947 }
2948 /*
2949  * Virtual Function operations
2950  */
2951 static void
2952 igbvf_intr_disable(struct e1000_hw *hw)
2953 {
2954         PMD_INIT_FUNC_TRACE();
2955
2956         /* Clear interrupt mask to stop from interrupts being generated */
2957         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2958
2959         E1000_WRITE_FLUSH(hw);
2960 }
2961
2962 static void
2963 igbvf_stop_adapter(struct rte_eth_dev *dev)
2964 {
2965         u32 reg_val;
2966         u16 i;
2967         struct rte_eth_dev_info dev_info;
2968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969
2970         memset(&dev_info, 0, sizeof(dev_info));
2971         eth_igbvf_infos_get(dev, &dev_info);
2972
2973         /* Clear interrupt mask to stop from interrupts being generated */
2974         igbvf_intr_disable(hw);
2975
2976         /* Clear any pending interrupts, flush previous writes */
2977         E1000_READ_REG(hw, E1000_EICR);
2978
2979         /* Disable the transmit unit.  Each queue must be disabled. */
2980         for (i = 0; i < dev_info.max_tx_queues; i++)
2981                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2982
2983         /* Disable the receive unit by stopping each queue */
2984         for (i = 0; i < dev_info.max_rx_queues; i++) {
2985                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2986                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2987                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2988                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2989                         ;
2990         }
2991
2992         /* flush all queues disables */
2993         E1000_WRITE_FLUSH(hw);
2994         msec_delay(2);
2995 }
2996
2997 static int eth_igbvf_link_update(struct e1000_hw *hw)
2998 {
2999         struct e1000_mbx_info *mbx = &hw->mbx;
3000         struct e1000_mac_info *mac = &hw->mac;
3001         int ret_val = E1000_SUCCESS;
3002
3003         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3004
3005         /*
3006          * We only want to run this if there has been a rst asserted.
3007          * in this case that could mean a link change, device reset,
3008          * or a virtual function reset
3009          */
3010
3011         /* If we were hit with a reset or timeout drop the link */
3012         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3013                 mac->get_link_status = TRUE;
3014
3015         if (!mac->get_link_status)
3016                 goto out;
3017
3018         /* if link status is down no point in checking to see if pf is up */
3019         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3020                 goto out;
3021
3022         /* if we passed all the tests above then the link is up and we no
3023          * longer need to check for link */
3024         mac->get_link_status = FALSE;
3025
3026 out:
3027         return ret_val;
3028 }
3029
3030
3031 static int
3032 igbvf_dev_configure(struct rte_eth_dev *dev)
3033 {
3034         struct rte_eth_conf* conf = &dev->data->dev_conf;
3035
3036         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3037                      dev->data->port_id);
3038
3039         /*
3040          * VF has no ability to enable/disable HW CRC
3041          * Keep the persistent behavior the same as Host PF
3042          */
3043 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3044         if (!conf->rxmode.hw_strip_crc) {
3045                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3046                 conf->rxmode.hw_strip_crc = 1;
3047         }
3048 #else
3049         if (conf->rxmode.hw_strip_crc) {
3050                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3051                 conf->rxmode.hw_strip_crc = 0;
3052         }
3053 #endif
3054
3055         return 0;
3056 }
3057
3058 static int
3059 igbvf_dev_start(struct rte_eth_dev *dev)
3060 {
3061         struct e1000_hw *hw =
3062                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct e1000_adapter *adapter =
3064                 E1000_DEV_PRIVATE(dev->data->dev_private);
3065         int ret;
3066         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3067         uint32_t intr_vector = 0;
3068
3069         PMD_INIT_FUNC_TRACE();
3070
3071         hw->mac.ops.reset_hw(hw);
3072         adapter->stopped = 0;
3073
3074         /* Set all vfta */
3075         igbvf_set_vfta_all(dev,1);
3076
3077         eth_igbvf_tx_init(dev);
3078
3079         /* This can fail when allocating mbufs for descriptor rings */
3080         ret = eth_igbvf_rx_init(dev);
3081         if (ret) {
3082                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3083                 igb_dev_clear_queues(dev);
3084                 return ret;
3085         }
3086
3087         /* check and configure queue intr-vector mapping */
3088         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3089                 intr_vector = dev->data->nb_rx_queues;
3090                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3091                 if (ret)
3092                         return ret;
3093         }
3094
3095         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3096                 intr_handle->intr_vec =
3097                         rte_zmalloc("intr_vec",
3098                                     dev->data->nb_rx_queues * sizeof(int), 0);
3099                 if (!intr_handle->intr_vec) {
3100                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3101                                      " intr_vec\n", dev->data->nb_rx_queues);
3102                         return -ENOMEM;
3103                 }
3104         }
3105
3106         eth_igbvf_configure_msix_intr(dev);
3107
3108         /* enable uio/vfio intr/eventfd mapping */
3109         rte_intr_enable(intr_handle);
3110
3111         /* resume enabled intr since hw reset */
3112         igbvf_intr_enable(dev);
3113
3114         return 0;
3115 }
3116
3117 static void
3118 igbvf_dev_stop(struct rte_eth_dev *dev)
3119 {
3120         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3121
3122         PMD_INIT_FUNC_TRACE();
3123
3124         igbvf_stop_adapter(dev);
3125
3126         /*
3127           * Clear what we set, but we still keep shadow_vfta to
3128           * restore after device starts
3129           */
3130         igbvf_set_vfta_all(dev,0);
3131
3132         igb_dev_clear_queues(dev);
3133
3134         /* disable intr eventfd mapping */
3135         rte_intr_disable(intr_handle);
3136
3137         /* Clean datapath event and queue/vec mapping */
3138         rte_intr_efd_disable(intr_handle);
3139         if (intr_handle->intr_vec) {
3140                 rte_free(intr_handle->intr_vec);
3141                 intr_handle->intr_vec = NULL;
3142         }
3143 }
3144
3145 static void
3146 igbvf_dev_close(struct rte_eth_dev *dev)
3147 {
3148         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3149         struct e1000_adapter *adapter =
3150                 E1000_DEV_PRIVATE(dev->data->dev_private);
3151         struct ether_addr addr;
3152
3153         PMD_INIT_FUNC_TRACE();
3154
3155         e1000_reset_hw(hw);
3156
3157         igbvf_dev_stop(dev);
3158         adapter->stopped = 1;
3159         igb_dev_free_queues(dev);
3160
3161         /**
3162          * reprogram the RAR with a zero mac address,
3163          * to ensure that the VF traffic goes to the PF
3164          * after stop, close and detach of the VF.
3165          **/
3166
3167         memset(&addr, 0, sizeof(addr));
3168         igbvf_default_mac_addr_set(dev, &addr);
3169 }
3170
3171 static void
3172 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3173 {
3174         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175
3176         /* Set both unicast and multicast promisc */
3177         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3178 }
3179
3180 static void
3181 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3182 {
3183         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184
3185         /* If in allmulticast mode leave multicast promisc */
3186         if (dev->data->all_multicast == 1)
3187                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3188         else
3189                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3190 }
3191
3192 static void
3193 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3194 {
3195         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3196
3197         /* In promiscuous mode multicast promisc already set */
3198         if (dev->data->promiscuous == 0)
3199                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3200 }
3201
3202 static void
3203 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3204 {
3205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206
3207         /* In promiscuous mode leave multicast promisc enabled */
3208         if (dev->data->promiscuous == 0)
3209                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3210 }
3211
3212 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3213 {
3214         struct e1000_mbx_info *mbx = &hw->mbx;
3215         uint32_t msgbuf[2];
3216         s32 err;
3217
3218         /* After set vlan, vlan strip will also be enabled in igb driver*/
3219         msgbuf[0] = E1000_VF_SET_VLAN;
3220         msgbuf[1] = vid;
3221         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3222         if (on)
3223                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3224
3225         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3226         if (err)
3227                 goto mbx_err;
3228
3229         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3230         if (err)
3231                 goto mbx_err;
3232
3233         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3234         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3235                 err = -EINVAL;
3236
3237 mbx_err:
3238         return err;
3239 }
3240
3241 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3242 {
3243         struct e1000_hw *hw =
3244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3245         struct e1000_vfta * shadow_vfta =
3246                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3247         int i = 0, j = 0, vfta = 0, mask = 1;
3248
3249         for (i = 0; i < IGB_VFTA_SIZE; i++){
3250                 vfta = shadow_vfta->vfta[i];
3251                 if(vfta){
3252                         mask = 1;
3253                         for (j = 0; j < 32; j++){
3254                                 if(vfta & mask)
3255                                         igbvf_set_vfta(hw,
3256                                                 (uint16_t)((i<<5)+j), on);
3257                                 mask<<=1;
3258                         }
3259                 }
3260         }
3261
3262 }
3263
3264 static int
3265 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3266 {
3267         struct e1000_hw *hw =
3268                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct e1000_vfta * shadow_vfta =
3270                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3271         uint32_t vid_idx = 0;
3272         uint32_t vid_bit = 0;
3273         int ret = 0;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3278         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3279         if(ret){
3280                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3281                 return ret;
3282         }
3283         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3284         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3285
3286         /*Save what we set and retore it after device reset*/
3287         if (on)
3288                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3289         else
3290                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3291
3292         return 0;
3293 }
3294
3295 static void
3296 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3297 {
3298         struct e1000_hw *hw =
3299                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300
3301         /* index is not used by rar_set() */
3302         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3303 }
3304
3305
3306 static int
3307 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3308                         struct rte_eth_rss_reta_entry64 *reta_conf,
3309                         uint16_t reta_size)
3310 {
3311         uint8_t i, j, mask;
3312         uint32_t reta, r;
3313         uint16_t idx, shift;
3314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3315
3316         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3317                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3318                         "(%d) doesn't match the number hardware can supported "
3319                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3320                 return -EINVAL;
3321         }
3322
3323         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3324                 idx = i / RTE_RETA_GROUP_SIZE;
3325                 shift = i % RTE_RETA_GROUP_SIZE;
3326                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3327                                                 IGB_4_BIT_MASK);
3328                 if (!mask)
3329                         continue;
3330                 if (mask == IGB_4_BIT_MASK)
3331                         r = 0;
3332                 else
3333                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3334                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3335                         if (mask & (0x1 << j))
3336                                 reta |= reta_conf[idx].reta[shift + j] <<
3337                                                         (CHAR_BIT * j);
3338                         else
3339                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3340                 }
3341                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3342         }
3343
3344         return 0;
3345 }
3346
3347 static int
3348 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3349                        struct rte_eth_rss_reta_entry64 *reta_conf,
3350                        uint16_t reta_size)
3351 {
3352         uint8_t i, j, mask;
3353         uint32_t reta;
3354         uint16_t idx, shift;
3355         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356
3357         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3358                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3359                         "(%d) doesn't match the number hardware can supported "
3360                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3361                 return -EINVAL;
3362         }
3363
3364         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3365                 idx = i / RTE_RETA_GROUP_SIZE;
3366                 shift = i % RTE_RETA_GROUP_SIZE;
3367                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3368                                                 IGB_4_BIT_MASK);
3369                 if (!mask)
3370                         continue;
3371                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3372                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3373                         if (mask & (0x1 << j))
3374                                 reta_conf[idx].reta[shift + j] =
3375                                         ((reta >> (CHAR_BIT * j)) &
3376                                                 IGB_8_BIT_MASK);
3377                 }
3378         }
3379
3380         return 0;
3381 }
3382
3383 #define MAC_TYPE_FILTER_SUP(type)    do {\
3384         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3385                 (type) != e1000_82576)\
3386                 return -ENOTSUP;\
3387 } while (0)
3388
3389 static int
3390 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3391                         struct rte_eth_syn_filter *filter,
3392                         bool add)
3393 {
3394         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395         uint32_t synqf, rfctl;
3396
3397         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3398                 return -EINVAL;
3399
3400         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3401
3402         if (add) {
3403                 if (synqf & E1000_SYN_FILTER_ENABLE)
3404                         return -EINVAL;
3405
3406                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3407                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3408
3409                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3410                 if (filter->hig_pri)
3411                         rfctl |= E1000_RFCTL_SYNQFP;
3412                 else
3413                         rfctl &= ~E1000_RFCTL_SYNQFP;
3414
3415                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3416         } else {
3417                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3418                         return -ENOENT;
3419                 synqf = 0;
3420         }
3421
3422         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3423         E1000_WRITE_FLUSH(hw);
3424         return 0;
3425 }
3426
3427 static int
3428 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3429                         struct rte_eth_syn_filter *filter)
3430 {
3431         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432         uint32_t synqf, rfctl;
3433
3434         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3435         if (synqf & E1000_SYN_FILTER_ENABLE) {
3436                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3437                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3438                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3439                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3440                 return 0;
3441         }
3442
3443         return -ENOENT;
3444 }
3445
3446 static int
3447 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3448                         enum rte_filter_op filter_op,
3449                         void *arg)
3450 {
3451         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452         int ret;
3453
3454         MAC_TYPE_FILTER_SUP(hw->mac.type);
3455
3456         if (filter_op == RTE_ETH_FILTER_NOP)
3457                 return 0;
3458
3459         if (arg == NULL) {
3460                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3461                             filter_op);
3462                 return -EINVAL;
3463         }
3464
3465         switch (filter_op) {
3466         case RTE_ETH_FILTER_ADD:
3467                 ret = eth_igb_syn_filter_set(dev,
3468                                 (struct rte_eth_syn_filter *)arg,
3469                                 TRUE);
3470                 break;
3471         case RTE_ETH_FILTER_DELETE:
3472                 ret = eth_igb_syn_filter_set(dev,
3473                                 (struct rte_eth_syn_filter *)arg,
3474                                 FALSE);
3475                 break;
3476         case RTE_ETH_FILTER_GET:
3477                 ret = eth_igb_syn_filter_get(dev,
3478                                 (struct rte_eth_syn_filter *)arg);
3479                 break;
3480         default:
3481                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3482                 ret = -EINVAL;
3483                 break;
3484         }
3485
3486         return ret;
3487 }
3488
3489 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3490         if ((type) != e1000_82580 && (type) != e1000_i350)\
3491                 return -ENOSYS; \
3492 } while (0)
3493
3494 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3495 static inline int
3496 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3497                         struct e1000_2tuple_filter_info *filter_info)
3498 {
3499         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3500                 return -EINVAL;
3501         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3502                 return -EINVAL;  /* filter index is out of range. */
3503         if (filter->tcp_flags > TCP_FLAG_ALL)
3504                 return -EINVAL;  /* flags is invalid. */
3505
3506         switch (filter->dst_port_mask) {
3507         case UINT16_MAX:
3508                 filter_info->dst_port_mask = 0;
3509                 filter_info->dst_port = filter->dst_port;
3510                 break;
3511         case 0:
3512                 filter_info->dst_port_mask = 1;
3513                 break;
3514         default:
3515                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3516                 return -EINVAL;
3517         }
3518
3519         switch (filter->proto_mask) {
3520         case UINT8_MAX:
3521                 filter_info->proto_mask = 0;
3522                 filter_info->proto = filter->proto;
3523                 break;
3524         case 0:
3525                 filter_info->proto_mask = 1;
3526                 break;
3527         default:
3528                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3529                 return -EINVAL;
3530         }
3531
3532         filter_info->priority = (uint8_t)filter->priority;
3533         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3534                 filter_info->tcp_flags = filter->tcp_flags;
3535         else
3536                 filter_info->tcp_flags = 0;
3537
3538         return 0;
3539 }
3540
3541 static inline struct e1000_2tuple_filter *
3542 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3543                         struct e1000_2tuple_filter_info *key)
3544 {
3545         struct e1000_2tuple_filter *it;
3546
3547         TAILQ_FOREACH(it, filter_list, entries) {
3548                 if (memcmp(key, &it->filter_info,
3549                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3550                         return it;
3551                 }
3552         }
3553         return NULL;
3554 }
3555
3556 /*
3557  * igb_add_2tuple_filter - add a 2tuple filter
3558  *
3559  * @param
3560  * dev: Pointer to struct rte_eth_dev.
3561  * ntuple_filter: ponter to the filter that will be added.
3562  *
3563  * @return
3564  *    - On success, zero.
3565  *    - On failure, a negative value.
3566  */
3567 static int
3568 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3569                         struct rte_eth_ntuple_filter *ntuple_filter)
3570 {
3571         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3572         struct e1000_filter_info *filter_info =
3573                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3574         struct e1000_2tuple_filter *filter;
3575         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3576         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3577         int i, ret;
3578
3579         filter = rte_zmalloc("e1000_2tuple_filter",
3580                         sizeof(struct e1000_2tuple_filter), 0);
3581         if (filter == NULL)
3582                 return -ENOMEM;
3583
3584         ret = ntuple_filter_to_2tuple(ntuple_filter,
3585                                       &filter->filter_info);
3586         if (ret < 0) {
3587                 rte_free(filter);
3588                 return ret;
3589         }
3590         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3591                                          &filter->filter_info) != NULL) {
3592                 PMD_DRV_LOG(ERR, "filter exists.");
3593                 rte_free(filter);
3594                 return -EEXIST;
3595         }
3596         filter->queue = ntuple_filter->queue;
3597
3598         /*
3599          * look for an unused 2tuple filter index,
3600          * and insert the filter to list.
3601          */
3602         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3603                 if (!(filter_info->twotuple_mask & (1 << i))) {
3604                         filter_info->twotuple_mask |= 1 << i;
3605                         filter->index = i;
3606                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3607                                           filter,
3608                                           entries);
3609                         break;
3610                 }
3611         }
3612         if (i >= E1000_MAX_TTQF_FILTERS) {
3613                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3614                 rte_free(filter);
3615                 return -ENOSYS;
3616         }
3617
3618         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3619         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3620                 imir |= E1000_IMIR_PORT_BP;
3621         else
3622                 imir &= ~E1000_IMIR_PORT_BP;
3623
3624         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3625
3626         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3627         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3628         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3629         if (filter->filter_info.proto_mask == 0)
3630                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3631
3632         /* tcp flags bits setting. */
3633         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3634                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3635                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3636                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3637                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3638                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3639                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3640                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3641                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3642                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3643                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3644                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3645                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3646         } else
3647                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3648         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3649         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3650         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3651         return 0;
3652 }
3653
3654 /*
3655  * igb_remove_2tuple_filter - remove a 2tuple filter
3656  *
3657  * @param
3658  * dev: Pointer to struct rte_eth_dev.
3659  * ntuple_filter: ponter to the filter that will be removed.
3660  *
3661  * @return
3662  *    - On success, zero.
3663  *    - On failure, a negative value.
3664  */
3665 static int
3666 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3667                         struct rte_eth_ntuple_filter *ntuple_filter)
3668 {
3669         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3670         struct e1000_filter_info *filter_info =
3671                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3672         struct e1000_2tuple_filter_info filter_2tuple;
3673         struct e1000_2tuple_filter *filter;
3674         int ret;
3675
3676         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3677         ret = ntuple_filter_to_2tuple(ntuple_filter,
3678                                       &filter_2tuple);
3679         if (ret < 0)
3680                 return ret;
3681
3682         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3683                                          &filter_2tuple);
3684         if (filter == NULL) {
3685                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3686                 return -ENOENT;
3687         }
3688
3689         filter_info->twotuple_mask &= ~(1 << filter->index);
3690         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3691         rte_free(filter);
3692
3693         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3694         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3695         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3696         return 0;
3697 }
3698
3699 static inline struct e1000_flex_filter *
3700 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3701                         struct e1000_flex_filter_info *key)
3702 {
3703         struct e1000_flex_filter *it;
3704
3705         TAILQ_FOREACH(it, filter_list, entries) {
3706                 if (memcmp(key, &it->filter_info,
3707                         sizeof(struct e1000_flex_filter_info)) == 0)
3708                         return it;
3709         }
3710
3711         return NULL;
3712 }
3713
3714 static int
3715 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3716                         struct rte_eth_flex_filter *filter,
3717                         bool add)
3718 {
3719         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720         struct e1000_filter_info *filter_info =
3721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3722         struct e1000_flex_filter *flex_filter, *it;
3723         uint32_t wufc, queueing, mask;
3724         uint32_t reg_off;
3725         uint8_t shift, i, j = 0;
3726
3727         flex_filter = rte_zmalloc("e1000_flex_filter",
3728                         sizeof(struct e1000_flex_filter), 0);
3729         if (flex_filter == NULL)
3730                 return -ENOMEM;
3731
3732         flex_filter->filter_info.len = filter->len;
3733         flex_filter->filter_info.priority = filter->priority;
3734         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3735         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3736                 mask = 0;
3737                 /* reverse bits in flex filter's mask*/
3738                 for (shift = 0; shift < CHAR_BIT; shift++) {
3739                         if (filter->mask[i] & (0x01 << shift))
3740                                 mask |= (0x80 >> shift);
3741                 }
3742                 flex_filter->filter_info.mask[i] = mask;
3743         }
3744
3745         wufc = E1000_READ_REG(hw, E1000_WUFC);
3746         if (flex_filter->index < E1000_MAX_FHFT)
3747                 reg_off = E1000_FHFT(flex_filter->index);
3748         else
3749                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3750
3751         if (add) {
3752                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3753                                 &flex_filter->filter_info) != NULL) {
3754                         PMD_DRV_LOG(ERR, "filter exists.");
3755                         rte_free(flex_filter);
3756                         return -EEXIST;
3757                 }
3758                 flex_filter->queue = filter->queue;
3759                 /*
3760                  * look for an unused flex filter index
3761                  * and insert the filter into the list.
3762                  */
3763                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3764                         if (!(filter_info->flex_mask & (1 << i))) {
3765                                 filter_info->flex_mask |= 1 << i;
3766                                 flex_filter->index = i;
3767                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3768                                         flex_filter,
3769                                         entries);
3770                                 break;
3771                         }
3772                 }
3773                 if (i >= E1000_MAX_FLEX_FILTERS) {
3774                         PMD_DRV_LOG(ERR, "flex filters are full.");
3775                         rte_free(flex_filter);
3776                         return -ENOSYS;
3777                 }
3778
3779                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3780                                 (E1000_WUFC_FLX0 << flex_filter->index));
3781                 queueing = filter->len |
3782                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3783                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3784                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3785                                 queueing);
3786                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3787                         E1000_WRITE_REG(hw, reg_off,
3788                                         flex_filter->filter_info.dwords[j]);
3789                         reg_off += sizeof(uint32_t);
3790                         E1000_WRITE_REG(hw, reg_off,
3791                                         flex_filter->filter_info.dwords[++j]);
3792                         reg_off += sizeof(uint32_t);
3793                         E1000_WRITE_REG(hw, reg_off,
3794                                 (uint32_t)flex_filter->filter_info.mask[i]);
3795                         reg_off += sizeof(uint32_t) * 2;
3796                         ++j;
3797                 }
3798         } else {
3799                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3800                                 &flex_filter->filter_info);
3801                 if (it == NULL) {
3802                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3803                         rte_free(flex_filter);
3804                         return -ENOENT;
3805                 }
3806
3807                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3808                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3809                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3810                         (~(E1000_WUFC_FLX0 << it->index)));
3811
3812                 filter_info->flex_mask &= ~(1 << it->index);
3813                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3814                 rte_free(it);
3815                 rte_free(flex_filter);
3816         }
3817
3818         return 0;
3819 }
3820
3821 static int
3822 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3823                         struct rte_eth_flex_filter *filter)
3824 {
3825         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826         struct e1000_filter_info *filter_info =
3827                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3828         struct e1000_flex_filter flex_filter, *it;
3829         uint32_t wufc, queueing, wufc_en = 0;
3830
3831         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3832         flex_filter.filter_info.len = filter->len;
3833         flex_filter.filter_info.priority = filter->priority;
3834         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3835         memcpy(flex_filter.filter_info.mask, filter->mask,
3836                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3837
3838         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3839                                 &flex_filter.filter_info);
3840         if (it == NULL) {
3841                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3842                 return -ENOENT;
3843         }
3844
3845         wufc = E1000_READ_REG(hw, E1000_WUFC);
3846         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3847
3848         if ((wufc & wufc_en) == wufc_en) {
3849                 uint32_t reg_off = 0;
3850                 if (it->index < E1000_MAX_FHFT)
3851                         reg_off = E1000_FHFT(it->index);
3852                 else
3853                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3854
3855                 queueing = E1000_READ_REG(hw,
3856                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3857                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3858                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3859                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3860                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3861                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3862                 return 0;
3863         }
3864         return -ENOENT;
3865 }
3866
3867 static int
3868 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3869                         enum rte_filter_op filter_op,
3870                         void *arg)
3871 {
3872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         struct rte_eth_flex_filter *filter;
3874         int ret = 0;
3875
3876         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3877
3878         if (filter_op == RTE_ETH_FILTER_NOP)
3879                 return ret;
3880
3881         if (arg == NULL) {
3882                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3883                             filter_op);
3884                 return -EINVAL;
3885         }
3886
3887         filter = (struct rte_eth_flex_filter *)arg;
3888         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3889             || filter->len % sizeof(uint64_t) != 0) {
3890                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3891                 return -EINVAL;
3892         }
3893         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3894                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3895                 return -EINVAL;
3896         }
3897
3898         switch (filter_op) {
3899         case RTE_ETH_FILTER_ADD:
3900                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3901                 break;
3902         case RTE_ETH_FILTER_DELETE:
3903                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3904                 break;
3905         case RTE_ETH_FILTER_GET:
3906                 ret = eth_igb_get_flex_filter(dev, filter);
3907                 break;
3908         default:
3909                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3910                 ret = -EINVAL;
3911                 break;
3912         }
3913
3914         return ret;
3915 }
3916
3917 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3918 static inline int
3919 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3920                         struct e1000_5tuple_filter_info *filter_info)
3921 {
3922         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3923                 return -EINVAL;
3924         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3925                 return -EINVAL;  /* filter index is out of range. */
3926         if (filter->tcp_flags > TCP_FLAG_ALL)
3927                 return -EINVAL;  /* flags is invalid. */
3928
3929         switch (filter->dst_ip_mask) {
3930         case UINT32_MAX:
3931                 filter_info->dst_ip_mask = 0;
3932                 filter_info->dst_ip = filter->dst_ip;
3933                 break;
3934         case 0:
3935                 filter_info->dst_ip_mask = 1;
3936                 break;
3937         default:
3938                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3939                 return -EINVAL;
3940         }
3941
3942         switch (filter->src_ip_mask) {
3943         case UINT32_MAX:
3944                 filter_info->src_ip_mask = 0;
3945                 filter_info->src_ip = filter->src_ip;
3946                 break;
3947         case 0:
3948                 filter_info->src_ip_mask = 1;
3949                 break;
3950         default:
3951                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3952                 return -EINVAL;
3953         }
3954
3955         switch (filter->dst_port_mask) {
3956         case UINT16_MAX:
3957                 filter_info->dst_port_mask = 0;
3958                 filter_info->dst_port = filter->dst_port;
3959                 break;
3960         case 0:
3961                 filter_info->dst_port_mask = 1;
3962                 break;
3963         default:
3964                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3965                 return -EINVAL;
3966         }
3967
3968         switch (filter->src_port_mask) {
3969         case UINT16_MAX:
3970                 filter_info->src_port_mask = 0;
3971                 filter_info->src_port = filter->src_port;
3972                 break;
3973         case 0:
3974                 filter_info->src_port_mask = 1;
3975                 break;
3976         default:
3977                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3978                 return -EINVAL;
3979         }
3980
3981         switch (filter->proto_mask) {
3982         case UINT8_MAX:
3983                 filter_info->proto_mask = 0;
3984                 filter_info->proto = filter->proto;
3985                 break;
3986         case 0:
3987                 filter_info->proto_mask = 1;
3988                 break;
3989         default:
3990                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3991                 return -EINVAL;
3992         }
3993
3994         filter_info->priority = (uint8_t)filter->priority;
3995         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3996                 filter_info->tcp_flags = filter->tcp_flags;
3997         else
3998                 filter_info->tcp_flags = 0;
3999
4000         return 0;
4001 }
4002
4003 static inline struct e1000_5tuple_filter *
4004 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4005                         struct e1000_5tuple_filter_info *key)
4006 {
4007         struct e1000_5tuple_filter *it;
4008
4009         TAILQ_FOREACH(it, filter_list, entries) {
4010                 if (memcmp(key, &it->filter_info,
4011                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4012                         return it;
4013                 }
4014         }
4015         return NULL;
4016 }
4017
4018 /*
4019  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4020  *
4021  * @param
4022  * dev: Pointer to struct rte_eth_dev.
4023  * ntuple_filter: ponter to the filter that will be added.
4024  *
4025  * @return
4026  *    - On success, zero.
4027  *    - On failure, a negative value.
4028  */
4029 static int
4030 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4031                         struct rte_eth_ntuple_filter *ntuple_filter)
4032 {
4033         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034         struct e1000_filter_info *filter_info =
4035                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4036         struct e1000_5tuple_filter *filter;
4037         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4038         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4039         uint8_t i;
4040         int ret;
4041
4042         filter = rte_zmalloc("e1000_5tuple_filter",
4043                         sizeof(struct e1000_5tuple_filter), 0);
4044         if (filter == NULL)
4045                 return -ENOMEM;
4046
4047         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4048                                             &filter->filter_info);
4049         if (ret < 0) {
4050                 rte_free(filter);
4051                 return ret;
4052         }
4053
4054         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4055                                          &filter->filter_info) != NULL) {
4056                 PMD_DRV_LOG(ERR, "filter exists.");
4057                 rte_free(filter);
4058                 return -EEXIST;
4059         }
4060         filter->queue = ntuple_filter->queue;
4061
4062         /*
4063          * look for an unused 5tuple filter index,
4064          * and insert the filter to list.
4065          */
4066         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4067                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4068                         filter_info->fivetuple_mask |= 1 << i;
4069                         filter->index = i;
4070                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4071                                           filter,
4072                                           entries);
4073                         break;
4074                 }
4075         }
4076         if (i >= E1000_MAX_FTQF_FILTERS) {
4077                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4078                 rte_free(filter);
4079                 return -ENOSYS;
4080         }
4081
4082         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4083         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4084                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4085         if (filter->filter_info.dst_ip_mask == 0)
4086                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4087         if (filter->filter_info.src_port_mask == 0)
4088                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4089         if (filter->filter_info.proto_mask == 0)
4090                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4091         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4092                 E1000_FTQF_QUEUE_MASK;
4093         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4094         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4095         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4096         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4097
4098         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4099         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4100
4101         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4102         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4103                 imir |= E1000_IMIR_PORT_BP;
4104         else
4105                 imir &= ~E1000_IMIR_PORT_BP;
4106         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4107
4108         /* tcp flags bits setting. */
4109         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4110                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4111                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4112                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4113                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4114                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4115                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4116                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4117                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4118                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4119                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4120                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4121                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4122         } else
4123                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4124         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4125         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4126         return 0;
4127 }
4128
4129 /*
4130  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4131  *
4132  * @param
4133  * dev: Pointer to struct rte_eth_dev.
4134  * ntuple_filter: ponter to the filter that will be removed.
4135  *
4136  * @return
4137  *    - On success, zero.
4138  *    - On failure, a negative value.
4139  */
4140 static int
4141 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4142                                 struct rte_eth_ntuple_filter *ntuple_filter)
4143 {
4144         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct e1000_filter_info *filter_info =
4146                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4147         struct e1000_5tuple_filter_info filter_5tuple;
4148         struct e1000_5tuple_filter *filter;
4149         int ret;
4150
4151         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4152         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4153                                             &filter_5tuple);
4154         if (ret < 0)
4155                 return ret;
4156
4157         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4158                                          &filter_5tuple);
4159         if (filter == NULL) {
4160                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4161                 return -ENOENT;
4162         }
4163
4164         filter_info->fivetuple_mask &= ~(1 << filter->index);
4165         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4166         rte_free(filter);
4167
4168         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4169                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4170         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4171         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4172         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4173         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4174         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4175         return 0;
4176 }
4177
4178 static int
4179 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4180 {
4181         uint32_t rctl;
4182         struct e1000_hw *hw;
4183         struct rte_eth_dev_info dev_info;
4184         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4185                                      VLAN_TAG_SIZE);
4186
4187         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188
4189 #ifdef RTE_LIBRTE_82571_SUPPORT
4190         /* XXX: not bigger than max_rx_pktlen */
4191         if (hw->mac.type == e1000_82571)
4192                 return -ENOTSUP;
4193 #endif
4194         eth_igb_infos_get(dev, &dev_info);
4195
4196         /* check that mtu is within the allowed range */
4197         if ((mtu < ETHER_MIN_MTU) ||
4198             (frame_size > dev_info.max_rx_pktlen))
4199                 return -EINVAL;
4200
4201         /* refuse mtu that requires the support of scattered packets when this
4202          * feature has not been enabled before. */
4203         if (!dev->data->scattered_rx &&
4204             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4205                 return -EINVAL;
4206
4207         rctl = E1000_READ_REG(hw, E1000_RCTL);
4208
4209         /* switch to jumbo mode if needed */
4210         if (frame_size > ETHER_MAX_LEN) {
4211                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4212                 rctl |= E1000_RCTL_LPE;
4213         } else {
4214                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4215                 rctl &= ~E1000_RCTL_LPE;
4216         }
4217         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4218
4219         /* update max frame size */
4220         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4221
4222         E1000_WRITE_REG(hw, E1000_RLPML,
4223                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4224
4225         return 0;
4226 }
4227
4228 /*
4229  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4230  *
4231  * @param
4232  * dev: Pointer to struct rte_eth_dev.
4233  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4234  * add: if true, add filter, if false, remove filter
4235  *
4236  * @return
4237  *    - On success, zero.
4238  *    - On failure, a negative value.
4239  */
4240 static int
4241 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4242                         struct rte_eth_ntuple_filter *ntuple_filter,
4243                         bool add)
4244 {
4245         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4246         int ret;
4247
4248         switch (ntuple_filter->flags) {
4249         case RTE_5TUPLE_FLAGS:
4250         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4251                 if (hw->mac.type != e1000_82576)
4252                         return -ENOTSUP;
4253                 if (add)
4254                         ret = igb_add_5tuple_filter_82576(dev,
4255                                                           ntuple_filter);
4256                 else
4257                         ret = igb_remove_5tuple_filter_82576(dev,
4258                                                              ntuple_filter);
4259                 break;
4260         case RTE_2TUPLE_FLAGS:
4261         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4262                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4263                         return -ENOTSUP;
4264                 if (add)
4265                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4266                 else
4267                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4268                 break;
4269         default:
4270                 ret = -EINVAL;
4271                 break;
4272         }
4273
4274         return ret;
4275 }
4276
4277 /*
4278  * igb_get_ntuple_filter - get a ntuple filter
4279  *
4280  * @param
4281  * dev: Pointer to struct rte_eth_dev.
4282  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4283  *
4284  * @return
4285  *    - On success, zero.
4286  *    - On failure, a negative value.
4287  */
4288 static int
4289 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4290                         struct rte_eth_ntuple_filter *ntuple_filter)
4291 {
4292         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293         struct e1000_filter_info *filter_info =
4294                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4295         struct e1000_5tuple_filter_info filter_5tuple;
4296         struct e1000_2tuple_filter_info filter_2tuple;
4297         struct e1000_5tuple_filter *p_5tuple_filter;
4298         struct e1000_2tuple_filter *p_2tuple_filter;
4299         int ret;
4300
4301         switch (ntuple_filter->flags) {
4302         case RTE_5TUPLE_FLAGS:
4303         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4304                 if (hw->mac.type != e1000_82576)
4305                         return -ENOTSUP;
4306                 memset(&filter_5tuple,
4307                         0,
4308                         sizeof(struct e1000_5tuple_filter_info));
4309                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4310                                                     &filter_5tuple);
4311                 if (ret < 0)
4312                         return ret;
4313                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4314                                         &filter_info->fivetuple_list,
4315                                         &filter_5tuple);
4316                 if (p_5tuple_filter == NULL) {
4317                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4318                         return -ENOENT;
4319                 }
4320                 ntuple_filter->queue = p_5tuple_filter->queue;
4321                 break;
4322         case RTE_2TUPLE_FLAGS:
4323         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4324                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4325                         return -ENOTSUP;
4326                 memset(&filter_2tuple,
4327                         0,
4328                         sizeof(struct e1000_2tuple_filter_info));
4329                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4330                 if (ret < 0)
4331                         return ret;
4332                 p_2tuple_filter = igb_2tuple_filter_lookup(
4333                                         &filter_info->twotuple_list,
4334                                         &filter_2tuple);
4335                 if (p_2tuple_filter == NULL) {
4336                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4337                         return -ENOENT;
4338                 }
4339                 ntuple_filter->queue = p_2tuple_filter->queue;
4340                 break;
4341         default:
4342                 ret = -EINVAL;
4343                 break;
4344         }
4345
4346         return 0;
4347 }
4348
4349 /*
4350  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4351  * @dev: pointer to rte_eth_dev structure
4352  * @filter_op:operation will be taken.
4353  * @arg: a pointer to specific structure corresponding to the filter_op
4354  */
4355 static int
4356 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4357                                 enum rte_filter_op filter_op,
4358                                 void *arg)
4359 {
4360         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         int ret;
4362
4363         MAC_TYPE_FILTER_SUP(hw->mac.type);
4364
4365         if (filter_op == RTE_ETH_FILTER_NOP)
4366                 return 0;
4367
4368         if (arg == NULL) {
4369                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4370                             filter_op);
4371                 return -EINVAL;
4372         }
4373
4374         switch (filter_op) {
4375         case RTE_ETH_FILTER_ADD:
4376                 ret = igb_add_del_ntuple_filter(dev,
4377                         (struct rte_eth_ntuple_filter *)arg,
4378                         TRUE);
4379                 break;
4380         case RTE_ETH_FILTER_DELETE:
4381                 ret = igb_add_del_ntuple_filter(dev,
4382                         (struct rte_eth_ntuple_filter *)arg,
4383                         FALSE);
4384                 break;
4385         case RTE_ETH_FILTER_GET:
4386                 ret = igb_get_ntuple_filter(dev,
4387                         (struct rte_eth_ntuple_filter *)arg);
4388                 break;
4389         default:
4390                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4391                 ret = -EINVAL;
4392                 break;
4393         }
4394         return ret;
4395 }
4396
4397 static inline int
4398 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4399                         uint16_t ethertype)
4400 {
4401         int i;
4402
4403         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4404                 if (filter_info->ethertype_filters[i] == ethertype &&
4405                     (filter_info->ethertype_mask & (1 << i)))
4406                         return i;
4407         }
4408         return -1;
4409 }
4410
4411 static inline int
4412 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4413                         uint16_t ethertype)
4414 {
4415         int i;
4416
4417         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4418                 if (!(filter_info->ethertype_mask & (1 << i))) {
4419                         filter_info->ethertype_mask |= 1 << i;
4420                         filter_info->ethertype_filters[i] = ethertype;
4421                         return i;
4422                 }
4423         }
4424         return -1;
4425 }
4426
4427 static inline int
4428 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4429                         uint8_t idx)
4430 {
4431         if (idx >= E1000_MAX_ETQF_FILTERS)
4432                 return -1;
4433         filter_info->ethertype_mask &= ~(1 << idx);
4434         filter_info->ethertype_filters[idx] = 0;
4435         return idx;
4436 }
4437
4438
4439 static int
4440 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4441                         struct rte_eth_ethertype_filter *filter,
4442                         bool add)
4443 {
4444         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445         struct e1000_filter_info *filter_info =
4446                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4447         uint32_t etqf = 0;
4448         int ret;
4449
4450         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4451                 filter->ether_type == ETHER_TYPE_IPv6) {
4452                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4453                         " ethertype filter.", filter->ether_type);
4454                 return -EINVAL;
4455         }
4456
4457         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4458                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4459                 return -EINVAL;
4460         }
4461         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4462                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4463                 return -EINVAL;
4464         }
4465
4466         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4467         if (ret >= 0 && add) {
4468                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4469                             filter->ether_type);
4470                 return -EEXIST;
4471         }
4472         if (ret < 0 && !add) {
4473                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4474                             filter->ether_type);
4475                 return -ENOENT;
4476         }
4477
4478         if (add) {
4479                 ret = igb_ethertype_filter_insert(filter_info,
4480                         filter->ether_type);
4481                 if (ret < 0) {
4482                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4483                         return -ENOSYS;
4484                 }
4485
4486                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4487                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4488                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4489         } else {
4490                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4491                 if (ret < 0)
4492                         return -ENOSYS;
4493         }
4494         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4495         E1000_WRITE_FLUSH(hw);
4496
4497         return 0;
4498 }
4499
4500 static int
4501 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4502                         struct rte_eth_ethertype_filter *filter)
4503 {
4504         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct e1000_filter_info *filter_info =
4506                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4507         uint32_t etqf;
4508         int ret;
4509
4510         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4511         if (ret < 0) {
4512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4513                             filter->ether_type);
4514                 return -ENOENT;
4515         }
4516
4517         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4518         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4519                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4520                 filter->flags = 0;
4521                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4522                                 E1000_ETQF_QUEUE_SHIFT;
4523                 return 0;
4524         }
4525
4526         return -ENOENT;
4527 }
4528
4529 /*
4530  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4531  * @dev: pointer to rte_eth_dev structure
4532  * @filter_op:operation will be taken.
4533  * @arg: a pointer to specific structure corresponding to the filter_op
4534  */
4535 static int
4536 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4537                                 enum rte_filter_op filter_op,
4538                                 void *arg)
4539 {
4540         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4541         int ret;
4542
4543         MAC_TYPE_FILTER_SUP(hw->mac.type);
4544
4545         if (filter_op == RTE_ETH_FILTER_NOP)
4546                 return 0;
4547
4548         if (arg == NULL) {
4549                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4550                             filter_op);
4551                 return -EINVAL;
4552         }
4553
4554         switch (filter_op) {
4555         case RTE_ETH_FILTER_ADD:
4556                 ret = igb_add_del_ethertype_filter(dev,
4557                         (struct rte_eth_ethertype_filter *)arg,
4558                         TRUE);
4559                 break;
4560         case RTE_ETH_FILTER_DELETE:
4561                 ret = igb_add_del_ethertype_filter(dev,
4562                         (struct rte_eth_ethertype_filter *)arg,
4563                         FALSE);
4564                 break;
4565         case RTE_ETH_FILTER_GET:
4566                 ret = igb_get_ethertype_filter(dev,
4567                         (struct rte_eth_ethertype_filter *)arg);
4568                 break;
4569         default:
4570                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4571                 ret = -EINVAL;
4572                 break;
4573         }
4574         return ret;
4575 }
4576
4577 static int
4578 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4579                      enum rte_filter_type filter_type,
4580                      enum rte_filter_op filter_op,
4581                      void *arg)
4582 {
4583         int ret = -EINVAL;
4584
4585         switch (filter_type) {
4586         case RTE_ETH_FILTER_NTUPLE:
4587                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4588                 break;
4589         case RTE_ETH_FILTER_ETHERTYPE:
4590                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4591                 break;
4592         case RTE_ETH_FILTER_SYN:
4593                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4594                 break;
4595         case RTE_ETH_FILTER_FLEXIBLE:
4596                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4597                 break;
4598         default:
4599                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4600                                                         filter_type);
4601                 break;
4602         }
4603
4604         return ret;
4605 }
4606
4607 static int
4608 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4609                          struct ether_addr *mc_addr_set,
4610                          uint32_t nb_mc_addr)
4611 {
4612         struct e1000_hw *hw;
4613
4614         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4615         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4616         return 0;
4617 }
4618
4619 static uint64_t
4620 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4621 {
4622         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623         uint64_t systime_cycles;
4624
4625         switch (hw->mac.type) {
4626         case e1000_i210:
4627         case e1000_i211:
4628                 /*
4629                  * Need to read System Time Residue Register to be able
4630                  * to read the other two registers.
4631                  */
4632                 E1000_READ_REG(hw, E1000_SYSTIMR);
4633                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4634                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4635                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4636                                 * NSEC_PER_SEC;
4637                 break;
4638         case e1000_82580:
4639         case e1000_i350:
4640         case e1000_i354:
4641                 /*
4642                  * Need to read System Time Residue Register to be able
4643                  * to read the other two registers.
4644                  */
4645                 E1000_READ_REG(hw, E1000_SYSTIMR);
4646                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4647                 /* Only the 8 LSB are valid. */
4648                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4649                                 & 0xff) << 32;
4650                 break;
4651         default:
4652                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4653                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4654                                 << 32;
4655                 break;
4656         }
4657
4658         return systime_cycles;
4659 }
4660
4661 static uint64_t
4662 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4663 {
4664         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665         uint64_t rx_tstamp_cycles;
4666
4667         switch (hw->mac.type) {
4668         case e1000_i210:
4669         case e1000_i211:
4670                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4671                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4672                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4673                                 * NSEC_PER_SEC;
4674                 break;
4675         case e1000_82580:
4676         case e1000_i350:
4677         case e1000_i354:
4678                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4679                 /* Only the 8 LSB are valid. */
4680                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4681                                 & 0xff) << 32;
4682                 break;
4683         default:
4684                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4685                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4686                                 << 32;
4687                 break;
4688         }
4689
4690         return rx_tstamp_cycles;
4691 }
4692
4693 static uint64_t
4694 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4695 {
4696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4697         uint64_t tx_tstamp_cycles;
4698
4699         switch (hw->mac.type) {
4700         case e1000_i210:
4701         case e1000_i211:
4702                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4703                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4704                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4705                                 * NSEC_PER_SEC;
4706                 break;
4707         case e1000_82580:
4708         case e1000_i350:
4709         case e1000_i354:
4710                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4711                 /* Only the 8 LSB are valid. */
4712                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4713                                 & 0xff) << 32;
4714                 break;
4715         default:
4716                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4717                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4718                                 << 32;
4719                 break;
4720         }
4721
4722         return tx_tstamp_cycles;
4723 }
4724
4725 static void
4726 igb_start_timecounters(struct rte_eth_dev *dev)
4727 {
4728         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729         struct e1000_adapter *adapter =
4730                 (struct e1000_adapter *)dev->data->dev_private;
4731         uint32_t incval = 1;
4732         uint32_t shift = 0;
4733         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4734
4735         switch (hw->mac.type) {
4736         case e1000_82580:
4737         case e1000_i350:
4738         case e1000_i354:
4739                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4740                 mask = (1ULL << 40) - 1;
4741                 /* fall-through */
4742         case e1000_i210:
4743         case e1000_i211:
4744                 /*
4745                  * Start incrementing the register
4746                  * used to timestamp PTP packets.
4747                  */
4748                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4749                 break;
4750         case e1000_82576:
4751                 incval = E1000_INCVALUE_82576;
4752                 shift = IGB_82576_TSYNC_SHIFT;
4753                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4754                                 E1000_INCPERIOD_82576 | incval);
4755                 break;
4756         default:
4757                 /* Not supported */
4758                 return;
4759         }
4760
4761         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4762         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4763         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4764
4765         adapter->systime_tc.cc_mask = mask;
4766         adapter->systime_tc.cc_shift = shift;
4767         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4768
4769         adapter->rx_tstamp_tc.cc_mask = mask;
4770         adapter->rx_tstamp_tc.cc_shift = shift;
4771         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4772
4773         adapter->tx_tstamp_tc.cc_mask = mask;
4774         adapter->tx_tstamp_tc.cc_shift = shift;
4775         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4776 }
4777
4778 static int
4779 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4780 {
4781         struct e1000_adapter *adapter =
4782                         (struct e1000_adapter *)dev->data->dev_private;
4783
4784         adapter->systime_tc.nsec += delta;
4785         adapter->rx_tstamp_tc.nsec += delta;
4786         adapter->tx_tstamp_tc.nsec += delta;
4787
4788         return 0;
4789 }
4790
4791 static int
4792 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4793 {
4794         uint64_t ns;
4795         struct e1000_adapter *adapter =
4796                         (struct e1000_adapter *)dev->data->dev_private;
4797
4798         ns = rte_timespec_to_ns(ts);
4799
4800         /* Set the timecounters to a new value. */
4801         adapter->systime_tc.nsec = ns;
4802         adapter->rx_tstamp_tc.nsec = ns;
4803         adapter->tx_tstamp_tc.nsec = ns;
4804
4805         return 0;
4806 }
4807
4808 static int
4809 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4810 {
4811         uint64_t ns, systime_cycles;
4812         struct e1000_adapter *adapter =
4813                         (struct e1000_adapter *)dev->data->dev_private;
4814
4815         systime_cycles = igb_read_systime_cyclecounter(dev);
4816         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4817         *ts = rte_ns_to_timespec(ns);
4818
4819         return 0;
4820 }
4821
4822 static int
4823 igb_timesync_enable(struct rte_eth_dev *dev)
4824 {
4825         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         uint32_t tsync_ctl;
4827         uint32_t tsauxc;
4828
4829         /* Stop the timesync system time. */
4830         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4831         /* Reset the timesync system time value. */
4832         switch (hw->mac.type) {
4833         case e1000_82580:
4834         case e1000_i350:
4835         case e1000_i354:
4836         case e1000_i210:
4837         case e1000_i211:
4838                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4839                 /* fall-through */
4840         case e1000_82576:
4841                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4842                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4843                 break;
4844         default:
4845                 /* Not supported. */
4846                 return -ENOTSUP;
4847         }
4848
4849         /* Enable system time for it isn't on by default. */
4850         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4851         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4852         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4853
4854         igb_start_timecounters(dev);
4855
4856         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4857         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4858                         (ETHER_TYPE_1588 |
4859                          E1000_ETQF_FILTER_ENABLE |
4860                          E1000_ETQF_1588));
4861
4862         /* Enable timestamping of received PTP packets. */
4863         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4864         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4865         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4866
4867         /* Enable Timestamping of transmitted PTP packets. */
4868         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4869         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4870         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4871
4872         return 0;
4873 }
4874
4875 static int
4876 igb_timesync_disable(struct rte_eth_dev *dev)
4877 {
4878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4879         uint32_t tsync_ctl;
4880
4881         /* Disable timestamping of transmitted PTP packets. */
4882         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4883         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4884         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4885
4886         /* Disable timestamping of received PTP packets. */
4887         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4888         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4889         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4890
4891         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4892         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4893
4894         /* Stop incrementating the System Time registers. */
4895         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4896
4897         return 0;
4898 }
4899
4900 static int
4901 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4902                                struct timespec *timestamp,
4903                                uint32_t flags __rte_unused)
4904 {
4905         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4906         struct e1000_adapter *adapter =
4907                         (struct e1000_adapter *)dev->data->dev_private;
4908         uint32_t tsync_rxctl;
4909         uint64_t rx_tstamp_cycles;
4910         uint64_t ns;
4911
4912         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4913         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4914                 return -EINVAL;
4915
4916         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4917         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4918         *timestamp = rte_ns_to_timespec(ns);
4919
4920         return  0;
4921 }
4922
4923 static int
4924 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4925                                struct timespec *timestamp)
4926 {
4927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         struct e1000_adapter *adapter =
4929                         (struct e1000_adapter *)dev->data->dev_private;
4930         uint32_t tsync_txctl;
4931         uint64_t tx_tstamp_cycles;
4932         uint64_t ns;
4933
4934         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4935         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4936                 return -EINVAL;
4937
4938         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4939         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4940         *timestamp = rte_ns_to_timespec(ns);
4941
4942         return  0;
4943 }
4944
4945 static int
4946 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4947 {
4948         int count = 0;
4949         int g_ind = 0;
4950         const struct reg_info *reg_group;
4951
4952         while ((reg_group = igb_regs[g_ind++]))
4953                 count += igb_reg_group_count(reg_group);
4954
4955         return count;
4956 }
4957
4958 static int
4959 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4960 {
4961         int count = 0;
4962         int g_ind = 0;
4963         const struct reg_info *reg_group;
4964
4965         while ((reg_group = igbvf_regs[g_ind++]))
4966                 count += igb_reg_group_count(reg_group);
4967
4968         return count;
4969 }
4970
4971 static int
4972 eth_igb_get_regs(struct rte_eth_dev *dev,
4973         struct rte_dev_reg_info *regs)
4974 {
4975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint32_t *data = regs->data;
4977         int g_ind = 0;
4978         int count = 0;
4979         const struct reg_info *reg_group;
4980
4981         if (data == NULL) {
4982                 regs->length = eth_igb_get_reg_length(dev);
4983                 regs->width = sizeof(uint32_t);
4984                 return 0;
4985         }
4986
4987         /* Support only full register dump */
4988         if ((regs->length == 0) ||
4989             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4990                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4991                         hw->device_id;
4992                 while ((reg_group = igb_regs[g_ind++]))
4993                         count += igb_read_regs_group(dev, &data[count],
4994                                                         reg_group);
4995                 return 0;
4996         }
4997
4998         return -ENOTSUP;
4999 }
5000
5001 static int
5002 igbvf_get_regs(struct rte_eth_dev *dev,
5003         struct rte_dev_reg_info *regs)
5004 {
5005         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         uint32_t *data = regs->data;
5007         int g_ind = 0;
5008         int count = 0;
5009         const struct reg_info *reg_group;
5010
5011         if (data == NULL) {
5012                 regs->length = igbvf_get_reg_length(dev);
5013                 regs->width = sizeof(uint32_t);
5014                 return 0;
5015         }
5016
5017         /* Support only full register dump */
5018         if ((regs->length == 0) ||
5019             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5020                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5021                         hw->device_id;
5022                 while ((reg_group = igbvf_regs[g_ind++]))
5023                         count += igb_read_regs_group(dev, &data[count],
5024                                                         reg_group);
5025                 return 0;
5026         }
5027
5028         return -ENOTSUP;
5029 }
5030
5031 static int
5032 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5033 {
5034         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035
5036         /* Return unit is byte count */
5037         return hw->nvm.word_size * 2;
5038 }
5039
5040 static int
5041 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5042         struct rte_dev_eeprom_info *in_eeprom)
5043 {
5044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         struct e1000_nvm_info *nvm = &hw->nvm;
5046         uint16_t *data = in_eeprom->data;
5047         int first, length;
5048
5049         first = in_eeprom->offset >> 1;
5050         length = in_eeprom->length >> 1;
5051         if ((first >= hw->nvm.word_size) ||
5052             ((first + length) >= hw->nvm.word_size))
5053                 return -EINVAL;
5054
5055         in_eeprom->magic = hw->vendor_id |
5056                 ((uint32_t)hw->device_id << 16);
5057
5058         if ((nvm->ops.read) == NULL)
5059                 return -ENOTSUP;
5060
5061         return nvm->ops.read(hw, first, length, data);
5062 }
5063
5064 static int
5065 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5066         struct rte_dev_eeprom_info *in_eeprom)
5067 {
5068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         struct e1000_nvm_info *nvm = &hw->nvm;
5070         uint16_t *data = in_eeprom->data;
5071         int first, length;
5072
5073         first = in_eeprom->offset >> 1;
5074         length = in_eeprom->length >> 1;
5075         if ((first >= hw->nvm.word_size) ||
5076             ((first + length) >= hw->nvm.word_size))
5077                 return -EINVAL;
5078
5079         in_eeprom->magic = (uint32_t)hw->vendor_id |
5080                 ((uint32_t)hw->device_id << 16);
5081
5082         if ((nvm->ops.write) == NULL)
5083                 return -ENOTSUP;
5084         return nvm->ops.write(hw,  first, length, data);
5085 }
5086
5087 static struct rte_driver pmd_igb_drv = {
5088         .type = PMD_PDEV,
5089         .init = rte_igb_pmd_init,
5090 };
5091
5092 static struct rte_driver pmd_igbvf_drv = {
5093         .type = PMD_PDEV,
5094         .init = rte_igbvf_pmd_init,
5095 };
5096
5097 static int
5098 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5099 {
5100         struct e1000_hw *hw =
5101                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102         uint32_t mask = 1 << queue_id;
5103
5104         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5105         E1000_WRITE_FLUSH(hw);
5106
5107         return 0;
5108 }
5109
5110 static int
5111 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5112 {
5113         struct e1000_hw *hw =
5114                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5115         uint32_t mask = 1 << queue_id;
5116         uint32_t regval;
5117
5118         regval = E1000_READ_REG(hw, E1000_EIMS);
5119         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5120         E1000_WRITE_FLUSH(hw);
5121
5122         rte_intr_enable(&dev->pci_dev->intr_handle);
5123
5124         return 0;
5125 }
5126
5127 static void
5128 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5129                    uint8_t index, uint8_t offset)
5130 {
5131         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5132
5133         /* clear bits */
5134         val &= ~((uint32_t)0xFF << offset);
5135
5136         /* write vector and valid bit */
5137         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5138
5139         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5140 }
5141
5142 static void
5143 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5144                            uint8_t queue, uint8_t msix_vector)
5145 {
5146         uint32_t tmp = 0;
5147
5148         if (hw->mac.type == e1000_82575) {
5149                 if (direction == 0)
5150                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5151                 else if (direction == 1)
5152                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5153                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5154         } else if (hw->mac.type == e1000_82576) {
5155                 if ((direction == 0) || (direction == 1))
5156                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5157                                            ((queue & 0x8) << 1) +
5158                                            8 * direction);
5159         } else if ((hw->mac.type == e1000_82580) ||
5160                         (hw->mac.type == e1000_i350) ||
5161                         (hw->mac.type == e1000_i354) ||
5162                         (hw->mac.type == e1000_i210) ||
5163                         (hw->mac.type == e1000_i211)) {
5164                 if ((direction == 0) || (direction == 1))
5165                         eth_igb_write_ivar(hw, msix_vector,
5166                                            queue >> 1,
5167                                            ((queue & 0x1) << 4) +
5168                                            8 * direction);
5169         }
5170 }
5171
5172 /* Sets up the hardware to generate MSI-X interrupts properly
5173  * @hw
5174  *  board private structure
5175  */
5176 static void
5177 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5178 {
5179         int queue_id;
5180         uint32_t tmpval, regval, intr_mask;
5181         struct e1000_hw *hw =
5182                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183         uint32_t vec = E1000_MISC_VEC_ID;
5184         uint32_t base = E1000_MISC_VEC_ID;
5185         uint32_t misc_shift = 0;
5186
5187         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5188
5189         /* won't configure msix register if no mapping is done
5190          * between intr vector and event fd
5191          */
5192         if (!rte_intr_dp_is_en(intr_handle))
5193                 return;
5194
5195         if (rte_intr_allow_others(intr_handle)) {
5196                 vec = base = E1000_RX_VEC_START;
5197                 misc_shift = 1;
5198         }
5199
5200         /* set interrupt vector for other causes */
5201         if (hw->mac.type == e1000_82575) {
5202                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5203                 /* enable MSI-X PBA support */
5204                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5205
5206                 /* Auto-Mask interrupts upon ICR read */
5207                 tmpval |= E1000_CTRL_EXT_EIAME;
5208                 tmpval |= E1000_CTRL_EXT_IRCA;
5209
5210                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5211
5212                 /* enable msix_other interrupt */
5213                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5214                 regval = E1000_READ_REG(hw, E1000_EIAC);
5215                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5216                 regval = E1000_READ_REG(hw, E1000_EIAM);
5217                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5218         } else if ((hw->mac.type == e1000_82576) ||
5219                         (hw->mac.type == e1000_82580) ||
5220                         (hw->mac.type == e1000_i350) ||
5221                         (hw->mac.type == e1000_i354) ||
5222                         (hw->mac.type == e1000_i210) ||
5223                         (hw->mac.type == e1000_i211)) {
5224                 /* turn on MSI-X capability first */
5225                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5226                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5227                                         E1000_GPIE_NSICR);
5228                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5229                         misc_shift;
5230                 regval = E1000_READ_REG(hw, E1000_EIAC);
5231                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5232
5233                 /* enable msix_other interrupt */
5234                 regval = E1000_READ_REG(hw, E1000_EIMS);
5235                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5236                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5237                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5238         }
5239
5240         /* use EIAM to auto-mask when MSI-X interrupt
5241          * is asserted, this saves a register write for every interrupt
5242          */
5243         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5244                 misc_shift;
5245         regval = E1000_READ_REG(hw, E1000_EIAM);
5246         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5247
5248         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5249                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5250                 intr_handle->intr_vec[queue_id] = vec;
5251                 if (vec < base + intr_handle->nb_efd - 1)
5252                         vec++;
5253         }
5254
5255         E1000_WRITE_FLUSH(hw);
5256 }
5257
5258 PMD_REGISTER_DRIVER(pmd_igb_drv, net_e1000_igb);
5259 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5260 PMD_REGISTER_DRIVER(pmd_igbvf_drv, net_e1000_igb_vf);
5261 DRIVER_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);