drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 120                                     struct rte_eth_xstat_name *xstats_names,
 121                                     unsigned int limit);
 122 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 123 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 124 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 125                                    char *fw_version, size_t fw_size);
 126 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 127                               struct rte_eth_dev_info *dev_info);
 128 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 129 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 130                                 struct rte_eth_dev_info *dev_info);
 131 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 132                                 struct rte_eth_fc_conf *fc_conf);
 133 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 134                                 struct rte_eth_fc_conf *fc_conf);
 135 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 136 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 137 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 138 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 139                                     struct rte_intr_handle *handle);
 140 static void eth_igb_interrupt_handler(void *param);
 141 static int  igb_hardware_init(struct e1000_hw *hw);
 142 static void igb_hw_control_acquire(struct e1000_hw *hw);
 143 static void igb_hw_control_release(struct e1000_hw *hw);
 144 static void igb_init_manageability(struct e1000_hw *hw);
 145 static void igb_release_manageability(struct e1000_hw *hw);
 146
 147 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 148
 149 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 150                 uint16_t vlan_id, int on);
 151 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 152                                  enum rte_vlan_type vlan_type,
 153                                  uint16_t tpid_id);
 154 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155
 156 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 160 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 161 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 162
 163 static int eth_igb_led_on(struct rte_eth_dev *dev);
 164 static int eth_igb_led_off(struct rte_eth_dev *dev);
 165
 166 static void igb_intr_disable(struct e1000_hw *hw);
 167 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 168 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 169                 struct ether_addr *mac_addr,
 170                 uint32_t index, uint32_t pool);
 171 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 172 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 173                 struct ether_addr *addr);
 174
 175 static void igbvf_intr_disable(struct e1000_hw *hw);
 176 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 177 static int igbvf_dev_start(struct rte_eth_dev *dev);
 178 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 179 static void igbvf_dev_close(struct rte_eth_dev *dev);
 180 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int eth_igbvf_link_update(struct e1000_hw *hw);
 185 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_stats *rte_stats);
 187 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 188                                 struct rte_eth_xstat *xstats, unsigned n);
 189 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 190                                       struct rte_eth_xstat_name *xstats_names,
 191                                       unsigned limit);
 192 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 193 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 196 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 197 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 198                 struct ether_addr *addr);
 199 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 200 static int igbvf_get_regs(struct rte_eth_dev *dev,
 201                 struct rte_dev_reg_info *regs);
 202
 203 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 204                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                    uint16_t reta_size);
 206 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 207                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 208                                   uint16_t reta_size);
 209
 210 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter,
 212                         bool add);
 213 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 214                         struct rte_eth_syn_filter *filter);
 215 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 216                         enum rte_filter_op filter_op,
 217                         void *arg);
 218 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_ntuple_filter *ntuple_filter);
 222 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter,
 224                         bool add);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter,
 236                         bool add);
 237 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 238                         struct rte_eth_ntuple_filter *filter);
 239 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 256                 struct rte_dev_reg_info *regs);
 257 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 258 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 261                 struct rte_dev_eeprom_info *eeprom);
 262 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 263                                     struct ether_addr *mc_addr_set,
 264                                     uint32_t nb_mc_addr);
 265 static int igb_timesync_enable(struct rte_eth_dev *dev);
 266 static int igb_timesync_disable(struct rte_eth_dev *dev);
 267 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp,
 269                                           uint32_t flags);
 270 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 271                                           struct timespec *timestamp);
 272 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 273 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 274                                   struct timespec *timestamp);
 275 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 276                                    const struct timespec *timestamp);
 277 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                         uint16_t queue_id);
 279 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                          uint16_t queue_id);
 281 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 282                                        uint8_t queue, uint8_t msix_vector);
 283 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 284                                uint8_t index, uint8_t offset);
 285 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 286 static void eth_igbvf_interrupt_handler(void *param);
 287 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 288
 289 /*
 290  * Define VF Stats MACRO for Non "cleared on read" register
 291  */
 292 #define UPDATE_VF_STAT(reg, last, cur)            \
 293 {                                                 \
 294         u32 latest = E1000_READ_REG(hw, reg);     \
 295         cur += (latest - last) & UINT_MAX;        \
 296         last = latest;                            \
 297 }
 298
 299 #define IGB_FC_PAUSE_TIME 0x0680
 300 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 301 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 302
 303 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 304
 305 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 306
 307 /*
 308  * The set of PCI devices this driver supports
 309  */
 310 static const struct rte_pci_id pci_id_igb_map[] = {
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 319
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 323
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 330
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 350         { .vendor_id = 0, /* sentinel */ },
 351 };
 352
 353 /*
 354  * The set of PCI devices this driver supports (for 82576&I350 VF)
 355  */
 356 static const struct rte_pci_id pci_id_igbvf_map[] = {
 357         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 360         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 361         { .vendor_id = 0, /* sentinel */ },
 362 };
 363
 364 static const struct rte_eth_desc_lim rx_desc_lim = {
 365         .nb_max = E1000_MAX_RING_DESC,
 366         .nb_min = E1000_MIN_RING_DESC,
 367         .nb_align = IGB_RXD_ALIGN,
 368 };
 369
 370 static const struct rte_eth_desc_lim tx_desc_lim = {
 371         .nb_max = E1000_MAX_RING_DESC,
 372         .nb_min = E1000_MIN_RING_DESC,
 373         .nb_align = IGB_RXD_ALIGN,
 374         .nb_seg_max = IGB_TX_MAX_SEG,
 375         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 376 };
 377
 378 static const struct eth_dev_ops eth_igb_ops = {
 379         .dev_configure        = eth_igb_configure,
 380         .dev_start            = eth_igb_start,
 381         .dev_stop             = eth_igb_stop,
 382         .dev_set_link_up      = eth_igb_dev_set_link_up,
 383         .dev_set_link_down    = eth_igb_dev_set_link_down,
 384         .dev_close            = eth_igb_close,
 385         .promiscuous_enable   = eth_igb_promiscuous_enable,
 386         .promiscuous_disable  = eth_igb_promiscuous_disable,
 387         .allmulticast_enable  = eth_igb_allmulticast_enable,
 388         .allmulticast_disable = eth_igb_allmulticast_disable,
 389         .link_update          = eth_igb_link_update,
 390         .stats_get            = eth_igb_stats_get,
 391         .xstats_get           = eth_igb_xstats_get,
 392         .xstats_get_names     = eth_igb_xstats_get_names,
 393         .stats_reset          = eth_igb_stats_reset,
 394         .xstats_reset         = eth_igb_xstats_reset,
 395         .fw_version_get       = eth_igb_fw_version_get,
 396         .dev_infos_get        = eth_igb_infos_get,
 397         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 398         .mtu_set              = eth_igb_mtu_set,
 399         .vlan_filter_set      = eth_igb_vlan_filter_set,
 400         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 401         .vlan_offload_set     = eth_igb_vlan_offload_set,
 402         .rx_queue_setup       = eth_igb_rx_queue_setup,
 403         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 404         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 405         .rx_queue_release     = eth_igb_rx_queue_release,
 406         .rx_queue_count       = eth_igb_rx_queue_count,
 407         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 408         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 409         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 410         .tx_queue_setup       = eth_igb_tx_queue_setup,
 411         .tx_queue_release     = eth_igb_tx_queue_release,
 412         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 413         .dev_led_on           = eth_igb_led_on,
 414         .dev_led_off          = eth_igb_led_off,
 415         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 416         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 417         .mac_addr_add         = eth_igb_rar_set,
 418         .mac_addr_remove      = eth_igb_rar_clear,
 419         .mac_addr_set         = eth_igb_default_mac_addr_set,
 420         .reta_update          = eth_igb_rss_reta_update,
 421         .reta_query           = eth_igb_rss_reta_query,
 422         .rss_hash_update      = eth_igb_rss_hash_update,
 423         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 424         .filter_ctrl          = eth_igb_filter_ctrl,
 425         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 426         .rxq_info_get         = igb_rxq_info_get,
 427         .txq_info_get         = igb_txq_info_get,
 428         .timesync_enable      = igb_timesync_enable,
 429         .timesync_disable     = igb_timesync_disable,
 430         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 431         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 432         .get_reg              = eth_igb_get_regs,
 433         .get_eeprom_length    = eth_igb_get_eeprom_length,
 434         .get_eeprom           = eth_igb_get_eeprom,
 435         .set_eeprom           = eth_igb_set_eeprom,
 436         .timesync_adjust_time = igb_timesync_adjust_time,
 437         .timesync_read_time   = igb_timesync_read_time,
 438         .timesync_write_time  = igb_timesync_write_time,
 439 };
 440
 441 /*
 442  * dev_ops for virtual function, bare necessities for basic vf
 443  * operation have been implemented
 444  */
 445 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 446         .dev_configure        = igbvf_dev_configure,
 447         .dev_start            = igbvf_dev_start,
 448         .dev_stop             = igbvf_dev_stop,
 449         .dev_close            = igbvf_dev_close,
 450         .promiscuous_enable   = igbvf_promiscuous_enable,
 451         .promiscuous_disable  = igbvf_promiscuous_disable,
 452         .allmulticast_enable  = igbvf_allmulticast_enable,
 453         .allmulticast_disable = igbvf_allmulticast_disable,
 454         .link_update          = eth_igb_link_update,
 455         .stats_get            = eth_igbvf_stats_get,
 456         .xstats_get           = eth_igbvf_xstats_get,
 457         .xstats_get_names     = eth_igbvf_xstats_get_names,
 458         .stats_reset          = eth_igbvf_stats_reset,
 459         .xstats_reset         = eth_igbvf_stats_reset,
 460         .vlan_filter_set      = igbvf_vlan_filter_set,
 461         .dev_infos_get        = eth_igbvf_infos_get,
 462         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 463         .rx_queue_setup       = eth_igb_rx_queue_setup,
 464         .rx_queue_release     = eth_igb_rx_queue_release,
 465         .tx_queue_setup       = eth_igb_tx_queue_setup,
 466         .tx_queue_release     = eth_igb_tx_queue_release,
 467         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 468         .rxq_info_get         = igb_rxq_info_get,
 469         .txq_info_get         = igb_txq_info_get,
 470         .mac_addr_set         = igbvf_default_mac_addr_set,
 471         .get_reg              = igbvf_get_regs,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_igb_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 481         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 482         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 483         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 484         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 485         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 486         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 487         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 488                 ecol)},
 489         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 490         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 491         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 492         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 493         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 494         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 495         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 496         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 497         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 498         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 499         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 500                 fcruc)},
 501         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 502         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 503         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 504         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 505         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 506                 prc1023)},
 507         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 508                 prc1522)},
 509         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 510         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 511         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 512         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 513         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 514         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 515         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 516         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 517         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 518         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 519         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 520         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 521         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 522         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 523         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 524         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 525         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 526         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 527                 ptc1023)},
 528         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 529                 ptc1522)},
 530         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 531         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 532         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 533         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 534         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 535         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 536         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 537
 538         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 539 };
 540
 541 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 542                 sizeof(rte_igb_stats_strings[0]))
 543
 544 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 545         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 546         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 547         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 548         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 549         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 550 };
 551
 552 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 553                 sizeof(rte_igbvf_stats_strings[0]))
 554
 555 /**
 556  * Atomically reads the link status information from global
 557  * structure rte_eth_dev.
 558  *
 559  * @param dev
 560  *   - Pointer to the structure rte_eth_dev to read from.
 561  *   - Pointer to the buffer to be saved with the link status.
 562  *
 563  * @return
 564  *   - On success, zero.
 565  *   - On failure, negative value.
 566  */
 567 static inline int
 568 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 569                                 struct rte_eth_link *link)
 570 {
 571         struct rte_eth_link *dst = link;
 572         struct rte_eth_link *src = &(dev->data->dev_link);
 573
 574         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 575                                         *(uint64_t *)src) == 0)
 576                 return -1;
 577
 578         return 0;
 579 }
 580
 581 /**
 582  * Atomically writes the link status information into global
 583  * structure rte_eth_dev.
 584  *
 585  * @param dev
 586  *   - Pointer to the structure rte_eth_dev to read from.
 587  *   - Pointer to the buffer to be saved with the link status.
 588  *
 589  * @return
 590  *   - On success, zero.
 591  *   - On failure, negative value.
 592  */
 593 static inline int
 594 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 595                                 struct rte_eth_link *link)
 596 {
 597         struct rte_eth_link *dst = &(dev->data->dev_link);
 598         struct rte_eth_link *src = link;
 599
 600         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 601                                         *(uint64_t *)src) == 0)
 602                 return -1;
 603
 604         return 0;
 605 }
 606
 607 static inline void
 608 igb_intr_enable(struct rte_eth_dev *dev)
 609 {
 610         struct e1000_interrupt *intr =
 611                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 612         struct e1000_hw *hw =
 613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 614
 615         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 616         E1000_WRITE_FLUSH(hw);
 617 }
 618
 619 static void
 620 igb_intr_disable(struct e1000_hw *hw)
 621 {
 622         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 623         E1000_WRITE_FLUSH(hw);
 624 }
 625
 626 static inline void
 627 igbvf_intr_enable(struct rte_eth_dev *dev)
 628 {
 629         struct e1000_hw *hw =
 630                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 631
 632         /* only for mailbox */
 633         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 636         E1000_WRITE_FLUSH(hw);
 637 }
 638
 639 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 640 static void
 641 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 642 {
 643         uint32_t tmp = 0;
 644
 645         /* mailbox */
 646         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 647         tmp |= E1000_VTIVAR_VALID;
 648         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 649 }
 650
 651 static void
 652 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 653 {
 654         struct e1000_hw *hw =
 655                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 656
 657         /* Configure VF other cause ivar */
 658         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 659 }
 660
 661 static inline int32_t
 662 igb_pf_reset_hw(struct e1000_hw *hw)
 663 {
 664         uint32_t ctrl_ext;
 665         int32_t status;
 666
 667         status = e1000_reset_hw(hw);
 668
 669         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 670         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 671         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 672         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 673         E1000_WRITE_FLUSH(hw);
 674
 675         return status;
 676 }
 677
 678 static void
 679 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 680 {
 681         struct e1000_hw *hw =
 682                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 683
 684
 685         hw->vendor_id = pci_dev->id.vendor_id;
 686         hw->device_id = pci_dev->id.device_id;
 687         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 688         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 689
 690         e1000_set_mac_type(hw);
 691
 692         /* need to check if it is a vf device below */
 693 }
 694
 695 static int
 696 igb_reset_swfw_lock(struct e1000_hw *hw)
 697 {
 698         int ret_val;
 699
 700         /*
 701          * Do mac ops initialization manually here, since we will need
 702          * some function pointers set by this call.
 703          */
 704         ret_val = e1000_init_mac_params(hw);
 705         if (ret_val)
 706                 return ret_val;
 707
 708         /*
 709          * SMBI lock should not fail in this early stage. If this is the case,
 710          * it is due to an improper exit of the application.
 711          * So force the release of the faulty lock.
 712          */
 713         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 714                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 715         }
 716         e1000_put_hw_semaphore_generic(hw);
 717
 718         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 719                 uint16_t mask;
 720
 721                 /*
 722                  * Phy lock should not fail in this early stage. If this is the case,
 723                  * it is due to an improper exit of the application.
 724                  * So force the release of the faulty lock.
 725                  */
 726                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 727                 if (hw->bus.func > E1000_FUNC_1)
 728                         mask <<= 2;
 729                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 730                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 731                                     hw->bus.func);
 732                 }
 733                 hw->mac.ops.release_swfw_sync(hw, mask);
 734
 735                 /*
 736                  * This one is more tricky since it is common to all ports; but
 737                  * swfw_sync retries last long enough (1s) to be almost sure that if
 738                  * lock can not be taken it is due to an improper lock of the
 739                  * semaphore.
 740                  */
 741                 mask = E1000_SWFW_EEP_SM;
 742                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 743                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 744                 }
 745                 hw->mac.ops.release_swfw_sync(hw, mask);
 746         }
 747
 748         return E1000_SUCCESS;
 749 }
 750
 751 static int
 752 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 753 {
 754         int error = 0;
 755         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 756         struct e1000_hw *hw =
 757                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 758         struct e1000_vfta * shadow_vfta =
 759                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 760         struct e1000_filter_info *filter_info =
 761                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 762         struct e1000_adapter *adapter =
 763                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 764
 765         uint32_t ctrl_ext;
 766
 767         eth_dev->dev_ops = &eth_igb_ops;
 768         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 769         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 770         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 771
 772         /* for secondary processes, we don't initialise any further as primary
 773          * has already done this work. Only check we don't need a different
 774          * RX function */
 775         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 776                 if (eth_dev->data->scattered_rx)
 777                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 778                 return 0;
 779         }
 780
 781         rte_eth_copy_pci_info(eth_dev, pci_dev);
 782         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 783
 784         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 785
 786         igb_identify_hardware(eth_dev, pci_dev);
 787         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 788                 error = -EIO;
 789                 goto err_late;
 790         }
 791
 792         e1000_get_bus_info(hw);
 793
 794         /* Reset any pending lock */
 795         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 796                 error = -EIO;
 797                 goto err_late;
 798         }
 799
 800         /* Finish initialization */
 801         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 802                 error = -EIO;
 803                 goto err_late;
 804         }
 805
 806         hw->mac.autoneg = 1;
 807         hw->phy.autoneg_wait_to_complete = 0;
 808         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 809
 810         /* Copper options */
 811         if (hw->phy.media_type == e1000_media_type_copper) {
 812                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 813                 hw->phy.disable_polarity_correction = 0;
 814                 hw->phy.ms_type = e1000_ms_hw_default;
 815         }
 816
 817         /*
 818          * Start from a known state, this is important in reading the nvm
 819          * and mac from that.
 820          */
 821         igb_pf_reset_hw(hw);
 822
 823         /* Make sure we have a good EEPROM before we read from it */
 824         if (e1000_validate_nvm_checksum(hw) < 0) {
 825                 /*
 826                  * Some PCI-E parts fail the first check due to
 827                  * the link being in sleep state, call it again,
 828                  * if it fails a second time its a real issue.
 829                  */
 830                 if (e1000_validate_nvm_checksum(hw) < 0) {
 831                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 832                         error = -EIO;
 833                         goto err_late;
 834                 }
 835         }
 836
 837         /* Read the permanent MAC address out of the EEPROM */
 838         if (e1000_read_mac_addr(hw) != 0) {
 839                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 840                 error = -EIO;
 841                 goto err_late;
 842         }
 843
 844         /* Allocate memory for storing MAC addresses */
 845         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 846                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 847         if (eth_dev->data->mac_addrs == NULL) {
 848                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 849                                                 "store MAC addresses",
 850                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 851                 error = -ENOMEM;
 852                 goto err_late;
 853         }
 854
 855         /* Copy the permanent MAC address */
 856         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 857
 858         /* initialize the vfta */
 859         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 860
 861         /* Now initialize the hardware */
 862         if (igb_hardware_init(hw) != 0) {
 863                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 864                 rte_free(eth_dev->data->mac_addrs);
 865                 eth_dev->data->mac_addrs = NULL;
 866                 error = -ENODEV;
 867                 goto err_late;
 868         }
 869         hw->mac.get_link_status = 1;
 870         adapter->stopped = 0;
 871
 872         /* Indicate SOL/IDER usage */
 873         if (e1000_check_reset_block(hw) < 0) {
 874                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 875                                         "SOL/IDER session");
 876         }
 877
 878         /* initialize PF if max_vfs not zero */
 879         igb_pf_host_init(eth_dev);
 880
 881         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 882         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 883         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 884         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 885         E1000_WRITE_FLUSH(hw);
 886
 887         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 888                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 889                      pci_dev->id.device_id);
 890
 891         rte_intr_callback_register(&pci_dev->intr_handle,
 892                                    eth_igb_interrupt_handler,
 893                                    (void *)eth_dev);
 894
 895         /* enable uio/vfio intr/eventfd mapping */
 896         rte_intr_enable(&pci_dev->intr_handle);
 897
 898         /* enable support intr */
 899         igb_intr_enable(eth_dev);
 900
 901         TAILQ_INIT(&filter_info->flex_list);
 902         filter_info->flex_mask = 0;
 903         TAILQ_INIT(&filter_info->twotuple_list);
 904         filter_info->twotuple_mask = 0;
 905         TAILQ_INIT(&filter_info->fivetuple_list);
 906         filter_info->fivetuple_mask = 0;
 907
 908         return 0;
 909
 910 err_late:
 911         igb_hw_control_release(hw);
 912
 913         return error;
 914 }
 915
 916 static int
 917 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 918 {
 919         struct rte_pci_device *pci_dev;
 920         struct rte_intr_handle *intr_handle;
 921         struct e1000_hw *hw;
 922         struct e1000_adapter *adapter =
 923                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 924
 925         PMD_INIT_FUNC_TRACE();
 926
 927         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 928                 return -EPERM;
 929
 930         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 931         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 932         intr_handle = &pci_dev->intr_handle;
 933
 934         if (adapter->stopped == 0)
 935                 eth_igb_close(eth_dev);
 936
 937         eth_dev->dev_ops = NULL;
 938         eth_dev->rx_pkt_burst = NULL;
 939         eth_dev->tx_pkt_burst = NULL;
 940
 941         /* Reset any pending lock */
 942         igb_reset_swfw_lock(hw);
 943
 944         rte_free(eth_dev->data->mac_addrs);
 945         eth_dev->data->mac_addrs = NULL;
 946
 947         /* uninitialize PF if max_vfs not zero */
 948         igb_pf_host_uninit(eth_dev);
 949
 950         /* disable uio intr before callback unregister */
 951         rte_intr_disable(intr_handle);
 952         rte_intr_callback_unregister(intr_handle,
 953                                      eth_igb_interrupt_handler, eth_dev);
 954
 955         return 0;
 956 }
 957
 958 /*
 959  * Virtual Function device init
 960  */
 961 static int
 962 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 963 {
 964         struct rte_pci_device *pci_dev;
 965         struct rte_intr_handle *intr_handle;
 966         struct e1000_adapter *adapter =
 967                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 968         struct e1000_hw *hw =
 969                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 970         int diag;
 971         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 976         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 977         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 978         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 979
 980         /* for secondary processes, we don't initialise any further as primary
 981          * has already done this work. Only check we don't need a different
 982          * RX function */
 983         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 984                 if (eth_dev->data->scattered_rx)
 985                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 986                 return 0;
 987         }
 988
 989         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 990         rte_eth_copy_pci_info(eth_dev, pci_dev);
 991         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 992
 993         hw->device_id = pci_dev->id.device_id;
 994         hw->vendor_id = pci_dev->id.vendor_id;
 995         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 996         adapter->stopped = 0;
 997
 998         /* Initialize the shared code (base driver) */
 999         diag = e1000_setup_init_funcs(hw, TRUE);
1000         if (diag != 0) {
1001                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1002                         diag);
1003                 return -EIO;
1004         }
1005
1006         /* init_mailbox_params */
1007         hw->mbx.ops.init_params(hw);
1008
1009         /* Disable the interrupts for VF */
1010         igbvf_intr_disable(hw);
1011
1012         diag = hw->mac.ops.reset_hw(hw);
1013
1014         /* Allocate memory for storing MAC addresses */
1015         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1016                 hw->mac.rar_entry_count, 0);
1017         if (eth_dev->data->mac_addrs == NULL) {
1018                 PMD_INIT_LOG(ERR,
1019                         "Failed to allocate %d bytes needed to store MAC "
1020                         "addresses",
1021                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1022                 return -ENOMEM;
1023         }
1024
1025         /* Generate a random MAC address, if none was assigned by PF. */
1026         if (is_zero_ether_addr(perm_addr)) {
1027                 eth_random_addr(perm_addr->addr_bytes);
1028                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1029                 if (diag) {
1030                         rte_free(eth_dev->data->mac_addrs);
1031                         eth_dev->data->mac_addrs = NULL;
1032                         return diag;
1033                 }
1034                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1035                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1036                              "%02x:%02x:%02x:%02x:%02x:%02x",
1037                              perm_addr->addr_bytes[0],
1038                              perm_addr->addr_bytes[1],
1039                              perm_addr->addr_bytes[2],
1040                              perm_addr->addr_bytes[3],
1041                              perm_addr->addr_bytes[4],
1042                              perm_addr->addr_bytes[5]);
1043         }
1044
1045         /* Copy the permanent MAC address */
1046         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1047                         &eth_dev->data->mac_addrs[0]);
1048
1049         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1050                      "mac.type=%s",
1051                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1052                      pci_dev->id.device_id, "igb_mac_82576_vf");
1053
1054         intr_handle = &pci_dev->intr_handle;
1055         rte_intr_callback_register(intr_handle,
1056                                    eth_igbvf_interrupt_handler, eth_dev);
1057
1058         return 0;
1059 }
1060
1061 static int
1062 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1063 {
1064         struct e1000_adapter *adapter =
1065                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1066         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1067
1068         PMD_INIT_FUNC_TRACE();
1069
1070         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1071                 return -EPERM;
1072
1073         if (adapter->stopped == 0)
1074                 igbvf_dev_close(eth_dev);
1075
1076         eth_dev->dev_ops = NULL;
1077         eth_dev->rx_pkt_burst = NULL;
1078         eth_dev->tx_pkt_burst = NULL;
1079
1080         rte_free(eth_dev->data->mac_addrs);
1081         eth_dev->data->mac_addrs = NULL;
1082
1083         /* disable uio intr before callback unregister */
1084         rte_intr_disable(&pci_dev->intr_handle);
1085         rte_intr_callback_unregister(&pci_dev->intr_handle,
1086                                      eth_igbvf_interrupt_handler,
1087                                      (void *)eth_dev);
1088
1089         return 0;
1090 }
1091
1092 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1093         struct rte_pci_device *pci_dev)
1094 {
1095         return rte_eth_dev_pci_generic_probe(pci_dev,
1096                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1097 }
1098
1099 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1100 {
1101         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1102 }
1103
1104 static struct rte_pci_driver rte_igb_pmd = {
1105         .id_table = pci_id_igb_map,
1106         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1107         .probe = eth_igb_pci_probe,
1108         .remove = eth_igb_pci_remove,
1109 };
1110
1111
1112 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1113         struct rte_pci_device *pci_dev)
1114 {
1115         return rte_eth_dev_pci_generic_probe(pci_dev,
1116                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1117 }
1118
1119 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1120 {
1121         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1122 }
1123
1124 /*
1125  * virtual function driver struct
1126  */
1127 static struct rte_pci_driver rte_igbvf_pmd = {
1128         .id_table = pci_id_igbvf_map,
1129         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1130         .probe = eth_igbvf_pci_probe,
1131         .remove = eth_igbvf_pci_remove,
1132 };
1133
1134 static void
1135 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1136 {
1137         struct e1000_hw *hw =
1138                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1139         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1140         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1141         rctl |= E1000_RCTL_VFE;
1142         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1143 }
1144
1145 static int
1146 igb_check_mq_mode(struct rte_eth_dev *dev)
1147 {
1148         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1149         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1150         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1151         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1152
1153         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1154             tx_mq_mode == ETH_MQ_TX_DCB ||
1155             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1156                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1157                 return -EINVAL;
1158         }
1159         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1160                 /* Check multi-queue mode.
1161                  * To no break software we accept ETH_MQ_RX_NONE as this might
1162                  * be used to turn off VLAN filter.
1163                  */
1164
1165                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1166                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1167                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1168                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1169                 } else {
1170                         /* Only support one queue on VFs.
1171                          * RSS together with SRIOV is not supported.
1172                          */
1173                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1174                                         " wrong mq_mode rx %d.",
1175                                         rx_mq_mode);
1176                         return -EINVAL;
1177                 }
1178                 /* TX mode is not used here, so mode might be ignored.*/
1179                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1180                         /* SRIOV only works in VMDq enable mode */
1181                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1182                                         " TX mode %d is not supported. "
1183                                         " Driver will behave as %d mode.",
1184                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1185                 }
1186
1187                 /* check valid queue number */
1188                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1189                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1190                                         " only support one queue on VFs.");
1191                         return -EINVAL;
1192                 }
1193         } else {
1194                 /* To no break software that set invalid mode, only display
1195                  * warning if invalid mode is used.
1196                  */
1197                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1198                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1199                     rx_mq_mode != ETH_MQ_RX_RSS) {
1200                         /* RSS together with VMDq not supported*/
1201                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1202                                      rx_mq_mode);
1203                         return -EINVAL;
1204                 }
1205
1206                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1207                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1208                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1209                                         " Due to txmode is meaningless in this"
1210                                         " driver, just ignore.",
1211                                         tx_mq_mode);
1212                 }
1213         }
1214         return 0;
1215 }
1216
1217 static int
1218 eth_igb_configure(struct rte_eth_dev *dev)
1219 {
1220         struct e1000_interrupt *intr =
1221                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1222         int ret;
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         /* multipe queue mode checking */
1227         ret  = igb_check_mq_mode(dev);
1228         if (ret != 0) {
1229                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1230                             ret);
1231                 return ret;
1232         }
1233
1234         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1235         PMD_INIT_FUNC_TRACE();
1236
1237         return 0;
1238 }
1239
1240 static int
1241 eth_igb_start(struct rte_eth_dev *dev)
1242 {
1243         struct e1000_hw *hw =
1244                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         struct e1000_adapter *adapter =
1246                 E1000_DEV_PRIVATE(dev->data->dev_private);
1247         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1248         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1249         int ret, mask;
1250         uint32_t intr_vector = 0;
1251         uint32_t ctrl_ext;
1252         uint32_t *speeds;
1253         int num_speeds;
1254         bool autoneg;
1255
1256         PMD_INIT_FUNC_TRACE();
1257
1258         /* disable uio/vfio intr/eventfd mapping */
1259         rte_intr_disable(intr_handle);
1260
1261         /* Power up the phy. Needed to make the link go Up */
1262         eth_igb_dev_set_link_up(dev);
1263
1264         /*
1265          * Packet Buffer Allocation (PBA)
1266          * Writing PBA sets the receive portion of the buffer
1267          * the remainder is used for the transmit buffer.
1268          */
1269         if (hw->mac.type == e1000_82575) {
1270                 uint32_t pba;
1271
1272                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1273                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1274         }
1275
1276         /* Put the address into the Receive Address Array */
1277         e1000_rar_set(hw, hw->mac.addr, 0);
1278
1279         /* Initialize the hardware */
1280         if (igb_hardware_init(hw)) {
1281                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1282                 return -EIO;
1283         }
1284         adapter->stopped = 0;
1285
1286         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1287
1288         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1289         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1290         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1291         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1292         E1000_WRITE_FLUSH(hw);
1293
1294         /* configure PF module if SRIOV enabled */
1295         igb_pf_host_configure(dev);
1296
1297         /* check and configure queue intr-vector mapping */
1298         if ((rte_intr_cap_multiple(intr_handle) ||
1299              !RTE_ETH_DEV_SRIOV(dev).active) &&
1300             dev->data->dev_conf.intr_conf.rxq != 0) {
1301                 intr_vector = dev->data->nb_rx_queues;
1302                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1303                         return -1;
1304         }
1305
1306         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1307                 intr_handle->intr_vec =
1308                         rte_zmalloc("intr_vec",
1309                                     dev->data->nb_rx_queues * sizeof(int), 0);
1310                 if (intr_handle->intr_vec == NULL) {
1311                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1312                                      " intr_vec", dev->data->nb_rx_queues);
1313                         return -ENOMEM;
1314                 }
1315         }
1316
1317         /* confiugre msix for rx interrupt */
1318         eth_igb_configure_msix_intr(dev);
1319
1320         /* Configure for OS presence */
1321         igb_init_manageability(hw);
1322
1323         eth_igb_tx_init(dev);
1324
1325         /* This can fail when allocating mbufs for descriptor rings */
1326         ret = eth_igb_rx_init(dev);
1327         if (ret) {
1328                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1329                 igb_dev_clear_queues(dev);
1330                 return ret;
1331         }
1332
1333         e1000_clear_hw_cntrs_base_generic(hw);
1334
1335         /*
1336          * VLAN Offload Settings
1337          */
1338         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1339                         ETH_VLAN_EXTEND_MASK;
1340         eth_igb_vlan_offload_set(dev, mask);
1341
1342         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1343                 /* Enable VLAN filter since VMDq always use VLAN filter */
1344                 igb_vmdq_vlan_hw_filter_enable(dev);
1345         }
1346
1347         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1348                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1349                 (hw->mac.type == e1000_i211)) {
1350                 /* Configure EITR with the maximum possible value (0xFFFF) */
1351                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1352         }
1353
1354         /* Setup link speed and duplex */
1355         speeds = &dev->data->dev_conf.link_speeds;
1356         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1357                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1358                 hw->mac.autoneg = 1;
1359         } else {
1360                 num_speeds = 0;
1361                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1362
1363                 /* Reset */
1364                 hw->phy.autoneg_advertised = 0;
1365
1366                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1367                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1368                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1369                         num_speeds = -1;
1370                         goto error_invalid_config;
1371                 }
1372                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1373                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1374                         num_speeds++;
1375                 }
1376                 if (*speeds & ETH_LINK_SPEED_10M) {
1377                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1378                         num_speeds++;
1379                 }
1380                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1381                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1382                         num_speeds++;
1383                 }
1384                 if (*speeds & ETH_LINK_SPEED_100M) {
1385                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1386                         num_speeds++;
1387                 }
1388                 if (*speeds & ETH_LINK_SPEED_1G) {
1389                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1390                         num_speeds++;
1391                 }
1392                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1393                         goto error_invalid_config;
1394
1395                 /* Set/reset the mac.autoneg based on the link speed,
1396                  * fixed or not
1397                  */
1398                 if (!autoneg) {
1399                         hw->mac.autoneg = 0;
1400                         hw->mac.forced_speed_duplex =
1401                                         hw->phy.autoneg_advertised;
1402                 } else {
1403                         hw->mac.autoneg = 1;
1404                 }
1405         }
1406
1407         e1000_setup_link(hw);
1408
1409         if (rte_intr_allow_others(intr_handle)) {
1410                 /* check if lsc interrupt is enabled */
1411                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1412                         eth_igb_lsc_interrupt_setup(dev);
1413         } else {
1414                 rte_intr_callback_unregister(intr_handle,
1415                                              eth_igb_interrupt_handler,
1416                                              (void *)dev);
1417                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1418                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1419                                      " no intr multiplex");
1420         }
1421
1422         /* check if rxq interrupt is enabled */
1423         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1424             rte_intr_dp_is_en(intr_handle))
1425                 eth_igb_rxq_interrupt_setup(dev);
1426
1427         /* enable uio/vfio intr/eventfd mapping */
1428         rte_intr_enable(intr_handle);
1429
1430         /* resume enabled intr since hw reset */
1431         igb_intr_enable(dev);
1432
1433         PMD_INIT_LOG(DEBUG, "<<");
1434
1435         return 0;
1436
1437 error_invalid_config:
1438         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1439                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1440         igb_dev_clear_queues(dev);
1441         return -EINVAL;
1442 }
1443
1444 /*********************************************************************
1445  *
1446  *  This routine disables all traffic on the adapter by issuing a
1447  *  global reset on the MAC.
1448  *
1449  **********************************************************************/
1450 static void
1451 eth_igb_stop(struct rte_eth_dev *dev)
1452 {
1453         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1454         struct e1000_filter_info *filter_info =
1455                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1456         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1457         struct rte_eth_link link;
1458         struct e1000_flex_filter *p_flex;
1459         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1460         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1461         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1462
1463         igb_intr_disable(hw);
1464
1465         /* disable intr eventfd mapping */
1466         rte_intr_disable(intr_handle);
1467
1468         igb_pf_reset_hw(hw);
1469         E1000_WRITE_REG(hw, E1000_WUC, 0);
1470
1471         /* Set bit for Go Link disconnect */
1472         if (hw->mac.type >= e1000_82580) {
1473                 uint32_t phpm_reg;
1474
1475                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1476                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1477                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1478         }
1479
1480         /* Power down the phy. Needed to make the link go Down */
1481         eth_igb_dev_set_link_down(dev);
1482
1483         igb_dev_clear_queues(dev);
1484
1485         /* clear the recorded link status */
1486         memset(&link, 0, sizeof(link));
1487         rte_igb_dev_atomic_write_link_status(dev, &link);
1488
1489         /* Remove all flex filters of the device */
1490         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1491                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1492                 rte_free(p_flex);
1493         }
1494         filter_info->flex_mask = 0;
1495
1496         /* Remove all ntuple filters of the device */
1497         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1498              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1499                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1500                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1501                              p_5tuple, entries);
1502                 rte_free(p_5tuple);
1503         }
1504         filter_info->fivetuple_mask = 0;
1505         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1506              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1507                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1508                 TAILQ_REMOVE(&filter_info->twotuple_list,
1509                              p_2tuple, entries);
1510                 rte_free(p_2tuple);
1511         }
1512         filter_info->twotuple_mask = 0;
1513
1514         if (!rte_intr_allow_others(intr_handle))
1515                 /* resume to the default handler */
1516                 rte_intr_callback_register(intr_handle,
1517                                            eth_igb_interrupt_handler,
1518                                            (void *)dev);
1519
1520         /* Clean datapath event and queue/vec mapping */
1521         rte_intr_efd_disable(intr_handle);
1522         if (intr_handle->intr_vec != NULL) {
1523                 rte_free(intr_handle->intr_vec);
1524                 intr_handle->intr_vec = NULL;
1525         }
1526 }
1527
1528 static int
1529 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1530 {
1531         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532
1533         if (hw->phy.media_type == e1000_media_type_copper)
1534                 e1000_power_up_phy(hw);
1535         else
1536                 e1000_power_up_fiber_serdes_link(hw);
1537
1538         return 0;
1539 }
1540
1541 static int
1542 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1543 {
1544         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545
1546         if (hw->phy.media_type == e1000_media_type_copper)
1547                 e1000_power_down_phy(hw);
1548         else
1549                 e1000_shutdown_fiber_serdes_link(hw);
1550
1551         return 0;
1552 }
1553
1554 static void
1555 eth_igb_close(struct rte_eth_dev *dev)
1556 {
1557         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1558         struct e1000_adapter *adapter =
1559                 E1000_DEV_PRIVATE(dev->data->dev_private);
1560         struct rte_eth_link link;
1561         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1562         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563
1564         eth_igb_stop(dev);
1565         adapter->stopped = 1;
1566
1567         e1000_phy_hw_reset(hw);
1568         igb_release_manageability(hw);
1569         igb_hw_control_release(hw);
1570
1571         /* Clear bit for Go Link disconnect */
1572         if (hw->mac.type >= e1000_82580) {
1573                 uint32_t phpm_reg;
1574
1575                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1576                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1577                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1578         }
1579
1580         igb_dev_free_queues(dev);
1581
1582         if (intr_handle->intr_vec) {
1583                 rte_free(intr_handle->intr_vec);
1584                 intr_handle->intr_vec = NULL;
1585         }
1586
1587         memset(&link, 0, sizeof(link));
1588         rte_igb_dev_atomic_write_link_status(dev, &link);
1589 }
1590
1591 static int
1592 igb_get_rx_buffer_size(struct e1000_hw *hw)
1593 {
1594         uint32_t rx_buf_size;
1595         if (hw->mac.type == e1000_82576) {
1596                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1597         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1598                 /* PBS needs to be translated according to a lookup table */
1599                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1600                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1601                 rx_buf_size = (rx_buf_size << 10);
1602         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1603                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1604         } else {
1605                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1606         }
1607
1608         return rx_buf_size;
1609 }
1610
1611 /*********************************************************************
1612  *
1613  *  Initialize the hardware
1614  *
1615  **********************************************************************/
1616 static int
1617 igb_hardware_init(struct e1000_hw *hw)
1618 {
1619         uint32_t rx_buf_size;
1620         int diag;
1621
1622         /* Let the firmware know the OS is in control */
1623         igb_hw_control_acquire(hw);
1624
1625         /*
1626          * These parameters control the automatic generation (Tx) and
1627          * response (Rx) to Ethernet PAUSE frames.
1628          * - High water mark should allow for at least two standard size (1518)
1629          *   frames to be received after sending an XOFF.
1630          * - Low water mark works best when it is very near the high water mark.
1631          *   This allows the receiver to restart by sending XON when it has
1632          *   drained a bit. Here we use an arbitrary value of 1500 which will
1633          *   restart after one full frame is pulled from the buffer. There
1634          *   could be several smaller frames in the buffer and if so they will
1635          *   not trigger the XON until their total number reduces the buffer
1636          *   by 1500.
1637          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1638          */
1639         rx_buf_size = igb_get_rx_buffer_size(hw);
1640
1641         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1642         hw->fc.low_water = hw->fc.high_water - 1500;
1643         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1644         hw->fc.send_xon = 1;
1645
1646         /* Set Flow control, use the tunable location if sane */
1647         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1648                 hw->fc.requested_mode = igb_fc_setting;
1649         else
1650                 hw->fc.requested_mode = e1000_fc_none;
1651
1652         /* Issue a global reset */
1653         igb_pf_reset_hw(hw);
1654         E1000_WRITE_REG(hw, E1000_WUC, 0);
1655
1656         diag = e1000_init_hw(hw);
1657         if (diag < 0)
1658                 return diag;
1659
1660         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1661         e1000_get_phy_info(hw);
1662         e1000_check_for_link(hw);
1663
1664         return 0;
1665 }
1666
1667 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1668 static void
1669 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1670 {
1671         int pause_frames;
1672
1673         uint64_t old_gprc  = stats->gprc;
1674         uint64_t old_gptc  = stats->gptc;
1675         uint64_t old_tpr   = stats->tpr;
1676         uint64_t old_tpt   = stats->tpt;
1677         uint64_t old_rpthc = stats->rpthc;
1678         uint64_t old_hgptc = stats->hgptc;
1679
1680         if(hw->phy.media_type == e1000_media_type_copper ||
1681             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1682                 stats->symerrs +=
1683                     E1000_READ_REG(hw,E1000_SYMERRS);
1684                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1685         }
1686
1687         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1688         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1689         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1690         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1691
1692         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1693         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1694         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1695         stats->dc += E1000_READ_REG(hw, E1000_DC);
1696         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1697         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1698         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1699         /*
1700         ** For watchdog management we need to know if we have been
1701         ** paused during the last interval, so capture that here.
1702         */
1703         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1704         stats->xoffrxc += pause_frames;
1705         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1706         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1707         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1708         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1709         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1710         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1711         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1712         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1713         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1714         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1715         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1716         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1717
1718         /* For the 64-bit byte counters the low dword must be read first. */
1719         /* Both registers clear on the read of the high dword */
1720
1721         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1722         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1723         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1724         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1725         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1726         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1727         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1728
1729         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1730         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1731         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1732         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1733         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1734
1735         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1736         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1737
1738         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1739         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1740         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1741         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1742         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1743         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1744
1745         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1746         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1747         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1748         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1749         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1750         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1751         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1752         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1753
1754         /* Interrupt Counts */
1755
1756         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1757         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1758         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1759         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1760         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1761         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1762         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1763         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1764         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1765
1766         /* Host to Card Statistics */
1767
1768         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1769         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1770         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1771         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1772         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1773         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1774         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1775         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1776         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1777         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1778         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1779         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1780         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1781         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1782         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1783         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1784
1785         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1786         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1787         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1788         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1789         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1790         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1791 }
1792
1793 static void
1794 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1795 {
1796         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         struct e1000_hw_stats *stats =
1798                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1799
1800         igb_read_stats_registers(hw, stats);
1801
1802         if (rte_stats == NULL)
1803                 return;
1804
1805         /* Rx Errors */
1806         rte_stats->imissed = stats->mpc;
1807         rte_stats->ierrors = stats->crcerrs +
1808                              stats->rlec + stats->ruc + stats->roc +
1809                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1810
1811         /* Tx Errors */
1812         rte_stats->oerrors = stats->ecol + stats->latecol;
1813
1814         rte_stats->ipackets = stats->gprc;
1815         rte_stats->opackets = stats->gptc;
1816         rte_stats->ibytes   = stats->gorc;
1817         rte_stats->obytes   = stats->gotc;
1818 }
1819
1820 static void
1821 eth_igb_stats_reset(struct rte_eth_dev *dev)
1822 {
1823         struct e1000_hw_stats *hw_stats =
1824                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1825
1826         /* HW registers are cleared on read */
1827         eth_igb_stats_get(dev, NULL);
1828
1829         /* Reset software totals */
1830         memset(hw_stats, 0, sizeof(*hw_stats));
1831 }
1832
1833 static void
1834 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1835 {
1836         struct e1000_hw_stats *stats =
1837                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1838
1839         /* HW registers are cleared on read */
1840         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1841
1842         /* Reset software totals */
1843         memset(stats, 0, sizeof(*stats));
1844 }
1845
1846 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1847         struct rte_eth_xstat_name *xstats_names,
1848         __rte_unused unsigned limit)
1849 {
1850         unsigned i;
1851
1852         if (xstats_names == NULL)
1853                 return IGB_NB_XSTATS;
1854
1855         /* Note: limit checked in rte_eth_xstats_names() */
1856
1857         for (i = 0; i < IGB_NB_XSTATS; i++) {
1858                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1859                          "%s", rte_igb_stats_strings[i].name);
1860         }
1861
1862         return IGB_NB_XSTATS;
1863 }
1864
1865 static int
1866 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1867                    unsigned n)
1868 {
1869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct e1000_hw_stats *hw_stats =
1871                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1872         unsigned i;
1873
1874         if (n < IGB_NB_XSTATS)
1875                 return IGB_NB_XSTATS;
1876
1877         igb_read_stats_registers(hw, hw_stats);
1878
1879         /* If this is a reset xstats is NULL, and we have cleared the
1880          * registers by reading them.
1881          */
1882         if (!xstats)
1883                 return 0;
1884
1885         /* Extended stats */
1886         for (i = 0; i < IGB_NB_XSTATS; i++) {
1887                 xstats[i].id = i;
1888                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1889                         rte_igb_stats_strings[i].offset);
1890         }
1891
1892         return IGB_NB_XSTATS;
1893 }
1894
1895 static void
1896 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1897 {
1898         /* Good Rx packets, include VF loopback */
1899         UPDATE_VF_STAT(E1000_VFGPRC,
1900             hw_stats->last_gprc, hw_stats->gprc);
1901
1902         /* Good Rx octets, include VF loopback */
1903         UPDATE_VF_STAT(E1000_VFGORC,
1904             hw_stats->last_gorc, hw_stats->gorc);
1905
1906         /* Good Tx packets, include VF loopback */
1907         UPDATE_VF_STAT(E1000_VFGPTC,
1908             hw_stats->last_gptc, hw_stats->gptc);
1909
1910         /* Good Tx octets, include VF loopback */
1911         UPDATE_VF_STAT(E1000_VFGOTC,
1912             hw_stats->last_gotc, hw_stats->gotc);
1913
1914         /* Rx Multicst packets */
1915         UPDATE_VF_STAT(E1000_VFMPRC,
1916             hw_stats->last_mprc, hw_stats->mprc);
1917
1918         /* Good Rx loopback packets */
1919         UPDATE_VF_STAT(E1000_VFGPRLBC,
1920             hw_stats->last_gprlbc, hw_stats->gprlbc);
1921
1922         /* Good Rx loopback octets */
1923         UPDATE_VF_STAT(E1000_VFGORLBC,
1924             hw_stats->last_gorlbc, hw_stats->gorlbc);
1925
1926         /* Good Tx loopback packets */
1927         UPDATE_VF_STAT(E1000_VFGPTLBC,
1928             hw_stats->last_gptlbc, hw_stats->gptlbc);
1929
1930         /* Good Tx loopback octets */
1931         UPDATE_VF_STAT(E1000_VFGOTLBC,
1932             hw_stats->last_gotlbc, hw_stats->gotlbc);
1933 }
1934
1935 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1936                                      struct rte_eth_xstat_name *xstats_names,
1937                                      __rte_unused unsigned limit)
1938 {
1939         unsigned i;
1940
1941         if (xstats_names != NULL)
1942                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1943                         snprintf(xstats_names[i].name,
1944                                 sizeof(xstats_names[i].name), "%s",
1945                                 rte_igbvf_stats_strings[i].name);
1946                 }
1947         return IGBVF_NB_XSTATS;
1948 }
1949
1950 static int
1951 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1952                      unsigned n)
1953 {
1954         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1956                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1957         unsigned i;
1958
1959         if (n < IGBVF_NB_XSTATS)
1960                 return IGBVF_NB_XSTATS;
1961
1962         igbvf_read_stats_registers(hw, hw_stats);
1963
1964         if (!xstats)
1965                 return 0;
1966
1967         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1968                 xstats[i].id = i;
1969                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1970                         rte_igbvf_stats_strings[i].offset);
1971         }
1972
1973         return IGBVF_NB_XSTATS;
1974 }
1975
1976 static void
1977 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1978 {
1979         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1981                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1982
1983         igbvf_read_stats_registers(hw, hw_stats);
1984
1985         if (rte_stats == NULL)
1986                 return;
1987
1988         rte_stats->ipackets = hw_stats->gprc;
1989         rte_stats->ibytes = hw_stats->gorc;
1990         rte_stats->opackets = hw_stats->gptc;
1991         rte_stats->obytes = hw_stats->gotc;
1992 }
1993
1994 static void
1995 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1996 {
1997         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1998                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1999
2000         /* Sync HW register to the last stats */
2001         eth_igbvf_stats_get(dev, NULL);
2002
2003         /* reset HW current stats*/
2004         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2005                offsetof(struct e1000_vf_stats, gprc));
2006 }
2007
2008 static int
2009 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2010                        size_t fw_size)
2011 {
2012         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         struct e1000_fw_version fw;
2014         int ret;
2015
2016         e1000_get_fw_version(hw, &fw);
2017
2018         switch (hw->mac.type) {
2019         case e1000_i210:
2020         case e1000_i211:
2021                 if (!(e1000_get_flash_presence_i210(hw))) {
2022                         ret = snprintf(fw_version, fw_size,
2023                                  "%2d.%2d-%d",
2024                                  fw.invm_major, fw.invm_minor,
2025                                  fw.invm_img_type);
2026                         break;
2027                 }
2028                 /* fall through */
2029         default:
2030                 /* if option rom is valid, display its version too */
2031                 if (fw.or_valid) {
2032                         ret = snprintf(fw_version, fw_size,
2033                                  "%d.%d, 0x%08x, %d.%d.%d",
2034                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2035                                  fw.or_major, fw.or_build, fw.or_patch);
2036                 /* no option rom */
2037                 } else {
2038                         if (fw.etrack_id != 0X0000) {
2039                                 ret = snprintf(fw_version, fw_size,
2040                                          "%d.%d, 0x%08x",
2041                                          fw.eep_major, fw.eep_minor,
2042                                          fw.etrack_id);
2043                         } else {
2044                                 ret = snprintf(fw_version, fw_size,
2045                                          "%d.%d.%d",
2046                                          fw.eep_major, fw.eep_minor,
2047                                          fw.eep_build);
2048                         }
2049                 }
2050                 break;
2051         }
2052
2053         ret += 1; /* add the size of '\0' */
2054         if (fw_size < (u32)ret)
2055                 return ret;
2056         else
2057                 return 0;
2058 }
2059
2060 static void
2061 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2062 {
2063         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064
2065         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2066         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2067         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2068         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2069         dev_info->rx_offload_capa =
2070                 DEV_RX_OFFLOAD_VLAN_STRIP |
2071                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2072                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2073                 DEV_RX_OFFLOAD_TCP_CKSUM;
2074         dev_info->tx_offload_capa =
2075                 DEV_TX_OFFLOAD_VLAN_INSERT |
2076                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2077                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2078                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2079                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2080                 DEV_TX_OFFLOAD_TCP_TSO;
2081
2082         switch (hw->mac.type) {
2083         case e1000_82575:
2084                 dev_info->max_rx_queues = 4;
2085                 dev_info->max_tx_queues = 4;
2086                 dev_info->max_vmdq_pools = 0;
2087                 break;
2088
2089         case e1000_82576:
2090                 dev_info->max_rx_queues = 16;
2091                 dev_info->max_tx_queues = 16;
2092                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2093                 dev_info->vmdq_queue_num = 16;
2094                 break;
2095
2096         case e1000_82580:
2097                 dev_info->max_rx_queues = 8;
2098                 dev_info->max_tx_queues = 8;
2099                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2100                 dev_info->vmdq_queue_num = 8;
2101                 break;
2102
2103         case e1000_i350:
2104                 dev_info->max_rx_queues = 8;
2105                 dev_info->max_tx_queues = 8;
2106                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2107                 dev_info->vmdq_queue_num = 8;
2108                 break;
2109
2110         case e1000_i354:
2111                 dev_info->max_rx_queues = 8;
2112                 dev_info->max_tx_queues = 8;
2113                 break;
2114
2115         case e1000_i210:
2116                 dev_info->max_rx_queues = 4;
2117                 dev_info->max_tx_queues = 4;
2118                 dev_info->max_vmdq_pools = 0;
2119                 break;
2120
2121         case e1000_i211:
2122                 dev_info->max_rx_queues = 2;
2123                 dev_info->max_tx_queues = 2;
2124                 dev_info->max_vmdq_pools = 0;
2125                 break;
2126
2127         default:
2128                 /* Should not happen */
2129                 break;
2130         }
2131         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2132         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2133         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2134
2135         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2136                 .rx_thresh = {
2137                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2138                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2139                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2140                 },
2141                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2142                 .rx_drop_en = 0,
2143         };
2144
2145         dev_info->default_txconf = (struct rte_eth_txconf) {
2146                 .tx_thresh = {
2147                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2148                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2149                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2150                 },
2151                 .txq_flags = 0,
2152         };
2153
2154         dev_info->rx_desc_lim = rx_desc_lim;
2155         dev_info->tx_desc_lim = tx_desc_lim;
2156
2157         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2158                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2159                         ETH_LINK_SPEED_1G;
2160 }
2161
2162 static const uint32_t *
2163 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2164 {
2165         static const uint32_t ptypes[] = {
2166                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2167                 RTE_PTYPE_L2_ETHER,
2168                 RTE_PTYPE_L3_IPV4,
2169                 RTE_PTYPE_L3_IPV4_EXT,
2170                 RTE_PTYPE_L3_IPV6,
2171                 RTE_PTYPE_L3_IPV6_EXT,
2172                 RTE_PTYPE_L4_TCP,
2173                 RTE_PTYPE_L4_UDP,
2174                 RTE_PTYPE_L4_SCTP,
2175                 RTE_PTYPE_TUNNEL_IP,
2176                 RTE_PTYPE_INNER_L3_IPV6,
2177                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2178                 RTE_PTYPE_INNER_L4_TCP,
2179                 RTE_PTYPE_INNER_L4_UDP,
2180                 RTE_PTYPE_UNKNOWN
2181         };
2182
2183         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2184             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2185                 return ptypes;
2186         return NULL;
2187 }
2188
2189 static void
2190 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2191 {
2192         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193
2194         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2195         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2196         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2197         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2198         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2199                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2200                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2201                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2202         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2203                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2204                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2205                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2206                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2207                                 DEV_TX_OFFLOAD_TCP_TSO;
2208         switch (hw->mac.type) {
2209         case e1000_vfadapt:
2210                 dev_info->max_rx_queues = 2;
2211                 dev_info->max_tx_queues = 2;
2212                 break;
2213         case e1000_vfadapt_i350:
2214                 dev_info->max_rx_queues = 1;
2215                 dev_info->max_tx_queues = 1;
2216                 break;
2217         default:
2218                 /* Should not happen */
2219                 break;
2220         }
2221
2222         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2223                 .rx_thresh = {
2224                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2225                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2226                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2227                 },
2228                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2229                 .rx_drop_en = 0,
2230         };
2231
2232         dev_info->default_txconf = (struct rte_eth_txconf) {
2233                 .tx_thresh = {
2234                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2235                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2236                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2237                 },
2238                 .txq_flags = 0,
2239         };
2240
2241         dev_info->rx_desc_lim = rx_desc_lim;
2242         dev_info->tx_desc_lim = tx_desc_lim;
2243 }
2244
2245 /* return 0 means link status changed, -1 means not changed */
2246 static int
2247 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2248 {
2249         struct e1000_hw *hw =
2250                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         struct rte_eth_link link, old;
2252         int link_check, count;
2253
2254         link_check = 0;
2255         hw->mac.get_link_status = 1;
2256
2257         /* possible wait-to-complete in up to 9 seconds */
2258         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2259                 /* Read the real link status */
2260                 switch (hw->phy.media_type) {
2261                 case e1000_media_type_copper:
2262                         /* Do the work to read phy */
2263                         e1000_check_for_link(hw);
2264                         link_check = !hw->mac.get_link_status;
2265                         break;
2266
2267                 case e1000_media_type_fiber:
2268                         e1000_check_for_link(hw);
2269                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2270                                       E1000_STATUS_LU);
2271                         break;
2272
2273                 case e1000_media_type_internal_serdes:
2274                         e1000_check_for_link(hw);
2275                         link_check = hw->mac.serdes_has_link;
2276                         break;
2277
2278                 /* VF device is type_unknown */
2279                 case e1000_media_type_unknown:
2280                         eth_igbvf_link_update(hw);
2281                         link_check = !hw->mac.get_link_status;
2282                         break;
2283
2284                 default:
2285                         break;
2286                 }
2287                 if (link_check || wait_to_complete == 0)
2288                         break;
2289                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2290         }
2291         memset(&link, 0, sizeof(link));
2292         rte_igb_dev_atomic_read_link_status(dev, &link);
2293         old = link;
2294
2295         /* Now we check if a transition has happened */
2296         if (link_check) {
2297                 uint16_t duplex, speed;
2298                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2299                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2300                                 ETH_LINK_FULL_DUPLEX :
2301                                 ETH_LINK_HALF_DUPLEX;
2302                 link.link_speed = speed;
2303                 link.link_status = ETH_LINK_UP;
2304                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2305                                 ETH_LINK_SPEED_FIXED);
2306         } else if (!link_check) {
2307                 link.link_speed = 0;
2308                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2309                 link.link_status = ETH_LINK_DOWN;
2310                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2311         }
2312         rte_igb_dev_atomic_write_link_status(dev, &link);
2313
2314         /* not changed */
2315         if (old.link_status == link.link_status)
2316                 return -1;
2317
2318         /* changed */
2319         return 0;
2320 }
2321
2322 /*
2323  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2324  * For ASF and Pass Through versions of f/w this means
2325  * that the driver is loaded.
2326  */
2327 static void
2328 igb_hw_control_acquire(struct e1000_hw *hw)
2329 {
2330         uint32_t ctrl_ext;
2331
2332         /* Let firmware know the driver has taken over */
2333         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2334         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2335 }
2336
2337 /*
2338  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2339  * For ASF and Pass Through versions of f/w this means that the
2340  * driver is no longer loaded.
2341  */
2342 static void
2343 igb_hw_control_release(struct e1000_hw *hw)
2344 {
2345         uint32_t ctrl_ext;
2346
2347         /* Let firmware taken over control of h/w */
2348         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2349         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2350                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2351 }
2352
2353 /*
2354  * Bit of a misnomer, what this really means is
2355  * to enable OS management of the system... aka
2356  * to disable special hardware management features.
2357  */
2358 static void
2359 igb_init_manageability(struct e1000_hw *hw)
2360 {
2361         if (e1000_enable_mng_pass_thru(hw)) {
2362                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2363                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2364
2365                 /* disable hardware interception of ARP */
2366                 manc &= ~(E1000_MANC_ARP_EN);
2367
2368                 /* enable receiving management packets to the host */
2369                 manc |= E1000_MANC_EN_MNG2HOST;
2370                 manc2h |= 1 << 5;  /* Mng Port 623 */
2371                 manc2h |= 1 << 6;  /* Mng Port 664 */
2372                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2373                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2374         }
2375 }
2376
2377 static void
2378 igb_release_manageability(struct e1000_hw *hw)
2379 {
2380         if (e1000_enable_mng_pass_thru(hw)) {
2381                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2382
2383                 manc |= E1000_MANC_ARP_EN;
2384                 manc &= ~E1000_MANC_EN_MNG2HOST;
2385
2386                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2387         }
2388 }
2389
2390 static void
2391 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2392 {
2393         struct e1000_hw *hw =
2394                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         uint32_t rctl;
2396
2397         rctl = E1000_READ_REG(hw, E1000_RCTL);
2398         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2399         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2400 }
2401
2402 static void
2403 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2404 {
2405         struct e1000_hw *hw =
2406                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         uint32_t rctl;
2408
2409         rctl = E1000_READ_REG(hw, E1000_RCTL);
2410         rctl &= (~E1000_RCTL_UPE);
2411         if (dev->data->all_multicast == 1)
2412                 rctl |= E1000_RCTL_MPE;
2413         else
2414                 rctl &= (~E1000_RCTL_MPE);
2415         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2416 }
2417
2418 static void
2419 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2420 {
2421         struct e1000_hw *hw =
2422                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         uint32_t rctl;
2424
2425         rctl = E1000_READ_REG(hw, E1000_RCTL);
2426         rctl |= E1000_RCTL_MPE;
2427         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2428 }
2429
2430 static void
2431 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2432 {
2433         struct e1000_hw *hw =
2434                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         uint32_t rctl;
2436
2437         if (dev->data->promiscuous == 1)
2438                 return; /* must remain in all_multicast mode */
2439         rctl = E1000_READ_REG(hw, E1000_RCTL);
2440         rctl &= (~E1000_RCTL_MPE);
2441         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2442 }
2443
2444 static int
2445 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2446 {
2447         struct e1000_hw *hw =
2448                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449         struct e1000_vfta * shadow_vfta =
2450                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2451         uint32_t vfta;
2452         uint32_t vid_idx;
2453         uint32_t vid_bit;
2454
2455         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2456                               E1000_VFTA_ENTRY_MASK);
2457         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2458         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2459         if (on)
2460                 vfta |= vid_bit;
2461         else
2462                 vfta &= ~vid_bit;
2463         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2464
2465         /* update local VFTA copy */
2466         shadow_vfta->vfta[vid_idx] = vfta;
2467
2468         return 0;
2469 }
2470
2471 static int
2472 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2473                       enum rte_vlan_type vlan_type,
2474                       uint16_t tpid)
2475 {
2476         struct e1000_hw *hw =
2477                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478         uint32_t reg, qinq;
2479
2480         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2481         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2482
2483         /* only outer TPID of double VLAN can be configured*/
2484         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2485                 reg = E1000_READ_REG(hw, E1000_VET);
2486                 reg = (reg & (~E1000_VET_VET_EXT)) |
2487                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2488                 E1000_WRITE_REG(hw, E1000_VET, reg);
2489
2490                 return 0;
2491         }
2492
2493         /* all other TPID values are read-only*/
2494         PMD_DRV_LOG(ERR, "Not supported");
2495
2496         return -ENOTSUP;
2497 }
2498
2499 static void
2500 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2501 {
2502         struct e1000_hw *hw =
2503                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504         uint32_t reg;
2505
2506         /* Filter Table Disable */
2507         reg = E1000_READ_REG(hw, E1000_RCTL);
2508         reg &= ~E1000_RCTL_CFIEN;
2509         reg &= ~E1000_RCTL_VFE;
2510         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2511 }
2512
2513 static void
2514 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2515 {
2516         struct e1000_hw *hw =
2517                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518         struct e1000_vfta * shadow_vfta =
2519                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2520         uint32_t reg;
2521         int i;
2522
2523         /* Filter Table Enable, CFI not used for packet acceptance */
2524         reg = E1000_READ_REG(hw, E1000_RCTL);
2525         reg &= ~E1000_RCTL_CFIEN;
2526         reg |= E1000_RCTL_VFE;
2527         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2528
2529         /* restore VFTA table */
2530         for (i = 0; i < IGB_VFTA_SIZE; i++)
2531                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2532 }
2533
2534 static void
2535 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2536 {
2537         struct e1000_hw *hw =
2538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         uint32_t reg;
2540
2541         /* VLAN Mode Disable */
2542         reg = E1000_READ_REG(hw, E1000_CTRL);
2543         reg &= ~E1000_CTRL_VME;
2544         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2545 }
2546
2547 static void
2548 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2549 {
2550         struct e1000_hw *hw =
2551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         uint32_t reg;
2553
2554         /* VLAN Mode Enable */
2555         reg = E1000_READ_REG(hw, E1000_CTRL);
2556         reg |= E1000_CTRL_VME;
2557         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2558 }
2559
2560 static void
2561 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2562 {
2563         struct e1000_hw *hw =
2564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2565         uint32_t reg;
2566
2567         /* CTRL_EXT: Extended VLAN */
2568         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2569         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2570         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2571
2572         /* Update maximum packet length */
2573         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2574                 E1000_WRITE_REG(hw, E1000_RLPML,
2575                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2576                                                 VLAN_TAG_SIZE);
2577 }
2578
2579 static void
2580 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2581 {
2582         struct e1000_hw *hw =
2583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584         uint32_t reg;
2585
2586         /* CTRL_EXT: Extended VLAN */
2587         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2588         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2589         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2590
2591         /* Update maximum packet length */
2592         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2593                 E1000_WRITE_REG(hw, E1000_RLPML,
2594                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2595                                                 2 * VLAN_TAG_SIZE);
2596 }
2597
2598 static void
2599 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2600 {
2601         if(mask & ETH_VLAN_STRIP_MASK){
2602                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2603                         igb_vlan_hw_strip_enable(dev);
2604                 else
2605                         igb_vlan_hw_strip_disable(dev);
2606         }
2607
2608         if(mask & ETH_VLAN_FILTER_MASK){
2609                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2610                         igb_vlan_hw_filter_enable(dev);
2611                 else
2612                         igb_vlan_hw_filter_disable(dev);
2613         }
2614
2615         if(mask & ETH_VLAN_EXTEND_MASK){
2616                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2617                         igb_vlan_hw_extend_enable(dev);
2618                 else
2619                         igb_vlan_hw_extend_disable(dev);
2620         }
2621 }
2622
2623
2624 /**
2625  * It enables the interrupt mask and then enable the interrupt.
2626  *
2627  * @param dev
2628  *  Pointer to struct rte_eth_dev.
2629  *
2630  * @return
2631  *  - On success, zero.
2632  *  - On failure, a negative value.
2633  */
2634 static int
2635 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2636 {
2637         struct e1000_interrupt *intr =
2638                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2639
2640         intr->mask |= E1000_ICR_LSC;
2641
2642         return 0;
2643 }
2644
2645 /* It clears the interrupt causes and enables the interrupt.
2646  * It will be called once only during nic initialized.
2647  *
2648  * @param dev
2649  *  Pointer to struct rte_eth_dev.
2650  *
2651  * @return
2652  *  - On success, zero.
2653  *  - On failure, a negative value.
2654  */
2655 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2656 {
2657         uint32_t mask, regval;
2658         struct e1000_hw *hw =
2659                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660         struct rte_eth_dev_info dev_info;
2661
2662         memset(&dev_info, 0, sizeof(dev_info));
2663         eth_igb_infos_get(dev, &dev_info);
2664
2665         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2666         regval = E1000_READ_REG(hw, E1000_EIMS);
2667         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2668
2669         return 0;
2670 }
2671
2672 /*
2673  * It reads ICR and gets interrupt causes, check it and set a bit flag
2674  * to update link status.
2675  *
2676  * @param dev
2677  *  Pointer to struct rte_eth_dev.
2678  *
2679  * @return
2680  *  - On success, zero.
2681  *  - On failure, a negative value.
2682  */
2683 static int
2684 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2685 {
2686         uint32_t icr;
2687         struct e1000_hw *hw =
2688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         struct e1000_interrupt *intr =
2690                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2691
2692         igb_intr_disable(hw);
2693
2694         /* read-on-clear nic registers here */
2695         icr = E1000_READ_REG(hw, E1000_ICR);
2696
2697         intr->flags = 0;
2698         if (icr & E1000_ICR_LSC) {
2699                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2700         }
2701
2702         if (icr & E1000_ICR_VMMB)
2703                 intr->flags |= E1000_FLAG_MAILBOX;
2704
2705         return 0;
2706 }
2707
2708 /*
2709  * It executes link_update after knowing an interrupt is prsent.
2710  *
2711  * @param dev
2712  *  Pointer to struct rte_eth_dev.
2713  *
2714  * @return
2715  *  - On success, zero.
2716  *  - On failure, a negative value.
2717  */
2718 static int
2719 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2720                          struct rte_intr_handle *intr_handle)
2721 {
2722         struct e1000_hw *hw =
2723                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct e1000_interrupt *intr =
2725                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2726         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2727         uint32_t tctl, rctl;
2728         struct rte_eth_link link;
2729         int ret;
2730
2731         if (intr->flags & E1000_FLAG_MAILBOX) {
2732                 igb_pf_mbx_process(dev);
2733                 intr->flags &= ~E1000_FLAG_MAILBOX;
2734         }
2735
2736         igb_intr_enable(dev);
2737         rte_intr_enable(intr_handle);
2738
2739         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2740                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2741
2742                 /* set get_link_status to check register later */
2743                 hw->mac.get_link_status = 1;
2744                 ret = eth_igb_link_update(dev, 0);
2745
2746                 /* check if link has changed */
2747                 if (ret < 0)
2748                         return 0;
2749
2750                 memset(&link, 0, sizeof(link));
2751                 rte_igb_dev_atomic_read_link_status(dev, &link);
2752                 if (link.link_status) {
2753                         PMD_INIT_LOG(INFO,
2754                                      " Port %d: Link Up - speed %u Mbps - %s",
2755                                      dev->data->port_id,
2756                                      (unsigned)link.link_speed,
2757                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2758                                      "full-duplex" : "half-duplex");
2759                 } else {
2760                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2761                                      dev->data->port_id);
2762                 }
2763
2764                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2765                              pci_dev->addr.domain,
2766                              pci_dev->addr.bus,
2767                              pci_dev->addr.devid,
2768                              pci_dev->addr.function);
2769                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2770                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2771                 if (link.link_status) {
2772                         /* enable Tx/Rx */
2773                         tctl |= E1000_TCTL_EN;
2774                         rctl |= E1000_RCTL_EN;
2775                 } else {
2776                         /* disable Tx/Rx */
2777                         tctl &= ~E1000_TCTL_EN;
2778                         rctl &= ~E1000_RCTL_EN;
2779                 }
2780                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2781                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2782                 E1000_WRITE_FLUSH(hw);
2783                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2784         }
2785
2786         return 0;
2787 }
2788
2789 /**
2790  * Interrupt handler which shall be registered at first.
2791  *
2792  * @param handle
2793  *  Pointer to interrupt handle.
2794  * @param param
2795  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2796  *
2797  * @return
2798  *  void
2799  */
2800 static void
2801 eth_igb_interrupt_handler(void *param)
2802 {
2803         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2804
2805         eth_igb_interrupt_get_status(dev);
2806         eth_igb_interrupt_action(dev, dev->intr_handle);
2807 }
2808
2809 static int
2810 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2811 {
2812         uint32_t eicr;
2813         struct e1000_hw *hw =
2814                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         struct e1000_interrupt *intr =
2816                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2817
2818         igbvf_intr_disable(hw);
2819
2820         /* read-on-clear nic registers here */
2821         eicr = E1000_READ_REG(hw, E1000_EICR);
2822         intr->flags = 0;
2823
2824         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2825                 intr->flags |= E1000_FLAG_MAILBOX;
2826
2827         return 0;
2828 }
2829
2830 void igbvf_mbx_process(struct rte_eth_dev *dev)
2831 {
2832         struct e1000_hw *hw =
2833                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834         struct e1000_mbx_info *mbx = &hw->mbx;
2835         u32 in_msg = 0;
2836
2837         if (mbx->ops.read(hw, &in_msg, 1, 0))
2838                 return;
2839
2840         /* PF reset VF event */
2841         if (in_msg == E1000_PF_CONTROL_MSG)
2842                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2843 }
2844
2845 static int
2846 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2847 {
2848         struct e1000_interrupt *intr =
2849                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2850
2851         if (intr->flags & E1000_FLAG_MAILBOX) {
2852                 igbvf_mbx_process(dev);
2853                 intr->flags &= ~E1000_FLAG_MAILBOX;
2854         }
2855
2856         igbvf_intr_enable(dev);
2857         rte_intr_enable(intr_handle);
2858
2859         return 0;
2860 }
2861
2862 static void
2863 eth_igbvf_interrupt_handler(void *param)
2864 {
2865         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2866
2867         eth_igbvf_interrupt_get_status(dev);
2868         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2869 }
2870
2871 static int
2872 eth_igb_led_on(struct rte_eth_dev *dev)
2873 {
2874         struct e1000_hw *hw;
2875
2876         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2878 }
2879
2880 static int
2881 eth_igb_led_off(struct rte_eth_dev *dev)
2882 {
2883         struct e1000_hw *hw;
2884
2885         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2887 }
2888
2889 static int
2890 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2891 {
2892         struct e1000_hw *hw;
2893         uint32_t ctrl;
2894         int tx_pause;
2895         int rx_pause;
2896
2897         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         fc_conf->pause_time = hw->fc.pause_time;
2899         fc_conf->high_water = hw->fc.high_water;
2900         fc_conf->low_water = hw->fc.low_water;
2901         fc_conf->send_xon = hw->fc.send_xon;
2902         fc_conf->autoneg = hw->mac.autoneg;
2903
2904         /*
2905          * Return rx_pause and tx_pause status according to actual setting of
2906          * the TFCE and RFCE bits in the CTRL register.
2907          */
2908         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2909         if (ctrl & E1000_CTRL_TFCE)
2910                 tx_pause = 1;
2911         else
2912                 tx_pause = 0;
2913
2914         if (ctrl & E1000_CTRL_RFCE)
2915                 rx_pause = 1;
2916         else
2917                 rx_pause = 0;
2918
2919         if (rx_pause && tx_pause)
2920                 fc_conf->mode = RTE_FC_FULL;
2921         else if (rx_pause)
2922                 fc_conf->mode = RTE_FC_RX_PAUSE;
2923         else if (tx_pause)
2924                 fc_conf->mode = RTE_FC_TX_PAUSE;
2925         else
2926                 fc_conf->mode = RTE_FC_NONE;
2927
2928         return 0;
2929 }
2930
2931 static int
2932 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2933 {
2934         struct e1000_hw *hw;
2935         int err;
2936         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2937                 e1000_fc_none,
2938                 e1000_fc_rx_pause,
2939                 e1000_fc_tx_pause,
2940                 e1000_fc_full
2941         };
2942         uint32_t rx_buf_size;
2943         uint32_t max_high_water;
2944         uint32_t rctl;
2945
2946         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947         if (fc_conf->autoneg != hw->mac.autoneg)
2948                 return -ENOTSUP;
2949         rx_buf_size = igb_get_rx_buffer_size(hw);
2950         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2951
2952         /* At least reserve one Ethernet frame for watermark */
2953         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2954         if ((fc_conf->high_water > max_high_water) ||
2955             (fc_conf->high_water < fc_conf->low_water)) {
2956                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2957                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2958                 return -EINVAL;
2959         }
2960
2961         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2962         hw->fc.pause_time     = fc_conf->pause_time;
2963         hw->fc.high_water     = fc_conf->high_water;
2964         hw->fc.low_water      = fc_conf->low_water;
2965         hw->fc.send_xon       = fc_conf->send_xon;
2966
2967         err = e1000_setup_link_generic(hw);
2968         if (err == E1000_SUCCESS) {
2969
2970                 /* check if we want to forward MAC frames - driver doesn't have native
2971                  * capability to do that, so we'll write the registers ourselves */
2972
2973                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2974
2975                 /* set or clear MFLCN.PMCF bit depending on configuration */
2976                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2977                         rctl |= E1000_RCTL_PMCF;
2978                 else
2979                         rctl &= ~E1000_RCTL_PMCF;
2980
2981                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2982                 E1000_WRITE_FLUSH(hw);
2983
2984                 return 0;
2985         }
2986
2987         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2988         return -EIO;
2989 }
2990
2991 #define E1000_RAH_POOLSEL_SHIFT      (18)
2992 static void
2993 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2994                 uint32_t index, __rte_unused uint32_t pool)
2995 {
2996         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2997         uint32_t rah;
2998
2999         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3000         rah = E1000_READ_REG(hw, E1000_RAH(index));
3001         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3002         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3003 }
3004
3005 static void
3006 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3007 {
3008         uint8_t addr[ETHER_ADDR_LEN];
3009         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010
3011         memset(addr, 0, sizeof(addr));
3012
3013         e1000_rar_set(hw, addr, index);
3014 }
3015
3016 static void
3017 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3018                                 struct ether_addr *addr)
3019 {
3020         eth_igb_rar_clear(dev, 0);
3021
3022         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3023 }
3024 /*
3025  * Virtual Function operations
3026  */
3027 static void
3028 igbvf_intr_disable(struct e1000_hw *hw)
3029 {
3030         PMD_INIT_FUNC_TRACE();
3031
3032         /* Clear interrupt mask to stop from interrupts being generated */
3033         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3034
3035         E1000_WRITE_FLUSH(hw);
3036 }
3037
3038 static void
3039 igbvf_stop_adapter(struct rte_eth_dev *dev)
3040 {
3041         u32 reg_val;
3042         u16 i;
3043         struct rte_eth_dev_info dev_info;
3044         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3045
3046         memset(&dev_info, 0, sizeof(dev_info));
3047         eth_igbvf_infos_get(dev, &dev_info);
3048
3049         /* Clear interrupt mask to stop from interrupts being generated */
3050         igbvf_intr_disable(hw);
3051
3052         /* Clear any pending interrupts, flush previous writes */
3053         E1000_READ_REG(hw, E1000_EICR);
3054
3055         /* Disable the transmit unit.  Each queue must be disabled. */
3056         for (i = 0; i < dev_info.max_tx_queues; i++)
3057                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3058
3059         /* Disable the receive unit by stopping each queue */
3060         for (i = 0; i < dev_info.max_rx_queues; i++) {
3061                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3062                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3063                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3064                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3065                         ;
3066         }
3067
3068         /* flush all queues disables */
3069         E1000_WRITE_FLUSH(hw);
3070         msec_delay(2);
3071 }
3072
3073 static int eth_igbvf_link_update(struct e1000_hw *hw)
3074 {
3075         struct e1000_mbx_info *mbx = &hw->mbx;
3076         struct e1000_mac_info *mac = &hw->mac;
3077         int ret_val = E1000_SUCCESS;
3078
3079         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3080
3081         /*
3082          * We only want to run this if there has been a rst asserted.
3083          * in this case that could mean a link change, device reset,
3084          * or a virtual function reset
3085          */
3086
3087         /* If we were hit with a reset or timeout drop the link */
3088         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3089                 mac->get_link_status = TRUE;
3090
3091         if (!mac->get_link_status)
3092                 goto out;
3093
3094         /* if link status is down no point in checking to see if pf is up */
3095         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3096                 goto out;
3097
3098         /* if we passed all the tests above then the link is up and we no
3099          * longer need to check for link */
3100         mac->get_link_status = FALSE;
3101
3102 out:
3103         return ret_val;
3104 }
3105
3106
3107 static int
3108 igbvf_dev_configure(struct rte_eth_dev *dev)
3109 {
3110         struct rte_eth_conf* conf = &dev->data->dev_conf;
3111
3112         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3113                      dev->data->port_id);
3114
3115         /*
3116          * VF has no ability to enable/disable HW CRC
3117          * Keep the persistent behavior the same as Host PF
3118          */
3119 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3120         if (!conf->rxmode.hw_strip_crc) {
3121                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3122                 conf->rxmode.hw_strip_crc = 1;
3123         }
3124 #else
3125         if (conf->rxmode.hw_strip_crc) {
3126                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3127                 conf->rxmode.hw_strip_crc = 0;
3128         }
3129 #endif
3130
3131         return 0;
3132 }
3133
3134 static int
3135 igbvf_dev_start(struct rte_eth_dev *dev)
3136 {
3137         struct e1000_hw *hw =
3138                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139         struct e1000_adapter *adapter =
3140                 E1000_DEV_PRIVATE(dev->data->dev_private);
3141         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3142         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3143         int ret;
3144         uint32_t intr_vector = 0;
3145
3146         PMD_INIT_FUNC_TRACE();
3147
3148         hw->mac.ops.reset_hw(hw);
3149         adapter->stopped = 0;
3150
3151         /* Set all vfta */
3152         igbvf_set_vfta_all(dev,1);
3153
3154         eth_igbvf_tx_init(dev);
3155
3156         /* This can fail when allocating mbufs for descriptor rings */
3157         ret = eth_igbvf_rx_init(dev);
3158         if (ret) {
3159                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3160                 igb_dev_clear_queues(dev);
3161                 return ret;
3162         }
3163
3164         /* check and configure queue intr-vector mapping */
3165         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3166                 intr_vector = dev->data->nb_rx_queues;
3167                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3168                 if (ret)
3169                         return ret;
3170         }
3171
3172         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3173                 intr_handle->intr_vec =
3174                         rte_zmalloc("intr_vec",
3175                                     dev->data->nb_rx_queues * sizeof(int), 0);
3176                 if (!intr_handle->intr_vec) {
3177                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3178                                      " intr_vec", dev->data->nb_rx_queues);
3179                         return -ENOMEM;
3180                 }
3181         }
3182
3183         eth_igbvf_configure_msix_intr(dev);
3184
3185         /* enable uio/vfio intr/eventfd mapping */
3186         rte_intr_enable(intr_handle);
3187
3188         /* resume enabled intr since hw reset */
3189         igbvf_intr_enable(dev);
3190
3191         return 0;
3192 }
3193
3194 static void
3195 igbvf_dev_stop(struct rte_eth_dev *dev)
3196 {
3197         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3198         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3199
3200         PMD_INIT_FUNC_TRACE();
3201
3202         igbvf_stop_adapter(dev);
3203
3204         /*
3205           * Clear what we set, but we still keep shadow_vfta to
3206           * restore after device starts
3207           */
3208         igbvf_set_vfta_all(dev,0);
3209
3210         igb_dev_clear_queues(dev);
3211
3212         /* disable intr eventfd mapping */
3213         rte_intr_disable(intr_handle);
3214
3215         /* Clean datapath event and queue/vec mapping */
3216         rte_intr_efd_disable(intr_handle);
3217         if (intr_handle->intr_vec) {
3218                 rte_free(intr_handle->intr_vec);
3219                 intr_handle->intr_vec = NULL;
3220         }
3221 }
3222
3223 static void
3224 igbvf_dev_close(struct rte_eth_dev *dev)
3225 {
3226         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3227         struct e1000_adapter *adapter =
3228                 E1000_DEV_PRIVATE(dev->data->dev_private);
3229         struct ether_addr addr;
3230
3231         PMD_INIT_FUNC_TRACE();
3232
3233         e1000_reset_hw(hw);
3234
3235         igbvf_dev_stop(dev);
3236         adapter->stopped = 1;
3237         igb_dev_free_queues(dev);
3238
3239         /**
3240          * reprogram the RAR with a zero mac address,
3241          * to ensure that the VF traffic goes to the PF
3242          * after stop, close and detach of the VF.
3243          **/
3244
3245         memset(&addr, 0, sizeof(addr));
3246         igbvf_default_mac_addr_set(dev, &addr);
3247 }
3248
3249 static void
3250 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3251 {
3252         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253
3254         /* Set both unicast and multicast promisc */
3255         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3256 }
3257
3258 static void
3259 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3260 {
3261         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3262
3263         /* If in allmulticast mode leave multicast promisc */
3264         if (dev->data->all_multicast == 1)
3265                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3266         else
3267                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3268 }
3269
3270 static void
3271 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3272 {
3273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3274
3275         /* In promiscuous mode multicast promisc already set */
3276         if (dev->data->promiscuous == 0)
3277                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3278 }
3279
3280 static void
3281 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3282 {
3283         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3284
3285         /* In promiscuous mode leave multicast promisc enabled */
3286         if (dev->data->promiscuous == 0)
3287                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3288 }
3289
3290 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3291 {
3292         struct e1000_mbx_info *mbx = &hw->mbx;
3293         uint32_t msgbuf[2];
3294         s32 err;
3295
3296         /* After set vlan, vlan strip will also be enabled in igb driver*/
3297         msgbuf[0] = E1000_VF_SET_VLAN;
3298         msgbuf[1] = vid;
3299         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3300         if (on)
3301                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3302
3303         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3304         if (err)
3305                 goto mbx_err;
3306
3307         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3308         if (err)
3309                 goto mbx_err;
3310
3311         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3312         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3313                 err = -EINVAL;
3314
3315 mbx_err:
3316         return err;
3317 }
3318
3319 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3320 {
3321         struct e1000_hw *hw =
3322                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323         struct e1000_vfta * shadow_vfta =
3324                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3325         int i = 0, j = 0, vfta = 0, mask = 1;
3326
3327         for (i = 0; i < IGB_VFTA_SIZE; i++){
3328                 vfta = shadow_vfta->vfta[i];
3329                 if(vfta){
3330                         mask = 1;
3331                         for (j = 0; j < 32; j++){
3332                                 if(vfta & mask)
3333                                         igbvf_set_vfta(hw,
3334                                                 (uint16_t)((i<<5)+j), on);
3335                                 mask<<=1;
3336                         }
3337                 }
3338         }
3339
3340 }
3341
3342 static int
3343 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3344 {
3345         struct e1000_hw *hw =
3346                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347         struct e1000_vfta * shadow_vfta =
3348                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3349         uint32_t vid_idx = 0;
3350         uint32_t vid_bit = 0;
3351         int ret = 0;
3352
3353         PMD_INIT_FUNC_TRACE();
3354
3355         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3356         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3357         if(ret){
3358                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3359                 return ret;
3360         }
3361         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3362         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3363
3364         /*Save what we set and retore it after device reset*/
3365         if (on)
3366                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3367         else
3368                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3369
3370         return 0;
3371 }
3372
3373 static void
3374 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3375 {
3376         struct e1000_hw *hw =
3377                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378
3379         /* index is not used by rar_set() */
3380         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3381 }
3382
3383
3384 static int
3385 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3386                         struct rte_eth_rss_reta_entry64 *reta_conf,
3387                         uint16_t reta_size)
3388 {
3389         uint8_t i, j, mask;
3390         uint32_t reta, r;
3391         uint16_t idx, shift;
3392         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393
3394         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3395                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3396                         "(%d) doesn't match the number hardware can supported "
3397                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3398                 return -EINVAL;
3399         }
3400
3401         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3402                 idx = i / RTE_RETA_GROUP_SIZE;
3403                 shift = i % RTE_RETA_GROUP_SIZE;
3404                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3405                                                 IGB_4_BIT_MASK);
3406                 if (!mask)
3407                         continue;
3408                 if (mask == IGB_4_BIT_MASK)
3409                         r = 0;
3410                 else
3411                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3412                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3413                         if (mask & (0x1 << j))
3414                                 reta |= reta_conf[idx].reta[shift + j] <<
3415                                                         (CHAR_BIT * j);
3416                         else
3417                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3418                 }
3419                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3420         }
3421
3422         return 0;
3423 }
3424
3425 static int
3426 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3427                        struct rte_eth_rss_reta_entry64 *reta_conf,
3428                        uint16_t reta_size)
3429 {
3430         uint8_t i, j, mask;
3431         uint32_t reta;
3432         uint16_t idx, shift;
3433         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434
3435         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3436                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3437                         "(%d) doesn't match the number hardware can supported "
3438                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3439                 return -EINVAL;
3440         }
3441
3442         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3443                 idx = i / RTE_RETA_GROUP_SIZE;
3444                 shift = i % RTE_RETA_GROUP_SIZE;
3445                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3446                                                 IGB_4_BIT_MASK);
3447                 if (!mask)
3448                         continue;
3449                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3450                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3451                         if (mask & (0x1 << j))
3452                                 reta_conf[idx].reta[shift + j] =
3453                                         ((reta >> (CHAR_BIT * j)) &
3454                                                 IGB_8_BIT_MASK);
3455                 }
3456         }
3457
3458         return 0;
3459 }
3460
3461 #define MAC_TYPE_FILTER_SUP(type)    do {\
3462         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3463                 (type) != e1000_82576)\
3464                 return -ENOTSUP;\
3465 } while (0)
3466
3467 static int
3468 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3469                         struct rte_eth_syn_filter *filter,
3470                         bool add)
3471 {
3472         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3473         uint32_t synqf, rfctl;
3474
3475         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3476                 return -EINVAL;
3477
3478         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3479
3480         if (add) {
3481                 if (synqf & E1000_SYN_FILTER_ENABLE)
3482                         return -EINVAL;
3483
3484                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3485                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3486
3487                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3488                 if (filter->hig_pri)
3489                         rfctl |= E1000_RFCTL_SYNQFP;
3490                 else
3491                         rfctl &= ~E1000_RFCTL_SYNQFP;
3492
3493                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3494         } else {
3495                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3496                         return -ENOENT;
3497                 synqf = 0;
3498         }
3499
3500         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3501         E1000_WRITE_FLUSH(hw);
3502         return 0;
3503 }
3504
3505 static int
3506 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3507                         struct rte_eth_syn_filter *filter)
3508 {
3509         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         uint32_t synqf, rfctl;
3511
3512         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3513         if (synqf & E1000_SYN_FILTER_ENABLE) {
3514                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3515                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3516                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3517                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3518                 return 0;
3519         }
3520
3521         return -ENOENT;
3522 }
3523
3524 static int
3525 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3526                         enum rte_filter_op filter_op,
3527                         void *arg)
3528 {
3529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530         int ret;
3531
3532         MAC_TYPE_FILTER_SUP(hw->mac.type);
3533
3534         if (filter_op == RTE_ETH_FILTER_NOP)
3535                 return 0;
3536
3537         if (arg == NULL) {
3538                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3539                             filter_op);
3540                 return -EINVAL;
3541         }
3542
3543         switch (filter_op) {
3544         case RTE_ETH_FILTER_ADD:
3545                 ret = eth_igb_syn_filter_set(dev,
3546                                 (struct rte_eth_syn_filter *)arg,
3547                                 TRUE);
3548                 break;
3549         case RTE_ETH_FILTER_DELETE:
3550                 ret = eth_igb_syn_filter_set(dev,
3551                                 (struct rte_eth_syn_filter *)arg,
3552                                 FALSE);
3553                 break;
3554         case RTE_ETH_FILTER_GET:
3555                 ret = eth_igb_syn_filter_get(dev,
3556                                 (struct rte_eth_syn_filter *)arg);
3557                 break;
3558         default:
3559                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3560                 ret = -EINVAL;
3561                 break;
3562         }
3563
3564         return ret;
3565 }
3566
3567 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3568         if ((type) != e1000_82580 && (type) != e1000_i350)\
3569                 return -ENOSYS; \
3570 } while (0)
3571
3572 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3573 static inline int
3574 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3575                         struct e1000_2tuple_filter_info *filter_info)
3576 {
3577         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3578                 return -EINVAL;
3579         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3580                 return -EINVAL;  /* filter index is out of range. */
3581         if (filter->tcp_flags > TCP_FLAG_ALL)
3582                 return -EINVAL;  /* flags is invalid. */
3583
3584         switch (filter->dst_port_mask) {
3585         case UINT16_MAX:
3586                 filter_info->dst_port_mask = 0;
3587                 filter_info->dst_port = filter->dst_port;
3588                 break;
3589         case 0:
3590                 filter_info->dst_port_mask = 1;
3591                 break;
3592         default:
3593                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3594                 return -EINVAL;
3595         }
3596
3597         switch (filter->proto_mask) {
3598         case UINT8_MAX:
3599                 filter_info->proto_mask = 0;
3600                 filter_info->proto = filter->proto;
3601                 break;
3602         case 0:
3603                 filter_info->proto_mask = 1;
3604                 break;
3605         default:
3606                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3607                 return -EINVAL;
3608         }
3609
3610         filter_info->priority = (uint8_t)filter->priority;
3611         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3612                 filter_info->tcp_flags = filter->tcp_flags;
3613         else
3614                 filter_info->tcp_flags = 0;
3615
3616         return 0;
3617 }
3618
3619 static inline struct e1000_2tuple_filter *
3620 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3621                         struct e1000_2tuple_filter_info *key)
3622 {
3623         struct e1000_2tuple_filter *it;
3624
3625         TAILQ_FOREACH(it, filter_list, entries) {
3626                 if (memcmp(key, &it->filter_info,
3627                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3628                         return it;
3629                 }
3630         }
3631         return NULL;
3632 }
3633
3634 /*
3635  * igb_add_2tuple_filter - add a 2tuple filter
3636  *
3637  * @param
3638  * dev: Pointer to struct rte_eth_dev.
3639  * ntuple_filter: ponter to the filter that will be added.
3640  *
3641  * @return
3642  *    - On success, zero.
3643  *    - On failure, a negative value.
3644  */
3645 static int
3646 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3647                         struct rte_eth_ntuple_filter *ntuple_filter)
3648 {
3649         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         struct e1000_filter_info *filter_info =
3651                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3652         struct e1000_2tuple_filter *filter;
3653         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3654         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3655         int i, ret;
3656
3657         filter = rte_zmalloc("e1000_2tuple_filter",
3658                         sizeof(struct e1000_2tuple_filter), 0);
3659         if (filter == NULL)
3660                 return -ENOMEM;
3661
3662         ret = ntuple_filter_to_2tuple(ntuple_filter,
3663                                       &filter->filter_info);
3664         if (ret < 0) {
3665                 rte_free(filter);
3666                 return ret;
3667         }
3668         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3669                                          &filter->filter_info) != NULL) {
3670                 PMD_DRV_LOG(ERR, "filter exists.");
3671                 rte_free(filter);
3672                 return -EEXIST;
3673         }
3674         filter->queue = ntuple_filter->queue;
3675
3676         /*
3677          * look for an unused 2tuple filter index,
3678          * and insert the filter to list.
3679          */
3680         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3681                 if (!(filter_info->twotuple_mask & (1 << i))) {
3682                         filter_info->twotuple_mask |= 1 << i;
3683                         filter->index = i;
3684                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3685                                           filter,
3686                                           entries);
3687                         break;
3688                 }
3689         }
3690         if (i >= E1000_MAX_TTQF_FILTERS) {
3691                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3692                 rte_free(filter);
3693                 return -ENOSYS;
3694         }
3695
3696         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3697         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3698                 imir |= E1000_IMIR_PORT_BP;
3699         else
3700                 imir &= ~E1000_IMIR_PORT_BP;
3701
3702         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3703
3704         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3705         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3706         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3707         if (filter->filter_info.proto_mask == 0)
3708                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3709
3710         /* tcp flags bits setting. */
3711         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3712                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3713                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3714                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3715                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3716                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3717                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3718                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3719                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3720                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3721                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3722                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3723                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3724         } else
3725                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3726         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3727         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3728         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3729         return 0;
3730 }
3731
3732 /*
3733  * igb_remove_2tuple_filter - remove a 2tuple filter
3734  *
3735  * @param
3736  * dev: Pointer to struct rte_eth_dev.
3737  * ntuple_filter: ponter to the filter that will be removed.
3738  *
3739  * @return
3740  *    - On success, zero.
3741  *    - On failure, a negative value.
3742  */
3743 static int
3744 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3745                         struct rte_eth_ntuple_filter *ntuple_filter)
3746 {
3747         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         struct e1000_filter_info *filter_info =
3749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3750         struct e1000_2tuple_filter_info filter_2tuple;
3751         struct e1000_2tuple_filter *filter;
3752         int ret;
3753
3754         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3755         ret = ntuple_filter_to_2tuple(ntuple_filter,
3756                                       &filter_2tuple);
3757         if (ret < 0)
3758                 return ret;
3759
3760         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3761                                          &filter_2tuple);
3762         if (filter == NULL) {
3763                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3764                 return -ENOENT;
3765         }
3766
3767         filter_info->twotuple_mask &= ~(1 << filter->index);
3768         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3769         rte_free(filter);
3770
3771         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3772         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3773         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3774         return 0;
3775 }
3776
3777 static inline struct e1000_flex_filter *
3778 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3779                         struct e1000_flex_filter_info *key)
3780 {
3781         struct e1000_flex_filter *it;
3782
3783         TAILQ_FOREACH(it, filter_list, entries) {
3784                 if (memcmp(key, &it->filter_info,
3785                         sizeof(struct e1000_flex_filter_info)) == 0)
3786                         return it;
3787         }
3788
3789         return NULL;
3790 }
3791
3792 static int
3793 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3794                         struct rte_eth_flex_filter *filter,
3795                         bool add)
3796 {
3797         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798         struct e1000_filter_info *filter_info =
3799                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3800         struct e1000_flex_filter *flex_filter, *it;
3801         uint32_t wufc, queueing, mask;
3802         uint32_t reg_off;
3803         uint8_t shift, i, j = 0;
3804
3805         flex_filter = rte_zmalloc("e1000_flex_filter",
3806                         sizeof(struct e1000_flex_filter), 0);
3807         if (flex_filter == NULL)
3808                 return -ENOMEM;
3809
3810         flex_filter->filter_info.len = filter->len;
3811         flex_filter->filter_info.priority = filter->priority;
3812         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3813         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3814                 mask = 0;
3815                 /* reverse bits in flex filter's mask*/
3816                 for (shift = 0; shift < CHAR_BIT; shift++) {
3817                         if (filter->mask[i] & (0x01 << shift))
3818                                 mask |= (0x80 >> shift);
3819                 }
3820                 flex_filter->filter_info.mask[i] = mask;
3821         }
3822
3823         wufc = E1000_READ_REG(hw, E1000_WUFC);
3824         if (flex_filter->index < E1000_MAX_FHFT)
3825                 reg_off = E1000_FHFT(flex_filter->index);
3826         else
3827                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3828
3829         if (add) {
3830                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3831                                 &flex_filter->filter_info) != NULL) {
3832                         PMD_DRV_LOG(ERR, "filter exists.");
3833                         rte_free(flex_filter);
3834                         return -EEXIST;
3835                 }
3836                 flex_filter->queue = filter->queue;
3837                 /*
3838                  * look for an unused flex filter index
3839                  * and insert the filter into the list.
3840                  */
3841                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3842                         if (!(filter_info->flex_mask & (1 << i))) {
3843                                 filter_info->flex_mask |= 1 << i;
3844                                 flex_filter->index = i;
3845                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3846                                         flex_filter,
3847                                         entries);
3848                                 break;
3849                         }
3850                 }
3851                 if (i >= E1000_MAX_FLEX_FILTERS) {
3852                         PMD_DRV_LOG(ERR, "flex filters are full.");
3853                         rte_free(flex_filter);
3854                         return -ENOSYS;
3855                 }
3856
3857                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3858                                 (E1000_WUFC_FLX0 << flex_filter->index));
3859                 queueing = filter->len |
3860                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3861                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3862                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3863                                 queueing);
3864                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3865                         E1000_WRITE_REG(hw, reg_off,
3866                                         flex_filter->filter_info.dwords[j]);
3867                         reg_off += sizeof(uint32_t);
3868                         E1000_WRITE_REG(hw, reg_off,
3869                                         flex_filter->filter_info.dwords[++j]);
3870                         reg_off += sizeof(uint32_t);
3871                         E1000_WRITE_REG(hw, reg_off,
3872                                 (uint32_t)flex_filter->filter_info.mask[i]);
3873                         reg_off += sizeof(uint32_t) * 2;
3874                         ++j;
3875                 }
3876         } else {
3877                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3878                                 &flex_filter->filter_info);
3879                 if (it == NULL) {
3880                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3881                         rte_free(flex_filter);
3882                         return -ENOENT;
3883                 }
3884
3885                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3886                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3887                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3888                         (~(E1000_WUFC_FLX0 << it->index)));
3889
3890                 filter_info->flex_mask &= ~(1 << it->index);
3891                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3892                 rte_free(it);
3893                 rte_free(flex_filter);
3894         }
3895
3896         return 0;
3897 }
3898
3899 static int
3900 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3901                         struct rte_eth_flex_filter *filter)
3902 {
3903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3904         struct e1000_filter_info *filter_info =
3905                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3906         struct e1000_flex_filter flex_filter, *it;
3907         uint32_t wufc, queueing, wufc_en = 0;
3908
3909         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3910         flex_filter.filter_info.len = filter->len;
3911         flex_filter.filter_info.priority = filter->priority;
3912         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3913         memcpy(flex_filter.filter_info.mask, filter->mask,
3914                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3915
3916         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3917                                 &flex_filter.filter_info);
3918         if (it == NULL) {
3919                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3920                 return -ENOENT;
3921         }
3922
3923         wufc = E1000_READ_REG(hw, E1000_WUFC);
3924         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3925
3926         if ((wufc & wufc_en) == wufc_en) {
3927                 uint32_t reg_off = 0;
3928                 if (it->index < E1000_MAX_FHFT)
3929                         reg_off = E1000_FHFT(it->index);
3930                 else
3931                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3932
3933                 queueing = E1000_READ_REG(hw,
3934                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3935                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3936                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3937                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3938                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3939                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3940                 return 0;
3941         }
3942         return -ENOENT;
3943 }
3944
3945 static int
3946 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3947                         enum rte_filter_op filter_op,
3948                         void *arg)
3949 {
3950         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951         struct rte_eth_flex_filter *filter;
3952         int ret = 0;
3953
3954         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3955
3956         if (filter_op == RTE_ETH_FILTER_NOP)
3957                 return ret;
3958
3959         if (arg == NULL) {
3960                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3961                             filter_op);
3962                 return -EINVAL;
3963         }
3964
3965         filter = (struct rte_eth_flex_filter *)arg;
3966         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3967             || filter->len % sizeof(uint64_t) != 0) {
3968                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3969                 return -EINVAL;
3970         }
3971         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3972                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3973                 return -EINVAL;
3974         }
3975
3976         switch (filter_op) {
3977         case RTE_ETH_FILTER_ADD:
3978                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3979                 break;
3980         case RTE_ETH_FILTER_DELETE:
3981                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3982                 break;
3983         case RTE_ETH_FILTER_GET:
3984                 ret = eth_igb_get_flex_filter(dev, filter);
3985                 break;
3986         default:
3987                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3988                 ret = -EINVAL;
3989                 break;
3990         }
3991
3992         return ret;
3993 }
3994
3995 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3996 static inline int
3997 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3998                         struct e1000_5tuple_filter_info *filter_info)
3999 {
4000         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4001                 return -EINVAL;
4002         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4003                 return -EINVAL;  /* filter index is out of range. */
4004         if (filter->tcp_flags > TCP_FLAG_ALL)
4005                 return -EINVAL;  /* flags is invalid. */
4006
4007         switch (filter->dst_ip_mask) {
4008         case UINT32_MAX:
4009                 filter_info->dst_ip_mask = 0;
4010                 filter_info->dst_ip = filter->dst_ip;
4011                 break;
4012         case 0:
4013                 filter_info->dst_ip_mask = 1;
4014                 break;
4015         default:
4016                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4017                 return -EINVAL;
4018         }
4019
4020         switch (filter->src_ip_mask) {
4021         case UINT32_MAX:
4022                 filter_info->src_ip_mask = 0;
4023                 filter_info->src_ip = filter->src_ip;
4024                 break;
4025         case 0:
4026                 filter_info->src_ip_mask = 1;
4027                 break;
4028         default:
4029                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4030                 return -EINVAL;
4031         }
4032
4033         switch (filter->dst_port_mask) {
4034         case UINT16_MAX:
4035                 filter_info->dst_port_mask = 0;
4036                 filter_info->dst_port = filter->dst_port;
4037                 break;
4038         case 0:
4039                 filter_info->dst_port_mask = 1;
4040                 break;
4041         default:
4042                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4043                 return -EINVAL;
4044         }
4045
4046         switch (filter->src_port_mask) {
4047         case UINT16_MAX:
4048                 filter_info->src_port_mask = 0;
4049                 filter_info->src_port = filter->src_port;
4050                 break;
4051         case 0:
4052                 filter_info->src_port_mask = 1;
4053                 break;
4054         default:
4055                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4056                 return -EINVAL;
4057         }
4058
4059         switch (filter->proto_mask) {
4060         case UINT8_MAX:
4061                 filter_info->proto_mask = 0;
4062                 filter_info->proto = filter->proto;
4063                 break;
4064         case 0:
4065                 filter_info->proto_mask = 1;
4066                 break;
4067         default:
4068                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4069                 return -EINVAL;
4070         }
4071
4072         filter_info->priority = (uint8_t)filter->priority;
4073         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4074                 filter_info->tcp_flags = filter->tcp_flags;
4075         else
4076                 filter_info->tcp_flags = 0;
4077
4078         return 0;
4079 }
4080
4081 static inline struct e1000_5tuple_filter *
4082 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4083                         struct e1000_5tuple_filter_info *key)
4084 {
4085         struct e1000_5tuple_filter *it;
4086
4087         TAILQ_FOREACH(it, filter_list, entries) {
4088                 if (memcmp(key, &it->filter_info,
4089                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4090                         return it;
4091                 }
4092         }
4093         return NULL;
4094 }
4095
4096 /*
4097  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4098  *
4099  * @param
4100  * dev: Pointer to struct rte_eth_dev.
4101  * ntuple_filter: ponter to the filter that will be added.
4102  *
4103  * @return
4104  *    - On success, zero.
4105  *    - On failure, a negative value.
4106  */
4107 static int
4108 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4109                         struct rte_eth_ntuple_filter *ntuple_filter)
4110 {
4111         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         struct e1000_filter_info *filter_info =
4113                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4114         struct e1000_5tuple_filter *filter;
4115         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4116         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4117         uint8_t i;
4118         int ret;
4119
4120         filter = rte_zmalloc("e1000_5tuple_filter",
4121                         sizeof(struct e1000_5tuple_filter), 0);
4122         if (filter == NULL)
4123                 return -ENOMEM;
4124
4125         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4126                                             &filter->filter_info);
4127         if (ret < 0) {
4128                 rte_free(filter);
4129                 return ret;
4130         }
4131
4132         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4133                                          &filter->filter_info) != NULL) {
4134                 PMD_DRV_LOG(ERR, "filter exists.");
4135                 rte_free(filter);
4136                 return -EEXIST;
4137         }
4138         filter->queue = ntuple_filter->queue;
4139
4140         /*
4141          * look for an unused 5tuple filter index,
4142          * and insert the filter to list.
4143          */
4144         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4145                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4146                         filter_info->fivetuple_mask |= 1 << i;
4147                         filter->index = i;
4148                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4149                                           filter,
4150                                           entries);
4151                         break;
4152                 }
4153         }
4154         if (i >= E1000_MAX_FTQF_FILTERS) {
4155                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4156                 rte_free(filter);
4157                 return -ENOSYS;
4158         }
4159
4160         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4161         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4162                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4163         if (filter->filter_info.dst_ip_mask == 0)
4164                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4165         if (filter->filter_info.src_port_mask == 0)
4166                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4167         if (filter->filter_info.proto_mask == 0)
4168                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4169         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4170                 E1000_FTQF_QUEUE_MASK;
4171         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4172         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4173         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4174         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4175
4176         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4177         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4178
4179         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4180         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4181                 imir |= E1000_IMIR_PORT_BP;
4182         else
4183                 imir &= ~E1000_IMIR_PORT_BP;
4184         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4185
4186         /* tcp flags bits setting. */
4187         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4188                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4189                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4190                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4191                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4192                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4193                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4194                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4195                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4196                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4197                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4198                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4199                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4200         } else
4201                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4202         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4203         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4204         return 0;
4205 }
4206
4207 /*
4208  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4209  *
4210  * @param
4211  * dev: Pointer to struct rte_eth_dev.
4212  * ntuple_filter: ponter to the filter that will be removed.
4213  *
4214  * @return
4215  *    - On success, zero.
4216  *    - On failure, a negative value.
4217  */
4218 static int
4219 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4220                                 struct rte_eth_ntuple_filter *ntuple_filter)
4221 {
4222         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223         struct e1000_filter_info *filter_info =
4224                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4225         struct e1000_5tuple_filter_info filter_5tuple;
4226         struct e1000_5tuple_filter *filter;
4227         int ret;
4228
4229         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4230         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4231                                             &filter_5tuple);
4232         if (ret < 0)
4233                 return ret;
4234
4235         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4236                                          &filter_5tuple);
4237         if (filter == NULL) {
4238                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4239                 return -ENOENT;
4240         }
4241
4242         filter_info->fivetuple_mask &= ~(1 << filter->index);
4243         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4244         rte_free(filter);
4245
4246         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4247                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4248         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4249         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4250         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4251         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4252         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4253         return 0;
4254 }
4255
4256 static int
4257 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4258 {
4259         uint32_t rctl;
4260         struct e1000_hw *hw;
4261         struct rte_eth_dev_info dev_info;
4262         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4263                                      VLAN_TAG_SIZE);
4264
4265         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266
4267 #ifdef RTE_LIBRTE_82571_SUPPORT
4268         /* XXX: not bigger than max_rx_pktlen */
4269         if (hw->mac.type == e1000_82571)
4270                 return -ENOTSUP;
4271 #endif
4272         eth_igb_infos_get(dev, &dev_info);
4273
4274         /* check that mtu is within the allowed range */
4275         if ((mtu < ETHER_MIN_MTU) ||
4276             (frame_size > dev_info.max_rx_pktlen))
4277                 return -EINVAL;
4278
4279         /* refuse mtu that requires the support of scattered packets when this
4280          * feature has not been enabled before. */
4281         if (!dev->data->scattered_rx &&
4282             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4283                 return -EINVAL;
4284
4285         rctl = E1000_READ_REG(hw, E1000_RCTL);
4286
4287         /* switch to jumbo mode if needed */
4288         if (frame_size > ETHER_MAX_LEN) {
4289                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4290                 rctl |= E1000_RCTL_LPE;
4291         } else {
4292                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4293                 rctl &= ~E1000_RCTL_LPE;
4294         }
4295         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4296
4297         /* update max frame size */
4298         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4299
4300         E1000_WRITE_REG(hw, E1000_RLPML,
4301                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4302
4303         return 0;
4304 }
4305
4306 /*
4307  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4308  *
4309  * @param
4310  * dev: Pointer to struct rte_eth_dev.
4311  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4312  * add: if true, add filter, if false, remove filter
4313  *
4314  * @return
4315  *    - On success, zero.
4316  *    - On failure, a negative value.
4317  */
4318 static int
4319 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4320                         struct rte_eth_ntuple_filter *ntuple_filter,
4321                         bool add)
4322 {
4323         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         int ret;
4325
4326         switch (ntuple_filter->flags) {
4327         case RTE_5TUPLE_FLAGS:
4328         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4329                 if (hw->mac.type != e1000_82576)
4330                         return -ENOTSUP;
4331                 if (add)
4332                         ret = igb_add_5tuple_filter_82576(dev,
4333                                                           ntuple_filter);
4334                 else
4335                         ret = igb_remove_5tuple_filter_82576(dev,
4336                                                              ntuple_filter);
4337                 break;
4338         case RTE_2TUPLE_FLAGS:
4339         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4340                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4341                         return -ENOTSUP;
4342                 if (add)
4343                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4344                 else
4345                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4346                 break;
4347         default:
4348                 ret = -EINVAL;
4349                 break;
4350         }
4351
4352         return ret;
4353 }
4354
4355 /*
4356  * igb_get_ntuple_filter - get a ntuple filter
4357  *
4358  * @param
4359  * dev: Pointer to struct rte_eth_dev.
4360  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4361  *
4362  * @return
4363  *    - On success, zero.
4364  *    - On failure, a negative value.
4365  */
4366 static int
4367 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4368                         struct rte_eth_ntuple_filter *ntuple_filter)
4369 {
4370         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371         struct e1000_filter_info *filter_info =
4372                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4373         struct e1000_5tuple_filter_info filter_5tuple;
4374         struct e1000_2tuple_filter_info filter_2tuple;
4375         struct e1000_5tuple_filter *p_5tuple_filter;
4376         struct e1000_2tuple_filter *p_2tuple_filter;
4377         int ret;
4378
4379         switch (ntuple_filter->flags) {
4380         case RTE_5TUPLE_FLAGS:
4381         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4382                 if (hw->mac.type != e1000_82576)
4383                         return -ENOTSUP;
4384                 memset(&filter_5tuple,
4385                         0,
4386                         sizeof(struct e1000_5tuple_filter_info));
4387                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4388                                                     &filter_5tuple);
4389                 if (ret < 0)
4390                         return ret;
4391                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4392                                         &filter_info->fivetuple_list,
4393                                         &filter_5tuple);
4394                 if (p_5tuple_filter == NULL) {
4395                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4396                         return -ENOENT;
4397                 }
4398                 ntuple_filter->queue = p_5tuple_filter->queue;
4399                 break;
4400         case RTE_2TUPLE_FLAGS:
4401         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4402                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4403                         return -ENOTSUP;
4404                 memset(&filter_2tuple,
4405                         0,
4406                         sizeof(struct e1000_2tuple_filter_info));
4407                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4408                 if (ret < 0)
4409                         return ret;
4410                 p_2tuple_filter = igb_2tuple_filter_lookup(
4411                                         &filter_info->twotuple_list,
4412                                         &filter_2tuple);
4413                 if (p_2tuple_filter == NULL) {
4414                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4415                         return -ENOENT;
4416                 }
4417                 ntuple_filter->queue = p_2tuple_filter->queue;
4418                 break;
4419         default:
4420                 ret = -EINVAL;
4421                 break;
4422         }
4423
4424         return 0;
4425 }
4426
4427 /*
4428  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4429  * @dev: pointer to rte_eth_dev structure
4430  * @filter_op:operation will be taken.
4431  * @arg: a pointer to specific structure corresponding to the filter_op
4432  */
4433 static int
4434 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4435                                 enum rte_filter_op filter_op,
4436                                 void *arg)
4437 {
4438         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439         int ret;
4440
4441         MAC_TYPE_FILTER_SUP(hw->mac.type);
4442
4443         if (filter_op == RTE_ETH_FILTER_NOP)
4444                 return 0;
4445
4446         if (arg == NULL) {
4447                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4448                             filter_op);
4449                 return -EINVAL;
4450         }
4451
4452         switch (filter_op) {
4453         case RTE_ETH_FILTER_ADD:
4454                 ret = igb_add_del_ntuple_filter(dev,
4455                         (struct rte_eth_ntuple_filter *)arg,
4456                         TRUE);
4457                 break;
4458         case RTE_ETH_FILTER_DELETE:
4459                 ret = igb_add_del_ntuple_filter(dev,
4460                         (struct rte_eth_ntuple_filter *)arg,
4461                         FALSE);
4462                 break;
4463         case RTE_ETH_FILTER_GET:
4464                 ret = igb_get_ntuple_filter(dev,
4465                         (struct rte_eth_ntuple_filter *)arg);
4466                 break;
4467         default:
4468                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4469                 ret = -EINVAL;
4470                 break;
4471         }
4472         return ret;
4473 }
4474
4475 static inline int
4476 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4477                         uint16_t ethertype)
4478 {
4479         int i;
4480
4481         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4482                 if (filter_info->ethertype_filters[i] == ethertype &&
4483                     (filter_info->ethertype_mask & (1 << i)))
4484                         return i;
4485         }
4486         return -1;
4487 }
4488
4489 static inline int
4490 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4491                         uint16_t ethertype)
4492 {
4493         int i;
4494
4495         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4496                 if (!(filter_info->ethertype_mask & (1 << i))) {
4497                         filter_info->ethertype_mask |= 1 << i;
4498                         filter_info->ethertype_filters[i] = ethertype;
4499                         return i;
4500                 }
4501         }
4502         return -1;
4503 }
4504
4505 static inline int
4506 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4507                         uint8_t idx)
4508 {
4509         if (idx >= E1000_MAX_ETQF_FILTERS)
4510                 return -1;
4511         filter_info->ethertype_mask &= ~(1 << idx);
4512         filter_info->ethertype_filters[idx] = 0;
4513         return idx;
4514 }
4515
4516
4517 static int
4518 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4519                         struct rte_eth_ethertype_filter *filter,
4520                         bool add)
4521 {
4522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4523         struct e1000_filter_info *filter_info =
4524                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4525         uint32_t etqf = 0;
4526         int ret;
4527
4528         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4529                 filter->ether_type == ETHER_TYPE_IPv6) {
4530                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4531                         " ethertype filter.", filter->ether_type);
4532                 return -EINVAL;
4533         }
4534
4535         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4536                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4537                 return -EINVAL;
4538         }
4539         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4540                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4541                 return -EINVAL;
4542         }
4543
4544         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4545         if (ret >= 0 && add) {
4546                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4547                             filter->ether_type);
4548                 return -EEXIST;
4549         }
4550         if (ret < 0 && !add) {
4551                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4552                             filter->ether_type);
4553                 return -ENOENT;
4554         }
4555
4556         if (add) {
4557                 ret = igb_ethertype_filter_insert(filter_info,
4558                         filter->ether_type);
4559                 if (ret < 0) {
4560                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4561                         return -ENOSYS;
4562                 }
4563
4564                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4565                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4566                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4567         } else {
4568                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4569                 if (ret < 0)
4570                         return -ENOSYS;
4571         }
4572         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4573         E1000_WRITE_FLUSH(hw);
4574
4575         return 0;
4576 }
4577
4578 static int
4579 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4580                         struct rte_eth_ethertype_filter *filter)
4581 {
4582         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583         struct e1000_filter_info *filter_info =
4584                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4585         uint32_t etqf;
4586         int ret;
4587
4588         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4589         if (ret < 0) {
4590                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4591                             filter->ether_type);
4592                 return -ENOENT;
4593         }
4594
4595         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4596         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4597                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4598                 filter->flags = 0;
4599                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4600                                 E1000_ETQF_QUEUE_SHIFT;
4601                 return 0;
4602         }
4603
4604         return -ENOENT;
4605 }
4606
4607 /*
4608  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4609  * @dev: pointer to rte_eth_dev structure
4610  * @filter_op:operation will be taken.
4611  * @arg: a pointer to specific structure corresponding to the filter_op
4612  */
4613 static int
4614 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4615                                 enum rte_filter_op filter_op,
4616                                 void *arg)
4617 {
4618         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4619         int ret;
4620
4621         MAC_TYPE_FILTER_SUP(hw->mac.type);
4622
4623         if (filter_op == RTE_ETH_FILTER_NOP)
4624                 return 0;
4625
4626         if (arg == NULL) {
4627                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4628                             filter_op);
4629                 return -EINVAL;
4630         }
4631
4632         switch (filter_op) {
4633         case RTE_ETH_FILTER_ADD:
4634                 ret = igb_add_del_ethertype_filter(dev,
4635                         (struct rte_eth_ethertype_filter *)arg,
4636                         TRUE);
4637                 break;
4638         case RTE_ETH_FILTER_DELETE:
4639                 ret = igb_add_del_ethertype_filter(dev,
4640                         (struct rte_eth_ethertype_filter *)arg,
4641                         FALSE);
4642                 break;
4643         case RTE_ETH_FILTER_GET:
4644                 ret = igb_get_ethertype_filter(dev,
4645                         (struct rte_eth_ethertype_filter *)arg);
4646                 break;
4647         default:
4648                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4649                 ret = -EINVAL;
4650                 break;
4651         }
4652         return ret;
4653 }
4654
4655 static int
4656 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4657                      enum rte_filter_type filter_type,
4658                      enum rte_filter_op filter_op,
4659                      void *arg)
4660 {
4661         int ret = -EINVAL;
4662
4663         switch (filter_type) {
4664         case RTE_ETH_FILTER_NTUPLE:
4665                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4666                 break;
4667         case RTE_ETH_FILTER_ETHERTYPE:
4668                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4669                 break;
4670         case RTE_ETH_FILTER_SYN:
4671                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4672                 break;
4673         case RTE_ETH_FILTER_FLEXIBLE:
4674                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4675                 break;
4676         default:
4677                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4678                                                         filter_type);
4679                 break;
4680         }
4681
4682         return ret;
4683 }
4684
4685 static int
4686 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4687                          struct ether_addr *mc_addr_set,
4688                          uint32_t nb_mc_addr)
4689 {
4690         struct e1000_hw *hw;
4691
4692         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4693         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4694         return 0;
4695 }
4696
4697 static uint64_t
4698 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4699 {
4700         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4701         uint64_t systime_cycles;
4702
4703         switch (hw->mac.type) {
4704         case e1000_i210:
4705         case e1000_i211:
4706                 /*
4707                  * Need to read System Time Residue Register to be able
4708                  * to read the other two registers.
4709                  */
4710                 E1000_READ_REG(hw, E1000_SYSTIMR);
4711                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4712                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4713                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4714                                 * NSEC_PER_SEC;
4715                 break;
4716         case e1000_82580:
4717         case e1000_i350:
4718         case e1000_i354:
4719                 /*
4720                  * Need to read System Time Residue Register to be able
4721                  * to read the other two registers.
4722                  */
4723                 E1000_READ_REG(hw, E1000_SYSTIMR);
4724                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4725                 /* Only the 8 LSB are valid. */
4726                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4727                                 & 0xff) << 32;
4728                 break;
4729         default:
4730                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4731                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4732                                 << 32;
4733                 break;
4734         }
4735
4736         return systime_cycles;
4737 }
4738
4739 static uint64_t
4740 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4741 {
4742         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743         uint64_t rx_tstamp_cycles;
4744
4745         switch (hw->mac.type) {
4746         case e1000_i210:
4747         case e1000_i211:
4748                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4749                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4750                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4751                                 * NSEC_PER_SEC;
4752                 break;
4753         case e1000_82580:
4754         case e1000_i350:
4755         case e1000_i354:
4756                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4757                 /* Only the 8 LSB are valid. */
4758                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4759                                 & 0xff) << 32;
4760                 break;
4761         default:
4762                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4763                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4764                                 << 32;
4765                 break;
4766         }
4767
4768         return rx_tstamp_cycles;
4769 }
4770
4771 static uint64_t
4772 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4773 {
4774         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4775         uint64_t tx_tstamp_cycles;
4776
4777         switch (hw->mac.type) {
4778         case e1000_i210:
4779         case e1000_i211:
4780                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4781                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4782                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4783                                 * NSEC_PER_SEC;
4784                 break;
4785         case e1000_82580:
4786         case e1000_i350:
4787         case e1000_i354:
4788                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4789                 /* Only the 8 LSB are valid. */
4790                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4791                                 & 0xff) << 32;
4792                 break;
4793         default:
4794                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4795                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4796                                 << 32;
4797                 break;
4798         }
4799
4800         return tx_tstamp_cycles;
4801 }
4802
4803 static void
4804 igb_start_timecounters(struct rte_eth_dev *dev)
4805 {
4806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4807         struct e1000_adapter *adapter =
4808                 (struct e1000_adapter *)dev->data->dev_private;
4809         uint32_t incval = 1;
4810         uint32_t shift = 0;
4811         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4812
4813         switch (hw->mac.type) {
4814         case e1000_82580:
4815         case e1000_i350:
4816         case e1000_i354:
4817                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4818                 mask = (1ULL << 40) - 1;
4819                 /* fall-through */
4820         case e1000_i210:
4821         case e1000_i211:
4822                 /*
4823                  * Start incrementing the register
4824                  * used to timestamp PTP packets.
4825                  */
4826                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4827                 break;
4828         case e1000_82576:
4829                 incval = E1000_INCVALUE_82576;
4830                 shift = IGB_82576_TSYNC_SHIFT;
4831                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4832                                 E1000_INCPERIOD_82576 | incval);
4833                 break;
4834         default:
4835                 /* Not supported */
4836                 return;
4837         }
4838
4839         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4840         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4841         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4842
4843         adapter->systime_tc.cc_mask = mask;
4844         adapter->systime_tc.cc_shift = shift;
4845         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4846
4847         adapter->rx_tstamp_tc.cc_mask = mask;
4848         adapter->rx_tstamp_tc.cc_shift = shift;
4849         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4850
4851         adapter->tx_tstamp_tc.cc_mask = mask;
4852         adapter->tx_tstamp_tc.cc_shift = shift;
4853         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4854 }
4855
4856 static int
4857 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4858 {
4859         struct e1000_adapter *adapter =
4860                         (struct e1000_adapter *)dev->data->dev_private;
4861
4862         adapter->systime_tc.nsec += delta;
4863         adapter->rx_tstamp_tc.nsec += delta;
4864         adapter->tx_tstamp_tc.nsec += delta;
4865
4866         return 0;
4867 }
4868
4869 static int
4870 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4871 {
4872         uint64_t ns;
4873         struct e1000_adapter *adapter =
4874                         (struct e1000_adapter *)dev->data->dev_private;
4875
4876         ns = rte_timespec_to_ns(ts);
4877
4878         /* Set the timecounters to a new value. */
4879         adapter->systime_tc.nsec = ns;
4880         adapter->rx_tstamp_tc.nsec = ns;
4881         adapter->tx_tstamp_tc.nsec = ns;
4882
4883         return 0;
4884 }
4885
4886 static int
4887 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4888 {
4889         uint64_t ns, systime_cycles;
4890         struct e1000_adapter *adapter =
4891                         (struct e1000_adapter *)dev->data->dev_private;
4892
4893         systime_cycles = igb_read_systime_cyclecounter(dev);
4894         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4895         *ts = rte_ns_to_timespec(ns);
4896
4897         return 0;
4898 }
4899
4900 static int
4901 igb_timesync_enable(struct rte_eth_dev *dev)
4902 {
4903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         uint32_t tsync_ctl;
4905         uint32_t tsauxc;
4906
4907         /* Stop the timesync system time. */
4908         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4909         /* Reset the timesync system time value. */
4910         switch (hw->mac.type) {
4911         case e1000_82580:
4912         case e1000_i350:
4913         case e1000_i354:
4914         case e1000_i210:
4915         case e1000_i211:
4916                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4917                 /* fall-through */
4918         case e1000_82576:
4919                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4920                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4921                 break;
4922         default:
4923                 /* Not supported. */
4924                 return -ENOTSUP;
4925         }
4926
4927         /* Enable system time for it isn't on by default. */
4928         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4929         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4930         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4931
4932         igb_start_timecounters(dev);
4933
4934         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4935         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4936                         (ETHER_TYPE_1588 |
4937                          E1000_ETQF_FILTER_ENABLE |
4938                          E1000_ETQF_1588));
4939
4940         /* Enable timestamping of received PTP packets. */
4941         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4942         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4943         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4944
4945         /* Enable Timestamping of transmitted PTP packets. */
4946         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4947         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4948         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4949
4950         return 0;
4951 }
4952
4953 static int
4954 igb_timesync_disable(struct rte_eth_dev *dev)
4955 {
4956         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         uint32_t tsync_ctl;
4958
4959         /* Disable timestamping of transmitted PTP packets. */
4960         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4961         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4962         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4963
4964         /* Disable timestamping of received PTP packets. */
4965         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4966         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4967         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4968
4969         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4970         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4971
4972         /* Stop incrementating the System Time registers. */
4973         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4974
4975         return 0;
4976 }
4977
4978 static int
4979 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4980                                struct timespec *timestamp,
4981                                uint32_t flags __rte_unused)
4982 {
4983         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4984         struct e1000_adapter *adapter =
4985                         (struct e1000_adapter *)dev->data->dev_private;
4986         uint32_t tsync_rxctl;
4987         uint64_t rx_tstamp_cycles;
4988         uint64_t ns;
4989
4990         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4991         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4992                 return -EINVAL;
4993
4994         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4995         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4996         *timestamp = rte_ns_to_timespec(ns);
4997
4998         return  0;
4999 }
5000
5001 static int
5002 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5003                                struct timespec *timestamp)
5004 {
5005         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006         struct e1000_adapter *adapter =
5007                         (struct e1000_adapter *)dev->data->dev_private;
5008         uint32_t tsync_txctl;
5009         uint64_t tx_tstamp_cycles;
5010         uint64_t ns;
5011
5012         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5013         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5014                 return -EINVAL;
5015
5016         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5017         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5018         *timestamp = rte_ns_to_timespec(ns);
5019
5020         return  0;
5021 }
5022
5023 static int
5024 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5025 {
5026         int count = 0;
5027         int g_ind = 0;
5028         const struct reg_info *reg_group;
5029
5030         while ((reg_group = igb_regs[g_ind++]))
5031                 count += igb_reg_group_count(reg_group);
5032
5033         return count;
5034 }
5035
5036 static int
5037 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5038 {
5039         int count = 0;
5040         int g_ind = 0;
5041         const struct reg_info *reg_group;
5042
5043         while ((reg_group = igbvf_regs[g_ind++]))
5044                 count += igb_reg_group_count(reg_group);
5045
5046         return count;
5047 }
5048
5049 static int
5050 eth_igb_get_regs(struct rte_eth_dev *dev,
5051         struct rte_dev_reg_info *regs)
5052 {
5053         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5054         uint32_t *data = regs->data;
5055         int g_ind = 0;
5056         int count = 0;
5057         const struct reg_info *reg_group;
5058
5059         if (data == NULL) {
5060                 regs->length = eth_igb_get_reg_length(dev);
5061                 regs->width = sizeof(uint32_t);
5062                 return 0;
5063         }
5064
5065         /* Support only full register dump */
5066         if ((regs->length == 0) ||
5067             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5068                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5069                         hw->device_id;
5070                 while ((reg_group = igb_regs[g_ind++]))
5071                         count += igb_read_regs_group(dev, &data[count],
5072                                                         reg_group);
5073                 return 0;
5074         }
5075
5076         return -ENOTSUP;
5077 }
5078
5079 static int
5080 igbvf_get_regs(struct rte_eth_dev *dev,
5081         struct rte_dev_reg_info *regs)
5082 {
5083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         uint32_t *data = regs->data;
5085         int g_ind = 0;
5086         int count = 0;
5087         const struct reg_info *reg_group;
5088
5089         if (data == NULL) {
5090                 regs->length = igbvf_get_reg_length(dev);
5091                 regs->width = sizeof(uint32_t);
5092                 return 0;
5093         }
5094
5095         /* Support only full register dump */
5096         if ((regs->length == 0) ||
5097             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5098                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5099                         hw->device_id;
5100                 while ((reg_group = igbvf_regs[g_ind++]))
5101                         count += igb_read_regs_group(dev, &data[count],
5102                                                         reg_group);
5103                 return 0;
5104         }
5105
5106         return -ENOTSUP;
5107 }
5108
5109 static int
5110 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5111 {
5112         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113
5114         /* Return unit is byte count */
5115         return hw->nvm.word_size * 2;
5116 }
5117
5118 static int
5119 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5120         struct rte_dev_eeprom_info *in_eeprom)
5121 {
5122         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5123         struct e1000_nvm_info *nvm = &hw->nvm;
5124         uint16_t *data = in_eeprom->data;
5125         int first, length;
5126
5127         first = in_eeprom->offset >> 1;
5128         length = in_eeprom->length >> 1;
5129         if ((first >= hw->nvm.word_size) ||
5130             ((first + length) >= hw->nvm.word_size))
5131                 return -EINVAL;
5132
5133         in_eeprom->magic = hw->vendor_id |
5134                 ((uint32_t)hw->device_id << 16);
5135
5136         if ((nvm->ops.read) == NULL)
5137                 return -ENOTSUP;
5138
5139         return nvm->ops.read(hw, first, length, data);
5140 }
5141
5142 static int
5143 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5144         struct rte_dev_eeprom_info *in_eeprom)
5145 {
5146         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         struct e1000_nvm_info *nvm = &hw->nvm;
5148         uint16_t *data = in_eeprom->data;
5149         int first, length;
5150
5151         first = in_eeprom->offset >> 1;
5152         length = in_eeprom->length >> 1;
5153         if ((first >= hw->nvm.word_size) ||
5154             ((first + length) >= hw->nvm.word_size))
5155                 return -EINVAL;
5156
5157         in_eeprom->magic = (uint32_t)hw->vendor_id |
5158                 ((uint32_t)hw->device_id << 16);
5159
5160         if ((nvm->ops.write) == NULL)
5161                 return -ENOTSUP;
5162         return nvm->ops.write(hw,  first, length, data);
5163 }
5164
5165 static int
5166 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5167 {
5168         struct e1000_hw *hw =
5169                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         uint32_t mask = 1 << queue_id;
5171
5172         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5173         E1000_WRITE_FLUSH(hw);
5174
5175         return 0;
5176 }
5177
5178 static int
5179 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5180 {
5181         struct e1000_hw *hw =
5182                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5183         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5184         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5185         uint32_t mask = 1 << queue_id;
5186         uint32_t regval;
5187
5188         regval = E1000_READ_REG(hw, E1000_EIMS);
5189         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5190         E1000_WRITE_FLUSH(hw);
5191
5192         rte_intr_enable(intr_handle);
5193
5194         return 0;
5195 }
5196
5197 static void
5198 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5199                    uint8_t index, uint8_t offset)
5200 {
5201         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5202
5203         /* clear bits */
5204         val &= ~((uint32_t)0xFF << offset);
5205
5206         /* write vector and valid bit */
5207         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5208
5209         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5210 }
5211
5212 static void
5213 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5214                            uint8_t queue, uint8_t msix_vector)
5215 {
5216         uint32_t tmp = 0;
5217
5218         if (hw->mac.type == e1000_82575) {
5219                 if (direction == 0)
5220                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5221                 else if (direction == 1)
5222                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5223                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5224         } else if (hw->mac.type == e1000_82576) {
5225                 if ((direction == 0) || (direction == 1))
5226                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5227                                            ((queue & 0x8) << 1) +
5228                                            8 * direction);
5229         } else if ((hw->mac.type == e1000_82580) ||
5230                         (hw->mac.type == e1000_i350) ||
5231                         (hw->mac.type == e1000_i354) ||
5232                         (hw->mac.type == e1000_i210) ||
5233                         (hw->mac.type == e1000_i211)) {
5234                 if ((direction == 0) || (direction == 1))
5235                         eth_igb_write_ivar(hw, msix_vector,
5236                                            queue >> 1,
5237                                            ((queue & 0x1) << 4) +
5238                                            8 * direction);
5239         }
5240 }
5241
5242 /* Sets up the hardware to generate MSI-X interrupts properly
5243  * @hw
5244  *  board private structure
5245  */
5246 static void
5247 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5248 {
5249         int queue_id;
5250         uint32_t tmpval, regval, intr_mask;
5251         struct e1000_hw *hw =
5252                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5253         uint32_t vec = E1000_MISC_VEC_ID;
5254         uint32_t base = E1000_MISC_VEC_ID;
5255         uint32_t misc_shift = 0;
5256         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5257         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5258
5259         /* won't configure msix register if no mapping is done
5260          * between intr vector and event fd
5261          */
5262         if (!rte_intr_dp_is_en(intr_handle))
5263                 return;
5264
5265         if (rte_intr_allow_others(intr_handle)) {
5266                 vec = base = E1000_RX_VEC_START;
5267                 misc_shift = 1;
5268         }
5269
5270         /* set interrupt vector for other causes */
5271         if (hw->mac.type == e1000_82575) {
5272                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5273                 /* enable MSI-X PBA support */
5274                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5275
5276                 /* Auto-Mask interrupts upon ICR read */
5277                 tmpval |= E1000_CTRL_EXT_EIAME;
5278                 tmpval |= E1000_CTRL_EXT_IRCA;
5279
5280                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5281
5282                 /* enable msix_other interrupt */
5283                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5284                 regval = E1000_READ_REG(hw, E1000_EIAC);
5285                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5286                 regval = E1000_READ_REG(hw, E1000_EIAM);
5287                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5288         } else if ((hw->mac.type == e1000_82576) ||
5289                         (hw->mac.type == e1000_82580) ||
5290                         (hw->mac.type == e1000_i350) ||
5291                         (hw->mac.type == e1000_i354) ||
5292                         (hw->mac.type == e1000_i210) ||
5293                         (hw->mac.type == e1000_i211)) {
5294                 /* turn on MSI-X capability first */
5295                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5296                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5297                                         E1000_GPIE_NSICR);
5298                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5299                         misc_shift;
5300                 regval = E1000_READ_REG(hw, E1000_EIAC);
5301                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5302
5303                 /* enable msix_other interrupt */
5304                 regval = E1000_READ_REG(hw, E1000_EIMS);
5305                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5306                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5307                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5308         }
5309
5310         /* use EIAM to auto-mask when MSI-X interrupt
5311          * is asserted, this saves a register write for every interrupt
5312          */
5313         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5314                 misc_shift;
5315         regval = E1000_READ_REG(hw, E1000_EIAM);
5316         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5317
5318         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5319                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5320                 intr_handle->intr_vec[queue_id] = vec;
5321                 if (vec < base + intr_handle->nb_efd - 1)
5322                         vec++;
5323         }
5324
5325         E1000_WRITE_FLUSH(hw);
5326 }
5327
5328 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5329 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5330 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5331 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5332 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5333 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");