drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29 #include "igb_regs.h"
  30
  31 /*
  32  * Default values for port configuration
  33  */
  34 #define IGB_DEFAULT_RX_FREE_THRESH  32
  35
  36 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  37 #define IGB_DEFAULT_RX_HTHRESH      8
  38 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  39
  40 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  41 #define IGB_DEFAULT_TX_HTHRESH      1
  42 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  43
  44 /* Bit shift and mask */
  45 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  46 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  47 #define IGB_8_BIT_WIDTH  CHAR_BIT
  48 #define IGB_8_BIT_MASK   UINT8_MAX
  49
  50 /* Additional timesync values. */
  51 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  52 #define E1000_ETQF_FILTER_1588       3
  53 #define IGB_82576_TSYNC_SHIFT        16
  54 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  55 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  56 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  57
  58 #define E1000_VTIVAR_MISC                0x01740
  59 #define E1000_VTIVAR_MISC_MASK           0xFF
  60 #define E1000_VTIVAR_VALID               0x80
  61 #define E1000_VTIVAR_MISC_MAILBOX        0
  62 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  63
  64 /* External VLAN Enable bit mask */
  65 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  66
  67 /* External VLAN Ether Type bit mask and shift */
  68 #define E1000_VET_VET_EXT            0xFFFF0000
  69 #define E1000_VET_VET_EXT_SHIFT      16
  70
  71 static int  eth_igb_configure(struct rte_eth_dev *dev);
  72 static int  eth_igb_start(struct rte_eth_dev *dev);
  73 static void eth_igb_stop(struct rte_eth_dev *dev);
  74 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  75 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  76 static void eth_igb_close(struct rte_eth_dev *dev);
  77 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  78 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  79 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  80 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  81 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  82                                 int wait_to_complete);
  83 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  84                                 struct rte_eth_stats *rte_stats);
  85 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  86                               struct rte_eth_xstat *xstats, unsigned n);
  87 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  88                 const uint64_t *ids,
  89                 uint64_t *values, unsigned int n);
  90 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  91                                     struct rte_eth_xstat_name *xstats_names,
  92                                     unsigned int size);
  93 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  94                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
  95                 unsigned int limit);
  96 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  97 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
  98 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
  99                                    char *fw_version, size_t fw_size);
 100 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_dev_info *dev_info);
 102 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 103 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 104                                 struct rte_eth_dev_info *dev_info);
 105 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_fc_conf *fc_conf);
 107 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 110 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 111 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 112 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 113                                     struct rte_intr_handle *handle);
 114 static void eth_igb_interrupt_handler(void *param);
 115 static int  igb_hardware_init(struct e1000_hw *hw);
 116 static void igb_hw_control_acquire(struct e1000_hw *hw);
 117 static void igb_hw_control_release(struct e1000_hw *hw);
 118 static void igb_init_manageability(struct e1000_hw *hw);
 119 static void igb_release_manageability(struct e1000_hw *hw);
 120
 121 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 122
 123 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 124                 uint16_t vlan_id, int on);
 125 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 126                                  enum rte_vlan_type vlan_type,
 127                                  uint16_t tpid_id);
 128 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129
 130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 136
 137 static int eth_igb_led_on(struct rte_eth_dev *dev);
 138 static int eth_igb_led_off(struct rte_eth_dev *dev);
 139
 140 static void igb_intr_disable(struct e1000_hw *hw);
 141 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 142 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 143                            struct ether_addr *mac_addr,
 144                            uint32_t index, uint32_t pool);
 145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 146 static int eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *addr);
 148
 149 static void igbvf_intr_disable(struct e1000_hw *hw);
 150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 151 static int igbvf_dev_start(struct rte_eth_dev *dev);
 152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 153 static void igbvf_dev_close(struct rte_eth_dev *dev);
 154 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 155 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 156 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 157 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 158 static int eth_igbvf_link_update(struct e1000_hw *hw);
 159 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 160                                 struct rte_eth_stats *rte_stats);
 161 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 162                                 struct rte_eth_xstat *xstats, unsigned n);
 163 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 164                                       struct rte_eth_xstat_name *xstats_names,
 165                                       unsigned limit);
 166 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 167 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 168                 uint16_t vlan_id, int on);
 169 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 170 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 171 static int igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 172                 struct ether_addr *addr);
 173 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 174 static int igbvf_get_regs(struct rte_eth_dev *dev,
 175                 struct rte_dev_reg_info *regs);
 176
 177 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 178                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 179                                    uint16_t reta_size);
 180 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 181                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                   uint16_t reta_size);
 183
 184 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 185                         struct rte_eth_syn_filter *filter);
 186 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 187                         enum rte_filter_op filter_op,
 188                         void *arg);
 189 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_ntuple_filter *ntuple_filter);
 191 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_flex_filter *filter);
 195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 196                         enum rte_filter_op filter_op,
 197                         void *arg);
 198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *ntuple_filter);
 200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *filter);
 204 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 205                                 enum rte_filter_op filter_op,
 206                                 void *arg);
 207 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ethertype_filter *filter);
 212 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 213                      enum rte_filter_type filter_type,
 214                      enum rte_filter_op filter_op,
 215                      void *arg);
 216 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 217 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 218                 struct rte_dev_reg_info *regs);
 219 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 220 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 221                 struct rte_dev_eeprom_info *eeprom);
 222 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_get_module_info(struct rte_eth_dev *dev,
 225                                    struct rte_eth_dev_module_info *modinfo);
 226 static int eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
 227                                      struct rte_dev_eeprom_info *info);
 228 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 229                                     struct ether_addr *mc_addr_set,
 230                                     uint32_t nb_mc_addr);
 231 static int igb_timesync_enable(struct rte_eth_dev *dev);
 232 static int igb_timesync_disable(struct rte_eth_dev *dev);
 233 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 234                                           struct timespec *timestamp,
 235                                           uint32_t flags);
 236 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 237                                           struct timespec *timestamp);
 238 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 239 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 240                                   struct timespec *timestamp);
 241 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 242                                    const struct timespec *timestamp);
 243 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 244                                         uint16_t queue_id);
 245 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 246                                          uint16_t queue_id);
 247 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 248                                        uint8_t queue, uint8_t msix_vector);
 249 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 250                                uint8_t index, uint8_t offset);
 251 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 252 static void eth_igbvf_interrupt_handler(void *param);
 253 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 254 static int igb_filter_restore(struct rte_eth_dev *dev);
 255
 256 /*
 257  * Define VF Stats MACRO for Non "cleared on read" register
 258  */
 259 #define UPDATE_VF_STAT(reg, last, cur)            \
 260 {                                                 \
 261         u32 latest = E1000_READ_REG(hw, reg);     \
 262         cur += (latest - last) & UINT_MAX;        \
 263         last = latest;                            \
 264 }
 265
 266 #define IGB_FC_PAUSE_TIME 0x0680
 267 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 268 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 269
 270 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 271
 272 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 273
 274 /*
 275  * The set of PCI devices this driver supports
 276  */
 277 static const struct rte_pci_id pci_id_igb_map[] = {
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 286
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 290
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 297
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 319         { .vendor_id = 0, /* sentinel */ },
 320 };
 321
 322 /*
 323  * The set of PCI devices this driver supports (for 82576&I350 VF)
 324  */
 325 static const struct rte_pci_id pci_id_igbvf_map[] = {
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 330         { .vendor_id = 0, /* sentinel */ },
 331 };
 332
 333 static const struct rte_eth_desc_lim rx_desc_lim = {
 334         .nb_max = E1000_MAX_RING_DESC,
 335         .nb_min = E1000_MIN_RING_DESC,
 336         .nb_align = IGB_RXD_ALIGN,
 337 };
 338
 339 static const struct rte_eth_desc_lim tx_desc_lim = {
 340         .nb_max = E1000_MAX_RING_DESC,
 341         .nb_min = E1000_MIN_RING_DESC,
 342         .nb_align = IGB_RXD_ALIGN,
 343         .nb_seg_max = IGB_TX_MAX_SEG,
 344         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 345 };
 346
 347 static const struct eth_dev_ops eth_igb_ops = {
 348         .dev_configure        = eth_igb_configure,
 349         .dev_start            = eth_igb_start,
 350         .dev_stop             = eth_igb_stop,
 351         .dev_set_link_up      = eth_igb_dev_set_link_up,
 352         .dev_set_link_down    = eth_igb_dev_set_link_down,
 353         .dev_close            = eth_igb_close,
 354         .promiscuous_enable   = eth_igb_promiscuous_enable,
 355         .promiscuous_disable  = eth_igb_promiscuous_disable,
 356         .allmulticast_enable  = eth_igb_allmulticast_enable,
 357         .allmulticast_disable = eth_igb_allmulticast_disable,
 358         .link_update          = eth_igb_link_update,
 359         .stats_get            = eth_igb_stats_get,
 360         .xstats_get           = eth_igb_xstats_get,
 361         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 362         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 363         .xstats_get_names     = eth_igb_xstats_get_names,
 364         .stats_reset          = eth_igb_stats_reset,
 365         .xstats_reset         = eth_igb_xstats_reset,
 366         .fw_version_get       = eth_igb_fw_version_get,
 367         .dev_infos_get        = eth_igb_infos_get,
 368         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 369         .mtu_set              = eth_igb_mtu_set,
 370         .vlan_filter_set      = eth_igb_vlan_filter_set,
 371         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 372         .vlan_offload_set     = eth_igb_vlan_offload_set,
 373         .rx_queue_setup       = eth_igb_rx_queue_setup,
 374         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 375         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 376         .rx_queue_release     = eth_igb_rx_queue_release,
 377         .rx_queue_count       = eth_igb_rx_queue_count,
 378         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 379         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 380         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 381         .tx_queue_setup       = eth_igb_tx_queue_setup,
 382         .tx_queue_release     = eth_igb_tx_queue_release,
 383         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 384         .dev_led_on           = eth_igb_led_on,
 385         .dev_led_off          = eth_igb_led_off,
 386         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 387         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 388         .mac_addr_add         = eth_igb_rar_set,
 389         .mac_addr_remove      = eth_igb_rar_clear,
 390         .mac_addr_set         = eth_igb_default_mac_addr_set,
 391         .reta_update          = eth_igb_rss_reta_update,
 392         .reta_query           = eth_igb_rss_reta_query,
 393         .rss_hash_update      = eth_igb_rss_hash_update,
 394         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 395         .filter_ctrl          = eth_igb_filter_ctrl,
 396         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 397         .rxq_info_get         = igb_rxq_info_get,
 398         .txq_info_get         = igb_txq_info_get,
 399         .timesync_enable      = igb_timesync_enable,
 400         .timesync_disable     = igb_timesync_disable,
 401         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 402         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 403         .get_reg              = eth_igb_get_regs,
 404         .get_eeprom_length    = eth_igb_get_eeprom_length,
 405         .get_eeprom           = eth_igb_get_eeprom,
 406         .set_eeprom           = eth_igb_set_eeprom,
 407         .get_module_info      = eth_igb_get_module_info,
 408         .get_module_eeprom    = eth_igb_get_module_eeprom,
 409         .timesync_adjust_time = igb_timesync_adjust_time,
 410         .timesync_read_time   = igb_timesync_read_time,
 411         .timesync_write_time  = igb_timesync_write_time,
 412 };
 413
 414 /*
 415  * dev_ops for virtual function, bare necessities for basic vf
 416  * operation have been implemented
 417  */
 418 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 419         .dev_configure        = igbvf_dev_configure,
 420         .dev_start            = igbvf_dev_start,
 421         .dev_stop             = igbvf_dev_stop,
 422         .dev_close            = igbvf_dev_close,
 423         .promiscuous_enable   = igbvf_promiscuous_enable,
 424         .promiscuous_disable  = igbvf_promiscuous_disable,
 425         .allmulticast_enable  = igbvf_allmulticast_enable,
 426         .allmulticast_disable = igbvf_allmulticast_disable,
 427         .link_update          = eth_igb_link_update,
 428         .stats_get            = eth_igbvf_stats_get,
 429         .xstats_get           = eth_igbvf_xstats_get,
 430         .xstats_get_names     = eth_igbvf_xstats_get_names,
 431         .stats_reset          = eth_igbvf_stats_reset,
 432         .xstats_reset         = eth_igbvf_stats_reset,
 433         .vlan_filter_set      = igbvf_vlan_filter_set,
 434         .dev_infos_get        = eth_igbvf_infos_get,
 435         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 436         .rx_queue_setup       = eth_igb_rx_queue_setup,
 437         .rx_queue_release     = eth_igb_rx_queue_release,
 438         .tx_queue_setup       = eth_igb_tx_queue_setup,
 439         .tx_queue_release     = eth_igb_tx_queue_release,
 440         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 441         .rxq_info_get         = igb_rxq_info_get,
 442         .txq_info_get         = igb_txq_info_get,
 443         .mac_addr_set         = igbvf_default_mac_addr_set,
 444         .get_reg              = igbvf_get_regs,
 445 };
 446
 447 /* store statistics names and its offset in stats structure */
 448 struct rte_igb_xstats_name_off {
 449         char name[RTE_ETH_XSTATS_NAME_SIZE];
 450         unsigned offset;
 451 };
 452
 453 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 454         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 455         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 456         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 457         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 458         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 459         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 460         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 461                 ecol)},
 462         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 463         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 464         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 465         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 466         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 467         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 468         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 469         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 470         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 471         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 472         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 473                 fcruc)},
 474         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 475         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 476         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 477         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 478         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 479                 prc1023)},
 480         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 481                 prc1522)},
 482         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 483         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 484         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 485         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 486         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 487         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 488         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 489         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 490         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 491         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 492         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 493         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 494         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 495         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 496         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 497         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 498         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 499         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 500                 ptc1023)},
 501         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 502                 ptc1522)},
 503         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 504         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 505         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 506         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 507         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 508         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 509         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 510
 511         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 512 };
 513
 514 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 515                 sizeof(rte_igb_stats_strings[0]))
 516
 517 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 518         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 519         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 520         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 521         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 522         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 523 };
 524
 525 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 526                 sizeof(rte_igbvf_stats_strings[0]))
 527
 528
 529 static inline void
 530 igb_intr_enable(struct rte_eth_dev *dev)
 531 {
 532         struct e1000_interrupt *intr =
 533                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 534         struct e1000_hw *hw =
 535                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 536
 537         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 538         E1000_WRITE_FLUSH(hw);
 539 }
 540
 541 static void
 542 igb_intr_disable(struct e1000_hw *hw)
 543 {
 544         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 545         E1000_WRITE_FLUSH(hw);
 546 }
 547
 548 static inline void
 549 igbvf_intr_enable(struct rte_eth_dev *dev)
 550 {
 551         struct e1000_hw *hw =
 552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 553
 554         /* only for mailbox */
 555         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 556         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 557         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 558         E1000_WRITE_FLUSH(hw);
 559 }
 560
 561 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 562 static void
 563 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 564 {
 565         uint32_t tmp = 0;
 566
 567         /* mailbox */
 568         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 569         tmp |= E1000_VTIVAR_VALID;
 570         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 571 }
 572
 573 static void
 574 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 575 {
 576         struct e1000_hw *hw =
 577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 578
 579         /* Configure VF other cause ivar */
 580         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 581 }
 582
 583 static inline int32_t
 584 igb_pf_reset_hw(struct e1000_hw *hw)
 585 {
 586         uint32_t ctrl_ext;
 587         int32_t status;
 588
 589         status = e1000_reset_hw(hw);
 590
 591         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 592         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 593         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 594         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 595         E1000_WRITE_FLUSH(hw);
 596
 597         return status;
 598 }
 599
 600 static void
 601 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 602 {
 603         struct e1000_hw *hw =
 604                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 605
 606
 607         hw->vendor_id = pci_dev->id.vendor_id;
 608         hw->device_id = pci_dev->id.device_id;
 609         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 610         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 611
 612         e1000_set_mac_type(hw);
 613
 614         /* need to check if it is a vf device below */
 615 }
 616
 617 static int
 618 igb_reset_swfw_lock(struct e1000_hw *hw)
 619 {
 620         int ret_val;
 621
 622         /*
 623          * Do mac ops initialization manually here, since we will need
 624          * some function pointers set by this call.
 625          */
 626         ret_val = e1000_init_mac_params(hw);
 627         if (ret_val)
 628                 return ret_val;
 629
 630         /*
 631          * SMBI lock should not fail in this early stage. If this is the case,
 632          * it is due to an improper exit of the application.
 633          * So force the release of the faulty lock.
 634          */
 635         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 636                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 637         }
 638         e1000_put_hw_semaphore_generic(hw);
 639
 640         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 641                 uint16_t mask;
 642
 643                 /*
 644                  * Phy lock should not fail in this early stage. If this is the case,
 645                  * it is due to an improper exit of the application.
 646                  * So force the release of the faulty lock.
 647                  */
 648                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 649                 if (hw->bus.func > E1000_FUNC_1)
 650                         mask <<= 2;
 651                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 652                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 653                                     hw->bus.func);
 654                 }
 655                 hw->mac.ops.release_swfw_sync(hw, mask);
 656
 657                 /*
 658                  * This one is more tricky since it is common to all ports; but
 659                  * swfw_sync retries last long enough (1s) to be almost sure that if
 660                  * lock can not be taken it is due to an improper lock of the
 661                  * semaphore.
 662                  */
 663                 mask = E1000_SWFW_EEP_SM;
 664                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 665                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 666                 }
 667                 hw->mac.ops.release_swfw_sync(hw, mask);
 668         }
 669
 670         return E1000_SUCCESS;
 671 }
 672
 673 /* Remove all ntuple filters of the device */
 674 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 675 {
 676         struct e1000_filter_info *filter_info =
 677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 678         struct e1000_5tuple_filter *p_5tuple;
 679         struct e1000_2tuple_filter *p_2tuple;
 680
 681         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 682                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 683                         p_5tuple, entries);
 684                         rte_free(p_5tuple);
 685         }
 686         filter_info->fivetuple_mask = 0;
 687         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 688                 TAILQ_REMOVE(&filter_info->twotuple_list,
 689                         p_2tuple, entries);
 690                         rte_free(p_2tuple);
 691         }
 692         filter_info->twotuple_mask = 0;
 693
 694         return 0;
 695 }
 696
 697 /* Remove all flex filters of the device */
 698 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 699 {
 700         struct e1000_filter_info *filter_info =
 701                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 702         struct e1000_flex_filter *p_flex;
 703
 704         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 705                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 706                 rte_free(p_flex);
 707         }
 708         filter_info->flex_mask = 0;
 709
 710         return 0;
 711 }
 712
 713 static int
 714 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 715 {
 716         int error = 0;
 717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 718         struct e1000_hw *hw =
 719                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 720         struct e1000_vfta * shadow_vfta =
 721                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 722         struct e1000_filter_info *filter_info =
 723                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 724         struct e1000_adapter *adapter =
 725                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 726
 727         uint32_t ctrl_ext;
 728
 729         eth_dev->dev_ops = &eth_igb_ops;
 730         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 731         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 732         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 733
 734         /* for secondary processes, we don't initialise any further as primary
 735          * has already done this work. Only check we don't need a different
 736          * RX function */
 737         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 738                 if (eth_dev->data->scattered_rx)
 739                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 740                 return 0;
 741         }
 742
 743         rte_eth_copy_pci_info(eth_dev, pci_dev);
 744
 745         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 746
 747         igb_identify_hardware(eth_dev, pci_dev);
 748         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 749                 error = -EIO;
 750                 goto err_late;
 751         }
 752
 753         e1000_get_bus_info(hw);
 754
 755         /* Reset any pending lock */
 756         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 757                 error = -EIO;
 758                 goto err_late;
 759         }
 760
 761         /* Finish initialization */
 762         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 763                 error = -EIO;
 764                 goto err_late;
 765         }
 766
 767         hw->mac.autoneg = 1;
 768         hw->phy.autoneg_wait_to_complete = 0;
 769         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 770
 771         /* Copper options */
 772         if (hw->phy.media_type == e1000_media_type_copper) {
 773                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 774                 hw->phy.disable_polarity_correction = 0;
 775                 hw->phy.ms_type = e1000_ms_hw_default;
 776         }
 777
 778         /*
 779          * Start from a known state, this is important in reading the nvm
 780          * and mac from that.
 781          */
 782         igb_pf_reset_hw(hw);
 783
 784         /* Make sure we have a good EEPROM before we read from it */
 785         if (e1000_validate_nvm_checksum(hw) < 0) {
 786                 /*
 787                  * Some PCI-E parts fail the first check due to
 788                  * the link being in sleep state, call it again,
 789                  * if it fails a second time its a real issue.
 790                  */
 791                 if (e1000_validate_nvm_checksum(hw) < 0) {
 792                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 793                         error = -EIO;
 794                         goto err_late;
 795                 }
 796         }
 797
 798         /* Read the permanent MAC address out of the EEPROM */
 799         if (e1000_read_mac_addr(hw) != 0) {
 800                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 801                 error = -EIO;
 802                 goto err_late;
 803         }
 804
 805         /* Allocate memory for storing MAC addresses */
 806         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 807                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 808         if (eth_dev->data->mac_addrs == NULL) {
 809                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 810                                                 "store MAC addresses",
 811                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 812                 error = -ENOMEM;
 813                 goto err_late;
 814         }
 815
 816         /* Copy the permanent MAC address */
 817         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 818
 819         /* initialize the vfta */
 820         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 821
 822         /* Now initialize the hardware */
 823         if (igb_hardware_init(hw) != 0) {
 824                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 825                 rte_free(eth_dev->data->mac_addrs);
 826                 eth_dev->data->mac_addrs = NULL;
 827                 error = -ENODEV;
 828                 goto err_late;
 829         }
 830         hw->mac.get_link_status = 1;
 831         adapter->stopped = 0;
 832
 833         /* Indicate SOL/IDER usage */
 834         if (e1000_check_reset_block(hw) < 0) {
 835                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 836                                         "SOL/IDER session");
 837         }
 838
 839         /* initialize PF if max_vfs not zero */
 840         igb_pf_host_init(eth_dev);
 841
 842         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 843         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 844         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 845         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 846         E1000_WRITE_FLUSH(hw);
 847
 848         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 849                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 850                      pci_dev->id.device_id);
 851
 852         rte_intr_callback_register(&pci_dev->intr_handle,
 853                                    eth_igb_interrupt_handler,
 854                                    (void *)eth_dev);
 855
 856         /* enable uio/vfio intr/eventfd mapping */
 857         rte_intr_enable(&pci_dev->intr_handle);
 858
 859         /* enable support intr */
 860         igb_intr_enable(eth_dev);
 861
 862         /* initialize filter info */
 863         memset(filter_info, 0,
 864                sizeof(struct e1000_filter_info));
 865
 866         TAILQ_INIT(&filter_info->flex_list);
 867         TAILQ_INIT(&filter_info->twotuple_list);
 868         TAILQ_INIT(&filter_info->fivetuple_list);
 869
 870         TAILQ_INIT(&igb_filter_ntuple_list);
 871         TAILQ_INIT(&igb_filter_ethertype_list);
 872         TAILQ_INIT(&igb_filter_syn_list);
 873         TAILQ_INIT(&igb_filter_flex_list);
 874         TAILQ_INIT(&igb_filter_rss_list);
 875         TAILQ_INIT(&igb_flow_list);
 876
 877         return 0;
 878
 879 err_late:
 880         igb_hw_control_release(hw);
 881
 882         return error;
 883 }
 884
 885 static int
 886 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 887 {
 888         struct rte_pci_device *pci_dev;
 889         struct rte_intr_handle *intr_handle;
 890         struct e1000_hw *hw;
 891         struct e1000_adapter *adapter =
 892                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 893         struct e1000_filter_info *filter_info =
 894                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 895
 896         PMD_INIT_FUNC_TRACE();
 897
 898         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 899                 return -EPERM;
 900
 901         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 902         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 903         intr_handle = &pci_dev->intr_handle;
 904
 905         if (adapter->stopped == 0)
 906                 eth_igb_close(eth_dev);
 907
 908         eth_dev->dev_ops = NULL;
 909         eth_dev->rx_pkt_burst = NULL;
 910         eth_dev->tx_pkt_burst = NULL;
 911
 912         /* Reset any pending lock */
 913         igb_reset_swfw_lock(hw);
 914
 915         rte_free(eth_dev->data->mac_addrs);
 916         eth_dev->data->mac_addrs = NULL;
 917
 918         /* uninitialize PF if max_vfs not zero */
 919         igb_pf_host_uninit(eth_dev);
 920
 921         /* disable uio intr before callback unregister */
 922         rte_intr_disable(intr_handle);
 923         rte_intr_callback_unregister(intr_handle,
 924                                      eth_igb_interrupt_handler, eth_dev);
 925
 926         /* clear the SYN filter info */
 927         filter_info->syn_info = 0;
 928
 929         /* clear the ethertype filters info */
 930         filter_info->ethertype_mask = 0;
 931         memset(filter_info->ethertype_filters, 0,
 932                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 933
 934         /* clear the rss filter info */
 935         memset(&filter_info->rss_info, 0,
 936                 sizeof(struct igb_rte_flow_rss_conf));
 937
 938         /* remove all ntuple filters of the device */
 939         igb_ntuple_filter_uninit(eth_dev);
 940
 941         /* remove all flex filters of the device */
 942         igb_flex_filter_uninit(eth_dev);
 943
 944         /* clear all the filters list */
 945         igb_filterlist_flush(eth_dev);
 946
 947         return 0;
 948 }
 949
 950 /*
 951  * Virtual Function device init
 952  */
 953 static int
 954 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 955 {
 956         struct rte_pci_device *pci_dev;
 957         struct rte_intr_handle *intr_handle;
 958         struct e1000_adapter *adapter =
 959                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 960         struct e1000_hw *hw =
 961                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 962         int diag;
 963         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 964
 965         PMD_INIT_FUNC_TRACE();
 966
 967         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 968         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 969         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 970         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 971
 972         /* for secondary processes, we don't initialise any further as primary
 973          * has already done this work. Only check we don't need a different
 974          * RX function */
 975         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 976                 if (eth_dev->data->scattered_rx)
 977                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 978                 return 0;
 979         }
 980
 981         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 982         rte_eth_copy_pci_info(eth_dev, pci_dev);
 983
 984         hw->device_id = pci_dev->id.device_id;
 985         hw->vendor_id = pci_dev->id.vendor_id;
 986         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 987         adapter->stopped = 0;
 988
 989         /* Initialize the shared code (base driver) */
 990         diag = e1000_setup_init_funcs(hw, TRUE);
 991         if (diag != 0) {
 992                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 993                         diag);
 994                 return -EIO;
 995         }
 996
 997         /* init_mailbox_params */
 998         hw->mbx.ops.init_params(hw);
 999
1000         /* Disable the interrupts for VF */
1001         igbvf_intr_disable(hw);
1002
1003         diag = hw->mac.ops.reset_hw(hw);
1004
1005         /* Allocate memory for storing MAC addresses */
1006         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1007                 hw->mac.rar_entry_count, 0);
1008         if (eth_dev->data->mac_addrs == NULL) {
1009                 PMD_INIT_LOG(ERR,
1010                         "Failed to allocate %d bytes needed to store MAC "
1011                         "addresses",
1012                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1013                 return -ENOMEM;
1014         }
1015
1016         /* Generate a random MAC address, if none was assigned by PF. */
1017         if (is_zero_ether_addr(perm_addr)) {
1018                 eth_random_addr(perm_addr->addr_bytes);
1019                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1020                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1021                              "%02x:%02x:%02x:%02x:%02x:%02x",
1022                              perm_addr->addr_bytes[0],
1023                              perm_addr->addr_bytes[1],
1024                              perm_addr->addr_bytes[2],
1025                              perm_addr->addr_bytes[3],
1026                              perm_addr->addr_bytes[4],
1027                              perm_addr->addr_bytes[5]);
1028         }
1029
1030         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1031         if (diag) {
1032                 rte_free(eth_dev->data->mac_addrs);
1033                 eth_dev->data->mac_addrs = NULL;
1034                 return diag;
1035         }
1036         /* Copy the permanent MAC address */
1037         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1038                         &eth_dev->data->mac_addrs[0]);
1039
1040         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1041                      "mac.type=%s",
1042                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1043                      pci_dev->id.device_id, "igb_mac_82576_vf");
1044
1045         intr_handle = &pci_dev->intr_handle;
1046         rte_intr_callback_register(intr_handle,
1047                                    eth_igbvf_interrupt_handler, eth_dev);
1048
1049         return 0;
1050 }
1051
1052 static int
1053 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1054 {
1055         struct e1000_adapter *adapter =
1056                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1058
1059         PMD_INIT_FUNC_TRACE();
1060
1061         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1062                 return -EPERM;
1063
1064         if (adapter->stopped == 0)
1065                 igbvf_dev_close(eth_dev);
1066
1067         eth_dev->dev_ops = NULL;
1068         eth_dev->rx_pkt_burst = NULL;
1069         eth_dev->tx_pkt_burst = NULL;
1070
1071         rte_free(eth_dev->data->mac_addrs);
1072         eth_dev->data->mac_addrs = NULL;
1073
1074         /* disable uio intr before callback unregister */
1075         rte_intr_disable(&pci_dev->intr_handle);
1076         rte_intr_callback_unregister(&pci_dev->intr_handle,
1077                                      eth_igbvf_interrupt_handler,
1078                                      (void *)eth_dev);
1079
1080         return 0;
1081 }
1082
1083 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1084         struct rte_pci_device *pci_dev)
1085 {
1086         return rte_eth_dev_pci_generic_probe(pci_dev,
1087                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1088 }
1089
1090 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1091 {
1092         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1093 }
1094
1095 static struct rte_pci_driver rte_igb_pmd = {
1096         .id_table = pci_id_igb_map,
1097         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1098                      RTE_PCI_DRV_IOVA_AS_VA,
1099         .probe = eth_igb_pci_probe,
1100         .remove = eth_igb_pci_remove,
1101 };
1102
1103
1104 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1105         struct rte_pci_device *pci_dev)
1106 {
1107         return rte_eth_dev_pci_generic_probe(pci_dev,
1108                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1109 }
1110
1111 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1112 {
1113         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1114 }
1115
1116 /*
1117  * virtual function driver struct
1118  */
1119 static struct rte_pci_driver rte_igbvf_pmd = {
1120         .id_table = pci_id_igbvf_map,
1121         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1122         .probe = eth_igbvf_pci_probe,
1123         .remove = eth_igbvf_pci_remove,
1124 };
1125
1126 static void
1127 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1128 {
1129         struct e1000_hw *hw =
1130                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1131         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1132         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1133         rctl |= E1000_RCTL_VFE;
1134         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1135 }
1136
1137 static int
1138 igb_check_mq_mode(struct rte_eth_dev *dev)
1139 {
1140         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1141         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1142         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1143         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1144
1145         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1146             tx_mq_mode == ETH_MQ_TX_DCB ||
1147             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1148                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1149                 return -EINVAL;
1150         }
1151         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1152                 /* Check multi-queue mode.
1153                  * To no break software we accept ETH_MQ_RX_NONE as this might
1154                  * be used to turn off VLAN filter.
1155                  */
1156
1157                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1158                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1159                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1160                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1161                 } else {
1162                         /* Only support one queue on VFs.
1163                          * RSS together with SRIOV is not supported.
1164                          */
1165                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1166                                         " wrong mq_mode rx %d.",
1167                                         rx_mq_mode);
1168                         return -EINVAL;
1169                 }
1170                 /* TX mode is not used here, so mode might be ignored.*/
1171                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1172                         /* SRIOV only works in VMDq enable mode */
1173                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1174                                         " TX mode %d is not supported. "
1175                                         " Driver will behave as %d mode.",
1176                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1177                 }
1178
1179                 /* check valid queue number */
1180                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1181                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1182                                         " only support one queue on VFs.");
1183                         return -EINVAL;
1184                 }
1185         } else {
1186                 /* To no break software that set invalid mode, only display
1187                  * warning if invalid mode is used.
1188                  */
1189                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1190                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1191                     rx_mq_mode != ETH_MQ_RX_RSS) {
1192                         /* RSS together with VMDq not supported*/
1193                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1194                                      rx_mq_mode);
1195                         return -EINVAL;
1196                 }
1197
1198                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1199                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1200                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1201                                         " Due to txmode is meaningless in this"
1202                                         " driver, just ignore.",
1203                                         tx_mq_mode);
1204                 }
1205         }
1206         return 0;
1207 }
1208
1209 static int
1210 eth_igb_configure(struct rte_eth_dev *dev)
1211 {
1212         struct e1000_interrupt *intr =
1213                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1214         int ret;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         /* multipe queue mode checking */
1219         ret  = igb_check_mq_mode(dev);
1220         if (ret != 0) {
1221                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1222                             ret);
1223                 return ret;
1224         }
1225
1226         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1227         PMD_INIT_FUNC_TRACE();
1228
1229         return 0;
1230 }
1231
1232 static void
1233 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1234                      bool enable)
1235 {
1236         struct e1000_hw *hw =
1237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238         uint32_t tctl, rctl;
1239
1240         tctl = E1000_READ_REG(hw, E1000_TCTL);
1241         rctl = E1000_READ_REG(hw, E1000_RCTL);
1242
1243         if (enable) {
1244                 /* enable Tx/Rx */
1245                 tctl |= E1000_TCTL_EN;
1246                 rctl |= E1000_RCTL_EN;
1247         } else {
1248                 /* disable Tx/Rx */
1249                 tctl &= ~E1000_TCTL_EN;
1250                 rctl &= ~E1000_RCTL_EN;
1251         }
1252         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1253         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1254         E1000_WRITE_FLUSH(hw);
1255 }
1256
1257 static int
1258 eth_igb_start(struct rte_eth_dev *dev)
1259 {
1260         struct e1000_hw *hw =
1261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262         struct e1000_adapter *adapter =
1263                 E1000_DEV_PRIVATE(dev->data->dev_private);
1264         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1265         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1266         int ret, mask;
1267         uint32_t intr_vector = 0;
1268         uint32_t ctrl_ext;
1269         uint32_t *speeds;
1270         int num_speeds;
1271         bool autoneg;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         /* disable uio/vfio intr/eventfd mapping */
1276         rte_intr_disable(intr_handle);
1277
1278         /* Power up the phy. Needed to make the link go Up */
1279         eth_igb_dev_set_link_up(dev);
1280
1281         /*
1282          * Packet Buffer Allocation (PBA)
1283          * Writing PBA sets the receive portion of the buffer
1284          * the remainder is used for the transmit buffer.
1285          */
1286         if (hw->mac.type == e1000_82575) {
1287                 uint32_t pba;
1288
1289                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1290                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1291         }
1292
1293         /* Put the address into the Receive Address Array */
1294         e1000_rar_set(hw, hw->mac.addr, 0);
1295
1296         /* Initialize the hardware */
1297         if (igb_hardware_init(hw)) {
1298                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1299                 return -EIO;
1300         }
1301         adapter->stopped = 0;
1302
1303         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1304
1305         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1306         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1307         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1308         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1309         E1000_WRITE_FLUSH(hw);
1310
1311         /* configure PF module if SRIOV enabled */
1312         igb_pf_host_configure(dev);
1313
1314         /* check and configure queue intr-vector mapping */
1315         if ((rte_intr_cap_multiple(intr_handle) ||
1316              !RTE_ETH_DEV_SRIOV(dev).active) &&
1317             dev->data->dev_conf.intr_conf.rxq != 0) {
1318                 intr_vector = dev->data->nb_rx_queues;
1319                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1320                         return -1;
1321         }
1322
1323         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1324                 intr_handle->intr_vec =
1325                         rte_zmalloc("intr_vec",
1326                                     dev->data->nb_rx_queues * sizeof(int), 0);
1327                 if (intr_handle->intr_vec == NULL) {
1328                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1329                                      " intr_vec", dev->data->nb_rx_queues);
1330                         return -ENOMEM;
1331                 }
1332         }
1333
1334         /* confiugre msix for rx interrupt */
1335         eth_igb_configure_msix_intr(dev);
1336
1337         /* Configure for OS presence */
1338         igb_init_manageability(hw);
1339
1340         eth_igb_tx_init(dev);
1341
1342         /* This can fail when allocating mbufs for descriptor rings */
1343         ret = eth_igb_rx_init(dev);
1344         if (ret) {
1345                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1346                 igb_dev_clear_queues(dev);
1347                 return ret;
1348         }
1349
1350         e1000_clear_hw_cntrs_base_generic(hw);
1351
1352         /*
1353          * VLAN Offload Settings
1354          */
1355         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1356                         ETH_VLAN_EXTEND_MASK;
1357         ret = eth_igb_vlan_offload_set(dev, mask);
1358         if (ret) {
1359                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1360                 igb_dev_clear_queues(dev);
1361                 return ret;
1362         }
1363
1364         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1365                 /* Enable VLAN filter since VMDq always use VLAN filter */
1366                 igb_vmdq_vlan_hw_filter_enable(dev);
1367         }
1368
1369         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1370                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1371                 (hw->mac.type == e1000_i211)) {
1372                 /* Configure EITR with the maximum possible value (0xFFFF) */
1373                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1374         }
1375
1376         /* Setup link speed and duplex */
1377         speeds = &dev->data->dev_conf.link_speeds;
1378         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1379                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1380                 hw->mac.autoneg = 1;
1381         } else {
1382                 num_speeds = 0;
1383                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1384
1385                 /* Reset */
1386                 hw->phy.autoneg_advertised = 0;
1387
1388                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1389                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1390                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1391                         num_speeds = -1;
1392                         goto error_invalid_config;
1393                 }
1394                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1395                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1396                         num_speeds++;
1397                 }
1398                 if (*speeds & ETH_LINK_SPEED_10M) {
1399                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1400                         num_speeds++;
1401                 }
1402                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1403                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1404                         num_speeds++;
1405                 }
1406                 if (*speeds & ETH_LINK_SPEED_100M) {
1407                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1408                         num_speeds++;
1409                 }
1410                 if (*speeds & ETH_LINK_SPEED_1G) {
1411                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1412                         num_speeds++;
1413                 }
1414                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1415                         goto error_invalid_config;
1416
1417                 /* Set/reset the mac.autoneg based on the link speed,
1418                  * fixed or not
1419                  */
1420                 if (!autoneg) {
1421                         hw->mac.autoneg = 0;
1422                         hw->mac.forced_speed_duplex =
1423                                         hw->phy.autoneg_advertised;
1424                 } else {
1425                         hw->mac.autoneg = 1;
1426                 }
1427         }
1428
1429         e1000_setup_link(hw);
1430
1431         if (rte_intr_allow_others(intr_handle)) {
1432                 /* check if lsc interrupt is enabled */
1433                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1434                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1435                 else
1436                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1437         } else {
1438                 rte_intr_callback_unregister(intr_handle,
1439                                              eth_igb_interrupt_handler,
1440                                              (void *)dev);
1441                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1442                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1443                                      " no intr multiplex");
1444         }
1445
1446         /* check if rxq interrupt is enabled */
1447         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1448             rte_intr_dp_is_en(intr_handle))
1449                 eth_igb_rxq_interrupt_setup(dev);
1450
1451         /* enable uio/vfio intr/eventfd mapping */
1452         rte_intr_enable(intr_handle);
1453
1454         /* resume enabled intr since hw reset */
1455         igb_intr_enable(dev);
1456
1457         /* restore all types filter */
1458         igb_filter_restore(dev);
1459
1460         eth_igb_rxtx_control(dev, true);
1461         eth_igb_link_update(dev, 0);
1462
1463         PMD_INIT_LOG(DEBUG, "<<");
1464
1465         return 0;
1466
1467 error_invalid_config:
1468         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1469                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1470         igb_dev_clear_queues(dev);
1471         return -EINVAL;
1472 }
1473
1474 /*********************************************************************
1475  *
1476  *  This routine disables all traffic on the adapter by issuing a
1477  *  global reset on the MAC.
1478  *
1479  **********************************************************************/
1480 static void
1481 eth_igb_stop(struct rte_eth_dev *dev)
1482 {
1483         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1485         struct rte_eth_link link;
1486         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1487
1488         eth_igb_rxtx_control(dev, false);
1489
1490         igb_intr_disable(hw);
1491
1492         /* disable intr eventfd mapping */
1493         rte_intr_disable(intr_handle);
1494
1495         igb_pf_reset_hw(hw);
1496         E1000_WRITE_REG(hw, E1000_WUC, 0);
1497
1498         /* Set bit for Go Link disconnect */
1499         if (hw->mac.type >= e1000_82580) {
1500                 uint32_t phpm_reg;
1501
1502                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1503                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1504                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1505         }
1506
1507         /* Power down the phy. Needed to make the link go Down */
1508         eth_igb_dev_set_link_down(dev);
1509
1510         igb_dev_clear_queues(dev);
1511
1512         /* clear the recorded link status */
1513         memset(&link, 0, sizeof(link));
1514         rte_eth_linkstatus_set(dev, &link);
1515
1516         if (!rte_intr_allow_others(intr_handle))
1517                 /* resume to the default handler */
1518                 rte_intr_callback_register(intr_handle,
1519                                            eth_igb_interrupt_handler,
1520                                            (void *)dev);
1521
1522         /* Clean datapath event and queue/vec mapping */
1523         rte_intr_efd_disable(intr_handle);
1524         if (intr_handle->intr_vec != NULL) {
1525                 rte_free(intr_handle->intr_vec);
1526                 intr_handle->intr_vec = NULL;
1527         }
1528 }
1529
1530 static int
1531 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1532 {
1533         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534
1535         if (hw->phy.media_type == e1000_media_type_copper)
1536                 e1000_power_up_phy(hw);
1537         else
1538                 e1000_power_up_fiber_serdes_link(hw);
1539
1540         return 0;
1541 }
1542
1543 static int
1544 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1545 {
1546         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1547
1548         if (hw->phy.media_type == e1000_media_type_copper)
1549                 e1000_power_down_phy(hw);
1550         else
1551                 e1000_shutdown_fiber_serdes_link(hw);
1552
1553         return 0;
1554 }
1555
1556 static void
1557 eth_igb_close(struct rte_eth_dev *dev)
1558 {
1559         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         struct e1000_adapter *adapter =
1561                 E1000_DEV_PRIVATE(dev->data->dev_private);
1562         struct rte_eth_link link;
1563         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1564         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1565
1566         eth_igb_stop(dev);
1567         adapter->stopped = 1;
1568
1569         e1000_phy_hw_reset(hw);
1570         igb_release_manageability(hw);
1571         igb_hw_control_release(hw);
1572
1573         /* Clear bit for Go Link disconnect */
1574         if (hw->mac.type >= e1000_82580) {
1575                 uint32_t phpm_reg;
1576
1577                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1578                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1579                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1580         }
1581
1582         igb_dev_free_queues(dev);
1583
1584         if (intr_handle->intr_vec) {
1585                 rte_free(intr_handle->intr_vec);
1586                 intr_handle->intr_vec = NULL;
1587         }
1588
1589         memset(&link, 0, sizeof(link));
1590         rte_eth_linkstatus_set(dev, &link);
1591 }
1592
1593 static int
1594 igb_get_rx_buffer_size(struct e1000_hw *hw)
1595 {
1596         uint32_t rx_buf_size;
1597         if (hw->mac.type == e1000_82576) {
1598                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1599         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1600                 /* PBS needs to be translated according to a lookup table */
1601                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1602                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1603                 rx_buf_size = (rx_buf_size << 10);
1604         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1605                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1606         } else {
1607                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1608         }
1609
1610         return rx_buf_size;
1611 }
1612
1613 /*********************************************************************
1614  *
1615  *  Initialize the hardware
1616  *
1617  **********************************************************************/
1618 static int
1619 igb_hardware_init(struct e1000_hw *hw)
1620 {
1621         uint32_t rx_buf_size;
1622         int diag;
1623
1624         /* Let the firmware know the OS is in control */
1625         igb_hw_control_acquire(hw);
1626
1627         /*
1628          * These parameters control the automatic generation (Tx) and
1629          * response (Rx) to Ethernet PAUSE frames.
1630          * - High water mark should allow for at least two standard size (1518)
1631          *   frames to be received after sending an XOFF.
1632          * - Low water mark works best when it is very near the high water mark.
1633          *   This allows the receiver to restart by sending XON when it has
1634          *   drained a bit. Here we use an arbitrary value of 1500 which will
1635          *   restart after one full frame is pulled from the buffer. There
1636          *   could be several smaller frames in the buffer and if so they will
1637          *   not trigger the XON until their total number reduces the buffer
1638          *   by 1500.
1639          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1640          */
1641         rx_buf_size = igb_get_rx_buffer_size(hw);
1642
1643         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1644         hw->fc.low_water = hw->fc.high_water - 1500;
1645         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1646         hw->fc.send_xon = 1;
1647
1648         /* Set Flow control, use the tunable location if sane */
1649         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1650                 hw->fc.requested_mode = igb_fc_setting;
1651         else
1652                 hw->fc.requested_mode = e1000_fc_none;
1653
1654         /* Issue a global reset */
1655         igb_pf_reset_hw(hw);
1656         E1000_WRITE_REG(hw, E1000_WUC, 0);
1657
1658         diag = e1000_init_hw(hw);
1659         if (diag < 0)
1660                 return diag;
1661
1662         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1663         e1000_get_phy_info(hw);
1664         e1000_check_for_link(hw);
1665
1666         return 0;
1667 }
1668
1669 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1670 static void
1671 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1672 {
1673         int pause_frames;
1674
1675         uint64_t old_gprc  = stats->gprc;
1676         uint64_t old_gptc  = stats->gptc;
1677         uint64_t old_tpr   = stats->tpr;
1678         uint64_t old_tpt   = stats->tpt;
1679         uint64_t old_rpthc = stats->rpthc;
1680         uint64_t old_hgptc = stats->hgptc;
1681
1682         if(hw->phy.media_type == e1000_media_type_copper ||
1683             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1684                 stats->symerrs +=
1685                     E1000_READ_REG(hw,E1000_SYMERRS);
1686                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1687         }
1688
1689         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1690         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1691         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1692         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1693
1694         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1695         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1696         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1697         stats->dc += E1000_READ_REG(hw, E1000_DC);
1698         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1699         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1700         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1701         /*
1702         ** For watchdog management we need to know if we have been
1703         ** paused during the last interval, so capture that here.
1704         */
1705         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1706         stats->xoffrxc += pause_frames;
1707         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1708         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1709         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1710         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1711         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1712         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1713         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1714         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1715         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1716         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1717         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1718         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1719
1720         /* For the 64-bit byte counters the low dword must be read first. */
1721         /* Both registers clear on the read of the high dword */
1722
1723         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1724         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1725         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1726         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1727         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1728         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1729         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1730
1731         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1732         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1733         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1734         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1735         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1736
1737         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1738         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1739
1740         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1741         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1742         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1743         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1744         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1745         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1746
1747         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1748         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1749         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1750         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1751         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1752         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1753         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1754         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1755
1756         /* Interrupt Counts */
1757
1758         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1759         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1760         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1761         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1762         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1763         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1764         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1765         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1766         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1767
1768         /* Host to Card Statistics */
1769
1770         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1771         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1772         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1773         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1774         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1775         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1776         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1777         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1778         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1779         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1780         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1781         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1782         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1783         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1784         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1785         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1786
1787         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1788         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1789         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1790         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1791         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1792         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1793 }
1794
1795 static int
1796 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1797 {
1798         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799         struct e1000_hw_stats *stats =
1800                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1801
1802         igb_read_stats_registers(hw, stats);
1803
1804         if (rte_stats == NULL)
1805                 return -EINVAL;
1806
1807         /* Rx Errors */
1808         rte_stats->imissed = stats->mpc;
1809         rte_stats->ierrors = stats->crcerrs +
1810                              stats->rlec + stats->ruc + stats->roc +
1811                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1812
1813         /* Tx Errors */
1814         rte_stats->oerrors = stats->ecol + stats->latecol;
1815
1816         rte_stats->ipackets = stats->gprc;
1817         rte_stats->opackets = stats->gptc;
1818         rte_stats->ibytes   = stats->gorc;
1819         rte_stats->obytes   = stats->gotc;
1820         return 0;
1821 }
1822
1823 static void
1824 eth_igb_stats_reset(struct rte_eth_dev *dev)
1825 {
1826         struct e1000_hw_stats *hw_stats =
1827                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1828
1829         /* HW registers are cleared on read */
1830         eth_igb_stats_get(dev, NULL);
1831
1832         /* Reset software totals */
1833         memset(hw_stats, 0, sizeof(*hw_stats));
1834 }
1835
1836 static void
1837 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1838 {
1839         struct e1000_hw_stats *stats =
1840                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1841
1842         /* HW registers are cleared on read */
1843         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1844
1845         /* Reset software totals */
1846         memset(stats, 0, sizeof(*stats));
1847 }
1848
1849 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1850         struct rte_eth_xstat_name *xstats_names,
1851         __rte_unused unsigned int size)
1852 {
1853         unsigned i;
1854
1855         if (xstats_names == NULL)
1856                 return IGB_NB_XSTATS;
1857
1858         /* Note: limit checked in rte_eth_xstats_names() */
1859
1860         for (i = 0; i < IGB_NB_XSTATS; i++) {
1861                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1862                          "%s", rte_igb_stats_strings[i].name);
1863         }
1864
1865         return IGB_NB_XSTATS;
1866 }
1867
1868 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1869                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1870                 unsigned int limit)
1871 {
1872         unsigned int i;
1873
1874         if (!ids) {
1875                 if (xstats_names == NULL)
1876                         return IGB_NB_XSTATS;
1877
1878                 for (i = 0; i < IGB_NB_XSTATS; i++)
1879                         snprintf(xstats_names[i].name,
1880                                         sizeof(xstats_names[i].name),
1881                                         "%s", rte_igb_stats_strings[i].name);
1882
1883                 return IGB_NB_XSTATS;
1884
1885         } else {
1886                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1887
1888                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1889                                 IGB_NB_XSTATS);
1890
1891                 for (i = 0; i < limit; i++) {
1892                         if (ids[i] >= IGB_NB_XSTATS) {
1893                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1894                                 return -1;
1895                         }
1896                         strcpy(xstats_names[i].name,
1897                                         xstats_names_copy[ids[i]].name);
1898                 }
1899                 return limit;
1900         }
1901 }
1902
1903 static int
1904 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1905                    unsigned n)
1906 {
1907         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908         struct e1000_hw_stats *hw_stats =
1909                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1910         unsigned i;
1911
1912         if (n < IGB_NB_XSTATS)
1913                 return IGB_NB_XSTATS;
1914
1915         igb_read_stats_registers(hw, hw_stats);
1916
1917         /* If this is a reset xstats is NULL, and we have cleared the
1918          * registers by reading them.
1919          */
1920         if (!xstats)
1921                 return 0;
1922
1923         /* Extended stats */
1924         for (i = 0; i < IGB_NB_XSTATS; i++) {
1925                 xstats[i].id = i;
1926                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1927                         rte_igb_stats_strings[i].offset);
1928         }
1929
1930         return IGB_NB_XSTATS;
1931 }
1932
1933 static int
1934 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1935                 uint64_t *values, unsigned int n)
1936 {
1937         unsigned int i;
1938
1939         if (!ids) {
1940                 struct e1000_hw *hw =
1941                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942                 struct e1000_hw_stats *hw_stats =
1943                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1944
1945                 if (n < IGB_NB_XSTATS)
1946                         return IGB_NB_XSTATS;
1947
1948                 igb_read_stats_registers(hw, hw_stats);
1949
1950                 /* If this is a reset xstats is NULL, and we have cleared the
1951                  * registers by reading them.
1952                  */
1953                 if (!values)
1954                         return 0;
1955
1956                 /* Extended stats */
1957                 for (i = 0; i < IGB_NB_XSTATS; i++)
1958                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1959                                         rte_igb_stats_strings[i].offset);
1960
1961                 return IGB_NB_XSTATS;
1962
1963         } else {
1964                 uint64_t values_copy[IGB_NB_XSTATS];
1965
1966                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1967                                 IGB_NB_XSTATS);
1968
1969                 for (i = 0; i < n; i++) {
1970                         if (ids[i] >= IGB_NB_XSTATS) {
1971                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1972                                 return -1;
1973                         }
1974                         values[i] = values_copy[ids[i]];
1975                 }
1976                 return n;
1977         }
1978 }
1979
1980 static void
1981 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1982 {
1983         /* Good Rx packets, include VF loopback */
1984         UPDATE_VF_STAT(E1000_VFGPRC,
1985             hw_stats->last_gprc, hw_stats->gprc);
1986
1987         /* Good Rx octets, include VF loopback */
1988         UPDATE_VF_STAT(E1000_VFGORC,
1989             hw_stats->last_gorc, hw_stats->gorc);
1990
1991         /* Good Tx packets, include VF loopback */
1992         UPDATE_VF_STAT(E1000_VFGPTC,
1993             hw_stats->last_gptc, hw_stats->gptc);
1994
1995         /* Good Tx octets, include VF loopback */
1996         UPDATE_VF_STAT(E1000_VFGOTC,
1997             hw_stats->last_gotc, hw_stats->gotc);
1998
1999         /* Rx Multicst packets */
2000         UPDATE_VF_STAT(E1000_VFMPRC,
2001             hw_stats->last_mprc, hw_stats->mprc);
2002
2003         /* Good Rx loopback packets */
2004         UPDATE_VF_STAT(E1000_VFGPRLBC,
2005             hw_stats->last_gprlbc, hw_stats->gprlbc);
2006
2007         /* Good Rx loopback octets */
2008         UPDATE_VF_STAT(E1000_VFGORLBC,
2009             hw_stats->last_gorlbc, hw_stats->gorlbc);
2010
2011         /* Good Tx loopback packets */
2012         UPDATE_VF_STAT(E1000_VFGPTLBC,
2013             hw_stats->last_gptlbc, hw_stats->gptlbc);
2014
2015         /* Good Tx loopback octets */
2016         UPDATE_VF_STAT(E1000_VFGOTLBC,
2017             hw_stats->last_gotlbc, hw_stats->gotlbc);
2018 }
2019
2020 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2021                                      struct rte_eth_xstat_name *xstats_names,
2022                                      __rte_unused unsigned limit)
2023 {
2024         unsigned i;
2025
2026         if (xstats_names != NULL)
2027                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2028                         snprintf(xstats_names[i].name,
2029                                 sizeof(xstats_names[i].name), "%s",
2030                                 rte_igbvf_stats_strings[i].name);
2031                 }
2032         return IGBVF_NB_XSTATS;
2033 }
2034
2035 static int
2036 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2037                      unsigned n)
2038 {
2039         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2041                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2042         unsigned i;
2043
2044         if (n < IGBVF_NB_XSTATS)
2045                 return IGBVF_NB_XSTATS;
2046
2047         igbvf_read_stats_registers(hw, hw_stats);
2048
2049         if (!xstats)
2050                 return 0;
2051
2052         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2053                 xstats[i].id = i;
2054                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2055                         rte_igbvf_stats_strings[i].offset);
2056         }
2057
2058         return IGBVF_NB_XSTATS;
2059 }
2060
2061 static int
2062 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2063 {
2064         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2066                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2067
2068         igbvf_read_stats_registers(hw, hw_stats);
2069
2070         if (rte_stats == NULL)
2071                 return -EINVAL;
2072
2073         rte_stats->ipackets = hw_stats->gprc;
2074         rte_stats->ibytes = hw_stats->gorc;
2075         rte_stats->opackets = hw_stats->gptc;
2076         rte_stats->obytes = hw_stats->gotc;
2077         return 0;
2078 }
2079
2080 static void
2081 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2082 {
2083         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2084                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2085
2086         /* Sync HW register to the last stats */
2087         eth_igbvf_stats_get(dev, NULL);
2088
2089         /* reset HW current stats*/
2090         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2091                offsetof(struct e1000_vf_stats, gprc));
2092 }
2093
2094 static int
2095 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2096                        size_t fw_size)
2097 {
2098         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct e1000_fw_version fw;
2100         int ret;
2101
2102         e1000_get_fw_version(hw, &fw);
2103
2104         switch (hw->mac.type) {
2105         case e1000_i210:
2106         case e1000_i211:
2107                 if (!(e1000_get_flash_presence_i210(hw))) {
2108                         ret = snprintf(fw_version, fw_size,
2109                                  "%2d.%2d-%d",
2110                                  fw.invm_major, fw.invm_minor,
2111                                  fw.invm_img_type);
2112                         break;
2113                 }
2114                 /* fall through */
2115         default:
2116                 /* if option rom is valid, display its version too */
2117                 if (fw.or_valid) {
2118                         ret = snprintf(fw_version, fw_size,
2119                                  "%d.%d, 0x%08x, %d.%d.%d",
2120                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2121                                  fw.or_major, fw.or_build, fw.or_patch);
2122                 /* no option rom */
2123                 } else {
2124                         if (fw.etrack_id != 0X0000) {
2125                                 ret = snprintf(fw_version, fw_size,
2126                                          "%d.%d, 0x%08x",
2127                                          fw.eep_major, fw.eep_minor,
2128                                          fw.etrack_id);
2129                         } else {
2130                                 ret = snprintf(fw_version, fw_size,
2131                                          "%d.%d.%d",
2132                                          fw.eep_major, fw.eep_minor,
2133                                          fw.eep_build);
2134                         }
2135                 }
2136                 break;
2137         }
2138
2139         ret += 1; /* add the size of '\0' */
2140         if (fw_size < (u32)ret)
2141                 return ret;
2142         else
2143                 return 0;
2144 }
2145
2146 static void
2147 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2148 {
2149         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2152         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2153         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2154         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2155         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2156                                     dev_info->rx_queue_offload_capa;
2157         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2158         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2159                                     dev_info->tx_queue_offload_capa;
2160
2161         switch (hw->mac.type) {
2162         case e1000_82575:
2163                 dev_info->max_rx_queues = 4;
2164                 dev_info->max_tx_queues = 4;
2165                 dev_info->max_vmdq_pools = 0;
2166                 break;
2167
2168         case e1000_82576:
2169                 dev_info->max_rx_queues = 16;
2170                 dev_info->max_tx_queues = 16;
2171                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2172                 dev_info->vmdq_queue_num = 16;
2173                 break;
2174
2175         case e1000_82580:
2176                 dev_info->max_rx_queues = 8;
2177                 dev_info->max_tx_queues = 8;
2178                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2179                 dev_info->vmdq_queue_num = 8;
2180                 break;
2181
2182         case e1000_i350:
2183                 dev_info->max_rx_queues = 8;
2184                 dev_info->max_tx_queues = 8;
2185                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2186                 dev_info->vmdq_queue_num = 8;
2187                 break;
2188
2189         case e1000_i354:
2190                 dev_info->max_rx_queues = 8;
2191                 dev_info->max_tx_queues = 8;
2192                 break;
2193
2194         case e1000_i210:
2195                 dev_info->max_rx_queues = 4;
2196                 dev_info->max_tx_queues = 4;
2197                 dev_info->max_vmdq_pools = 0;
2198                 break;
2199
2200         case e1000_i211:
2201                 dev_info->max_rx_queues = 2;
2202                 dev_info->max_tx_queues = 2;
2203                 dev_info->max_vmdq_pools = 0;
2204                 break;
2205
2206         default:
2207                 /* Should not happen */
2208                 break;
2209         }
2210         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2211         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2212         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2213
2214         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2215                 .rx_thresh = {
2216                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2217                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2218                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2219                 },
2220                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2221                 .rx_drop_en = 0,
2222                 .offloads = 0,
2223         };
2224
2225         dev_info->default_txconf = (struct rte_eth_txconf) {
2226                 .tx_thresh = {
2227                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2228                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2229                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2230                 },
2231                 .offloads = 0,
2232         };
2233
2234         dev_info->rx_desc_lim = rx_desc_lim;
2235         dev_info->tx_desc_lim = tx_desc_lim;
2236
2237         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2238                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2239                         ETH_LINK_SPEED_1G;
2240 }
2241
2242 static const uint32_t *
2243 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2244 {
2245         static const uint32_t ptypes[] = {
2246                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2247                 RTE_PTYPE_L2_ETHER,
2248                 RTE_PTYPE_L3_IPV4,
2249                 RTE_PTYPE_L3_IPV4_EXT,
2250                 RTE_PTYPE_L3_IPV6,
2251                 RTE_PTYPE_L3_IPV6_EXT,
2252                 RTE_PTYPE_L4_TCP,
2253                 RTE_PTYPE_L4_UDP,
2254                 RTE_PTYPE_L4_SCTP,
2255                 RTE_PTYPE_TUNNEL_IP,
2256                 RTE_PTYPE_INNER_L3_IPV6,
2257                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2258                 RTE_PTYPE_INNER_L4_TCP,
2259                 RTE_PTYPE_INNER_L4_UDP,
2260                 RTE_PTYPE_UNKNOWN
2261         };
2262
2263         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2264             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2265                 return ptypes;
2266         return NULL;
2267 }
2268
2269 static void
2270 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2271 {
2272         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273
2274         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2275         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2276         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2277         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2278                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2279                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2280                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2281                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2282                                 DEV_TX_OFFLOAD_TCP_TSO;
2283         switch (hw->mac.type) {
2284         case e1000_vfadapt:
2285                 dev_info->max_rx_queues = 2;
2286                 dev_info->max_tx_queues = 2;
2287                 break;
2288         case e1000_vfadapt_i350:
2289                 dev_info->max_rx_queues = 1;
2290                 dev_info->max_tx_queues = 1;
2291                 break;
2292         default:
2293                 /* Should not happen */
2294                 break;
2295         }
2296
2297         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2298         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2299                                     dev_info->rx_queue_offload_capa;
2300         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2301         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2302                                     dev_info->tx_queue_offload_capa;
2303
2304         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2305                 .rx_thresh = {
2306                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2307                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2308                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2309                 },
2310                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2311                 .rx_drop_en = 0,
2312                 .offloads = 0,
2313         };
2314
2315         dev_info->default_txconf = (struct rte_eth_txconf) {
2316                 .tx_thresh = {
2317                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2318                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2319                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2320                 },
2321                 .offloads = 0,
2322         };
2323
2324         dev_info->rx_desc_lim = rx_desc_lim;
2325         dev_info->tx_desc_lim = tx_desc_lim;
2326 }
2327
2328 /* return 0 means link status changed, -1 means not changed */
2329 static int
2330 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2331 {
2332         struct e1000_hw *hw =
2333                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2334         struct rte_eth_link link;
2335         int link_check, count;
2336
2337         link_check = 0;
2338         hw->mac.get_link_status = 1;
2339
2340         /* possible wait-to-complete in up to 9 seconds */
2341         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2342                 /* Read the real link status */
2343                 switch (hw->phy.media_type) {
2344                 case e1000_media_type_copper:
2345                         /* Do the work to read phy */
2346                         e1000_check_for_link(hw);
2347                         link_check = !hw->mac.get_link_status;
2348                         break;
2349
2350                 case e1000_media_type_fiber:
2351                         e1000_check_for_link(hw);
2352                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2353                                       E1000_STATUS_LU);
2354                         break;
2355
2356                 case e1000_media_type_internal_serdes:
2357                         e1000_check_for_link(hw);
2358                         link_check = hw->mac.serdes_has_link;
2359                         break;
2360
2361                 /* VF device is type_unknown */
2362                 case e1000_media_type_unknown:
2363                         eth_igbvf_link_update(hw);
2364                         link_check = !hw->mac.get_link_status;
2365                         break;
2366
2367                 default:
2368                         break;
2369                 }
2370                 if (link_check || wait_to_complete == 0)
2371                         break;
2372                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2373         }
2374         memset(&link, 0, sizeof(link));
2375
2376         /* Now we check if a transition has happened */
2377         if (link_check) {
2378                 uint16_t duplex, speed;
2379                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2380                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2381                                 ETH_LINK_FULL_DUPLEX :
2382                                 ETH_LINK_HALF_DUPLEX;
2383                 link.link_speed = speed;
2384                 link.link_status = ETH_LINK_UP;
2385                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2386                                 ETH_LINK_SPEED_FIXED);
2387         } else if (!link_check) {
2388                 link.link_speed = 0;
2389                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2390                 link.link_status = ETH_LINK_DOWN;
2391                 link.link_autoneg = ETH_LINK_FIXED;
2392         }
2393
2394         return rte_eth_linkstatus_set(dev, &link);
2395 }
2396
2397 /*
2398  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2399  * For ASF and Pass Through versions of f/w this means
2400  * that the driver is loaded.
2401  */
2402 static void
2403 igb_hw_control_acquire(struct e1000_hw *hw)
2404 {
2405         uint32_t ctrl_ext;
2406
2407         /* Let firmware know the driver has taken over */
2408         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2409         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2410 }
2411
2412 /*
2413  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2414  * For ASF and Pass Through versions of f/w this means that the
2415  * driver is no longer loaded.
2416  */
2417 static void
2418 igb_hw_control_release(struct e1000_hw *hw)
2419 {
2420         uint32_t ctrl_ext;
2421
2422         /* Let firmware taken over control of h/w */
2423         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2424         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2425                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2426 }
2427
2428 /*
2429  * Bit of a misnomer, what this really means is
2430  * to enable OS management of the system... aka
2431  * to disable special hardware management features.
2432  */
2433 static void
2434 igb_init_manageability(struct e1000_hw *hw)
2435 {
2436         if (e1000_enable_mng_pass_thru(hw)) {
2437                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2438                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2439
2440                 /* disable hardware interception of ARP */
2441                 manc &= ~(E1000_MANC_ARP_EN);
2442
2443                 /* enable receiving management packets to the host */
2444                 manc |= E1000_MANC_EN_MNG2HOST;
2445                 manc2h |= 1 << 5;  /* Mng Port 623 */
2446                 manc2h |= 1 << 6;  /* Mng Port 664 */
2447                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2448                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2449         }
2450 }
2451
2452 static void
2453 igb_release_manageability(struct e1000_hw *hw)
2454 {
2455         if (e1000_enable_mng_pass_thru(hw)) {
2456                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2457
2458                 manc |= E1000_MANC_ARP_EN;
2459                 manc &= ~E1000_MANC_EN_MNG2HOST;
2460
2461                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2462         }
2463 }
2464
2465 static void
2466 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2467 {
2468         struct e1000_hw *hw =
2469                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470         uint32_t rctl;
2471
2472         rctl = E1000_READ_REG(hw, E1000_RCTL);
2473         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2474         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2475 }
2476
2477 static void
2478 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2479 {
2480         struct e1000_hw *hw =
2481                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482         uint32_t rctl;
2483
2484         rctl = E1000_READ_REG(hw, E1000_RCTL);
2485         rctl &= (~E1000_RCTL_UPE);
2486         if (dev->data->all_multicast == 1)
2487                 rctl |= E1000_RCTL_MPE;
2488         else
2489                 rctl &= (~E1000_RCTL_MPE);
2490         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2491 }
2492
2493 static void
2494 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2495 {
2496         struct e1000_hw *hw =
2497                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         uint32_t rctl;
2499
2500         rctl = E1000_READ_REG(hw, E1000_RCTL);
2501         rctl |= E1000_RCTL_MPE;
2502         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2503 }
2504
2505 static void
2506 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2507 {
2508         struct e1000_hw *hw =
2509                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         uint32_t rctl;
2511
2512         if (dev->data->promiscuous == 1)
2513                 return; /* must remain in all_multicast mode */
2514         rctl = E1000_READ_REG(hw, E1000_RCTL);
2515         rctl &= (~E1000_RCTL_MPE);
2516         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2517 }
2518
2519 static int
2520 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2521 {
2522         struct e1000_hw *hw =
2523                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         struct e1000_vfta * shadow_vfta =
2525                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2526         uint32_t vfta;
2527         uint32_t vid_idx;
2528         uint32_t vid_bit;
2529
2530         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2531                               E1000_VFTA_ENTRY_MASK);
2532         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2533         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2534         if (on)
2535                 vfta |= vid_bit;
2536         else
2537                 vfta &= ~vid_bit;
2538         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2539
2540         /* update local VFTA copy */
2541         shadow_vfta->vfta[vid_idx] = vfta;
2542
2543         return 0;
2544 }
2545
2546 static int
2547 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2548                       enum rte_vlan_type vlan_type,
2549                       uint16_t tpid)
2550 {
2551         struct e1000_hw *hw =
2552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         uint32_t reg, qinq;
2554
2555         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2556         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2557
2558         /* only outer TPID of double VLAN can be configured*/
2559         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2560                 reg = E1000_READ_REG(hw, E1000_VET);
2561                 reg = (reg & (~E1000_VET_VET_EXT)) |
2562                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2563                 E1000_WRITE_REG(hw, E1000_VET, reg);
2564
2565                 return 0;
2566         }
2567
2568         /* all other TPID values are read-only*/
2569         PMD_DRV_LOG(ERR, "Not supported");
2570
2571         return -ENOTSUP;
2572 }
2573
2574 static void
2575 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2576 {
2577         struct e1000_hw *hw =
2578                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         uint32_t reg;
2580
2581         /* Filter Table Disable */
2582         reg = E1000_READ_REG(hw, E1000_RCTL);
2583         reg &= ~E1000_RCTL_CFIEN;
2584         reg &= ~E1000_RCTL_VFE;
2585         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2586 }
2587
2588 static void
2589 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2590 {
2591         struct e1000_hw *hw =
2592                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         struct e1000_vfta * shadow_vfta =
2594                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2595         uint32_t reg;
2596         int i;
2597
2598         /* Filter Table Enable, CFI not used for packet acceptance */
2599         reg = E1000_READ_REG(hw, E1000_RCTL);
2600         reg &= ~E1000_RCTL_CFIEN;
2601         reg |= E1000_RCTL_VFE;
2602         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2603
2604         /* restore VFTA table */
2605         for (i = 0; i < IGB_VFTA_SIZE; i++)
2606                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2607 }
2608
2609 static void
2610 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2611 {
2612         struct e1000_hw *hw =
2613                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         uint32_t reg;
2615
2616         /* VLAN Mode Disable */
2617         reg = E1000_READ_REG(hw, E1000_CTRL);
2618         reg &= ~E1000_CTRL_VME;
2619         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2620 }
2621
2622 static void
2623 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2624 {
2625         struct e1000_hw *hw =
2626                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627         uint32_t reg;
2628
2629         /* VLAN Mode Enable */
2630         reg = E1000_READ_REG(hw, E1000_CTRL);
2631         reg |= E1000_CTRL_VME;
2632         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2633 }
2634
2635 static void
2636 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2637 {
2638         struct e1000_hw *hw =
2639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         uint32_t reg;
2641
2642         /* CTRL_EXT: Extended VLAN */
2643         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2644         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2645         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2646
2647         /* Update maximum packet length */
2648         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2649                 E1000_WRITE_REG(hw, E1000_RLPML,
2650                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2651                                                 VLAN_TAG_SIZE);
2652 }
2653
2654 static void
2655 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2656 {
2657         struct e1000_hw *hw =
2658                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659         uint32_t reg;
2660
2661         /* CTRL_EXT: Extended VLAN */
2662         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2663         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2664         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2665
2666         /* Update maximum packet length */
2667         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2668                 E1000_WRITE_REG(hw, E1000_RLPML,
2669                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2670                                                 2 * VLAN_TAG_SIZE);
2671 }
2672
2673 static int
2674 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2675 {
2676         struct rte_eth_rxmode *rxmode;
2677
2678         rxmode = &dev->data->dev_conf.rxmode;
2679         if(mask & ETH_VLAN_STRIP_MASK){
2680                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2681                         igb_vlan_hw_strip_enable(dev);
2682                 else
2683                         igb_vlan_hw_strip_disable(dev);
2684         }
2685
2686         if(mask & ETH_VLAN_FILTER_MASK){
2687                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2688                         igb_vlan_hw_filter_enable(dev);
2689                 else
2690                         igb_vlan_hw_filter_disable(dev);
2691         }
2692
2693         if(mask & ETH_VLAN_EXTEND_MASK){
2694                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2695                         igb_vlan_hw_extend_enable(dev);
2696                 else
2697                         igb_vlan_hw_extend_disable(dev);
2698         }
2699
2700         return 0;
2701 }
2702
2703
2704 /**
2705  * It enables the interrupt mask and then enable the interrupt.
2706  *
2707  * @param dev
2708  *  Pointer to struct rte_eth_dev.
2709  * @param on
2710  *  Enable or Disable
2711  *
2712  * @return
2713  *  - On success, zero.
2714  *  - On failure, a negative value.
2715  */
2716 static int
2717 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2718 {
2719         struct e1000_interrupt *intr =
2720                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2721
2722         if (on)
2723                 intr->mask |= E1000_ICR_LSC;
2724         else
2725                 intr->mask &= ~E1000_ICR_LSC;
2726
2727         return 0;
2728 }
2729
2730 /* It clears the interrupt causes and enables the interrupt.
2731  * It will be called once only during nic initialized.
2732  *
2733  * @param dev
2734  *  Pointer to struct rte_eth_dev.
2735  *
2736  * @return
2737  *  - On success, zero.
2738  *  - On failure, a negative value.
2739  */
2740 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2741 {
2742         uint32_t mask, regval;
2743         struct e1000_hw *hw =
2744                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745         struct rte_eth_dev_info dev_info;
2746
2747         memset(&dev_info, 0, sizeof(dev_info));
2748         eth_igb_infos_get(dev, &dev_info);
2749
2750         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2751         regval = E1000_READ_REG(hw, E1000_EIMS);
2752         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2753
2754         return 0;
2755 }
2756
2757 /*
2758  * It reads ICR and gets interrupt causes, check it and set a bit flag
2759  * to update link status.
2760  *
2761  * @param dev
2762  *  Pointer to struct rte_eth_dev.
2763  *
2764  * @return
2765  *  - On success, zero.
2766  *  - On failure, a negative value.
2767  */
2768 static int
2769 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2770 {
2771         uint32_t icr;
2772         struct e1000_hw *hw =
2773                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         struct e1000_interrupt *intr =
2775                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2776
2777         igb_intr_disable(hw);
2778
2779         /* read-on-clear nic registers here */
2780         icr = E1000_READ_REG(hw, E1000_ICR);
2781
2782         intr->flags = 0;
2783         if (icr & E1000_ICR_LSC) {
2784                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2785         }
2786
2787         if (icr & E1000_ICR_VMMB)
2788                 intr->flags |= E1000_FLAG_MAILBOX;
2789
2790         return 0;
2791 }
2792
2793 /*
2794  * It executes link_update after knowing an interrupt is prsent.
2795  *
2796  * @param dev
2797  *  Pointer to struct rte_eth_dev.
2798  *
2799  * @return
2800  *  - On success, zero.
2801  *  - On failure, a negative value.
2802  */
2803 static int
2804 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2805                          struct rte_intr_handle *intr_handle)
2806 {
2807         struct e1000_hw *hw =
2808                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         struct e1000_interrupt *intr =
2810                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2811         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2812         struct rte_eth_link link;
2813         int ret;
2814
2815         if (intr->flags & E1000_FLAG_MAILBOX) {
2816                 igb_pf_mbx_process(dev);
2817                 intr->flags &= ~E1000_FLAG_MAILBOX;
2818         }
2819
2820         igb_intr_enable(dev);
2821         rte_intr_enable(intr_handle);
2822
2823         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2824                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2825
2826                 /* set get_link_status to check register later */
2827                 hw->mac.get_link_status = 1;
2828                 ret = eth_igb_link_update(dev, 0);
2829
2830                 /* check if link has changed */
2831                 if (ret < 0)
2832                         return 0;
2833
2834                 rte_eth_linkstatus_get(dev, &link);
2835                 if (link.link_status) {
2836                         PMD_INIT_LOG(INFO,
2837                                      " Port %d: Link Up - speed %u Mbps - %s",
2838                                      dev->data->port_id,
2839                                      (unsigned)link.link_speed,
2840                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2841                                      "full-duplex" : "half-duplex");
2842                 } else {
2843                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2844                                      dev->data->port_id);
2845                 }
2846
2847                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2848                              pci_dev->addr.domain,
2849                              pci_dev->addr.bus,
2850                              pci_dev->addr.devid,
2851                              pci_dev->addr.function);
2852                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2853                                               NULL);
2854         }
2855
2856         return 0;
2857 }
2858
2859 /**
2860  * Interrupt handler which shall be registered at first.
2861  *
2862  * @param handle
2863  *  Pointer to interrupt handle.
2864  * @param param
2865  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2866  *
2867  * @return
2868  *  void
2869  */
2870 static void
2871 eth_igb_interrupt_handler(void *param)
2872 {
2873         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2874
2875         eth_igb_interrupt_get_status(dev);
2876         eth_igb_interrupt_action(dev, dev->intr_handle);
2877 }
2878
2879 static int
2880 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2881 {
2882         uint32_t eicr;
2883         struct e1000_hw *hw =
2884                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885         struct e1000_interrupt *intr =
2886                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2887
2888         igbvf_intr_disable(hw);
2889
2890         /* read-on-clear nic registers here */
2891         eicr = E1000_READ_REG(hw, E1000_EICR);
2892         intr->flags = 0;
2893
2894         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2895                 intr->flags |= E1000_FLAG_MAILBOX;
2896
2897         return 0;
2898 }
2899
2900 void igbvf_mbx_process(struct rte_eth_dev *dev)
2901 {
2902         struct e1000_hw *hw =
2903                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2904         struct e1000_mbx_info *mbx = &hw->mbx;
2905         u32 in_msg = 0;
2906
2907         /* peek the message first */
2908         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2909
2910         /* PF reset VF event */
2911         if (in_msg == E1000_PF_CONTROL_MSG) {
2912                 /* dummy mbx read to ack pf */
2913                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2914                         return;
2915                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2916                                               NULL);
2917         }
2918 }
2919
2920 static int
2921 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2922 {
2923         struct e1000_interrupt *intr =
2924                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2925
2926         if (intr->flags & E1000_FLAG_MAILBOX) {
2927                 igbvf_mbx_process(dev);
2928                 intr->flags &= ~E1000_FLAG_MAILBOX;
2929         }
2930
2931         igbvf_intr_enable(dev);
2932         rte_intr_enable(intr_handle);
2933
2934         return 0;
2935 }
2936
2937 static void
2938 eth_igbvf_interrupt_handler(void *param)
2939 {
2940         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2941
2942         eth_igbvf_interrupt_get_status(dev);
2943         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2944 }
2945
2946 static int
2947 eth_igb_led_on(struct rte_eth_dev *dev)
2948 {
2949         struct e1000_hw *hw;
2950
2951         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2953 }
2954
2955 static int
2956 eth_igb_led_off(struct rte_eth_dev *dev)
2957 {
2958         struct e1000_hw *hw;
2959
2960         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2962 }
2963
2964 static int
2965 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2966 {
2967         struct e1000_hw *hw;
2968         uint32_t ctrl;
2969         int tx_pause;
2970         int rx_pause;
2971
2972         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         fc_conf->pause_time = hw->fc.pause_time;
2974         fc_conf->high_water = hw->fc.high_water;
2975         fc_conf->low_water = hw->fc.low_water;
2976         fc_conf->send_xon = hw->fc.send_xon;
2977         fc_conf->autoneg = hw->mac.autoneg;
2978
2979         /*
2980          * Return rx_pause and tx_pause status according to actual setting of
2981          * the TFCE and RFCE bits in the CTRL register.
2982          */
2983         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2984         if (ctrl & E1000_CTRL_TFCE)
2985                 tx_pause = 1;
2986         else
2987                 tx_pause = 0;
2988
2989         if (ctrl & E1000_CTRL_RFCE)
2990                 rx_pause = 1;
2991         else
2992                 rx_pause = 0;
2993
2994         if (rx_pause && tx_pause)
2995                 fc_conf->mode = RTE_FC_FULL;
2996         else if (rx_pause)
2997                 fc_conf->mode = RTE_FC_RX_PAUSE;
2998         else if (tx_pause)
2999                 fc_conf->mode = RTE_FC_TX_PAUSE;
3000         else
3001                 fc_conf->mode = RTE_FC_NONE;
3002
3003         return 0;
3004 }
3005
3006 static int
3007 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3008 {
3009         struct e1000_hw *hw;
3010         int err;
3011         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3012                 e1000_fc_none,
3013                 e1000_fc_rx_pause,
3014                 e1000_fc_tx_pause,
3015                 e1000_fc_full
3016         };
3017         uint32_t rx_buf_size;
3018         uint32_t max_high_water;
3019         uint32_t rctl;
3020
3021         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         if (fc_conf->autoneg != hw->mac.autoneg)
3023                 return -ENOTSUP;
3024         rx_buf_size = igb_get_rx_buffer_size(hw);
3025         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3026
3027         /* At least reserve one Ethernet frame for watermark */
3028         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3029         if ((fc_conf->high_water > max_high_water) ||
3030             (fc_conf->high_water < fc_conf->low_water)) {
3031                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3032                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3033                 return -EINVAL;
3034         }
3035
3036         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3037         hw->fc.pause_time     = fc_conf->pause_time;
3038         hw->fc.high_water     = fc_conf->high_water;
3039         hw->fc.low_water      = fc_conf->low_water;
3040         hw->fc.send_xon       = fc_conf->send_xon;
3041
3042         err = e1000_setup_link_generic(hw);
3043         if (err == E1000_SUCCESS) {
3044
3045                 /* check if we want to forward MAC frames - driver doesn't have native
3046                  * capability to do that, so we'll write the registers ourselves */
3047
3048                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3049
3050                 /* set or clear MFLCN.PMCF bit depending on configuration */
3051                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3052                         rctl |= E1000_RCTL_PMCF;
3053                 else
3054                         rctl &= ~E1000_RCTL_PMCF;
3055
3056                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3057                 E1000_WRITE_FLUSH(hw);
3058
3059                 return 0;
3060         }
3061
3062         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3063         return -EIO;
3064 }
3065
3066 #define E1000_RAH_POOLSEL_SHIFT      (18)
3067 static int
3068 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3069                 uint32_t index, uint32_t pool)
3070 {
3071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3072         uint32_t rah;
3073
3074         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3075         rah = E1000_READ_REG(hw, E1000_RAH(index));
3076         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3077         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3078         return 0;
3079 }
3080
3081 static void
3082 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3083 {
3084         uint8_t addr[ETHER_ADDR_LEN];
3085         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086
3087         memset(addr, 0, sizeof(addr));
3088
3089         e1000_rar_set(hw, addr, index);
3090 }
3091
3092 static int
3093 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3094                                 struct ether_addr *addr)
3095 {
3096         eth_igb_rar_clear(dev, 0);
3097         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3098
3099         return 0;
3100 }
3101 /*
3102  * Virtual Function operations
3103  */
3104 static void
3105 igbvf_intr_disable(struct e1000_hw *hw)
3106 {
3107         PMD_INIT_FUNC_TRACE();
3108
3109         /* Clear interrupt mask to stop from interrupts being generated */
3110         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3111
3112         E1000_WRITE_FLUSH(hw);
3113 }
3114
3115 static void
3116 igbvf_stop_adapter(struct rte_eth_dev *dev)
3117 {
3118         u32 reg_val;
3119         u16 i;
3120         struct rte_eth_dev_info dev_info;
3121         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122
3123         memset(&dev_info, 0, sizeof(dev_info));
3124         eth_igbvf_infos_get(dev, &dev_info);
3125
3126         /* Clear interrupt mask to stop from interrupts being generated */
3127         igbvf_intr_disable(hw);
3128
3129         /* Clear any pending interrupts, flush previous writes */
3130         E1000_READ_REG(hw, E1000_EICR);
3131
3132         /* Disable the transmit unit.  Each queue must be disabled. */
3133         for (i = 0; i < dev_info.max_tx_queues; i++)
3134                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3135
3136         /* Disable the receive unit by stopping each queue */
3137         for (i = 0; i < dev_info.max_rx_queues; i++) {
3138                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3139                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3140                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3141                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3142                         ;
3143         }
3144
3145         /* flush all queues disables */
3146         E1000_WRITE_FLUSH(hw);
3147         msec_delay(2);
3148 }
3149
3150 static int eth_igbvf_link_update(struct e1000_hw *hw)
3151 {
3152         struct e1000_mbx_info *mbx = &hw->mbx;
3153         struct e1000_mac_info *mac = &hw->mac;
3154         int ret_val = E1000_SUCCESS;
3155
3156         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3157
3158         /*
3159          * We only want to run this if there has been a rst asserted.
3160          * in this case that could mean a link change, device reset,
3161          * or a virtual function reset
3162          */
3163
3164         /* If we were hit with a reset or timeout drop the link */
3165         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3166                 mac->get_link_status = TRUE;
3167
3168         if (!mac->get_link_status)
3169                 goto out;
3170
3171         /* if link status is down no point in checking to see if pf is up */
3172         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3173                 goto out;
3174
3175         /* if we passed all the tests above then the link is up and we no
3176          * longer need to check for link */
3177         mac->get_link_status = FALSE;
3178
3179 out:
3180         return ret_val;
3181 }
3182
3183
3184 static int
3185 igbvf_dev_configure(struct rte_eth_dev *dev)
3186 {
3187         struct rte_eth_conf* conf = &dev->data->dev_conf;
3188
3189         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3190                      dev->data->port_id);
3191
3192         /*
3193          * VF has no ability to enable/disable HW CRC
3194          * Keep the persistent behavior the same as Host PF
3195          */
3196 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3197         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3198                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3199                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3200         }
3201 #else
3202         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3203                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3204                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3205         }
3206 #endif
3207
3208         return 0;
3209 }
3210
3211 static int
3212 igbvf_dev_start(struct rte_eth_dev *dev)
3213 {
3214         struct e1000_hw *hw =
3215                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3216         struct e1000_adapter *adapter =
3217                 E1000_DEV_PRIVATE(dev->data->dev_private);
3218         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3219         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3220         int ret;
3221         uint32_t intr_vector = 0;
3222
3223         PMD_INIT_FUNC_TRACE();
3224
3225         hw->mac.ops.reset_hw(hw);
3226         adapter->stopped = 0;
3227
3228         /* Set all vfta */
3229         igbvf_set_vfta_all(dev,1);
3230
3231         eth_igbvf_tx_init(dev);
3232
3233         /* This can fail when allocating mbufs for descriptor rings */
3234         ret = eth_igbvf_rx_init(dev);
3235         if (ret) {
3236                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3237                 igb_dev_clear_queues(dev);
3238                 return ret;
3239         }
3240
3241         /* check and configure queue intr-vector mapping */
3242         if (rte_intr_cap_multiple(intr_handle) &&
3243             dev->data->dev_conf.intr_conf.rxq) {
3244                 intr_vector = dev->data->nb_rx_queues;
3245                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3246                 if (ret)
3247                         return ret;
3248         }
3249
3250         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3251                 intr_handle->intr_vec =
3252                         rte_zmalloc("intr_vec",
3253                                     dev->data->nb_rx_queues * sizeof(int), 0);
3254                 if (!intr_handle->intr_vec) {
3255                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3256                                      " intr_vec", dev->data->nb_rx_queues);
3257                         return -ENOMEM;
3258                 }
3259         }
3260
3261         eth_igbvf_configure_msix_intr(dev);
3262
3263         /* enable uio/vfio intr/eventfd mapping */
3264         rte_intr_enable(intr_handle);
3265
3266         /* resume enabled intr since hw reset */
3267         igbvf_intr_enable(dev);
3268
3269         return 0;
3270 }
3271
3272 static void
3273 igbvf_dev_stop(struct rte_eth_dev *dev)
3274 {
3275         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3276         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3277
3278         PMD_INIT_FUNC_TRACE();
3279
3280         igbvf_stop_adapter(dev);
3281
3282         /*
3283           * Clear what we set, but we still keep shadow_vfta to
3284           * restore after device starts
3285           */
3286         igbvf_set_vfta_all(dev,0);
3287
3288         igb_dev_clear_queues(dev);
3289
3290         /* disable intr eventfd mapping */
3291         rte_intr_disable(intr_handle);
3292
3293         /* Clean datapath event and queue/vec mapping */
3294         rte_intr_efd_disable(intr_handle);
3295         if (intr_handle->intr_vec) {
3296                 rte_free(intr_handle->intr_vec);
3297                 intr_handle->intr_vec = NULL;
3298         }
3299 }
3300
3301 static void
3302 igbvf_dev_close(struct rte_eth_dev *dev)
3303 {
3304         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305         struct e1000_adapter *adapter =
3306                 E1000_DEV_PRIVATE(dev->data->dev_private);
3307         struct ether_addr addr;
3308
3309         PMD_INIT_FUNC_TRACE();
3310
3311         e1000_reset_hw(hw);
3312
3313         igbvf_dev_stop(dev);
3314         adapter->stopped = 1;
3315         igb_dev_free_queues(dev);
3316
3317         /**
3318          * reprogram the RAR with a zero mac address,
3319          * to ensure that the VF traffic goes to the PF
3320          * after stop, close and detach of the VF.
3321          **/
3322
3323         memset(&addr, 0, sizeof(addr));
3324         igbvf_default_mac_addr_set(dev, &addr);
3325 }
3326
3327 static void
3328 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3329 {
3330         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3331
3332         /* Set both unicast and multicast promisc */
3333         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3334 }
3335
3336 static void
3337 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3338 {
3339         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340
3341         /* If in allmulticast mode leave multicast promisc */
3342         if (dev->data->all_multicast == 1)
3343                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3344         else
3345                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3346 }
3347
3348 static void
3349 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3350 {
3351         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3352
3353         /* In promiscuous mode multicast promisc already set */
3354         if (dev->data->promiscuous == 0)
3355                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3356 }
3357
3358 static void
3359 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3360 {
3361         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362
3363         /* In promiscuous mode leave multicast promisc enabled */
3364         if (dev->data->promiscuous == 0)
3365                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3366 }
3367
3368 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3369 {
3370         struct e1000_mbx_info *mbx = &hw->mbx;
3371         uint32_t msgbuf[2];
3372         s32 err;
3373
3374         /* After set vlan, vlan strip will also be enabled in igb driver*/
3375         msgbuf[0] = E1000_VF_SET_VLAN;
3376         msgbuf[1] = vid;
3377         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3378         if (on)
3379                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3380
3381         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3382         if (err)
3383                 goto mbx_err;
3384
3385         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3386         if (err)
3387                 goto mbx_err;
3388
3389         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3390         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3391                 err = -EINVAL;
3392
3393 mbx_err:
3394         return err;
3395 }
3396
3397 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3398 {
3399         struct e1000_hw *hw =
3400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401         struct e1000_vfta * shadow_vfta =
3402                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3403         int i = 0, j = 0, vfta = 0, mask = 1;
3404
3405         for (i = 0; i < IGB_VFTA_SIZE; i++){
3406                 vfta = shadow_vfta->vfta[i];
3407                 if(vfta){
3408                         mask = 1;
3409                         for (j = 0; j < 32; j++){
3410                                 if(vfta & mask)
3411                                         igbvf_set_vfta(hw,
3412                                                 (uint16_t)((i<<5)+j), on);
3413                                 mask<<=1;
3414                         }
3415                 }
3416         }
3417
3418 }
3419
3420 static int
3421 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3422 {
3423         struct e1000_hw *hw =
3424                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425         struct e1000_vfta * shadow_vfta =
3426                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3427         uint32_t vid_idx = 0;
3428         uint32_t vid_bit = 0;
3429         int ret = 0;
3430
3431         PMD_INIT_FUNC_TRACE();
3432
3433         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3434         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3435         if(ret){
3436                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3437                 return ret;
3438         }
3439         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3440         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3441
3442         /*Save what we set and retore it after device reset*/
3443         if (on)
3444                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3445         else
3446                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3447
3448         return 0;
3449 }
3450
3451 static int
3452 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3453 {
3454         struct e1000_hw *hw =
3455                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456
3457         /* index is not used by rar_set() */
3458         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3459         return 0;
3460 }
3461
3462
3463 static int
3464 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3465                         struct rte_eth_rss_reta_entry64 *reta_conf,
3466                         uint16_t reta_size)
3467 {
3468         uint8_t i, j, mask;
3469         uint32_t reta, r;
3470         uint16_t idx, shift;
3471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472
3473         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3474                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3475                         "(%d) doesn't match the number hardware can supported "
3476                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3477                 return -EINVAL;
3478         }
3479
3480         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3481                 idx = i / RTE_RETA_GROUP_SIZE;
3482                 shift = i % RTE_RETA_GROUP_SIZE;
3483                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3484                                                 IGB_4_BIT_MASK);
3485                 if (!mask)
3486                         continue;
3487                 if (mask == IGB_4_BIT_MASK)
3488                         r = 0;
3489                 else
3490                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3491                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3492                         if (mask & (0x1 << j))
3493                                 reta |= reta_conf[idx].reta[shift + j] <<
3494                                                         (CHAR_BIT * j);
3495                         else
3496                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3497                 }
3498                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3499         }
3500
3501         return 0;
3502 }
3503
3504 static int
3505 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3506                        struct rte_eth_rss_reta_entry64 *reta_conf,
3507                        uint16_t reta_size)
3508 {
3509         uint8_t i, j, mask;
3510         uint32_t reta;
3511         uint16_t idx, shift;
3512         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513
3514         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3515                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3516                         "(%d) doesn't match the number hardware can supported "
3517                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3518                 return -EINVAL;
3519         }
3520
3521         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3522                 idx = i / RTE_RETA_GROUP_SIZE;
3523                 shift = i % RTE_RETA_GROUP_SIZE;
3524                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3525                                                 IGB_4_BIT_MASK);
3526                 if (!mask)
3527                         continue;
3528                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3529                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3530                         if (mask & (0x1 << j))
3531                                 reta_conf[idx].reta[shift + j] =
3532                                         ((reta >> (CHAR_BIT * j)) &
3533                                                 IGB_8_BIT_MASK);
3534                 }
3535         }
3536
3537         return 0;
3538 }
3539
3540 int
3541 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3542                         struct rte_eth_syn_filter *filter,
3543                         bool add)
3544 {
3545         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3546         struct e1000_filter_info *filter_info =
3547                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3548         uint32_t synqf, rfctl;
3549
3550         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3551                 return -EINVAL;
3552
3553         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3554
3555         if (add) {
3556                 if (synqf & E1000_SYN_FILTER_ENABLE)
3557                         return -EINVAL;
3558
3559                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3560                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3561
3562                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3563                 if (filter->hig_pri)
3564                         rfctl |= E1000_RFCTL_SYNQFP;
3565                 else
3566                         rfctl &= ~E1000_RFCTL_SYNQFP;
3567
3568                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3569         } else {
3570                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3571                         return -ENOENT;
3572                 synqf = 0;
3573         }
3574
3575         filter_info->syn_info = synqf;
3576         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3577         E1000_WRITE_FLUSH(hw);
3578         return 0;
3579 }
3580
3581 static int
3582 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3583                         struct rte_eth_syn_filter *filter)
3584 {
3585         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586         uint32_t synqf, rfctl;
3587
3588         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3589         if (synqf & E1000_SYN_FILTER_ENABLE) {
3590                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3591                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3592                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3593                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3594                 return 0;
3595         }
3596
3597         return -ENOENT;
3598 }
3599
3600 static int
3601 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3602                         enum rte_filter_op filter_op,
3603                         void *arg)
3604 {
3605         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3606         int ret;
3607
3608         MAC_TYPE_FILTER_SUP(hw->mac.type);
3609
3610         if (filter_op == RTE_ETH_FILTER_NOP)
3611                 return 0;
3612
3613         if (arg == NULL) {
3614                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3615                             filter_op);
3616                 return -EINVAL;
3617         }
3618
3619         switch (filter_op) {
3620         case RTE_ETH_FILTER_ADD:
3621                 ret = eth_igb_syn_filter_set(dev,
3622                                 (struct rte_eth_syn_filter *)arg,
3623                                 TRUE);
3624                 break;
3625         case RTE_ETH_FILTER_DELETE:
3626                 ret = eth_igb_syn_filter_set(dev,
3627                                 (struct rte_eth_syn_filter *)arg,
3628                                 FALSE);
3629                 break;
3630         case RTE_ETH_FILTER_GET:
3631                 ret = eth_igb_syn_filter_get(dev,
3632                                 (struct rte_eth_syn_filter *)arg);
3633                 break;
3634         default:
3635                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3636                 ret = -EINVAL;
3637                 break;
3638         }
3639
3640         return ret;
3641 }
3642
3643 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3644 static inline int
3645 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3646                         struct e1000_2tuple_filter_info *filter_info)
3647 {
3648         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3649                 return -EINVAL;
3650         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3651                 return -EINVAL;  /* filter index is out of range. */
3652         if (filter->tcp_flags > TCP_FLAG_ALL)
3653                 return -EINVAL;  /* flags is invalid. */
3654
3655         switch (filter->dst_port_mask) {
3656         case UINT16_MAX:
3657                 filter_info->dst_port_mask = 0;
3658                 filter_info->dst_port = filter->dst_port;
3659                 break;
3660         case 0:
3661                 filter_info->dst_port_mask = 1;
3662                 break;
3663         default:
3664                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3665                 return -EINVAL;
3666         }
3667
3668         switch (filter->proto_mask) {
3669         case UINT8_MAX:
3670                 filter_info->proto_mask = 0;
3671                 filter_info->proto = filter->proto;
3672                 break;
3673         case 0:
3674                 filter_info->proto_mask = 1;
3675                 break;
3676         default:
3677                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3678                 return -EINVAL;
3679         }
3680
3681         filter_info->priority = (uint8_t)filter->priority;
3682         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3683                 filter_info->tcp_flags = filter->tcp_flags;
3684         else
3685                 filter_info->tcp_flags = 0;
3686
3687         return 0;
3688 }
3689
3690 static inline struct e1000_2tuple_filter *
3691 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3692                         struct e1000_2tuple_filter_info *key)
3693 {
3694         struct e1000_2tuple_filter *it;
3695
3696         TAILQ_FOREACH(it, filter_list, entries) {
3697                 if (memcmp(key, &it->filter_info,
3698                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3699                         return it;
3700                 }
3701         }
3702         return NULL;
3703 }
3704
3705 /* inject a igb 2tuple filter to HW */
3706 static inline void
3707 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3708                            struct e1000_2tuple_filter *filter)
3709 {
3710         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3712         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3713         int i;
3714
3715         i = filter->index;
3716         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3717         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3718                 imir |= E1000_IMIR_PORT_BP;
3719         else
3720                 imir &= ~E1000_IMIR_PORT_BP;
3721
3722         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3723
3724         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3725         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3726         ttqf |= (uint32_t)(filter->filter_info.proto &
3727                                                 E1000_TTQF_PROTOCOL_MASK);
3728         if (filter->filter_info.proto_mask == 0)
3729                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3730
3731         /* tcp flags bits setting. */
3732         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3733                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3734                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3735                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3736                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3737                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3738                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3739                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3740                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3741                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3742                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3743                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3744                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3745         } else {
3746                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3747         }
3748         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3749         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3750         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3751 }
3752
3753 /*
3754  * igb_add_2tuple_filter - add a 2tuple filter
3755  *
3756  * @param
3757  * dev: Pointer to struct rte_eth_dev.
3758  * ntuple_filter: ponter to the filter that will be added.
3759  *
3760  * @return
3761  *    - On success, zero.
3762  *    - On failure, a negative value.
3763  */
3764 static int
3765 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3766                         struct rte_eth_ntuple_filter *ntuple_filter)
3767 {
3768         struct e1000_filter_info *filter_info =
3769                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3770         struct e1000_2tuple_filter *filter;
3771         int i, ret;
3772
3773         filter = rte_zmalloc("e1000_2tuple_filter",
3774                         sizeof(struct e1000_2tuple_filter), 0);
3775         if (filter == NULL)
3776                 return -ENOMEM;
3777
3778         ret = ntuple_filter_to_2tuple(ntuple_filter,
3779                                       &filter->filter_info);
3780         if (ret < 0) {
3781                 rte_free(filter);
3782                 return ret;
3783         }
3784         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3785                                          &filter->filter_info) != NULL) {
3786                 PMD_DRV_LOG(ERR, "filter exists.");
3787                 rte_free(filter);
3788                 return -EEXIST;
3789         }
3790         filter->queue = ntuple_filter->queue;
3791
3792         /*
3793          * look for an unused 2tuple filter index,
3794          * and insert the filter to list.
3795          */
3796         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3797                 if (!(filter_info->twotuple_mask & (1 << i))) {
3798                         filter_info->twotuple_mask |= 1 << i;
3799                         filter->index = i;
3800                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3801                                           filter,
3802                                           entries);
3803                         break;
3804                 }
3805         }
3806         if (i >= E1000_MAX_TTQF_FILTERS) {
3807                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3808                 rte_free(filter);
3809                 return -ENOSYS;
3810         }
3811
3812         igb_inject_2uple_filter(dev, filter);
3813         return 0;
3814 }
3815
3816 int
3817 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3818                         struct e1000_2tuple_filter *filter)
3819 {
3820         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821         struct e1000_filter_info *filter_info =
3822                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3823
3824         filter_info->twotuple_mask &= ~(1 << filter->index);
3825         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3826         rte_free(filter);
3827
3828         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3829         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3830         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3831         return 0;
3832 }
3833
3834 /*
3835  * igb_remove_2tuple_filter - remove a 2tuple filter
3836  *
3837  * @param
3838  * dev: Pointer to struct rte_eth_dev.
3839  * ntuple_filter: ponter to the filter that will be removed.
3840  *
3841  * @return
3842  *    - On success, zero.
3843  *    - On failure, a negative value.
3844  */
3845 static int
3846 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3847                         struct rte_eth_ntuple_filter *ntuple_filter)
3848 {
3849         struct e1000_filter_info *filter_info =
3850                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3851         struct e1000_2tuple_filter_info filter_2tuple;
3852         struct e1000_2tuple_filter *filter;
3853         int ret;
3854
3855         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3856         ret = ntuple_filter_to_2tuple(ntuple_filter,
3857                                       &filter_2tuple);
3858         if (ret < 0)
3859                 return ret;
3860
3861         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3862                                          &filter_2tuple);
3863         if (filter == NULL) {
3864                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3865                 return -ENOENT;
3866         }
3867
3868         igb_delete_2tuple_filter(dev, filter);
3869
3870         return 0;
3871 }
3872
3873 /* inject a igb flex filter to HW */
3874 static inline void
3875 igb_inject_flex_filter(struct rte_eth_dev *dev,
3876                            struct e1000_flex_filter *filter)
3877 {
3878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         uint32_t wufc, queueing;
3880         uint32_t reg_off;
3881         uint8_t i, j = 0;
3882
3883         wufc = E1000_READ_REG(hw, E1000_WUFC);
3884         if (filter->index < E1000_MAX_FHFT)
3885                 reg_off = E1000_FHFT(filter->index);
3886         else
3887                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3888
3889         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3890                         (E1000_WUFC_FLX0 << filter->index));
3891         queueing = filter->filter_info.len |
3892                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3893                 (filter->filter_info.priority <<
3894                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3895         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3896                         queueing);
3897
3898         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3899                 E1000_WRITE_REG(hw, reg_off,
3900                                 filter->filter_info.dwords[j]);
3901                 reg_off += sizeof(uint32_t);
3902                 E1000_WRITE_REG(hw, reg_off,
3903                                 filter->filter_info.dwords[++j]);
3904                 reg_off += sizeof(uint32_t);
3905                 E1000_WRITE_REG(hw, reg_off,
3906                         (uint32_t)filter->filter_info.mask[i]);
3907                 reg_off += sizeof(uint32_t) * 2;
3908                 ++j;
3909         }
3910 }
3911
3912 static inline struct e1000_flex_filter *
3913 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3914                         struct e1000_flex_filter_info *key)
3915 {
3916         struct e1000_flex_filter *it;
3917
3918         TAILQ_FOREACH(it, filter_list, entries) {
3919                 if (memcmp(key, &it->filter_info,
3920                         sizeof(struct e1000_flex_filter_info)) == 0)
3921                         return it;
3922         }
3923
3924         return NULL;
3925 }
3926
3927 /* remove a flex byte filter
3928  * @param
3929  * dev: Pointer to struct rte_eth_dev.
3930  * filter: the pointer of the filter will be removed.
3931  */
3932 void
3933 igb_remove_flex_filter(struct rte_eth_dev *dev,
3934                         struct e1000_flex_filter *filter)
3935 {
3936         struct e1000_filter_info *filter_info =
3937                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939         uint32_t wufc, i;
3940         uint32_t reg_off;
3941
3942         wufc = E1000_READ_REG(hw, E1000_WUFC);
3943         if (filter->index < E1000_MAX_FHFT)
3944                 reg_off = E1000_FHFT(filter->index);
3945         else
3946                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3947
3948         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3949                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3950
3951         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3952                 (~(E1000_WUFC_FLX0 << filter->index)));
3953
3954         filter_info->flex_mask &= ~(1 << filter->index);
3955         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3956         rte_free(filter);
3957 }
3958
3959 int
3960 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3961                         struct rte_eth_flex_filter *filter,
3962                         bool add)
3963 {
3964         struct e1000_filter_info *filter_info =
3965                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3966         struct e1000_flex_filter *flex_filter, *it;
3967         uint32_t mask;
3968         uint8_t shift, i;
3969
3970         flex_filter = rte_zmalloc("e1000_flex_filter",
3971                         sizeof(struct e1000_flex_filter), 0);
3972         if (flex_filter == NULL)
3973                 return -ENOMEM;
3974
3975         flex_filter->filter_info.len = filter->len;
3976         flex_filter->filter_info.priority = filter->priority;
3977         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3978         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3979                 mask = 0;
3980                 /* reverse bits in flex filter's mask*/
3981                 for (shift = 0; shift < CHAR_BIT; shift++) {
3982                         if (filter->mask[i] & (0x01 << shift))
3983                                 mask |= (0x80 >> shift);
3984                 }
3985                 flex_filter->filter_info.mask[i] = mask;
3986         }
3987
3988         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3989                                 &flex_filter->filter_info);
3990         if (it == NULL && !add) {
3991                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3992                 rte_free(flex_filter);
3993                 return -ENOENT;
3994         }
3995         if (it != NULL && add) {
3996                 PMD_DRV_LOG(ERR, "filter exists.");
3997                 rte_free(flex_filter);
3998                 return -EEXIST;
3999         }
4000
4001         if (add) {
4002                 flex_filter->queue = filter->queue;
4003                 /*
4004                  * look for an unused flex filter index
4005                  * and insert the filter into the list.
4006                  */
4007                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4008                         if (!(filter_info->flex_mask & (1 << i))) {
4009                                 filter_info->flex_mask |= 1 << i;
4010                                 flex_filter->index = i;
4011                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4012                                         flex_filter,
4013                                         entries);
4014                                 break;
4015                         }
4016                 }
4017                 if (i >= E1000_MAX_FLEX_FILTERS) {
4018                         PMD_DRV_LOG(ERR, "flex filters are full.");
4019                         rte_free(flex_filter);
4020                         return -ENOSYS;
4021                 }
4022
4023                 igb_inject_flex_filter(dev, flex_filter);
4024
4025         } else {
4026                 igb_remove_flex_filter(dev, it);
4027                 rte_free(flex_filter);
4028         }
4029
4030         return 0;
4031 }
4032
4033 static int
4034 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4035                         struct rte_eth_flex_filter *filter)
4036 {
4037         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038         struct e1000_filter_info *filter_info =
4039                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4040         struct e1000_flex_filter flex_filter, *it;
4041         uint32_t wufc, queueing, wufc_en = 0;
4042
4043         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4044         flex_filter.filter_info.len = filter->len;
4045         flex_filter.filter_info.priority = filter->priority;
4046         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4047         memcpy(flex_filter.filter_info.mask, filter->mask,
4048                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4049
4050         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4051                                 &flex_filter.filter_info);
4052         if (it == NULL) {
4053                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4054                 return -ENOENT;
4055         }
4056
4057         wufc = E1000_READ_REG(hw, E1000_WUFC);
4058         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4059
4060         if ((wufc & wufc_en) == wufc_en) {
4061                 uint32_t reg_off = 0;
4062                 if (it->index < E1000_MAX_FHFT)
4063                         reg_off = E1000_FHFT(it->index);
4064                 else
4065                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4066
4067                 queueing = E1000_READ_REG(hw,
4068                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4069                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4070                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4071                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4072                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4073                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4074                 return 0;
4075         }
4076         return -ENOENT;
4077 }
4078
4079 static int
4080 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4081                         enum rte_filter_op filter_op,
4082                         void *arg)
4083 {
4084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         struct rte_eth_flex_filter *filter;
4086         int ret = 0;
4087
4088         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4089
4090         if (filter_op == RTE_ETH_FILTER_NOP)
4091                 return ret;
4092
4093         if (arg == NULL) {
4094                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4095                             filter_op);
4096                 return -EINVAL;
4097         }
4098
4099         filter = (struct rte_eth_flex_filter *)arg;
4100         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4101             || filter->len % sizeof(uint64_t) != 0) {
4102                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4103                 return -EINVAL;
4104         }
4105         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4106                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4107                 return -EINVAL;
4108         }
4109
4110         switch (filter_op) {
4111         case RTE_ETH_FILTER_ADD:
4112                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4113                 break;
4114         case RTE_ETH_FILTER_DELETE:
4115                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4116                 break;
4117         case RTE_ETH_FILTER_GET:
4118                 ret = eth_igb_get_flex_filter(dev, filter);
4119                 break;
4120         default:
4121                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4122                 ret = -EINVAL;
4123                 break;
4124         }
4125
4126         return ret;
4127 }
4128
4129 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4130 static inline int
4131 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4132                         struct e1000_5tuple_filter_info *filter_info)
4133 {
4134         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4135                 return -EINVAL;
4136         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4137                 return -EINVAL;  /* filter index is out of range. */
4138         if (filter->tcp_flags > TCP_FLAG_ALL)
4139                 return -EINVAL;  /* flags is invalid. */
4140
4141         switch (filter->dst_ip_mask) {
4142         case UINT32_MAX:
4143                 filter_info->dst_ip_mask = 0;
4144                 filter_info->dst_ip = filter->dst_ip;
4145                 break;
4146         case 0:
4147                 filter_info->dst_ip_mask = 1;
4148                 break;
4149         default:
4150                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4151                 return -EINVAL;
4152         }
4153
4154         switch (filter->src_ip_mask) {
4155         case UINT32_MAX:
4156                 filter_info->src_ip_mask = 0;
4157                 filter_info->src_ip = filter->src_ip;
4158                 break;
4159         case 0:
4160                 filter_info->src_ip_mask = 1;
4161                 break;
4162         default:
4163                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4164                 return -EINVAL;
4165         }
4166
4167         switch (filter->dst_port_mask) {
4168         case UINT16_MAX:
4169                 filter_info->dst_port_mask = 0;
4170                 filter_info->dst_port = filter->dst_port;
4171                 break;
4172         case 0:
4173                 filter_info->dst_port_mask = 1;
4174                 break;
4175         default:
4176                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4177                 return -EINVAL;
4178         }
4179
4180         switch (filter->src_port_mask) {
4181         case UINT16_MAX:
4182                 filter_info->src_port_mask = 0;
4183                 filter_info->src_port = filter->src_port;
4184                 break;
4185         case 0:
4186                 filter_info->src_port_mask = 1;
4187                 break;
4188         default:
4189                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4190                 return -EINVAL;
4191         }
4192
4193         switch (filter->proto_mask) {
4194         case UINT8_MAX:
4195                 filter_info->proto_mask = 0;
4196                 filter_info->proto = filter->proto;
4197                 break;
4198         case 0:
4199                 filter_info->proto_mask = 1;
4200                 break;
4201         default:
4202                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4203                 return -EINVAL;
4204         }
4205
4206         filter_info->priority = (uint8_t)filter->priority;
4207         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4208                 filter_info->tcp_flags = filter->tcp_flags;
4209         else
4210                 filter_info->tcp_flags = 0;
4211
4212         return 0;
4213 }
4214
4215 static inline struct e1000_5tuple_filter *
4216 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4217                         struct e1000_5tuple_filter_info *key)
4218 {
4219         struct e1000_5tuple_filter *it;
4220
4221         TAILQ_FOREACH(it, filter_list, entries) {
4222                 if (memcmp(key, &it->filter_info,
4223                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4224                         return it;
4225                 }
4226         }
4227         return NULL;
4228 }
4229
4230 /* inject a igb 5-tuple filter to HW */
4231 static inline void
4232 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4233                            struct e1000_5tuple_filter *filter)
4234 {
4235         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4237         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4238         uint8_t i;
4239
4240         i = filter->index;
4241         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4242         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4243                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4244         if (filter->filter_info.dst_ip_mask == 0)
4245                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4246         if (filter->filter_info.src_port_mask == 0)
4247                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4248         if (filter->filter_info.proto_mask == 0)
4249                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4250         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4251                 E1000_FTQF_QUEUE_MASK;
4252         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4253         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4254         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4255         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4256
4257         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4258         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4259
4260         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4261         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4262                 imir |= E1000_IMIR_PORT_BP;
4263         else
4264                 imir &= ~E1000_IMIR_PORT_BP;
4265         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4266
4267         /* tcp flags bits setting. */
4268         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4269                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4270                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4271                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4272                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4273                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4274                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4275                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4276                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4277                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4278                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4279                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4280                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4281         } else {
4282                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4283         }
4284         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4285         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4286 }
4287
4288 /*
4289  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4290  *
4291  * @param
4292  * dev: Pointer to struct rte_eth_dev.
4293  * ntuple_filter: ponter to the filter that will be added.
4294  *
4295  * @return
4296  *    - On success, zero.
4297  *    - On failure, a negative value.
4298  */
4299 static int
4300 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4301                         struct rte_eth_ntuple_filter *ntuple_filter)
4302 {
4303         struct e1000_filter_info *filter_info =
4304                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4305         struct e1000_5tuple_filter *filter;
4306         uint8_t i;
4307         int ret;
4308
4309         filter = rte_zmalloc("e1000_5tuple_filter",
4310                         sizeof(struct e1000_5tuple_filter), 0);
4311         if (filter == NULL)
4312                 return -ENOMEM;
4313
4314         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4315                                             &filter->filter_info);
4316         if (ret < 0) {
4317                 rte_free(filter);
4318                 return ret;
4319         }
4320
4321         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4322                                          &filter->filter_info) != NULL) {
4323                 PMD_DRV_LOG(ERR, "filter exists.");
4324                 rte_free(filter);
4325                 return -EEXIST;
4326         }
4327         filter->queue = ntuple_filter->queue;
4328
4329         /*
4330          * look for an unused 5tuple filter index,
4331          * and insert the filter to list.
4332          */
4333         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4334                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4335                         filter_info->fivetuple_mask |= 1 << i;
4336                         filter->index = i;
4337                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4338                                           filter,
4339                                           entries);
4340                         break;
4341                 }
4342         }
4343         if (i >= E1000_MAX_FTQF_FILTERS) {
4344                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4345                 rte_free(filter);
4346                 return -ENOSYS;
4347         }
4348
4349         igb_inject_5tuple_filter_82576(dev, filter);
4350         return 0;
4351 }
4352
4353 int
4354 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4355                                 struct e1000_5tuple_filter *filter)
4356 {
4357         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         struct e1000_filter_info *filter_info =
4359                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4360
4361         filter_info->fivetuple_mask &= ~(1 << filter->index);
4362         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4363         rte_free(filter);
4364
4365         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4366                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4367         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4368         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4369         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4370         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4371         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4372         return 0;
4373 }
4374
4375 /*
4376  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4377  *
4378  * @param
4379  * dev: Pointer to struct rte_eth_dev.
4380  * ntuple_filter: ponter to the filter that will be removed.
4381  *
4382  * @return
4383  *    - On success, zero.
4384  *    - On failure, a negative value.
4385  */
4386 static int
4387 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4388                                 struct rte_eth_ntuple_filter *ntuple_filter)
4389 {
4390         struct e1000_filter_info *filter_info =
4391                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4392         struct e1000_5tuple_filter_info filter_5tuple;
4393         struct e1000_5tuple_filter *filter;
4394         int ret;
4395
4396         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4397         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4398                                             &filter_5tuple);
4399         if (ret < 0)
4400                 return ret;
4401
4402         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4403                                          &filter_5tuple);
4404         if (filter == NULL) {
4405                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4406                 return -ENOENT;
4407         }
4408
4409         igb_delete_5tuple_filter_82576(dev, filter);
4410
4411         return 0;
4412 }
4413
4414 static int
4415 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4416 {
4417         uint32_t rctl;
4418         struct e1000_hw *hw;
4419         struct rte_eth_dev_info dev_info;
4420         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4421                                      VLAN_TAG_SIZE);
4422
4423         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424
4425 #ifdef RTE_LIBRTE_82571_SUPPORT
4426         /* XXX: not bigger than max_rx_pktlen */
4427         if (hw->mac.type == e1000_82571)
4428                 return -ENOTSUP;
4429 #endif
4430         eth_igb_infos_get(dev, &dev_info);
4431
4432         /* check that mtu is within the allowed range */
4433         if ((mtu < ETHER_MIN_MTU) ||
4434             (frame_size > dev_info.max_rx_pktlen))
4435                 return -EINVAL;
4436
4437         /* refuse mtu that requires the support of scattered packets when this
4438          * feature has not been enabled before. */
4439         if (!dev->data->scattered_rx &&
4440             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4441                 return -EINVAL;
4442
4443         rctl = E1000_READ_REG(hw, E1000_RCTL);
4444
4445         /* switch to jumbo mode if needed */
4446         if (frame_size > ETHER_MAX_LEN) {
4447                 dev->data->dev_conf.rxmode.offloads |=
4448                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4449                 rctl |= E1000_RCTL_LPE;
4450         } else {
4451                 dev->data->dev_conf.rxmode.offloads &=
4452                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4453                 rctl &= ~E1000_RCTL_LPE;
4454         }
4455         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4456
4457         /* update max frame size */
4458         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4459
4460         E1000_WRITE_REG(hw, E1000_RLPML,
4461                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4462
4463         return 0;
4464 }
4465
4466 /*
4467  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4468  *
4469  * @param
4470  * dev: Pointer to struct rte_eth_dev.
4471  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4472  * add: if true, add filter, if false, remove filter
4473  *
4474  * @return
4475  *    - On success, zero.
4476  *    - On failure, a negative value.
4477  */
4478 int
4479 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4480                         struct rte_eth_ntuple_filter *ntuple_filter,
4481                         bool add)
4482 {
4483         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484         int ret;
4485
4486         switch (ntuple_filter->flags) {
4487         case RTE_5TUPLE_FLAGS:
4488         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4489                 if (hw->mac.type != e1000_82576)
4490                         return -ENOTSUP;
4491                 if (add)
4492                         ret = igb_add_5tuple_filter_82576(dev,
4493                                                           ntuple_filter);
4494                 else
4495                         ret = igb_remove_5tuple_filter_82576(dev,
4496                                                              ntuple_filter);
4497                 break;
4498         case RTE_2TUPLE_FLAGS:
4499         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4500                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4501                         hw->mac.type != e1000_i210 &&
4502                         hw->mac.type != e1000_i211)
4503                         return -ENOTSUP;
4504                 if (add)
4505                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4506                 else
4507                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4508                 break;
4509         default:
4510                 ret = -EINVAL;
4511                 break;
4512         }
4513
4514         return ret;
4515 }
4516
4517 /*
4518  * igb_get_ntuple_filter - get a ntuple filter
4519  *
4520  * @param
4521  * dev: Pointer to struct rte_eth_dev.
4522  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4523  *
4524  * @return
4525  *    - On success, zero.
4526  *    - On failure, a negative value.
4527  */
4528 static int
4529 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4530                         struct rte_eth_ntuple_filter *ntuple_filter)
4531 {
4532         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4533         struct e1000_filter_info *filter_info =
4534                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4535         struct e1000_5tuple_filter_info filter_5tuple;
4536         struct e1000_2tuple_filter_info filter_2tuple;
4537         struct e1000_5tuple_filter *p_5tuple_filter;
4538         struct e1000_2tuple_filter *p_2tuple_filter;
4539         int ret;
4540
4541         switch (ntuple_filter->flags) {
4542         case RTE_5TUPLE_FLAGS:
4543         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4544                 if (hw->mac.type != e1000_82576)
4545                         return -ENOTSUP;
4546                 memset(&filter_5tuple,
4547                         0,
4548                         sizeof(struct e1000_5tuple_filter_info));
4549                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4550                                                     &filter_5tuple);
4551                 if (ret < 0)
4552                         return ret;
4553                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4554                                         &filter_info->fivetuple_list,
4555                                         &filter_5tuple);
4556                 if (p_5tuple_filter == NULL) {
4557                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4558                         return -ENOENT;
4559                 }
4560                 ntuple_filter->queue = p_5tuple_filter->queue;
4561                 break;
4562         case RTE_2TUPLE_FLAGS:
4563         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4564                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4565                         return -ENOTSUP;
4566                 memset(&filter_2tuple,
4567                         0,
4568                         sizeof(struct e1000_2tuple_filter_info));
4569                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4570                 if (ret < 0)
4571                         return ret;
4572                 p_2tuple_filter = igb_2tuple_filter_lookup(
4573                                         &filter_info->twotuple_list,
4574                                         &filter_2tuple);
4575                 if (p_2tuple_filter == NULL) {
4576                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4577                         return -ENOENT;
4578                 }
4579                 ntuple_filter->queue = p_2tuple_filter->queue;
4580                 break;
4581         default:
4582                 ret = -EINVAL;
4583                 break;
4584         }
4585
4586         return 0;
4587 }
4588
4589 /*
4590  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4591  * @dev: pointer to rte_eth_dev structure
4592  * @filter_op:operation will be taken.
4593  * @arg: a pointer to specific structure corresponding to the filter_op
4594  */
4595 static int
4596 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4597                                 enum rte_filter_op filter_op,
4598                                 void *arg)
4599 {
4600         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601         int ret;
4602
4603         MAC_TYPE_FILTER_SUP(hw->mac.type);
4604
4605         if (filter_op == RTE_ETH_FILTER_NOP)
4606                 return 0;
4607
4608         if (arg == NULL) {
4609                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4610                             filter_op);
4611                 return -EINVAL;
4612         }
4613
4614         switch (filter_op) {
4615         case RTE_ETH_FILTER_ADD:
4616                 ret = igb_add_del_ntuple_filter(dev,
4617                         (struct rte_eth_ntuple_filter *)arg,
4618                         TRUE);
4619                 break;
4620         case RTE_ETH_FILTER_DELETE:
4621                 ret = igb_add_del_ntuple_filter(dev,
4622                         (struct rte_eth_ntuple_filter *)arg,
4623                         FALSE);
4624                 break;
4625         case RTE_ETH_FILTER_GET:
4626                 ret = igb_get_ntuple_filter(dev,
4627                         (struct rte_eth_ntuple_filter *)arg);
4628                 break;
4629         default:
4630                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4631                 ret = -EINVAL;
4632                 break;
4633         }
4634         return ret;
4635 }
4636
4637 static inline int
4638 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4639                         uint16_t ethertype)
4640 {
4641         int i;
4642
4643         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4644                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4645                     (filter_info->ethertype_mask & (1 << i)))
4646                         return i;
4647         }
4648         return -1;
4649 }
4650
4651 static inline int
4652 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4653                         uint16_t ethertype, uint32_t etqf)
4654 {
4655         int i;
4656
4657         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4658                 if (!(filter_info->ethertype_mask & (1 << i))) {
4659                         filter_info->ethertype_mask |= 1 << i;
4660                         filter_info->ethertype_filters[i].ethertype = ethertype;
4661                         filter_info->ethertype_filters[i].etqf = etqf;
4662                         return i;
4663                 }
4664         }
4665         return -1;
4666 }
4667
4668 int
4669 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4670                         uint8_t idx)
4671 {
4672         if (idx >= E1000_MAX_ETQF_FILTERS)
4673                 return -1;
4674         filter_info->ethertype_mask &= ~(1 << idx);
4675         filter_info->ethertype_filters[idx].ethertype = 0;
4676         filter_info->ethertype_filters[idx].etqf = 0;
4677         return idx;
4678 }
4679
4680
4681 int
4682 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4683                         struct rte_eth_ethertype_filter *filter,
4684                         bool add)
4685 {
4686         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4687         struct e1000_filter_info *filter_info =
4688                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4689         uint32_t etqf = 0;
4690         int ret;
4691
4692         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4693                 filter->ether_type == ETHER_TYPE_IPv6) {
4694                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4695                         " ethertype filter.", filter->ether_type);
4696                 return -EINVAL;
4697         }
4698
4699         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4700                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4701                 return -EINVAL;
4702         }
4703         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4704                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4705                 return -EINVAL;
4706         }
4707
4708         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4709         if (ret >= 0 && add) {
4710                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4711                             filter->ether_type);
4712                 return -EEXIST;
4713         }
4714         if (ret < 0 && !add) {
4715                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4716                             filter->ether_type);
4717                 return -ENOENT;
4718         }
4719
4720         if (add) {
4721                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4722                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4723                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4724                 ret = igb_ethertype_filter_insert(filter_info,
4725                                 filter->ether_type, etqf);
4726                 if (ret < 0) {
4727                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4728                         return -ENOSYS;
4729                 }
4730         } else {
4731                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4732                 if (ret < 0)
4733                         return -ENOSYS;
4734         }
4735         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4736         E1000_WRITE_FLUSH(hw);
4737
4738         return 0;
4739 }
4740
4741 static int
4742 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4743                         struct rte_eth_ethertype_filter *filter)
4744 {
4745         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746         struct e1000_filter_info *filter_info =
4747                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4748         uint32_t etqf;
4749         int ret;
4750
4751         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4752         if (ret < 0) {
4753                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4754                             filter->ether_type);
4755                 return -ENOENT;
4756         }
4757
4758         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4759         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4760                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4761                 filter->flags = 0;
4762                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4763                                 E1000_ETQF_QUEUE_SHIFT;
4764                 return 0;
4765         }
4766
4767         return -ENOENT;
4768 }
4769
4770 /*
4771  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4772  * @dev: pointer to rte_eth_dev structure
4773  * @filter_op:operation will be taken.
4774  * @arg: a pointer to specific structure corresponding to the filter_op
4775  */
4776 static int
4777 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4778                                 enum rte_filter_op filter_op,
4779                                 void *arg)
4780 {
4781         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4782         int ret;
4783
4784         MAC_TYPE_FILTER_SUP(hw->mac.type);
4785
4786         if (filter_op == RTE_ETH_FILTER_NOP)
4787                 return 0;
4788
4789         if (arg == NULL) {
4790                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4791                             filter_op);
4792                 return -EINVAL;
4793         }
4794
4795         switch (filter_op) {
4796         case RTE_ETH_FILTER_ADD:
4797                 ret = igb_add_del_ethertype_filter(dev,
4798                         (struct rte_eth_ethertype_filter *)arg,
4799                         TRUE);
4800                 break;
4801         case RTE_ETH_FILTER_DELETE:
4802                 ret = igb_add_del_ethertype_filter(dev,
4803                         (struct rte_eth_ethertype_filter *)arg,
4804                         FALSE);
4805                 break;
4806         case RTE_ETH_FILTER_GET:
4807                 ret = igb_get_ethertype_filter(dev,
4808                         (struct rte_eth_ethertype_filter *)arg);
4809                 break;
4810         default:
4811                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4812                 ret = -EINVAL;
4813                 break;
4814         }
4815         return ret;
4816 }
4817
4818 static int
4819 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4820                      enum rte_filter_type filter_type,
4821                      enum rte_filter_op filter_op,
4822                      void *arg)
4823 {
4824         int ret = 0;
4825
4826         switch (filter_type) {
4827         case RTE_ETH_FILTER_NTUPLE:
4828                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4829                 break;
4830         case RTE_ETH_FILTER_ETHERTYPE:
4831                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4832                 break;
4833         case RTE_ETH_FILTER_SYN:
4834                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4835                 break;
4836         case RTE_ETH_FILTER_FLEXIBLE:
4837                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4838                 break;
4839         case RTE_ETH_FILTER_GENERIC:
4840                 if (filter_op != RTE_ETH_FILTER_GET)
4841                         return -EINVAL;
4842                 *(const void **)arg = &igb_flow_ops;
4843                 break;
4844         default:
4845                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4846                                                         filter_type);
4847                 break;
4848         }
4849
4850         return ret;
4851 }
4852
4853 static int
4854 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4855                          struct ether_addr *mc_addr_set,
4856                          uint32_t nb_mc_addr)
4857 {
4858         struct e1000_hw *hw;
4859
4860         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4862         return 0;
4863 }
4864
4865 static uint64_t
4866 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4867 {
4868         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4869         uint64_t systime_cycles;
4870
4871         switch (hw->mac.type) {
4872         case e1000_i210:
4873         case e1000_i211:
4874                 /*
4875                  * Need to read System Time Residue Register to be able
4876                  * to read the other two registers.
4877                  */
4878                 E1000_READ_REG(hw, E1000_SYSTIMR);
4879                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4880                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4881                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4882                                 * NSEC_PER_SEC;
4883                 break;
4884         case e1000_82580:
4885         case e1000_i350:
4886         case e1000_i354:
4887                 /*
4888                  * Need to read System Time Residue Register to be able
4889                  * to read the other two registers.
4890                  */
4891                 E1000_READ_REG(hw, E1000_SYSTIMR);
4892                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4893                 /* Only the 8 LSB are valid. */
4894                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4895                                 & 0xff) << 32;
4896                 break;
4897         default:
4898                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4899                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4900                                 << 32;
4901                 break;
4902         }
4903
4904         return systime_cycles;
4905 }
4906
4907 static uint64_t
4908 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4909 {
4910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911         uint64_t rx_tstamp_cycles;
4912
4913         switch (hw->mac.type) {
4914         case e1000_i210:
4915         case e1000_i211:
4916                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4917                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4918                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4919                                 * NSEC_PER_SEC;
4920                 break;
4921         case e1000_82580:
4922         case e1000_i350:
4923         case e1000_i354:
4924                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4925                 /* Only the 8 LSB are valid. */
4926                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4927                                 & 0xff) << 32;
4928                 break;
4929         default:
4930                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4931                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4932                                 << 32;
4933                 break;
4934         }
4935
4936         return rx_tstamp_cycles;
4937 }
4938
4939 static uint64_t
4940 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4941 {
4942         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4943         uint64_t tx_tstamp_cycles;
4944
4945         switch (hw->mac.type) {
4946         case e1000_i210:
4947         case e1000_i211:
4948                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4949                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4950                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4951                                 * NSEC_PER_SEC;
4952                 break;
4953         case e1000_82580:
4954         case e1000_i350:
4955         case e1000_i354:
4956                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4957                 /* Only the 8 LSB are valid. */
4958                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4959                                 & 0xff) << 32;
4960                 break;
4961         default:
4962                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4963                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4964                                 << 32;
4965                 break;
4966         }
4967
4968         return tx_tstamp_cycles;
4969 }
4970
4971 static void
4972 igb_start_timecounters(struct rte_eth_dev *dev)
4973 {
4974         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975         struct e1000_adapter *adapter =
4976                 (struct e1000_adapter *)dev->data->dev_private;
4977         uint32_t incval = 1;
4978         uint32_t shift = 0;
4979         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4980
4981         switch (hw->mac.type) {
4982         case e1000_82580:
4983         case e1000_i350:
4984         case e1000_i354:
4985                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4986                 mask = (1ULL << 40) - 1;
4987                 /* fall-through */
4988         case e1000_i210:
4989         case e1000_i211:
4990                 /*
4991                  * Start incrementing the register
4992                  * used to timestamp PTP packets.
4993                  */
4994                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4995                 break;
4996         case e1000_82576:
4997                 incval = E1000_INCVALUE_82576;
4998                 shift = IGB_82576_TSYNC_SHIFT;
4999                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5000                                 E1000_INCPERIOD_82576 | incval);
5001                 break;
5002         default:
5003                 /* Not supported */
5004                 return;
5005         }
5006
5007         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5008         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5009         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5010
5011         adapter->systime_tc.cc_mask = mask;
5012         adapter->systime_tc.cc_shift = shift;
5013         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5014
5015         adapter->rx_tstamp_tc.cc_mask = mask;
5016         adapter->rx_tstamp_tc.cc_shift = shift;
5017         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5018
5019         adapter->tx_tstamp_tc.cc_mask = mask;
5020         adapter->tx_tstamp_tc.cc_shift = shift;
5021         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5022 }
5023
5024 static int
5025 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5026 {
5027         struct e1000_adapter *adapter =
5028                         (struct e1000_adapter *)dev->data->dev_private;
5029
5030         adapter->systime_tc.nsec += delta;
5031         adapter->rx_tstamp_tc.nsec += delta;
5032         adapter->tx_tstamp_tc.nsec += delta;
5033
5034         return 0;
5035 }
5036
5037 static int
5038 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5039 {
5040         uint64_t ns;
5041         struct e1000_adapter *adapter =
5042                         (struct e1000_adapter *)dev->data->dev_private;
5043
5044         ns = rte_timespec_to_ns(ts);
5045
5046         /* Set the timecounters to a new value. */
5047         adapter->systime_tc.nsec = ns;
5048         adapter->rx_tstamp_tc.nsec = ns;
5049         adapter->tx_tstamp_tc.nsec = ns;
5050
5051         return 0;
5052 }
5053
5054 static int
5055 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5056 {
5057         uint64_t ns, systime_cycles;
5058         struct e1000_adapter *adapter =
5059                         (struct e1000_adapter *)dev->data->dev_private;
5060
5061         systime_cycles = igb_read_systime_cyclecounter(dev);
5062         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5063         *ts = rte_ns_to_timespec(ns);
5064
5065         return 0;
5066 }
5067
5068 static int
5069 igb_timesync_enable(struct rte_eth_dev *dev)
5070 {
5071         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5072         uint32_t tsync_ctl;
5073         uint32_t tsauxc;
5074
5075         /* Stop the timesync system time. */
5076         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5077         /* Reset the timesync system time value. */
5078         switch (hw->mac.type) {
5079         case e1000_82580:
5080         case e1000_i350:
5081         case e1000_i354:
5082         case e1000_i210:
5083         case e1000_i211:
5084                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5085                 /* fall-through */
5086         case e1000_82576:
5087                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5088                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5089                 break;
5090         default:
5091                 /* Not supported. */
5092                 return -ENOTSUP;
5093         }
5094
5095         /* Enable system time for it isn't on by default. */
5096         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5097         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5098         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5099
5100         igb_start_timecounters(dev);
5101
5102         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5103         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5104                         (ETHER_TYPE_1588 |
5105                          E1000_ETQF_FILTER_ENABLE |
5106                          E1000_ETQF_1588));
5107
5108         /* Enable timestamping of received PTP packets. */
5109         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5110         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5111         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5112
5113         /* Enable Timestamping of transmitted PTP packets. */
5114         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5115         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5116         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5117
5118         return 0;
5119 }
5120
5121 static int
5122 igb_timesync_disable(struct rte_eth_dev *dev)
5123 {
5124         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5125         uint32_t tsync_ctl;
5126
5127         /* Disable timestamping of transmitted PTP packets. */
5128         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5129         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5130         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5131
5132         /* Disable timestamping of received PTP packets. */
5133         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5134         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5135         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5136
5137         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5138         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5139
5140         /* Stop incrementating the System Time registers. */
5141         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5142
5143         return 0;
5144 }
5145
5146 static int
5147 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5148                                struct timespec *timestamp,
5149                                uint32_t flags __rte_unused)
5150 {
5151         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5152         struct e1000_adapter *adapter =
5153                         (struct e1000_adapter *)dev->data->dev_private;
5154         uint32_t tsync_rxctl;
5155         uint64_t rx_tstamp_cycles;
5156         uint64_t ns;
5157
5158         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5159         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5160                 return -EINVAL;
5161
5162         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5163         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5164         *timestamp = rte_ns_to_timespec(ns);
5165
5166         return  0;
5167 }
5168
5169 static int
5170 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5171                                struct timespec *timestamp)
5172 {
5173         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         struct e1000_adapter *adapter =
5175                         (struct e1000_adapter *)dev->data->dev_private;
5176         uint32_t tsync_txctl;
5177         uint64_t tx_tstamp_cycles;
5178         uint64_t ns;
5179
5180         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5181         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5182                 return -EINVAL;
5183
5184         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5185         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5186         *timestamp = rte_ns_to_timespec(ns);
5187
5188         return  0;
5189 }
5190
5191 static int
5192 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5193 {
5194         int count = 0;
5195         int g_ind = 0;
5196         const struct reg_info *reg_group;
5197
5198         while ((reg_group = igb_regs[g_ind++]))
5199                 count += igb_reg_group_count(reg_group);
5200
5201         return count;
5202 }
5203
5204 static int
5205 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5206 {
5207         int count = 0;
5208         int g_ind = 0;
5209         const struct reg_info *reg_group;
5210
5211         while ((reg_group = igbvf_regs[g_ind++]))
5212                 count += igb_reg_group_count(reg_group);
5213
5214         return count;
5215 }
5216
5217 static int
5218 eth_igb_get_regs(struct rte_eth_dev *dev,
5219         struct rte_dev_reg_info *regs)
5220 {
5221         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5222         uint32_t *data = regs->data;
5223         int g_ind = 0;
5224         int count = 0;
5225         const struct reg_info *reg_group;
5226
5227         if (data == NULL) {
5228                 regs->length = eth_igb_get_reg_length(dev);
5229                 regs->width = sizeof(uint32_t);
5230                 return 0;
5231         }
5232
5233         /* Support only full register dump */
5234         if ((regs->length == 0) ||
5235             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5236                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5237                         hw->device_id;
5238                 while ((reg_group = igb_regs[g_ind++]))
5239                         count += igb_read_regs_group(dev, &data[count],
5240                                                         reg_group);
5241                 return 0;
5242         }
5243
5244         return -ENOTSUP;
5245 }
5246
5247 static int
5248 igbvf_get_regs(struct rte_eth_dev *dev,
5249         struct rte_dev_reg_info *regs)
5250 {
5251         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252         uint32_t *data = regs->data;
5253         int g_ind = 0;
5254         int count = 0;
5255         const struct reg_info *reg_group;
5256
5257         if (data == NULL) {
5258                 regs->length = igbvf_get_reg_length(dev);
5259                 regs->width = sizeof(uint32_t);
5260                 return 0;
5261         }
5262
5263         /* Support only full register dump */
5264         if ((regs->length == 0) ||
5265             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5266                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5267                         hw->device_id;
5268                 while ((reg_group = igbvf_regs[g_ind++]))
5269                         count += igb_read_regs_group(dev, &data[count],
5270                                                         reg_group);
5271                 return 0;
5272         }
5273
5274         return -ENOTSUP;
5275 }
5276
5277 static int
5278 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5279 {
5280         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5281
5282         /* Return unit is byte count */
5283         return hw->nvm.word_size * 2;
5284 }
5285
5286 static int
5287 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5288         struct rte_dev_eeprom_info *in_eeprom)
5289 {
5290         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         struct e1000_nvm_info *nvm = &hw->nvm;
5292         uint16_t *data = in_eeprom->data;
5293         int first, length;
5294
5295         first = in_eeprom->offset >> 1;
5296         length = in_eeprom->length >> 1;
5297         if ((first >= hw->nvm.word_size) ||
5298             ((first + length) >= hw->nvm.word_size))
5299                 return -EINVAL;
5300
5301         in_eeprom->magic = hw->vendor_id |
5302                 ((uint32_t)hw->device_id << 16);
5303
5304         if ((nvm->ops.read) == NULL)
5305                 return -ENOTSUP;
5306
5307         return nvm->ops.read(hw, first, length, data);
5308 }
5309
5310 static int
5311 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5312         struct rte_dev_eeprom_info *in_eeprom)
5313 {
5314         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315         struct e1000_nvm_info *nvm = &hw->nvm;
5316         uint16_t *data = in_eeprom->data;
5317         int first, length;
5318
5319         first = in_eeprom->offset >> 1;
5320         length = in_eeprom->length >> 1;
5321         if ((first >= hw->nvm.word_size) ||
5322             ((first + length) >= hw->nvm.word_size))
5323                 return -EINVAL;
5324
5325         in_eeprom->magic = (uint32_t)hw->vendor_id |
5326                 ((uint32_t)hw->device_id << 16);
5327
5328         if ((nvm->ops.write) == NULL)
5329                 return -ENOTSUP;
5330         return nvm->ops.write(hw,  first, length, data);
5331 }
5332
5333 static int
5334 eth_igb_get_module_info(struct rte_eth_dev *dev,
5335                         struct rte_eth_dev_module_info *modinfo)
5336 {
5337         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5338
5339         uint32_t status = 0;
5340         uint16_t sff8472_rev, addr_mode;
5341         bool page_swap = false;
5342
5343         if (hw->phy.media_type == e1000_media_type_copper ||
5344             hw->phy.media_type == e1000_media_type_unknown)
5345                 return -EOPNOTSUPP;
5346
5347         /* Check whether we support SFF-8472 or not */
5348         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
5349         if (status)
5350                 return -EIO;
5351
5352         /* addressing mode is not supported */
5353         status = e1000_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
5354         if (status)
5355                 return -EIO;
5356
5357         /* addressing mode is not supported */
5358         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
5359                 PMD_DRV_LOG(ERR,
5360                             "Address change required to access page 0xA2, "
5361                             "but not supported. Please report the module "
5362                             "type to the driver maintainers.\n");
5363                 page_swap = true;
5364         }
5365
5366         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
5367                 /* We have an SFP, but it does not support SFF-8472 */
5368                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
5369                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
5370         } else {
5371                 /* We have an SFP which supports a revision of SFF-8472 */
5372                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
5373                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
5374         }
5375
5376         return 0;
5377 }
5378
5379 static int
5380 eth_igb_get_module_eeprom(struct rte_eth_dev *dev,
5381                           struct rte_dev_eeprom_info *info)
5382 {
5383         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5384
5385         uint32_t status = 0;
5386         uint16_t dataword[RTE_ETH_MODULE_SFF_8472_LEN / 2 + 1];
5387         u16 first_word, last_word;
5388         int i = 0;
5389
5390         if (info->length == 0)
5391                 return -EINVAL;
5392
5393         first_word = info->offset >> 1;
5394         last_word = (info->offset + info->length - 1) >> 1;
5395
5396         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
5397         for (i = 0; i < last_word - first_word + 1; i++) {
5398                 status = e1000_read_phy_reg_i2c(hw, (first_word + i) * 2,
5399                                                 &dataword[i]);
5400                 if (status) {
5401                         /* Error occurred while reading module */
5402                         return -EIO;
5403                 }
5404
5405                 dataword[i] = rte_be_to_cpu_16(dataword[i]);
5406         }
5407
5408         memcpy(info->data, (u8 *)dataword + (info->offset & 1), info->length);
5409
5410         return 0;
5411 }
5412
5413 static int
5414 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5415 {
5416         struct e1000_hw *hw =
5417                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5418         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5419         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5420         uint32_t vec = E1000_MISC_VEC_ID;
5421
5422         if (rte_intr_allow_others(intr_handle))
5423                 vec = E1000_RX_VEC_START;
5424
5425         uint32_t mask = 1 << (queue_id + vec);
5426
5427         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5428         E1000_WRITE_FLUSH(hw);
5429
5430         return 0;
5431 }
5432
5433 static int
5434 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5435 {
5436         struct e1000_hw *hw =
5437                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5438         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5439         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5440         uint32_t vec = E1000_MISC_VEC_ID;
5441
5442         if (rte_intr_allow_others(intr_handle))
5443                 vec = E1000_RX_VEC_START;
5444
5445         uint32_t mask = 1 << (queue_id + vec);
5446         uint32_t regval;
5447
5448         regval = E1000_READ_REG(hw, E1000_EIMS);
5449         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5450         E1000_WRITE_FLUSH(hw);
5451
5452         rte_intr_enable(intr_handle);
5453
5454         return 0;
5455 }
5456
5457 static void
5458 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5459                    uint8_t index, uint8_t offset)
5460 {
5461         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5462
5463         /* clear bits */
5464         val &= ~((uint32_t)0xFF << offset);
5465
5466         /* write vector and valid bit */
5467         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5468
5469         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5470 }
5471
5472 static void
5473 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5474                            uint8_t queue, uint8_t msix_vector)
5475 {
5476         uint32_t tmp = 0;
5477
5478         if (hw->mac.type == e1000_82575) {
5479                 if (direction == 0)
5480                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5481                 else if (direction == 1)
5482                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5483                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5484         } else if (hw->mac.type == e1000_82576) {
5485                 if ((direction == 0) || (direction == 1))
5486                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5487                                            ((queue & 0x8) << 1) +
5488                                            8 * direction);
5489         } else if ((hw->mac.type == e1000_82580) ||
5490                         (hw->mac.type == e1000_i350) ||
5491                         (hw->mac.type == e1000_i354) ||
5492                         (hw->mac.type == e1000_i210) ||
5493                         (hw->mac.type == e1000_i211)) {
5494                 if ((direction == 0) || (direction == 1))
5495                         eth_igb_write_ivar(hw, msix_vector,
5496                                            queue >> 1,
5497                                            ((queue & 0x1) << 4) +
5498                                            8 * direction);
5499         }
5500 }
5501
5502 /* Sets up the hardware to generate MSI-X interrupts properly
5503  * @hw
5504  *  board private structure
5505  */
5506 static void
5507 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5508 {
5509         int queue_id;
5510         uint32_t tmpval, regval, intr_mask;
5511         struct e1000_hw *hw =
5512                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         uint32_t vec = E1000_MISC_VEC_ID;
5514         uint32_t base = E1000_MISC_VEC_ID;
5515         uint32_t misc_shift = 0;
5516         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5517         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5518
5519         /* won't configure msix register if no mapping is done
5520          * between intr vector and event fd
5521          */
5522         if (!rte_intr_dp_is_en(intr_handle))
5523                 return;
5524
5525         if (rte_intr_allow_others(intr_handle)) {
5526                 vec = base = E1000_RX_VEC_START;
5527                 misc_shift = 1;
5528         }
5529
5530         /* set interrupt vector for other causes */
5531         if (hw->mac.type == e1000_82575) {
5532                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5533                 /* enable MSI-X PBA support */
5534                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5535
5536                 /* Auto-Mask interrupts upon ICR read */
5537                 tmpval |= E1000_CTRL_EXT_EIAME;
5538                 tmpval |= E1000_CTRL_EXT_IRCA;
5539
5540                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5541
5542                 /* enable msix_other interrupt */
5543                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5544                 regval = E1000_READ_REG(hw, E1000_EIAC);
5545                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5546                 regval = E1000_READ_REG(hw, E1000_EIAM);
5547                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5548         } else if ((hw->mac.type == e1000_82576) ||
5549                         (hw->mac.type == e1000_82580) ||
5550                         (hw->mac.type == e1000_i350) ||
5551                         (hw->mac.type == e1000_i354) ||
5552                         (hw->mac.type == e1000_i210) ||
5553                         (hw->mac.type == e1000_i211)) {
5554                 /* turn on MSI-X capability first */
5555                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5556                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5557                                         E1000_GPIE_NSICR);
5558                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5559                         misc_shift;
5560                 regval = E1000_READ_REG(hw, E1000_EIAC);
5561                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5562
5563                 /* enable msix_other interrupt */
5564                 regval = E1000_READ_REG(hw, E1000_EIMS);
5565                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5566                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5567                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5568         }
5569
5570         /* use EIAM to auto-mask when MSI-X interrupt
5571          * is asserted, this saves a register write for every interrupt
5572          */
5573         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5574                 misc_shift;
5575         regval = E1000_READ_REG(hw, E1000_EIAM);
5576         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5577
5578         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5579                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5580                 intr_handle->intr_vec[queue_id] = vec;
5581                 if (vec < base + intr_handle->nb_efd - 1)
5582                         vec++;
5583         }
5584
5585         E1000_WRITE_FLUSH(hw);
5586 }
5587
5588 /* restore n-tuple filter */
5589 static inline void
5590 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5591 {
5592         struct e1000_filter_info *filter_info =
5593                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5594         struct e1000_5tuple_filter *p_5tuple;
5595         struct e1000_2tuple_filter *p_2tuple;
5596
5597         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5598                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5599         }
5600
5601         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5602                 igb_inject_2uple_filter(dev, p_2tuple);
5603         }
5604 }
5605
5606 /* restore SYN filter */
5607 static inline void
5608 igb_syn_filter_restore(struct rte_eth_dev *dev)
5609 {
5610         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611         struct e1000_filter_info *filter_info =
5612                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5613         uint32_t synqf;
5614
5615         synqf = filter_info->syn_info;
5616
5617         if (synqf & E1000_SYN_FILTER_ENABLE) {
5618                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5619                 E1000_WRITE_FLUSH(hw);
5620         }
5621 }
5622
5623 /* restore ethernet type filter */
5624 static inline void
5625 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5626 {
5627         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5628         struct e1000_filter_info *filter_info =
5629                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5630         int i;
5631
5632         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5633                 if (filter_info->ethertype_mask & (1 << i)) {
5634                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5635                                 filter_info->ethertype_filters[i].etqf);
5636                         E1000_WRITE_FLUSH(hw);
5637                 }
5638         }
5639 }
5640
5641 /* restore flex byte filter */
5642 static inline void
5643 igb_flex_filter_restore(struct rte_eth_dev *dev)
5644 {
5645         struct e1000_filter_info *filter_info =
5646                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5647         struct e1000_flex_filter *flex_filter;
5648
5649         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5650                 igb_inject_flex_filter(dev, flex_filter);
5651         }
5652 }
5653
5654 /* restore rss filter */
5655 static inline void
5656 igb_rss_filter_restore(struct rte_eth_dev *dev)
5657 {
5658         struct e1000_filter_info *filter_info =
5659                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5660
5661         if (filter_info->rss_info.conf.queue_num)
5662                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5663 }
5664
5665 /* restore all types filter */
5666 static int
5667 igb_filter_restore(struct rte_eth_dev *dev)
5668 {
5669         igb_ntuple_filter_restore(dev);
5670         igb_ethertype_filter_restore(dev);
5671         igb_syn_filter_restore(dev);
5672         igb_flex_filter_restore(dev);
5673         igb_rss_filter_restore(dev);
5674
5675         return 0;
5676 }
5677
5678 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5679 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5680 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5681 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5682 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5683 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");