drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 100                               struct rte_eth_xstats *xstats, unsigned n);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 104                               struct rte_eth_dev_info *dev_info);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 115 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 116                                                         void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129
 130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 136
 137 static int eth_igb_led_on(struct rte_eth_dev *dev);
 138 static int eth_igb_led_off(struct rte_eth_dev *dev);
 139
 140 static void igb_intr_disable(struct e1000_hw *hw);
 141 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 142 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 143                 struct ether_addr *mac_addr,
 144                 uint32_t index, uint32_t pool);
 145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 146 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *addr);
 148
 149 static void igbvf_intr_disable(struct e1000_hw *hw);
 150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 151 static int igbvf_dev_start(struct rte_eth_dev *dev);
 152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 153 static void igbvf_dev_close(struct rte_eth_dev *dev);
 154 static int eth_igbvf_link_update(struct e1000_hw *hw);
 155 static void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);
 156 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 157 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 158                 uint16_t vlan_id, int on);
 159 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 160 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 161 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 162                 struct ether_addr *addr);
 163 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 164 static int igbvf_get_regs(struct rte_eth_dev *dev,
 165                 struct rte_dev_reg_info *regs);
 166
 167 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 168                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 169                                    uint16_t reta_size);
 170 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 171                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 172                                   uint16_t reta_size);
 173
 174 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 175                         struct rte_eth_syn_filter *filter,
 176                         bool add);
 177 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 178                         struct rte_eth_syn_filter *filter);
 179 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 180                         enum rte_filter_op filter_op,
 181                         void *arg);
 182 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 183                         struct rte_eth_ntuple_filter *ntuple_filter);
 184 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 185                         struct rte_eth_ntuple_filter *ntuple_filter);
 186 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_flex_filter *filter,
 188                         bool add);
 189 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_flex_filter *filter);
 191 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 192                         enum rte_filter_op filter_op,
 193                         void *arg);
 194 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 197                         struct rte_eth_ntuple_filter *ntuple_filter);
 198 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *filter,
 200                         bool add);
 201 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_ntuple_filter *filter);
 203 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 204                                 enum rte_filter_op filter_op,
 205                                 void *arg);
 206 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 207                         struct rte_eth_ethertype_filter *filter,
 208                         bool add);
 209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 213                         struct rte_eth_ethertype_filter *filter);
 214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 215                      enum rte_filter_type filter_type,
 216                      enum rte_filter_op filter_op,
 217                      void *arg);
 218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 220                 struct rte_dev_reg_info *regs);
 221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 225                 struct rte_dev_eeprom_info *eeprom);
 226 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 227                                     struct ether_addr *mc_addr_set,
 228                                     uint32_t nb_mc_addr);
 229 static int igb_timesync_enable(struct rte_eth_dev *dev);
 230 static int igb_timesync_disable(struct rte_eth_dev *dev);
 231 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp,
 233                                           uint32_t flags);
 234 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp);
 236 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 237                                         uint16_t queue_id);
 238 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 239                                          uint16_t queue_id);
 240 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 241                                        uint8_t queue, uint8_t msix_vector);
 242 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 243                                uint8_t index, uint8_t offset);
 244 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 245
 246 /*
 247  * Define VF Stats MACRO for Non "cleared on read" register
 248  */
 249 #define UPDATE_VF_STAT(reg, last, cur)            \
 250 {                                                 \
 251         u32 latest = E1000_READ_REG(hw, reg);     \
 252         cur += (latest - last) & UINT_MAX;        \
 253         last = latest;                            \
 254 }
 255
 256 #define IGB_FC_PAUSE_TIME 0x0680
 257 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 258 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 259
 260 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 261
 262 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 263
 264 /*
 265  * The set of PCI devices this driver supports
 266  */
 267 static const struct rte_pci_id pci_id_igb_map[] = {
 268
 269 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 270 #include "rte_pci_dev_ids.h"
 271
 272 {0},
 273 };
 274
 275 /*
 276  * The set of PCI devices this driver supports (for 82576&I350 VF)
 277  */
 278 static const struct rte_pci_id pci_id_igbvf_map[] = {
 279
 280 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 281 #include "rte_pci_dev_ids.h"
 282
 283 {0},
 284 };
 285
 286 static const struct rte_eth_desc_lim rx_desc_lim = {
 287         .nb_max = E1000_MAX_RING_DESC,
 288         .nb_min = E1000_MIN_RING_DESC,
 289         .nb_align = IGB_RXD_ALIGN,
 290 };
 291
 292 static const struct rte_eth_desc_lim tx_desc_lim = {
 293         .nb_max = E1000_MAX_RING_DESC,
 294         .nb_min = E1000_MIN_RING_DESC,
 295         .nb_align = IGB_RXD_ALIGN,
 296 };
 297
 298 static const struct eth_dev_ops eth_igb_ops = {
 299         .dev_configure        = eth_igb_configure,
 300         .dev_start            = eth_igb_start,
 301         .dev_stop             = eth_igb_stop,
 302         .dev_close            = eth_igb_close,
 303         .promiscuous_enable   = eth_igb_promiscuous_enable,
 304         .promiscuous_disable  = eth_igb_promiscuous_disable,
 305         .allmulticast_enable  = eth_igb_allmulticast_enable,
 306         .allmulticast_disable = eth_igb_allmulticast_disable,
 307         .link_update          = eth_igb_link_update,
 308         .stats_get            = eth_igb_stats_get,
 309         .xstats_get           = eth_igb_xstats_get,
 310         .stats_reset          = eth_igb_stats_reset,
 311         .xstats_reset         = eth_igb_xstats_reset,
 312         .dev_infos_get        = eth_igb_infos_get,
 313         .mtu_set              = eth_igb_mtu_set,
 314         .vlan_filter_set      = eth_igb_vlan_filter_set,
 315         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 316         .vlan_offload_set     = eth_igb_vlan_offload_set,
 317         .rx_queue_setup       = eth_igb_rx_queue_setup,
 318         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 319         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 320         .rx_queue_release     = eth_igb_rx_queue_release,
 321         .rx_queue_count       = eth_igb_rx_queue_count,
 322         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 323         .tx_queue_setup       = eth_igb_tx_queue_setup,
 324         .tx_queue_release     = eth_igb_tx_queue_release,
 325         .dev_led_on           = eth_igb_led_on,
 326         .dev_led_off          = eth_igb_led_off,
 327         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 328         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 329         .mac_addr_add         = eth_igb_rar_set,
 330         .mac_addr_remove      = eth_igb_rar_clear,
 331         .mac_addr_set         = eth_igb_default_mac_addr_set,
 332         .reta_update          = eth_igb_rss_reta_update,
 333         .reta_query           = eth_igb_rss_reta_query,
 334         .rss_hash_update      = eth_igb_rss_hash_update,
 335         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 336         .filter_ctrl          = eth_igb_filter_ctrl,
 337         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 338         .rxq_info_get         = igb_rxq_info_get,
 339         .txq_info_get         = igb_txq_info_get,
 340         .timesync_enable      = igb_timesync_enable,
 341         .timesync_disable     = igb_timesync_disable,
 342         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 343         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 344         .get_reg_length       = eth_igb_get_reg_length,
 345         .get_reg              = eth_igb_get_regs,
 346         .get_eeprom_length    = eth_igb_get_eeprom_length,
 347         .get_eeprom           = eth_igb_get_eeprom,
 348         .set_eeprom           = eth_igb_set_eeprom,
 349 };
 350
 351 /*
 352  * dev_ops for virtual function, bare necessities for basic vf
 353  * operation have been implemented
 354  */
 355 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 356         .dev_configure        = igbvf_dev_configure,
 357         .dev_start            = igbvf_dev_start,
 358         .dev_stop             = igbvf_dev_stop,
 359         .dev_close            = igbvf_dev_close,
 360         .link_update          = eth_igb_link_update,
 361         .stats_get            = eth_igbvf_stats_get,
 362         .stats_reset          = eth_igbvf_stats_reset,
 363         .vlan_filter_set      = igbvf_vlan_filter_set,
 364         .dev_infos_get        = eth_igbvf_infos_get,
 365         .rx_queue_setup       = eth_igb_rx_queue_setup,
 366         .rx_queue_release     = eth_igb_rx_queue_release,
 367         .tx_queue_setup       = eth_igb_tx_queue_setup,
 368         .tx_queue_release     = eth_igb_tx_queue_release,
 369         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 370         .rxq_info_get         = igb_rxq_info_get,
 371         .txq_info_get         = igb_txq_info_get,
 372         .mac_addr_set         = igbvf_default_mac_addr_set,
 373         .get_reg_length       = igbvf_get_reg_length,
 374         .get_reg              = igbvf_get_regs,
 375 };
 376
 377 /* store statistics names and its offset in stats structure */
 378 struct rte_igb_xstats_name_off {
 379         char name[RTE_ETH_XSTATS_NAME_SIZE];
 380         unsigned offset;
 381 };
 382
 383 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 384         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 385         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 386         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 387         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 388         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 389         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 390         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 391                 ecol)},
 392         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 393         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 394         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 395         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 396         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 397         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 398         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 399         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 400         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 401         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 402         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 403                 fcruc)},
 404         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 405         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 406         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 407         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 408         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 409                 prc1023)},
 410         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 411                 prc1522)},
 412         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 413         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 414         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 415         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 416         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 417         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 418         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 419         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 420         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 421         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 422         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 423         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 424         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 425         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 426         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 427         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 428         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 429         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 430                 ptc1023)},
 431         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 432                 ptc1522)},
 433         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 434         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 435         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 436         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 437         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 438         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 439         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 440
 441         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 442 };
 443
 444 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 445                 sizeof(rte_igb_stats_strings[0]))
 446
 447 /**
 448  * Atomically reads the link status information from global
 449  * structure rte_eth_dev.
 450  *
 451  * @param dev
 452  *   - Pointer to the structure rte_eth_dev to read from.
 453  *   - Pointer to the buffer to be saved with the link status.
 454  *
 455  * @return
 456  *   - On success, zero.
 457  *   - On failure, negative value.
 458  */
 459 static inline int
 460 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 461                                 struct rte_eth_link *link)
 462 {
 463         struct rte_eth_link *dst = link;
 464         struct rte_eth_link *src = &(dev->data->dev_link);
 465
 466         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 467                                         *(uint64_t *)src) == 0)
 468                 return -1;
 469
 470         return 0;
 471 }
 472
 473 /**
 474  * Atomically writes the link status information into global
 475  * structure rte_eth_dev.
 476  *
 477  * @param dev
 478  *   - Pointer to the structure rte_eth_dev to read from.
 479  *   - Pointer to the buffer to be saved with the link status.
 480  *
 481  * @return
 482  *   - On success, zero.
 483  *   - On failure, negative value.
 484  */
 485 static inline int
 486 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 487                                 struct rte_eth_link *link)
 488 {
 489         struct rte_eth_link *dst = &(dev->data->dev_link);
 490         struct rte_eth_link *src = link;
 491
 492         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 493                                         *(uint64_t *)src) == 0)
 494                 return -1;
 495
 496         return 0;
 497 }
 498
 499 static inline void
 500 igb_intr_enable(struct rte_eth_dev *dev)
 501 {
 502         struct e1000_interrupt *intr =
 503                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 504         struct e1000_hw *hw =
 505                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 506
 507         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 508         E1000_WRITE_FLUSH(hw);
 509 }
 510
 511 static void
 512 igb_intr_disable(struct e1000_hw *hw)
 513 {
 514         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 515         E1000_WRITE_FLUSH(hw);
 516 }
 517
 518 static inline int32_t
 519 igb_pf_reset_hw(struct e1000_hw *hw)
 520 {
 521         uint32_t ctrl_ext;
 522         int32_t status;
 523
 524         status = e1000_reset_hw(hw);
 525
 526         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 527         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 528         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 529         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 530         E1000_WRITE_FLUSH(hw);
 531
 532         return status;
 533 }
 534
 535 static void
 536 igb_identify_hardware(struct rte_eth_dev *dev)
 537 {
 538         struct e1000_hw *hw =
 539                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 540
 541         hw->vendor_id = dev->pci_dev->id.vendor_id;
 542         hw->device_id = dev->pci_dev->id.device_id;
 543         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 544         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 545
 546         e1000_set_mac_type(hw);
 547
 548         /* need to check if it is a vf device below */
 549 }
 550
 551 static int
 552 igb_reset_swfw_lock(struct e1000_hw *hw)
 553 {
 554         int ret_val;
 555
 556         /*
 557          * Do mac ops initialization manually here, since we will need
 558          * some function pointers set by this call.
 559          */
 560         ret_val = e1000_init_mac_params(hw);
 561         if (ret_val)
 562                 return ret_val;
 563
 564         /*
 565          * SMBI lock should not fail in this early stage. If this is the case,
 566          * it is due to an improper exit of the application.
 567          * So force the release of the faulty lock.
 568          */
 569         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 570                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 571         }
 572         e1000_put_hw_semaphore_generic(hw);
 573
 574         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 575                 uint16_t mask;
 576
 577                 /*
 578                  * Phy lock should not fail in this early stage. If this is the case,
 579                  * it is due to an improper exit of the application.
 580                  * So force the release of the faulty lock.
 581                  */
 582                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 583                 if (hw->bus.func > E1000_FUNC_1)
 584                         mask <<= 2;
 585                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 586                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 587                                     hw->bus.func);
 588                 }
 589                 hw->mac.ops.release_swfw_sync(hw, mask);
 590
 591                 /*
 592                  * This one is more tricky since it is common to all ports; but
 593                  * swfw_sync retries last long enough (1s) to be almost sure that if
 594                  * lock can not be taken it is due to an improper lock of the
 595                  * semaphore.
 596                  */
 597                 mask = E1000_SWFW_EEP_SM;
 598                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 599                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 600                 }
 601                 hw->mac.ops.release_swfw_sync(hw, mask);
 602         }
 603
 604         return E1000_SUCCESS;
 605 }
 606
 607 static int
 608 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 609 {
 610         int error = 0;
 611         struct rte_pci_device *pci_dev;
 612         struct e1000_hw *hw =
 613                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 614         struct e1000_vfta * shadow_vfta =
 615                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 616         struct e1000_filter_info *filter_info =
 617                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 618         struct e1000_adapter *adapter =
 619                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 620
 621         uint32_t ctrl_ext;
 622
 623         pci_dev = eth_dev->pci_dev;
 624         eth_dev->dev_ops = &eth_igb_ops;
 625         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 626         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 627
 628         /* for secondary processes, we don't initialise any further as primary
 629          * has already done this work. Only check we don't need a different
 630          * RX function */
 631         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 632                 if (eth_dev->data->scattered_rx)
 633                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 634                 return 0;
 635         }
 636
 637         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 638
 639         igb_identify_hardware(eth_dev);
 640         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 641                 error = -EIO;
 642                 goto err_late;
 643         }
 644
 645         e1000_get_bus_info(hw);
 646
 647         /* Reset any pending lock */
 648         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 649                 error = -EIO;
 650                 goto err_late;
 651         }
 652
 653         /* Finish initialization */
 654         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 655                 error = -EIO;
 656                 goto err_late;
 657         }
 658
 659         hw->mac.autoneg = 1;
 660         hw->phy.autoneg_wait_to_complete = 0;
 661         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 662
 663         /* Copper options */
 664         if (hw->phy.media_type == e1000_media_type_copper) {
 665                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 666                 hw->phy.disable_polarity_correction = 0;
 667                 hw->phy.ms_type = e1000_ms_hw_default;
 668         }
 669
 670         /*
 671          * Start from a known state, this is important in reading the nvm
 672          * and mac from that.
 673          */
 674         igb_pf_reset_hw(hw);
 675
 676         /* Make sure we have a good EEPROM before we read from it */
 677         if (e1000_validate_nvm_checksum(hw) < 0) {
 678                 /*
 679                  * Some PCI-E parts fail the first check due to
 680                  * the link being in sleep state, call it again,
 681                  * if it fails a second time its a real issue.
 682                  */
 683                 if (e1000_validate_nvm_checksum(hw) < 0) {
 684                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 685                         error = -EIO;
 686                         goto err_late;
 687                 }
 688         }
 689
 690         /* Read the permanent MAC address out of the EEPROM */
 691         if (e1000_read_mac_addr(hw) != 0) {
 692                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 693                 error = -EIO;
 694                 goto err_late;
 695         }
 696
 697         /* Allocate memory for storing MAC addresses */
 698         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 699                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 700         if (eth_dev->data->mac_addrs == NULL) {
 701                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 702                                                 "store MAC addresses",
 703                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 704                 error = -ENOMEM;
 705                 goto err_late;
 706         }
 707
 708         /* Copy the permanent MAC address */
 709         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 710
 711         /* initialize the vfta */
 712         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 713
 714         /* Now initialize the hardware */
 715         if (igb_hardware_init(hw) != 0) {
 716                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 717                 rte_free(eth_dev->data->mac_addrs);
 718                 eth_dev->data->mac_addrs = NULL;
 719                 error = -ENODEV;
 720                 goto err_late;
 721         }
 722         hw->mac.get_link_status = 1;
 723         adapter->stopped = 0;
 724
 725         /* Indicate SOL/IDER usage */
 726         if (e1000_check_reset_block(hw) < 0) {
 727                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 728                                         "SOL/IDER session");
 729         }
 730
 731         /* initialize PF if max_vfs not zero */
 732         igb_pf_host_init(eth_dev);
 733
 734         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 735         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 736         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 737         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 738         E1000_WRITE_FLUSH(hw);
 739
 740         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 741                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 742                      pci_dev->id.device_id);
 743
 744         /* enable support intr */
 745         igb_intr_enable(eth_dev);
 746
 747         TAILQ_INIT(&filter_info->flex_list);
 748         filter_info->flex_mask = 0;
 749         TAILQ_INIT(&filter_info->twotuple_list);
 750         filter_info->twotuple_mask = 0;
 751         TAILQ_INIT(&filter_info->fivetuple_list);
 752         filter_info->fivetuple_mask = 0;
 753
 754         return 0;
 755
 756 err_late:
 757         igb_hw_control_release(hw);
 758
 759         return (error);
 760 }
 761
 762 static int
 763 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 764 {
 765         struct rte_pci_device *pci_dev;
 766         struct e1000_hw *hw;
 767         struct e1000_adapter *adapter =
 768                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 769
 770         PMD_INIT_FUNC_TRACE();
 771
 772         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 773                 return -EPERM;
 774
 775         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 776         pci_dev = eth_dev->pci_dev;
 777
 778         if (adapter->stopped == 0)
 779                 eth_igb_close(eth_dev);
 780
 781         eth_dev->dev_ops = NULL;
 782         eth_dev->rx_pkt_burst = NULL;
 783         eth_dev->tx_pkt_burst = NULL;
 784
 785         /* Reset any pending lock */
 786         igb_reset_swfw_lock(hw);
 787
 788         rte_free(eth_dev->data->mac_addrs);
 789         eth_dev->data->mac_addrs = NULL;
 790
 791         /* uninitialize PF if max_vfs not zero */
 792         igb_pf_host_uninit(eth_dev);
 793
 794         /* disable uio intr before callback unregister */
 795         rte_intr_disable(&(pci_dev->intr_handle));
 796         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 797                 eth_igb_interrupt_handler, (void *)eth_dev);
 798
 799         return 0;
 800 }
 801
 802 /*
 803  * Virtual Function device init
 804  */
 805 static int
 806 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 807 {
 808         struct rte_pci_device *pci_dev;
 809         struct e1000_adapter *adapter =
 810                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 811         struct e1000_hw *hw =
 812                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 813         int diag;
 814
 815         PMD_INIT_FUNC_TRACE();
 816
 817         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 818         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 819         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 820
 821         /* for secondary processes, we don't initialise any further as primary
 822          * has already done this work. Only check we don't need a different
 823          * RX function */
 824         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 825                 if (eth_dev->data->scattered_rx)
 826                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 827                 return 0;
 828         }
 829
 830         pci_dev = eth_dev->pci_dev;
 831
 832         hw->device_id = pci_dev->id.device_id;
 833         hw->vendor_id = pci_dev->id.vendor_id;
 834         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 835         adapter->stopped = 0;
 836
 837         /* Initialize the shared code (base driver) */
 838         diag = e1000_setup_init_funcs(hw, TRUE);
 839         if (diag != 0) {
 840                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 841                         diag);
 842                 return -EIO;
 843         }
 844
 845         /* init_mailbox_params */
 846         hw->mbx.ops.init_params(hw);
 847
 848         /* Disable the interrupts for VF */
 849         igbvf_intr_disable(hw);
 850
 851         diag = hw->mac.ops.reset_hw(hw);
 852
 853         /* Allocate memory for storing MAC addresses */
 854         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 855                 hw->mac.rar_entry_count, 0);
 856         if (eth_dev->data->mac_addrs == NULL) {
 857                 PMD_INIT_LOG(ERR,
 858                         "Failed to allocate %d bytes needed to store MAC "
 859                         "addresses",
 860                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 861                 return -ENOMEM;
 862         }
 863
 864         /* Copy the permanent MAC address */
 865         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 866                         &eth_dev->data->mac_addrs[0]);
 867
 868         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 869                      "mac.type=%s",
 870                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 871                      pci_dev->id.device_id, "igb_mac_82576_vf");
 872
 873         return 0;
 874 }
 875
 876 static int
 877 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 878 {
 879         struct e1000_adapter *adapter =
 880                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 881
 882         PMD_INIT_FUNC_TRACE();
 883
 884         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 885                 return -EPERM;
 886
 887         if (adapter->stopped == 0)
 888                 igbvf_dev_close(eth_dev);
 889
 890         eth_dev->dev_ops = NULL;
 891         eth_dev->rx_pkt_burst = NULL;
 892         eth_dev->tx_pkt_burst = NULL;
 893
 894         rte_free(eth_dev->data->mac_addrs);
 895         eth_dev->data->mac_addrs = NULL;
 896
 897         return 0;
 898 }
 899
 900 static struct eth_driver rte_igb_pmd = {
 901         .pci_drv = {
 902                 .name = "rte_igb_pmd",
 903                 .id_table = pci_id_igb_map,
 904                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 905                         RTE_PCI_DRV_DETACHABLE,
 906         },
 907         .eth_dev_init = eth_igb_dev_init,
 908         .eth_dev_uninit = eth_igb_dev_uninit,
 909         .dev_private_size = sizeof(struct e1000_adapter),
 910 };
 911
 912 /*
 913  * virtual function driver struct
 914  */
 915 static struct eth_driver rte_igbvf_pmd = {
 916         .pci_drv = {
 917                 .name = "rte_igbvf_pmd",
 918                 .id_table = pci_id_igbvf_map,
 919                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 920         },
 921         .eth_dev_init = eth_igbvf_dev_init,
 922         .eth_dev_uninit = eth_igbvf_dev_uninit,
 923         .dev_private_size = sizeof(struct e1000_adapter),
 924 };
 925
 926 static int
 927 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 928 {
 929         rte_eth_driver_register(&rte_igb_pmd);
 930         return 0;
 931 }
 932
 933 static void
 934 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 935 {
 936         struct e1000_hw *hw =
 937                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 939         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 940         rctl |= E1000_RCTL_VFE;
 941         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 942 }
 943
 944 /*
 945  * VF Driver initialization routine.
 946  * Invoked one at EAL init time.
 947  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 948  */
 949 static int
 950 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 951 {
 952         PMD_INIT_FUNC_TRACE();
 953
 954         rte_eth_driver_register(&rte_igbvf_pmd);
 955         return (0);
 956 }
 957
 958 static int
 959 igb_check_mq_mode(struct rte_eth_dev *dev)
 960 {
 961         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 962         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 963         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 964         uint16_t nb_tx_q = dev->data->nb_rx_queues;
 965
 966         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
 967             tx_mq_mode == ETH_MQ_TX_DCB ||
 968             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 969                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 970                 return -EINVAL;
 971         }
 972         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
 973                 /* Check multi-queue mode.
 974                  * To no break software we accept ETH_MQ_RX_NONE as this might
 975                  * be used to turn off VLAN filter.
 976                  */
 977
 978                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
 979                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 980                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
 981                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
 982                 } else {
 983                         /* Only support one queue on VFs.
 984                          * RSS together with SRIOV is not supported.
 985                          */
 986                         PMD_INIT_LOG(ERR, "SRIOV is active,"
 987                                         " wrong mq_mode rx %d.",
 988                                         rx_mq_mode);
 989                         return -EINVAL;
 990                 }
 991                 /* TX mode is not used here, so mode might be ignored.*/
 992                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
 993                         /* SRIOV only works in VMDq enable mode */
 994                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
 995                                         " TX mode %d is not supported. "
 996                                         " Driver will behave as %d mode.",
 997                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
 998                 }
 999
1000                 /* check valid queue number */
1001                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1002                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1003                                         " only support one queue on VFs.");
1004                         return -EINVAL;
1005                 }
1006         } else {
1007                 /* To no break software that set invalid mode, only display
1008                  * warning if invalid mode is used.
1009                  */
1010                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1011                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1012                     rx_mq_mode != ETH_MQ_RX_RSS) {
1013                         /* RSS together with VMDq not supported*/
1014                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1015                                      rx_mq_mode);
1016                         return -EINVAL;
1017                 }
1018
1019                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1020                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1021                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1022                                         " Due to txmode is meaningless in this"
1023                                         " driver, just ignore.",
1024                                         tx_mq_mode);
1025                 }
1026         }
1027         return 0;
1028 }
1029
1030 static int
1031 eth_igb_configure(struct rte_eth_dev *dev)
1032 {
1033         struct e1000_interrupt *intr =
1034                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1035         int ret;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         /* multipe queue mode checking */
1040         ret  = igb_check_mq_mode(dev);
1041         if (ret != 0) {
1042                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1043                             ret);
1044                 return ret;
1045         }
1046
1047         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1048         PMD_INIT_FUNC_TRACE();
1049
1050         return 0;
1051 }
1052
1053 static int
1054 eth_igb_start(struct rte_eth_dev *dev)
1055 {
1056         struct e1000_hw *hw =
1057                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1058         struct e1000_adapter *adapter =
1059                 E1000_DEV_PRIVATE(dev->data->dev_private);
1060         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1061         int ret, mask;
1062         uint32_t intr_vector = 0;
1063         uint32_t ctrl_ext;
1064
1065         PMD_INIT_FUNC_TRACE();
1066
1067         /* Power up the phy. Needed to make the link go Up */
1068         e1000_power_up_phy(hw);
1069
1070         /*
1071          * Packet Buffer Allocation (PBA)
1072          * Writing PBA sets the receive portion of the buffer
1073          * the remainder is used for the transmit buffer.
1074          */
1075         if (hw->mac.type == e1000_82575) {
1076                 uint32_t pba;
1077
1078                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1079                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1080         }
1081
1082         /* Put the address into the Receive Address Array */
1083         e1000_rar_set(hw, hw->mac.addr, 0);
1084
1085         /* Initialize the hardware */
1086         if (igb_hardware_init(hw)) {
1087                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1088                 return (-EIO);
1089         }
1090         adapter->stopped = 0;
1091
1092         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1093
1094         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1095         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1096         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1097         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1098         E1000_WRITE_FLUSH(hw);
1099
1100         /* configure PF module if SRIOV enabled */
1101         igb_pf_host_configure(dev);
1102
1103         /* check and configure queue intr-vector mapping */
1104         if (dev->data->dev_conf.intr_conf.rxq != 0)
1105                 intr_vector = dev->data->nb_rx_queues;
1106
1107         if (rte_intr_efd_enable(intr_handle, intr_vector))
1108                 return -1;
1109
1110         if (rte_intr_dp_is_en(intr_handle)) {
1111                 intr_handle->intr_vec =
1112                         rte_zmalloc("intr_vec",
1113                                     dev->data->nb_rx_queues * sizeof(int), 0);
1114                 if (intr_handle->intr_vec == NULL) {
1115                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1116                                      " intr_vec\n", dev->data->nb_rx_queues);
1117                         return -ENOMEM;
1118                 }
1119         }
1120
1121         /* confiugre msix for rx interrupt */
1122         eth_igb_configure_msix_intr(dev);
1123
1124         /* Configure for OS presence */
1125         igb_init_manageability(hw);
1126
1127         eth_igb_tx_init(dev);
1128
1129         /* This can fail when allocating mbufs for descriptor rings */
1130         ret = eth_igb_rx_init(dev);
1131         if (ret) {
1132                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1133                 igb_dev_clear_queues(dev);
1134                 return ret;
1135         }
1136
1137         e1000_clear_hw_cntrs_base_generic(hw);
1138
1139         /*
1140          * VLAN Offload Settings
1141          */
1142         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1143                         ETH_VLAN_EXTEND_MASK;
1144         eth_igb_vlan_offload_set(dev, mask);
1145
1146         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1147                 /* Enable VLAN filter since VMDq always use VLAN filter */
1148                 igb_vmdq_vlan_hw_filter_enable(dev);
1149         }
1150
1151         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1152                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1153                 (hw->mac.type == e1000_i211)) {
1154                 /* Configure EITR with the maximum possible value (0xFFFF) */
1155                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1156         }
1157
1158         /* Setup link speed and duplex */
1159         switch (dev->data->dev_conf.link_speed) {
1160         case ETH_LINK_SPEED_AUTONEG:
1161                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1162                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1163                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1164                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1165                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1166                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1167                 else
1168                         goto error_invalid_config;
1169                 break;
1170         case ETH_LINK_SPEED_10:
1171                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1172                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1173                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1174                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1175                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1176                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1177                 else
1178                         goto error_invalid_config;
1179                 break;
1180         case ETH_LINK_SPEED_100:
1181                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1182                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1183                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1184                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1185                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1186                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1187                 else
1188                         goto error_invalid_config;
1189                 break;
1190         case ETH_LINK_SPEED_1000:
1191                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1192                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1193                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1194                 else
1195                         goto error_invalid_config;
1196                 break;
1197         case ETH_LINK_SPEED_10000:
1198         default:
1199                 goto error_invalid_config;
1200         }
1201         e1000_setup_link(hw);
1202
1203         /* check if lsc interrupt feature is enabled */
1204         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1205                 if (rte_intr_allow_others(intr_handle)) {
1206                         rte_intr_callback_register(intr_handle,
1207                                                    eth_igb_interrupt_handler,
1208                                                    (void *)dev);
1209                         eth_igb_lsc_interrupt_setup(dev);
1210                 } else
1211                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1212                                      " no intr multiplex\n");
1213         }
1214
1215         /* check if rxq interrupt is enabled */
1216         if (dev->data->dev_conf.intr_conf.rxq != 0)
1217                 eth_igb_rxq_interrupt_setup(dev);
1218
1219         /* enable uio/vfio intr/eventfd mapping */
1220         rte_intr_enable(intr_handle);
1221
1222         /* resume enabled intr since hw reset */
1223         igb_intr_enable(dev);
1224
1225         PMD_INIT_LOG(DEBUG, "<<");
1226
1227         return (0);
1228
1229 error_invalid_config:
1230         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1231                      dev->data->dev_conf.link_speed,
1232                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1233         igb_dev_clear_queues(dev);
1234         return (-EINVAL);
1235 }
1236
1237 /*********************************************************************
1238  *
1239  *  This routine disables all traffic on the adapter by issuing a
1240  *  global reset on the MAC.
1241  *
1242  **********************************************************************/
1243 static void
1244 eth_igb_stop(struct rte_eth_dev *dev)
1245 {
1246         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247         struct e1000_filter_info *filter_info =
1248                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1249         struct rte_eth_link link;
1250         struct e1000_flex_filter *p_flex;
1251         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1252         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1253         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1254
1255         igb_intr_disable(hw);
1256
1257         /* disable intr eventfd mapping */
1258         rte_intr_disable(intr_handle);
1259
1260         igb_pf_reset_hw(hw);
1261         E1000_WRITE_REG(hw, E1000_WUC, 0);
1262
1263         /* Set bit for Go Link disconnect */
1264         if (hw->mac.type >= e1000_82580) {
1265                 uint32_t phpm_reg;
1266
1267                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1268                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1269                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1270         }
1271
1272         /* Power down the phy. Needed to make the link go Down */
1273         if (hw->phy.media_type == e1000_media_type_copper)
1274                 e1000_power_down_phy(hw);
1275         else
1276                 e1000_shutdown_fiber_serdes_link(hw);
1277
1278         igb_dev_clear_queues(dev);
1279
1280         /* clear the recorded link status */
1281         memset(&link, 0, sizeof(link));
1282         rte_igb_dev_atomic_write_link_status(dev, &link);
1283
1284         /* Remove all flex filters of the device */
1285         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1286                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1287                 rte_free(p_flex);
1288         }
1289         filter_info->flex_mask = 0;
1290
1291         /* Remove all ntuple filters of the device */
1292         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1293              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1294                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1295                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1296                              p_5tuple, entries);
1297                 rte_free(p_5tuple);
1298         }
1299         filter_info->fivetuple_mask = 0;
1300         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1301              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1302                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1303                 TAILQ_REMOVE(&filter_info->twotuple_list,
1304                              p_2tuple, entries);
1305                 rte_free(p_2tuple);
1306         }
1307         filter_info->twotuple_mask = 0;
1308
1309         /* Clean datapath event and queue/vec mapping */
1310         rte_intr_efd_disable(intr_handle);
1311         if (intr_handle->intr_vec != NULL) {
1312                 rte_free(intr_handle->intr_vec);
1313                 intr_handle->intr_vec = NULL;
1314         }
1315 }
1316
1317 static void
1318 eth_igb_close(struct rte_eth_dev *dev)
1319 {
1320         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321         struct e1000_adapter *adapter =
1322                 E1000_DEV_PRIVATE(dev->data->dev_private);
1323         struct rte_eth_link link;
1324         struct rte_pci_device *pci_dev;
1325
1326         eth_igb_stop(dev);
1327         adapter->stopped = 1;
1328
1329         e1000_phy_hw_reset(hw);
1330         igb_release_manageability(hw);
1331         igb_hw_control_release(hw);
1332
1333         /* Clear bit for Go Link disconnect */
1334         if (hw->mac.type >= e1000_82580) {
1335                 uint32_t phpm_reg;
1336
1337                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1338                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1339                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1340         }
1341
1342         igb_dev_free_queues(dev);
1343
1344         pci_dev = dev->pci_dev;
1345         if (pci_dev->intr_handle.intr_vec) {
1346                 rte_free(pci_dev->intr_handle.intr_vec);
1347                 pci_dev->intr_handle.intr_vec = NULL;
1348         }
1349
1350         memset(&link, 0, sizeof(link));
1351         rte_igb_dev_atomic_write_link_status(dev, &link);
1352 }
1353
1354 static int
1355 igb_get_rx_buffer_size(struct e1000_hw *hw)
1356 {
1357         uint32_t rx_buf_size;
1358         if (hw->mac.type == e1000_82576) {
1359                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1360         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1361                 /* PBS needs to be translated according to a lookup table */
1362                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1363                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1364                 rx_buf_size = (rx_buf_size << 10);
1365         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1366                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1367         } else {
1368                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1369         }
1370
1371         return rx_buf_size;
1372 }
1373
1374 /*********************************************************************
1375  *
1376  *  Initialize the hardware
1377  *
1378  **********************************************************************/
1379 static int
1380 igb_hardware_init(struct e1000_hw *hw)
1381 {
1382         uint32_t rx_buf_size;
1383         int diag;
1384
1385         /* Let the firmware know the OS is in control */
1386         igb_hw_control_acquire(hw);
1387
1388         /*
1389          * These parameters control the automatic generation (Tx) and
1390          * response (Rx) to Ethernet PAUSE frames.
1391          * - High water mark should allow for at least two standard size (1518)
1392          *   frames to be received after sending an XOFF.
1393          * - Low water mark works best when it is very near the high water mark.
1394          *   This allows the receiver to restart by sending XON when it has
1395          *   drained a bit. Here we use an arbitrary value of 1500 which will
1396          *   restart after one full frame is pulled from the buffer. There
1397          *   could be several smaller frames in the buffer and if so they will
1398          *   not trigger the XON until their total number reduces the buffer
1399          *   by 1500.
1400          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1401          */
1402         rx_buf_size = igb_get_rx_buffer_size(hw);
1403
1404         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1405         hw->fc.low_water = hw->fc.high_water - 1500;
1406         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1407         hw->fc.send_xon = 1;
1408
1409         /* Set Flow control, use the tunable location if sane */
1410         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1411                 hw->fc.requested_mode = igb_fc_setting;
1412         else
1413                 hw->fc.requested_mode = e1000_fc_none;
1414
1415         /* Issue a global reset */
1416         igb_pf_reset_hw(hw);
1417         E1000_WRITE_REG(hw, E1000_WUC, 0);
1418
1419         diag = e1000_init_hw(hw);
1420         if (diag < 0)
1421                 return (diag);
1422
1423         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1424         e1000_get_phy_info(hw);
1425         e1000_check_for_link(hw);
1426
1427         return (0);
1428 }
1429
1430 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1431 static void
1432 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1433 {
1434         int pause_frames;
1435
1436         if(hw->phy.media_type == e1000_media_type_copper ||
1437             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1438                 stats->symerrs +=
1439                     E1000_READ_REG(hw,E1000_SYMERRS);
1440                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1441         }
1442
1443         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1444         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1445         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1446         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1447
1448         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1449         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1450         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1451         stats->dc += E1000_READ_REG(hw, E1000_DC);
1452         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1453         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1454         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1455         /*
1456         ** For watchdog management we need to know if we have been
1457         ** paused during the last interval, so capture that here.
1458         */
1459         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1460         stats->xoffrxc += pause_frames;
1461         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1462         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1463         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1464         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1465         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1466         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1467         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1468         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1469         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1470         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1471         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1472         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1473
1474         /* For the 64-bit byte counters the low dword must be read first. */
1475         /* Both registers clear on the read of the high dword */
1476
1477         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1478         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1479         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1480         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1481
1482         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1483         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1484         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1485         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1486         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1487
1488         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1489         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1490         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1491         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1492
1493         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1494         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1495         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1496         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1497         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1498         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1499         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1500         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1501         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1502         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1503
1504         /* Interrupt Counts */
1505
1506         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1507         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1508         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1509         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1510         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1511         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1512         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1513         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1514         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1515
1516         /* Host to Card Statistics */
1517
1518         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1519         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1520         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1521         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1522         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1523         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1524         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1525         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1526         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1527         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1528         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1529         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1530         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1531         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1532
1533         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1534         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1535         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1536         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1537         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1538         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1539 }
1540
1541 static void
1542 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1543 {
1544         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1545         struct e1000_hw_stats *stats =
1546                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1547
1548         igb_read_stats_registers(hw, stats);
1549
1550         if (rte_stats == NULL)
1551                 return;
1552
1553         /* Rx Errors */
1554         rte_stats->ibadcrc = stats->crcerrs;
1555         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1556         rte_stats->imissed = stats->mpc;
1557         rte_stats->ierrors = rte_stats->ibadcrc +
1558                              rte_stats->ibadlen +
1559                              rte_stats->imissed +
1560                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1561
1562         /* Tx Errors */
1563         rte_stats->oerrors = stats->ecol + stats->latecol;
1564
1565         /* XON/XOFF pause frames */
1566         rte_stats->tx_pause_xon  = stats->xontxc;
1567         rte_stats->rx_pause_xon  = stats->xonrxc;
1568         rte_stats->tx_pause_xoff = stats->xofftxc;
1569         rte_stats->rx_pause_xoff = stats->xoffrxc;
1570
1571         rte_stats->ipackets = stats->gprc;
1572         rte_stats->opackets = stats->gptc;
1573         rte_stats->ibytes   = stats->gorc;
1574         rte_stats->obytes   = stats->gotc;
1575 }
1576
1577 static void
1578 eth_igb_stats_reset(struct rte_eth_dev *dev)
1579 {
1580         struct e1000_hw_stats *hw_stats =
1581                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1582
1583         /* HW registers are cleared on read */
1584         eth_igb_stats_get(dev, NULL);
1585
1586         /* Reset software totals */
1587         memset(hw_stats, 0, sizeof(*hw_stats));
1588 }
1589
1590 static void
1591 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1592 {
1593         struct e1000_hw_stats *stats =
1594                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1595
1596         /* HW registers are cleared on read */
1597         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1598
1599         /* Reset software totals */
1600         memset(stats, 0, sizeof(*stats));
1601 }
1602
1603 static int
1604 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1605                    unsigned n)
1606 {
1607         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         struct e1000_hw_stats *hw_stats =
1609                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1610         unsigned i;
1611
1612         if (n < IGB_NB_XSTATS)
1613                 return IGB_NB_XSTATS;
1614
1615         igb_read_stats_registers(hw, hw_stats);
1616
1617         /* If this is a reset xstats is NULL, and we have cleared the
1618          * registers by reading them.
1619          */
1620         if (!xstats)
1621                 return 0;
1622
1623         /* Extended stats */
1624         for (i = 0; i < IGB_NB_XSTATS; i++) {
1625                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1626                          "%s", rte_igb_stats_strings[i].name);
1627                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1628                         rte_igb_stats_strings[i].offset);
1629         }
1630
1631         return IGB_NB_XSTATS;
1632 }
1633
1634 static void
1635 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1636 {
1637         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1639                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1640
1641         /* Good Rx packets, include VF loopback */
1642         UPDATE_VF_STAT(E1000_VFGPRC,
1643             hw_stats->last_gprc, hw_stats->gprc);
1644
1645         /* Good Rx octets, include VF loopback */
1646         UPDATE_VF_STAT(E1000_VFGORC,
1647             hw_stats->last_gorc, hw_stats->gorc);
1648
1649         /* Good Tx packets, include VF loopback */
1650         UPDATE_VF_STAT(E1000_VFGPTC,
1651             hw_stats->last_gptc, hw_stats->gptc);
1652
1653         /* Good Tx octets, include VF loopback */
1654         UPDATE_VF_STAT(E1000_VFGOTC,
1655             hw_stats->last_gotc, hw_stats->gotc);
1656
1657         /* Rx Multicst packets */
1658         UPDATE_VF_STAT(E1000_VFMPRC,
1659             hw_stats->last_mprc, hw_stats->mprc);
1660
1661         /* Good Rx loopback packets */
1662         UPDATE_VF_STAT(E1000_VFGPRLBC,
1663             hw_stats->last_gprlbc, hw_stats->gprlbc);
1664
1665         /* Good Rx loopback octets */
1666         UPDATE_VF_STAT(E1000_VFGORLBC,
1667             hw_stats->last_gorlbc, hw_stats->gorlbc);
1668
1669         /* Good Tx loopback packets */
1670         UPDATE_VF_STAT(E1000_VFGPTLBC,
1671             hw_stats->last_gptlbc, hw_stats->gptlbc);
1672
1673         /* Good Tx loopback octets */
1674         UPDATE_VF_STAT(E1000_VFGOTLBC,
1675             hw_stats->last_gotlbc, hw_stats->gotlbc);
1676
1677         if (rte_stats == NULL)
1678                 return;
1679
1680         rte_stats->ipackets = hw_stats->gprc;
1681         rte_stats->ibytes = hw_stats->gorc;
1682         rte_stats->opackets = hw_stats->gptc;
1683         rte_stats->obytes = hw_stats->gotc;
1684         rte_stats->imcasts = hw_stats->mprc;
1685         rte_stats->ilbpackets = hw_stats->gprlbc;
1686         rte_stats->ilbbytes = hw_stats->gorlbc;
1687         rte_stats->olbpackets = hw_stats->gptlbc;
1688         rte_stats->olbbytes = hw_stats->gotlbc;
1689 }
1690
1691 static void
1692 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1693 {
1694         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1695                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1696
1697         /* Sync HW register to the last stats */
1698         eth_igbvf_stats_get(dev, NULL);
1699
1700         /* reset HW current stats*/
1701         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1702                offsetof(struct e1000_vf_stats, gprc));
1703
1704 }
1705
1706 static void
1707 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1708 {
1709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710
1711         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1712         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1713         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1714         dev_info->rx_offload_capa =
1715                 DEV_RX_OFFLOAD_VLAN_STRIP |
1716                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1717                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1718                 DEV_RX_OFFLOAD_TCP_CKSUM;
1719         dev_info->tx_offload_capa =
1720                 DEV_TX_OFFLOAD_VLAN_INSERT |
1721                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1722                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1723                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1724                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1725                 DEV_TX_OFFLOAD_TCP_TSO;
1726
1727         switch (hw->mac.type) {
1728         case e1000_82575:
1729                 dev_info->max_rx_queues = 4;
1730                 dev_info->max_tx_queues = 4;
1731                 dev_info->max_vmdq_pools = 0;
1732                 break;
1733
1734         case e1000_82576:
1735                 dev_info->max_rx_queues = 16;
1736                 dev_info->max_tx_queues = 16;
1737                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1738                 dev_info->vmdq_queue_num = 16;
1739                 break;
1740
1741         case e1000_82580:
1742                 dev_info->max_rx_queues = 8;
1743                 dev_info->max_tx_queues = 8;
1744                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1745                 dev_info->vmdq_queue_num = 8;
1746                 break;
1747
1748         case e1000_i350:
1749                 dev_info->max_rx_queues = 8;
1750                 dev_info->max_tx_queues = 8;
1751                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1752                 dev_info->vmdq_queue_num = 8;
1753                 break;
1754
1755         case e1000_i354:
1756                 dev_info->max_rx_queues = 8;
1757                 dev_info->max_tx_queues = 8;
1758                 break;
1759
1760         case e1000_i210:
1761                 dev_info->max_rx_queues = 4;
1762                 dev_info->max_tx_queues = 4;
1763                 dev_info->max_vmdq_pools = 0;
1764                 break;
1765
1766         case e1000_i211:
1767                 dev_info->max_rx_queues = 2;
1768                 dev_info->max_tx_queues = 2;
1769                 dev_info->max_vmdq_pools = 0;
1770                 break;
1771
1772         default:
1773                 /* Should not happen */
1774                 break;
1775         }
1776         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1777         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1778         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1779
1780         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1781                 .rx_thresh = {
1782                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1783                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1784                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1785                 },
1786                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1787                 .rx_drop_en = 0,
1788         };
1789
1790         dev_info->default_txconf = (struct rte_eth_txconf) {
1791                 .tx_thresh = {
1792                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1793                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1794                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1795                 },
1796                 .txq_flags = 0,
1797         };
1798
1799         dev_info->rx_desc_lim = rx_desc_lim;
1800         dev_info->tx_desc_lim = tx_desc_lim;
1801 }
1802
1803 static void
1804 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1805 {
1806         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807
1808         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1809         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1810         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1811         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1812                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1813                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1814                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1815         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1816                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1817                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1818                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1819                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1820                                 DEV_TX_OFFLOAD_TCP_TSO;
1821         switch (hw->mac.type) {
1822         case e1000_vfadapt:
1823                 dev_info->max_rx_queues = 2;
1824                 dev_info->max_tx_queues = 2;
1825                 break;
1826         case e1000_vfadapt_i350:
1827                 dev_info->max_rx_queues = 1;
1828                 dev_info->max_tx_queues = 1;
1829                 break;
1830         default:
1831                 /* Should not happen */
1832                 break;
1833         }
1834
1835         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1836                 .rx_thresh = {
1837                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1838                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1839                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1840                 },
1841                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1842                 .rx_drop_en = 0,
1843         };
1844
1845         dev_info->default_txconf = (struct rte_eth_txconf) {
1846                 .tx_thresh = {
1847                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1848                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1849                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1850                 },
1851                 .txq_flags = 0,
1852         };
1853
1854         dev_info->rx_desc_lim = rx_desc_lim;
1855         dev_info->tx_desc_lim = tx_desc_lim;
1856 }
1857
1858 /* return 0 means link status changed, -1 means not changed */
1859 static int
1860 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1861 {
1862         struct e1000_hw *hw =
1863                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         struct rte_eth_link link, old;
1865         int link_check, count;
1866
1867         link_check = 0;
1868         hw->mac.get_link_status = 1;
1869
1870         /* possible wait-to-complete in up to 9 seconds */
1871         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1872                 /* Read the real link status */
1873                 switch (hw->phy.media_type) {
1874                 case e1000_media_type_copper:
1875                         /* Do the work to read phy */
1876                         e1000_check_for_link(hw);
1877                         link_check = !hw->mac.get_link_status;
1878                         break;
1879
1880                 case e1000_media_type_fiber:
1881                         e1000_check_for_link(hw);
1882                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1883                                       E1000_STATUS_LU);
1884                         break;
1885
1886                 case e1000_media_type_internal_serdes:
1887                         e1000_check_for_link(hw);
1888                         link_check = hw->mac.serdes_has_link;
1889                         break;
1890
1891                 /* VF device is type_unknown */
1892                 case e1000_media_type_unknown:
1893                         eth_igbvf_link_update(hw);
1894                         link_check = !hw->mac.get_link_status;
1895                         break;
1896
1897                 default:
1898                         break;
1899                 }
1900                 if (link_check || wait_to_complete == 0)
1901                         break;
1902                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1903         }
1904         memset(&link, 0, sizeof(link));
1905         rte_igb_dev_atomic_read_link_status(dev, &link);
1906         old = link;
1907
1908         /* Now we check if a transition has happened */
1909         if (link_check) {
1910                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1911                                           &link.link_duplex);
1912                 link.link_status = 1;
1913         } else if (!link_check) {
1914                 link.link_speed = 0;
1915                 link.link_duplex = 0;
1916                 link.link_status = 0;
1917         }
1918         rte_igb_dev_atomic_write_link_status(dev, &link);
1919
1920         /* not changed */
1921         if (old.link_status == link.link_status)
1922                 return -1;
1923
1924         /* changed */
1925         return 0;
1926 }
1927
1928 /*
1929  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1930  * For ASF and Pass Through versions of f/w this means
1931  * that the driver is loaded.
1932  */
1933 static void
1934 igb_hw_control_acquire(struct e1000_hw *hw)
1935 {
1936         uint32_t ctrl_ext;
1937
1938         /* Let firmware know the driver has taken over */
1939         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1940         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1941 }
1942
1943 /*
1944  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1945  * For ASF and Pass Through versions of f/w this means that the
1946  * driver is no longer loaded.
1947  */
1948 static void
1949 igb_hw_control_release(struct e1000_hw *hw)
1950 {
1951         uint32_t ctrl_ext;
1952
1953         /* Let firmware taken over control of h/w */
1954         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1955         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
1956                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1957 }
1958
1959 /*
1960  * Bit of a misnomer, what this really means is
1961  * to enable OS management of the system... aka
1962  * to disable special hardware management features.
1963  */
1964 static void
1965 igb_init_manageability(struct e1000_hw *hw)
1966 {
1967         if (e1000_enable_mng_pass_thru(hw)) {
1968                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
1969                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1970
1971                 /* disable hardware interception of ARP */
1972                 manc &= ~(E1000_MANC_ARP_EN);
1973
1974                 /* enable receiving management packets to the host */
1975                 manc |= E1000_MANC_EN_MNG2HOST;
1976                 manc2h |= 1 << 5;  /* Mng Port 623 */
1977                 manc2h |= 1 << 6;  /* Mng Port 664 */
1978                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
1979                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1980         }
1981 }
1982
1983 static void
1984 igb_release_manageability(struct e1000_hw *hw)
1985 {
1986         if (e1000_enable_mng_pass_thru(hw)) {
1987                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
1988
1989                 manc |= E1000_MANC_ARP_EN;
1990                 manc &= ~E1000_MANC_EN_MNG2HOST;
1991
1992                 E1000_WRITE_REG(hw, E1000_MANC, manc);
1993         }
1994 }
1995
1996 static void
1997 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
1998 {
1999         struct e1000_hw *hw =
2000                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         uint32_t rctl;
2002
2003         rctl = E1000_READ_REG(hw, E1000_RCTL);
2004         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2005         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2006 }
2007
2008 static void
2009 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2010 {
2011         struct e1000_hw *hw =
2012                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         uint32_t rctl;
2014
2015         rctl = E1000_READ_REG(hw, E1000_RCTL);
2016         rctl &= (~E1000_RCTL_UPE);
2017         if (dev->data->all_multicast == 1)
2018                 rctl |= E1000_RCTL_MPE;
2019         else
2020                 rctl &= (~E1000_RCTL_MPE);
2021         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2022 }
2023
2024 static void
2025 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2026 {
2027         struct e1000_hw *hw =
2028                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t rctl;
2030
2031         rctl = E1000_READ_REG(hw, E1000_RCTL);
2032         rctl |= E1000_RCTL_MPE;
2033         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2034 }
2035
2036 static void
2037 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2038 {
2039         struct e1000_hw *hw =
2040                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         uint32_t rctl;
2042
2043         if (dev->data->promiscuous == 1)
2044                 return; /* must remain in all_multicast mode */
2045         rctl = E1000_READ_REG(hw, E1000_RCTL);
2046         rctl &= (~E1000_RCTL_MPE);
2047         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2048 }
2049
2050 static int
2051 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2052 {
2053         struct e1000_hw *hw =
2054                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct e1000_vfta * shadow_vfta =
2056                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2057         uint32_t vfta;
2058         uint32_t vid_idx;
2059         uint32_t vid_bit;
2060
2061         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2062                               E1000_VFTA_ENTRY_MASK);
2063         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2064         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2065         if (on)
2066                 vfta |= vid_bit;
2067         else
2068                 vfta &= ~vid_bit;
2069         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2070
2071         /* update local VFTA copy */
2072         shadow_vfta->vfta[vid_idx] = vfta;
2073
2074         return 0;
2075 }
2076
2077 static void
2078 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2079 {
2080         struct e1000_hw *hw =
2081                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         uint32_t reg = ETHER_TYPE_VLAN ;
2083
2084         reg |= (tpid << 16);
2085         E1000_WRITE_REG(hw, E1000_VET, reg);
2086 }
2087
2088 static void
2089 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2090 {
2091         struct e1000_hw *hw =
2092                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093         uint32_t reg;
2094
2095         /* Filter Table Disable */
2096         reg = E1000_READ_REG(hw, E1000_RCTL);
2097         reg &= ~E1000_RCTL_CFIEN;
2098         reg &= ~E1000_RCTL_VFE;
2099         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2100 }
2101
2102 static void
2103 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2104 {
2105         struct e1000_hw *hw =
2106                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct e1000_vfta * shadow_vfta =
2108                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2109         uint32_t reg;
2110         int i;
2111
2112         /* Filter Table Enable, CFI not used for packet acceptance */
2113         reg = E1000_READ_REG(hw, E1000_RCTL);
2114         reg &= ~E1000_RCTL_CFIEN;
2115         reg |= E1000_RCTL_VFE;
2116         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2117
2118         /* restore VFTA table */
2119         for (i = 0; i < IGB_VFTA_SIZE; i++)
2120                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2121 }
2122
2123 static void
2124 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2125 {
2126         struct e1000_hw *hw =
2127                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128         uint32_t reg;
2129
2130         /* VLAN Mode Disable */
2131         reg = E1000_READ_REG(hw, E1000_CTRL);
2132         reg &= ~E1000_CTRL_VME;
2133         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2134 }
2135
2136 static void
2137 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2138 {
2139         struct e1000_hw *hw =
2140                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         uint32_t reg;
2142
2143         /* VLAN Mode Enable */
2144         reg = E1000_READ_REG(hw, E1000_CTRL);
2145         reg |= E1000_CTRL_VME;
2146         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2147 }
2148
2149 static void
2150 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2151 {
2152         struct e1000_hw *hw =
2153                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         uint32_t reg;
2155
2156         /* CTRL_EXT: Extended VLAN */
2157         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2158         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2159         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2160
2161         /* Update maximum packet length */
2162         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2163                 E1000_WRITE_REG(hw, E1000_RLPML,
2164                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2165                                                 VLAN_TAG_SIZE);
2166 }
2167
2168 static void
2169 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2170 {
2171         struct e1000_hw *hw =
2172                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         uint32_t reg;
2174
2175         /* CTRL_EXT: Extended VLAN */
2176         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2177         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2178         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2179
2180         /* Update maximum packet length */
2181         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2182                 E1000_WRITE_REG(hw, E1000_RLPML,
2183                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2184                                                 2 * VLAN_TAG_SIZE);
2185 }
2186
2187 static void
2188 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 {
2190         if(mask & ETH_VLAN_STRIP_MASK){
2191                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2192                         igb_vlan_hw_strip_enable(dev);
2193                 else
2194                         igb_vlan_hw_strip_disable(dev);
2195         }
2196
2197         if(mask & ETH_VLAN_FILTER_MASK){
2198                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2199                         igb_vlan_hw_filter_enable(dev);
2200                 else
2201                         igb_vlan_hw_filter_disable(dev);
2202         }
2203
2204         if(mask & ETH_VLAN_EXTEND_MASK){
2205                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2206                         igb_vlan_hw_extend_enable(dev);
2207                 else
2208                         igb_vlan_hw_extend_disable(dev);
2209         }
2210 }
2211
2212
2213 /**
2214  * It enables the interrupt mask and then enable the interrupt.
2215  *
2216  * @param dev
2217  *  Pointer to struct rte_eth_dev.
2218  *
2219  * @return
2220  *  - On success, zero.
2221  *  - On failure, a negative value.
2222  */
2223 static int
2224 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2225 {
2226         struct e1000_interrupt *intr =
2227                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2228
2229         intr->mask |= E1000_ICR_LSC;
2230
2231         return 0;
2232 }
2233
2234 /* It clears the interrupt causes and enables the interrupt.
2235  * It will be called once only during nic initialized.
2236  *
2237  * @param dev
2238  *  Pointer to struct rte_eth_dev.
2239  *
2240  * @return
2241  *  - On success, zero.
2242  *  - On failure, a negative value.
2243  */
2244 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2245 {
2246         uint32_t mask, regval;
2247         struct e1000_hw *hw =
2248                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2249         struct rte_eth_dev_info dev_info;
2250
2251         memset(&dev_info, 0, sizeof(dev_info));
2252         eth_igb_infos_get(dev, &dev_info);
2253
2254         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2255         regval = E1000_READ_REG(hw, E1000_EIMS);
2256         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2257
2258         return 0;
2259 }
2260
2261 /*
2262  * It reads ICR and gets interrupt causes, check it and set a bit flag
2263  * to update link status.
2264  *
2265  * @param dev
2266  *  Pointer to struct rte_eth_dev.
2267  *
2268  * @return
2269  *  - On success, zero.
2270  *  - On failure, a negative value.
2271  */
2272 static int
2273 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2274 {
2275         uint32_t icr;
2276         struct e1000_hw *hw =
2277                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         struct e1000_interrupt *intr =
2279                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2280
2281         igb_intr_disable(hw);
2282
2283         /* read-on-clear nic registers here */
2284         icr = E1000_READ_REG(hw, E1000_ICR);
2285
2286         intr->flags = 0;
2287         if (icr & E1000_ICR_LSC) {
2288                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2289         }
2290
2291         if (icr & E1000_ICR_VMMB)
2292                 intr->flags |= E1000_FLAG_MAILBOX;
2293
2294         return 0;
2295 }
2296
2297 /*
2298  * It executes link_update after knowing an interrupt is prsent.
2299  *
2300  * @param dev
2301  *  Pointer to struct rte_eth_dev.
2302  *
2303  * @return
2304  *  - On success, zero.
2305  *  - On failure, a negative value.
2306  */
2307 static int
2308 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2309 {
2310         struct e1000_hw *hw =
2311                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2312         struct e1000_interrupt *intr =
2313                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2314         uint32_t tctl, rctl;
2315         struct rte_eth_link link;
2316         int ret;
2317
2318         if (intr->flags & E1000_FLAG_MAILBOX) {
2319                 igb_pf_mbx_process(dev);
2320                 intr->flags &= ~E1000_FLAG_MAILBOX;
2321         }
2322
2323         igb_intr_enable(dev);
2324         rte_intr_enable(&(dev->pci_dev->intr_handle));
2325
2326         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2327                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2328
2329                 /* set get_link_status to check register later */
2330                 hw->mac.get_link_status = 1;
2331                 ret = eth_igb_link_update(dev, 0);
2332
2333                 /* check if link has changed */
2334                 if (ret < 0)
2335                         return 0;
2336
2337                 memset(&link, 0, sizeof(link));
2338                 rte_igb_dev_atomic_read_link_status(dev, &link);
2339                 if (link.link_status) {
2340                         PMD_INIT_LOG(INFO,
2341                                      " Port %d: Link Up - speed %u Mbps - %s",
2342                                      dev->data->port_id,
2343                                      (unsigned)link.link_speed,
2344                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2345                                      "full-duplex" : "half-duplex");
2346                 } else {
2347                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2348                                      dev->data->port_id);
2349                 }
2350
2351                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2352                              dev->pci_dev->addr.domain,
2353                              dev->pci_dev->addr.bus,
2354                              dev->pci_dev->addr.devid,
2355                              dev->pci_dev->addr.function);
2356                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2357                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2358                 if (link.link_status) {
2359                         /* enable Tx/Rx */
2360                         tctl |= E1000_TCTL_EN;
2361                         rctl |= E1000_RCTL_EN;
2362                 } else {
2363                         /* disable Tx/Rx */
2364                         tctl &= ~E1000_TCTL_EN;
2365                         rctl &= ~E1000_RCTL_EN;
2366                 }
2367                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2368                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2369                 E1000_WRITE_FLUSH(hw);
2370                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2371         }
2372
2373         return 0;
2374 }
2375
2376 /**
2377  * Interrupt handler which shall be registered at first.
2378  *
2379  * @param handle
2380  *  Pointer to interrupt handle.
2381  * @param param
2382  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2383  *
2384  * @return
2385  *  void
2386  */
2387 static void
2388 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2389                                                         void *param)
2390 {
2391         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2392
2393         eth_igb_interrupt_get_status(dev);
2394         eth_igb_interrupt_action(dev);
2395 }
2396
2397 static int
2398 eth_igb_led_on(struct rte_eth_dev *dev)
2399 {
2400         struct e1000_hw *hw;
2401
2402         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2403         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2404 }
2405
2406 static int
2407 eth_igb_led_off(struct rte_eth_dev *dev)
2408 {
2409         struct e1000_hw *hw;
2410
2411         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2413 }
2414
2415 static int
2416 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2417 {
2418         struct e1000_hw *hw;
2419         uint32_t ctrl;
2420         int tx_pause;
2421         int rx_pause;
2422
2423         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         fc_conf->pause_time = hw->fc.pause_time;
2425         fc_conf->high_water = hw->fc.high_water;
2426         fc_conf->low_water = hw->fc.low_water;
2427         fc_conf->send_xon = hw->fc.send_xon;
2428         fc_conf->autoneg = hw->mac.autoneg;
2429
2430         /*
2431          * Return rx_pause and tx_pause status according to actual setting of
2432          * the TFCE and RFCE bits in the CTRL register.
2433          */
2434         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2435         if (ctrl & E1000_CTRL_TFCE)
2436                 tx_pause = 1;
2437         else
2438                 tx_pause = 0;
2439
2440         if (ctrl & E1000_CTRL_RFCE)
2441                 rx_pause = 1;
2442         else
2443                 rx_pause = 0;
2444
2445         if (rx_pause && tx_pause)
2446                 fc_conf->mode = RTE_FC_FULL;
2447         else if (rx_pause)
2448                 fc_conf->mode = RTE_FC_RX_PAUSE;
2449         else if (tx_pause)
2450                 fc_conf->mode = RTE_FC_TX_PAUSE;
2451         else
2452                 fc_conf->mode = RTE_FC_NONE;
2453
2454         return 0;
2455 }
2456
2457 static int
2458 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2459 {
2460         struct e1000_hw *hw;
2461         int err;
2462         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2463                 e1000_fc_none,
2464                 e1000_fc_rx_pause,
2465                 e1000_fc_tx_pause,
2466                 e1000_fc_full
2467         };
2468         uint32_t rx_buf_size;
2469         uint32_t max_high_water;
2470         uint32_t rctl;
2471
2472         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         if (fc_conf->autoneg != hw->mac.autoneg)
2474                 return -ENOTSUP;
2475         rx_buf_size = igb_get_rx_buffer_size(hw);
2476         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2477
2478         /* At least reserve one Ethernet frame for watermark */
2479         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2480         if ((fc_conf->high_water > max_high_water) ||
2481             (fc_conf->high_water < fc_conf->low_water)) {
2482                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2483                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2484                 return (-EINVAL);
2485         }
2486
2487         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2488         hw->fc.pause_time     = fc_conf->pause_time;
2489         hw->fc.high_water     = fc_conf->high_water;
2490         hw->fc.low_water      = fc_conf->low_water;
2491         hw->fc.send_xon       = fc_conf->send_xon;
2492
2493         err = e1000_setup_link_generic(hw);
2494         if (err == E1000_SUCCESS) {
2495
2496                 /* check if we want to forward MAC frames - driver doesn't have native
2497                  * capability to do that, so we'll write the registers ourselves */
2498
2499                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2500
2501                 /* set or clear MFLCN.PMCF bit depending on configuration */
2502                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2503                         rctl |= E1000_RCTL_PMCF;
2504                 else
2505                         rctl &= ~E1000_RCTL_PMCF;
2506
2507                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2508                 E1000_WRITE_FLUSH(hw);
2509
2510                 return 0;
2511         }
2512
2513         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2514         return (-EIO);
2515 }
2516
2517 #define E1000_RAH_POOLSEL_SHIFT      (18)
2518 static void
2519 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2520                 uint32_t index, __rte_unused uint32_t pool)
2521 {
2522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t rah;
2524
2525         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2526         rah = E1000_READ_REG(hw, E1000_RAH(index));
2527         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2528         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2529 }
2530
2531 static void
2532 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2533 {
2534         uint8_t addr[ETHER_ADDR_LEN];
2535         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536
2537         memset(addr, 0, sizeof(addr));
2538
2539         e1000_rar_set(hw, addr, index);
2540 }
2541
2542 static void
2543 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2544                                 struct ether_addr *addr)
2545 {
2546         eth_igb_rar_clear(dev, 0);
2547
2548         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2549 }
2550 /*
2551  * Virtual Function operations
2552  */
2553 static void
2554 igbvf_intr_disable(struct e1000_hw *hw)
2555 {
2556         PMD_INIT_FUNC_TRACE();
2557
2558         /* Clear interrupt mask to stop from interrupts being generated */
2559         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2560
2561         E1000_WRITE_FLUSH(hw);
2562 }
2563
2564 static void
2565 igbvf_stop_adapter(struct rte_eth_dev *dev)
2566 {
2567         u32 reg_val;
2568         u16 i;
2569         struct rte_eth_dev_info dev_info;
2570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571
2572         memset(&dev_info, 0, sizeof(dev_info));
2573         eth_igbvf_infos_get(dev, &dev_info);
2574
2575         /* Clear interrupt mask to stop from interrupts being generated */
2576         igbvf_intr_disable(hw);
2577
2578         /* Clear any pending interrupts, flush previous writes */
2579         E1000_READ_REG(hw, E1000_EICR);
2580
2581         /* Disable the transmit unit.  Each queue must be disabled. */
2582         for (i = 0; i < dev_info.max_tx_queues; i++)
2583                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2584
2585         /* Disable the receive unit by stopping each queue */
2586         for (i = 0; i < dev_info.max_rx_queues; i++) {
2587                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2588                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2589                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2590                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2591                         ;
2592         }
2593
2594         /* flush all queues disables */
2595         E1000_WRITE_FLUSH(hw);
2596         msec_delay(2);
2597 }
2598
2599 static int eth_igbvf_link_update(struct e1000_hw *hw)
2600 {
2601         struct e1000_mbx_info *mbx = &hw->mbx;
2602         struct e1000_mac_info *mac = &hw->mac;
2603         int ret_val = E1000_SUCCESS;
2604
2605         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2606
2607         /*
2608          * We only want to run this if there has been a rst asserted.
2609          * in this case that could mean a link change, device reset,
2610          * or a virtual function reset
2611          */
2612
2613         /* If we were hit with a reset or timeout drop the link */
2614         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2615                 mac->get_link_status = TRUE;
2616
2617         if (!mac->get_link_status)
2618                 goto out;
2619
2620         /* if link status is down no point in checking to see if pf is up */
2621         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2622                 goto out;
2623
2624         /* if we passed all the tests above then the link is up and we no
2625          * longer need to check for link */
2626         mac->get_link_status = FALSE;
2627
2628 out:
2629         return ret_val;
2630 }
2631
2632
2633 static int
2634 igbvf_dev_configure(struct rte_eth_dev *dev)
2635 {
2636         struct rte_eth_conf* conf = &dev->data->dev_conf;
2637
2638         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2639                      dev->data->port_id);
2640
2641         /*
2642          * VF has no ability to enable/disable HW CRC
2643          * Keep the persistent behavior the same as Host PF
2644          */
2645 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2646         if (!conf->rxmode.hw_strip_crc) {
2647                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2648                 conf->rxmode.hw_strip_crc = 1;
2649         }
2650 #else
2651         if (conf->rxmode.hw_strip_crc) {
2652                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2653                 conf->rxmode.hw_strip_crc = 0;
2654         }
2655 #endif
2656
2657         return 0;
2658 }
2659
2660 static int
2661 igbvf_dev_start(struct rte_eth_dev *dev)
2662 {
2663         struct e1000_hw *hw =
2664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2665         struct e1000_adapter *adapter =
2666                 E1000_DEV_PRIVATE(dev->data->dev_private);
2667         int ret;
2668
2669         PMD_INIT_FUNC_TRACE();
2670
2671         hw->mac.ops.reset_hw(hw);
2672         adapter->stopped = 0;
2673
2674         /* Set all vfta */
2675         igbvf_set_vfta_all(dev,1);
2676
2677         eth_igbvf_tx_init(dev);
2678
2679         /* This can fail when allocating mbufs for descriptor rings */
2680         ret = eth_igbvf_rx_init(dev);
2681         if (ret) {
2682                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2683                 igb_dev_clear_queues(dev);
2684                 return ret;
2685         }
2686
2687         return 0;
2688 }
2689
2690 static void
2691 igbvf_dev_stop(struct rte_eth_dev *dev)
2692 {
2693         PMD_INIT_FUNC_TRACE();
2694
2695         igbvf_stop_adapter(dev);
2696
2697         /*
2698           * Clear what we set, but we still keep shadow_vfta to
2699           * restore after device starts
2700           */
2701         igbvf_set_vfta_all(dev,0);
2702
2703         igb_dev_clear_queues(dev);
2704 }
2705
2706 static void
2707 igbvf_dev_close(struct rte_eth_dev *dev)
2708 {
2709         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         struct e1000_adapter *adapter =
2711                 E1000_DEV_PRIVATE(dev->data->dev_private);
2712
2713         PMD_INIT_FUNC_TRACE();
2714
2715         e1000_reset_hw(hw);
2716
2717         igbvf_dev_stop(dev);
2718         adapter->stopped = 1;
2719         igb_dev_free_queues(dev);
2720 }
2721
2722 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2723 {
2724         struct e1000_mbx_info *mbx = &hw->mbx;
2725         uint32_t msgbuf[2];
2726
2727         /* After set vlan, vlan strip will also be enabled in igb driver*/
2728         msgbuf[0] = E1000_VF_SET_VLAN;
2729         msgbuf[1] = vid;
2730         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2731         if (on)
2732                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2733
2734         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2735 }
2736
2737 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2738 {
2739         struct e1000_hw *hw =
2740                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741         struct e1000_vfta * shadow_vfta =
2742                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2743         int i = 0, j = 0, vfta = 0, mask = 1;
2744
2745         for (i = 0; i < IGB_VFTA_SIZE; i++){
2746                 vfta = shadow_vfta->vfta[i];
2747                 if(vfta){
2748                         mask = 1;
2749                         for (j = 0; j < 32; j++){
2750                                 if(vfta & mask)
2751                                         igbvf_set_vfta(hw,
2752                                                 (uint16_t)((i<<5)+j), on);
2753                                 mask<<=1;
2754                         }
2755                 }
2756         }
2757
2758 }
2759
2760 static int
2761 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2762 {
2763         struct e1000_hw *hw =
2764                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         struct e1000_vfta * shadow_vfta =
2766                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2767         uint32_t vid_idx = 0;
2768         uint32_t vid_bit = 0;
2769         int ret = 0;
2770
2771         PMD_INIT_FUNC_TRACE();
2772
2773         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2774         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2775         if(ret){
2776                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2777                 return ret;
2778         }
2779         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2780         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2781
2782         /*Save what we set and retore it after device reset*/
2783         if (on)
2784                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2785         else
2786                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2787
2788         return 0;
2789 }
2790
2791 static void
2792 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2793 {
2794         struct e1000_hw *hw =
2795                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796
2797         /* index is not used by rar_set() */
2798         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2799 }
2800
2801
2802 static int
2803 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2804                         struct rte_eth_rss_reta_entry64 *reta_conf,
2805                         uint16_t reta_size)
2806 {
2807         uint8_t i, j, mask;
2808         uint32_t reta, r;
2809         uint16_t idx, shift;
2810         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811
2812         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2813                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2814                         "(%d) doesn't match the number hardware can supported "
2815                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2816                 return -EINVAL;
2817         }
2818
2819         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2820                 idx = i / RTE_RETA_GROUP_SIZE;
2821                 shift = i % RTE_RETA_GROUP_SIZE;
2822                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2823                                                 IGB_4_BIT_MASK);
2824                 if (!mask)
2825                         continue;
2826                 if (mask == IGB_4_BIT_MASK)
2827                         r = 0;
2828                 else
2829                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2830                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2831                         if (mask & (0x1 << j))
2832                                 reta |= reta_conf[idx].reta[shift + j] <<
2833                                                         (CHAR_BIT * j);
2834                         else
2835                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2836                 }
2837                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int
2844 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2845                        struct rte_eth_rss_reta_entry64 *reta_conf,
2846                        uint16_t reta_size)
2847 {
2848         uint8_t i, j, mask;
2849         uint32_t reta;
2850         uint16_t idx, shift;
2851         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852
2853         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2854                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2855                         "(%d) doesn't match the number hardware can supported "
2856                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2857                 return -EINVAL;
2858         }
2859
2860         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2861                 idx = i / RTE_RETA_GROUP_SIZE;
2862                 shift = i % RTE_RETA_GROUP_SIZE;
2863                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2864                                                 IGB_4_BIT_MASK);
2865                 if (!mask)
2866                         continue;
2867                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2868                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2869                         if (mask & (0x1 << j))
2870                                 reta_conf[idx].reta[shift + j] =
2871                                         ((reta >> (CHAR_BIT * j)) &
2872                                                 IGB_8_BIT_MASK);
2873                 }
2874         }
2875
2876         return 0;
2877 }
2878
2879 #define MAC_TYPE_FILTER_SUP(type)    do {\
2880         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2881                 (type) != e1000_82576)\
2882                 return -ENOTSUP;\
2883 } while (0)
2884
2885 static int
2886 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2887                         struct rte_eth_syn_filter *filter,
2888                         bool add)
2889 {
2890         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891         uint32_t synqf, rfctl;
2892
2893         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2894                 return -EINVAL;
2895
2896         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2897
2898         if (add) {
2899                 if (synqf & E1000_SYN_FILTER_ENABLE)
2900                         return -EINVAL;
2901
2902                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2903                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2904
2905                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2906                 if (filter->hig_pri)
2907                         rfctl |= E1000_RFCTL_SYNQFP;
2908                 else
2909                         rfctl &= ~E1000_RFCTL_SYNQFP;
2910
2911                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2912         } else {
2913                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2914                         return -ENOENT;
2915                 synqf = 0;
2916         }
2917
2918         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2919         E1000_WRITE_FLUSH(hw);
2920         return 0;
2921 }
2922
2923 static int
2924 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2925                         struct rte_eth_syn_filter *filter)
2926 {
2927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         uint32_t synqf, rfctl;
2929
2930         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2931         if (synqf & E1000_SYN_FILTER_ENABLE) {
2932                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2933                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2934                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2935                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2936                 return 0;
2937         }
2938
2939         return -ENOENT;
2940 }
2941
2942 static int
2943 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2944                         enum rte_filter_op filter_op,
2945                         void *arg)
2946 {
2947         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         int ret;
2949
2950         MAC_TYPE_FILTER_SUP(hw->mac.type);
2951
2952         if (filter_op == RTE_ETH_FILTER_NOP)
2953                 return 0;
2954
2955         if (arg == NULL) {
2956                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
2957                             filter_op);
2958                 return -EINVAL;
2959         }
2960
2961         switch (filter_op) {
2962         case RTE_ETH_FILTER_ADD:
2963                 ret = eth_igb_syn_filter_set(dev,
2964                                 (struct rte_eth_syn_filter *)arg,
2965                                 TRUE);
2966                 break;
2967         case RTE_ETH_FILTER_DELETE:
2968                 ret = eth_igb_syn_filter_set(dev,
2969                                 (struct rte_eth_syn_filter *)arg,
2970                                 FALSE);
2971                 break;
2972         case RTE_ETH_FILTER_GET:
2973                 ret = eth_igb_syn_filter_get(dev,
2974                                 (struct rte_eth_syn_filter *)arg);
2975                 break;
2976         default:
2977                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
2978                 ret = -EINVAL;
2979                 break;
2980         }
2981
2982         return ret;
2983 }
2984
2985 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
2986         if ((type) != e1000_82580 && (type) != e1000_i350)\
2987                 return -ENOSYS; \
2988 } while (0)
2989
2990 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
2991 static inline int
2992 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
2993                         struct e1000_2tuple_filter_info *filter_info)
2994 {
2995         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2996                 return -EINVAL;
2997         if (filter->priority > E1000_2TUPLE_MAX_PRI)
2998                 return -EINVAL;  /* filter index is out of range. */
2999         if (filter->tcp_flags > TCP_FLAG_ALL)
3000                 return -EINVAL;  /* flags is invalid. */
3001
3002         switch (filter->dst_port_mask) {
3003         case UINT16_MAX:
3004                 filter_info->dst_port_mask = 0;
3005                 filter_info->dst_port = filter->dst_port;
3006                 break;
3007         case 0:
3008                 filter_info->dst_port_mask = 1;
3009                 break;
3010         default:
3011                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3012                 return -EINVAL;
3013         }
3014
3015         switch (filter->proto_mask) {
3016         case UINT8_MAX:
3017                 filter_info->proto_mask = 0;
3018                 filter_info->proto = filter->proto;
3019                 break;
3020         case 0:
3021                 filter_info->proto_mask = 1;
3022                 break;
3023         default:
3024                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3025                 return -EINVAL;
3026         }
3027
3028         filter_info->priority = (uint8_t)filter->priority;
3029         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3030                 filter_info->tcp_flags = filter->tcp_flags;
3031         else
3032                 filter_info->tcp_flags = 0;
3033
3034         return 0;
3035 }
3036
3037 static inline struct e1000_2tuple_filter *
3038 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3039                         struct e1000_2tuple_filter_info *key)
3040 {
3041         struct e1000_2tuple_filter *it;
3042
3043         TAILQ_FOREACH(it, filter_list, entries) {
3044                 if (memcmp(key, &it->filter_info,
3045                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3046                         return it;
3047                 }
3048         }
3049         return NULL;
3050 }
3051
3052 /*
3053  * igb_add_2tuple_filter - add a 2tuple filter
3054  *
3055  * @param
3056  * dev: Pointer to struct rte_eth_dev.
3057  * ntuple_filter: ponter to the filter that will be added.
3058  *
3059  * @return
3060  *    - On success, zero.
3061  *    - On failure, a negative value.
3062  */
3063 static int
3064 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3065                         struct rte_eth_ntuple_filter *ntuple_filter)
3066 {
3067         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         struct e1000_filter_info *filter_info =
3069                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3070         struct e1000_2tuple_filter *filter;
3071         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3072         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3073         int i, ret;
3074
3075         filter = rte_zmalloc("e1000_2tuple_filter",
3076                         sizeof(struct e1000_2tuple_filter), 0);
3077         if (filter == NULL)
3078                 return -ENOMEM;
3079
3080         ret = ntuple_filter_to_2tuple(ntuple_filter,
3081                                       &filter->filter_info);
3082         if (ret < 0) {
3083                 rte_free(filter);
3084                 return ret;
3085         }
3086         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3087                                          &filter->filter_info) != NULL) {
3088                 PMD_DRV_LOG(ERR, "filter exists.");
3089                 rte_free(filter);
3090                 return -EEXIST;
3091         }
3092         filter->queue = ntuple_filter->queue;
3093
3094         /*
3095          * look for an unused 2tuple filter index,
3096          * and insert the filter to list.
3097          */
3098         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3099                 if (!(filter_info->twotuple_mask & (1 << i))) {
3100                         filter_info->twotuple_mask |= 1 << i;
3101                         filter->index = i;
3102                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3103                                           filter,
3104                                           entries);
3105                         break;
3106                 }
3107         }
3108         if (i >= E1000_MAX_TTQF_FILTERS) {
3109                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3110                 rte_free(filter);
3111                 return -ENOSYS;
3112         }
3113
3114         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3115         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3116                 imir |= E1000_IMIR_PORT_BP;
3117         else
3118                 imir &= ~E1000_IMIR_PORT_BP;
3119
3120         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3121
3122         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3123         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3124         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3125         if (filter->filter_info.proto_mask == 0)
3126                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3127
3128         /* tcp flags bits setting. */
3129         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3130                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3131                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3132                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3133                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3134                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3135                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3136                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3137                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3138                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3139                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3140                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3141                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3142         } else
3143                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3144         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3145         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3146         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3147         return 0;
3148 }
3149
3150 /*
3151  * igb_remove_2tuple_filter - remove a 2tuple filter
3152  *
3153  * @param
3154  * dev: Pointer to struct rte_eth_dev.
3155  * ntuple_filter: ponter to the filter that will be removed.
3156  *
3157  * @return
3158  *    - On success, zero.
3159  *    - On failure, a negative value.
3160  */
3161 static int
3162 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3163                         struct rte_eth_ntuple_filter *ntuple_filter)
3164 {
3165         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3166         struct e1000_filter_info *filter_info =
3167                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3168         struct e1000_2tuple_filter_info filter_2tuple;
3169         struct e1000_2tuple_filter *filter;
3170         int ret;
3171
3172         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3173         ret = ntuple_filter_to_2tuple(ntuple_filter,
3174                                       &filter_2tuple);
3175         if (ret < 0)
3176                 return ret;
3177
3178         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3179                                          &filter_2tuple);
3180         if (filter == NULL) {
3181                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3182                 return -ENOENT;
3183         }
3184
3185         filter_info->twotuple_mask &= ~(1 << filter->index);
3186         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3187         rte_free(filter);
3188
3189         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3190         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3191         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3192         return 0;
3193 }
3194
3195 static inline struct e1000_flex_filter *
3196 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3197                         struct e1000_flex_filter_info *key)
3198 {
3199         struct e1000_flex_filter *it;
3200
3201         TAILQ_FOREACH(it, filter_list, entries) {
3202                 if (memcmp(key, &it->filter_info,
3203                         sizeof(struct e1000_flex_filter_info)) == 0)
3204                         return it;
3205         }
3206
3207         return NULL;
3208 }
3209
3210 static int
3211 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3212                         struct rte_eth_flex_filter *filter,
3213                         bool add)
3214 {
3215         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3216         struct e1000_filter_info *filter_info =
3217                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3218         struct e1000_flex_filter *flex_filter, *it;
3219         uint32_t wufc, queueing, mask;
3220         uint32_t reg_off;
3221         uint8_t shift, i, j = 0;
3222
3223         flex_filter = rte_zmalloc("e1000_flex_filter",
3224                         sizeof(struct e1000_flex_filter), 0);
3225         if (flex_filter == NULL)
3226                 return -ENOMEM;
3227
3228         flex_filter->filter_info.len = filter->len;
3229         flex_filter->filter_info.priority = filter->priority;
3230         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3231         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3232                 mask = 0;
3233                 /* reverse bits in flex filter's mask*/
3234                 for (shift = 0; shift < CHAR_BIT; shift++) {
3235                         if (filter->mask[i] & (0x01 << shift))
3236                                 mask |= (0x80 >> shift);
3237                 }
3238                 flex_filter->filter_info.mask[i] = mask;
3239         }
3240
3241         wufc = E1000_READ_REG(hw, E1000_WUFC);
3242         if (flex_filter->index < E1000_MAX_FHFT)
3243                 reg_off = E1000_FHFT(flex_filter->index);
3244         else
3245                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3246
3247         if (add) {
3248                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3249                                 &flex_filter->filter_info) != NULL) {
3250                         PMD_DRV_LOG(ERR, "filter exists.");
3251                         rte_free(flex_filter);
3252                         return -EEXIST;
3253                 }
3254                 flex_filter->queue = filter->queue;
3255                 /*
3256                  * look for an unused flex filter index
3257                  * and insert the filter into the list.
3258                  */
3259                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3260                         if (!(filter_info->flex_mask & (1 << i))) {
3261                                 filter_info->flex_mask |= 1 << i;
3262                                 flex_filter->index = i;
3263                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3264                                         flex_filter,
3265                                         entries);
3266                                 break;
3267                         }
3268                 }
3269                 if (i >= E1000_MAX_FLEX_FILTERS) {
3270                         PMD_DRV_LOG(ERR, "flex filters are full.");
3271                         rte_free(flex_filter);
3272                         return -ENOSYS;
3273                 }
3274
3275                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3276                                 (E1000_WUFC_FLX0 << flex_filter->index));
3277                 queueing = filter->len |
3278                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3279                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3280                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3281                                 queueing);
3282                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3283                         E1000_WRITE_REG(hw, reg_off,
3284                                         flex_filter->filter_info.dwords[j]);
3285                         reg_off += sizeof(uint32_t);
3286                         E1000_WRITE_REG(hw, reg_off,
3287                                         flex_filter->filter_info.dwords[++j]);
3288                         reg_off += sizeof(uint32_t);
3289                         E1000_WRITE_REG(hw, reg_off,
3290                                 (uint32_t)flex_filter->filter_info.mask[i]);
3291                         reg_off += sizeof(uint32_t) * 2;
3292                         ++j;
3293                 }
3294         } else {
3295                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3296                                 &flex_filter->filter_info);
3297                 if (it == NULL) {
3298                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3299                         rte_free(flex_filter);
3300                         return -ENOENT;
3301                 }
3302
3303                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3304                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3305                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3306                         (~(E1000_WUFC_FLX0 << it->index)));
3307
3308                 filter_info->flex_mask &= ~(1 << it->index);
3309                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3310                 rte_free(it);
3311                 rte_free(flex_filter);
3312         }
3313
3314         return 0;
3315 }
3316
3317 static int
3318 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3319                         struct rte_eth_flex_filter *filter)
3320 {
3321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         struct e1000_filter_info *filter_info =
3323                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3324         struct e1000_flex_filter flex_filter, *it;
3325         uint32_t wufc, queueing, wufc_en = 0;
3326
3327         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3328         flex_filter.filter_info.len = filter->len;
3329         flex_filter.filter_info.priority = filter->priority;
3330         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3331         memcpy(flex_filter.filter_info.mask, filter->mask,
3332                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3333
3334         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3335                                 &flex_filter.filter_info);
3336         if (it == NULL) {
3337                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3338                 return -ENOENT;
3339         }
3340
3341         wufc = E1000_READ_REG(hw, E1000_WUFC);
3342         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3343
3344         if ((wufc & wufc_en) == wufc_en) {
3345                 uint32_t reg_off = 0;
3346                 if (it->index < E1000_MAX_FHFT)
3347                         reg_off = E1000_FHFT(it->index);
3348                 else
3349                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3350
3351                 queueing = E1000_READ_REG(hw,
3352                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3353                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3354                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3355                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3356                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3357                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3358                 return 0;
3359         }
3360         return -ENOENT;
3361 }
3362
3363 static int
3364 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3365                         enum rte_filter_op filter_op,
3366                         void *arg)
3367 {
3368         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369         struct rte_eth_flex_filter *filter;
3370         int ret = 0;
3371
3372         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3373
3374         if (filter_op == RTE_ETH_FILTER_NOP)
3375                 return ret;
3376
3377         if (arg == NULL) {
3378                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3379                             filter_op);
3380                 return -EINVAL;
3381         }
3382
3383         filter = (struct rte_eth_flex_filter *)arg;
3384         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3385             || filter->len % sizeof(uint64_t) != 0) {
3386                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3387                 return -EINVAL;
3388         }
3389         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3390                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3391                 return -EINVAL;
3392         }
3393
3394         switch (filter_op) {
3395         case RTE_ETH_FILTER_ADD:
3396                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3397                 break;
3398         case RTE_ETH_FILTER_DELETE:
3399                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3400                 break;
3401         case RTE_ETH_FILTER_GET:
3402                 ret = eth_igb_get_flex_filter(dev, filter);
3403                 break;
3404         default:
3405                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3406                 ret = -EINVAL;
3407                 break;
3408         }
3409
3410         return ret;
3411 }
3412
3413 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3414 static inline int
3415 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3416                         struct e1000_5tuple_filter_info *filter_info)
3417 {
3418         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3419                 return -EINVAL;
3420         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3421                 return -EINVAL;  /* filter index is out of range. */
3422         if (filter->tcp_flags > TCP_FLAG_ALL)
3423                 return -EINVAL;  /* flags is invalid. */
3424
3425         switch (filter->dst_ip_mask) {
3426         case UINT32_MAX:
3427                 filter_info->dst_ip_mask = 0;
3428                 filter_info->dst_ip = filter->dst_ip;
3429                 break;
3430         case 0:
3431                 filter_info->dst_ip_mask = 1;
3432                 break;
3433         default:
3434                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3435                 return -EINVAL;
3436         }
3437
3438         switch (filter->src_ip_mask) {
3439         case UINT32_MAX:
3440                 filter_info->src_ip_mask = 0;
3441                 filter_info->src_ip = filter->src_ip;
3442                 break;
3443         case 0:
3444                 filter_info->src_ip_mask = 1;
3445                 break;
3446         default:
3447                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3448                 return -EINVAL;
3449         }
3450
3451         switch (filter->dst_port_mask) {
3452         case UINT16_MAX:
3453                 filter_info->dst_port_mask = 0;
3454                 filter_info->dst_port = filter->dst_port;
3455                 break;
3456         case 0:
3457                 filter_info->dst_port_mask = 1;
3458                 break;
3459         default:
3460                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3461                 return -EINVAL;
3462         }
3463
3464         switch (filter->src_port_mask) {
3465         case UINT16_MAX:
3466                 filter_info->src_port_mask = 0;
3467                 filter_info->src_port = filter->src_port;
3468                 break;
3469         case 0:
3470                 filter_info->src_port_mask = 1;
3471                 break;
3472         default:
3473                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3474                 return -EINVAL;
3475         }
3476
3477         switch (filter->proto_mask) {
3478         case UINT8_MAX:
3479                 filter_info->proto_mask = 0;
3480                 filter_info->proto = filter->proto;
3481                 break;
3482         case 0:
3483                 filter_info->proto_mask = 1;
3484                 break;
3485         default:
3486                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3487                 return -EINVAL;
3488         }
3489
3490         filter_info->priority = (uint8_t)filter->priority;
3491         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3492                 filter_info->tcp_flags = filter->tcp_flags;
3493         else
3494                 filter_info->tcp_flags = 0;
3495
3496         return 0;
3497 }
3498
3499 static inline struct e1000_5tuple_filter *
3500 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3501                         struct e1000_5tuple_filter_info *key)
3502 {
3503         struct e1000_5tuple_filter *it;
3504
3505         TAILQ_FOREACH(it, filter_list, entries) {
3506                 if (memcmp(key, &it->filter_info,
3507                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3508                         return it;
3509                 }
3510         }
3511         return NULL;
3512 }
3513
3514 /*
3515  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3516  *
3517  * @param
3518  * dev: Pointer to struct rte_eth_dev.
3519  * ntuple_filter: ponter to the filter that will be added.
3520  *
3521  * @return
3522  *    - On success, zero.
3523  *    - On failure, a negative value.
3524  */
3525 static int
3526 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3527                         struct rte_eth_ntuple_filter *ntuple_filter)
3528 {
3529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3530         struct e1000_filter_info *filter_info =
3531                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3532         struct e1000_5tuple_filter *filter;
3533         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3534         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3535         uint8_t i;
3536         int ret;
3537
3538         filter = rte_zmalloc("e1000_5tuple_filter",
3539                         sizeof(struct e1000_5tuple_filter), 0);
3540         if (filter == NULL)
3541                 return -ENOMEM;
3542
3543         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3544                                             &filter->filter_info);
3545         if (ret < 0) {
3546                 rte_free(filter);
3547                 return ret;
3548         }
3549
3550         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3551                                          &filter->filter_info) != NULL) {
3552                 PMD_DRV_LOG(ERR, "filter exists.");
3553                 rte_free(filter);
3554                 return -EEXIST;
3555         }
3556         filter->queue = ntuple_filter->queue;
3557
3558         /*
3559          * look for an unused 5tuple filter index,
3560          * and insert the filter to list.
3561          */
3562         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3563                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3564                         filter_info->fivetuple_mask |= 1 << i;
3565                         filter->index = i;
3566                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3567                                           filter,
3568                                           entries);
3569                         break;
3570                 }
3571         }
3572         if (i >= E1000_MAX_FTQF_FILTERS) {
3573                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3574                 rte_free(filter);
3575                 return -ENOSYS;
3576         }
3577
3578         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3579         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3580                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3581         if (filter->filter_info.dst_ip_mask == 0)
3582                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3583         if (filter->filter_info.src_port_mask == 0)
3584                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3585         if (filter->filter_info.proto_mask == 0)
3586                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3587         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3588                 E1000_FTQF_QUEUE_MASK;
3589         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3590         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3591         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3592         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3593
3594         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3595         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3596
3597         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3598         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3599                 imir |= E1000_IMIR_PORT_BP;
3600         else
3601                 imir &= ~E1000_IMIR_PORT_BP;
3602         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3603
3604         /* tcp flags bits setting. */
3605         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3606                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3607                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3608                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3609                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3610                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3611                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3612                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3613                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3614                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3615                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3616                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3617                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3618         } else
3619                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3620         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3621         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3622         return 0;
3623 }
3624
3625 /*
3626  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3627  *
3628  * @param
3629  * dev: Pointer to struct rte_eth_dev.
3630  * ntuple_filter: ponter to the filter that will be removed.
3631  *
3632  * @return
3633  *    - On success, zero.
3634  *    - On failure, a negative value.
3635  */
3636 static int
3637 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3638                                 struct rte_eth_ntuple_filter *ntuple_filter)
3639 {
3640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         struct e1000_filter_info *filter_info =
3642                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3643         struct e1000_5tuple_filter_info filter_5tuple;
3644         struct e1000_5tuple_filter *filter;
3645         int ret;
3646
3647         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3648         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3649                                             &filter_5tuple);
3650         if (ret < 0)
3651                 return ret;
3652
3653         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3654                                          &filter_5tuple);
3655         if (filter == NULL) {
3656                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3657                 return -ENOENT;
3658         }
3659
3660         filter_info->fivetuple_mask &= ~(1 << filter->index);
3661         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3662         rte_free(filter);
3663
3664         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3665                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3666         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3667         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3668         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3669         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3670         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3671         return 0;
3672 }
3673
3674 static int
3675 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3676 {
3677         uint32_t rctl;
3678         struct e1000_hw *hw;
3679         struct rte_eth_dev_info dev_info;
3680         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3681                                      VLAN_TAG_SIZE);
3682
3683         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684
3685 #ifdef RTE_LIBRTE_82571_SUPPORT
3686         /* XXX: not bigger than max_rx_pktlen */
3687         if (hw->mac.type == e1000_82571)
3688                 return -ENOTSUP;
3689 #endif
3690         eth_igb_infos_get(dev, &dev_info);
3691
3692         /* check that mtu is within the allowed range */
3693         if ((mtu < ETHER_MIN_MTU) ||
3694             (frame_size > dev_info.max_rx_pktlen))
3695                 return -EINVAL;
3696
3697         /* refuse mtu that requires the support of scattered packets when this
3698          * feature has not been enabled before. */
3699         if (!dev->data->scattered_rx &&
3700             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3701                 return -EINVAL;
3702
3703         rctl = E1000_READ_REG(hw, E1000_RCTL);
3704
3705         /* switch to jumbo mode if needed */
3706         if (frame_size > ETHER_MAX_LEN) {
3707                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3708                 rctl |= E1000_RCTL_LPE;
3709         } else {
3710                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3711                 rctl &= ~E1000_RCTL_LPE;
3712         }
3713         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3714
3715         /* update max frame size */
3716         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3717
3718         E1000_WRITE_REG(hw, E1000_RLPML,
3719                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3720
3721         return 0;
3722 }
3723
3724 /*
3725  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3726  *
3727  * @param
3728  * dev: Pointer to struct rte_eth_dev.
3729  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3730  * add: if true, add filter, if false, remove filter
3731  *
3732  * @return
3733  *    - On success, zero.
3734  *    - On failure, a negative value.
3735  */
3736 static int
3737 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3738                         struct rte_eth_ntuple_filter *ntuple_filter,
3739                         bool add)
3740 {
3741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3742         int ret;
3743
3744         switch (ntuple_filter->flags) {
3745         case RTE_5TUPLE_FLAGS:
3746         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3747                 if (hw->mac.type != e1000_82576)
3748                         return -ENOTSUP;
3749                 if (add)
3750                         ret = igb_add_5tuple_filter_82576(dev,
3751                                                           ntuple_filter);
3752                 else
3753                         ret = igb_remove_5tuple_filter_82576(dev,
3754                                                              ntuple_filter);
3755                 break;
3756         case RTE_2TUPLE_FLAGS:
3757         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3758                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3759                         return -ENOTSUP;
3760                 if (add)
3761                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3762                 else
3763                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3764                 break;
3765         default:
3766                 ret = -EINVAL;
3767                 break;
3768         }
3769
3770         return ret;
3771 }
3772
3773 /*
3774  * igb_get_ntuple_filter - get a ntuple filter
3775  *
3776  * @param
3777  * dev: Pointer to struct rte_eth_dev.
3778  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3779  *
3780  * @return
3781  *    - On success, zero.
3782  *    - On failure, a negative value.
3783  */
3784 static int
3785 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3786                         struct rte_eth_ntuple_filter *ntuple_filter)
3787 {
3788         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789         struct e1000_filter_info *filter_info =
3790                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3791         struct e1000_5tuple_filter_info filter_5tuple;
3792         struct e1000_2tuple_filter_info filter_2tuple;
3793         struct e1000_5tuple_filter *p_5tuple_filter;
3794         struct e1000_2tuple_filter *p_2tuple_filter;
3795         int ret;
3796
3797         switch (ntuple_filter->flags) {
3798         case RTE_5TUPLE_FLAGS:
3799         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3800                 if (hw->mac.type != e1000_82576)
3801                         return -ENOTSUP;
3802                 memset(&filter_5tuple,
3803                         0,
3804                         sizeof(struct e1000_5tuple_filter_info));
3805                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3806                                                     &filter_5tuple);
3807                 if (ret < 0)
3808                         return ret;
3809                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3810                                         &filter_info->fivetuple_list,
3811                                         &filter_5tuple);
3812                 if (p_5tuple_filter == NULL) {
3813                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3814                         return -ENOENT;
3815                 }
3816                 ntuple_filter->queue = p_5tuple_filter->queue;
3817                 break;
3818         case RTE_2TUPLE_FLAGS:
3819         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3820                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3821                         return -ENOTSUP;
3822                 memset(&filter_2tuple,
3823                         0,
3824                         sizeof(struct e1000_2tuple_filter_info));
3825                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3826                 if (ret < 0)
3827                         return ret;
3828                 p_2tuple_filter = igb_2tuple_filter_lookup(
3829                                         &filter_info->twotuple_list,
3830                                         &filter_2tuple);
3831                 if (p_2tuple_filter == NULL) {
3832                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3833                         return -ENOENT;
3834                 }
3835                 ntuple_filter->queue = p_2tuple_filter->queue;
3836                 break;
3837         default:
3838                 ret = -EINVAL;
3839                 break;
3840         }
3841
3842         return 0;
3843 }
3844
3845 /*
3846  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3847  * @dev: pointer to rte_eth_dev structure
3848  * @filter_op:operation will be taken.
3849  * @arg: a pointer to specific structure corresponding to the filter_op
3850  */
3851 static int
3852 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3853                                 enum rte_filter_op filter_op,
3854                                 void *arg)
3855 {
3856         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857         int ret;
3858
3859         MAC_TYPE_FILTER_SUP(hw->mac.type);
3860
3861         if (filter_op == RTE_ETH_FILTER_NOP)
3862                 return 0;
3863
3864         if (arg == NULL) {
3865                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3866                             filter_op);
3867                 return -EINVAL;
3868         }
3869
3870         switch (filter_op) {
3871         case RTE_ETH_FILTER_ADD:
3872                 ret = igb_add_del_ntuple_filter(dev,
3873                         (struct rte_eth_ntuple_filter *)arg,
3874                         TRUE);
3875                 break;
3876         case RTE_ETH_FILTER_DELETE:
3877                 ret = igb_add_del_ntuple_filter(dev,
3878                         (struct rte_eth_ntuple_filter *)arg,
3879                         FALSE);
3880                 break;
3881         case RTE_ETH_FILTER_GET:
3882                 ret = igb_get_ntuple_filter(dev,
3883                         (struct rte_eth_ntuple_filter *)arg);
3884                 break;
3885         default:
3886                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3887                 ret = -EINVAL;
3888                 break;
3889         }
3890         return ret;
3891 }
3892
3893 static inline int
3894 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3895                         uint16_t ethertype)
3896 {
3897         int i;
3898
3899         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3900                 if (filter_info->ethertype_filters[i] == ethertype &&
3901                     (filter_info->ethertype_mask & (1 << i)))
3902                         return i;
3903         }
3904         return -1;
3905 }
3906
3907 static inline int
3908 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3909                         uint16_t ethertype)
3910 {
3911         int i;
3912
3913         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3914                 if (!(filter_info->ethertype_mask & (1 << i))) {
3915                         filter_info->ethertype_mask |= 1 << i;
3916                         filter_info->ethertype_filters[i] = ethertype;
3917                         return i;
3918                 }
3919         }
3920         return -1;
3921 }
3922
3923 static inline int
3924 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3925                         uint8_t idx)
3926 {
3927         if (idx >= E1000_MAX_ETQF_FILTERS)
3928                 return -1;
3929         filter_info->ethertype_mask &= ~(1 << idx);
3930         filter_info->ethertype_filters[idx] = 0;
3931         return idx;
3932 }
3933
3934
3935 static int
3936 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3937                         struct rte_eth_ethertype_filter *filter,
3938                         bool add)
3939 {
3940         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941         struct e1000_filter_info *filter_info =
3942                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3943         uint32_t etqf = 0;
3944         int ret;
3945
3946         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3947                 filter->ether_type == ETHER_TYPE_IPv6) {
3948                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3949                         " ethertype filter.", filter->ether_type);
3950                 return -EINVAL;
3951         }
3952
3953         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3954                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3955                 return -EINVAL;
3956         }
3957         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3958                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3959                 return -EINVAL;
3960         }
3961
3962         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
3963         if (ret >= 0 && add) {
3964                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3965                             filter->ether_type);
3966                 return -EEXIST;
3967         }
3968         if (ret < 0 && !add) {
3969                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3970                             filter->ether_type);
3971                 return -ENOENT;
3972         }
3973
3974         if (add) {
3975                 ret = igb_ethertype_filter_insert(filter_info,
3976                         filter->ether_type);
3977                 if (ret < 0) {
3978                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3979                         return -ENOSYS;
3980                 }
3981
3982                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
3983                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
3984                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
3985         } else {
3986                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
3987                 if (ret < 0)
3988                         return -ENOSYS;
3989         }
3990         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
3991         E1000_WRITE_FLUSH(hw);
3992
3993         return 0;
3994 }
3995
3996 static int
3997 igb_get_ethertype_filter(struct rte_eth_dev *dev,
3998                         struct rte_eth_ethertype_filter *filter)
3999 {
4000         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4001         struct e1000_filter_info *filter_info =
4002                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4003         uint32_t etqf;
4004         int ret;
4005
4006         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4007         if (ret < 0) {
4008                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4009                             filter->ether_type);
4010                 return -ENOENT;
4011         }
4012
4013         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4014         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4015                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4016                 filter->flags = 0;
4017                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4018                                 E1000_ETQF_QUEUE_SHIFT;
4019                 return 0;
4020         }
4021
4022         return -ENOENT;
4023 }
4024
4025 /*
4026  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4027  * @dev: pointer to rte_eth_dev structure
4028  * @filter_op:operation will be taken.
4029  * @arg: a pointer to specific structure corresponding to the filter_op
4030  */
4031 static int
4032 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4033                                 enum rte_filter_op filter_op,
4034                                 void *arg)
4035 {
4036         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037         int ret;
4038
4039         MAC_TYPE_FILTER_SUP(hw->mac.type);
4040
4041         if (filter_op == RTE_ETH_FILTER_NOP)
4042                 return 0;
4043
4044         if (arg == NULL) {
4045                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4046                             filter_op);
4047                 return -EINVAL;
4048         }
4049
4050         switch (filter_op) {
4051         case RTE_ETH_FILTER_ADD:
4052                 ret = igb_add_del_ethertype_filter(dev,
4053                         (struct rte_eth_ethertype_filter *)arg,
4054                         TRUE);
4055                 break;
4056         case RTE_ETH_FILTER_DELETE:
4057                 ret = igb_add_del_ethertype_filter(dev,
4058                         (struct rte_eth_ethertype_filter *)arg,
4059                         FALSE);
4060                 break;
4061         case RTE_ETH_FILTER_GET:
4062                 ret = igb_get_ethertype_filter(dev,
4063                         (struct rte_eth_ethertype_filter *)arg);
4064                 break;
4065         default:
4066                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4067                 ret = -EINVAL;
4068                 break;
4069         }
4070         return ret;
4071 }
4072
4073 static int
4074 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4075                      enum rte_filter_type filter_type,
4076                      enum rte_filter_op filter_op,
4077                      void *arg)
4078 {
4079         int ret = -EINVAL;
4080
4081         switch (filter_type) {
4082         case RTE_ETH_FILTER_NTUPLE:
4083                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4084                 break;
4085         case RTE_ETH_FILTER_ETHERTYPE:
4086                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4087                 break;
4088         case RTE_ETH_FILTER_SYN:
4089                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4090                 break;
4091         case RTE_ETH_FILTER_FLEXIBLE:
4092                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4093                 break;
4094         default:
4095                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4096                                                         filter_type);
4097                 break;
4098         }
4099
4100         return ret;
4101 }
4102
4103 static int
4104 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4105                          struct ether_addr *mc_addr_set,
4106                          uint32_t nb_mc_addr)
4107 {
4108         struct e1000_hw *hw;
4109
4110         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4111         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4112         return 0;
4113 }
4114
4115 static int
4116 igb_timesync_enable(struct rte_eth_dev *dev)
4117 {
4118         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4119         uint32_t tsync_ctl;
4120         uint32_t tsauxc;
4121
4122         /* Enable system time for it isn't on by default. */
4123         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4124         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4125         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4126
4127         /* Start incrementing the register used to timestamp PTP packets. */
4128         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4129
4130         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4131         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4132                         (ETHER_TYPE_1588 |
4133                          E1000_ETQF_FILTER_ENABLE |
4134                          E1000_ETQF_1588));
4135
4136         /* Enable timestamping of received PTP packets. */
4137         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4138         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4139         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4140
4141         /* Enable Timestamping of transmitted PTP packets. */
4142         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4143         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4144         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4145
4146         return 0;
4147 }
4148
4149 static int
4150 igb_timesync_disable(struct rte_eth_dev *dev)
4151 {
4152         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153         uint32_t tsync_ctl;
4154
4155         /* Disable timestamping of transmitted PTP packets. */
4156         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4157         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4158         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4159
4160         /* Disable timestamping of received PTP packets. */
4161         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4162         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4163         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4164
4165         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4166         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4167
4168         /* Stop incrementating the System Time registers. */
4169         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4170
4171         return 0;
4172 }
4173
4174 static int
4175 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4176                                struct timespec *timestamp,
4177                                uint32_t flags __rte_unused)
4178 {
4179         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         uint32_t tsync_rxctl;
4181         uint32_t rx_stmpl;
4182         uint32_t rx_stmph;
4183
4184         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4185         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4186                 return -EINVAL;
4187
4188         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4189         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4190
4191         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4192         timestamp->tv_nsec = 0;
4193
4194         return  0;
4195 }
4196
4197 static int
4198 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4199                                struct timespec *timestamp)
4200 {
4201         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         uint32_t tsync_txctl;
4203         uint32_t tx_stmpl;
4204         uint32_t tx_stmph;
4205
4206         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4207         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4208                 return -EINVAL;
4209
4210         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4211         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4212
4213         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4214         timestamp->tv_nsec = 0;
4215
4216         return  0;
4217 }
4218
4219 static int
4220 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4221 {
4222         int count = 0;
4223         int g_ind = 0;
4224         const struct reg_info *reg_group;
4225
4226         while ((reg_group = igb_regs[g_ind++]))
4227                 count += igb_reg_group_count(reg_group);
4228
4229         return count;
4230 }
4231
4232 static int
4233 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4234 {
4235         int count = 0;
4236         int g_ind = 0;
4237         const struct reg_info *reg_group;
4238
4239         while ((reg_group = igbvf_regs[g_ind++]))
4240                 count += igb_reg_group_count(reg_group);
4241
4242         return count;
4243 }
4244
4245 static int
4246 eth_igb_get_regs(struct rte_eth_dev *dev,
4247         struct rte_dev_reg_info *regs)
4248 {
4249         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4250         uint32_t *data = regs->data;
4251         int g_ind = 0;
4252         int count = 0;
4253         const struct reg_info *reg_group;
4254
4255         /* Support only full register dump */
4256         if ((regs->length == 0) ||
4257             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4258                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4259                         hw->device_id;
4260                 while ((reg_group = igb_regs[g_ind++]))
4261                         count += igb_read_regs_group(dev, &data[count],
4262                                                         reg_group);
4263                 return 0;
4264         }
4265
4266         return -ENOTSUP;
4267 }
4268
4269 static int
4270 igbvf_get_regs(struct rte_eth_dev *dev,
4271         struct rte_dev_reg_info *regs)
4272 {
4273         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274         uint32_t *data = regs->data;
4275         int g_ind = 0;
4276         int count = 0;
4277         const struct reg_info *reg_group;
4278
4279         /* Support only full register dump */
4280         if ((regs->length == 0) ||
4281             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4282                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4283                         hw->device_id;
4284                 while ((reg_group = igbvf_regs[g_ind++]))
4285                         count += igb_read_regs_group(dev, &data[count],
4286                                                         reg_group);
4287                 return 0;
4288         }
4289
4290         return -ENOTSUP;
4291 }
4292
4293 static int
4294 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4295 {
4296         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4297
4298         /* Return unit is byte count */
4299         return hw->nvm.word_size * 2;
4300 }
4301
4302 static int
4303 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4304         struct rte_dev_eeprom_info *in_eeprom)
4305 {
4306         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4307         struct e1000_nvm_info *nvm = &hw->nvm;
4308         uint16_t *data = in_eeprom->data;
4309         int first, length;
4310
4311         first = in_eeprom->offset >> 1;
4312         length = in_eeprom->length >> 1;
4313         if ((first >= hw->nvm.word_size) ||
4314             ((first + length) >= hw->nvm.word_size))
4315                 return -EINVAL;
4316
4317         in_eeprom->magic = hw->vendor_id |
4318                 ((uint32_t)hw->device_id << 16);
4319
4320         if ((nvm->ops.read) == NULL)
4321                 return -ENOTSUP;
4322
4323         return nvm->ops.read(hw, first, length, data);
4324 }
4325
4326 static int
4327 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4328         struct rte_dev_eeprom_info *in_eeprom)
4329 {
4330         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4331         struct e1000_nvm_info *nvm = &hw->nvm;
4332         uint16_t *data = in_eeprom->data;
4333         int first, length;
4334
4335         first = in_eeprom->offset >> 1;
4336         length = in_eeprom->length >> 1;
4337         if ((first >= hw->nvm.word_size) ||
4338             ((first + length) >= hw->nvm.word_size))
4339                 return -EINVAL;
4340
4341         in_eeprom->magic = (uint32_t)hw->vendor_id |
4342                 ((uint32_t)hw->device_id << 16);
4343
4344         if ((nvm->ops.write) == NULL)
4345                 return -ENOTSUP;
4346         return nvm->ops.write(hw,  first, length, data);
4347 }
4348
4349 static struct rte_driver pmd_igb_drv = {
4350         .type = PMD_PDEV,
4351         .init = rte_igb_pmd_init,
4352 };
4353
4354 static struct rte_driver pmd_igbvf_drv = {
4355         .type = PMD_PDEV,
4356         .init = rte_igbvf_pmd_init,
4357 };
4358
4359 static int
4360 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4361 {
4362         struct e1000_hw *hw =
4363                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4364         uint32_t mask = 1 << queue_id;
4365
4366         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4367         E1000_WRITE_FLUSH(hw);
4368
4369         return 0;
4370 }
4371
4372 static int
4373 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4374 {
4375         struct e1000_hw *hw =
4376                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         uint32_t mask = 1 << queue_id;
4378         uint32_t regval;
4379
4380         regval = E1000_READ_REG(hw, E1000_EIMS);
4381         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4382         E1000_WRITE_FLUSH(hw);
4383
4384         rte_intr_enable(&dev->pci_dev->intr_handle);
4385
4386         return 0;
4387 }
4388
4389 static void
4390 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4391                    uint8_t index, uint8_t offset)
4392 {
4393         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4394
4395         /* clear bits */
4396         val &= ~((uint32_t)0xFF << offset);
4397
4398         /* write vector and valid bit */
4399         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4400
4401         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4402 }
4403
4404 static void
4405 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4406                            uint8_t queue, uint8_t msix_vector)
4407 {
4408         uint32_t tmp = 0;
4409
4410         if (hw->mac.type == e1000_82575) {
4411                 if (direction == 0)
4412                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4413                 else if (direction == 1)
4414                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4415                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4416         } else if (hw->mac.type == e1000_82576) {
4417                 if ((direction == 0) || (direction == 1))
4418                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4419                                            ((queue & 0x8) << 1) +
4420                                            8 * direction);
4421         } else if ((hw->mac.type == e1000_82580) ||
4422                         (hw->mac.type == e1000_i350) ||
4423                         (hw->mac.type == e1000_i354) ||
4424                         (hw->mac.type == e1000_i210) ||
4425                         (hw->mac.type == e1000_i211)) {
4426                 if ((direction == 0) || (direction == 1))
4427                         eth_igb_write_ivar(hw, msix_vector,
4428                                            queue >> 1,
4429                                            ((queue & 0x1) << 4) +
4430                                            8 * direction);
4431         }
4432 }
4433
4434 /* Sets up the hardware to generate MSI-X interrupts properly
4435  * @hw
4436  *  board private structure
4437  */
4438 static void
4439 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4440 {
4441         int queue_id;
4442         uint32_t tmpval, regval, intr_mask;
4443         struct e1000_hw *hw =
4444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445         uint32_t vec = 0;
4446         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4447
4448         /* won't configure msix register if no mapping is done
4449          * between intr vector and event fd
4450          */
4451         if (!rte_intr_dp_is_en(intr_handle))
4452                 return;
4453
4454         /* set interrupt vector for other causes */
4455         if (hw->mac.type == e1000_82575) {
4456                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4457                 /* enable MSI-X PBA support */
4458                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4459
4460                 /* Auto-Mask interrupts upon ICR read */
4461                 tmpval |= E1000_CTRL_EXT_EIAME;
4462                 tmpval |= E1000_CTRL_EXT_IRCA;
4463
4464                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4465
4466                 /* enable msix_other interrupt */
4467                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4468                 regval = E1000_READ_REG(hw, E1000_EIAC);
4469                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4470                 regval = E1000_READ_REG(hw, E1000_EIAM);
4471                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4472         } else if ((hw->mac.type == e1000_82576) ||
4473                         (hw->mac.type == e1000_82580) ||
4474                         (hw->mac.type == e1000_i350) ||
4475                         (hw->mac.type == e1000_i354) ||
4476                         (hw->mac.type == e1000_i210) ||
4477                         (hw->mac.type == e1000_i211)) {
4478                 /* turn on MSI-X capability first */
4479                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4480                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4481                                         E1000_GPIE_NSICR);
4482
4483                 intr_mask = (1 << intr_handle->max_intr) - 1;
4484                 regval = E1000_READ_REG(hw, E1000_EIAC);
4485                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4486
4487                 /* enable msix_other interrupt */
4488                 regval = E1000_READ_REG(hw, E1000_EIMS);
4489                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4490                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4491                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4492         }
4493
4494         /* use EIAM to auto-mask when MSI-X interrupt
4495          * is asserted, this saves a register write for every interrupt
4496          */
4497         intr_mask = (1 << intr_handle->nb_efd) - 1;
4498         regval = E1000_READ_REG(hw, E1000_EIAM);
4499         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4500
4501         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4502                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4503                 intr_handle->intr_vec[queue_id] = vec;
4504                 if (vec < intr_handle->nb_efd - 1)
4505                         vec++;
4506         }
4507
4508         E1000_WRITE_FLUSH(hw);
4509 }
4510
4511 PMD_REGISTER_DRIVER(pmd_igb_drv);
4512 PMD_REGISTER_DRIVER(pmd_igbvf_drv);