drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 static int  eth_igb_configure(struct rte_eth_dev *dev);
  90 static int  eth_igb_start(struct rte_eth_dev *dev);
  91 static void eth_igb_stop(struct rte_eth_dev *dev);
  92 static void eth_igb_close(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  96 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  97 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  98                                 int wait_to_complete);
  99 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 100                                 struct rte_eth_stats *rte_stats);
 101 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 102                               struct rte_eth_xstats *xstats, unsigned n);
 103 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 105 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 106                               struct rte_eth_dev_info *dev_info);
 107 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 112                                 struct rte_eth_fc_conf *fc_conf);
 113 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 116 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 117 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 118                                                         void *param);
 119 static int  igb_hardware_init(struct e1000_hw *hw);
 120 static void igb_hw_control_acquire(struct e1000_hw *hw);
 121 static void igb_hw_control_release(struct e1000_hw *hw);
 122 static void igb_init_manageability(struct e1000_hw *hw);
 123 static void igb_release_manageability(struct e1000_hw *hw);
 124
 125 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 126
 127 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 128                 uint16_t vlan_id, int on);
 129 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 130                                  enum rte_vlan_type vlan_type,
 131                                  uint16_t tpid_id);
 132 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 133
 134 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 139 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 140
 141 static int eth_igb_led_on(struct rte_eth_dev *dev);
 142 static int eth_igb_led_off(struct rte_eth_dev *dev);
 143
 144 static void igb_intr_disable(struct e1000_hw *hw);
 145 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 146 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *mac_addr,
 148                 uint32_t index, uint32_t pool);
 149 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 150 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 151                 struct ether_addr *addr);
 152
 153 static void igbvf_intr_disable(struct e1000_hw *hw);
 154 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 155 static int igbvf_dev_start(struct rte_eth_dev *dev);
 156 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 157 static void igbvf_dev_close(struct rte_eth_dev *dev);
 158 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 159 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 160 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 161 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 162 static int eth_igbvf_link_update(struct e1000_hw *hw);
 163 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 164                                 struct rte_eth_stats *rte_stats);
 165 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 166                                 struct rte_eth_xstats *xstats, unsigned n);
 167 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 168 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 169                 uint16_t vlan_id, int on);
 170 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 171 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 172 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 173                 struct ether_addr *addr);
 174 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 175 static int igbvf_get_regs(struct rte_eth_dev *dev,
 176                 struct rte_dev_reg_info *regs);
 177
 178 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 179                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 180                                    uint16_t reta_size);
 181 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 182                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 183                                   uint16_t reta_size);
 184
 185 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 186                         struct rte_eth_syn_filter *filter,
 187                         bool add);
 188 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 189                         struct rte_eth_syn_filter *filter);
 190 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 191                         enum rte_filter_op filter_op,
 192                         void *arg);
 193 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_ntuple_filter *ntuple_filter);
 197 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 198                         struct rte_eth_flex_filter *filter,
 199                         bool add);
 200 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 201                         struct rte_eth_flex_filter *filter);
 202 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 203                         enum rte_filter_op filter_op,
 204                         void *arg);
 205 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *ntuple_filter);
 207 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 208                         struct rte_eth_ntuple_filter *ntuple_filter);
 209 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ntuple_filter *filter,
 211                         bool add);
 212 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 213                         struct rte_eth_ntuple_filter *filter);
 214 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 215                                 enum rte_filter_op filter_op,
 216                                 void *arg);
 217 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_ethertype_filter *filter,
 219                         bool add);
 220 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 221                                 enum rte_filter_op filter_op,
 222                                 void *arg);
 223 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 224                         struct rte_eth_ethertype_filter *filter);
 225 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 226                      enum rte_filter_type filter_type,
 227                      enum rte_filter_op filter_op,
 228                      void *arg);
 229 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 230 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 231                 struct rte_dev_reg_info *regs);
 232 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 233 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 234                 struct rte_dev_eeprom_info *eeprom);
 235 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 236                 struct rte_dev_eeprom_info *eeprom);
 237 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 238                                     struct ether_addr *mc_addr_set,
 239                                     uint32_t nb_mc_addr);
 240 static int igb_timesync_enable(struct rte_eth_dev *dev);
 241 static int igb_timesync_disable(struct rte_eth_dev *dev);
 242 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 243                                           struct timespec *timestamp,
 244                                           uint32_t flags);
 245 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 246                                           struct timespec *timestamp);
 247 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 248 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 249                                   struct timespec *timestamp);
 250 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 251                                    const struct timespec *timestamp);
 252 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 253                                         uint16_t queue_id);
 254 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 255                                          uint16_t queue_id);
 256 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 257                                        uint8_t queue, uint8_t msix_vector);
 258 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 259                                uint8_t index, uint8_t offset);
 260 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 261
 262 /*
 263  * Define VF Stats MACRO for Non "cleared on read" register
 264  */
 265 #define UPDATE_VF_STAT(reg, last, cur)            \
 266 {                                                 \
 267         u32 latest = E1000_READ_REG(hw, reg);     \
 268         cur += (latest - last) & UINT_MAX;        \
 269         last = latest;                            \
 270 }
 271
 272 #define IGB_FC_PAUSE_TIME 0x0680
 273 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 274 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 275
 276 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 277
 278 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 279
 280 /*
 281  * The set of PCI devices this driver supports
 282  */
 283 static const struct rte_pci_id pci_id_igb_map[] = {
 284
 285 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 286 #include "rte_pci_dev_ids.h"
 287
 288 {0},
 289 };
 290
 291 /*
 292  * The set of PCI devices this driver supports (for 82576&I350 VF)
 293  */
 294 static const struct rte_pci_id pci_id_igbvf_map[] = {
 295
 296 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 297 #include "rte_pci_dev_ids.h"
 298
 299 {0},
 300 };
 301
 302 static const struct rte_eth_desc_lim rx_desc_lim = {
 303         .nb_max = E1000_MAX_RING_DESC,
 304         .nb_min = E1000_MIN_RING_DESC,
 305         .nb_align = IGB_RXD_ALIGN,
 306 };
 307
 308 static const struct rte_eth_desc_lim tx_desc_lim = {
 309         .nb_max = E1000_MAX_RING_DESC,
 310         .nb_min = E1000_MIN_RING_DESC,
 311         .nb_align = IGB_RXD_ALIGN,
 312 };
 313
 314 static const struct eth_dev_ops eth_igb_ops = {
 315         .dev_configure        = eth_igb_configure,
 316         .dev_start            = eth_igb_start,
 317         .dev_stop             = eth_igb_stop,
 318         .dev_close            = eth_igb_close,
 319         .promiscuous_enable   = eth_igb_promiscuous_enable,
 320         .promiscuous_disable  = eth_igb_promiscuous_disable,
 321         .allmulticast_enable  = eth_igb_allmulticast_enable,
 322         .allmulticast_disable = eth_igb_allmulticast_disable,
 323         .link_update          = eth_igb_link_update,
 324         .stats_get            = eth_igb_stats_get,
 325         .xstats_get           = eth_igb_xstats_get,
 326         .stats_reset          = eth_igb_stats_reset,
 327         .xstats_reset         = eth_igb_xstats_reset,
 328         .dev_infos_get        = eth_igb_infos_get,
 329         .mtu_set              = eth_igb_mtu_set,
 330         .vlan_filter_set      = eth_igb_vlan_filter_set,
 331         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 332         .vlan_offload_set     = eth_igb_vlan_offload_set,
 333         .rx_queue_setup       = eth_igb_rx_queue_setup,
 334         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 335         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 336         .rx_queue_release     = eth_igb_rx_queue_release,
 337         .rx_queue_count       = eth_igb_rx_queue_count,
 338         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 339         .tx_queue_setup       = eth_igb_tx_queue_setup,
 340         .tx_queue_release     = eth_igb_tx_queue_release,
 341         .dev_led_on           = eth_igb_led_on,
 342         .dev_led_off          = eth_igb_led_off,
 343         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 344         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 345         .mac_addr_add         = eth_igb_rar_set,
 346         .mac_addr_remove      = eth_igb_rar_clear,
 347         .mac_addr_set         = eth_igb_default_mac_addr_set,
 348         .reta_update          = eth_igb_rss_reta_update,
 349         .reta_query           = eth_igb_rss_reta_query,
 350         .rss_hash_update      = eth_igb_rss_hash_update,
 351         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 352         .filter_ctrl          = eth_igb_filter_ctrl,
 353         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 354         .rxq_info_get         = igb_rxq_info_get,
 355         .txq_info_get         = igb_txq_info_get,
 356         .timesync_enable      = igb_timesync_enable,
 357         .timesync_disable     = igb_timesync_disable,
 358         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 359         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 360         .get_reg_length       = eth_igb_get_reg_length,
 361         .get_reg              = eth_igb_get_regs,
 362         .get_eeprom_length    = eth_igb_get_eeprom_length,
 363         .get_eeprom           = eth_igb_get_eeprom,
 364         .set_eeprom           = eth_igb_set_eeprom,
 365         .timesync_adjust_time = igb_timesync_adjust_time,
 366         .timesync_read_time   = igb_timesync_read_time,
 367         .timesync_write_time  = igb_timesync_write_time,
 368 };
 369
 370 /*
 371  * dev_ops for virtual function, bare necessities for basic vf
 372  * operation have been implemented
 373  */
 374 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 375         .dev_configure        = igbvf_dev_configure,
 376         .dev_start            = igbvf_dev_start,
 377         .dev_stop             = igbvf_dev_stop,
 378         .dev_close            = igbvf_dev_close,
 379         .promiscuous_enable   = igbvf_promiscuous_enable,
 380         .promiscuous_disable  = igbvf_promiscuous_disable,
 381         .allmulticast_enable  = igbvf_allmulticast_enable,
 382         .allmulticast_disable = igbvf_allmulticast_disable,
 383         .link_update          = eth_igb_link_update,
 384         .stats_get            = eth_igbvf_stats_get,
 385         .xstats_get           = eth_igbvf_xstats_get,
 386         .stats_reset          = eth_igbvf_stats_reset,
 387         .xstats_reset         = eth_igbvf_stats_reset,
 388         .vlan_filter_set      = igbvf_vlan_filter_set,
 389         .dev_infos_get        = eth_igbvf_infos_get,
 390         .rx_queue_setup       = eth_igb_rx_queue_setup,
 391         .rx_queue_release     = eth_igb_rx_queue_release,
 392         .tx_queue_setup       = eth_igb_tx_queue_setup,
 393         .tx_queue_release     = eth_igb_tx_queue_release,
 394         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 395         .rxq_info_get         = igb_rxq_info_get,
 396         .txq_info_get         = igb_txq_info_get,
 397         .mac_addr_set         = igbvf_default_mac_addr_set,
 398         .get_reg_length       = igbvf_get_reg_length,
 399         .get_reg              = igbvf_get_regs,
 400 };
 401
 402 /* store statistics names and its offset in stats structure */
 403 struct rte_igb_xstats_name_off {
 404         char name[RTE_ETH_XSTATS_NAME_SIZE];
 405         unsigned offset;
 406 };
 407
 408 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 409         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 410         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 411         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 412         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 413         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 414         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 415         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 416                 ecol)},
 417         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 418         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 419         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 420         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 421         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 422         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 423         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 424         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 425         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 426         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 427         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 428                 fcruc)},
 429         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 430         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 431         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 432         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 433         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 434                 prc1023)},
 435         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 436                 prc1522)},
 437         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 438         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 439         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 440         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 441         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 442         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 443         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 444         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 445         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 446         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 447         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 448         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 449         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 450         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 451         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 452         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 453         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 454         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 455                 ptc1023)},
 456         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 457                 ptc1522)},
 458         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 459         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 460         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 461         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 462         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 463         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 464         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 465
 466         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 467 };
 468
 469 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 470                 sizeof(rte_igb_stats_strings[0]))
 471
 472 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 473         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 474         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 475         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 476         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 477         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 478 };
 479
 480 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 481                 sizeof(rte_igbvf_stats_strings[0]))
 482
 483 /**
 484  * Atomically reads the link status information from global
 485  * structure rte_eth_dev.
 486  *
 487  * @param dev
 488  *   - Pointer to the structure rte_eth_dev to read from.
 489  *   - Pointer to the buffer to be saved with the link status.
 490  *
 491  * @return
 492  *   - On success, zero.
 493  *   - On failure, negative value.
 494  */
 495 static inline int
 496 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 497                                 struct rte_eth_link *link)
 498 {
 499         struct rte_eth_link *dst = link;
 500         struct rte_eth_link *src = &(dev->data->dev_link);
 501
 502         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 503                                         *(uint64_t *)src) == 0)
 504                 return -1;
 505
 506         return 0;
 507 }
 508
 509 /**
 510  * Atomically writes the link status information into global
 511  * structure rte_eth_dev.
 512  *
 513  * @param dev
 514  *   - Pointer to the structure rte_eth_dev to read from.
 515  *   - Pointer to the buffer to be saved with the link status.
 516  *
 517  * @return
 518  *   - On success, zero.
 519  *   - On failure, negative value.
 520  */
 521 static inline int
 522 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 523                                 struct rte_eth_link *link)
 524 {
 525         struct rte_eth_link *dst = &(dev->data->dev_link);
 526         struct rte_eth_link *src = link;
 527
 528         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 529                                         *(uint64_t *)src) == 0)
 530                 return -1;
 531
 532         return 0;
 533 }
 534
 535 static inline void
 536 igb_intr_enable(struct rte_eth_dev *dev)
 537 {
 538         struct e1000_interrupt *intr =
 539                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 540         struct e1000_hw *hw =
 541                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 542
 543         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 544         E1000_WRITE_FLUSH(hw);
 545 }
 546
 547 static void
 548 igb_intr_disable(struct e1000_hw *hw)
 549 {
 550         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 551         E1000_WRITE_FLUSH(hw);
 552 }
 553
 554 static inline int32_t
 555 igb_pf_reset_hw(struct e1000_hw *hw)
 556 {
 557         uint32_t ctrl_ext;
 558         int32_t status;
 559
 560         status = e1000_reset_hw(hw);
 561
 562         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 563         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 564         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 565         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 566         E1000_WRITE_FLUSH(hw);
 567
 568         return status;
 569 }
 570
 571 static void
 572 igb_identify_hardware(struct rte_eth_dev *dev)
 573 {
 574         struct e1000_hw *hw =
 575                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 576
 577         hw->vendor_id = dev->pci_dev->id.vendor_id;
 578         hw->device_id = dev->pci_dev->id.device_id;
 579         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 580         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 581
 582         e1000_set_mac_type(hw);
 583
 584         /* need to check if it is a vf device below */
 585 }
 586
 587 static int
 588 igb_reset_swfw_lock(struct e1000_hw *hw)
 589 {
 590         int ret_val;
 591
 592         /*
 593          * Do mac ops initialization manually here, since we will need
 594          * some function pointers set by this call.
 595          */
 596         ret_val = e1000_init_mac_params(hw);
 597         if (ret_val)
 598                 return ret_val;
 599
 600         /*
 601          * SMBI lock should not fail in this early stage. If this is the case,
 602          * it is due to an improper exit of the application.
 603          * So force the release of the faulty lock.
 604          */
 605         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 606                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 607         }
 608         e1000_put_hw_semaphore_generic(hw);
 609
 610         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 611                 uint16_t mask;
 612
 613                 /*
 614                  * Phy lock should not fail in this early stage. If this is the case,
 615                  * it is due to an improper exit of the application.
 616                  * So force the release of the faulty lock.
 617                  */
 618                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 619                 if (hw->bus.func > E1000_FUNC_1)
 620                         mask <<= 2;
 621                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 622                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 623                                     hw->bus.func);
 624                 }
 625                 hw->mac.ops.release_swfw_sync(hw, mask);
 626
 627                 /*
 628                  * This one is more tricky since it is common to all ports; but
 629                  * swfw_sync retries last long enough (1s) to be almost sure that if
 630                  * lock can not be taken it is due to an improper lock of the
 631                  * semaphore.
 632                  */
 633                 mask = E1000_SWFW_EEP_SM;
 634                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 635                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 636                 }
 637                 hw->mac.ops.release_swfw_sync(hw, mask);
 638         }
 639
 640         return E1000_SUCCESS;
 641 }
 642
 643 static int
 644 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 645 {
 646         int error = 0;
 647         struct rte_pci_device *pci_dev;
 648         struct e1000_hw *hw =
 649                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 650         struct e1000_vfta * shadow_vfta =
 651                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 652         struct e1000_filter_info *filter_info =
 653                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 654         struct e1000_adapter *adapter =
 655                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 656
 657         uint32_t ctrl_ext;
 658
 659         pci_dev = eth_dev->pci_dev;
 660
 661         eth_dev->dev_ops = &eth_igb_ops;
 662         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 663         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 664
 665         /* for secondary processes, we don't initialise any further as primary
 666          * has already done this work. Only check we don't need a different
 667          * RX function */
 668         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 669                 if (eth_dev->data->scattered_rx)
 670                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 671                 return 0;
 672         }
 673
 674         rte_eth_copy_pci_info(eth_dev, pci_dev);
 675
 676         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 677
 678         igb_identify_hardware(eth_dev);
 679         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 680                 error = -EIO;
 681                 goto err_late;
 682         }
 683
 684         e1000_get_bus_info(hw);
 685
 686         /* Reset any pending lock */
 687         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 688                 error = -EIO;
 689                 goto err_late;
 690         }
 691
 692         /* Finish initialization */
 693         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 694                 error = -EIO;
 695                 goto err_late;
 696         }
 697
 698         hw->mac.autoneg = 1;
 699         hw->phy.autoneg_wait_to_complete = 0;
 700         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 701
 702         /* Copper options */
 703         if (hw->phy.media_type == e1000_media_type_copper) {
 704                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 705                 hw->phy.disable_polarity_correction = 0;
 706                 hw->phy.ms_type = e1000_ms_hw_default;
 707         }
 708
 709         /*
 710          * Start from a known state, this is important in reading the nvm
 711          * and mac from that.
 712          */
 713         igb_pf_reset_hw(hw);
 714
 715         /* Make sure we have a good EEPROM before we read from it */
 716         if (e1000_validate_nvm_checksum(hw) < 0) {
 717                 /*
 718                  * Some PCI-E parts fail the first check due to
 719                  * the link being in sleep state, call it again,
 720                  * if it fails a second time its a real issue.
 721                  */
 722                 if (e1000_validate_nvm_checksum(hw) < 0) {
 723                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 724                         error = -EIO;
 725                         goto err_late;
 726                 }
 727         }
 728
 729         /* Read the permanent MAC address out of the EEPROM */
 730         if (e1000_read_mac_addr(hw) != 0) {
 731                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 732                 error = -EIO;
 733                 goto err_late;
 734         }
 735
 736         /* Allocate memory for storing MAC addresses */
 737         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 738                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 739         if (eth_dev->data->mac_addrs == NULL) {
 740                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 741                                                 "store MAC addresses",
 742                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 743                 error = -ENOMEM;
 744                 goto err_late;
 745         }
 746
 747         /* Copy the permanent MAC address */
 748         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 749
 750         /* initialize the vfta */
 751         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 752
 753         /* Now initialize the hardware */
 754         if (igb_hardware_init(hw) != 0) {
 755                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 756                 rte_free(eth_dev->data->mac_addrs);
 757                 eth_dev->data->mac_addrs = NULL;
 758                 error = -ENODEV;
 759                 goto err_late;
 760         }
 761         hw->mac.get_link_status = 1;
 762         adapter->stopped = 0;
 763
 764         /* Indicate SOL/IDER usage */
 765         if (e1000_check_reset_block(hw) < 0) {
 766                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 767                                         "SOL/IDER session");
 768         }
 769
 770         /* initialize PF if max_vfs not zero */
 771         igb_pf_host_init(eth_dev);
 772
 773         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 774         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 775         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 776         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 777         E1000_WRITE_FLUSH(hw);
 778
 779         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 780                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 781                      pci_dev->id.device_id);
 782
 783         rte_intr_callback_register(&pci_dev->intr_handle,
 784                                    eth_igb_interrupt_handler,
 785                                    (void *)eth_dev);
 786
 787         /* enable uio/vfio intr/eventfd mapping */
 788         rte_intr_enable(&pci_dev->intr_handle);
 789
 790         /* enable support intr */
 791         igb_intr_enable(eth_dev);
 792
 793         TAILQ_INIT(&filter_info->flex_list);
 794         filter_info->flex_mask = 0;
 795         TAILQ_INIT(&filter_info->twotuple_list);
 796         filter_info->twotuple_mask = 0;
 797         TAILQ_INIT(&filter_info->fivetuple_list);
 798         filter_info->fivetuple_mask = 0;
 799
 800         return 0;
 801
 802 err_late:
 803         igb_hw_control_release(hw);
 804
 805         return error;
 806 }
 807
 808 static int
 809 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 810 {
 811         struct rte_pci_device *pci_dev;
 812         struct e1000_hw *hw;
 813         struct e1000_adapter *adapter =
 814                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 815
 816         PMD_INIT_FUNC_TRACE();
 817
 818         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 819                 return -EPERM;
 820
 821         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 822         pci_dev = eth_dev->pci_dev;
 823
 824         if (adapter->stopped == 0)
 825                 eth_igb_close(eth_dev);
 826
 827         eth_dev->dev_ops = NULL;
 828         eth_dev->rx_pkt_burst = NULL;
 829         eth_dev->tx_pkt_burst = NULL;
 830
 831         /* Reset any pending lock */
 832         igb_reset_swfw_lock(hw);
 833
 834         rte_free(eth_dev->data->mac_addrs);
 835         eth_dev->data->mac_addrs = NULL;
 836
 837         /* uninitialize PF if max_vfs not zero */
 838         igb_pf_host_uninit(eth_dev);
 839
 840         /* disable uio intr before callback unregister */
 841         rte_intr_disable(&(pci_dev->intr_handle));
 842         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 843                 eth_igb_interrupt_handler, (void *)eth_dev);
 844
 845         return 0;
 846 }
 847
 848 /*
 849  * Virtual Function device init
 850  */
 851 static int
 852 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 853 {
 854         struct rte_pci_device *pci_dev;
 855         struct e1000_adapter *adapter =
 856                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 857         struct e1000_hw *hw =
 858                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 859         int diag;
 860         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 861
 862         PMD_INIT_FUNC_TRACE();
 863
 864         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 865         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 866         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 867
 868         /* for secondary processes, we don't initialise any further as primary
 869          * has already done this work. Only check we don't need a different
 870          * RX function */
 871         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 872                 if (eth_dev->data->scattered_rx)
 873                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 874                 return 0;
 875         }
 876
 877         pci_dev = eth_dev->pci_dev;
 878
 879         rte_eth_copy_pci_info(eth_dev, pci_dev);
 880
 881         hw->device_id = pci_dev->id.device_id;
 882         hw->vendor_id = pci_dev->id.vendor_id;
 883         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 884         adapter->stopped = 0;
 885
 886         /* Initialize the shared code (base driver) */
 887         diag = e1000_setup_init_funcs(hw, TRUE);
 888         if (diag != 0) {
 889                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 890                         diag);
 891                 return -EIO;
 892         }
 893
 894         /* init_mailbox_params */
 895         hw->mbx.ops.init_params(hw);
 896
 897         /* Disable the interrupts for VF */
 898         igbvf_intr_disable(hw);
 899
 900         diag = hw->mac.ops.reset_hw(hw);
 901
 902         /* Allocate memory for storing MAC addresses */
 903         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 904                 hw->mac.rar_entry_count, 0);
 905         if (eth_dev->data->mac_addrs == NULL) {
 906                 PMD_INIT_LOG(ERR,
 907                         "Failed to allocate %d bytes needed to store MAC "
 908                         "addresses",
 909                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 910                 return -ENOMEM;
 911         }
 912
 913         /* Generate a random MAC address, if none was assigned by PF. */
 914         if (is_zero_ether_addr(perm_addr)) {
 915                 eth_random_addr(perm_addr->addr_bytes);
 916                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 917                 if (diag) {
 918                         rte_free(eth_dev->data->mac_addrs);
 919                         eth_dev->data->mac_addrs = NULL;
 920                         return diag;
 921                 }
 922                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 923                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 924                              "%02x:%02x:%02x:%02x:%02x:%02x",
 925                              perm_addr->addr_bytes[0],
 926                              perm_addr->addr_bytes[1],
 927                              perm_addr->addr_bytes[2],
 928                              perm_addr->addr_bytes[3],
 929                              perm_addr->addr_bytes[4],
 930                              perm_addr->addr_bytes[5]);
 931         }
 932
 933         /* Copy the permanent MAC address */
 934         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 935                         &eth_dev->data->mac_addrs[0]);
 936
 937         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 938                      "mac.type=%s",
 939                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 940                      pci_dev->id.device_id, "igb_mac_82576_vf");
 941
 942         return 0;
 943 }
 944
 945 static int
 946 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 947 {
 948         struct e1000_adapter *adapter =
 949                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 950
 951         PMD_INIT_FUNC_TRACE();
 952
 953         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 954                 return -EPERM;
 955
 956         if (adapter->stopped == 0)
 957                 igbvf_dev_close(eth_dev);
 958
 959         eth_dev->dev_ops = NULL;
 960         eth_dev->rx_pkt_burst = NULL;
 961         eth_dev->tx_pkt_burst = NULL;
 962
 963         rte_free(eth_dev->data->mac_addrs);
 964         eth_dev->data->mac_addrs = NULL;
 965
 966         return 0;
 967 }
 968
 969 static struct eth_driver rte_igb_pmd = {
 970         .pci_drv = {
 971                 .name = "rte_igb_pmd",
 972                 .id_table = pci_id_igb_map,
 973                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 974                         RTE_PCI_DRV_DETACHABLE,
 975         },
 976         .eth_dev_init = eth_igb_dev_init,
 977         .eth_dev_uninit = eth_igb_dev_uninit,
 978         .dev_private_size = sizeof(struct e1000_adapter),
 979 };
 980
 981 /*
 982  * virtual function driver struct
 983  */
 984 static struct eth_driver rte_igbvf_pmd = {
 985         .pci_drv = {
 986                 .name = "rte_igbvf_pmd",
 987                 .id_table = pci_id_igbvf_map,
 988                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 989         },
 990         .eth_dev_init = eth_igbvf_dev_init,
 991         .eth_dev_uninit = eth_igbvf_dev_uninit,
 992         .dev_private_size = sizeof(struct e1000_adapter),
 993 };
 994
 995 static int
 996 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 997 {
 998         rte_eth_driver_register(&rte_igb_pmd);
 999         return 0;
1000 }
1001
1002 static void
1003 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1004 {
1005         struct e1000_hw *hw =
1006                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1007         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1008         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1009         rctl |= E1000_RCTL_VFE;
1010         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1011 }
1012
1013 /*
1014  * VF Driver initialization routine.
1015  * Invoked one at EAL init time.
1016  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1017  */
1018 static int
1019 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1020 {
1021         PMD_INIT_FUNC_TRACE();
1022
1023         rte_eth_driver_register(&rte_igbvf_pmd);
1024         return 0;
1025 }
1026
1027 static int
1028 igb_check_mq_mode(struct rte_eth_dev *dev)
1029 {
1030         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1031         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1032         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1033         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1034
1035         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1036             tx_mq_mode == ETH_MQ_TX_DCB ||
1037             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1038                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1039                 return -EINVAL;
1040         }
1041         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1042                 /* Check multi-queue mode.
1043                  * To no break software we accept ETH_MQ_RX_NONE as this might
1044                  * be used to turn off VLAN filter.
1045                  */
1046
1047                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1048                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1049                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1050                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1051                 } else {
1052                         /* Only support one queue on VFs.
1053                          * RSS together with SRIOV is not supported.
1054                          */
1055                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1056                                         " wrong mq_mode rx %d.",
1057                                         rx_mq_mode);
1058                         return -EINVAL;
1059                 }
1060                 /* TX mode is not used here, so mode might be ignored.*/
1061                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1062                         /* SRIOV only works in VMDq enable mode */
1063                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1064                                         " TX mode %d is not supported. "
1065                                         " Driver will behave as %d mode.",
1066                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1067                 }
1068
1069                 /* check valid queue number */
1070                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1071                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1072                                         " only support one queue on VFs.");
1073                         return -EINVAL;
1074                 }
1075         } else {
1076                 /* To no break software that set invalid mode, only display
1077                  * warning if invalid mode is used.
1078                  */
1079                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1080                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1081                     rx_mq_mode != ETH_MQ_RX_RSS) {
1082                         /* RSS together with VMDq not supported*/
1083                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1084                                      rx_mq_mode);
1085                         return -EINVAL;
1086                 }
1087
1088                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1089                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1090                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1091                                         " Due to txmode is meaningless in this"
1092                                         " driver, just ignore.",
1093                                         tx_mq_mode);
1094                 }
1095         }
1096         return 0;
1097 }
1098
1099 static int
1100 eth_igb_configure(struct rte_eth_dev *dev)
1101 {
1102         struct e1000_interrupt *intr =
1103                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1104         int ret;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         /* multipe queue mode checking */
1109         ret  = igb_check_mq_mode(dev);
1110         if (ret != 0) {
1111                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1112                             ret);
1113                 return ret;
1114         }
1115
1116         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1117         PMD_INIT_FUNC_TRACE();
1118
1119         return 0;
1120 }
1121
1122 static int
1123 eth_igb_start(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct e1000_adapter *adapter =
1128                 E1000_DEV_PRIVATE(dev->data->dev_private);
1129         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1130         int ret, mask;
1131         uint32_t intr_vector = 0;
1132         uint32_t ctrl_ext;
1133
1134         PMD_INIT_FUNC_TRACE();
1135
1136         /* disable uio/vfio intr/eventfd mapping */
1137         rte_intr_disable(intr_handle);
1138
1139         /* Power up the phy. Needed to make the link go Up */
1140         e1000_power_up_phy(hw);
1141
1142         /*
1143          * Packet Buffer Allocation (PBA)
1144          * Writing PBA sets the receive portion of the buffer
1145          * the remainder is used for the transmit buffer.
1146          */
1147         if (hw->mac.type == e1000_82575) {
1148                 uint32_t pba;
1149
1150                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1151                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1152         }
1153
1154         /* Put the address into the Receive Address Array */
1155         e1000_rar_set(hw, hw->mac.addr, 0);
1156
1157         /* Initialize the hardware */
1158         if (igb_hardware_init(hw)) {
1159                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1160                 return -EIO;
1161         }
1162         adapter->stopped = 0;
1163
1164         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1165
1166         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1167         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1168         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1169         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1170         E1000_WRITE_FLUSH(hw);
1171
1172         /* configure PF module if SRIOV enabled */
1173         igb_pf_host_configure(dev);
1174
1175         /* check and configure queue intr-vector mapping */
1176         if ((rte_intr_cap_multiple(intr_handle) ||
1177              !RTE_ETH_DEV_SRIOV(dev).active) &&
1178             dev->data->dev_conf.intr_conf.rxq != 0) {
1179                 intr_vector = dev->data->nb_rx_queues;
1180                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1181                         return -1;
1182         }
1183
1184         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1185                 intr_handle->intr_vec =
1186                         rte_zmalloc("intr_vec",
1187                                     dev->data->nb_rx_queues * sizeof(int), 0);
1188                 if (intr_handle->intr_vec == NULL) {
1189                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1190                                      " intr_vec\n", dev->data->nb_rx_queues);
1191                         return -ENOMEM;
1192                 }
1193         }
1194
1195         /* confiugre msix for rx interrupt */
1196         eth_igb_configure_msix_intr(dev);
1197
1198         /* Configure for OS presence */
1199         igb_init_manageability(hw);
1200
1201         eth_igb_tx_init(dev);
1202
1203         /* This can fail when allocating mbufs for descriptor rings */
1204         ret = eth_igb_rx_init(dev);
1205         if (ret) {
1206                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1207                 igb_dev_clear_queues(dev);
1208                 return ret;
1209         }
1210
1211         e1000_clear_hw_cntrs_base_generic(hw);
1212
1213         /*
1214          * VLAN Offload Settings
1215          */
1216         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1217                         ETH_VLAN_EXTEND_MASK;
1218         eth_igb_vlan_offload_set(dev, mask);
1219
1220         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1221                 /* Enable VLAN filter since VMDq always use VLAN filter */
1222                 igb_vmdq_vlan_hw_filter_enable(dev);
1223         }
1224
1225         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1226                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1227                 (hw->mac.type == e1000_i211)) {
1228                 /* Configure EITR with the maximum possible value (0xFFFF) */
1229                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1230         }
1231
1232         /* Setup link speed and duplex */
1233         switch (dev->data->dev_conf.link_speed) {
1234         case ETH_LINK_SPEED_AUTONEG:
1235                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1236                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1237                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1238                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1239                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1240                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1241                 else
1242                         goto error_invalid_config;
1243                 break;
1244         case ETH_LINK_SPEED_10:
1245                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1246                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1247                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1248                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1249                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1250                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1251                 else
1252                         goto error_invalid_config;
1253                 break;
1254         case ETH_LINK_SPEED_100:
1255                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1256                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1257                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1258                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1259                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1260                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1261                 else
1262                         goto error_invalid_config;
1263                 break;
1264         case ETH_LINK_SPEED_1000:
1265                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1266                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1267                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1268                 else
1269                         goto error_invalid_config;
1270                 break;
1271         case ETH_LINK_SPEED_10000:
1272         default:
1273                 goto error_invalid_config;
1274         }
1275         e1000_setup_link(hw);
1276
1277         if (rte_intr_allow_others(intr_handle)) {
1278                 /* check if lsc interrupt is enabled */
1279                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1280                         eth_igb_lsc_interrupt_setup(dev);
1281         } else {
1282                 rte_intr_callback_unregister(intr_handle,
1283                                              eth_igb_interrupt_handler,
1284                                              (void *)dev);
1285                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1286                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1287                                      " no intr multiplex\n");
1288         }
1289
1290         /* check if rxq interrupt is enabled */
1291         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1292             rte_intr_dp_is_en(intr_handle))
1293                 eth_igb_rxq_interrupt_setup(dev);
1294
1295         /* enable uio/vfio intr/eventfd mapping */
1296         rte_intr_enable(intr_handle);
1297
1298         /* resume enabled intr since hw reset */
1299         igb_intr_enable(dev);
1300
1301         PMD_INIT_LOG(DEBUG, "<<");
1302
1303         return 0;
1304
1305 error_invalid_config:
1306         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1307                      dev->data->dev_conf.link_speed,
1308                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1309         igb_dev_clear_queues(dev);
1310         return -EINVAL;
1311 }
1312
1313 /*********************************************************************
1314  *
1315  *  This routine disables all traffic on the adapter by issuing a
1316  *  global reset on the MAC.
1317  *
1318  **********************************************************************/
1319 static void
1320 eth_igb_stop(struct rte_eth_dev *dev)
1321 {
1322         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323         struct e1000_filter_info *filter_info =
1324                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1325         struct rte_eth_link link;
1326         struct e1000_flex_filter *p_flex;
1327         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1328         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1329         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1330
1331         igb_intr_disable(hw);
1332
1333         /* disable intr eventfd mapping */
1334         rte_intr_disable(intr_handle);
1335
1336         igb_pf_reset_hw(hw);
1337         E1000_WRITE_REG(hw, E1000_WUC, 0);
1338
1339         /* Set bit for Go Link disconnect */
1340         if (hw->mac.type >= e1000_82580) {
1341                 uint32_t phpm_reg;
1342
1343                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1344                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1345                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1346         }
1347
1348         /* Power down the phy. Needed to make the link go Down */
1349         if (hw->phy.media_type == e1000_media_type_copper)
1350                 e1000_power_down_phy(hw);
1351         else
1352                 e1000_shutdown_fiber_serdes_link(hw);
1353
1354         igb_dev_clear_queues(dev);
1355
1356         /* clear the recorded link status */
1357         memset(&link, 0, sizeof(link));
1358         rte_igb_dev_atomic_write_link_status(dev, &link);
1359
1360         /* Remove all flex filters of the device */
1361         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1362                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1363                 rte_free(p_flex);
1364         }
1365         filter_info->flex_mask = 0;
1366
1367         /* Remove all ntuple filters of the device */
1368         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1369              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1370                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1371                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1372                              p_5tuple, entries);
1373                 rte_free(p_5tuple);
1374         }
1375         filter_info->fivetuple_mask = 0;
1376         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1377              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1378                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1379                 TAILQ_REMOVE(&filter_info->twotuple_list,
1380                              p_2tuple, entries);
1381                 rte_free(p_2tuple);
1382         }
1383         filter_info->twotuple_mask = 0;
1384
1385         if (!rte_intr_allow_others(intr_handle))
1386                 /* resume to the default handler */
1387                 rte_intr_callback_register(intr_handle,
1388                                            eth_igb_interrupt_handler,
1389                                            (void *)dev);
1390
1391         /* Clean datapath event and queue/vec mapping */
1392         rte_intr_efd_disable(intr_handle);
1393         if (intr_handle->intr_vec != NULL) {
1394                 rte_free(intr_handle->intr_vec);
1395                 intr_handle->intr_vec = NULL;
1396         }
1397 }
1398
1399 static void
1400 eth_igb_close(struct rte_eth_dev *dev)
1401 {
1402         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1403         struct e1000_adapter *adapter =
1404                 E1000_DEV_PRIVATE(dev->data->dev_private);
1405         struct rte_eth_link link;
1406         struct rte_pci_device *pci_dev;
1407
1408         eth_igb_stop(dev);
1409         adapter->stopped = 1;
1410
1411         e1000_phy_hw_reset(hw);
1412         igb_release_manageability(hw);
1413         igb_hw_control_release(hw);
1414
1415         /* Clear bit for Go Link disconnect */
1416         if (hw->mac.type >= e1000_82580) {
1417                 uint32_t phpm_reg;
1418
1419                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1420                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1421                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1422         }
1423
1424         igb_dev_free_queues(dev);
1425
1426         pci_dev = dev->pci_dev;
1427         if (pci_dev->intr_handle.intr_vec) {
1428                 rte_free(pci_dev->intr_handle.intr_vec);
1429                 pci_dev->intr_handle.intr_vec = NULL;
1430         }
1431
1432         memset(&link, 0, sizeof(link));
1433         rte_igb_dev_atomic_write_link_status(dev, &link);
1434 }
1435
1436 static int
1437 igb_get_rx_buffer_size(struct e1000_hw *hw)
1438 {
1439         uint32_t rx_buf_size;
1440         if (hw->mac.type == e1000_82576) {
1441                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1442         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1443                 /* PBS needs to be translated according to a lookup table */
1444                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1445                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1446                 rx_buf_size = (rx_buf_size << 10);
1447         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1448                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1449         } else {
1450                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1451         }
1452
1453         return rx_buf_size;
1454 }
1455
1456 /*********************************************************************
1457  *
1458  *  Initialize the hardware
1459  *
1460  **********************************************************************/
1461 static int
1462 igb_hardware_init(struct e1000_hw *hw)
1463 {
1464         uint32_t rx_buf_size;
1465         int diag;
1466
1467         /* Let the firmware know the OS is in control */
1468         igb_hw_control_acquire(hw);
1469
1470         /*
1471          * These parameters control the automatic generation (Tx) and
1472          * response (Rx) to Ethernet PAUSE frames.
1473          * - High water mark should allow for at least two standard size (1518)
1474          *   frames to be received after sending an XOFF.
1475          * - Low water mark works best when it is very near the high water mark.
1476          *   This allows the receiver to restart by sending XON when it has
1477          *   drained a bit. Here we use an arbitrary value of 1500 which will
1478          *   restart after one full frame is pulled from the buffer. There
1479          *   could be several smaller frames in the buffer and if so they will
1480          *   not trigger the XON until their total number reduces the buffer
1481          *   by 1500.
1482          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1483          */
1484         rx_buf_size = igb_get_rx_buffer_size(hw);
1485
1486         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1487         hw->fc.low_water = hw->fc.high_water - 1500;
1488         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1489         hw->fc.send_xon = 1;
1490
1491         /* Set Flow control, use the tunable location if sane */
1492         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1493                 hw->fc.requested_mode = igb_fc_setting;
1494         else
1495                 hw->fc.requested_mode = e1000_fc_none;
1496
1497         /* Issue a global reset */
1498         igb_pf_reset_hw(hw);
1499         E1000_WRITE_REG(hw, E1000_WUC, 0);
1500
1501         diag = e1000_init_hw(hw);
1502         if (diag < 0)
1503                 return diag;
1504
1505         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1506         e1000_get_phy_info(hw);
1507         e1000_check_for_link(hw);
1508
1509         return 0;
1510 }
1511
1512 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1513 static void
1514 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1515 {
1516         int pause_frames;
1517
1518         uint64_t old_gprc  = stats->gprc;
1519         uint64_t old_gptc  = stats->gptc;
1520         uint64_t old_tpr   = stats->tpr;
1521         uint64_t old_tpt   = stats->tpt;
1522         uint64_t old_rpthc = stats->rpthc;
1523         uint64_t old_hgptc = stats->hgptc;
1524
1525         if(hw->phy.media_type == e1000_media_type_copper ||
1526             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1527                 stats->symerrs +=
1528                     E1000_READ_REG(hw,E1000_SYMERRS);
1529                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1530         }
1531
1532         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1533         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1534         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1535         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1536
1537         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1538         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1539         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1540         stats->dc += E1000_READ_REG(hw, E1000_DC);
1541         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1542         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1543         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1544         /*
1545         ** For watchdog management we need to know if we have been
1546         ** paused during the last interval, so capture that here.
1547         */
1548         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1549         stats->xoffrxc += pause_frames;
1550         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1551         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1552         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1553         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1554         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1555         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1556         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1557         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1558         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1559         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1560         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1561         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1562
1563         /* For the 64-bit byte counters the low dword must be read first. */
1564         /* Both registers clear on the read of the high dword */
1565
1566         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1567         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1568         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1569         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1570         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1571         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1572         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1573
1574         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1575         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1576         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1577         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1578         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1579
1580         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1581         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1582
1583         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1584         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1585         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1586         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1587         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1588         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1589
1590         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1591         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1592         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1593         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1594         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1595         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1596         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1597         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1598
1599         /* Interrupt Counts */
1600
1601         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1602         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1603         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1604         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1605         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1606         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1607         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1608         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1609         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1610
1611         /* Host to Card Statistics */
1612
1613         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1614         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1615         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1616         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1617         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1618         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1619         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1620         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1621         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1622         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1623         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1624         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1625         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1626         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1627         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1628         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1629
1630         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1631         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1632         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1633         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1634         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1635         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1636 }
1637
1638 static void
1639 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1640 {
1641         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         struct e1000_hw_stats *stats =
1643                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1644
1645         igb_read_stats_registers(hw, stats);
1646
1647         if (rte_stats == NULL)
1648                 return;
1649
1650         /* Rx Errors */
1651         rte_stats->imissed = stats->mpc;
1652         rte_stats->ierrors = stats->crcerrs +
1653                              stats->rlec + stats->ruc + stats->roc +
1654                              rte_stats->imissed +
1655                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1656
1657         /* Tx Errors */
1658         rte_stats->oerrors = stats->ecol + stats->latecol;
1659
1660         rte_stats->ipackets = stats->gprc;
1661         rte_stats->opackets = stats->gptc;
1662         rte_stats->ibytes   = stats->gorc;
1663         rte_stats->obytes   = stats->gotc;
1664 }
1665
1666 static void
1667 eth_igb_stats_reset(struct rte_eth_dev *dev)
1668 {
1669         struct e1000_hw_stats *hw_stats =
1670                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1671
1672         /* HW registers are cleared on read */
1673         eth_igb_stats_get(dev, NULL);
1674
1675         /* Reset software totals */
1676         memset(hw_stats, 0, sizeof(*hw_stats));
1677 }
1678
1679 static void
1680 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1681 {
1682         struct e1000_hw_stats *stats =
1683                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1684
1685         /* HW registers are cleared on read */
1686         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1687
1688         /* Reset software totals */
1689         memset(stats, 0, sizeof(*stats));
1690 }
1691
1692 static int
1693 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1694                    unsigned n)
1695 {
1696         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         struct e1000_hw_stats *hw_stats =
1698                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1699         unsigned i;
1700
1701         if (n < IGB_NB_XSTATS)
1702                 return IGB_NB_XSTATS;
1703
1704         igb_read_stats_registers(hw, hw_stats);
1705
1706         /* If this is a reset xstats is NULL, and we have cleared the
1707          * registers by reading them.
1708          */
1709         if (!xstats)
1710                 return 0;
1711
1712         /* Extended stats */
1713         for (i = 0; i < IGB_NB_XSTATS; i++) {
1714                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1715                          "%s", rte_igb_stats_strings[i].name);
1716                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1717                         rte_igb_stats_strings[i].offset);
1718         }
1719
1720         return IGB_NB_XSTATS;
1721 }
1722
1723 static void
1724 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1725 {
1726         /* Good Rx packets, include VF loopback */
1727         UPDATE_VF_STAT(E1000_VFGPRC,
1728             hw_stats->last_gprc, hw_stats->gprc);
1729
1730         /* Good Rx octets, include VF loopback */
1731         UPDATE_VF_STAT(E1000_VFGORC,
1732             hw_stats->last_gorc, hw_stats->gorc);
1733
1734         /* Good Tx packets, include VF loopback */
1735         UPDATE_VF_STAT(E1000_VFGPTC,
1736             hw_stats->last_gptc, hw_stats->gptc);
1737
1738         /* Good Tx octets, include VF loopback */
1739         UPDATE_VF_STAT(E1000_VFGOTC,
1740             hw_stats->last_gotc, hw_stats->gotc);
1741
1742         /* Rx Multicst packets */
1743         UPDATE_VF_STAT(E1000_VFMPRC,
1744             hw_stats->last_mprc, hw_stats->mprc);
1745
1746         /* Good Rx loopback packets */
1747         UPDATE_VF_STAT(E1000_VFGPRLBC,
1748             hw_stats->last_gprlbc, hw_stats->gprlbc);
1749
1750         /* Good Rx loopback octets */
1751         UPDATE_VF_STAT(E1000_VFGORLBC,
1752             hw_stats->last_gorlbc, hw_stats->gorlbc);
1753
1754         /* Good Tx loopback packets */
1755         UPDATE_VF_STAT(E1000_VFGPTLBC,
1756             hw_stats->last_gptlbc, hw_stats->gptlbc);
1757
1758         /* Good Tx loopback octets */
1759         UPDATE_VF_STAT(E1000_VFGOTLBC,
1760             hw_stats->last_gotlbc, hw_stats->gotlbc);
1761 }
1762
1763 static int
1764 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1765                      unsigned n)
1766 {
1767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1768         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1769                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1770         unsigned i;
1771
1772         if (n < IGBVF_NB_XSTATS)
1773                 return IGBVF_NB_XSTATS;
1774
1775         igbvf_read_stats_registers(hw, hw_stats);
1776
1777         if (!xstats)
1778                 return 0;
1779
1780         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1781                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1782                          rte_igbvf_stats_strings[i].name);
1783                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1784                         rte_igbvf_stats_strings[i].offset);
1785         }
1786
1787         return IGBVF_NB_XSTATS;
1788 }
1789
1790 static void
1791 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1792 {
1793         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1794         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1795                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1796
1797         igbvf_read_stats_registers(hw, hw_stats);
1798
1799         if (rte_stats == NULL)
1800                 return;
1801
1802         rte_stats->ipackets = hw_stats->gprc;
1803         rte_stats->ibytes = hw_stats->gorc;
1804         rte_stats->opackets = hw_stats->gptc;
1805         rte_stats->obytes = hw_stats->gotc;
1806         rte_stats->imcasts = hw_stats->mprc;
1807         rte_stats->ilbpackets = hw_stats->gprlbc;
1808         rte_stats->ilbbytes = hw_stats->gorlbc;
1809         rte_stats->olbpackets = hw_stats->gptlbc;
1810         rte_stats->olbbytes = hw_stats->gotlbc;
1811 }
1812
1813 static void
1814 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1815 {
1816         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1817                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1818
1819         /* Sync HW register to the last stats */
1820         eth_igbvf_stats_get(dev, NULL);
1821
1822         /* reset HW current stats*/
1823         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1824                offsetof(struct e1000_vf_stats, gprc));
1825 }
1826
1827 static void
1828 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1829 {
1830         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831
1832         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1833         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1834         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1835         dev_info->rx_offload_capa =
1836                 DEV_RX_OFFLOAD_VLAN_STRIP |
1837                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1838                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1839                 DEV_RX_OFFLOAD_TCP_CKSUM;
1840         dev_info->tx_offload_capa =
1841                 DEV_TX_OFFLOAD_VLAN_INSERT |
1842                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1843                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1844                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1845                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1846                 DEV_TX_OFFLOAD_TCP_TSO;
1847
1848         switch (hw->mac.type) {
1849         case e1000_82575:
1850                 dev_info->max_rx_queues = 4;
1851                 dev_info->max_tx_queues = 4;
1852                 dev_info->max_vmdq_pools = 0;
1853                 break;
1854
1855         case e1000_82576:
1856                 dev_info->max_rx_queues = 16;
1857                 dev_info->max_tx_queues = 16;
1858                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1859                 dev_info->vmdq_queue_num = 16;
1860                 break;
1861
1862         case e1000_82580:
1863                 dev_info->max_rx_queues = 8;
1864                 dev_info->max_tx_queues = 8;
1865                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1866                 dev_info->vmdq_queue_num = 8;
1867                 break;
1868
1869         case e1000_i350:
1870                 dev_info->max_rx_queues = 8;
1871                 dev_info->max_tx_queues = 8;
1872                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1873                 dev_info->vmdq_queue_num = 8;
1874                 break;
1875
1876         case e1000_i354:
1877                 dev_info->max_rx_queues = 8;
1878                 dev_info->max_tx_queues = 8;
1879                 break;
1880
1881         case e1000_i210:
1882                 dev_info->max_rx_queues = 4;
1883                 dev_info->max_tx_queues = 4;
1884                 dev_info->max_vmdq_pools = 0;
1885                 break;
1886
1887         case e1000_i211:
1888                 dev_info->max_rx_queues = 2;
1889                 dev_info->max_tx_queues = 2;
1890                 dev_info->max_vmdq_pools = 0;
1891                 break;
1892
1893         default:
1894                 /* Should not happen */
1895                 break;
1896         }
1897         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1898         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1899         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1900
1901         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1902                 .rx_thresh = {
1903                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1904                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1905                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1906                 },
1907                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1908                 .rx_drop_en = 0,
1909         };
1910
1911         dev_info->default_txconf = (struct rte_eth_txconf) {
1912                 .tx_thresh = {
1913                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1914                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1915                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1916                 },
1917                 .txq_flags = 0,
1918         };
1919
1920         dev_info->rx_desc_lim = rx_desc_lim;
1921         dev_info->tx_desc_lim = tx_desc_lim;
1922 }
1923
1924 static void
1925 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1926 {
1927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928
1929         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1930         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1931         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1932         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1933                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1934                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1935                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1936         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1937                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1938                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1939                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1940                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1941                                 DEV_TX_OFFLOAD_TCP_TSO;
1942         switch (hw->mac.type) {
1943         case e1000_vfadapt:
1944                 dev_info->max_rx_queues = 2;
1945                 dev_info->max_tx_queues = 2;
1946                 break;
1947         case e1000_vfadapt_i350:
1948                 dev_info->max_rx_queues = 1;
1949                 dev_info->max_tx_queues = 1;
1950                 break;
1951         default:
1952                 /* Should not happen */
1953                 break;
1954         }
1955
1956         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1957                 .rx_thresh = {
1958                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1959                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1960                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1961                 },
1962                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1963                 .rx_drop_en = 0,
1964         };
1965
1966         dev_info->default_txconf = (struct rte_eth_txconf) {
1967                 .tx_thresh = {
1968                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1969                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1970                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1971                 },
1972                 .txq_flags = 0,
1973         };
1974
1975         dev_info->rx_desc_lim = rx_desc_lim;
1976         dev_info->tx_desc_lim = tx_desc_lim;
1977 }
1978
1979 /* return 0 means link status changed, -1 means not changed */
1980 static int
1981 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1982 {
1983         struct e1000_hw *hw =
1984                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct rte_eth_link link, old;
1986         int link_check, count;
1987
1988         link_check = 0;
1989         hw->mac.get_link_status = 1;
1990
1991         /* possible wait-to-complete in up to 9 seconds */
1992         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1993                 /* Read the real link status */
1994                 switch (hw->phy.media_type) {
1995                 case e1000_media_type_copper:
1996                         /* Do the work to read phy */
1997                         e1000_check_for_link(hw);
1998                         link_check = !hw->mac.get_link_status;
1999                         break;
2000
2001                 case e1000_media_type_fiber:
2002                         e1000_check_for_link(hw);
2003                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2004                                       E1000_STATUS_LU);
2005                         break;
2006
2007                 case e1000_media_type_internal_serdes:
2008                         e1000_check_for_link(hw);
2009                         link_check = hw->mac.serdes_has_link;
2010                         break;
2011
2012                 /* VF device is type_unknown */
2013                 case e1000_media_type_unknown:
2014                         eth_igbvf_link_update(hw);
2015                         link_check = !hw->mac.get_link_status;
2016                         break;
2017
2018                 default:
2019                         break;
2020                 }
2021                 if (link_check || wait_to_complete == 0)
2022                         break;
2023                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2024         }
2025         memset(&link, 0, sizeof(link));
2026         rte_igb_dev_atomic_read_link_status(dev, &link);
2027         old = link;
2028
2029         /* Now we check if a transition has happened */
2030         if (link_check) {
2031                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2032                                           &link.link_duplex);
2033                 link.link_status = 1;
2034         } else if (!link_check) {
2035                 link.link_speed = 0;
2036                 link.link_duplex = 0;
2037                 link.link_status = 0;
2038         }
2039         rte_igb_dev_atomic_write_link_status(dev, &link);
2040
2041         /* not changed */
2042         if (old.link_status == link.link_status)
2043                 return -1;
2044
2045         /* changed */
2046         return 0;
2047 }
2048
2049 /*
2050  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2051  * For ASF and Pass Through versions of f/w this means
2052  * that the driver is loaded.
2053  */
2054 static void
2055 igb_hw_control_acquire(struct e1000_hw *hw)
2056 {
2057         uint32_t ctrl_ext;
2058
2059         /* Let firmware know the driver has taken over */
2060         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2061         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2062 }
2063
2064 /*
2065  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2066  * For ASF and Pass Through versions of f/w this means that the
2067  * driver is no longer loaded.
2068  */
2069 static void
2070 igb_hw_control_release(struct e1000_hw *hw)
2071 {
2072         uint32_t ctrl_ext;
2073
2074         /* Let firmware taken over control of h/w */
2075         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2076         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2077                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2078 }
2079
2080 /*
2081  * Bit of a misnomer, what this really means is
2082  * to enable OS management of the system... aka
2083  * to disable special hardware management features.
2084  */
2085 static void
2086 igb_init_manageability(struct e1000_hw *hw)
2087 {
2088         if (e1000_enable_mng_pass_thru(hw)) {
2089                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2090                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2091
2092                 /* disable hardware interception of ARP */
2093                 manc &= ~(E1000_MANC_ARP_EN);
2094
2095                 /* enable receiving management packets to the host */
2096                 manc |= E1000_MANC_EN_MNG2HOST;
2097                 manc2h |= 1 << 5;  /* Mng Port 623 */
2098                 manc2h |= 1 << 6;  /* Mng Port 664 */
2099                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2100                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2101         }
2102 }
2103
2104 static void
2105 igb_release_manageability(struct e1000_hw *hw)
2106 {
2107         if (e1000_enable_mng_pass_thru(hw)) {
2108                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2109
2110                 manc |= E1000_MANC_ARP_EN;
2111                 manc &= ~E1000_MANC_EN_MNG2HOST;
2112
2113                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2114         }
2115 }
2116
2117 static void
2118 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2119 {
2120         struct e1000_hw *hw =
2121                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2122         uint32_t rctl;
2123
2124         rctl = E1000_READ_REG(hw, E1000_RCTL);
2125         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2126         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2127 }
2128
2129 static void
2130 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2131 {
2132         struct e1000_hw *hw =
2133                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         uint32_t rctl;
2135
2136         rctl = E1000_READ_REG(hw, E1000_RCTL);
2137         rctl &= (~E1000_RCTL_UPE);
2138         if (dev->data->all_multicast == 1)
2139                 rctl |= E1000_RCTL_MPE;
2140         else
2141                 rctl &= (~E1000_RCTL_MPE);
2142         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2143 }
2144
2145 static void
2146 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2147 {
2148         struct e1000_hw *hw =
2149                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         uint32_t rctl;
2151
2152         rctl = E1000_READ_REG(hw, E1000_RCTL);
2153         rctl |= E1000_RCTL_MPE;
2154         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2155 }
2156
2157 static void
2158 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2159 {
2160         struct e1000_hw *hw =
2161                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162         uint32_t rctl;
2163
2164         if (dev->data->promiscuous == 1)
2165                 return; /* must remain in all_multicast mode */
2166         rctl = E1000_READ_REG(hw, E1000_RCTL);
2167         rctl &= (~E1000_RCTL_MPE);
2168         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2169 }
2170
2171 static int
2172 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2173 {
2174         struct e1000_hw *hw =
2175                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176         struct e1000_vfta * shadow_vfta =
2177                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2178         uint32_t vfta;
2179         uint32_t vid_idx;
2180         uint32_t vid_bit;
2181
2182         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2183                               E1000_VFTA_ENTRY_MASK);
2184         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2185         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2186         if (on)
2187                 vfta |= vid_bit;
2188         else
2189                 vfta &= ~vid_bit;
2190         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2191
2192         /* update local VFTA copy */
2193         shadow_vfta->vfta[vid_idx] = vfta;
2194
2195         return 0;
2196 }
2197
2198 static int
2199 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2200                       enum rte_vlan_type vlan_type,
2201                       uint16_t tpid)
2202 {
2203         struct e1000_hw *hw =
2204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2205         uint32_t reg = ETHER_TYPE_VLAN;
2206         int ret = 0;
2207
2208         switch (vlan_type) {
2209         case ETH_VLAN_TYPE_INNER:
2210                 reg |= (tpid << 16);
2211                 E1000_WRITE_REG(hw, E1000_VET, reg);
2212                 break;
2213         default:
2214                 ret = -EINVAL;
2215                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
2216                 break;
2217         }
2218
2219         return ret;
2220 }
2221
2222 static void
2223 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2224 {
2225         struct e1000_hw *hw =
2226                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         uint32_t reg;
2228
2229         /* Filter Table Disable */
2230         reg = E1000_READ_REG(hw, E1000_RCTL);
2231         reg &= ~E1000_RCTL_CFIEN;
2232         reg &= ~E1000_RCTL_VFE;
2233         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2234 }
2235
2236 static void
2237 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2238 {
2239         struct e1000_hw *hw =
2240                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2241         struct e1000_vfta * shadow_vfta =
2242                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2243         uint32_t reg;
2244         int i;
2245
2246         /* Filter Table Enable, CFI not used for packet acceptance */
2247         reg = E1000_READ_REG(hw, E1000_RCTL);
2248         reg &= ~E1000_RCTL_CFIEN;
2249         reg |= E1000_RCTL_VFE;
2250         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2251
2252         /* restore VFTA table */
2253         for (i = 0; i < IGB_VFTA_SIZE; i++)
2254                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2255 }
2256
2257 static void
2258 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2259 {
2260         struct e1000_hw *hw =
2261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         uint32_t reg;
2263
2264         /* VLAN Mode Disable */
2265         reg = E1000_READ_REG(hw, E1000_CTRL);
2266         reg &= ~E1000_CTRL_VME;
2267         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2268 }
2269
2270 static void
2271 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2272 {
2273         struct e1000_hw *hw =
2274                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         uint32_t reg;
2276
2277         /* VLAN Mode Enable */
2278         reg = E1000_READ_REG(hw, E1000_CTRL);
2279         reg |= E1000_CTRL_VME;
2280         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2281 }
2282
2283 static void
2284 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2285 {
2286         struct e1000_hw *hw =
2287                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2288         uint32_t reg;
2289
2290         /* CTRL_EXT: Extended VLAN */
2291         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2292         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2293         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2294
2295         /* Update maximum packet length */
2296         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2297                 E1000_WRITE_REG(hw, E1000_RLPML,
2298                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2299                                                 VLAN_TAG_SIZE);
2300 }
2301
2302 static void
2303 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2304 {
2305         struct e1000_hw *hw =
2306                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         uint32_t reg;
2308
2309         /* CTRL_EXT: Extended VLAN */
2310         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2311         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2312         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2313
2314         /* Update maximum packet length */
2315         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2316                 E1000_WRITE_REG(hw, E1000_RLPML,
2317                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2318                                                 2 * VLAN_TAG_SIZE);
2319 }
2320
2321 static void
2322 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2323 {
2324         if(mask & ETH_VLAN_STRIP_MASK){
2325                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2326                         igb_vlan_hw_strip_enable(dev);
2327                 else
2328                         igb_vlan_hw_strip_disable(dev);
2329         }
2330
2331         if(mask & ETH_VLAN_FILTER_MASK){
2332                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2333                         igb_vlan_hw_filter_enable(dev);
2334                 else
2335                         igb_vlan_hw_filter_disable(dev);
2336         }
2337
2338         if(mask & ETH_VLAN_EXTEND_MASK){
2339                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2340                         igb_vlan_hw_extend_enable(dev);
2341                 else
2342                         igb_vlan_hw_extend_disable(dev);
2343         }
2344 }
2345
2346
2347 /**
2348  * It enables the interrupt mask and then enable the interrupt.
2349  *
2350  * @param dev
2351  *  Pointer to struct rte_eth_dev.
2352  *
2353  * @return
2354  *  - On success, zero.
2355  *  - On failure, a negative value.
2356  */
2357 static int
2358 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2359 {
2360         struct e1000_interrupt *intr =
2361                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2362
2363         intr->mask |= E1000_ICR_LSC;
2364
2365         return 0;
2366 }
2367
2368 /* It clears the interrupt causes and enables the interrupt.
2369  * It will be called once only during nic initialized.
2370  *
2371  * @param dev
2372  *  Pointer to struct rte_eth_dev.
2373  *
2374  * @return
2375  *  - On success, zero.
2376  *  - On failure, a negative value.
2377  */
2378 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2379 {
2380         uint32_t mask, regval;
2381         struct e1000_hw *hw =
2382                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         struct rte_eth_dev_info dev_info;
2384
2385         memset(&dev_info, 0, sizeof(dev_info));
2386         eth_igb_infos_get(dev, &dev_info);
2387
2388         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2389         regval = E1000_READ_REG(hw, E1000_EIMS);
2390         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2391
2392         return 0;
2393 }
2394
2395 /*
2396  * It reads ICR and gets interrupt causes, check it and set a bit flag
2397  * to update link status.
2398  *
2399  * @param dev
2400  *  Pointer to struct rte_eth_dev.
2401  *
2402  * @return
2403  *  - On success, zero.
2404  *  - On failure, a negative value.
2405  */
2406 static int
2407 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2408 {
2409         uint32_t icr;
2410         struct e1000_hw *hw =
2411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         struct e1000_interrupt *intr =
2413                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414
2415         igb_intr_disable(hw);
2416
2417         /* read-on-clear nic registers here */
2418         icr = E1000_READ_REG(hw, E1000_ICR);
2419
2420         intr->flags = 0;
2421         if (icr & E1000_ICR_LSC) {
2422                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2423         }
2424
2425         if (icr & E1000_ICR_VMMB)
2426                 intr->flags |= E1000_FLAG_MAILBOX;
2427
2428         return 0;
2429 }
2430
2431 /*
2432  * It executes link_update after knowing an interrupt is prsent.
2433  *
2434  * @param dev
2435  *  Pointer to struct rte_eth_dev.
2436  *
2437  * @return
2438  *  - On success, zero.
2439  *  - On failure, a negative value.
2440  */
2441 static int
2442 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2443 {
2444         struct e1000_hw *hw =
2445                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         struct e1000_interrupt *intr =
2447                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2448         uint32_t tctl, rctl;
2449         struct rte_eth_link link;
2450         int ret;
2451
2452         if (intr->flags & E1000_FLAG_MAILBOX) {
2453                 igb_pf_mbx_process(dev);
2454                 intr->flags &= ~E1000_FLAG_MAILBOX;
2455         }
2456
2457         igb_intr_enable(dev);
2458         rte_intr_enable(&(dev->pci_dev->intr_handle));
2459
2460         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2461                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2462
2463                 /* set get_link_status to check register later */
2464                 hw->mac.get_link_status = 1;
2465                 ret = eth_igb_link_update(dev, 0);
2466
2467                 /* check if link has changed */
2468                 if (ret < 0)
2469                         return 0;
2470
2471                 memset(&link, 0, sizeof(link));
2472                 rte_igb_dev_atomic_read_link_status(dev, &link);
2473                 if (link.link_status) {
2474                         PMD_INIT_LOG(INFO,
2475                                      " Port %d: Link Up - speed %u Mbps - %s",
2476                                      dev->data->port_id,
2477                                      (unsigned)link.link_speed,
2478                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2479                                      "full-duplex" : "half-duplex");
2480                 } else {
2481                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2482                                      dev->data->port_id);
2483                 }
2484
2485                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2486                              dev->pci_dev->addr.domain,
2487                              dev->pci_dev->addr.bus,
2488                              dev->pci_dev->addr.devid,
2489                              dev->pci_dev->addr.function);
2490                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2491                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2492                 if (link.link_status) {
2493                         /* enable Tx/Rx */
2494                         tctl |= E1000_TCTL_EN;
2495                         rctl |= E1000_RCTL_EN;
2496                 } else {
2497                         /* disable Tx/Rx */
2498                         tctl &= ~E1000_TCTL_EN;
2499                         rctl &= ~E1000_RCTL_EN;
2500                 }
2501                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2502                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2503                 E1000_WRITE_FLUSH(hw);
2504                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2505         }
2506
2507         return 0;
2508 }
2509
2510 /**
2511  * Interrupt handler which shall be registered at first.
2512  *
2513  * @param handle
2514  *  Pointer to interrupt handle.
2515  * @param param
2516  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2517  *
2518  * @return
2519  *  void
2520  */
2521 static void
2522 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2523                                                         void *param)
2524 {
2525         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2526
2527         eth_igb_interrupt_get_status(dev);
2528         eth_igb_interrupt_action(dev);
2529 }
2530
2531 static int
2532 eth_igb_led_on(struct rte_eth_dev *dev)
2533 {
2534         struct e1000_hw *hw;
2535
2536         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2538 }
2539
2540 static int
2541 eth_igb_led_off(struct rte_eth_dev *dev)
2542 {
2543         struct e1000_hw *hw;
2544
2545         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2547 }
2548
2549 static int
2550 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2551 {
2552         struct e1000_hw *hw;
2553         uint32_t ctrl;
2554         int tx_pause;
2555         int rx_pause;
2556
2557         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558         fc_conf->pause_time = hw->fc.pause_time;
2559         fc_conf->high_water = hw->fc.high_water;
2560         fc_conf->low_water = hw->fc.low_water;
2561         fc_conf->send_xon = hw->fc.send_xon;
2562         fc_conf->autoneg = hw->mac.autoneg;
2563
2564         /*
2565          * Return rx_pause and tx_pause status according to actual setting of
2566          * the TFCE and RFCE bits in the CTRL register.
2567          */
2568         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2569         if (ctrl & E1000_CTRL_TFCE)
2570                 tx_pause = 1;
2571         else
2572                 tx_pause = 0;
2573
2574         if (ctrl & E1000_CTRL_RFCE)
2575                 rx_pause = 1;
2576         else
2577                 rx_pause = 0;
2578
2579         if (rx_pause && tx_pause)
2580                 fc_conf->mode = RTE_FC_FULL;
2581         else if (rx_pause)
2582                 fc_conf->mode = RTE_FC_RX_PAUSE;
2583         else if (tx_pause)
2584                 fc_conf->mode = RTE_FC_TX_PAUSE;
2585         else
2586                 fc_conf->mode = RTE_FC_NONE;
2587
2588         return 0;
2589 }
2590
2591 static int
2592 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2593 {
2594         struct e1000_hw *hw;
2595         int err;
2596         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2597                 e1000_fc_none,
2598                 e1000_fc_rx_pause,
2599                 e1000_fc_tx_pause,
2600                 e1000_fc_full
2601         };
2602         uint32_t rx_buf_size;
2603         uint32_t max_high_water;
2604         uint32_t rctl;
2605
2606         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607         if (fc_conf->autoneg != hw->mac.autoneg)
2608                 return -ENOTSUP;
2609         rx_buf_size = igb_get_rx_buffer_size(hw);
2610         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2611
2612         /* At least reserve one Ethernet frame for watermark */
2613         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2614         if ((fc_conf->high_water > max_high_water) ||
2615             (fc_conf->high_water < fc_conf->low_water)) {
2616                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2617                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2618                 return -EINVAL;
2619         }
2620
2621         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2622         hw->fc.pause_time     = fc_conf->pause_time;
2623         hw->fc.high_water     = fc_conf->high_water;
2624         hw->fc.low_water      = fc_conf->low_water;
2625         hw->fc.send_xon       = fc_conf->send_xon;
2626
2627         err = e1000_setup_link_generic(hw);
2628         if (err == E1000_SUCCESS) {
2629
2630                 /* check if we want to forward MAC frames - driver doesn't have native
2631                  * capability to do that, so we'll write the registers ourselves */
2632
2633                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2634
2635                 /* set or clear MFLCN.PMCF bit depending on configuration */
2636                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2637                         rctl |= E1000_RCTL_PMCF;
2638                 else
2639                         rctl &= ~E1000_RCTL_PMCF;
2640
2641                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2642                 E1000_WRITE_FLUSH(hw);
2643
2644                 return 0;
2645         }
2646
2647         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2648         return -EIO;
2649 }
2650
2651 #define E1000_RAH_POOLSEL_SHIFT      (18)
2652 static void
2653 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2654                 uint32_t index, __rte_unused uint32_t pool)
2655 {
2656         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint32_t rah;
2658
2659         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2660         rah = E1000_READ_REG(hw, E1000_RAH(index));
2661         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2662         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2663 }
2664
2665 static void
2666 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2667 {
2668         uint8_t addr[ETHER_ADDR_LEN];
2669         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670
2671         memset(addr, 0, sizeof(addr));
2672
2673         e1000_rar_set(hw, addr, index);
2674 }
2675
2676 static void
2677 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2678                                 struct ether_addr *addr)
2679 {
2680         eth_igb_rar_clear(dev, 0);
2681
2682         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2683 }
2684 /*
2685  * Virtual Function operations
2686  */
2687 static void
2688 igbvf_intr_disable(struct e1000_hw *hw)
2689 {
2690         PMD_INIT_FUNC_TRACE();
2691
2692         /* Clear interrupt mask to stop from interrupts being generated */
2693         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2694
2695         E1000_WRITE_FLUSH(hw);
2696 }
2697
2698 static void
2699 igbvf_stop_adapter(struct rte_eth_dev *dev)
2700 {
2701         u32 reg_val;
2702         u16 i;
2703         struct rte_eth_dev_info dev_info;
2704         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705
2706         memset(&dev_info, 0, sizeof(dev_info));
2707         eth_igbvf_infos_get(dev, &dev_info);
2708
2709         /* Clear interrupt mask to stop from interrupts being generated */
2710         igbvf_intr_disable(hw);
2711
2712         /* Clear any pending interrupts, flush previous writes */
2713         E1000_READ_REG(hw, E1000_EICR);
2714
2715         /* Disable the transmit unit.  Each queue must be disabled. */
2716         for (i = 0; i < dev_info.max_tx_queues; i++)
2717                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2718
2719         /* Disable the receive unit by stopping each queue */
2720         for (i = 0; i < dev_info.max_rx_queues; i++) {
2721                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2722                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2723                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2724                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2725                         ;
2726         }
2727
2728         /* flush all queues disables */
2729         E1000_WRITE_FLUSH(hw);
2730         msec_delay(2);
2731 }
2732
2733 static int eth_igbvf_link_update(struct e1000_hw *hw)
2734 {
2735         struct e1000_mbx_info *mbx = &hw->mbx;
2736         struct e1000_mac_info *mac = &hw->mac;
2737         int ret_val = E1000_SUCCESS;
2738
2739         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2740
2741         /*
2742          * We only want to run this if there has been a rst asserted.
2743          * in this case that could mean a link change, device reset,
2744          * or a virtual function reset
2745          */
2746
2747         /* If we were hit with a reset or timeout drop the link */
2748         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2749                 mac->get_link_status = TRUE;
2750
2751         if (!mac->get_link_status)
2752                 goto out;
2753
2754         /* if link status is down no point in checking to see if pf is up */
2755         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2756                 goto out;
2757
2758         /* if we passed all the tests above then the link is up and we no
2759          * longer need to check for link */
2760         mac->get_link_status = FALSE;
2761
2762 out:
2763         return ret_val;
2764 }
2765
2766
2767 static int
2768 igbvf_dev_configure(struct rte_eth_dev *dev)
2769 {
2770         struct rte_eth_conf* conf = &dev->data->dev_conf;
2771
2772         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2773                      dev->data->port_id);
2774
2775         /*
2776          * VF has no ability to enable/disable HW CRC
2777          * Keep the persistent behavior the same as Host PF
2778          */
2779 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2780         if (!conf->rxmode.hw_strip_crc) {
2781                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2782                 conf->rxmode.hw_strip_crc = 1;
2783         }
2784 #else
2785         if (conf->rxmode.hw_strip_crc) {
2786                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2787                 conf->rxmode.hw_strip_crc = 0;
2788         }
2789 #endif
2790
2791         return 0;
2792 }
2793
2794 static int
2795 igbvf_dev_start(struct rte_eth_dev *dev)
2796 {
2797         struct e1000_hw *hw =
2798                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         struct e1000_adapter *adapter =
2800                 E1000_DEV_PRIVATE(dev->data->dev_private);
2801         int ret;
2802
2803         PMD_INIT_FUNC_TRACE();
2804
2805         hw->mac.ops.reset_hw(hw);
2806         adapter->stopped = 0;
2807
2808         /* Set all vfta */
2809         igbvf_set_vfta_all(dev,1);
2810
2811         eth_igbvf_tx_init(dev);
2812
2813         /* This can fail when allocating mbufs for descriptor rings */
2814         ret = eth_igbvf_rx_init(dev);
2815         if (ret) {
2816                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2817                 igb_dev_clear_queues(dev);
2818                 return ret;
2819         }
2820
2821         return 0;
2822 }
2823
2824 static void
2825 igbvf_dev_stop(struct rte_eth_dev *dev)
2826 {
2827         PMD_INIT_FUNC_TRACE();
2828
2829         igbvf_stop_adapter(dev);
2830
2831         /*
2832           * Clear what we set, but we still keep shadow_vfta to
2833           * restore after device starts
2834           */
2835         igbvf_set_vfta_all(dev,0);
2836
2837         igb_dev_clear_queues(dev);
2838 }
2839
2840 static void
2841 igbvf_dev_close(struct rte_eth_dev *dev)
2842 {
2843         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct e1000_adapter *adapter =
2845                 E1000_DEV_PRIVATE(dev->data->dev_private);
2846         struct ether_addr addr;
2847
2848         PMD_INIT_FUNC_TRACE();
2849
2850         e1000_reset_hw(hw);
2851
2852         igbvf_dev_stop(dev);
2853         adapter->stopped = 1;
2854         igb_dev_free_queues(dev);
2855
2856         /**
2857          * reprogram the RAR with a zero mac address,
2858          * to ensure that the VF traffic goes to the PF
2859          * after stop, close and detach of the VF.
2860          **/
2861
2862         memset(&addr, 0, sizeof(addr));
2863         igbvf_default_mac_addr_set(dev, &addr);
2864 }
2865
2866 static void
2867 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
2868 {
2869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870
2871         /* Set both unicast and multicast promisc */
2872         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
2873 }
2874
2875 static void
2876 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
2877 {
2878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879
2880         /* If in allmulticast mode leave multicast promisc */
2881         if (dev->data->all_multicast == 1)
2882                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2883         else
2884                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2885 }
2886
2887 static void
2888 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
2889 {
2890         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891
2892         /* In promiscuous mode multicast promisc already set */
2893         if (dev->data->promiscuous == 0)
2894                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
2895 }
2896
2897 static void
2898 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
2899 {
2900         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901
2902         /* In promiscuous mode leave multicast promisc enabled */
2903         if (dev->data->promiscuous == 0)
2904                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
2905 }
2906
2907 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2908 {
2909         struct e1000_mbx_info *mbx = &hw->mbx;
2910         uint32_t msgbuf[2];
2911         s32 err;
2912
2913         /* After set vlan, vlan strip will also be enabled in igb driver*/
2914         msgbuf[0] = E1000_VF_SET_VLAN;
2915         msgbuf[1] = vid;
2916         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2917         if (on)
2918                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2919
2920         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2921         if (err)
2922                 goto mbx_err;
2923
2924         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2925         if (err)
2926                 goto mbx_err;
2927
2928         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2929         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2930                 err = -EINVAL;
2931
2932 mbx_err:
2933         return err;
2934 }
2935
2936 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2937 {
2938         struct e1000_hw *hw =
2939                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940         struct e1000_vfta * shadow_vfta =
2941                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2942         int i = 0, j = 0, vfta = 0, mask = 1;
2943
2944         for (i = 0; i < IGB_VFTA_SIZE; i++){
2945                 vfta = shadow_vfta->vfta[i];
2946                 if(vfta){
2947                         mask = 1;
2948                         for (j = 0; j < 32; j++){
2949                                 if(vfta & mask)
2950                                         igbvf_set_vfta(hw,
2951                                                 (uint16_t)((i<<5)+j), on);
2952                                 mask<<=1;
2953                         }
2954                 }
2955         }
2956
2957 }
2958
2959 static int
2960 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2961 {
2962         struct e1000_hw *hw =
2963                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         struct e1000_vfta * shadow_vfta =
2965                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2966         uint32_t vid_idx = 0;
2967         uint32_t vid_bit = 0;
2968         int ret = 0;
2969
2970         PMD_INIT_FUNC_TRACE();
2971
2972         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2973         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2974         if(ret){
2975                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2976                 return ret;
2977         }
2978         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2979         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2980
2981         /*Save what we set and retore it after device reset*/
2982         if (on)
2983                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2984         else
2985                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2986
2987         return 0;
2988 }
2989
2990 static void
2991 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2992 {
2993         struct e1000_hw *hw =
2994                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995
2996         /* index is not used by rar_set() */
2997         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2998 }
2999
3000
3001 static int
3002 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3003                         struct rte_eth_rss_reta_entry64 *reta_conf,
3004                         uint16_t reta_size)
3005 {
3006         uint8_t i, j, mask;
3007         uint32_t reta, r;
3008         uint16_t idx, shift;
3009         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010
3011         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3012                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3013                         "(%d) doesn't match the number hardware can supported "
3014                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3015                 return -EINVAL;
3016         }
3017
3018         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3019                 idx = i / RTE_RETA_GROUP_SIZE;
3020                 shift = i % RTE_RETA_GROUP_SIZE;
3021                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3022                                                 IGB_4_BIT_MASK);
3023                 if (!mask)
3024                         continue;
3025                 if (mask == IGB_4_BIT_MASK)
3026                         r = 0;
3027                 else
3028                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3029                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3030                         if (mask & (0x1 << j))
3031                                 reta |= reta_conf[idx].reta[shift + j] <<
3032                                                         (CHAR_BIT * j);
3033                         else
3034                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3035                 }
3036                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3037         }
3038
3039         return 0;
3040 }
3041
3042 static int
3043 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3044                        struct rte_eth_rss_reta_entry64 *reta_conf,
3045                        uint16_t reta_size)
3046 {
3047         uint8_t i, j, mask;
3048         uint32_t reta;
3049         uint16_t idx, shift;
3050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051
3052         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3053                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3054                         "(%d) doesn't match the number hardware can supported "
3055                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3056                 return -EINVAL;
3057         }
3058
3059         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3060                 idx = i / RTE_RETA_GROUP_SIZE;
3061                 shift = i % RTE_RETA_GROUP_SIZE;
3062                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3063                                                 IGB_4_BIT_MASK);
3064                 if (!mask)
3065                         continue;
3066                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3067                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3068                         if (mask & (0x1 << j))
3069                                 reta_conf[idx].reta[shift + j] =
3070                                         ((reta >> (CHAR_BIT * j)) &
3071                                                 IGB_8_BIT_MASK);
3072                 }
3073         }
3074
3075         return 0;
3076 }
3077
3078 #define MAC_TYPE_FILTER_SUP(type)    do {\
3079         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3080                 (type) != e1000_82576)\
3081                 return -ENOTSUP;\
3082 } while (0)
3083
3084 static int
3085 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3086                         struct rte_eth_syn_filter *filter,
3087                         bool add)
3088 {
3089         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3090         uint32_t synqf, rfctl;
3091
3092         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3093                 return -EINVAL;
3094
3095         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3096
3097         if (add) {
3098                 if (synqf & E1000_SYN_FILTER_ENABLE)
3099                         return -EINVAL;
3100
3101                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3102                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3103
3104                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3105                 if (filter->hig_pri)
3106                         rfctl |= E1000_RFCTL_SYNQFP;
3107                 else
3108                         rfctl &= ~E1000_RFCTL_SYNQFP;
3109
3110                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3111         } else {
3112                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3113                         return -ENOENT;
3114                 synqf = 0;
3115         }
3116
3117         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3118         E1000_WRITE_FLUSH(hw);
3119         return 0;
3120 }
3121
3122 static int
3123 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3124                         struct rte_eth_syn_filter *filter)
3125 {
3126         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3127         uint32_t synqf, rfctl;
3128
3129         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3130         if (synqf & E1000_SYN_FILTER_ENABLE) {
3131                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3132                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3133                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3134                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3135                 return 0;
3136         }
3137
3138         return -ENOENT;
3139 }
3140
3141 static int
3142 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3143                         enum rte_filter_op filter_op,
3144                         void *arg)
3145 {
3146         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3147         int ret;
3148
3149         MAC_TYPE_FILTER_SUP(hw->mac.type);
3150
3151         if (filter_op == RTE_ETH_FILTER_NOP)
3152                 return 0;
3153
3154         if (arg == NULL) {
3155                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3156                             filter_op);
3157                 return -EINVAL;
3158         }
3159
3160         switch (filter_op) {
3161         case RTE_ETH_FILTER_ADD:
3162                 ret = eth_igb_syn_filter_set(dev,
3163                                 (struct rte_eth_syn_filter *)arg,
3164                                 TRUE);
3165                 break;
3166         case RTE_ETH_FILTER_DELETE:
3167                 ret = eth_igb_syn_filter_set(dev,
3168                                 (struct rte_eth_syn_filter *)arg,
3169                                 FALSE);
3170                 break;
3171         case RTE_ETH_FILTER_GET:
3172                 ret = eth_igb_syn_filter_get(dev,
3173                                 (struct rte_eth_syn_filter *)arg);
3174                 break;
3175         default:
3176                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3177                 ret = -EINVAL;
3178                 break;
3179         }
3180
3181         return ret;
3182 }
3183
3184 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3185         if ((type) != e1000_82580 && (type) != e1000_i350)\
3186                 return -ENOSYS; \
3187 } while (0)
3188
3189 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3190 static inline int
3191 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3192                         struct e1000_2tuple_filter_info *filter_info)
3193 {
3194         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3195                 return -EINVAL;
3196         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3197                 return -EINVAL;  /* filter index is out of range. */
3198         if (filter->tcp_flags > TCP_FLAG_ALL)
3199                 return -EINVAL;  /* flags is invalid. */
3200
3201         switch (filter->dst_port_mask) {
3202         case UINT16_MAX:
3203                 filter_info->dst_port_mask = 0;
3204                 filter_info->dst_port = filter->dst_port;
3205                 break;
3206         case 0:
3207                 filter_info->dst_port_mask = 1;
3208                 break;
3209         default:
3210                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3211                 return -EINVAL;
3212         }
3213
3214         switch (filter->proto_mask) {
3215         case UINT8_MAX:
3216                 filter_info->proto_mask = 0;
3217                 filter_info->proto = filter->proto;
3218                 break;
3219         case 0:
3220                 filter_info->proto_mask = 1;
3221                 break;
3222         default:
3223                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3224                 return -EINVAL;
3225         }
3226
3227         filter_info->priority = (uint8_t)filter->priority;
3228         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3229                 filter_info->tcp_flags = filter->tcp_flags;
3230         else
3231                 filter_info->tcp_flags = 0;
3232
3233         return 0;
3234 }
3235
3236 static inline struct e1000_2tuple_filter *
3237 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3238                         struct e1000_2tuple_filter_info *key)
3239 {
3240         struct e1000_2tuple_filter *it;
3241
3242         TAILQ_FOREACH(it, filter_list, entries) {
3243                 if (memcmp(key, &it->filter_info,
3244                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3245                         return it;
3246                 }
3247         }
3248         return NULL;
3249 }
3250
3251 /*
3252  * igb_add_2tuple_filter - add a 2tuple filter
3253  *
3254  * @param
3255  * dev: Pointer to struct rte_eth_dev.
3256  * ntuple_filter: ponter to the filter that will be added.
3257  *
3258  * @return
3259  *    - On success, zero.
3260  *    - On failure, a negative value.
3261  */
3262 static int
3263 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3264                         struct rte_eth_ntuple_filter *ntuple_filter)
3265 {
3266         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3267         struct e1000_filter_info *filter_info =
3268                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3269         struct e1000_2tuple_filter *filter;
3270         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3271         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3272         int i, ret;
3273
3274         filter = rte_zmalloc("e1000_2tuple_filter",
3275                         sizeof(struct e1000_2tuple_filter), 0);
3276         if (filter == NULL)
3277                 return -ENOMEM;
3278
3279         ret = ntuple_filter_to_2tuple(ntuple_filter,
3280                                       &filter->filter_info);
3281         if (ret < 0) {
3282                 rte_free(filter);
3283                 return ret;
3284         }
3285         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3286                                          &filter->filter_info) != NULL) {
3287                 PMD_DRV_LOG(ERR, "filter exists.");
3288                 rte_free(filter);
3289                 return -EEXIST;
3290         }
3291         filter->queue = ntuple_filter->queue;
3292
3293         /*
3294          * look for an unused 2tuple filter index,
3295          * and insert the filter to list.
3296          */
3297         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3298                 if (!(filter_info->twotuple_mask & (1 << i))) {
3299                         filter_info->twotuple_mask |= 1 << i;
3300                         filter->index = i;
3301                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3302                                           filter,
3303                                           entries);
3304                         break;
3305                 }
3306         }
3307         if (i >= E1000_MAX_TTQF_FILTERS) {
3308                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3309                 rte_free(filter);
3310                 return -ENOSYS;
3311         }
3312
3313         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3314         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3315                 imir |= E1000_IMIR_PORT_BP;
3316         else
3317                 imir &= ~E1000_IMIR_PORT_BP;
3318
3319         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3320
3321         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3322         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3323         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3324         if (filter->filter_info.proto_mask == 0)
3325                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3326
3327         /* tcp flags bits setting. */
3328         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3329                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3330                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3331                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3332                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3333                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3334                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3335                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3336                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3337                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3338                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3339                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3340                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3341         } else
3342                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3343         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3344         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3345         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3346         return 0;
3347 }
3348
3349 /*
3350  * igb_remove_2tuple_filter - remove a 2tuple filter
3351  *
3352  * @param
3353  * dev: Pointer to struct rte_eth_dev.
3354  * ntuple_filter: ponter to the filter that will be removed.
3355  *
3356  * @return
3357  *    - On success, zero.
3358  *    - On failure, a negative value.
3359  */
3360 static int
3361 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3362                         struct rte_eth_ntuple_filter *ntuple_filter)
3363 {
3364         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365         struct e1000_filter_info *filter_info =
3366                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3367         struct e1000_2tuple_filter_info filter_2tuple;
3368         struct e1000_2tuple_filter *filter;
3369         int ret;
3370
3371         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3372         ret = ntuple_filter_to_2tuple(ntuple_filter,
3373                                       &filter_2tuple);
3374         if (ret < 0)
3375                 return ret;
3376
3377         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3378                                          &filter_2tuple);
3379         if (filter == NULL) {
3380                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3381                 return -ENOENT;
3382         }
3383
3384         filter_info->twotuple_mask &= ~(1 << filter->index);
3385         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3386         rte_free(filter);
3387
3388         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3389         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3390         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3391         return 0;
3392 }
3393
3394 static inline struct e1000_flex_filter *
3395 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3396                         struct e1000_flex_filter_info *key)
3397 {
3398         struct e1000_flex_filter *it;
3399
3400         TAILQ_FOREACH(it, filter_list, entries) {
3401                 if (memcmp(key, &it->filter_info,
3402                         sizeof(struct e1000_flex_filter_info)) == 0)
3403                         return it;
3404         }
3405
3406         return NULL;
3407 }
3408
3409 static int
3410 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3411                         struct rte_eth_flex_filter *filter,
3412                         bool add)
3413 {
3414         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3415         struct e1000_filter_info *filter_info =
3416                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3417         struct e1000_flex_filter *flex_filter, *it;
3418         uint32_t wufc, queueing, mask;
3419         uint32_t reg_off;
3420         uint8_t shift, i, j = 0;
3421
3422         flex_filter = rte_zmalloc("e1000_flex_filter",
3423                         sizeof(struct e1000_flex_filter), 0);
3424         if (flex_filter == NULL)
3425                 return -ENOMEM;
3426
3427         flex_filter->filter_info.len = filter->len;
3428         flex_filter->filter_info.priority = filter->priority;
3429         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3430         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3431                 mask = 0;
3432                 /* reverse bits in flex filter's mask*/
3433                 for (shift = 0; shift < CHAR_BIT; shift++) {
3434                         if (filter->mask[i] & (0x01 << shift))
3435                                 mask |= (0x80 >> shift);
3436                 }
3437                 flex_filter->filter_info.mask[i] = mask;
3438         }
3439
3440         wufc = E1000_READ_REG(hw, E1000_WUFC);
3441         if (flex_filter->index < E1000_MAX_FHFT)
3442                 reg_off = E1000_FHFT(flex_filter->index);
3443         else
3444                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3445
3446         if (add) {
3447                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3448                                 &flex_filter->filter_info) != NULL) {
3449                         PMD_DRV_LOG(ERR, "filter exists.");
3450                         rte_free(flex_filter);
3451                         return -EEXIST;
3452                 }
3453                 flex_filter->queue = filter->queue;
3454                 /*
3455                  * look for an unused flex filter index
3456                  * and insert the filter into the list.
3457                  */
3458                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3459                         if (!(filter_info->flex_mask & (1 << i))) {
3460                                 filter_info->flex_mask |= 1 << i;
3461                                 flex_filter->index = i;
3462                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3463                                         flex_filter,
3464                                         entries);
3465                                 break;
3466                         }
3467                 }
3468                 if (i >= E1000_MAX_FLEX_FILTERS) {
3469                         PMD_DRV_LOG(ERR, "flex filters are full.");
3470                         rte_free(flex_filter);
3471                         return -ENOSYS;
3472                 }
3473
3474                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3475                                 (E1000_WUFC_FLX0 << flex_filter->index));
3476                 queueing = filter->len |
3477                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3478                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3479                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3480                                 queueing);
3481                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3482                         E1000_WRITE_REG(hw, reg_off,
3483                                         flex_filter->filter_info.dwords[j]);
3484                         reg_off += sizeof(uint32_t);
3485                         E1000_WRITE_REG(hw, reg_off,
3486                                         flex_filter->filter_info.dwords[++j]);
3487                         reg_off += sizeof(uint32_t);
3488                         E1000_WRITE_REG(hw, reg_off,
3489                                 (uint32_t)flex_filter->filter_info.mask[i]);
3490                         reg_off += sizeof(uint32_t) * 2;
3491                         ++j;
3492                 }
3493         } else {
3494                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3495                                 &flex_filter->filter_info);
3496                 if (it == NULL) {
3497                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3498                         rte_free(flex_filter);
3499                         return -ENOENT;
3500                 }
3501
3502                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3503                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3504                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3505                         (~(E1000_WUFC_FLX0 << it->index)));
3506
3507                 filter_info->flex_mask &= ~(1 << it->index);
3508                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3509                 rte_free(it);
3510                 rte_free(flex_filter);
3511         }
3512
3513         return 0;
3514 }
3515
3516 static int
3517 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3518                         struct rte_eth_flex_filter *filter)
3519 {
3520         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521         struct e1000_filter_info *filter_info =
3522                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3523         struct e1000_flex_filter flex_filter, *it;
3524         uint32_t wufc, queueing, wufc_en = 0;
3525
3526         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3527         flex_filter.filter_info.len = filter->len;
3528         flex_filter.filter_info.priority = filter->priority;
3529         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3530         memcpy(flex_filter.filter_info.mask, filter->mask,
3531                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3532
3533         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3534                                 &flex_filter.filter_info);
3535         if (it == NULL) {
3536                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3537                 return -ENOENT;
3538         }
3539
3540         wufc = E1000_READ_REG(hw, E1000_WUFC);
3541         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3542
3543         if ((wufc & wufc_en) == wufc_en) {
3544                 uint32_t reg_off = 0;
3545                 if (it->index < E1000_MAX_FHFT)
3546                         reg_off = E1000_FHFT(it->index);
3547                 else
3548                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3549
3550                 queueing = E1000_READ_REG(hw,
3551                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3552                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3553                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3554                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3555                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3556                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3557                 return 0;
3558         }
3559         return -ENOENT;
3560 }
3561
3562 static int
3563 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3564                         enum rte_filter_op filter_op,
3565                         void *arg)
3566 {
3567         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3568         struct rte_eth_flex_filter *filter;
3569         int ret = 0;
3570
3571         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3572
3573         if (filter_op == RTE_ETH_FILTER_NOP)
3574                 return ret;
3575
3576         if (arg == NULL) {
3577                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3578                             filter_op);
3579                 return -EINVAL;
3580         }
3581
3582         filter = (struct rte_eth_flex_filter *)arg;
3583         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3584             || filter->len % sizeof(uint64_t) != 0) {
3585                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3586                 return -EINVAL;
3587         }
3588         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3589                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3590                 return -EINVAL;
3591         }
3592
3593         switch (filter_op) {
3594         case RTE_ETH_FILTER_ADD:
3595                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3596                 break;
3597         case RTE_ETH_FILTER_DELETE:
3598                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3599                 break;
3600         case RTE_ETH_FILTER_GET:
3601                 ret = eth_igb_get_flex_filter(dev, filter);
3602                 break;
3603         default:
3604                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3605                 ret = -EINVAL;
3606                 break;
3607         }
3608
3609         return ret;
3610 }
3611
3612 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3613 static inline int
3614 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3615                         struct e1000_5tuple_filter_info *filter_info)
3616 {
3617         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3618                 return -EINVAL;
3619         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3620                 return -EINVAL;  /* filter index is out of range. */
3621         if (filter->tcp_flags > TCP_FLAG_ALL)
3622                 return -EINVAL;  /* flags is invalid. */
3623
3624         switch (filter->dst_ip_mask) {
3625         case UINT32_MAX:
3626                 filter_info->dst_ip_mask = 0;
3627                 filter_info->dst_ip = filter->dst_ip;
3628                 break;
3629         case 0:
3630                 filter_info->dst_ip_mask = 1;
3631                 break;
3632         default:
3633                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3634                 return -EINVAL;
3635         }
3636
3637         switch (filter->src_ip_mask) {
3638         case UINT32_MAX:
3639                 filter_info->src_ip_mask = 0;
3640                 filter_info->src_ip = filter->src_ip;
3641                 break;
3642         case 0:
3643                 filter_info->src_ip_mask = 1;
3644                 break;
3645         default:
3646                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3647                 return -EINVAL;
3648         }
3649
3650         switch (filter->dst_port_mask) {
3651         case UINT16_MAX:
3652                 filter_info->dst_port_mask = 0;
3653                 filter_info->dst_port = filter->dst_port;
3654                 break;
3655         case 0:
3656                 filter_info->dst_port_mask = 1;
3657                 break;
3658         default:
3659                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3660                 return -EINVAL;
3661         }
3662
3663         switch (filter->src_port_mask) {
3664         case UINT16_MAX:
3665                 filter_info->src_port_mask = 0;
3666                 filter_info->src_port = filter->src_port;
3667                 break;
3668         case 0:
3669                 filter_info->src_port_mask = 1;
3670                 break;
3671         default:
3672                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3673                 return -EINVAL;
3674         }
3675
3676         switch (filter->proto_mask) {
3677         case UINT8_MAX:
3678                 filter_info->proto_mask = 0;
3679                 filter_info->proto = filter->proto;
3680                 break;
3681         case 0:
3682                 filter_info->proto_mask = 1;
3683                 break;
3684         default:
3685                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3686                 return -EINVAL;
3687         }
3688
3689         filter_info->priority = (uint8_t)filter->priority;
3690         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3691                 filter_info->tcp_flags = filter->tcp_flags;
3692         else
3693                 filter_info->tcp_flags = 0;
3694
3695         return 0;
3696 }
3697
3698 static inline struct e1000_5tuple_filter *
3699 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3700                         struct e1000_5tuple_filter_info *key)
3701 {
3702         struct e1000_5tuple_filter *it;
3703
3704         TAILQ_FOREACH(it, filter_list, entries) {
3705                 if (memcmp(key, &it->filter_info,
3706                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3707                         return it;
3708                 }
3709         }
3710         return NULL;
3711 }
3712
3713 /*
3714  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3715  *
3716  * @param
3717  * dev: Pointer to struct rte_eth_dev.
3718  * ntuple_filter: ponter to the filter that will be added.
3719  *
3720  * @return
3721  *    - On success, zero.
3722  *    - On failure, a negative value.
3723  */
3724 static int
3725 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3726                         struct rte_eth_ntuple_filter *ntuple_filter)
3727 {
3728         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         struct e1000_filter_info *filter_info =
3730                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3731         struct e1000_5tuple_filter *filter;
3732         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3733         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3734         uint8_t i;
3735         int ret;
3736
3737         filter = rte_zmalloc("e1000_5tuple_filter",
3738                         sizeof(struct e1000_5tuple_filter), 0);
3739         if (filter == NULL)
3740                 return -ENOMEM;
3741
3742         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3743                                             &filter->filter_info);
3744         if (ret < 0) {
3745                 rte_free(filter);
3746                 return ret;
3747         }
3748
3749         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3750                                          &filter->filter_info) != NULL) {
3751                 PMD_DRV_LOG(ERR, "filter exists.");
3752                 rte_free(filter);
3753                 return -EEXIST;
3754         }
3755         filter->queue = ntuple_filter->queue;
3756
3757         /*
3758          * look for an unused 5tuple filter index,
3759          * and insert the filter to list.
3760          */
3761         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3762                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3763                         filter_info->fivetuple_mask |= 1 << i;
3764                         filter->index = i;
3765                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3766                                           filter,
3767                                           entries);
3768                         break;
3769                 }
3770         }
3771         if (i >= E1000_MAX_FTQF_FILTERS) {
3772                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3773                 rte_free(filter);
3774                 return -ENOSYS;
3775         }
3776
3777         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3778         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3779                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3780         if (filter->filter_info.dst_ip_mask == 0)
3781                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3782         if (filter->filter_info.src_port_mask == 0)
3783                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3784         if (filter->filter_info.proto_mask == 0)
3785                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3786         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3787                 E1000_FTQF_QUEUE_MASK;
3788         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3789         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3790         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3791         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3792
3793         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3794         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3795
3796         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3797         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3798                 imir |= E1000_IMIR_PORT_BP;
3799         else
3800                 imir &= ~E1000_IMIR_PORT_BP;
3801         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3802
3803         /* tcp flags bits setting. */
3804         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3805                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3806                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3807                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3808                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3809                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3810                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3811                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3812                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3813                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3814                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3815                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3816                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3817         } else
3818                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3819         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3820         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3821         return 0;
3822 }
3823
3824 /*
3825  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3826  *
3827  * @param
3828  * dev: Pointer to struct rte_eth_dev.
3829  * ntuple_filter: ponter to the filter that will be removed.
3830  *
3831  * @return
3832  *    - On success, zero.
3833  *    - On failure, a negative value.
3834  */
3835 static int
3836 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3837                                 struct rte_eth_ntuple_filter *ntuple_filter)
3838 {
3839         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         struct e1000_filter_info *filter_info =
3841                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3842         struct e1000_5tuple_filter_info filter_5tuple;
3843         struct e1000_5tuple_filter *filter;
3844         int ret;
3845
3846         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3847         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3848                                             &filter_5tuple);
3849         if (ret < 0)
3850                 return ret;
3851
3852         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3853                                          &filter_5tuple);
3854         if (filter == NULL) {
3855                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3856                 return -ENOENT;
3857         }
3858
3859         filter_info->fivetuple_mask &= ~(1 << filter->index);
3860         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3861         rte_free(filter);
3862
3863         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3864                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3865         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3866         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3867         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3868         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3869         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3870         return 0;
3871 }
3872
3873 static int
3874 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3875 {
3876         uint32_t rctl;
3877         struct e1000_hw *hw;
3878         struct rte_eth_dev_info dev_info;
3879         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3880                                      VLAN_TAG_SIZE);
3881
3882         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3883
3884 #ifdef RTE_LIBRTE_82571_SUPPORT
3885         /* XXX: not bigger than max_rx_pktlen */
3886         if (hw->mac.type == e1000_82571)
3887                 return -ENOTSUP;
3888 #endif
3889         eth_igb_infos_get(dev, &dev_info);
3890
3891         /* check that mtu is within the allowed range */
3892         if ((mtu < ETHER_MIN_MTU) ||
3893             (frame_size > dev_info.max_rx_pktlen))
3894                 return -EINVAL;
3895
3896         /* refuse mtu that requires the support of scattered packets when this
3897          * feature has not been enabled before. */
3898         if (!dev->data->scattered_rx &&
3899             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3900                 return -EINVAL;
3901
3902         rctl = E1000_READ_REG(hw, E1000_RCTL);
3903
3904         /* switch to jumbo mode if needed */
3905         if (frame_size > ETHER_MAX_LEN) {
3906                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3907                 rctl |= E1000_RCTL_LPE;
3908         } else {
3909                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3910                 rctl &= ~E1000_RCTL_LPE;
3911         }
3912         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3913
3914         /* update max frame size */
3915         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3916
3917         E1000_WRITE_REG(hw, E1000_RLPML,
3918                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3919
3920         return 0;
3921 }
3922
3923 /*
3924  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3925  *
3926  * @param
3927  * dev: Pointer to struct rte_eth_dev.
3928  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3929  * add: if true, add filter, if false, remove filter
3930  *
3931  * @return
3932  *    - On success, zero.
3933  *    - On failure, a negative value.
3934  */
3935 static int
3936 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3937                         struct rte_eth_ntuple_filter *ntuple_filter,
3938                         bool add)
3939 {
3940         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941         int ret;
3942
3943         switch (ntuple_filter->flags) {
3944         case RTE_5TUPLE_FLAGS:
3945         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3946                 if (hw->mac.type != e1000_82576)
3947                         return -ENOTSUP;
3948                 if (add)
3949                         ret = igb_add_5tuple_filter_82576(dev,
3950                                                           ntuple_filter);
3951                 else
3952                         ret = igb_remove_5tuple_filter_82576(dev,
3953                                                              ntuple_filter);
3954                 break;
3955         case RTE_2TUPLE_FLAGS:
3956         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3957                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3958                         return -ENOTSUP;
3959                 if (add)
3960                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3961                 else
3962                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3963                 break;
3964         default:
3965                 ret = -EINVAL;
3966                 break;
3967         }
3968
3969         return ret;
3970 }
3971
3972 /*
3973  * igb_get_ntuple_filter - get a ntuple filter
3974  *
3975  * @param
3976  * dev: Pointer to struct rte_eth_dev.
3977  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3978  *
3979  * @return
3980  *    - On success, zero.
3981  *    - On failure, a negative value.
3982  */
3983 static int
3984 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3985                         struct rte_eth_ntuple_filter *ntuple_filter)
3986 {
3987         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988         struct e1000_filter_info *filter_info =
3989                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3990         struct e1000_5tuple_filter_info filter_5tuple;
3991         struct e1000_2tuple_filter_info filter_2tuple;
3992         struct e1000_5tuple_filter *p_5tuple_filter;
3993         struct e1000_2tuple_filter *p_2tuple_filter;
3994         int ret;
3995
3996         switch (ntuple_filter->flags) {
3997         case RTE_5TUPLE_FLAGS:
3998         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3999                 if (hw->mac.type != e1000_82576)
4000                         return -ENOTSUP;
4001                 memset(&filter_5tuple,
4002                         0,
4003                         sizeof(struct e1000_5tuple_filter_info));
4004                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4005                                                     &filter_5tuple);
4006                 if (ret < 0)
4007                         return ret;
4008                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4009                                         &filter_info->fivetuple_list,
4010                                         &filter_5tuple);
4011                 if (p_5tuple_filter == NULL) {
4012                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4013                         return -ENOENT;
4014                 }
4015                 ntuple_filter->queue = p_5tuple_filter->queue;
4016                 break;
4017         case RTE_2TUPLE_FLAGS:
4018         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4019                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4020                         return -ENOTSUP;
4021                 memset(&filter_2tuple,
4022                         0,
4023                         sizeof(struct e1000_2tuple_filter_info));
4024                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4025                 if (ret < 0)
4026                         return ret;
4027                 p_2tuple_filter = igb_2tuple_filter_lookup(
4028                                         &filter_info->twotuple_list,
4029                                         &filter_2tuple);
4030                 if (p_2tuple_filter == NULL) {
4031                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4032                         return -ENOENT;
4033                 }
4034                 ntuple_filter->queue = p_2tuple_filter->queue;
4035                 break;
4036         default:
4037                 ret = -EINVAL;
4038                 break;
4039         }
4040
4041         return 0;
4042 }
4043
4044 /*
4045  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4046  * @dev: pointer to rte_eth_dev structure
4047  * @filter_op:operation will be taken.
4048  * @arg: a pointer to specific structure corresponding to the filter_op
4049  */
4050 static int
4051 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4052                                 enum rte_filter_op filter_op,
4053                                 void *arg)
4054 {
4055         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4056         int ret;
4057
4058         MAC_TYPE_FILTER_SUP(hw->mac.type);
4059
4060         if (filter_op == RTE_ETH_FILTER_NOP)
4061                 return 0;
4062
4063         if (arg == NULL) {
4064                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4065                             filter_op);
4066                 return -EINVAL;
4067         }
4068
4069         switch (filter_op) {
4070         case RTE_ETH_FILTER_ADD:
4071                 ret = igb_add_del_ntuple_filter(dev,
4072                         (struct rte_eth_ntuple_filter *)arg,
4073                         TRUE);
4074                 break;
4075         case RTE_ETH_FILTER_DELETE:
4076                 ret = igb_add_del_ntuple_filter(dev,
4077                         (struct rte_eth_ntuple_filter *)arg,
4078                         FALSE);
4079                 break;
4080         case RTE_ETH_FILTER_GET:
4081                 ret = igb_get_ntuple_filter(dev,
4082                         (struct rte_eth_ntuple_filter *)arg);
4083                 break;
4084         default:
4085                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4086                 ret = -EINVAL;
4087                 break;
4088         }
4089         return ret;
4090 }
4091
4092 static inline int
4093 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4094                         uint16_t ethertype)
4095 {
4096         int i;
4097
4098         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4099                 if (filter_info->ethertype_filters[i] == ethertype &&
4100                     (filter_info->ethertype_mask & (1 << i)))
4101                         return i;
4102         }
4103         return -1;
4104 }
4105
4106 static inline int
4107 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4108                         uint16_t ethertype)
4109 {
4110         int i;
4111
4112         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4113                 if (!(filter_info->ethertype_mask & (1 << i))) {
4114                         filter_info->ethertype_mask |= 1 << i;
4115                         filter_info->ethertype_filters[i] = ethertype;
4116                         return i;
4117                 }
4118         }
4119         return -1;
4120 }
4121
4122 static inline int
4123 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4124                         uint8_t idx)
4125 {
4126         if (idx >= E1000_MAX_ETQF_FILTERS)
4127                 return -1;
4128         filter_info->ethertype_mask &= ~(1 << idx);
4129         filter_info->ethertype_filters[idx] = 0;
4130         return idx;
4131 }
4132
4133
4134 static int
4135 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4136                         struct rte_eth_ethertype_filter *filter,
4137                         bool add)
4138 {
4139         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         struct e1000_filter_info *filter_info =
4141                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4142         uint32_t etqf = 0;
4143         int ret;
4144
4145         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4146                 filter->ether_type == ETHER_TYPE_IPv6) {
4147                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4148                         " ethertype filter.", filter->ether_type);
4149                 return -EINVAL;
4150         }
4151
4152         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4153                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4154                 return -EINVAL;
4155         }
4156         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4157                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4158                 return -EINVAL;
4159         }
4160
4161         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4162         if (ret >= 0 && add) {
4163                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4164                             filter->ether_type);
4165                 return -EEXIST;
4166         }
4167         if (ret < 0 && !add) {
4168                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4169                             filter->ether_type);
4170                 return -ENOENT;
4171         }
4172
4173         if (add) {
4174                 ret = igb_ethertype_filter_insert(filter_info,
4175                         filter->ether_type);
4176                 if (ret < 0) {
4177                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4178                         return -ENOSYS;
4179                 }
4180
4181                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4182                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4183                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4184         } else {
4185                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4186                 if (ret < 0)
4187                         return -ENOSYS;
4188         }
4189         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4190         E1000_WRITE_FLUSH(hw);
4191
4192         return 0;
4193 }
4194
4195 static int
4196 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4197                         struct rte_eth_ethertype_filter *filter)
4198 {
4199         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200         struct e1000_filter_info *filter_info =
4201                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4202         uint32_t etqf;
4203         int ret;
4204
4205         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4206         if (ret < 0) {
4207                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4208                             filter->ether_type);
4209                 return -ENOENT;
4210         }
4211
4212         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4213         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4214                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4215                 filter->flags = 0;
4216                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4217                                 E1000_ETQF_QUEUE_SHIFT;
4218                 return 0;
4219         }
4220
4221         return -ENOENT;
4222 }
4223
4224 /*
4225  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4226  * @dev: pointer to rte_eth_dev structure
4227  * @filter_op:operation will be taken.
4228  * @arg: a pointer to specific structure corresponding to the filter_op
4229  */
4230 static int
4231 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4232                                 enum rte_filter_op filter_op,
4233                                 void *arg)
4234 {
4235         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236         int ret;
4237
4238         MAC_TYPE_FILTER_SUP(hw->mac.type);
4239
4240         if (filter_op == RTE_ETH_FILTER_NOP)
4241                 return 0;
4242
4243         if (arg == NULL) {
4244                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4245                             filter_op);
4246                 return -EINVAL;
4247         }
4248
4249         switch (filter_op) {
4250         case RTE_ETH_FILTER_ADD:
4251                 ret = igb_add_del_ethertype_filter(dev,
4252                         (struct rte_eth_ethertype_filter *)arg,
4253                         TRUE);
4254                 break;
4255         case RTE_ETH_FILTER_DELETE:
4256                 ret = igb_add_del_ethertype_filter(dev,
4257                         (struct rte_eth_ethertype_filter *)arg,
4258                         FALSE);
4259                 break;
4260         case RTE_ETH_FILTER_GET:
4261                 ret = igb_get_ethertype_filter(dev,
4262                         (struct rte_eth_ethertype_filter *)arg);
4263                 break;
4264         default:
4265                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4266                 ret = -EINVAL;
4267                 break;
4268         }
4269         return ret;
4270 }
4271
4272 static int
4273 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4274                      enum rte_filter_type filter_type,
4275                      enum rte_filter_op filter_op,
4276                      void *arg)
4277 {
4278         int ret = -EINVAL;
4279
4280         switch (filter_type) {
4281         case RTE_ETH_FILTER_NTUPLE:
4282                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4283                 break;
4284         case RTE_ETH_FILTER_ETHERTYPE:
4285                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4286                 break;
4287         case RTE_ETH_FILTER_SYN:
4288                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4289                 break;
4290         case RTE_ETH_FILTER_FLEXIBLE:
4291                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4292                 break;
4293         default:
4294                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4295                                                         filter_type);
4296                 break;
4297         }
4298
4299         return ret;
4300 }
4301
4302 static int
4303 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4304                          struct ether_addr *mc_addr_set,
4305                          uint32_t nb_mc_addr)
4306 {
4307         struct e1000_hw *hw;
4308
4309         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4310         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4311         return 0;
4312 }
4313
4314 static uint64_t
4315 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4316 {
4317         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4318         uint64_t systime_cycles;
4319
4320         switch (hw->mac.type) {
4321         case e1000_i210:
4322         case e1000_i211:
4323                 /*
4324                  * Need to read System Time Residue Register to be able
4325                  * to read the other two registers.
4326                  */
4327                 E1000_READ_REG(hw, E1000_SYSTIMR);
4328                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4329                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4330                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4331                                 * NSEC_PER_SEC;
4332                 break;
4333         case e1000_82580:
4334         case e1000_i350:
4335         case e1000_i354:
4336                 /*
4337                  * Need to read System Time Residue Register to be able
4338                  * to read the other two registers.
4339                  */
4340                 E1000_READ_REG(hw, E1000_SYSTIMR);
4341                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4342                 /* Only the 8 LSB are valid. */
4343                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4344                                 & 0xff) << 32;
4345                 break;
4346         default:
4347                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4348                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4349                                 << 32;
4350                 break;
4351         }
4352
4353         return systime_cycles;
4354 }
4355
4356 static uint64_t
4357 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4358 {
4359         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         uint64_t rx_tstamp_cycles;
4361
4362         switch (hw->mac.type) {
4363         case e1000_i210:
4364         case e1000_i211:
4365                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4366                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4367                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4368                                 * NSEC_PER_SEC;
4369                 break;
4370         case e1000_82580:
4371         case e1000_i350:
4372         case e1000_i354:
4373                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4374                 /* Only the 8 LSB are valid. */
4375                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4376                                 & 0xff) << 32;
4377                 break;
4378         default:
4379                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4380                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4381                                 << 32;
4382                 break;
4383         }
4384
4385         return rx_tstamp_cycles;
4386 }
4387
4388 static uint64_t
4389 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4390 {
4391         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         uint64_t tx_tstamp_cycles;
4393
4394         switch (hw->mac.type) {
4395         case e1000_i210:
4396         case e1000_i211:
4397                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4398                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4399                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4400                                 * NSEC_PER_SEC;
4401                 break;
4402         case e1000_82580:
4403         case e1000_i350:
4404         case e1000_i354:
4405                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4406                 /* Only the 8 LSB are valid. */
4407                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4408                                 & 0xff) << 32;
4409                 break;
4410         default:
4411                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4412                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4413                                 << 32;
4414                 break;
4415         }
4416
4417         return tx_tstamp_cycles;
4418 }
4419
4420 static void
4421 igb_start_timecounters(struct rte_eth_dev *dev)
4422 {
4423         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         struct e1000_adapter *adapter =
4425                 (struct e1000_adapter *)dev->data->dev_private;
4426         uint32_t incval = 1;
4427         uint32_t shift = 0;
4428         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4429
4430         switch (hw->mac.type) {
4431         case e1000_82580:
4432         case e1000_i350:
4433         case e1000_i354:
4434                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4435                 mask = (1ULL << 40) - 1;
4436                 /* fall-through */
4437         case e1000_i210:
4438         case e1000_i211:
4439                 /*
4440                  * Start incrementing the register
4441                  * used to timestamp PTP packets.
4442                  */
4443                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4444                 break;
4445         case e1000_82576:
4446                 incval = E1000_INCVALUE_82576;
4447                 shift = IGB_82576_TSYNC_SHIFT;
4448                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4449                                 E1000_INCPERIOD_82576 | incval);
4450                 break;
4451         default:
4452                 /* Not supported */
4453                 return;
4454         }
4455
4456         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4457         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4458         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4459
4460         adapter->systime_tc.cc_mask = mask;
4461         adapter->systime_tc.cc_shift = shift;
4462         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4463
4464         adapter->rx_tstamp_tc.cc_mask = mask;
4465         adapter->rx_tstamp_tc.cc_shift = shift;
4466         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4467
4468         adapter->tx_tstamp_tc.cc_mask = mask;
4469         adapter->tx_tstamp_tc.cc_shift = shift;
4470         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4471 }
4472
4473 static int
4474 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4475 {
4476         struct e1000_adapter *adapter =
4477                         (struct e1000_adapter *)dev->data->dev_private;
4478
4479         adapter->systime_tc.nsec += delta;
4480         adapter->rx_tstamp_tc.nsec += delta;
4481         adapter->tx_tstamp_tc.nsec += delta;
4482
4483         return 0;
4484 }
4485
4486 static int
4487 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4488 {
4489         uint64_t ns;
4490         struct e1000_adapter *adapter =
4491                         (struct e1000_adapter *)dev->data->dev_private;
4492
4493         ns = rte_timespec_to_ns(ts);
4494
4495         /* Set the timecounters to a new value. */
4496         adapter->systime_tc.nsec = ns;
4497         adapter->rx_tstamp_tc.nsec = ns;
4498         adapter->tx_tstamp_tc.nsec = ns;
4499
4500         return 0;
4501 }
4502
4503 static int
4504 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4505 {
4506         uint64_t ns, systime_cycles;
4507         struct e1000_adapter *adapter =
4508                         (struct e1000_adapter *)dev->data->dev_private;
4509
4510         systime_cycles = igb_read_systime_cyclecounter(dev);
4511         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4512         *ts = rte_ns_to_timespec(ns);
4513
4514         return 0;
4515 }
4516
4517 static int
4518 igb_timesync_enable(struct rte_eth_dev *dev)
4519 {
4520         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4521         uint32_t tsync_ctl;
4522         uint32_t tsauxc;
4523
4524         /* Stop the timesync system time. */
4525         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4526         /* Reset the timesync system time value. */
4527         switch (hw->mac.type) {
4528         case e1000_82580:
4529         case e1000_i350:
4530         case e1000_i354:
4531         case e1000_i210:
4532         case e1000_i211:
4533                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4534                 /* fall-through */
4535         case e1000_82576:
4536                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4537                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4538                 break;
4539         default:
4540                 /* Not supported. */
4541                 return -ENOTSUP;
4542         }
4543
4544         /* Enable system time for it isn't on by default. */
4545         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4546         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4547         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4548
4549         igb_start_timecounters(dev);
4550
4551         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4552         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4553                         (ETHER_TYPE_1588 |
4554                          E1000_ETQF_FILTER_ENABLE |
4555                          E1000_ETQF_1588));
4556
4557         /* Enable timestamping of received PTP packets. */
4558         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4559         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4560         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4561
4562         /* Enable Timestamping of transmitted PTP packets. */
4563         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4564         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4565         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4566
4567         return 0;
4568 }
4569
4570 static int
4571 igb_timesync_disable(struct rte_eth_dev *dev)
4572 {
4573         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4574         uint32_t tsync_ctl;
4575
4576         /* Disable timestamping of transmitted PTP packets. */
4577         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4578         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4579         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4580
4581         /* Disable timestamping of received PTP packets. */
4582         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4583         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4584         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4585
4586         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4587         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4588
4589         /* Stop incrementating the System Time registers. */
4590         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4591
4592         return 0;
4593 }
4594
4595 static int
4596 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4597                                struct timespec *timestamp,
4598                                uint32_t flags __rte_unused)
4599 {
4600         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4601         struct e1000_adapter *adapter =
4602                         (struct e1000_adapter *)dev->data->dev_private;
4603         uint32_t tsync_rxctl;
4604         uint64_t rx_tstamp_cycles;
4605         uint64_t ns;
4606
4607         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4608         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4609                 return -EINVAL;
4610
4611         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4612         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4613         *timestamp = rte_ns_to_timespec(ns);
4614
4615         return  0;
4616 }
4617
4618 static int
4619 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4620                                struct timespec *timestamp)
4621 {
4622         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4623         struct e1000_adapter *adapter =
4624                         (struct e1000_adapter *)dev->data->dev_private;
4625         uint32_t tsync_txctl;
4626         uint64_t tx_tstamp_cycles;
4627         uint64_t ns;
4628
4629         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4630         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4631                 return -EINVAL;
4632
4633         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4634         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4635         *timestamp = rte_ns_to_timespec(ns);
4636
4637         return  0;
4638 }
4639
4640 static int
4641 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4642 {
4643         int count = 0;
4644         int g_ind = 0;
4645         const struct reg_info *reg_group;
4646
4647         while ((reg_group = igb_regs[g_ind++]))
4648                 count += igb_reg_group_count(reg_group);
4649
4650         return count;
4651 }
4652
4653 static int
4654 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4655 {
4656         int count = 0;
4657         int g_ind = 0;
4658         const struct reg_info *reg_group;
4659
4660         while ((reg_group = igbvf_regs[g_ind++]))
4661                 count += igb_reg_group_count(reg_group);
4662
4663         return count;
4664 }
4665
4666 static int
4667 eth_igb_get_regs(struct rte_eth_dev *dev,
4668         struct rte_dev_reg_info *regs)
4669 {
4670         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         uint32_t *data = regs->data;
4672         int g_ind = 0;
4673         int count = 0;
4674         const struct reg_info *reg_group;
4675
4676         /* Support only full register dump */
4677         if ((regs->length == 0) ||
4678             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4679                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4680                         hw->device_id;
4681                 while ((reg_group = igb_regs[g_ind++]))
4682                         count += igb_read_regs_group(dev, &data[count],
4683                                                         reg_group);
4684                 return 0;
4685         }
4686
4687         return -ENOTSUP;
4688 }
4689
4690 static int
4691 igbvf_get_regs(struct rte_eth_dev *dev,
4692         struct rte_dev_reg_info *regs)
4693 {
4694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         uint32_t *data = regs->data;
4696         int g_ind = 0;
4697         int count = 0;
4698         const struct reg_info *reg_group;
4699
4700         /* Support only full register dump */
4701         if ((regs->length == 0) ||
4702             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4703                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4704                         hw->device_id;
4705                 while ((reg_group = igbvf_regs[g_ind++]))
4706                         count += igb_read_regs_group(dev, &data[count],
4707                                                         reg_group);
4708                 return 0;
4709         }
4710
4711         return -ENOTSUP;
4712 }
4713
4714 static int
4715 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4716 {
4717         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718
4719         /* Return unit is byte count */
4720         return hw->nvm.word_size * 2;
4721 }
4722
4723 static int
4724 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4725         struct rte_dev_eeprom_info *in_eeprom)
4726 {
4727         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728         struct e1000_nvm_info *nvm = &hw->nvm;
4729         uint16_t *data = in_eeprom->data;
4730         int first, length;
4731
4732         first = in_eeprom->offset >> 1;
4733         length = in_eeprom->length >> 1;
4734         if ((first >= hw->nvm.word_size) ||
4735             ((first + length) >= hw->nvm.word_size))
4736                 return -EINVAL;
4737
4738         in_eeprom->magic = hw->vendor_id |
4739                 ((uint32_t)hw->device_id << 16);
4740
4741         if ((nvm->ops.read) == NULL)
4742                 return -ENOTSUP;
4743
4744         return nvm->ops.read(hw, first, length, data);
4745 }
4746
4747 static int
4748 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4749         struct rte_dev_eeprom_info *in_eeprom)
4750 {
4751         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4752         struct e1000_nvm_info *nvm = &hw->nvm;
4753         uint16_t *data = in_eeprom->data;
4754         int first, length;
4755
4756         first = in_eeprom->offset >> 1;
4757         length = in_eeprom->length >> 1;
4758         if ((first >= hw->nvm.word_size) ||
4759             ((first + length) >= hw->nvm.word_size))
4760                 return -EINVAL;
4761
4762         in_eeprom->magic = (uint32_t)hw->vendor_id |
4763                 ((uint32_t)hw->device_id << 16);
4764
4765         if ((nvm->ops.write) == NULL)
4766                 return -ENOTSUP;
4767         return nvm->ops.write(hw,  first, length, data);
4768 }
4769
4770 static struct rte_driver pmd_igb_drv = {
4771         .type = PMD_PDEV,
4772         .init = rte_igb_pmd_init,
4773 };
4774
4775 static struct rte_driver pmd_igbvf_drv = {
4776         .type = PMD_PDEV,
4777         .init = rte_igbvf_pmd_init,
4778 };
4779
4780 static int
4781 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4782 {
4783         struct e1000_hw *hw =
4784                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         uint32_t mask = 1 << queue_id;
4786
4787         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4788         E1000_WRITE_FLUSH(hw);
4789
4790         return 0;
4791 }
4792
4793 static int
4794 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4795 {
4796         struct e1000_hw *hw =
4797                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         uint32_t mask = 1 << queue_id;
4799         uint32_t regval;
4800
4801         regval = E1000_READ_REG(hw, E1000_EIMS);
4802         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4803         E1000_WRITE_FLUSH(hw);
4804
4805         rte_intr_enable(&dev->pci_dev->intr_handle);
4806
4807         return 0;
4808 }
4809
4810 static void
4811 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4812                    uint8_t index, uint8_t offset)
4813 {
4814         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4815
4816         /* clear bits */
4817         val &= ~((uint32_t)0xFF << offset);
4818
4819         /* write vector and valid bit */
4820         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4821
4822         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4823 }
4824
4825 static void
4826 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4827                            uint8_t queue, uint8_t msix_vector)
4828 {
4829         uint32_t tmp = 0;
4830
4831         if (hw->mac.type == e1000_82575) {
4832                 if (direction == 0)
4833                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4834                 else if (direction == 1)
4835                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4836                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4837         } else if (hw->mac.type == e1000_82576) {
4838                 if ((direction == 0) || (direction == 1))
4839                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4840                                            ((queue & 0x8) << 1) +
4841                                            8 * direction);
4842         } else if ((hw->mac.type == e1000_82580) ||
4843                         (hw->mac.type == e1000_i350) ||
4844                         (hw->mac.type == e1000_i354) ||
4845                         (hw->mac.type == e1000_i210) ||
4846                         (hw->mac.type == e1000_i211)) {
4847                 if ((direction == 0) || (direction == 1))
4848                         eth_igb_write_ivar(hw, msix_vector,
4849                                            queue >> 1,
4850                                            ((queue & 0x1) << 4) +
4851                                            8 * direction);
4852         }
4853 }
4854
4855 /* Sets up the hardware to generate MSI-X interrupts properly
4856  * @hw
4857  *  board private structure
4858  */
4859 static void
4860 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4861 {
4862         int queue_id;
4863         uint32_t tmpval, regval, intr_mask;
4864         struct e1000_hw *hw =
4865                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866         uint32_t vec = E1000_MISC_VEC_ID;
4867         uint32_t base = E1000_MISC_VEC_ID;
4868         uint32_t misc_shift = 0;
4869
4870         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4871
4872         /* won't configure msix register if no mapping is done
4873          * between intr vector and event fd
4874          */
4875         if (!rte_intr_dp_is_en(intr_handle))
4876                 return;
4877
4878         if (rte_intr_allow_others(intr_handle)) {
4879                 vec = base = E1000_RX_VEC_START;
4880                 misc_shift = 1;
4881         }
4882
4883         /* set interrupt vector for other causes */
4884         if (hw->mac.type == e1000_82575) {
4885                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4886                 /* enable MSI-X PBA support */
4887                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4888
4889                 /* Auto-Mask interrupts upon ICR read */
4890                 tmpval |= E1000_CTRL_EXT_EIAME;
4891                 tmpval |= E1000_CTRL_EXT_IRCA;
4892
4893                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4894
4895                 /* enable msix_other interrupt */
4896                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4897                 regval = E1000_READ_REG(hw, E1000_EIAC);
4898                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4899                 regval = E1000_READ_REG(hw, E1000_EIAM);
4900                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4901         } else if ((hw->mac.type == e1000_82576) ||
4902                         (hw->mac.type == e1000_82580) ||
4903                         (hw->mac.type == e1000_i350) ||
4904                         (hw->mac.type == e1000_i354) ||
4905                         (hw->mac.type == e1000_i210) ||
4906                         (hw->mac.type == e1000_i211)) {
4907                 /* turn on MSI-X capability first */
4908                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4909                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4910                                         E1000_GPIE_NSICR);
4911                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4912                         misc_shift;
4913                 regval = E1000_READ_REG(hw, E1000_EIAC);
4914                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4915
4916                 /* enable msix_other interrupt */
4917                 regval = E1000_READ_REG(hw, E1000_EIMS);
4918                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4919                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4920                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4921         }
4922
4923         /* use EIAM to auto-mask when MSI-X interrupt
4924          * is asserted, this saves a register write for every interrupt
4925          */
4926         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4927                 misc_shift;
4928         regval = E1000_READ_REG(hw, E1000_EIAM);
4929         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4930
4931         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4932                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4933                 intr_handle->intr_vec[queue_id] = vec;
4934                 if (vec < base + intr_handle->nb_efd - 1)
4935                         vec++;
4936         }
4937
4938         E1000_WRITE_FLUSH(hw);
4939 }
4940
4941 PMD_REGISTER_DRIVER(pmd_igb_drv);
4942 PMD_REGISTER_DRIVER(pmd_igbvf_drv);