drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffff
  82 #define E1000_ETQF_FILTER_1588       3
  83 #define IGB_82576_TSYNC_SHIFT        16
  84 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  85 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  86 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  87
  88 static int  eth_igb_configure(struct rte_eth_dev *dev);
  89 static int  eth_igb_start(struct rte_eth_dev *dev);
  90 static void eth_igb_stop(struct rte_eth_dev *dev);
  91 static void eth_igb_close(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  93 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  95 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  96 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  99                                 struct rte_eth_stats *rte_stats);
 100 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 101                               struct rte_eth_xstats *xstats, unsigned n);
 102 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 104 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 105                               struct rte_eth_dev_info *dev_info);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 116 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 117                                                         void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 129 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 130
 131 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 137
 138 static int eth_igb_led_on(struct rte_eth_dev *dev);
 139 static int eth_igb_led_off(struct rte_eth_dev *dev);
 140
 141 static void igb_intr_disable(struct e1000_hw *hw);
 142 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 143 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 144                 struct ether_addr *mac_addr,
 145                 uint32_t index, uint32_t pool);
 146 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 147 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 148                 struct ether_addr *addr);
 149
 150 static void igbvf_intr_disable(struct e1000_hw *hw);
 151 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 152 static int igbvf_dev_start(struct rte_eth_dev *dev);
 153 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 154 static void igbvf_dev_close(struct rte_eth_dev *dev);
 155 static int eth_igbvf_link_update(struct e1000_hw *hw);
 156 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 157                                 struct rte_eth_stats *rte_stats);
 158 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_xstats *xstats, unsigned n);
 160 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 161 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 164 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 165 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 166                 struct ether_addr *addr);
 167 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 168 static int igbvf_get_regs(struct rte_eth_dev *dev,
 169                 struct rte_dev_reg_info *regs);
 170
 171 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 172                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 173                                    uint16_t reta_size);
 174 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 175                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 176                                   uint16_t reta_size);
 177
 178 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 179                         struct rte_eth_syn_filter *filter,
 180                         bool add);
 181 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 182                         struct rte_eth_syn_filter *filter);
 183 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 184                         enum rte_filter_op filter_op,
 185                         void *arg);
 186 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 187                         struct rte_eth_ntuple_filter *ntuple_filter);
 188 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 189                         struct rte_eth_ntuple_filter *ntuple_filter);
 190 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 191                         struct rte_eth_flex_filter *filter,
 192                         bool add);
 193 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_flex_filter *filter);
 195 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 196                         enum rte_filter_op filter_op,
 197                         void *arg);
 198 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 199                         struct rte_eth_ntuple_filter *ntuple_filter);
 200 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *filter,
 204                         bool add);
 205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *filter);
 207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 217                         struct rte_eth_ethertype_filter *filter);
 218 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 219                      enum rte_filter_type filter_type,
 220                      enum rte_filter_op filter_op,
 221                      void *arg);
 222 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 223 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 224                 struct rte_dev_reg_info *regs);
 225 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 226 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 227                 struct rte_dev_eeprom_info *eeprom);
 228 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 229                 struct rte_dev_eeprom_info *eeprom);
 230 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 231                                     struct ether_addr *mc_addr_set,
 232                                     uint32_t nb_mc_addr);
 233 static int igb_timesync_enable(struct rte_eth_dev *dev);
 234 static int igb_timesync_disable(struct rte_eth_dev *dev);
 235 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 236                                           struct timespec *timestamp,
 237                                           uint32_t flags);
 238 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 239                                           struct timespec *timestamp);
 240 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 241 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 242                                   struct timespec *timestamp);
 243 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 244                                    const struct timespec *timestamp);
 245 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 246                                         uint16_t queue_id);
 247 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 248                                          uint16_t queue_id);
 249 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 250                                        uint8_t queue, uint8_t msix_vector);
 251 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 252                                uint8_t index, uint8_t offset);
 253 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)            \
 259 {                                                 \
 260         u32 latest = E1000_READ_REG(hw, reg);     \
 261         cur += (latest - last) & UINT_MAX;        \
 262         last = latest;                            \
 263 }
 264
 265 #define IGB_FC_PAUSE_TIME 0x0680
 266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 268
 269 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 270
 271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 272
 273 /*
 274  * The set of PCI devices this driver supports
 275  */
 276 static const struct rte_pci_id pci_id_igb_map[] = {
 277
 278 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 279 #include "rte_pci_dev_ids.h"
 280
 281 {0},
 282 };
 283
 284 /*
 285  * The set of PCI devices this driver supports (for 82576&I350 VF)
 286  */
 287 static const struct rte_pci_id pci_id_igbvf_map[] = {
 288
 289 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 290 #include "rte_pci_dev_ids.h"
 291
 292 {0},
 293 };
 294
 295 static const struct rte_eth_desc_lim rx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct rte_eth_desc_lim tx_desc_lim = {
 302         .nb_max = E1000_MAX_RING_DESC,
 303         .nb_min = E1000_MIN_RING_DESC,
 304         .nb_align = IGB_RXD_ALIGN,
 305 };
 306
 307 static const struct eth_dev_ops eth_igb_ops = {
 308         .dev_configure        = eth_igb_configure,
 309         .dev_start            = eth_igb_start,
 310         .dev_stop             = eth_igb_stop,
 311         .dev_close            = eth_igb_close,
 312         .promiscuous_enable   = eth_igb_promiscuous_enable,
 313         .promiscuous_disable  = eth_igb_promiscuous_disable,
 314         .allmulticast_enable  = eth_igb_allmulticast_enable,
 315         .allmulticast_disable = eth_igb_allmulticast_disable,
 316         .link_update          = eth_igb_link_update,
 317         .stats_get            = eth_igb_stats_get,
 318         .xstats_get           = eth_igb_xstats_get,
 319         .stats_reset          = eth_igb_stats_reset,
 320         .xstats_reset         = eth_igb_xstats_reset,
 321         .dev_infos_get        = eth_igb_infos_get,
 322         .mtu_set              = eth_igb_mtu_set,
 323         .vlan_filter_set      = eth_igb_vlan_filter_set,
 324         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 325         .vlan_offload_set     = eth_igb_vlan_offload_set,
 326         .rx_queue_setup       = eth_igb_rx_queue_setup,
 327         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 328         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 329         .rx_queue_release     = eth_igb_rx_queue_release,
 330         .rx_queue_count       = eth_igb_rx_queue_count,
 331         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 332         .tx_queue_setup       = eth_igb_tx_queue_setup,
 333         .tx_queue_release     = eth_igb_tx_queue_release,
 334         .dev_led_on           = eth_igb_led_on,
 335         .dev_led_off          = eth_igb_led_off,
 336         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 337         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 338         .mac_addr_add         = eth_igb_rar_set,
 339         .mac_addr_remove      = eth_igb_rar_clear,
 340         .mac_addr_set         = eth_igb_default_mac_addr_set,
 341         .reta_update          = eth_igb_rss_reta_update,
 342         .reta_query           = eth_igb_rss_reta_query,
 343         .rss_hash_update      = eth_igb_rss_hash_update,
 344         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 345         .filter_ctrl          = eth_igb_filter_ctrl,
 346         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 347         .rxq_info_get         = igb_rxq_info_get,
 348         .txq_info_get         = igb_txq_info_get,
 349         .timesync_enable      = igb_timesync_enable,
 350         .timesync_disable     = igb_timesync_disable,
 351         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 352         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 353         .get_reg_length       = eth_igb_get_reg_length,
 354         .get_reg              = eth_igb_get_regs,
 355         .get_eeprom_length    = eth_igb_get_eeprom_length,
 356         .get_eeprom           = eth_igb_get_eeprom,
 357         .set_eeprom           = eth_igb_set_eeprom,
 358         .timesync_adjust_time = igb_timesync_adjust_time,
 359         .timesync_read_time   = igb_timesync_read_time,
 360         .timesync_write_time  = igb_timesync_write_time,
 361 };
 362
 363 /*
 364  * dev_ops for virtual function, bare necessities for basic vf
 365  * operation have been implemented
 366  */
 367 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 368         .dev_configure        = igbvf_dev_configure,
 369         .dev_start            = igbvf_dev_start,
 370         .dev_stop             = igbvf_dev_stop,
 371         .dev_close            = igbvf_dev_close,
 372         .link_update          = eth_igb_link_update,
 373         .stats_get            = eth_igbvf_stats_get,
 374         .xstats_get           = eth_igbvf_xstats_get,
 375         .stats_reset          = eth_igbvf_stats_reset,
 376         .xstats_reset         = eth_igbvf_stats_reset,
 377         .vlan_filter_set      = igbvf_vlan_filter_set,
 378         .dev_infos_get        = eth_igbvf_infos_get,
 379         .rx_queue_setup       = eth_igb_rx_queue_setup,
 380         .rx_queue_release     = eth_igb_rx_queue_release,
 381         .tx_queue_setup       = eth_igb_tx_queue_setup,
 382         .tx_queue_release     = eth_igb_tx_queue_release,
 383         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 384         .rxq_info_get         = igb_rxq_info_get,
 385         .txq_info_get         = igb_txq_info_get,
 386         .mac_addr_set         = igbvf_default_mac_addr_set,
 387         .get_reg_length       = igbvf_get_reg_length,
 388         .get_reg              = igbvf_get_regs,
 389 };
 390
 391 /* store statistics names and its offset in stats structure */
 392 struct rte_igb_xstats_name_off {
 393         char name[RTE_ETH_XSTATS_NAME_SIZE];
 394         unsigned offset;
 395 };
 396
 397 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 398         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 399         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 400         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 401         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 402         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 403         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 404         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 405                 ecol)},
 406         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 407         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 408         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 409         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 410         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 411         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 412         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 413         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 414         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 415         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 416         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 417                 fcruc)},
 418         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 419         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 420         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 421         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 422         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 423                 prc1023)},
 424         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 425                 prc1522)},
 426         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 427         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 428         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 429         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 430         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 431         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 432         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 433         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 434         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 435         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 436         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 437         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 438         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 439         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 440         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 441         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 442         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 443         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 444                 ptc1023)},
 445         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 446                 ptc1522)},
 447         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 448         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 449         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 450         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 451         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 452         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 453         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 454
 455         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 456 };
 457
 458 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 459                 sizeof(rte_igb_stats_strings[0]))
 460
 461 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 462         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 463         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 464         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 465         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 466         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 467 };
 468
 469 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 470                 sizeof(rte_igbvf_stats_strings[0]))
 471
 472 /**
 473  * Atomically reads the link status information from global
 474  * structure rte_eth_dev.
 475  *
 476  * @param dev
 477  *   - Pointer to the structure rte_eth_dev to read from.
 478  *   - Pointer to the buffer to be saved with the link status.
 479  *
 480  * @return
 481  *   - On success, zero.
 482  *   - On failure, negative value.
 483  */
 484 static inline int
 485 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 486                                 struct rte_eth_link *link)
 487 {
 488         struct rte_eth_link *dst = link;
 489         struct rte_eth_link *src = &(dev->data->dev_link);
 490
 491         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 492                                         *(uint64_t *)src) == 0)
 493                 return -1;
 494
 495         return 0;
 496 }
 497
 498 /**
 499  * Atomically writes the link status information into global
 500  * structure rte_eth_dev.
 501  *
 502  * @param dev
 503  *   - Pointer to the structure rte_eth_dev to read from.
 504  *   - Pointer to the buffer to be saved with the link status.
 505  *
 506  * @return
 507  *   - On success, zero.
 508  *   - On failure, negative value.
 509  */
 510 static inline int
 511 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 512                                 struct rte_eth_link *link)
 513 {
 514         struct rte_eth_link *dst = &(dev->data->dev_link);
 515         struct rte_eth_link *src = link;
 516
 517         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 518                                         *(uint64_t *)src) == 0)
 519                 return -1;
 520
 521         return 0;
 522 }
 523
 524 static inline void
 525 igb_intr_enable(struct rte_eth_dev *dev)
 526 {
 527         struct e1000_interrupt *intr =
 528                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 529         struct e1000_hw *hw =
 530                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 531
 532         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 533         E1000_WRITE_FLUSH(hw);
 534 }
 535
 536 static void
 537 igb_intr_disable(struct e1000_hw *hw)
 538 {
 539         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 540         E1000_WRITE_FLUSH(hw);
 541 }
 542
 543 static inline int32_t
 544 igb_pf_reset_hw(struct e1000_hw *hw)
 545 {
 546         uint32_t ctrl_ext;
 547         int32_t status;
 548
 549         status = e1000_reset_hw(hw);
 550
 551         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 552         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 553         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 554         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 555         E1000_WRITE_FLUSH(hw);
 556
 557         return status;
 558 }
 559
 560 static void
 561 igb_identify_hardware(struct rte_eth_dev *dev)
 562 {
 563         struct e1000_hw *hw =
 564                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 565
 566         hw->vendor_id = dev->pci_dev->id.vendor_id;
 567         hw->device_id = dev->pci_dev->id.device_id;
 568         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 569         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 570
 571         e1000_set_mac_type(hw);
 572
 573         /* need to check if it is a vf device below */
 574 }
 575
 576 static int
 577 igb_reset_swfw_lock(struct e1000_hw *hw)
 578 {
 579         int ret_val;
 580
 581         /*
 582          * Do mac ops initialization manually here, since we will need
 583          * some function pointers set by this call.
 584          */
 585         ret_val = e1000_init_mac_params(hw);
 586         if (ret_val)
 587                 return ret_val;
 588
 589         /*
 590          * SMBI lock should not fail in this early stage. If this is the case,
 591          * it is due to an improper exit of the application.
 592          * So force the release of the faulty lock.
 593          */
 594         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 595                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 596         }
 597         e1000_put_hw_semaphore_generic(hw);
 598
 599         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 600                 uint16_t mask;
 601
 602                 /*
 603                  * Phy lock should not fail in this early stage. If this is the case,
 604                  * it is due to an improper exit of the application.
 605                  * So force the release of the faulty lock.
 606                  */
 607                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 608                 if (hw->bus.func > E1000_FUNC_1)
 609                         mask <<= 2;
 610                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 611                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 612                                     hw->bus.func);
 613                 }
 614                 hw->mac.ops.release_swfw_sync(hw, mask);
 615
 616                 /*
 617                  * This one is more tricky since it is common to all ports; but
 618                  * swfw_sync retries last long enough (1s) to be almost sure that if
 619                  * lock can not be taken it is due to an improper lock of the
 620                  * semaphore.
 621                  */
 622                 mask = E1000_SWFW_EEP_SM;
 623                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 624                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 625                 }
 626                 hw->mac.ops.release_swfw_sync(hw, mask);
 627         }
 628
 629         return E1000_SUCCESS;
 630 }
 631
 632 static int
 633 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 634 {
 635         int error = 0;
 636         struct rte_pci_device *pci_dev;
 637         struct e1000_hw *hw =
 638                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 639         struct e1000_vfta * shadow_vfta =
 640                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 641         struct e1000_filter_info *filter_info =
 642                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 643         struct e1000_adapter *adapter =
 644                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 645
 646         uint32_t ctrl_ext;
 647
 648         pci_dev = eth_dev->pci_dev;
 649
 650         eth_dev->dev_ops = &eth_igb_ops;
 651         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 652         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 653
 654         /* for secondary processes, we don't initialise any further as primary
 655          * has already done this work. Only check we don't need a different
 656          * RX function */
 657         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 658                 if (eth_dev->data->scattered_rx)
 659                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 660                 return 0;
 661         }
 662
 663         rte_eth_copy_pci_info(eth_dev, pci_dev);
 664
 665         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 666
 667         igb_identify_hardware(eth_dev);
 668         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 669                 error = -EIO;
 670                 goto err_late;
 671         }
 672
 673         e1000_get_bus_info(hw);
 674
 675         /* Reset any pending lock */
 676         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 677                 error = -EIO;
 678                 goto err_late;
 679         }
 680
 681         /* Finish initialization */
 682         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 683                 error = -EIO;
 684                 goto err_late;
 685         }
 686
 687         hw->mac.autoneg = 1;
 688         hw->phy.autoneg_wait_to_complete = 0;
 689         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 690
 691         /* Copper options */
 692         if (hw->phy.media_type == e1000_media_type_copper) {
 693                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 694                 hw->phy.disable_polarity_correction = 0;
 695                 hw->phy.ms_type = e1000_ms_hw_default;
 696         }
 697
 698         /*
 699          * Start from a known state, this is important in reading the nvm
 700          * and mac from that.
 701          */
 702         igb_pf_reset_hw(hw);
 703
 704         /* Make sure we have a good EEPROM before we read from it */
 705         if (e1000_validate_nvm_checksum(hw) < 0) {
 706                 /*
 707                  * Some PCI-E parts fail the first check due to
 708                  * the link being in sleep state, call it again,
 709                  * if it fails a second time its a real issue.
 710                  */
 711                 if (e1000_validate_nvm_checksum(hw) < 0) {
 712                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 713                         error = -EIO;
 714                         goto err_late;
 715                 }
 716         }
 717
 718         /* Read the permanent MAC address out of the EEPROM */
 719         if (e1000_read_mac_addr(hw) != 0) {
 720                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 721                 error = -EIO;
 722                 goto err_late;
 723         }
 724
 725         /* Allocate memory for storing MAC addresses */
 726         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 727                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 728         if (eth_dev->data->mac_addrs == NULL) {
 729                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 730                                                 "store MAC addresses",
 731                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 732                 error = -ENOMEM;
 733                 goto err_late;
 734         }
 735
 736         /* Copy the permanent MAC address */
 737         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 738
 739         /* initialize the vfta */
 740         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 741
 742         /* Now initialize the hardware */
 743         if (igb_hardware_init(hw) != 0) {
 744                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 745                 rte_free(eth_dev->data->mac_addrs);
 746                 eth_dev->data->mac_addrs = NULL;
 747                 error = -ENODEV;
 748                 goto err_late;
 749         }
 750         hw->mac.get_link_status = 1;
 751         adapter->stopped = 0;
 752
 753         /* Indicate SOL/IDER usage */
 754         if (e1000_check_reset_block(hw) < 0) {
 755                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 756                                         "SOL/IDER session");
 757         }
 758
 759         /* initialize PF if max_vfs not zero */
 760         igb_pf_host_init(eth_dev);
 761
 762         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 763         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 764         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 765         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 766         E1000_WRITE_FLUSH(hw);
 767
 768         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 769                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 770                      pci_dev->id.device_id);
 771
 772         rte_intr_callback_register(&pci_dev->intr_handle,
 773                                    eth_igb_interrupt_handler,
 774                                    (void *)eth_dev);
 775
 776         /* enable uio/vfio intr/eventfd mapping */
 777         rte_intr_enable(&pci_dev->intr_handle);
 778
 779         /* enable support intr */
 780         igb_intr_enable(eth_dev);
 781
 782         TAILQ_INIT(&filter_info->flex_list);
 783         filter_info->flex_mask = 0;
 784         TAILQ_INIT(&filter_info->twotuple_list);
 785         filter_info->twotuple_mask = 0;
 786         TAILQ_INIT(&filter_info->fivetuple_list);
 787         filter_info->fivetuple_mask = 0;
 788
 789         return 0;
 790
 791 err_late:
 792         igb_hw_control_release(hw);
 793
 794         return (error);
 795 }
 796
 797 static int
 798 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 799 {
 800         struct rte_pci_device *pci_dev;
 801         struct e1000_hw *hw;
 802         struct e1000_adapter *adapter =
 803                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 804
 805         PMD_INIT_FUNC_TRACE();
 806
 807         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 808                 return -EPERM;
 809
 810         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 811         pci_dev = eth_dev->pci_dev;
 812
 813         if (adapter->stopped == 0)
 814                 eth_igb_close(eth_dev);
 815
 816         eth_dev->dev_ops = NULL;
 817         eth_dev->rx_pkt_burst = NULL;
 818         eth_dev->tx_pkt_burst = NULL;
 819
 820         /* Reset any pending lock */
 821         igb_reset_swfw_lock(hw);
 822
 823         rte_free(eth_dev->data->mac_addrs);
 824         eth_dev->data->mac_addrs = NULL;
 825
 826         /* uninitialize PF if max_vfs not zero */
 827         igb_pf_host_uninit(eth_dev);
 828
 829         /* disable uio intr before callback unregister */
 830         rte_intr_disable(&(pci_dev->intr_handle));
 831         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 832                 eth_igb_interrupt_handler, (void *)eth_dev);
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * Virtual Function device init
 839  */
 840 static int
 841 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 842 {
 843         struct rte_pci_device *pci_dev;
 844         struct e1000_adapter *adapter =
 845                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 846         struct e1000_hw *hw =
 847                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 848         int diag;
 849
 850         PMD_INIT_FUNC_TRACE();
 851
 852         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 853         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 854         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 855
 856         /* for secondary processes, we don't initialise any further as primary
 857          * has already done this work. Only check we don't need a different
 858          * RX function */
 859         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 860                 if (eth_dev->data->scattered_rx)
 861                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 862                 return 0;
 863         }
 864
 865         pci_dev = eth_dev->pci_dev;
 866
 867         rte_eth_copy_pci_info(eth_dev, pci_dev);
 868
 869         hw->device_id = pci_dev->id.device_id;
 870         hw->vendor_id = pci_dev->id.vendor_id;
 871         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 872         adapter->stopped = 0;
 873
 874         /* Initialize the shared code (base driver) */
 875         diag = e1000_setup_init_funcs(hw, TRUE);
 876         if (diag != 0) {
 877                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 878                         diag);
 879                 return -EIO;
 880         }
 881
 882         /* init_mailbox_params */
 883         hw->mbx.ops.init_params(hw);
 884
 885         /* Disable the interrupts for VF */
 886         igbvf_intr_disable(hw);
 887
 888         diag = hw->mac.ops.reset_hw(hw);
 889
 890         /* Allocate memory for storing MAC addresses */
 891         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 892                 hw->mac.rar_entry_count, 0);
 893         if (eth_dev->data->mac_addrs == NULL) {
 894                 PMD_INIT_LOG(ERR,
 895                         "Failed to allocate %d bytes needed to store MAC "
 896                         "addresses",
 897                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 898                 return -ENOMEM;
 899         }
 900
 901         /* Copy the permanent MAC address */
 902         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 903                         &eth_dev->data->mac_addrs[0]);
 904
 905         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 906                      "mac.type=%s",
 907                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 908                      pci_dev->id.device_id, "igb_mac_82576_vf");
 909
 910         return 0;
 911 }
 912
 913 static int
 914 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 915 {
 916         struct e1000_adapter *adapter =
 917                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 918
 919         PMD_INIT_FUNC_TRACE();
 920
 921         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 922                 return -EPERM;
 923
 924         if (adapter->stopped == 0)
 925                 igbvf_dev_close(eth_dev);
 926
 927         eth_dev->dev_ops = NULL;
 928         eth_dev->rx_pkt_burst = NULL;
 929         eth_dev->tx_pkt_burst = NULL;
 930
 931         rte_free(eth_dev->data->mac_addrs);
 932         eth_dev->data->mac_addrs = NULL;
 933
 934         return 0;
 935 }
 936
 937 static struct eth_driver rte_igb_pmd = {
 938         .pci_drv = {
 939                 .name = "rte_igb_pmd",
 940                 .id_table = pci_id_igb_map,
 941                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 942                         RTE_PCI_DRV_DETACHABLE,
 943         },
 944         .eth_dev_init = eth_igb_dev_init,
 945         .eth_dev_uninit = eth_igb_dev_uninit,
 946         .dev_private_size = sizeof(struct e1000_adapter),
 947 };
 948
 949 /*
 950  * virtual function driver struct
 951  */
 952 static struct eth_driver rte_igbvf_pmd = {
 953         .pci_drv = {
 954                 .name = "rte_igbvf_pmd",
 955                 .id_table = pci_id_igbvf_map,
 956                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 957         },
 958         .eth_dev_init = eth_igbvf_dev_init,
 959         .eth_dev_uninit = eth_igbvf_dev_uninit,
 960         .dev_private_size = sizeof(struct e1000_adapter),
 961 };
 962
 963 static int
 964 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 965 {
 966         rte_eth_driver_register(&rte_igb_pmd);
 967         return 0;
 968 }
 969
 970 static void
 971 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 972 {
 973         struct e1000_hw *hw =
 974                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 975         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 976         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 977         rctl |= E1000_RCTL_VFE;
 978         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 979 }
 980
 981 /*
 982  * VF Driver initialization routine.
 983  * Invoked one at EAL init time.
 984  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 985  */
 986 static int
 987 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 988 {
 989         PMD_INIT_FUNC_TRACE();
 990
 991         rte_eth_driver_register(&rte_igbvf_pmd);
 992         return (0);
 993 }
 994
 995 static int
 996 igb_check_mq_mode(struct rte_eth_dev *dev)
 997 {
 998         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 999         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1000         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1001         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1002
1003         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1004             tx_mq_mode == ETH_MQ_TX_DCB ||
1005             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1006                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1007                 return -EINVAL;
1008         }
1009         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1010                 /* Check multi-queue mode.
1011                  * To no break software we accept ETH_MQ_RX_NONE as this might
1012                  * be used to turn off VLAN filter.
1013                  */
1014
1015                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1016                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1017                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1018                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1019                 } else {
1020                         /* Only support one queue on VFs.
1021                          * RSS together with SRIOV is not supported.
1022                          */
1023                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1024                                         " wrong mq_mode rx %d.",
1025                                         rx_mq_mode);
1026                         return -EINVAL;
1027                 }
1028                 /* TX mode is not used here, so mode might be ignored.*/
1029                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1030                         /* SRIOV only works in VMDq enable mode */
1031                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1032                                         " TX mode %d is not supported. "
1033                                         " Driver will behave as %d mode.",
1034                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1035                 }
1036
1037                 /* check valid queue number */
1038                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1039                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1040                                         " only support one queue on VFs.");
1041                         return -EINVAL;
1042                 }
1043         } else {
1044                 /* To no break software that set invalid mode, only display
1045                  * warning if invalid mode is used.
1046                  */
1047                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1048                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1049                     rx_mq_mode != ETH_MQ_RX_RSS) {
1050                         /* RSS together with VMDq not supported*/
1051                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1052                                      rx_mq_mode);
1053                         return -EINVAL;
1054                 }
1055
1056                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1057                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1058                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1059                                         " Due to txmode is meaningless in this"
1060                                         " driver, just ignore.",
1061                                         tx_mq_mode);
1062                 }
1063         }
1064         return 0;
1065 }
1066
1067 static int
1068 eth_igb_configure(struct rte_eth_dev *dev)
1069 {
1070         struct e1000_interrupt *intr =
1071                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1072         int ret;
1073
1074         PMD_INIT_FUNC_TRACE();
1075
1076         /* multipe queue mode checking */
1077         ret  = igb_check_mq_mode(dev);
1078         if (ret != 0) {
1079                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1080                             ret);
1081                 return ret;
1082         }
1083
1084         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1085         PMD_INIT_FUNC_TRACE();
1086
1087         return 0;
1088 }
1089
1090 static int
1091 eth_igb_start(struct rte_eth_dev *dev)
1092 {
1093         struct e1000_hw *hw =
1094                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1095         struct e1000_adapter *adapter =
1096                 E1000_DEV_PRIVATE(dev->data->dev_private);
1097         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1098         int ret, mask;
1099         uint32_t intr_vector = 0;
1100         uint32_t ctrl_ext;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         /* disable uio/vfio intr/eventfd mapping */
1105         rte_intr_disable(intr_handle);
1106
1107         /* Power up the phy. Needed to make the link go Up */
1108         e1000_power_up_phy(hw);
1109
1110         /*
1111          * Packet Buffer Allocation (PBA)
1112          * Writing PBA sets the receive portion of the buffer
1113          * the remainder is used for the transmit buffer.
1114          */
1115         if (hw->mac.type == e1000_82575) {
1116                 uint32_t pba;
1117
1118                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1119                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1120         }
1121
1122         /* Put the address into the Receive Address Array */
1123         e1000_rar_set(hw, hw->mac.addr, 0);
1124
1125         /* Initialize the hardware */
1126         if (igb_hardware_init(hw)) {
1127                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1128                 return (-EIO);
1129         }
1130         adapter->stopped = 0;
1131
1132         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1133
1134         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1135         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1136         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1137         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1138         E1000_WRITE_FLUSH(hw);
1139
1140         /* configure PF module if SRIOV enabled */
1141         igb_pf_host_configure(dev);
1142
1143         /* check and configure queue intr-vector mapping */
1144         if ((rte_intr_cap_multiple(intr_handle) ||
1145              !RTE_ETH_DEV_SRIOV(dev).active) &&
1146             dev->data->dev_conf.intr_conf.rxq != 0) {
1147                 intr_vector = dev->data->nb_rx_queues;
1148                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1149                         return -1;
1150         }
1151
1152         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1153                 intr_handle->intr_vec =
1154                         rte_zmalloc("intr_vec",
1155                                     dev->data->nb_rx_queues * sizeof(int), 0);
1156                 if (intr_handle->intr_vec == NULL) {
1157                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1158                                      " intr_vec\n", dev->data->nb_rx_queues);
1159                         return -ENOMEM;
1160                 }
1161         }
1162
1163         /* confiugre msix for rx interrupt */
1164         eth_igb_configure_msix_intr(dev);
1165
1166         /* Configure for OS presence */
1167         igb_init_manageability(hw);
1168
1169         eth_igb_tx_init(dev);
1170
1171         /* This can fail when allocating mbufs for descriptor rings */
1172         ret = eth_igb_rx_init(dev);
1173         if (ret) {
1174                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1175                 igb_dev_clear_queues(dev);
1176                 return ret;
1177         }
1178
1179         e1000_clear_hw_cntrs_base_generic(hw);
1180
1181         /*
1182          * VLAN Offload Settings
1183          */
1184         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1185                         ETH_VLAN_EXTEND_MASK;
1186         eth_igb_vlan_offload_set(dev, mask);
1187
1188         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1189                 /* Enable VLAN filter since VMDq always use VLAN filter */
1190                 igb_vmdq_vlan_hw_filter_enable(dev);
1191         }
1192
1193         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1194                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1195                 (hw->mac.type == e1000_i211)) {
1196                 /* Configure EITR with the maximum possible value (0xFFFF) */
1197                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1198         }
1199
1200         /* Setup link speed and duplex */
1201         switch (dev->data->dev_conf.link_speed) {
1202         case ETH_LINK_SPEED_AUTONEG:
1203                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1204                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1205                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1206                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1207                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1208                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1209                 else
1210                         goto error_invalid_config;
1211                 break;
1212         case ETH_LINK_SPEED_10:
1213                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1214                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1215                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1216                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1217                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1218                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1219                 else
1220                         goto error_invalid_config;
1221                 break;
1222         case ETH_LINK_SPEED_100:
1223                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1224                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1225                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1226                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1227                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1228                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1229                 else
1230                         goto error_invalid_config;
1231                 break;
1232         case ETH_LINK_SPEED_1000:
1233                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1234                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1235                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1236                 else
1237                         goto error_invalid_config;
1238                 break;
1239         case ETH_LINK_SPEED_10000:
1240         default:
1241                 goto error_invalid_config;
1242         }
1243         e1000_setup_link(hw);
1244
1245         if (rte_intr_allow_others(intr_handle)) {
1246                 /* check if lsc interrupt is enabled */
1247                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1248                         eth_igb_lsc_interrupt_setup(dev);
1249         } else {
1250                 rte_intr_callback_unregister(intr_handle,
1251                                              eth_igb_interrupt_handler,
1252                                              (void *)dev);
1253                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1254                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1255                                      " no intr multiplex\n");
1256         }
1257
1258         /* check if rxq interrupt is enabled */
1259         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1260             rte_intr_dp_is_en(intr_handle))
1261                 eth_igb_rxq_interrupt_setup(dev);
1262
1263         /* enable uio/vfio intr/eventfd mapping */
1264         rte_intr_enable(intr_handle);
1265
1266         /* resume enabled intr since hw reset */
1267         igb_intr_enable(dev);
1268
1269         PMD_INIT_LOG(DEBUG, "<<");
1270
1271         return (0);
1272
1273 error_invalid_config:
1274         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1275                      dev->data->dev_conf.link_speed,
1276                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1277         igb_dev_clear_queues(dev);
1278         return (-EINVAL);
1279 }
1280
1281 /*********************************************************************
1282  *
1283  *  This routine disables all traffic on the adapter by issuing a
1284  *  global reset on the MAC.
1285  *
1286  **********************************************************************/
1287 static void
1288 eth_igb_stop(struct rte_eth_dev *dev)
1289 {
1290         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1291         struct e1000_filter_info *filter_info =
1292                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1293         struct rte_eth_link link;
1294         struct e1000_flex_filter *p_flex;
1295         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1296         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1297         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1298
1299         igb_intr_disable(hw);
1300
1301         /* disable intr eventfd mapping */
1302         rte_intr_disable(intr_handle);
1303
1304         igb_pf_reset_hw(hw);
1305         E1000_WRITE_REG(hw, E1000_WUC, 0);
1306
1307         /* Set bit for Go Link disconnect */
1308         if (hw->mac.type >= e1000_82580) {
1309                 uint32_t phpm_reg;
1310
1311                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1312                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1313                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1314         }
1315
1316         /* Power down the phy. Needed to make the link go Down */
1317         if (hw->phy.media_type == e1000_media_type_copper)
1318                 e1000_power_down_phy(hw);
1319         else
1320                 e1000_shutdown_fiber_serdes_link(hw);
1321
1322         igb_dev_clear_queues(dev);
1323
1324         /* clear the recorded link status */
1325         memset(&link, 0, sizeof(link));
1326         rte_igb_dev_atomic_write_link_status(dev, &link);
1327
1328         /* Remove all flex filters of the device */
1329         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1330                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1331                 rte_free(p_flex);
1332         }
1333         filter_info->flex_mask = 0;
1334
1335         /* Remove all ntuple filters of the device */
1336         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1337              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1338                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1339                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1340                              p_5tuple, entries);
1341                 rte_free(p_5tuple);
1342         }
1343         filter_info->fivetuple_mask = 0;
1344         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1345              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1346                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1347                 TAILQ_REMOVE(&filter_info->twotuple_list,
1348                              p_2tuple, entries);
1349                 rte_free(p_2tuple);
1350         }
1351         filter_info->twotuple_mask = 0;
1352
1353         if (!rte_intr_allow_others(intr_handle))
1354                 /* resume to the default handler */
1355                 rte_intr_callback_register(intr_handle,
1356                                            eth_igb_interrupt_handler,
1357                                            (void *)dev);
1358
1359         /* Clean datapath event and queue/vec mapping */
1360         rte_intr_efd_disable(intr_handle);
1361         if (intr_handle->intr_vec != NULL) {
1362                 rte_free(intr_handle->intr_vec);
1363                 intr_handle->intr_vec = NULL;
1364         }
1365 }
1366
1367 static void
1368 eth_igb_close(struct rte_eth_dev *dev)
1369 {
1370         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1371         struct e1000_adapter *adapter =
1372                 E1000_DEV_PRIVATE(dev->data->dev_private);
1373         struct rte_eth_link link;
1374         struct rte_pci_device *pci_dev;
1375
1376         eth_igb_stop(dev);
1377         adapter->stopped = 1;
1378
1379         e1000_phy_hw_reset(hw);
1380         igb_release_manageability(hw);
1381         igb_hw_control_release(hw);
1382
1383         /* Clear bit for Go Link disconnect */
1384         if (hw->mac.type >= e1000_82580) {
1385                 uint32_t phpm_reg;
1386
1387                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1388                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1389                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1390         }
1391
1392         igb_dev_free_queues(dev);
1393
1394         pci_dev = dev->pci_dev;
1395         if (pci_dev->intr_handle.intr_vec) {
1396                 rte_free(pci_dev->intr_handle.intr_vec);
1397                 pci_dev->intr_handle.intr_vec = NULL;
1398         }
1399
1400         memset(&link, 0, sizeof(link));
1401         rte_igb_dev_atomic_write_link_status(dev, &link);
1402 }
1403
1404 static int
1405 igb_get_rx_buffer_size(struct e1000_hw *hw)
1406 {
1407         uint32_t rx_buf_size;
1408         if (hw->mac.type == e1000_82576) {
1409                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1410         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1411                 /* PBS needs to be translated according to a lookup table */
1412                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1413                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1414                 rx_buf_size = (rx_buf_size << 10);
1415         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1416                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1417         } else {
1418                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1419         }
1420
1421         return rx_buf_size;
1422 }
1423
1424 /*********************************************************************
1425  *
1426  *  Initialize the hardware
1427  *
1428  **********************************************************************/
1429 static int
1430 igb_hardware_init(struct e1000_hw *hw)
1431 {
1432         uint32_t rx_buf_size;
1433         int diag;
1434
1435         /* Let the firmware know the OS is in control */
1436         igb_hw_control_acquire(hw);
1437
1438         /*
1439          * These parameters control the automatic generation (Tx) and
1440          * response (Rx) to Ethernet PAUSE frames.
1441          * - High water mark should allow for at least two standard size (1518)
1442          *   frames to be received after sending an XOFF.
1443          * - Low water mark works best when it is very near the high water mark.
1444          *   This allows the receiver to restart by sending XON when it has
1445          *   drained a bit. Here we use an arbitrary value of 1500 which will
1446          *   restart after one full frame is pulled from the buffer. There
1447          *   could be several smaller frames in the buffer and if so they will
1448          *   not trigger the XON until their total number reduces the buffer
1449          *   by 1500.
1450          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1451          */
1452         rx_buf_size = igb_get_rx_buffer_size(hw);
1453
1454         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1455         hw->fc.low_water = hw->fc.high_water - 1500;
1456         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1457         hw->fc.send_xon = 1;
1458
1459         /* Set Flow control, use the tunable location if sane */
1460         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1461                 hw->fc.requested_mode = igb_fc_setting;
1462         else
1463                 hw->fc.requested_mode = e1000_fc_none;
1464
1465         /* Issue a global reset */
1466         igb_pf_reset_hw(hw);
1467         E1000_WRITE_REG(hw, E1000_WUC, 0);
1468
1469         diag = e1000_init_hw(hw);
1470         if (diag < 0)
1471                 return (diag);
1472
1473         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1474         e1000_get_phy_info(hw);
1475         e1000_check_for_link(hw);
1476
1477         return (0);
1478 }
1479
1480 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1481 static void
1482 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1483 {
1484         int pause_frames;
1485
1486         uint64_t old_gprc  = stats->gprc;
1487         uint64_t old_gptc  = stats->gptc;
1488         uint64_t old_tpr   = stats->tpr;
1489         uint64_t old_tpt   = stats->tpt;
1490         uint64_t old_rpthc = stats->rpthc;
1491         uint64_t old_hgptc = stats->hgptc;
1492
1493         if(hw->phy.media_type == e1000_media_type_copper ||
1494             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1495                 stats->symerrs +=
1496                     E1000_READ_REG(hw,E1000_SYMERRS);
1497                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1498         }
1499
1500         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1501         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1502         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1503         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1504
1505         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1506         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1507         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1508         stats->dc += E1000_READ_REG(hw, E1000_DC);
1509         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1510         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1511         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1512         /*
1513         ** For watchdog management we need to know if we have been
1514         ** paused during the last interval, so capture that here.
1515         */
1516         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1517         stats->xoffrxc += pause_frames;
1518         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1519         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1520         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1521         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1522         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1523         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1524         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1525         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1526         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1527         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1528         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1529         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1530
1531         /* For the 64-bit byte counters the low dword must be read first. */
1532         /* Both registers clear on the read of the high dword */
1533
1534         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1535         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1536         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1537         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1538         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1539         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1540         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1541
1542         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1543         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1544         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1545         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1546         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1547
1548         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1549         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1550
1551         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1552         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1553         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1554         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1555         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1556         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1557
1558         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1559         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1560         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1561         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1562         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1563         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1564         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1565         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1566
1567         /* Interrupt Counts */
1568
1569         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1570         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1571         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1572         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1573         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1574         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1575         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1576         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1577         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1578
1579         /* Host to Card Statistics */
1580
1581         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1582         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1583         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1584         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1585         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1586         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1587         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1588         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1589         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1590         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1591         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1592         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1593         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1594         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1595         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1596         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1597
1598         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1599         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1600         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1601         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1602         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1603         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1604 }
1605
1606 static void
1607 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1608 {
1609         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         struct e1000_hw_stats *stats =
1611                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1612
1613         igb_read_stats_registers(hw, stats);
1614
1615         if (rte_stats == NULL)
1616                 return;
1617
1618         /* Rx Errors */
1619         rte_stats->imissed = stats->mpc;
1620         rte_stats->ierrors = stats->crcerrs +
1621                              stats->rlec + stats->ruc + stats->roc +
1622                              rte_stats->imissed +
1623                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1624
1625         /* Tx Errors */
1626         rte_stats->oerrors = stats->ecol + stats->latecol;
1627
1628         rte_stats->ipackets = stats->gprc;
1629         rte_stats->opackets = stats->gptc;
1630         rte_stats->ibytes   = stats->gorc;
1631         rte_stats->obytes   = stats->gotc;
1632 }
1633
1634 static void
1635 eth_igb_stats_reset(struct rte_eth_dev *dev)
1636 {
1637         struct e1000_hw_stats *hw_stats =
1638                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1639
1640         /* HW registers are cleared on read */
1641         eth_igb_stats_get(dev, NULL);
1642
1643         /* Reset software totals */
1644         memset(hw_stats, 0, sizeof(*hw_stats));
1645 }
1646
1647 static void
1648 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1649 {
1650         struct e1000_hw_stats *stats =
1651                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1652
1653         /* HW registers are cleared on read */
1654         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1655
1656         /* Reset software totals */
1657         memset(stats, 0, sizeof(*stats));
1658 }
1659
1660 static int
1661 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1662                    unsigned n)
1663 {
1664         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         struct e1000_hw_stats *hw_stats =
1666                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1667         unsigned i;
1668
1669         if (n < IGB_NB_XSTATS)
1670                 return IGB_NB_XSTATS;
1671
1672         igb_read_stats_registers(hw, hw_stats);
1673
1674         /* If this is a reset xstats is NULL, and we have cleared the
1675          * registers by reading them.
1676          */
1677         if (!xstats)
1678                 return 0;
1679
1680         /* Extended stats */
1681         for (i = 0; i < IGB_NB_XSTATS; i++) {
1682                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1683                          "%s", rte_igb_stats_strings[i].name);
1684                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1685                         rte_igb_stats_strings[i].offset);
1686         }
1687
1688         return IGB_NB_XSTATS;
1689 }
1690
1691 static void
1692 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1693 {
1694         /* Good Rx packets, include VF loopback */
1695         UPDATE_VF_STAT(E1000_VFGPRC,
1696             hw_stats->last_gprc, hw_stats->gprc);
1697
1698         /* Good Rx octets, include VF loopback */
1699         UPDATE_VF_STAT(E1000_VFGORC,
1700             hw_stats->last_gorc, hw_stats->gorc);
1701
1702         /* Good Tx packets, include VF loopback */
1703         UPDATE_VF_STAT(E1000_VFGPTC,
1704             hw_stats->last_gptc, hw_stats->gptc);
1705
1706         /* Good Tx octets, include VF loopback */
1707         UPDATE_VF_STAT(E1000_VFGOTC,
1708             hw_stats->last_gotc, hw_stats->gotc);
1709
1710         /* Rx Multicst packets */
1711         UPDATE_VF_STAT(E1000_VFMPRC,
1712             hw_stats->last_mprc, hw_stats->mprc);
1713
1714         /* Good Rx loopback packets */
1715         UPDATE_VF_STAT(E1000_VFGPRLBC,
1716             hw_stats->last_gprlbc, hw_stats->gprlbc);
1717
1718         /* Good Rx loopback octets */
1719         UPDATE_VF_STAT(E1000_VFGORLBC,
1720             hw_stats->last_gorlbc, hw_stats->gorlbc);
1721
1722         /* Good Tx loopback packets */
1723         UPDATE_VF_STAT(E1000_VFGPTLBC,
1724             hw_stats->last_gptlbc, hw_stats->gptlbc);
1725
1726         /* Good Tx loopback octets */
1727         UPDATE_VF_STAT(E1000_VFGOTLBC,
1728             hw_stats->last_gotlbc, hw_stats->gotlbc);
1729 }
1730
1731 static int
1732 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1733                      unsigned n)
1734 {
1735         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1737                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1738         unsigned i;
1739
1740         if (n < IGBVF_NB_XSTATS)
1741                 return IGBVF_NB_XSTATS;
1742
1743         igbvf_read_stats_registers(hw, hw_stats);
1744
1745         if (!xstats)
1746                 return 0;
1747
1748         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1749                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1750                          rte_igbvf_stats_strings[i].name);
1751                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1752                         rte_igbvf_stats_strings[i].offset);
1753         }
1754
1755         return IGBVF_NB_XSTATS;
1756 }
1757
1758 static void
1759 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1760 {
1761         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1763                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1764
1765         igbvf_read_stats_registers(hw, hw_stats);
1766
1767         if (rte_stats == NULL)
1768                 return;
1769
1770         rte_stats->ipackets = hw_stats->gprc;
1771         rte_stats->ibytes = hw_stats->gorc;
1772         rte_stats->opackets = hw_stats->gptc;
1773         rte_stats->obytes = hw_stats->gotc;
1774         rte_stats->imcasts = hw_stats->mprc;
1775         rte_stats->ilbpackets = hw_stats->gprlbc;
1776         rte_stats->ilbbytes = hw_stats->gorlbc;
1777         rte_stats->olbpackets = hw_stats->gptlbc;
1778         rte_stats->olbbytes = hw_stats->gotlbc;
1779 }
1780
1781 static void
1782 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1783 {
1784         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1785                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1786
1787         /* Sync HW register to the last stats */
1788         eth_igbvf_stats_get(dev, NULL);
1789
1790         /* reset HW current stats*/
1791         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1792                offsetof(struct e1000_vf_stats, gprc));
1793 }
1794
1795 static void
1796 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1797 {
1798         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1799
1800         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1801         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1802         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1803         dev_info->rx_offload_capa =
1804                 DEV_RX_OFFLOAD_VLAN_STRIP |
1805                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1806                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1807                 DEV_RX_OFFLOAD_TCP_CKSUM;
1808         dev_info->tx_offload_capa =
1809                 DEV_TX_OFFLOAD_VLAN_INSERT |
1810                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1811                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1812                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1813                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1814                 DEV_TX_OFFLOAD_TCP_TSO;
1815
1816         switch (hw->mac.type) {
1817         case e1000_82575:
1818                 dev_info->max_rx_queues = 4;
1819                 dev_info->max_tx_queues = 4;
1820                 dev_info->max_vmdq_pools = 0;
1821                 break;
1822
1823         case e1000_82576:
1824                 dev_info->max_rx_queues = 16;
1825                 dev_info->max_tx_queues = 16;
1826                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1827                 dev_info->vmdq_queue_num = 16;
1828                 break;
1829
1830         case e1000_82580:
1831                 dev_info->max_rx_queues = 8;
1832                 dev_info->max_tx_queues = 8;
1833                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1834                 dev_info->vmdq_queue_num = 8;
1835                 break;
1836
1837         case e1000_i350:
1838                 dev_info->max_rx_queues = 8;
1839                 dev_info->max_tx_queues = 8;
1840                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1841                 dev_info->vmdq_queue_num = 8;
1842                 break;
1843
1844         case e1000_i354:
1845                 dev_info->max_rx_queues = 8;
1846                 dev_info->max_tx_queues = 8;
1847                 break;
1848
1849         case e1000_i210:
1850                 dev_info->max_rx_queues = 4;
1851                 dev_info->max_tx_queues = 4;
1852                 dev_info->max_vmdq_pools = 0;
1853                 break;
1854
1855         case e1000_i211:
1856                 dev_info->max_rx_queues = 2;
1857                 dev_info->max_tx_queues = 2;
1858                 dev_info->max_vmdq_pools = 0;
1859                 break;
1860
1861         default:
1862                 /* Should not happen */
1863                 break;
1864         }
1865         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1866         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1867         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1868
1869         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1870                 .rx_thresh = {
1871                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1872                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1873                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1874                 },
1875                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1876                 .rx_drop_en = 0,
1877         };
1878
1879         dev_info->default_txconf = (struct rte_eth_txconf) {
1880                 .tx_thresh = {
1881                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1882                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1883                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1884                 },
1885                 .txq_flags = 0,
1886         };
1887
1888         dev_info->rx_desc_lim = rx_desc_lim;
1889         dev_info->tx_desc_lim = tx_desc_lim;
1890 }
1891
1892 static void
1893 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1894 {
1895         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896
1897         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1898         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1899         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1900         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1901                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1902                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1903                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1904         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1905                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1906                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1907                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1908                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1909                                 DEV_TX_OFFLOAD_TCP_TSO;
1910         switch (hw->mac.type) {
1911         case e1000_vfadapt:
1912                 dev_info->max_rx_queues = 2;
1913                 dev_info->max_tx_queues = 2;
1914                 break;
1915         case e1000_vfadapt_i350:
1916                 dev_info->max_rx_queues = 1;
1917                 dev_info->max_tx_queues = 1;
1918                 break;
1919         default:
1920                 /* Should not happen */
1921                 break;
1922         }
1923
1924         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1925                 .rx_thresh = {
1926                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1927                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1928                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1929                 },
1930                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1931                 .rx_drop_en = 0,
1932         };
1933
1934         dev_info->default_txconf = (struct rte_eth_txconf) {
1935                 .tx_thresh = {
1936                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1937                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1938                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1939                 },
1940                 .txq_flags = 0,
1941         };
1942
1943         dev_info->rx_desc_lim = rx_desc_lim;
1944         dev_info->tx_desc_lim = tx_desc_lim;
1945 }
1946
1947 /* return 0 means link status changed, -1 means not changed */
1948 static int
1949 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1950 {
1951         struct e1000_hw *hw =
1952                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct rte_eth_link link, old;
1954         int link_check, count;
1955
1956         link_check = 0;
1957         hw->mac.get_link_status = 1;
1958
1959         /* possible wait-to-complete in up to 9 seconds */
1960         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1961                 /* Read the real link status */
1962                 switch (hw->phy.media_type) {
1963                 case e1000_media_type_copper:
1964                         /* Do the work to read phy */
1965                         e1000_check_for_link(hw);
1966                         link_check = !hw->mac.get_link_status;
1967                         break;
1968
1969                 case e1000_media_type_fiber:
1970                         e1000_check_for_link(hw);
1971                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1972                                       E1000_STATUS_LU);
1973                         break;
1974
1975                 case e1000_media_type_internal_serdes:
1976                         e1000_check_for_link(hw);
1977                         link_check = hw->mac.serdes_has_link;
1978                         break;
1979
1980                 /* VF device is type_unknown */
1981                 case e1000_media_type_unknown:
1982                         eth_igbvf_link_update(hw);
1983                         link_check = !hw->mac.get_link_status;
1984                         break;
1985
1986                 default:
1987                         break;
1988                 }
1989                 if (link_check || wait_to_complete == 0)
1990                         break;
1991                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1992         }
1993         memset(&link, 0, sizeof(link));
1994         rte_igb_dev_atomic_read_link_status(dev, &link);
1995         old = link;
1996
1997         /* Now we check if a transition has happened */
1998         if (link_check) {
1999                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
2000                                           &link.link_duplex);
2001                 link.link_status = 1;
2002         } else if (!link_check) {
2003                 link.link_speed = 0;
2004                 link.link_duplex = 0;
2005                 link.link_status = 0;
2006         }
2007         rte_igb_dev_atomic_write_link_status(dev, &link);
2008
2009         /* not changed */
2010         if (old.link_status == link.link_status)
2011                 return -1;
2012
2013         /* changed */
2014         return 0;
2015 }
2016
2017 /*
2018  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2019  * For ASF and Pass Through versions of f/w this means
2020  * that the driver is loaded.
2021  */
2022 static void
2023 igb_hw_control_acquire(struct e1000_hw *hw)
2024 {
2025         uint32_t ctrl_ext;
2026
2027         /* Let firmware know the driver has taken over */
2028         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2029         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2030 }
2031
2032 /*
2033  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2034  * For ASF and Pass Through versions of f/w this means that the
2035  * driver is no longer loaded.
2036  */
2037 static void
2038 igb_hw_control_release(struct e1000_hw *hw)
2039 {
2040         uint32_t ctrl_ext;
2041
2042         /* Let firmware taken over control of h/w */
2043         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2044         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2045                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2046 }
2047
2048 /*
2049  * Bit of a misnomer, what this really means is
2050  * to enable OS management of the system... aka
2051  * to disable special hardware management features.
2052  */
2053 static void
2054 igb_init_manageability(struct e1000_hw *hw)
2055 {
2056         if (e1000_enable_mng_pass_thru(hw)) {
2057                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2058                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2059
2060                 /* disable hardware interception of ARP */
2061                 manc &= ~(E1000_MANC_ARP_EN);
2062
2063                 /* enable receiving management packets to the host */
2064                 manc |= E1000_MANC_EN_MNG2HOST;
2065                 manc2h |= 1 << 5;  /* Mng Port 623 */
2066                 manc2h |= 1 << 6;  /* Mng Port 664 */
2067                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2068                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2069         }
2070 }
2071
2072 static void
2073 igb_release_manageability(struct e1000_hw *hw)
2074 {
2075         if (e1000_enable_mng_pass_thru(hw)) {
2076                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2077
2078                 manc |= E1000_MANC_ARP_EN;
2079                 manc &= ~E1000_MANC_EN_MNG2HOST;
2080
2081                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2082         }
2083 }
2084
2085 static void
2086 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2087 {
2088         struct e1000_hw *hw =
2089                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2090         uint32_t rctl;
2091
2092         rctl = E1000_READ_REG(hw, E1000_RCTL);
2093         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2094         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2095 }
2096
2097 static void
2098 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2099 {
2100         struct e1000_hw *hw =
2101                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         uint32_t rctl;
2103
2104         rctl = E1000_READ_REG(hw, E1000_RCTL);
2105         rctl &= (~E1000_RCTL_UPE);
2106         if (dev->data->all_multicast == 1)
2107                 rctl |= E1000_RCTL_MPE;
2108         else
2109                 rctl &= (~E1000_RCTL_MPE);
2110         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2111 }
2112
2113 static void
2114 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2115 {
2116         struct e1000_hw *hw =
2117                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2118         uint32_t rctl;
2119
2120         rctl = E1000_READ_REG(hw, E1000_RCTL);
2121         rctl |= E1000_RCTL_MPE;
2122         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2123 }
2124
2125 static void
2126 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2127 {
2128         struct e1000_hw *hw =
2129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130         uint32_t rctl;
2131
2132         if (dev->data->promiscuous == 1)
2133                 return; /* must remain in all_multicast mode */
2134         rctl = E1000_READ_REG(hw, E1000_RCTL);
2135         rctl &= (~E1000_RCTL_MPE);
2136         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2137 }
2138
2139 static int
2140 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2141 {
2142         struct e1000_hw *hw =
2143                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144         struct e1000_vfta * shadow_vfta =
2145                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2146         uint32_t vfta;
2147         uint32_t vid_idx;
2148         uint32_t vid_bit;
2149
2150         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2151                               E1000_VFTA_ENTRY_MASK);
2152         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2153         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2154         if (on)
2155                 vfta |= vid_bit;
2156         else
2157                 vfta &= ~vid_bit;
2158         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2159
2160         /* update local VFTA copy */
2161         shadow_vfta->vfta[vid_idx] = vfta;
2162
2163         return 0;
2164 }
2165
2166 static void
2167 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2168 {
2169         struct e1000_hw *hw =
2170                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171         uint32_t reg = ETHER_TYPE_VLAN ;
2172
2173         reg |= (tpid << 16);
2174         E1000_WRITE_REG(hw, E1000_VET, reg);
2175 }
2176
2177 static void
2178 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2179 {
2180         struct e1000_hw *hw =
2181                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         uint32_t reg;
2183
2184         /* Filter Table Disable */
2185         reg = E1000_READ_REG(hw, E1000_RCTL);
2186         reg &= ~E1000_RCTL_CFIEN;
2187         reg &= ~E1000_RCTL_VFE;
2188         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2189 }
2190
2191 static void
2192 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2193 {
2194         struct e1000_hw *hw =
2195                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         struct e1000_vfta * shadow_vfta =
2197                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2198         uint32_t reg;
2199         int i;
2200
2201         /* Filter Table Enable, CFI not used for packet acceptance */
2202         reg = E1000_READ_REG(hw, E1000_RCTL);
2203         reg &= ~E1000_RCTL_CFIEN;
2204         reg |= E1000_RCTL_VFE;
2205         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2206
2207         /* restore VFTA table */
2208         for (i = 0; i < IGB_VFTA_SIZE; i++)
2209                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2210 }
2211
2212 static void
2213 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2214 {
2215         struct e1000_hw *hw =
2216                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         uint32_t reg;
2218
2219         /* VLAN Mode Disable */
2220         reg = E1000_READ_REG(hw, E1000_CTRL);
2221         reg &= ~E1000_CTRL_VME;
2222         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2223 }
2224
2225 static void
2226 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2227 {
2228         struct e1000_hw *hw =
2229                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2230         uint32_t reg;
2231
2232         /* VLAN Mode Enable */
2233         reg = E1000_READ_REG(hw, E1000_CTRL);
2234         reg |= E1000_CTRL_VME;
2235         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2236 }
2237
2238 static void
2239 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2240 {
2241         struct e1000_hw *hw =
2242                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint32_t reg;
2244
2245         /* CTRL_EXT: Extended VLAN */
2246         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2247         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2248         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2249
2250         /* Update maximum packet length */
2251         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2252                 E1000_WRITE_REG(hw, E1000_RLPML,
2253                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2254                                                 VLAN_TAG_SIZE);
2255 }
2256
2257 static void
2258 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2259 {
2260         struct e1000_hw *hw =
2261                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         uint32_t reg;
2263
2264         /* CTRL_EXT: Extended VLAN */
2265         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2266         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2267         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2268
2269         /* Update maximum packet length */
2270         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2271                 E1000_WRITE_REG(hw, E1000_RLPML,
2272                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2273                                                 2 * VLAN_TAG_SIZE);
2274 }
2275
2276 static void
2277 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2278 {
2279         if(mask & ETH_VLAN_STRIP_MASK){
2280                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2281                         igb_vlan_hw_strip_enable(dev);
2282                 else
2283                         igb_vlan_hw_strip_disable(dev);
2284         }
2285
2286         if(mask & ETH_VLAN_FILTER_MASK){
2287                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2288                         igb_vlan_hw_filter_enable(dev);
2289                 else
2290                         igb_vlan_hw_filter_disable(dev);
2291         }
2292
2293         if(mask & ETH_VLAN_EXTEND_MASK){
2294                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2295                         igb_vlan_hw_extend_enable(dev);
2296                 else
2297                         igb_vlan_hw_extend_disable(dev);
2298         }
2299 }
2300
2301
2302 /**
2303  * It enables the interrupt mask and then enable the interrupt.
2304  *
2305  * @param dev
2306  *  Pointer to struct rte_eth_dev.
2307  *
2308  * @return
2309  *  - On success, zero.
2310  *  - On failure, a negative value.
2311  */
2312 static int
2313 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2314 {
2315         struct e1000_interrupt *intr =
2316                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2317
2318         intr->mask |= E1000_ICR_LSC;
2319
2320         return 0;
2321 }
2322
2323 /* It clears the interrupt causes and enables the interrupt.
2324  * It will be called once only during nic initialized.
2325  *
2326  * @param dev
2327  *  Pointer to struct rte_eth_dev.
2328  *
2329  * @return
2330  *  - On success, zero.
2331  *  - On failure, a negative value.
2332  */
2333 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2334 {
2335         uint32_t mask, regval;
2336         struct e1000_hw *hw =
2337                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338         struct rte_eth_dev_info dev_info;
2339
2340         memset(&dev_info, 0, sizeof(dev_info));
2341         eth_igb_infos_get(dev, &dev_info);
2342
2343         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2344         regval = E1000_READ_REG(hw, E1000_EIMS);
2345         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2346
2347         return 0;
2348 }
2349
2350 /*
2351  * It reads ICR and gets interrupt causes, check it and set a bit flag
2352  * to update link status.
2353  *
2354  * @param dev
2355  *  Pointer to struct rte_eth_dev.
2356  *
2357  * @return
2358  *  - On success, zero.
2359  *  - On failure, a negative value.
2360  */
2361 static int
2362 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2363 {
2364         uint32_t icr;
2365         struct e1000_hw *hw =
2366                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367         struct e1000_interrupt *intr =
2368                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369
2370         igb_intr_disable(hw);
2371
2372         /* read-on-clear nic registers here */
2373         icr = E1000_READ_REG(hw, E1000_ICR);
2374
2375         intr->flags = 0;
2376         if (icr & E1000_ICR_LSC) {
2377                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2378         }
2379
2380         if (icr & E1000_ICR_VMMB)
2381                 intr->flags |= E1000_FLAG_MAILBOX;
2382
2383         return 0;
2384 }
2385
2386 /*
2387  * It executes link_update after knowing an interrupt is prsent.
2388  *
2389  * @param dev
2390  *  Pointer to struct rte_eth_dev.
2391  *
2392  * @return
2393  *  - On success, zero.
2394  *  - On failure, a negative value.
2395  */
2396 static int
2397 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2398 {
2399         struct e1000_hw *hw =
2400                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         struct e1000_interrupt *intr =
2402                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403         uint32_t tctl, rctl;
2404         struct rte_eth_link link;
2405         int ret;
2406
2407         if (intr->flags & E1000_FLAG_MAILBOX) {
2408                 igb_pf_mbx_process(dev);
2409                 intr->flags &= ~E1000_FLAG_MAILBOX;
2410         }
2411
2412         igb_intr_enable(dev);
2413         rte_intr_enable(&(dev->pci_dev->intr_handle));
2414
2415         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2416                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2417
2418                 /* set get_link_status to check register later */
2419                 hw->mac.get_link_status = 1;
2420                 ret = eth_igb_link_update(dev, 0);
2421
2422                 /* check if link has changed */
2423                 if (ret < 0)
2424                         return 0;
2425
2426                 memset(&link, 0, sizeof(link));
2427                 rte_igb_dev_atomic_read_link_status(dev, &link);
2428                 if (link.link_status) {
2429                         PMD_INIT_LOG(INFO,
2430                                      " Port %d: Link Up - speed %u Mbps - %s",
2431                                      dev->data->port_id,
2432                                      (unsigned)link.link_speed,
2433                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2434                                      "full-duplex" : "half-duplex");
2435                 } else {
2436                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2437                                      dev->data->port_id);
2438                 }
2439
2440                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2441                              dev->pci_dev->addr.domain,
2442                              dev->pci_dev->addr.bus,
2443                              dev->pci_dev->addr.devid,
2444                              dev->pci_dev->addr.function);
2445                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2446                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2447                 if (link.link_status) {
2448                         /* enable Tx/Rx */
2449                         tctl |= E1000_TCTL_EN;
2450                         rctl |= E1000_RCTL_EN;
2451                 } else {
2452                         /* disable Tx/Rx */
2453                         tctl &= ~E1000_TCTL_EN;
2454                         rctl &= ~E1000_RCTL_EN;
2455                 }
2456                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2457                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2458                 E1000_WRITE_FLUSH(hw);
2459                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2460         }
2461
2462         return 0;
2463 }
2464
2465 /**
2466  * Interrupt handler which shall be registered at first.
2467  *
2468  * @param handle
2469  *  Pointer to interrupt handle.
2470  * @param param
2471  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2472  *
2473  * @return
2474  *  void
2475  */
2476 static void
2477 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2478                                                         void *param)
2479 {
2480         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2481
2482         eth_igb_interrupt_get_status(dev);
2483         eth_igb_interrupt_action(dev);
2484 }
2485
2486 static int
2487 eth_igb_led_on(struct rte_eth_dev *dev)
2488 {
2489         struct e1000_hw *hw;
2490
2491         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2493 }
2494
2495 static int
2496 eth_igb_led_off(struct rte_eth_dev *dev)
2497 {
2498         struct e1000_hw *hw;
2499
2500         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2502 }
2503
2504 static int
2505 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2506 {
2507         struct e1000_hw *hw;
2508         uint32_t ctrl;
2509         int tx_pause;
2510         int rx_pause;
2511
2512         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         fc_conf->pause_time = hw->fc.pause_time;
2514         fc_conf->high_water = hw->fc.high_water;
2515         fc_conf->low_water = hw->fc.low_water;
2516         fc_conf->send_xon = hw->fc.send_xon;
2517         fc_conf->autoneg = hw->mac.autoneg;
2518
2519         /*
2520          * Return rx_pause and tx_pause status according to actual setting of
2521          * the TFCE and RFCE bits in the CTRL register.
2522          */
2523         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2524         if (ctrl & E1000_CTRL_TFCE)
2525                 tx_pause = 1;
2526         else
2527                 tx_pause = 0;
2528
2529         if (ctrl & E1000_CTRL_RFCE)
2530                 rx_pause = 1;
2531         else
2532                 rx_pause = 0;
2533
2534         if (rx_pause && tx_pause)
2535                 fc_conf->mode = RTE_FC_FULL;
2536         else if (rx_pause)
2537                 fc_conf->mode = RTE_FC_RX_PAUSE;
2538         else if (tx_pause)
2539                 fc_conf->mode = RTE_FC_TX_PAUSE;
2540         else
2541                 fc_conf->mode = RTE_FC_NONE;
2542
2543         return 0;
2544 }
2545
2546 static int
2547 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2548 {
2549         struct e1000_hw *hw;
2550         int err;
2551         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2552                 e1000_fc_none,
2553                 e1000_fc_rx_pause,
2554                 e1000_fc_tx_pause,
2555                 e1000_fc_full
2556         };
2557         uint32_t rx_buf_size;
2558         uint32_t max_high_water;
2559         uint32_t rctl;
2560
2561         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         if (fc_conf->autoneg != hw->mac.autoneg)
2563                 return -ENOTSUP;
2564         rx_buf_size = igb_get_rx_buffer_size(hw);
2565         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2566
2567         /* At least reserve one Ethernet frame for watermark */
2568         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2569         if ((fc_conf->high_water > max_high_water) ||
2570             (fc_conf->high_water < fc_conf->low_water)) {
2571                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2572                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2573                 return (-EINVAL);
2574         }
2575
2576         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2577         hw->fc.pause_time     = fc_conf->pause_time;
2578         hw->fc.high_water     = fc_conf->high_water;
2579         hw->fc.low_water      = fc_conf->low_water;
2580         hw->fc.send_xon       = fc_conf->send_xon;
2581
2582         err = e1000_setup_link_generic(hw);
2583         if (err == E1000_SUCCESS) {
2584
2585                 /* check if we want to forward MAC frames - driver doesn't have native
2586                  * capability to do that, so we'll write the registers ourselves */
2587
2588                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2589
2590                 /* set or clear MFLCN.PMCF bit depending on configuration */
2591                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2592                         rctl |= E1000_RCTL_PMCF;
2593                 else
2594                         rctl &= ~E1000_RCTL_PMCF;
2595
2596                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2597                 E1000_WRITE_FLUSH(hw);
2598
2599                 return 0;
2600         }
2601
2602         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2603         return (-EIO);
2604 }
2605
2606 #define E1000_RAH_POOLSEL_SHIFT      (18)
2607 static void
2608 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2609                 uint32_t index, __rte_unused uint32_t pool)
2610 {
2611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         uint32_t rah;
2613
2614         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2615         rah = E1000_READ_REG(hw, E1000_RAH(index));
2616         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2617         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2618 }
2619
2620 static void
2621 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2622 {
2623         uint8_t addr[ETHER_ADDR_LEN];
2624         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625
2626         memset(addr, 0, sizeof(addr));
2627
2628         e1000_rar_set(hw, addr, index);
2629 }
2630
2631 static void
2632 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2633                                 struct ether_addr *addr)
2634 {
2635         eth_igb_rar_clear(dev, 0);
2636
2637         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2638 }
2639 /*
2640  * Virtual Function operations
2641  */
2642 static void
2643 igbvf_intr_disable(struct e1000_hw *hw)
2644 {
2645         PMD_INIT_FUNC_TRACE();
2646
2647         /* Clear interrupt mask to stop from interrupts being generated */
2648         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2649
2650         E1000_WRITE_FLUSH(hw);
2651 }
2652
2653 static void
2654 igbvf_stop_adapter(struct rte_eth_dev *dev)
2655 {
2656         u32 reg_val;
2657         u16 i;
2658         struct rte_eth_dev_info dev_info;
2659         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660
2661         memset(&dev_info, 0, sizeof(dev_info));
2662         eth_igbvf_infos_get(dev, &dev_info);
2663
2664         /* Clear interrupt mask to stop from interrupts being generated */
2665         igbvf_intr_disable(hw);
2666
2667         /* Clear any pending interrupts, flush previous writes */
2668         E1000_READ_REG(hw, E1000_EICR);
2669
2670         /* Disable the transmit unit.  Each queue must be disabled. */
2671         for (i = 0; i < dev_info.max_tx_queues; i++)
2672                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2673
2674         /* Disable the receive unit by stopping each queue */
2675         for (i = 0; i < dev_info.max_rx_queues; i++) {
2676                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2677                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2678                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2679                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2680                         ;
2681         }
2682
2683         /* flush all queues disables */
2684         E1000_WRITE_FLUSH(hw);
2685         msec_delay(2);
2686 }
2687
2688 static int eth_igbvf_link_update(struct e1000_hw *hw)
2689 {
2690         struct e1000_mbx_info *mbx = &hw->mbx;
2691         struct e1000_mac_info *mac = &hw->mac;
2692         int ret_val = E1000_SUCCESS;
2693
2694         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2695
2696         /*
2697          * We only want to run this if there has been a rst asserted.
2698          * in this case that could mean a link change, device reset,
2699          * or a virtual function reset
2700          */
2701
2702         /* If we were hit with a reset or timeout drop the link */
2703         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2704                 mac->get_link_status = TRUE;
2705
2706         if (!mac->get_link_status)
2707                 goto out;
2708
2709         /* if link status is down no point in checking to see if pf is up */
2710         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2711                 goto out;
2712
2713         /* if we passed all the tests above then the link is up and we no
2714          * longer need to check for link */
2715         mac->get_link_status = FALSE;
2716
2717 out:
2718         return ret_val;
2719 }
2720
2721
2722 static int
2723 igbvf_dev_configure(struct rte_eth_dev *dev)
2724 {
2725         struct rte_eth_conf* conf = &dev->data->dev_conf;
2726
2727         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2728                      dev->data->port_id);
2729
2730         /*
2731          * VF has no ability to enable/disable HW CRC
2732          * Keep the persistent behavior the same as Host PF
2733          */
2734 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2735         if (!conf->rxmode.hw_strip_crc) {
2736                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2737                 conf->rxmode.hw_strip_crc = 1;
2738         }
2739 #else
2740         if (conf->rxmode.hw_strip_crc) {
2741                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2742                 conf->rxmode.hw_strip_crc = 0;
2743         }
2744 #endif
2745
2746         return 0;
2747 }
2748
2749 static int
2750 igbvf_dev_start(struct rte_eth_dev *dev)
2751 {
2752         struct e1000_hw *hw =
2753                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754         struct e1000_adapter *adapter =
2755                 E1000_DEV_PRIVATE(dev->data->dev_private);
2756         int ret;
2757
2758         PMD_INIT_FUNC_TRACE();
2759
2760         hw->mac.ops.reset_hw(hw);
2761         adapter->stopped = 0;
2762
2763         /* Set all vfta */
2764         igbvf_set_vfta_all(dev,1);
2765
2766         eth_igbvf_tx_init(dev);
2767
2768         /* This can fail when allocating mbufs for descriptor rings */
2769         ret = eth_igbvf_rx_init(dev);
2770         if (ret) {
2771                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2772                 igb_dev_clear_queues(dev);
2773                 return ret;
2774         }
2775
2776         return 0;
2777 }
2778
2779 static void
2780 igbvf_dev_stop(struct rte_eth_dev *dev)
2781 {
2782         PMD_INIT_FUNC_TRACE();
2783
2784         igbvf_stop_adapter(dev);
2785
2786         /*
2787           * Clear what we set, but we still keep shadow_vfta to
2788           * restore after device starts
2789           */
2790         igbvf_set_vfta_all(dev,0);
2791
2792         igb_dev_clear_queues(dev);
2793 }
2794
2795 static void
2796 igbvf_dev_close(struct rte_eth_dev *dev)
2797 {
2798         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         struct e1000_adapter *adapter =
2800                 E1000_DEV_PRIVATE(dev->data->dev_private);
2801
2802         PMD_INIT_FUNC_TRACE();
2803
2804         e1000_reset_hw(hw);
2805
2806         igbvf_dev_stop(dev);
2807         adapter->stopped = 1;
2808         igb_dev_free_queues(dev);
2809 }
2810
2811 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2812 {
2813         struct e1000_mbx_info *mbx = &hw->mbx;
2814         uint32_t msgbuf[2];
2815         s32 err;
2816
2817         /* After set vlan, vlan strip will also be enabled in igb driver*/
2818         msgbuf[0] = E1000_VF_SET_VLAN;
2819         msgbuf[1] = vid;
2820         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2821         if (on)
2822                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2823
2824         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
2825         if (err)
2826                 goto mbx_err;
2827
2828         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
2829         if (err)
2830                 goto mbx_err;
2831
2832         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
2833         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
2834                 err = -EINVAL;
2835
2836 mbx_err:
2837         return err;
2838 }
2839
2840 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2841 {
2842         struct e1000_hw *hw =
2843                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct e1000_vfta * shadow_vfta =
2845                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2846         int i = 0, j = 0, vfta = 0, mask = 1;
2847
2848         for (i = 0; i < IGB_VFTA_SIZE; i++){
2849                 vfta = shadow_vfta->vfta[i];
2850                 if(vfta){
2851                         mask = 1;
2852                         for (j = 0; j < 32; j++){
2853                                 if(vfta & mask)
2854                                         igbvf_set_vfta(hw,
2855                                                 (uint16_t)((i<<5)+j), on);
2856                                 mask<<=1;
2857                         }
2858                 }
2859         }
2860
2861 }
2862
2863 static int
2864 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2865 {
2866         struct e1000_hw *hw =
2867                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2868         struct e1000_vfta * shadow_vfta =
2869                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2870         uint32_t vid_idx = 0;
2871         uint32_t vid_bit = 0;
2872         int ret = 0;
2873
2874         PMD_INIT_FUNC_TRACE();
2875
2876         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2877         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2878         if(ret){
2879                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2880                 return ret;
2881         }
2882         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2883         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2884
2885         /*Save what we set and retore it after device reset*/
2886         if (on)
2887                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2888         else
2889                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2890
2891         return 0;
2892 }
2893
2894 static void
2895 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2896 {
2897         struct e1000_hw *hw =
2898                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899
2900         /* index is not used by rar_set() */
2901         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2902 }
2903
2904
2905 static int
2906 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2907                         struct rte_eth_rss_reta_entry64 *reta_conf,
2908                         uint16_t reta_size)
2909 {
2910         uint8_t i, j, mask;
2911         uint32_t reta, r;
2912         uint16_t idx, shift;
2913         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914
2915         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2916                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2917                         "(%d) doesn't match the number hardware can supported "
2918                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2919                 return -EINVAL;
2920         }
2921
2922         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2923                 idx = i / RTE_RETA_GROUP_SIZE;
2924                 shift = i % RTE_RETA_GROUP_SIZE;
2925                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2926                                                 IGB_4_BIT_MASK);
2927                 if (!mask)
2928                         continue;
2929                 if (mask == IGB_4_BIT_MASK)
2930                         r = 0;
2931                 else
2932                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2933                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2934                         if (mask & (0x1 << j))
2935                                 reta |= reta_conf[idx].reta[shift + j] <<
2936                                                         (CHAR_BIT * j);
2937                         else
2938                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2939                 }
2940                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2941         }
2942
2943         return 0;
2944 }
2945
2946 static int
2947 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2948                        struct rte_eth_rss_reta_entry64 *reta_conf,
2949                        uint16_t reta_size)
2950 {
2951         uint8_t i, j, mask;
2952         uint32_t reta;
2953         uint16_t idx, shift;
2954         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955
2956         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2957                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2958                         "(%d) doesn't match the number hardware can supported "
2959                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2960                 return -EINVAL;
2961         }
2962
2963         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2964                 idx = i / RTE_RETA_GROUP_SIZE;
2965                 shift = i % RTE_RETA_GROUP_SIZE;
2966                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2967                                                 IGB_4_BIT_MASK);
2968                 if (!mask)
2969                         continue;
2970                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2971                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2972                         if (mask & (0x1 << j))
2973                                 reta_conf[idx].reta[shift + j] =
2974                                         ((reta >> (CHAR_BIT * j)) &
2975                                                 IGB_8_BIT_MASK);
2976                 }
2977         }
2978
2979         return 0;
2980 }
2981
2982 #define MAC_TYPE_FILTER_SUP(type)    do {\
2983         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2984                 (type) != e1000_82576)\
2985                 return -ENOTSUP;\
2986 } while (0)
2987
2988 static int
2989 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2990                         struct rte_eth_syn_filter *filter,
2991                         bool add)
2992 {
2993         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2994         uint32_t synqf, rfctl;
2995
2996         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2997                 return -EINVAL;
2998
2999         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3000
3001         if (add) {
3002                 if (synqf & E1000_SYN_FILTER_ENABLE)
3003                         return -EINVAL;
3004
3005                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3006                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3007
3008                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3009                 if (filter->hig_pri)
3010                         rfctl |= E1000_RFCTL_SYNQFP;
3011                 else
3012                         rfctl &= ~E1000_RFCTL_SYNQFP;
3013
3014                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3015         } else {
3016                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3017                         return -ENOENT;
3018                 synqf = 0;
3019         }
3020
3021         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3022         E1000_WRITE_FLUSH(hw);
3023         return 0;
3024 }
3025
3026 static int
3027 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3028                         struct rte_eth_syn_filter *filter)
3029 {
3030         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031         uint32_t synqf, rfctl;
3032
3033         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3034         if (synqf & E1000_SYN_FILTER_ENABLE) {
3035                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3036                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3037                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3038                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3039                 return 0;
3040         }
3041
3042         return -ENOENT;
3043 }
3044
3045 static int
3046 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3047                         enum rte_filter_op filter_op,
3048                         void *arg)
3049 {
3050         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051         int ret;
3052
3053         MAC_TYPE_FILTER_SUP(hw->mac.type);
3054
3055         if (filter_op == RTE_ETH_FILTER_NOP)
3056                 return 0;
3057
3058         if (arg == NULL) {
3059                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3060                             filter_op);
3061                 return -EINVAL;
3062         }
3063
3064         switch (filter_op) {
3065         case RTE_ETH_FILTER_ADD:
3066                 ret = eth_igb_syn_filter_set(dev,
3067                                 (struct rte_eth_syn_filter *)arg,
3068                                 TRUE);
3069                 break;
3070         case RTE_ETH_FILTER_DELETE:
3071                 ret = eth_igb_syn_filter_set(dev,
3072                                 (struct rte_eth_syn_filter *)arg,
3073                                 FALSE);
3074                 break;
3075         case RTE_ETH_FILTER_GET:
3076                 ret = eth_igb_syn_filter_get(dev,
3077                                 (struct rte_eth_syn_filter *)arg);
3078                 break;
3079         default:
3080                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3081                 ret = -EINVAL;
3082                 break;
3083         }
3084
3085         return ret;
3086 }
3087
3088 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3089         if ((type) != e1000_82580 && (type) != e1000_i350)\
3090                 return -ENOSYS; \
3091 } while (0)
3092
3093 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3094 static inline int
3095 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3096                         struct e1000_2tuple_filter_info *filter_info)
3097 {
3098         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3099                 return -EINVAL;
3100         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3101                 return -EINVAL;  /* filter index is out of range. */
3102         if (filter->tcp_flags > TCP_FLAG_ALL)
3103                 return -EINVAL;  /* flags is invalid. */
3104
3105         switch (filter->dst_port_mask) {
3106         case UINT16_MAX:
3107                 filter_info->dst_port_mask = 0;
3108                 filter_info->dst_port = filter->dst_port;
3109                 break;
3110         case 0:
3111                 filter_info->dst_port_mask = 1;
3112                 break;
3113         default:
3114                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3115                 return -EINVAL;
3116         }
3117
3118         switch (filter->proto_mask) {
3119         case UINT8_MAX:
3120                 filter_info->proto_mask = 0;
3121                 filter_info->proto = filter->proto;
3122                 break;
3123         case 0:
3124                 filter_info->proto_mask = 1;
3125                 break;
3126         default:
3127                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3128                 return -EINVAL;
3129         }
3130
3131         filter_info->priority = (uint8_t)filter->priority;
3132         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3133                 filter_info->tcp_flags = filter->tcp_flags;
3134         else
3135                 filter_info->tcp_flags = 0;
3136
3137         return 0;
3138 }
3139
3140 static inline struct e1000_2tuple_filter *
3141 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3142                         struct e1000_2tuple_filter_info *key)
3143 {
3144         struct e1000_2tuple_filter *it;
3145
3146         TAILQ_FOREACH(it, filter_list, entries) {
3147                 if (memcmp(key, &it->filter_info,
3148                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3149                         return it;
3150                 }
3151         }
3152         return NULL;
3153 }
3154
3155 /*
3156  * igb_add_2tuple_filter - add a 2tuple filter
3157  *
3158  * @param
3159  * dev: Pointer to struct rte_eth_dev.
3160  * ntuple_filter: ponter to the filter that will be added.
3161  *
3162  * @return
3163  *    - On success, zero.
3164  *    - On failure, a negative value.
3165  */
3166 static int
3167 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3168                         struct rte_eth_ntuple_filter *ntuple_filter)
3169 {
3170         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         struct e1000_filter_info *filter_info =
3172                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3173         struct e1000_2tuple_filter *filter;
3174         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3175         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3176         int i, ret;
3177
3178         filter = rte_zmalloc("e1000_2tuple_filter",
3179                         sizeof(struct e1000_2tuple_filter), 0);
3180         if (filter == NULL)
3181                 return -ENOMEM;
3182
3183         ret = ntuple_filter_to_2tuple(ntuple_filter,
3184                                       &filter->filter_info);
3185         if (ret < 0) {
3186                 rte_free(filter);
3187                 return ret;
3188         }
3189         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3190                                          &filter->filter_info) != NULL) {
3191                 PMD_DRV_LOG(ERR, "filter exists.");
3192                 rte_free(filter);
3193                 return -EEXIST;
3194         }
3195         filter->queue = ntuple_filter->queue;
3196
3197         /*
3198          * look for an unused 2tuple filter index,
3199          * and insert the filter to list.
3200          */
3201         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3202                 if (!(filter_info->twotuple_mask & (1 << i))) {
3203                         filter_info->twotuple_mask |= 1 << i;
3204                         filter->index = i;
3205                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3206                                           filter,
3207                                           entries);
3208                         break;
3209                 }
3210         }
3211         if (i >= E1000_MAX_TTQF_FILTERS) {
3212                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3213                 rte_free(filter);
3214                 return -ENOSYS;
3215         }
3216
3217         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3218         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3219                 imir |= E1000_IMIR_PORT_BP;
3220         else
3221                 imir &= ~E1000_IMIR_PORT_BP;
3222
3223         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3224
3225         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3226         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3227         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3228         if (filter->filter_info.proto_mask == 0)
3229                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3230
3231         /* tcp flags bits setting. */
3232         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3233                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3234                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3235                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3236                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3237                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3238                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3239                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3240                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3241                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3242                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3243                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3244                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3245         } else
3246                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3247         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3248         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3249         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3250         return 0;
3251 }
3252
3253 /*
3254  * igb_remove_2tuple_filter - remove a 2tuple filter
3255  *
3256  * @param
3257  * dev: Pointer to struct rte_eth_dev.
3258  * ntuple_filter: ponter to the filter that will be removed.
3259  *
3260  * @return
3261  *    - On success, zero.
3262  *    - On failure, a negative value.
3263  */
3264 static int
3265 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3266                         struct rte_eth_ntuple_filter *ntuple_filter)
3267 {
3268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct e1000_filter_info *filter_info =
3270                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3271         struct e1000_2tuple_filter_info filter_2tuple;
3272         struct e1000_2tuple_filter *filter;
3273         int ret;
3274
3275         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3276         ret = ntuple_filter_to_2tuple(ntuple_filter,
3277                                       &filter_2tuple);
3278         if (ret < 0)
3279                 return ret;
3280
3281         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3282                                          &filter_2tuple);
3283         if (filter == NULL) {
3284                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3285                 return -ENOENT;
3286         }
3287
3288         filter_info->twotuple_mask &= ~(1 << filter->index);
3289         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3290         rte_free(filter);
3291
3292         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3293         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3294         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3295         return 0;
3296 }
3297
3298 static inline struct e1000_flex_filter *
3299 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3300                         struct e1000_flex_filter_info *key)
3301 {
3302         struct e1000_flex_filter *it;
3303
3304         TAILQ_FOREACH(it, filter_list, entries) {
3305                 if (memcmp(key, &it->filter_info,
3306                         sizeof(struct e1000_flex_filter_info)) == 0)
3307                         return it;
3308         }
3309
3310         return NULL;
3311 }
3312
3313 static int
3314 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3315                         struct rte_eth_flex_filter *filter,
3316                         bool add)
3317 {
3318         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319         struct e1000_filter_info *filter_info =
3320                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3321         struct e1000_flex_filter *flex_filter, *it;
3322         uint32_t wufc, queueing, mask;
3323         uint32_t reg_off;
3324         uint8_t shift, i, j = 0;
3325
3326         flex_filter = rte_zmalloc("e1000_flex_filter",
3327                         sizeof(struct e1000_flex_filter), 0);
3328         if (flex_filter == NULL)
3329                 return -ENOMEM;
3330
3331         flex_filter->filter_info.len = filter->len;
3332         flex_filter->filter_info.priority = filter->priority;
3333         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3334         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3335                 mask = 0;
3336                 /* reverse bits in flex filter's mask*/
3337                 for (shift = 0; shift < CHAR_BIT; shift++) {
3338                         if (filter->mask[i] & (0x01 << shift))
3339                                 mask |= (0x80 >> shift);
3340                 }
3341                 flex_filter->filter_info.mask[i] = mask;
3342         }
3343
3344         wufc = E1000_READ_REG(hw, E1000_WUFC);
3345         if (flex_filter->index < E1000_MAX_FHFT)
3346                 reg_off = E1000_FHFT(flex_filter->index);
3347         else
3348                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3349
3350         if (add) {
3351                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3352                                 &flex_filter->filter_info) != NULL) {
3353                         PMD_DRV_LOG(ERR, "filter exists.");
3354                         rte_free(flex_filter);
3355                         return -EEXIST;
3356                 }
3357                 flex_filter->queue = filter->queue;
3358                 /*
3359                  * look for an unused flex filter index
3360                  * and insert the filter into the list.
3361                  */
3362                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3363                         if (!(filter_info->flex_mask & (1 << i))) {
3364                                 filter_info->flex_mask |= 1 << i;
3365                                 flex_filter->index = i;
3366                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3367                                         flex_filter,
3368                                         entries);
3369                                 break;
3370                         }
3371                 }
3372                 if (i >= E1000_MAX_FLEX_FILTERS) {
3373                         PMD_DRV_LOG(ERR, "flex filters are full.");
3374                         rte_free(flex_filter);
3375                         return -ENOSYS;
3376                 }
3377
3378                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3379                                 (E1000_WUFC_FLX0 << flex_filter->index));
3380                 queueing = filter->len |
3381                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3382                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3383                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3384                                 queueing);
3385                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3386                         E1000_WRITE_REG(hw, reg_off,
3387                                         flex_filter->filter_info.dwords[j]);
3388                         reg_off += sizeof(uint32_t);
3389                         E1000_WRITE_REG(hw, reg_off,
3390                                         flex_filter->filter_info.dwords[++j]);
3391                         reg_off += sizeof(uint32_t);
3392                         E1000_WRITE_REG(hw, reg_off,
3393                                 (uint32_t)flex_filter->filter_info.mask[i]);
3394                         reg_off += sizeof(uint32_t) * 2;
3395                         ++j;
3396                 }
3397         } else {
3398                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3399                                 &flex_filter->filter_info);
3400                 if (it == NULL) {
3401                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3402                         rte_free(flex_filter);
3403                         return -ENOENT;
3404                 }
3405
3406                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3407                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3408                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3409                         (~(E1000_WUFC_FLX0 << it->index)));
3410
3411                 filter_info->flex_mask &= ~(1 << it->index);
3412                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3413                 rte_free(it);
3414                 rte_free(flex_filter);
3415         }
3416
3417         return 0;
3418 }
3419
3420 static int
3421 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3422                         struct rte_eth_flex_filter *filter)
3423 {
3424         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425         struct e1000_filter_info *filter_info =
3426                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3427         struct e1000_flex_filter flex_filter, *it;
3428         uint32_t wufc, queueing, wufc_en = 0;
3429
3430         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3431         flex_filter.filter_info.len = filter->len;
3432         flex_filter.filter_info.priority = filter->priority;
3433         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3434         memcpy(flex_filter.filter_info.mask, filter->mask,
3435                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3436
3437         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3438                                 &flex_filter.filter_info);
3439         if (it == NULL) {
3440                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3441                 return -ENOENT;
3442         }
3443
3444         wufc = E1000_READ_REG(hw, E1000_WUFC);
3445         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3446
3447         if ((wufc & wufc_en) == wufc_en) {
3448                 uint32_t reg_off = 0;
3449                 if (it->index < E1000_MAX_FHFT)
3450                         reg_off = E1000_FHFT(it->index);
3451                 else
3452                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3453
3454                 queueing = E1000_READ_REG(hw,
3455                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3456                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3457                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3458                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3459                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3460                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3461                 return 0;
3462         }
3463         return -ENOENT;
3464 }
3465
3466 static int
3467 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3468                         enum rte_filter_op filter_op,
3469                         void *arg)
3470 {
3471         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3472         struct rte_eth_flex_filter *filter;
3473         int ret = 0;
3474
3475         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3476
3477         if (filter_op == RTE_ETH_FILTER_NOP)
3478                 return ret;
3479
3480         if (arg == NULL) {
3481                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3482                             filter_op);
3483                 return -EINVAL;
3484         }
3485
3486         filter = (struct rte_eth_flex_filter *)arg;
3487         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3488             || filter->len % sizeof(uint64_t) != 0) {
3489                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3490                 return -EINVAL;
3491         }
3492         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3493                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3494                 return -EINVAL;
3495         }
3496
3497         switch (filter_op) {
3498         case RTE_ETH_FILTER_ADD:
3499                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3500                 break;
3501         case RTE_ETH_FILTER_DELETE:
3502                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3503                 break;
3504         case RTE_ETH_FILTER_GET:
3505                 ret = eth_igb_get_flex_filter(dev, filter);
3506                 break;
3507         default:
3508                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3509                 ret = -EINVAL;
3510                 break;
3511         }
3512
3513         return ret;
3514 }
3515
3516 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3517 static inline int
3518 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3519                         struct e1000_5tuple_filter_info *filter_info)
3520 {
3521         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3522                 return -EINVAL;
3523         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3524                 return -EINVAL;  /* filter index is out of range. */
3525         if (filter->tcp_flags > TCP_FLAG_ALL)
3526                 return -EINVAL;  /* flags is invalid. */
3527
3528         switch (filter->dst_ip_mask) {
3529         case UINT32_MAX:
3530                 filter_info->dst_ip_mask = 0;
3531                 filter_info->dst_ip = filter->dst_ip;
3532                 break;
3533         case 0:
3534                 filter_info->dst_ip_mask = 1;
3535                 break;
3536         default:
3537                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3538                 return -EINVAL;
3539         }
3540
3541         switch (filter->src_ip_mask) {
3542         case UINT32_MAX:
3543                 filter_info->src_ip_mask = 0;
3544                 filter_info->src_ip = filter->src_ip;
3545                 break;
3546         case 0:
3547                 filter_info->src_ip_mask = 1;
3548                 break;
3549         default:
3550                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3551                 return -EINVAL;
3552         }
3553
3554         switch (filter->dst_port_mask) {
3555         case UINT16_MAX:
3556                 filter_info->dst_port_mask = 0;
3557                 filter_info->dst_port = filter->dst_port;
3558                 break;
3559         case 0:
3560                 filter_info->dst_port_mask = 1;
3561                 break;
3562         default:
3563                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3564                 return -EINVAL;
3565         }
3566
3567         switch (filter->src_port_mask) {
3568         case UINT16_MAX:
3569                 filter_info->src_port_mask = 0;
3570                 filter_info->src_port = filter->src_port;
3571                 break;
3572         case 0:
3573                 filter_info->src_port_mask = 1;
3574                 break;
3575         default:
3576                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3577                 return -EINVAL;
3578         }
3579
3580         switch (filter->proto_mask) {
3581         case UINT8_MAX:
3582                 filter_info->proto_mask = 0;
3583                 filter_info->proto = filter->proto;
3584                 break;
3585         case 0:
3586                 filter_info->proto_mask = 1;
3587                 break;
3588         default:
3589                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3590                 return -EINVAL;
3591         }
3592
3593         filter_info->priority = (uint8_t)filter->priority;
3594         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3595                 filter_info->tcp_flags = filter->tcp_flags;
3596         else
3597                 filter_info->tcp_flags = 0;
3598
3599         return 0;
3600 }
3601
3602 static inline struct e1000_5tuple_filter *
3603 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3604                         struct e1000_5tuple_filter_info *key)
3605 {
3606         struct e1000_5tuple_filter *it;
3607
3608         TAILQ_FOREACH(it, filter_list, entries) {
3609                 if (memcmp(key, &it->filter_info,
3610                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3611                         return it;
3612                 }
3613         }
3614         return NULL;
3615 }
3616
3617 /*
3618  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3619  *
3620  * @param
3621  * dev: Pointer to struct rte_eth_dev.
3622  * ntuple_filter: ponter to the filter that will be added.
3623  *
3624  * @return
3625  *    - On success, zero.
3626  *    - On failure, a negative value.
3627  */
3628 static int
3629 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3630                         struct rte_eth_ntuple_filter *ntuple_filter)
3631 {
3632         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633         struct e1000_filter_info *filter_info =
3634                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3635         struct e1000_5tuple_filter *filter;
3636         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3637         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3638         uint8_t i;
3639         int ret;
3640
3641         filter = rte_zmalloc("e1000_5tuple_filter",
3642                         sizeof(struct e1000_5tuple_filter), 0);
3643         if (filter == NULL)
3644                 return -ENOMEM;
3645
3646         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3647                                             &filter->filter_info);
3648         if (ret < 0) {
3649                 rte_free(filter);
3650                 return ret;
3651         }
3652
3653         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3654                                          &filter->filter_info) != NULL) {
3655                 PMD_DRV_LOG(ERR, "filter exists.");
3656                 rte_free(filter);
3657                 return -EEXIST;
3658         }
3659         filter->queue = ntuple_filter->queue;
3660
3661         /*
3662          * look for an unused 5tuple filter index,
3663          * and insert the filter to list.
3664          */
3665         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3666                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3667                         filter_info->fivetuple_mask |= 1 << i;
3668                         filter->index = i;
3669                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3670                                           filter,
3671                                           entries);
3672                         break;
3673                 }
3674         }
3675         if (i >= E1000_MAX_FTQF_FILTERS) {
3676                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3677                 rte_free(filter);
3678                 return -ENOSYS;
3679         }
3680
3681         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3682         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3683                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3684         if (filter->filter_info.dst_ip_mask == 0)
3685                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3686         if (filter->filter_info.src_port_mask == 0)
3687                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3688         if (filter->filter_info.proto_mask == 0)
3689                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3690         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3691                 E1000_FTQF_QUEUE_MASK;
3692         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3693         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3694         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3695         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3696
3697         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3698         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3699
3700         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3701         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3702                 imir |= E1000_IMIR_PORT_BP;
3703         else
3704                 imir &= ~E1000_IMIR_PORT_BP;
3705         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3706
3707         /* tcp flags bits setting. */
3708         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3709                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3710                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3711                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3712                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3713                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3714                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3715                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3716                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3717                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3718                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3719                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3720                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3721         } else
3722                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3723         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3724         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3725         return 0;
3726 }
3727
3728 /*
3729  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3730  *
3731  * @param
3732  * dev: Pointer to struct rte_eth_dev.
3733  * ntuple_filter: ponter to the filter that will be removed.
3734  *
3735  * @return
3736  *    - On success, zero.
3737  *    - On failure, a negative value.
3738  */
3739 static int
3740 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3741                                 struct rte_eth_ntuple_filter *ntuple_filter)
3742 {
3743         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744         struct e1000_filter_info *filter_info =
3745                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3746         struct e1000_5tuple_filter_info filter_5tuple;
3747         struct e1000_5tuple_filter *filter;
3748         int ret;
3749
3750         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3751         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3752                                             &filter_5tuple);
3753         if (ret < 0)
3754                 return ret;
3755
3756         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3757                                          &filter_5tuple);
3758         if (filter == NULL) {
3759                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3760                 return -ENOENT;
3761         }
3762
3763         filter_info->fivetuple_mask &= ~(1 << filter->index);
3764         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3765         rte_free(filter);
3766
3767         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3768                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3769         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3770         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3771         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3772         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3773         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3774         return 0;
3775 }
3776
3777 static int
3778 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3779 {
3780         uint32_t rctl;
3781         struct e1000_hw *hw;
3782         struct rte_eth_dev_info dev_info;
3783         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3784                                      VLAN_TAG_SIZE);
3785
3786         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3787
3788 #ifdef RTE_LIBRTE_82571_SUPPORT
3789         /* XXX: not bigger than max_rx_pktlen */
3790         if (hw->mac.type == e1000_82571)
3791                 return -ENOTSUP;
3792 #endif
3793         eth_igb_infos_get(dev, &dev_info);
3794
3795         /* check that mtu is within the allowed range */
3796         if ((mtu < ETHER_MIN_MTU) ||
3797             (frame_size > dev_info.max_rx_pktlen))
3798                 return -EINVAL;
3799
3800         /* refuse mtu that requires the support of scattered packets when this
3801          * feature has not been enabled before. */
3802         if (!dev->data->scattered_rx &&
3803             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3804                 return -EINVAL;
3805
3806         rctl = E1000_READ_REG(hw, E1000_RCTL);
3807
3808         /* switch to jumbo mode if needed */
3809         if (frame_size > ETHER_MAX_LEN) {
3810                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3811                 rctl |= E1000_RCTL_LPE;
3812         } else {
3813                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3814                 rctl &= ~E1000_RCTL_LPE;
3815         }
3816         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3817
3818         /* update max frame size */
3819         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3820
3821         E1000_WRITE_REG(hw, E1000_RLPML,
3822                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3823
3824         return 0;
3825 }
3826
3827 /*
3828  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3829  *
3830  * @param
3831  * dev: Pointer to struct rte_eth_dev.
3832  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3833  * add: if true, add filter, if false, remove filter
3834  *
3835  * @return
3836  *    - On success, zero.
3837  *    - On failure, a negative value.
3838  */
3839 static int
3840 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3841                         struct rte_eth_ntuple_filter *ntuple_filter,
3842                         bool add)
3843 {
3844         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845         int ret;
3846
3847         switch (ntuple_filter->flags) {
3848         case RTE_5TUPLE_FLAGS:
3849         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3850                 if (hw->mac.type != e1000_82576)
3851                         return -ENOTSUP;
3852                 if (add)
3853                         ret = igb_add_5tuple_filter_82576(dev,
3854                                                           ntuple_filter);
3855                 else
3856                         ret = igb_remove_5tuple_filter_82576(dev,
3857                                                              ntuple_filter);
3858                 break;
3859         case RTE_2TUPLE_FLAGS:
3860         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3861                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3862                         return -ENOTSUP;
3863                 if (add)
3864                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3865                 else
3866                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3867                 break;
3868         default:
3869                 ret = -EINVAL;
3870                 break;
3871         }
3872
3873         return ret;
3874 }
3875
3876 /*
3877  * igb_get_ntuple_filter - get a ntuple filter
3878  *
3879  * @param
3880  * dev: Pointer to struct rte_eth_dev.
3881  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3882  *
3883  * @return
3884  *    - On success, zero.
3885  *    - On failure, a negative value.
3886  */
3887 static int
3888 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3889                         struct rte_eth_ntuple_filter *ntuple_filter)
3890 {
3891         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         struct e1000_filter_info *filter_info =
3893                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3894         struct e1000_5tuple_filter_info filter_5tuple;
3895         struct e1000_2tuple_filter_info filter_2tuple;
3896         struct e1000_5tuple_filter *p_5tuple_filter;
3897         struct e1000_2tuple_filter *p_2tuple_filter;
3898         int ret;
3899
3900         switch (ntuple_filter->flags) {
3901         case RTE_5TUPLE_FLAGS:
3902         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3903                 if (hw->mac.type != e1000_82576)
3904                         return -ENOTSUP;
3905                 memset(&filter_5tuple,
3906                         0,
3907                         sizeof(struct e1000_5tuple_filter_info));
3908                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3909                                                     &filter_5tuple);
3910                 if (ret < 0)
3911                         return ret;
3912                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3913                                         &filter_info->fivetuple_list,
3914                                         &filter_5tuple);
3915                 if (p_5tuple_filter == NULL) {
3916                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3917                         return -ENOENT;
3918                 }
3919                 ntuple_filter->queue = p_5tuple_filter->queue;
3920                 break;
3921         case RTE_2TUPLE_FLAGS:
3922         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3923                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3924                         return -ENOTSUP;
3925                 memset(&filter_2tuple,
3926                         0,
3927                         sizeof(struct e1000_2tuple_filter_info));
3928                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3929                 if (ret < 0)
3930                         return ret;
3931                 p_2tuple_filter = igb_2tuple_filter_lookup(
3932                                         &filter_info->twotuple_list,
3933                                         &filter_2tuple);
3934                 if (p_2tuple_filter == NULL) {
3935                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3936                         return -ENOENT;
3937                 }
3938                 ntuple_filter->queue = p_2tuple_filter->queue;
3939                 break;
3940         default:
3941                 ret = -EINVAL;
3942                 break;
3943         }
3944
3945         return 0;
3946 }
3947
3948 /*
3949  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3950  * @dev: pointer to rte_eth_dev structure
3951  * @filter_op:operation will be taken.
3952  * @arg: a pointer to specific structure corresponding to the filter_op
3953  */
3954 static int
3955 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3956                                 enum rte_filter_op filter_op,
3957                                 void *arg)
3958 {
3959         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960         int ret;
3961
3962         MAC_TYPE_FILTER_SUP(hw->mac.type);
3963
3964         if (filter_op == RTE_ETH_FILTER_NOP)
3965                 return 0;
3966
3967         if (arg == NULL) {
3968                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3969                             filter_op);
3970                 return -EINVAL;
3971         }
3972
3973         switch (filter_op) {
3974         case RTE_ETH_FILTER_ADD:
3975                 ret = igb_add_del_ntuple_filter(dev,
3976                         (struct rte_eth_ntuple_filter *)arg,
3977                         TRUE);
3978                 break;
3979         case RTE_ETH_FILTER_DELETE:
3980                 ret = igb_add_del_ntuple_filter(dev,
3981                         (struct rte_eth_ntuple_filter *)arg,
3982                         FALSE);
3983                 break;
3984         case RTE_ETH_FILTER_GET:
3985                 ret = igb_get_ntuple_filter(dev,
3986                         (struct rte_eth_ntuple_filter *)arg);
3987                 break;
3988         default:
3989                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3990                 ret = -EINVAL;
3991                 break;
3992         }
3993         return ret;
3994 }
3995
3996 static inline int
3997 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3998                         uint16_t ethertype)
3999 {
4000         int i;
4001
4002         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4003                 if (filter_info->ethertype_filters[i] == ethertype &&
4004                     (filter_info->ethertype_mask & (1 << i)))
4005                         return i;
4006         }
4007         return -1;
4008 }
4009
4010 static inline int
4011 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4012                         uint16_t ethertype)
4013 {
4014         int i;
4015
4016         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4017                 if (!(filter_info->ethertype_mask & (1 << i))) {
4018                         filter_info->ethertype_mask |= 1 << i;
4019                         filter_info->ethertype_filters[i] = ethertype;
4020                         return i;
4021                 }
4022         }
4023         return -1;
4024 }
4025
4026 static inline int
4027 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4028                         uint8_t idx)
4029 {
4030         if (idx >= E1000_MAX_ETQF_FILTERS)
4031                 return -1;
4032         filter_info->ethertype_mask &= ~(1 << idx);
4033         filter_info->ethertype_filters[idx] = 0;
4034         return idx;
4035 }
4036
4037
4038 static int
4039 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4040                         struct rte_eth_ethertype_filter *filter,
4041                         bool add)
4042 {
4043         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         struct e1000_filter_info *filter_info =
4045                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4046         uint32_t etqf = 0;
4047         int ret;
4048
4049         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4050                 filter->ether_type == ETHER_TYPE_IPv6) {
4051                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4052                         " ethertype filter.", filter->ether_type);
4053                 return -EINVAL;
4054         }
4055
4056         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4057                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4058                 return -EINVAL;
4059         }
4060         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4061                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4062                 return -EINVAL;
4063         }
4064
4065         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4066         if (ret >= 0 && add) {
4067                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4068                             filter->ether_type);
4069                 return -EEXIST;
4070         }
4071         if (ret < 0 && !add) {
4072                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4073                             filter->ether_type);
4074                 return -ENOENT;
4075         }
4076
4077         if (add) {
4078                 ret = igb_ethertype_filter_insert(filter_info,
4079                         filter->ether_type);
4080                 if (ret < 0) {
4081                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4082                         return -ENOSYS;
4083                 }
4084
4085                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4086                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4087                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4088         } else {
4089                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4090                 if (ret < 0)
4091                         return -ENOSYS;
4092         }
4093         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4094         E1000_WRITE_FLUSH(hw);
4095
4096         return 0;
4097 }
4098
4099 static int
4100 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4101                         struct rte_eth_ethertype_filter *filter)
4102 {
4103         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104         struct e1000_filter_info *filter_info =
4105                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4106         uint32_t etqf;
4107         int ret;
4108
4109         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4110         if (ret < 0) {
4111                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4112                             filter->ether_type);
4113                 return -ENOENT;
4114         }
4115
4116         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4117         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4118                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4119                 filter->flags = 0;
4120                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4121                                 E1000_ETQF_QUEUE_SHIFT;
4122                 return 0;
4123         }
4124
4125         return -ENOENT;
4126 }
4127
4128 /*
4129  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4130  * @dev: pointer to rte_eth_dev structure
4131  * @filter_op:operation will be taken.
4132  * @arg: a pointer to specific structure corresponding to the filter_op
4133  */
4134 static int
4135 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4136                                 enum rte_filter_op filter_op,
4137                                 void *arg)
4138 {
4139         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         int ret;
4141
4142         MAC_TYPE_FILTER_SUP(hw->mac.type);
4143
4144         if (filter_op == RTE_ETH_FILTER_NOP)
4145                 return 0;
4146
4147         if (arg == NULL) {
4148                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4149                             filter_op);
4150                 return -EINVAL;
4151         }
4152
4153         switch (filter_op) {
4154         case RTE_ETH_FILTER_ADD:
4155                 ret = igb_add_del_ethertype_filter(dev,
4156                         (struct rte_eth_ethertype_filter *)arg,
4157                         TRUE);
4158                 break;
4159         case RTE_ETH_FILTER_DELETE:
4160                 ret = igb_add_del_ethertype_filter(dev,
4161                         (struct rte_eth_ethertype_filter *)arg,
4162                         FALSE);
4163                 break;
4164         case RTE_ETH_FILTER_GET:
4165                 ret = igb_get_ethertype_filter(dev,
4166                         (struct rte_eth_ethertype_filter *)arg);
4167                 break;
4168         default:
4169                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4170                 ret = -EINVAL;
4171                 break;
4172         }
4173         return ret;
4174 }
4175
4176 static int
4177 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4178                      enum rte_filter_type filter_type,
4179                      enum rte_filter_op filter_op,
4180                      void *arg)
4181 {
4182         int ret = -EINVAL;
4183
4184         switch (filter_type) {
4185         case RTE_ETH_FILTER_NTUPLE:
4186                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4187                 break;
4188         case RTE_ETH_FILTER_ETHERTYPE:
4189                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4190                 break;
4191         case RTE_ETH_FILTER_SYN:
4192                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4193                 break;
4194         case RTE_ETH_FILTER_FLEXIBLE:
4195                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4196                 break;
4197         default:
4198                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4199                                                         filter_type);
4200                 break;
4201         }
4202
4203         return ret;
4204 }
4205
4206 static int
4207 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4208                          struct ether_addr *mc_addr_set,
4209                          uint32_t nb_mc_addr)
4210 {
4211         struct e1000_hw *hw;
4212
4213         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4214         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4215         return 0;
4216 }
4217
4218 static uint64_t
4219 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4220 {
4221         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         uint64_t systime_cycles;
4223
4224         switch (hw->mac.type) {
4225         case e1000_i210:
4226         case e1000_i211:
4227                 /*
4228                  * Need to read System Time Residue Register to be able
4229                  * to read the other two registers.
4230                  */
4231                 E1000_READ_REG(hw, E1000_SYSTIMR);
4232                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4233                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4234                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4235                                 * NSEC_PER_SEC;
4236                 break;
4237         case e1000_82580:
4238         case e1000_i350:
4239         case e1000_i354:
4240                 /*
4241                  * Need to read System Time Residue Register to be able
4242                  * to read the other two registers.
4243                  */
4244                 E1000_READ_REG(hw, E1000_SYSTIMR);
4245                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4246                 /* Only the 8 LSB are valid. */
4247                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4248                                 & 0xff) << 32;
4249                 break;
4250         default:
4251                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4252                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4253                                 << 32;
4254                 break;
4255         }
4256
4257         return systime_cycles;
4258 }
4259
4260 static uint64_t
4261 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4262 {
4263         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264         uint64_t rx_tstamp_cycles;
4265
4266         switch (hw->mac.type) {
4267         case e1000_i210:
4268         case e1000_i211:
4269                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4270                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4271                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4272                                 * NSEC_PER_SEC;
4273                 break;
4274         case e1000_82580:
4275         case e1000_i350:
4276         case e1000_i354:
4277                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4278                 /* Only the 8 LSB are valid. */
4279                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4280                                 & 0xff) << 32;
4281                 break;
4282         default:
4283                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4284                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4285                                 << 32;
4286                 break;
4287         }
4288
4289         return rx_tstamp_cycles;
4290 }
4291
4292 static uint64_t
4293 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4294 {
4295         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4296         uint64_t tx_tstamp_cycles;
4297
4298         switch (hw->mac.type) {
4299         case e1000_i210:
4300         case e1000_i211:
4301                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4302                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4303                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4304                                 * NSEC_PER_SEC;
4305                 break;
4306         case e1000_82580:
4307         case e1000_i350:
4308         case e1000_i354:
4309                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4310                 /* Only the 8 LSB are valid. */
4311                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4312                                 & 0xff) << 32;
4313                 break;
4314         default:
4315                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4316                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4317                                 << 32;
4318                 break;
4319         }
4320
4321         return tx_tstamp_cycles;
4322 }
4323
4324 static void
4325 igb_start_timecounters(struct rte_eth_dev *dev)
4326 {
4327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         struct e1000_adapter *adapter =
4329                 (struct e1000_adapter *)dev->data->dev_private;
4330         uint32_t incval = 1;
4331         uint32_t shift = 0;
4332         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4333
4334         switch (hw->mac.type) {
4335         case e1000_82580:
4336         case e1000_i350:
4337         case e1000_i354:
4338                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4339                 mask = (1ULL << 40) - 1;
4340                 /* fall-through */
4341         case e1000_i210:
4342         case e1000_i211:
4343                 /*
4344                  * Start incrementing the register
4345                  * used to timestamp PTP packets.
4346                  */
4347                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4348                 break;
4349         case e1000_82576:
4350                 incval = E1000_INCVALUE_82576;
4351                 shift = IGB_82576_TSYNC_SHIFT;
4352                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4353                                 E1000_INCPERIOD_82576 | incval);
4354                 break;
4355         default:
4356                 /* Not supported */
4357                 return;
4358         }
4359
4360         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4361         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4362         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4363
4364         adapter->systime_tc.cc_mask = mask;
4365         adapter->systime_tc.cc_shift = shift;
4366         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4367
4368         adapter->rx_tstamp_tc.cc_mask = mask;
4369         adapter->rx_tstamp_tc.cc_shift = shift;
4370         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4371
4372         adapter->tx_tstamp_tc.cc_mask = mask;
4373         adapter->tx_tstamp_tc.cc_shift = shift;
4374         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4375 }
4376
4377 static int
4378 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4379 {
4380         struct e1000_adapter *adapter =
4381                         (struct e1000_adapter *)dev->data->dev_private;
4382
4383         adapter->systime_tc.nsec += delta;
4384         adapter->rx_tstamp_tc.nsec += delta;
4385         adapter->tx_tstamp_tc.nsec += delta;
4386
4387         return 0;
4388 }
4389
4390 static int
4391 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4392 {
4393         uint64_t ns;
4394         struct e1000_adapter *adapter =
4395                         (struct e1000_adapter *)dev->data->dev_private;
4396
4397         ns = rte_timespec_to_ns(ts);
4398
4399         /* Set the timecounters to a new value. */
4400         adapter->systime_tc.nsec = ns;
4401         adapter->rx_tstamp_tc.nsec = ns;
4402         adapter->tx_tstamp_tc.nsec = ns;
4403
4404         return 0;
4405 }
4406
4407 static int
4408 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4409 {
4410         uint64_t ns, systime_cycles;
4411         struct e1000_adapter *adapter =
4412                         (struct e1000_adapter *)dev->data->dev_private;
4413
4414         systime_cycles = igb_read_systime_cyclecounter(dev);
4415         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4416         *ts = rte_ns_to_timespec(ns);
4417
4418         return 0;
4419 }
4420
4421 static int
4422 igb_timesync_enable(struct rte_eth_dev *dev)
4423 {
4424         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425         uint32_t tsync_ctl;
4426         uint32_t tsauxc;
4427
4428         /* Stop the timesync system time. */
4429         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4430         /* Reset the timesync system time value. */
4431         switch (hw->mac.type) {
4432         case e1000_82580:
4433         case e1000_i350:
4434         case e1000_i354:
4435         case e1000_i210:
4436         case e1000_i211:
4437                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4438                 /* fall-through */
4439         case e1000_82576:
4440                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4441                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4442                 break;
4443         default:
4444                 /* Not supported. */
4445                 return -ENOTSUP;
4446         }
4447
4448         /* Enable system time for it isn't on by default. */
4449         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4450         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4451         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4452
4453         igb_start_timecounters(dev);
4454
4455         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4456         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4457                         (ETHER_TYPE_1588 |
4458                          E1000_ETQF_FILTER_ENABLE |
4459                          E1000_ETQF_1588));
4460
4461         /* Enable timestamping of received PTP packets. */
4462         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4463         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4464         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4465
4466         /* Enable Timestamping of transmitted PTP packets. */
4467         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4468         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4469         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4470
4471         return 0;
4472 }
4473
4474 static int
4475 igb_timesync_disable(struct rte_eth_dev *dev)
4476 {
4477         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478         uint32_t tsync_ctl;
4479
4480         /* Disable timestamping of transmitted PTP packets. */
4481         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4482         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4483         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4484
4485         /* Disable timestamping of received PTP packets. */
4486         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4487         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4488         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4489
4490         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4491         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4492
4493         /* Stop incrementating the System Time registers. */
4494         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4495
4496         return 0;
4497 }
4498
4499 static int
4500 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4501                                struct timespec *timestamp,
4502                                uint32_t flags __rte_unused)
4503 {
4504         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct e1000_adapter *adapter =
4506                         (struct e1000_adapter *)dev->data->dev_private;
4507         uint32_t tsync_rxctl;
4508         uint64_t rx_tstamp_cycles;
4509         uint64_t ns;
4510
4511         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4512         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4513                 return -EINVAL;
4514
4515         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4516         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4517         *timestamp = rte_ns_to_timespec(ns);
4518
4519         return  0;
4520 }
4521
4522 static int
4523 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4524                                struct timespec *timestamp)
4525 {
4526         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         struct e1000_adapter *adapter =
4528                         (struct e1000_adapter *)dev->data->dev_private;
4529         uint32_t tsync_txctl;
4530         uint64_t tx_tstamp_cycles;
4531         uint64_t ns;
4532
4533         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4534         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4535                 return -EINVAL;
4536
4537         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4538         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4539         *timestamp = rte_ns_to_timespec(ns);
4540
4541         return  0;
4542 }
4543
4544 static int
4545 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4546 {
4547         int count = 0;
4548         int g_ind = 0;
4549         const struct reg_info *reg_group;
4550
4551         while ((reg_group = igb_regs[g_ind++]))
4552                 count += igb_reg_group_count(reg_group);
4553
4554         return count;
4555 }
4556
4557 static int
4558 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4559 {
4560         int count = 0;
4561         int g_ind = 0;
4562         const struct reg_info *reg_group;
4563
4564         while ((reg_group = igbvf_regs[g_ind++]))
4565                 count += igb_reg_group_count(reg_group);
4566
4567         return count;
4568 }
4569
4570 static int
4571 eth_igb_get_regs(struct rte_eth_dev *dev,
4572         struct rte_dev_reg_info *regs)
4573 {
4574         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4575         uint32_t *data = regs->data;
4576         int g_ind = 0;
4577         int count = 0;
4578         const struct reg_info *reg_group;
4579
4580         /* Support only full register dump */
4581         if ((regs->length == 0) ||
4582             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4583                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4584                         hw->device_id;
4585                 while ((reg_group = igb_regs[g_ind++]))
4586                         count += igb_read_regs_group(dev, &data[count],
4587                                                         reg_group);
4588                 return 0;
4589         }
4590
4591         return -ENOTSUP;
4592 }
4593
4594 static int
4595 igbvf_get_regs(struct rte_eth_dev *dev,
4596         struct rte_dev_reg_info *regs)
4597 {
4598         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599         uint32_t *data = regs->data;
4600         int g_ind = 0;
4601         int count = 0;
4602         const struct reg_info *reg_group;
4603
4604         /* Support only full register dump */
4605         if ((regs->length == 0) ||
4606             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4607                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4608                         hw->device_id;
4609                 while ((reg_group = igbvf_regs[g_ind++]))
4610                         count += igb_read_regs_group(dev, &data[count],
4611                                                         reg_group);
4612                 return 0;
4613         }
4614
4615         return -ENOTSUP;
4616 }
4617
4618 static int
4619 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4620 {
4621         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4622
4623         /* Return unit is byte count */
4624         return hw->nvm.word_size * 2;
4625 }
4626
4627 static int
4628 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4629         struct rte_dev_eeprom_info *in_eeprom)
4630 {
4631         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4632         struct e1000_nvm_info *nvm = &hw->nvm;
4633         uint16_t *data = in_eeprom->data;
4634         int first, length;
4635
4636         first = in_eeprom->offset >> 1;
4637         length = in_eeprom->length >> 1;
4638         if ((first >= hw->nvm.word_size) ||
4639             ((first + length) >= hw->nvm.word_size))
4640                 return -EINVAL;
4641
4642         in_eeprom->magic = hw->vendor_id |
4643                 ((uint32_t)hw->device_id << 16);
4644
4645         if ((nvm->ops.read) == NULL)
4646                 return -ENOTSUP;
4647
4648         return nvm->ops.read(hw, first, length, data);
4649 }
4650
4651 static int
4652 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4653         struct rte_dev_eeprom_info *in_eeprom)
4654 {
4655         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4656         struct e1000_nvm_info *nvm = &hw->nvm;
4657         uint16_t *data = in_eeprom->data;
4658         int first, length;
4659
4660         first = in_eeprom->offset >> 1;
4661         length = in_eeprom->length >> 1;
4662         if ((first >= hw->nvm.word_size) ||
4663             ((first + length) >= hw->nvm.word_size))
4664                 return -EINVAL;
4665
4666         in_eeprom->magic = (uint32_t)hw->vendor_id |
4667                 ((uint32_t)hw->device_id << 16);
4668
4669         if ((nvm->ops.write) == NULL)
4670                 return -ENOTSUP;
4671         return nvm->ops.write(hw,  first, length, data);
4672 }
4673
4674 static struct rte_driver pmd_igb_drv = {
4675         .type = PMD_PDEV,
4676         .init = rte_igb_pmd_init,
4677 };
4678
4679 static struct rte_driver pmd_igbvf_drv = {
4680         .type = PMD_PDEV,
4681         .init = rte_igbvf_pmd_init,
4682 };
4683
4684 static int
4685 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4686 {
4687         struct e1000_hw *hw =
4688                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689         uint32_t mask = 1 << queue_id;
4690
4691         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4692         E1000_WRITE_FLUSH(hw);
4693
4694         return 0;
4695 }
4696
4697 static int
4698 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4699 {
4700         struct e1000_hw *hw =
4701                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         uint32_t mask = 1 << queue_id;
4703         uint32_t regval;
4704
4705         regval = E1000_READ_REG(hw, E1000_EIMS);
4706         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4707         E1000_WRITE_FLUSH(hw);
4708
4709         rte_intr_enable(&dev->pci_dev->intr_handle);
4710
4711         return 0;
4712 }
4713
4714 static void
4715 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4716                    uint8_t index, uint8_t offset)
4717 {
4718         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4719
4720         /* clear bits */
4721         val &= ~((uint32_t)0xFF << offset);
4722
4723         /* write vector and valid bit */
4724         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4725
4726         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4727 }
4728
4729 static void
4730 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4731                            uint8_t queue, uint8_t msix_vector)
4732 {
4733         uint32_t tmp = 0;
4734
4735         if (hw->mac.type == e1000_82575) {
4736                 if (direction == 0)
4737                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4738                 else if (direction == 1)
4739                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4740                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4741         } else if (hw->mac.type == e1000_82576) {
4742                 if ((direction == 0) || (direction == 1))
4743                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4744                                            ((queue & 0x8) << 1) +
4745                                            8 * direction);
4746         } else if ((hw->mac.type == e1000_82580) ||
4747                         (hw->mac.type == e1000_i350) ||
4748                         (hw->mac.type == e1000_i354) ||
4749                         (hw->mac.type == e1000_i210) ||
4750                         (hw->mac.type == e1000_i211)) {
4751                 if ((direction == 0) || (direction == 1))
4752                         eth_igb_write_ivar(hw, msix_vector,
4753                                            queue >> 1,
4754                                            ((queue & 0x1) << 4) +
4755                                            8 * direction);
4756         }
4757 }
4758
4759 /* Sets up the hardware to generate MSI-X interrupts properly
4760  * @hw
4761  *  board private structure
4762  */
4763 static void
4764 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4765 {
4766         int queue_id;
4767         uint32_t tmpval, regval, intr_mask;
4768         struct e1000_hw *hw =
4769                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770         uint32_t vec = E1000_MISC_VEC_ID;
4771         uint32_t base = E1000_MISC_VEC_ID;
4772         uint32_t misc_shift = 0;
4773
4774         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4775
4776         /* won't configure msix register if no mapping is done
4777          * between intr vector and event fd
4778          */
4779         if (!rte_intr_dp_is_en(intr_handle))
4780                 return;
4781
4782         if (rte_intr_allow_others(intr_handle)) {
4783                 vec = base = E1000_RX_VEC_START;
4784                 misc_shift = 1;
4785         }
4786
4787         /* set interrupt vector for other causes */
4788         if (hw->mac.type == e1000_82575) {
4789                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4790                 /* enable MSI-X PBA support */
4791                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4792
4793                 /* Auto-Mask interrupts upon ICR read */
4794                 tmpval |= E1000_CTRL_EXT_EIAME;
4795                 tmpval |= E1000_CTRL_EXT_IRCA;
4796
4797                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4798
4799                 /* enable msix_other interrupt */
4800                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4801                 regval = E1000_READ_REG(hw, E1000_EIAC);
4802                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4803                 regval = E1000_READ_REG(hw, E1000_EIAM);
4804                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4805         } else if ((hw->mac.type == e1000_82576) ||
4806                         (hw->mac.type == e1000_82580) ||
4807                         (hw->mac.type == e1000_i350) ||
4808                         (hw->mac.type == e1000_i354) ||
4809                         (hw->mac.type == e1000_i210) ||
4810                         (hw->mac.type == e1000_i211)) {
4811                 /* turn on MSI-X capability first */
4812                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4813                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4814                                         E1000_GPIE_NSICR);
4815                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4816                         misc_shift;
4817                 regval = E1000_READ_REG(hw, E1000_EIAC);
4818                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4819
4820                 /* enable msix_other interrupt */
4821                 regval = E1000_READ_REG(hw, E1000_EIMS);
4822                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4823                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4824                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4825         }
4826
4827         /* use EIAM to auto-mask when MSI-X interrupt
4828          * is asserted, this saves a register write for every interrupt
4829          */
4830         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
4831                 misc_shift;
4832         regval = E1000_READ_REG(hw, E1000_EIAM);
4833         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4834
4835         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4836                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4837                 intr_handle->intr_vec[queue_id] = vec;
4838                 if (vec < base + intr_handle->nb_efd - 1)
4839                         vec++;
4840         }
4841
4842         E1000_WRITE_FLUSH(hw);
4843 }
4844
4845 PMD_REGISTER_DRIVER(pmd_igb_drv);
4846 PMD_REGISTER_DRIVER(pmd_igbvf_drv);