drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294 static int igb_filter_restore(struct rte_eth_dev *dev);
 295
 296 /*
 297  * Define VF Stats MACRO for Non "cleared on read" register
 298  */
 299 #define UPDATE_VF_STAT(reg, last, cur)            \
 300 {                                                 \
 301         u32 latest = E1000_READ_REG(hw, reg);     \
 302         cur += (latest - last) & UINT_MAX;        \
 303         last = latest;                            \
 304 }
 305
 306 #define IGB_FC_PAUSE_TIME 0x0680
 307 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 308 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 309
 310 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 311
 312 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 313
 314 /*
 315  * The set of PCI devices this driver supports
 316  */
 317 static const struct rte_pci_id pci_id_igb_map[] = {
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 326
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 330
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 337
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 357         { .vendor_id = 0, /* sentinel */ },
 358 };
 359
 360 /*
 361  * The set of PCI devices this driver supports (for 82576&I350 VF)
 362  */
 363 static const struct rte_pci_id pci_id_igbvf_map[] = {
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 367         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 368         { .vendor_id = 0, /* sentinel */ },
 369 };
 370
 371 static const struct rte_eth_desc_lim rx_desc_lim = {
 372         .nb_max = E1000_MAX_RING_DESC,
 373         .nb_min = E1000_MIN_RING_DESC,
 374         .nb_align = IGB_RXD_ALIGN,
 375 };
 376
 377 static const struct rte_eth_desc_lim tx_desc_lim = {
 378         .nb_max = E1000_MAX_RING_DESC,
 379         .nb_min = E1000_MIN_RING_DESC,
 380         .nb_align = IGB_RXD_ALIGN,
 381         .nb_seg_max = IGB_TX_MAX_SEG,
 382         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 383 };
 384
 385 static const struct eth_dev_ops eth_igb_ops = {
 386         .dev_configure        = eth_igb_configure,
 387         .dev_start            = eth_igb_start,
 388         .dev_stop             = eth_igb_stop,
 389         .dev_set_link_up      = eth_igb_dev_set_link_up,
 390         .dev_set_link_down    = eth_igb_dev_set_link_down,
 391         .dev_close            = eth_igb_close,
 392         .promiscuous_enable   = eth_igb_promiscuous_enable,
 393         .promiscuous_disable  = eth_igb_promiscuous_disable,
 394         .allmulticast_enable  = eth_igb_allmulticast_enable,
 395         .allmulticast_disable = eth_igb_allmulticast_disable,
 396         .link_update          = eth_igb_link_update,
 397         .stats_get            = eth_igb_stats_get,
 398         .xstats_get           = eth_igb_xstats_get,
 399         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 400         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 401         .xstats_get_names     = eth_igb_xstats_get_names,
 402         .stats_reset          = eth_igb_stats_reset,
 403         .xstats_reset         = eth_igb_xstats_reset,
 404         .fw_version_get       = eth_igb_fw_version_get,
 405         .dev_infos_get        = eth_igb_infos_get,
 406         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 407         .mtu_set              = eth_igb_mtu_set,
 408         .vlan_filter_set      = eth_igb_vlan_filter_set,
 409         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 410         .vlan_offload_set     = eth_igb_vlan_offload_set,
 411         .rx_queue_setup       = eth_igb_rx_queue_setup,
 412         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 413         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 414         .rx_queue_release     = eth_igb_rx_queue_release,
 415         .rx_queue_count       = eth_igb_rx_queue_count,
 416         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 417         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 418         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 419         .tx_queue_setup       = eth_igb_tx_queue_setup,
 420         .tx_queue_release     = eth_igb_tx_queue_release,
 421         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 422         .dev_led_on           = eth_igb_led_on,
 423         .dev_led_off          = eth_igb_led_off,
 424         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 425         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 426         .mac_addr_add         = eth_igb_rar_set,
 427         .mac_addr_remove      = eth_igb_rar_clear,
 428         .mac_addr_set         = eth_igb_default_mac_addr_set,
 429         .reta_update          = eth_igb_rss_reta_update,
 430         .reta_query           = eth_igb_rss_reta_query,
 431         .rss_hash_update      = eth_igb_rss_hash_update,
 432         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 433         .filter_ctrl          = eth_igb_filter_ctrl,
 434         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 435         .rxq_info_get         = igb_rxq_info_get,
 436         .txq_info_get         = igb_txq_info_get,
 437         .timesync_enable      = igb_timesync_enable,
 438         .timesync_disable     = igb_timesync_disable,
 439         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 440         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 441         .get_reg              = eth_igb_get_regs,
 442         .get_eeprom_length    = eth_igb_get_eeprom_length,
 443         .get_eeprom           = eth_igb_get_eeprom,
 444         .set_eeprom           = eth_igb_set_eeprom,
 445         .timesync_adjust_time = igb_timesync_adjust_time,
 446         .timesync_read_time   = igb_timesync_read_time,
 447         .timesync_write_time  = igb_timesync_write_time,
 448 };
 449
 450 /*
 451  * dev_ops for virtual function, bare necessities for basic vf
 452  * operation have been implemented
 453  */
 454 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 455         .dev_configure        = igbvf_dev_configure,
 456         .dev_start            = igbvf_dev_start,
 457         .dev_stop             = igbvf_dev_stop,
 458         .dev_close            = igbvf_dev_close,
 459         .promiscuous_enable   = igbvf_promiscuous_enable,
 460         .promiscuous_disable  = igbvf_promiscuous_disable,
 461         .allmulticast_enable  = igbvf_allmulticast_enable,
 462         .allmulticast_disable = igbvf_allmulticast_disable,
 463         .link_update          = eth_igb_link_update,
 464         .stats_get            = eth_igbvf_stats_get,
 465         .xstats_get           = eth_igbvf_xstats_get,
 466         .xstats_get_names     = eth_igbvf_xstats_get_names,
 467         .stats_reset          = eth_igbvf_stats_reset,
 468         .xstats_reset         = eth_igbvf_stats_reset,
 469         .vlan_filter_set      = igbvf_vlan_filter_set,
 470         .dev_infos_get        = eth_igbvf_infos_get,
 471         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 472         .rx_queue_setup       = eth_igb_rx_queue_setup,
 473         .rx_queue_release     = eth_igb_rx_queue_release,
 474         .tx_queue_setup       = eth_igb_tx_queue_setup,
 475         .tx_queue_release     = eth_igb_tx_queue_release,
 476         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 477         .rxq_info_get         = igb_rxq_info_get,
 478         .txq_info_get         = igb_txq_info_get,
 479         .mac_addr_set         = igbvf_default_mac_addr_set,
 480         .get_reg              = igbvf_get_regs,
 481 };
 482
 483 /* store statistics names and its offset in stats structure */
 484 struct rte_igb_xstats_name_off {
 485         char name[RTE_ETH_XSTATS_NAME_SIZE];
 486         unsigned offset;
 487 };
 488
 489 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 490         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 491         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 492         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 493         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 494         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 495         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 496         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 497                 ecol)},
 498         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 499         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 500         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 501         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 502         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 503         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 504         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 505         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 506         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 507         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 508         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 509                 fcruc)},
 510         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 513         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 514         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 515                 prc1023)},
 516         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 517                 prc1522)},
 518         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 519         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 520         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 521         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 522         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 523         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 524         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 525         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 526         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 527         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 528         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 529         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 530         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 531         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 533         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 534         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 535         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 536                 ptc1023)},
 537         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 538                 ptc1522)},
 539         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 540         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 541         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 542         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 543         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 544         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 545         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 546
 547         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 548 };
 549
 550 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 551                 sizeof(rte_igb_stats_strings[0]))
 552
 553 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 554         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 555         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 556         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 557         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 558         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 559 };
 560
 561 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 562                 sizeof(rte_igbvf_stats_strings[0]))
 563
 564 /**
 565  * Atomically reads the link status information from global
 566  * structure rte_eth_dev.
 567  *
 568  * @param dev
 569  *   - Pointer to the structure rte_eth_dev to read from.
 570  *   - Pointer to the buffer to be saved with the link status.
 571  *
 572  * @return
 573  *   - On success, zero.
 574  *   - On failure, negative value.
 575  */
 576 static inline int
 577 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 578                                 struct rte_eth_link *link)
 579 {
 580         struct rte_eth_link *dst = link;
 581         struct rte_eth_link *src = &(dev->data->dev_link);
 582
 583         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 584                                         *(uint64_t *)src) == 0)
 585                 return -1;
 586
 587         return 0;
 588 }
 589
 590 /**
 591  * Atomically writes the link status information into global
 592  * structure rte_eth_dev.
 593  *
 594  * @param dev
 595  *   - Pointer to the structure rte_eth_dev to read from.
 596  *   - Pointer to the buffer to be saved with the link status.
 597  *
 598  * @return
 599  *   - On success, zero.
 600  *   - On failure, negative value.
 601  */
 602 static inline int
 603 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 604                                 struct rte_eth_link *link)
 605 {
 606         struct rte_eth_link *dst = &(dev->data->dev_link);
 607         struct rte_eth_link *src = link;
 608
 609         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 610                                         *(uint64_t *)src) == 0)
 611                 return -1;
 612
 613         return 0;
 614 }
 615
 616 static inline void
 617 igb_intr_enable(struct rte_eth_dev *dev)
 618 {
 619         struct e1000_interrupt *intr =
 620                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 625         E1000_WRITE_FLUSH(hw);
 626 }
 627
 628 static void
 629 igb_intr_disable(struct e1000_hw *hw)
 630 {
 631         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 632         E1000_WRITE_FLUSH(hw);
 633 }
 634
 635 static inline void
 636 igbvf_intr_enable(struct rte_eth_dev *dev)
 637 {
 638         struct e1000_hw *hw =
 639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         /* only for mailbox */
 642         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 645         E1000_WRITE_FLUSH(hw);
 646 }
 647
 648 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 649 static void
 650 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 651 {
 652         uint32_t tmp = 0;
 653
 654         /* mailbox */
 655         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 656         tmp |= E1000_VTIVAR_VALID;
 657         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 658 }
 659
 660 static void
 661 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 662 {
 663         struct e1000_hw *hw =
 664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 665
 666         /* Configure VF other cause ivar */
 667         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 668 }
 669
 670 static inline int32_t
 671 igb_pf_reset_hw(struct e1000_hw *hw)
 672 {
 673         uint32_t ctrl_ext;
 674         int32_t status;
 675
 676         status = e1000_reset_hw(hw);
 677
 678         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 679         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 680         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 681         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 682         E1000_WRITE_FLUSH(hw);
 683
 684         return status;
 685 }
 686
 687 static void
 688 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 689 {
 690         struct e1000_hw *hw =
 691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 692
 693
 694         hw->vendor_id = pci_dev->id.vendor_id;
 695         hw->device_id = pci_dev->id.device_id;
 696         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 697         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 698
 699         e1000_set_mac_type(hw);
 700
 701         /* need to check if it is a vf device below */
 702 }
 703
 704 static int
 705 igb_reset_swfw_lock(struct e1000_hw *hw)
 706 {
 707         int ret_val;
 708
 709         /*
 710          * Do mac ops initialization manually here, since we will need
 711          * some function pointers set by this call.
 712          */
 713         ret_val = e1000_init_mac_params(hw);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         /*
 718          * SMBI lock should not fail in this early stage. If this is the case,
 719          * it is due to an improper exit of the application.
 720          * So force the release of the faulty lock.
 721          */
 722         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 723                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 724         }
 725         e1000_put_hw_semaphore_generic(hw);
 726
 727         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 728                 uint16_t mask;
 729
 730                 /*
 731                  * Phy lock should not fail in this early stage. If this is the case,
 732                  * it is due to an improper exit of the application.
 733                  * So force the release of the faulty lock.
 734                  */
 735                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 736                 if (hw->bus.func > E1000_FUNC_1)
 737                         mask <<= 2;
 738                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 739                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 740                                     hw->bus.func);
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743
 744                 /*
 745                  * This one is more tricky since it is common to all ports; but
 746                  * swfw_sync retries last long enough (1s) to be almost sure that if
 747                  * lock can not be taken it is due to an improper lock of the
 748                  * semaphore.
 749                  */
 750                 mask = E1000_SWFW_EEP_SM;
 751                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 752                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 753                 }
 754                 hw->mac.ops.release_swfw_sync(hw, mask);
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 /* Remove all ntuple filters of the device */
 761 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 762 {
 763         struct e1000_filter_info *filter_info =
 764                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 765         struct e1000_5tuple_filter *p_5tuple;
 766         struct e1000_2tuple_filter *p_2tuple;
 767
 768         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 769                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 770                         p_5tuple, entries);
 771                         rte_free(p_5tuple);
 772         }
 773         filter_info->fivetuple_mask = 0;
 774         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 775                 TAILQ_REMOVE(&filter_info->twotuple_list,
 776                         p_2tuple, entries);
 777                         rte_free(p_2tuple);
 778         }
 779         filter_info->twotuple_mask = 0;
 780
 781         return 0;
 782 }
 783
 784 /* Remove all flex filters of the device */
 785 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 786 {
 787         struct e1000_filter_info *filter_info =
 788                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 789         struct e1000_flex_filter *p_flex;
 790
 791         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 792                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 793                 rte_free(p_flex);
 794         }
 795         filter_info->flex_mask = 0;
 796
 797         return 0;
 798 }
 799
 800 static int
 801 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 802 {
 803         int error = 0;
 804         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 805         struct e1000_hw *hw =
 806                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 807         struct e1000_vfta * shadow_vfta =
 808                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 809         struct e1000_filter_info *filter_info =
 810                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 811         struct e1000_adapter *adapter =
 812                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 813
 814         uint32_t ctrl_ext;
 815
 816         eth_dev->dev_ops = &eth_igb_ops;
 817         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 818         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 819         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 820
 821         /* for secondary processes, we don't initialise any further as primary
 822          * has already done this work. Only check we don't need a different
 823          * RX function */
 824         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 825                 if (eth_dev->data->scattered_rx)
 826                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 827                 return 0;
 828         }
 829
 830         rte_eth_copy_pci_info(eth_dev, pci_dev);
 831         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 832
 833         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 834
 835         igb_identify_hardware(eth_dev, pci_dev);
 836         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 837                 error = -EIO;
 838                 goto err_late;
 839         }
 840
 841         e1000_get_bus_info(hw);
 842
 843         /* Reset any pending lock */
 844         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 845                 error = -EIO;
 846                 goto err_late;
 847         }
 848
 849         /* Finish initialization */
 850         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 851                 error = -EIO;
 852                 goto err_late;
 853         }
 854
 855         hw->mac.autoneg = 1;
 856         hw->phy.autoneg_wait_to_complete = 0;
 857         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 858
 859         /* Copper options */
 860         if (hw->phy.media_type == e1000_media_type_copper) {
 861                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 862                 hw->phy.disable_polarity_correction = 0;
 863                 hw->phy.ms_type = e1000_ms_hw_default;
 864         }
 865
 866         /*
 867          * Start from a known state, this is important in reading the nvm
 868          * and mac from that.
 869          */
 870         igb_pf_reset_hw(hw);
 871
 872         /* Make sure we have a good EEPROM before we read from it */
 873         if (e1000_validate_nvm_checksum(hw) < 0) {
 874                 /*
 875                  * Some PCI-E parts fail the first check due to
 876                  * the link being in sleep state, call it again,
 877                  * if it fails a second time its a real issue.
 878                  */
 879                 if (e1000_validate_nvm_checksum(hw) < 0) {
 880                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 881                         error = -EIO;
 882                         goto err_late;
 883                 }
 884         }
 885
 886         /* Read the permanent MAC address out of the EEPROM */
 887         if (e1000_read_mac_addr(hw) != 0) {
 888                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 889                 error = -EIO;
 890                 goto err_late;
 891         }
 892
 893         /* Allocate memory for storing MAC addresses */
 894         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 895                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 896         if (eth_dev->data->mac_addrs == NULL) {
 897                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 898                                                 "store MAC addresses",
 899                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 900                 error = -ENOMEM;
 901                 goto err_late;
 902         }
 903
 904         /* Copy the permanent MAC address */
 905         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 906
 907         /* initialize the vfta */
 908         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 909
 910         /* Now initialize the hardware */
 911         if (igb_hardware_init(hw) != 0) {
 912                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 913                 rte_free(eth_dev->data->mac_addrs);
 914                 eth_dev->data->mac_addrs = NULL;
 915                 error = -ENODEV;
 916                 goto err_late;
 917         }
 918         hw->mac.get_link_status = 1;
 919         adapter->stopped = 0;
 920
 921         /* Indicate SOL/IDER usage */
 922         if (e1000_check_reset_block(hw) < 0) {
 923                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 924                                         "SOL/IDER session");
 925         }
 926
 927         /* initialize PF if max_vfs not zero */
 928         igb_pf_host_init(eth_dev);
 929
 930         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 931         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 932         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 933         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 934         E1000_WRITE_FLUSH(hw);
 935
 936         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 937                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 938                      pci_dev->id.device_id);
 939
 940         rte_intr_callback_register(&pci_dev->intr_handle,
 941                                    eth_igb_interrupt_handler,
 942                                    (void *)eth_dev);
 943
 944         /* enable uio/vfio intr/eventfd mapping */
 945         rte_intr_enable(&pci_dev->intr_handle);
 946
 947         /* enable support intr */
 948         igb_intr_enable(eth_dev);
 949
 950         /* initialize filter info */
 951         memset(filter_info, 0,
 952                sizeof(struct e1000_filter_info));
 953
 954         TAILQ_INIT(&filter_info->flex_list);
 955         TAILQ_INIT(&filter_info->twotuple_list);
 956         TAILQ_INIT(&filter_info->fivetuple_list);
 957
 958         return 0;
 959
 960 err_late:
 961         igb_hw_control_release(hw);
 962
 963         return error;
 964 }
 965
 966 static int
 967 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 968 {
 969         struct rte_pci_device *pci_dev;
 970         struct rte_intr_handle *intr_handle;
 971         struct e1000_hw *hw;
 972         struct e1000_adapter *adapter =
 973                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 974         struct e1000_filter_info *filter_info =
 975                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 976
 977         PMD_INIT_FUNC_TRACE();
 978
 979         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 980                 return -EPERM;
 981
 982         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 983         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 984         intr_handle = &pci_dev->intr_handle;
 985
 986         if (adapter->stopped == 0)
 987                 eth_igb_close(eth_dev);
 988
 989         eth_dev->dev_ops = NULL;
 990         eth_dev->rx_pkt_burst = NULL;
 991         eth_dev->tx_pkt_burst = NULL;
 992
 993         /* Reset any pending lock */
 994         igb_reset_swfw_lock(hw);
 995
 996         rte_free(eth_dev->data->mac_addrs);
 997         eth_dev->data->mac_addrs = NULL;
 998
 999         /* uninitialize PF if max_vfs not zero */
1000         igb_pf_host_uninit(eth_dev);
1001
1002         /* disable uio intr before callback unregister */
1003         rte_intr_disable(intr_handle);
1004         rte_intr_callback_unregister(intr_handle,
1005                                      eth_igb_interrupt_handler, eth_dev);
1006
1007         /* clear the SYN filter info */
1008         filter_info->syn_info = 0;
1009
1010         /* clear the ethertype filters info */
1011         filter_info->ethertype_mask = 0;
1012         memset(filter_info->ethertype_filters, 0,
1013                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
1014
1015         /* remove all ntuple filters of the device */
1016         igb_ntuple_filter_uninit(eth_dev);
1017
1018         /* remove all flex filters of the device */
1019         igb_flex_filter_uninit(eth_dev);
1020
1021         return 0;
1022 }
1023
1024 /*
1025  * Virtual Function device init
1026  */
1027 static int
1028 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1029 {
1030         struct rte_pci_device *pci_dev;
1031         struct rte_intr_handle *intr_handle;
1032         struct e1000_adapter *adapter =
1033                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1034         struct e1000_hw *hw =
1035                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1036         int diag;
1037         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1038
1039         PMD_INIT_FUNC_TRACE();
1040
1041         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1042         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1043         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1044         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1045
1046         /* for secondary processes, we don't initialise any further as primary
1047          * has already done this work. Only check we don't need a different
1048          * RX function */
1049         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1050                 if (eth_dev->data->scattered_rx)
1051                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1052                 return 0;
1053         }
1054
1055         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1056         rte_eth_copy_pci_info(eth_dev, pci_dev);
1057         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1058
1059         hw->device_id = pci_dev->id.device_id;
1060         hw->vendor_id = pci_dev->id.vendor_id;
1061         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1062         adapter->stopped = 0;
1063
1064         /* Initialize the shared code (base driver) */
1065         diag = e1000_setup_init_funcs(hw, TRUE);
1066         if (diag != 0) {
1067                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1068                         diag);
1069                 return -EIO;
1070         }
1071
1072         /* init_mailbox_params */
1073         hw->mbx.ops.init_params(hw);
1074
1075         /* Disable the interrupts for VF */
1076         igbvf_intr_disable(hw);
1077
1078         diag = hw->mac.ops.reset_hw(hw);
1079
1080         /* Allocate memory for storing MAC addresses */
1081         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1082                 hw->mac.rar_entry_count, 0);
1083         if (eth_dev->data->mac_addrs == NULL) {
1084                 PMD_INIT_LOG(ERR,
1085                         "Failed to allocate %d bytes needed to store MAC "
1086                         "addresses",
1087                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1088                 return -ENOMEM;
1089         }
1090
1091         /* Generate a random MAC address, if none was assigned by PF. */
1092         if (is_zero_ether_addr(perm_addr)) {
1093                 eth_random_addr(perm_addr->addr_bytes);
1094                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1095                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1096                              "%02x:%02x:%02x:%02x:%02x:%02x",
1097                              perm_addr->addr_bytes[0],
1098                              perm_addr->addr_bytes[1],
1099                              perm_addr->addr_bytes[2],
1100                              perm_addr->addr_bytes[3],
1101                              perm_addr->addr_bytes[4],
1102                              perm_addr->addr_bytes[5]);
1103         }
1104
1105         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1106         if (diag) {
1107                 rte_free(eth_dev->data->mac_addrs);
1108                 eth_dev->data->mac_addrs = NULL;
1109                 return diag;
1110         }
1111         /* Copy the permanent MAC address */
1112         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1113                         &eth_dev->data->mac_addrs[0]);
1114
1115         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1116                      "mac.type=%s",
1117                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1118                      pci_dev->id.device_id, "igb_mac_82576_vf");
1119
1120         intr_handle = &pci_dev->intr_handle;
1121         rte_intr_callback_register(intr_handle,
1122                                    eth_igbvf_interrupt_handler, eth_dev);
1123
1124         return 0;
1125 }
1126
1127 static int
1128 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1129 {
1130         struct e1000_adapter *adapter =
1131                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1132         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1133
1134         PMD_INIT_FUNC_TRACE();
1135
1136         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1137                 return -EPERM;
1138
1139         if (adapter->stopped == 0)
1140                 igbvf_dev_close(eth_dev);
1141
1142         eth_dev->dev_ops = NULL;
1143         eth_dev->rx_pkt_burst = NULL;
1144         eth_dev->tx_pkt_burst = NULL;
1145
1146         rte_free(eth_dev->data->mac_addrs);
1147         eth_dev->data->mac_addrs = NULL;
1148
1149         /* disable uio intr before callback unregister */
1150         rte_intr_disable(&pci_dev->intr_handle);
1151         rte_intr_callback_unregister(&pci_dev->intr_handle,
1152                                      eth_igbvf_interrupt_handler,
1153                                      (void *)eth_dev);
1154
1155         return 0;
1156 }
1157
1158 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1159         struct rte_pci_device *pci_dev)
1160 {
1161         return rte_eth_dev_pci_generic_probe(pci_dev,
1162                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1163 }
1164
1165 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1166 {
1167         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1168 }
1169
1170 static struct rte_pci_driver rte_igb_pmd = {
1171         .id_table = pci_id_igb_map,
1172         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1173         .probe = eth_igb_pci_probe,
1174         .remove = eth_igb_pci_remove,
1175 };
1176
1177
1178 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1179         struct rte_pci_device *pci_dev)
1180 {
1181         return rte_eth_dev_pci_generic_probe(pci_dev,
1182                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1183 }
1184
1185 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1186 {
1187         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1188 }
1189
1190 /*
1191  * virtual function driver struct
1192  */
1193 static struct rte_pci_driver rte_igbvf_pmd = {
1194         .id_table = pci_id_igbvf_map,
1195         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1196         .probe = eth_igbvf_pci_probe,
1197         .remove = eth_igbvf_pci_remove,
1198 };
1199
1200 static void
1201 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1202 {
1203         struct e1000_hw *hw =
1204                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1206         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1207         rctl |= E1000_RCTL_VFE;
1208         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1209 }
1210
1211 static int
1212 igb_check_mq_mode(struct rte_eth_dev *dev)
1213 {
1214         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1215         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1216         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1217         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1218
1219         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1220             tx_mq_mode == ETH_MQ_TX_DCB ||
1221             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1222                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1223                 return -EINVAL;
1224         }
1225         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1226                 /* Check multi-queue mode.
1227                  * To no break software we accept ETH_MQ_RX_NONE as this might
1228                  * be used to turn off VLAN filter.
1229                  */
1230
1231                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1232                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1233                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1234                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1235                 } else {
1236                         /* Only support one queue on VFs.
1237                          * RSS together with SRIOV is not supported.
1238                          */
1239                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1240                                         " wrong mq_mode rx %d.",
1241                                         rx_mq_mode);
1242                         return -EINVAL;
1243                 }
1244                 /* TX mode is not used here, so mode might be ignored.*/
1245                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1246                         /* SRIOV only works in VMDq enable mode */
1247                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1248                                         " TX mode %d is not supported. "
1249                                         " Driver will behave as %d mode.",
1250                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1251                 }
1252
1253                 /* check valid queue number */
1254                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1255                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1256                                         " only support one queue on VFs.");
1257                         return -EINVAL;
1258                 }
1259         } else {
1260                 /* To no break software that set invalid mode, only display
1261                  * warning if invalid mode is used.
1262                  */
1263                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1264                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1265                     rx_mq_mode != ETH_MQ_RX_RSS) {
1266                         /* RSS together with VMDq not supported*/
1267                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1268                                      rx_mq_mode);
1269                         return -EINVAL;
1270                 }
1271
1272                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1273                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1274                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1275                                         " Due to txmode is meaningless in this"
1276                                         " driver, just ignore.",
1277                                         tx_mq_mode);
1278                 }
1279         }
1280         return 0;
1281 }
1282
1283 static int
1284 eth_igb_configure(struct rte_eth_dev *dev)
1285 {
1286         struct e1000_interrupt *intr =
1287                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1288         int ret;
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         /* multipe queue mode checking */
1293         ret  = igb_check_mq_mode(dev);
1294         if (ret != 0) {
1295                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1296                             ret);
1297                 return ret;
1298         }
1299
1300         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1301         PMD_INIT_FUNC_TRACE();
1302
1303         return 0;
1304 }
1305
1306 static int
1307 eth_igb_start(struct rte_eth_dev *dev)
1308 {
1309         struct e1000_hw *hw =
1310                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1311         struct e1000_adapter *adapter =
1312                 E1000_DEV_PRIVATE(dev->data->dev_private);
1313         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1315         int ret, mask;
1316         uint32_t intr_vector = 0;
1317         uint32_t ctrl_ext;
1318         uint32_t *speeds;
1319         int num_speeds;
1320         bool autoneg;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         /* disable uio/vfio intr/eventfd mapping */
1325         rte_intr_disable(intr_handle);
1326
1327         /* Power up the phy. Needed to make the link go Up */
1328         eth_igb_dev_set_link_up(dev);
1329
1330         /*
1331          * Packet Buffer Allocation (PBA)
1332          * Writing PBA sets the receive portion of the buffer
1333          * the remainder is used for the transmit buffer.
1334          */
1335         if (hw->mac.type == e1000_82575) {
1336                 uint32_t pba;
1337
1338                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1339                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1340         }
1341
1342         /* Put the address into the Receive Address Array */
1343         e1000_rar_set(hw, hw->mac.addr, 0);
1344
1345         /* Initialize the hardware */
1346         if (igb_hardware_init(hw)) {
1347                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1348                 return -EIO;
1349         }
1350         adapter->stopped = 0;
1351
1352         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1353
1354         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1355         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1356         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1357         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1358         E1000_WRITE_FLUSH(hw);
1359
1360         /* configure PF module if SRIOV enabled */
1361         igb_pf_host_configure(dev);
1362
1363         /* check and configure queue intr-vector mapping */
1364         if ((rte_intr_cap_multiple(intr_handle) ||
1365              !RTE_ETH_DEV_SRIOV(dev).active) &&
1366             dev->data->dev_conf.intr_conf.rxq != 0) {
1367                 intr_vector = dev->data->nb_rx_queues;
1368                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1369                         return -1;
1370         }
1371
1372         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1373                 intr_handle->intr_vec =
1374                         rte_zmalloc("intr_vec",
1375                                     dev->data->nb_rx_queues * sizeof(int), 0);
1376                 if (intr_handle->intr_vec == NULL) {
1377                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1378                                      " intr_vec", dev->data->nb_rx_queues);
1379                         return -ENOMEM;
1380                 }
1381         }
1382
1383         /* confiugre msix for rx interrupt */
1384         eth_igb_configure_msix_intr(dev);
1385
1386         /* Configure for OS presence */
1387         igb_init_manageability(hw);
1388
1389         eth_igb_tx_init(dev);
1390
1391         /* This can fail when allocating mbufs for descriptor rings */
1392         ret = eth_igb_rx_init(dev);
1393         if (ret) {
1394                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1395                 igb_dev_clear_queues(dev);
1396                 return ret;
1397         }
1398
1399         e1000_clear_hw_cntrs_base_generic(hw);
1400
1401         /*
1402          * VLAN Offload Settings
1403          */
1404         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1405                         ETH_VLAN_EXTEND_MASK;
1406         eth_igb_vlan_offload_set(dev, mask);
1407
1408         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1409                 /* Enable VLAN filter since VMDq always use VLAN filter */
1410                 igb_vmdq_vlan_hw_filter_enable(dev);
1411         }
1412
1413         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1414                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1415                 (hw->mac.type == e1000_i211)) {
1416                 /* Configure EITR with the maximum possible value (0xFFFF) */
1417                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1418         }
1419
1420         /* Setup link speed and duplex */
1421         speeds = &dev->data->dev_conf.link_speeds;
1422         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1423                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1424                 hw->mac.autoneg = 1;
1425         } else {
1426                 num_speeds = 0;
1427                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1428
1429                 /* Reset */
1430                 hw->phy.autoneg_advertised = 0;
1431
1432                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1433                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1434                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1435                         num_speeds = -1;
1436                         goto error_invalid_config;
1437                 }
1438                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1439                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1440                         num_speeds++;
1441                 }
1442                 if (*speeds & ETH_LINK_SPEED_10M) {
1443                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1444                         num_speeds++;
1445                 }
1446                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1447                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1448                         num_speeds++;
1449                 }
1450                 if (*speeds & ETH_LINK_SPEED_100M) {
1451                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1452                         num_speeds++;
1453                 }
1454                 if (*speeds & ETH_LINK_SPEED_1G) {
1455                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1456                         num_speeds++;
1457                 }
1458                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1459                         goto error_invalid_config;
1460
1461                 /* Set/reset the mac.autoneg based on the link speed,
1462                  * fixed or not
1463                  */
1464                 if (!autoneg) {
1465                         hw->mac.autoneg = 0;
1466                         hw->mac.forced_speed_duplex =
1467                                         hw->phy.autoneg_advertised;
1468                 } else {
1469                         hw->mac.autoneg = 1;
1470                 }
1471         }
1472
1473         e1000_setup_link(hw);
1474
1475         if (rte_intr_allow_others(intr_handle)) {
1476                 /* check if lsc interrupt is enabled */
1477                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1478                         eth_igb_lsc_interrupt_setup(dev);
1479         } else {
1480                 rte_intr_callback_unregister(intr_handle,
1481                                              eth_igb_interrupt_handler,
1482                                              (void *)dev);
1483                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1484                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1485                                      " no intr multiplex");
1486         }
1487
1488         /* check if rxq interrupt is enabled */
1489         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1490             rte_intr_dp_is_en(intr_handle))
1491                 eth_igb_rxq_interrupt_setup(dev);
1492
1493         /* enable uio/vfio intr/eventfd mapping */
1494         rte_intr_enable(intr_handle);
1495
1496         /* resume enabled intr since hw reset */
1497         igb_intr_enable(dev);
1498
1499         /* restore all types filter */
1500         igb_filter_restore(dev);
1501
1502         PMD_INIT_LOG(DEBUG, "<<");
1503
1504         return 0;
1505
1506 error_invalid_config:
1507         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1508                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1509         igb_dev_clear_queues(dev);
1510         return -EINVAL;
1511 }
1512
1513 /*********************************************************************
1514  *
1515  *  This routine disables all traffic on the adapter by issuing a
1516  *  global reset on the MAC.
1517  *
1518  **********************************************************************/
1519 static void
1520 eth_igb_stop(struct rte_eth_dev *dev)
1521 {
1522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1524         struct rte_eth_link link;
1525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1526
1527         igb_intr_disable(hw);
1528
1529         /* disable intr eventfd mapping */
1530         rte_intr_disable(intr_handle);
1531
1532         igb_pf_reset_hw(hw);
1533         E1000_WRITE_REG(hw, E1000_WUC, 0);
1534
1535         /* Set bit for Go Link disconnect */
1536         if (hw->mac.type >= e1000_82580) {
1537                 uint32_t phpm_reg;
1538
1539                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1540                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1541                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1542         }
1543
1544         /* Power down the phy. Needed to make the link go Down */
1545         eth_igb_dev_set_link_down(dev);
1546
1547         igb_dev_clear_queues(dev);
1548
1549         /* clear the recorded link status */
1550         memset(&link, 0, sizeof(link));
1551         rte_igb_dev_atomic_write_link_status(dev, &link);
1552
1553         if (!rte_intr_allow_others(intr_handle))
1554                 /* resume to the default handler */
1555                 rte_intr_callback_register(intr_handle,
1556                                            eth_igb_interrupt_handler,
1557                                            (void *)dev);
1558
1559         /* Clean datapath event and queue/vec mapping */
1560         rte_intr_efd_disable(intr_handle);
1561         if (intr_handle->intr_vec != NULL) {
1562                 rte_free(intr_handle->intr_vec);
1563                 intr_handle->intr_vec = NULL;
1564         }
1565 }
1566
1567 static int
1568 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1569 {
1570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571
1572         if (hw->phy.media_type == e1000_media_type_copper)
1573                 e1000_power_up_phy(hw);
1574         else
1575                 e1000_power_up_fiber_serdes_link(hw);
1576
1577         return 0;
1578 }
1579
1580 static int
1581 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1582 {
1583         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584
1585         if (hw->phy.media_type == e1000_media_type_copper)
1586                 e1000_power_down_phy(hw);
1587         else
1588                 e1000_shutdown_fiber_serdes_link(hw);
1589
1590         return 0;
1591 }
1592
1593 static void
1594 eth_igb_close(struct rte_eth_dev *dev)
1595 {
1596         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597         struct e1000_adapter *adapter =
1598                 E1000_DEV_PRIVATE(dev->data->dev_private);
1599         struct rte_eth_link link;
1600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1602
1603         eth_igb_stop(dev);
1604         adapter->stopped = 1;
1605
1606         e1000_phy_hw_reset(hw);
1607         igb_release_manageability(hw);
1608         igb_hw_control_release(hw);
1609
1610         /* Clear bit for Go Link disconnect */
1611         if (hw->mac.type >= e1000_82580) {
1612                 uint32_t phpm_reg;
1613
1614                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1615                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1616                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1617         }
1618
1619         igb_dev_free_queues(dev);
1620
1621         if (intr_handle->intr_vec) {
1622                 rte_free(intr_handle->intr_vec);
1623                 intr_handle->intr_vec = NULL;
1624         }
1625
1626         memset(&link, 0, sizeof(link));
1627         rte_igb_dev_atomic_write_link_status(dev, &link);
1628 }
1629
1630 static int
1631 igb_get_rx_buffer_size(struct e1000_hw *hw)
1632 {
1633         uint32_t rx_buf_size;
1634         if (hw->mac.type == e1000_82576) {
1635                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1636         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1637                 /* PBS needs to be translated according to a lookup table */
1638                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1639                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1640                 rx_buf_size = (rx_buf_size << 10);
1641         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1642                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1643         } else {
1644                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1645         }
1646
1647         return rx_buf_size;
1648 }
1649
1650 /*********************************************************************
1651  *
1652  *  Initialize the hardware
1653  *
1654  **********************************************************************/
1655 static int
1656 igb_hardware_init(struct e1000_hw *hw)
1657 {
1658         uint32_t rx_buf_size;
1659         int diag;
1660
1661         /* Let the firmware know the OS is in control */
1662         igb_hw_control_acquire(hw);
1663
1664         /*
1665          * These parameters control the automatic generation (Tx) and
1666          * response (Rx) to Ethernet PAUSE frames.
1667          * - High water mark should allow for at least two standard size (1518)
1668          *   frames to be received after sending an XOFF.
1669          * - Low water mark works best when it is very near the high water mark.
1670          *   This allows the receiver to restart by sending XON when it has
1671          *   drained a bit. Here we use an arbitrary value of 1500 which will
1672          *   restart after one full frame is pulled from the buffer. There
1673          *   could be several smaller frames in the buffer and if so they will
1674          *   not trigger the XON until their total number reduces the buffer
1675          *   by 1500.
1676          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1677          */
1678         rx_buf_size = igb_get_rx_buffer_size(hw);
1679
1680         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1681         hw->fc.low_water = hw->fc.high_water - 1500;
1682         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1683         hw->fc.send_xon = 1;
1684
1685         /* Set Flow control, use the tunable location if sane */
1686         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1687                 hw->fc.requested_mode = igb_fc_setting;
1688         else
1689                 hw->fc.requested_mode = e1000_fc_none;
1690
1691         /* Issue a global reset */
1692         igb_pf_reset_hw(hw);
1693         E1000_WRITE_REG(hw, E1000_WUC, 0);
1694
1695         diag = e1000_init_hw(hw);
1696         if (diag < 0)
1697                 return diag;
1698
1699         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1700         e1000_get_phy_info(hw);
1701         e1000_check_for_link(hw);
1702
1703         return 0;
1704 }
1705
1706 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1707 static void
1708 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1709 {
1710         int pause_frames;
1711
1712         uint64_t old_gprc  = stats->gprc;
1713         uint64_t old_gptc  = stats->gptc;
1714         uint64_t old_tpr   = stats->tpr;
1715         uint64_t old_tpt   = stats->tpt;
1716         uint64_t old_rpthc = stats->rpthc;
1717         uint64_t old_hgptc = stats->hgptc;
1718
1719         if(hw->phy.media_type == e1000_media_type_copper ||
1720             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1721                 stats->symerrs +=
1722                     E1000_READ_REG(hw,E1000_SYMERRS);
1723                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1724         }
1725
1726         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1727         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1728         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1729         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1730
1731         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1732         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1733         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1734         stats->dc += E1000_READ_REG(hw, E1000_DC);
1735         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1736         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1737         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1738         /*
1739         ** For watchdog management we need to know if we have been
1740         ** paused during the last interval, so capture that here.
1741         */
1742         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1743         stats->xoffrxc += pause_frames;
1744         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1745         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1746         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1747         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1748         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1749         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1750         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1751         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1752         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1753         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1754         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1755         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1756
1757         /* For the 64-bit byte counters the low dword must be read first. */
1758         /* Both registers clear on the read of the high dword */
1759
1760         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1761         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1762         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1763         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1764         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1765         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1766         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1767
1768         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1769         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1770         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1771         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1772         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1773
1774         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1775         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1776
1777         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1778         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1779         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1780         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1781         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1782         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1783
1784         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1785         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1786         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1787         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1788         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1789         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1790         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1791         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1792
1793         /* Interrupt Counts */
1794
1795         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1796         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1797         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1798         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1799         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1800         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1801         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1802         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1803         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1804
1805         /* Host to Card Statistics */
1806
1807         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1808         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1809         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1810         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1811         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1812         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1813         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1814         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1815         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1816         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1817         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1818         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1819         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1820         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1821         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1822         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1823
1824         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1825         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1826         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1827         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1828         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1829         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1830 }
1831
1832 static void
1833 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1834 {
1835         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct e1000_hw_stats *stats =
1837                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1838
1839         igb_read_stats_registers(hw, stats);
1840
1841         if (rte_stats == NULL)
1842                 return;
1843
1844         /* Rx Errors */
1845         rte_stats->imissed = stats->mpc;
1846         rte_stats->ierrors = stats->crcerrs +
1847                              stats->rlec + stats->ruc + stats->roc +
1848                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1849
1850         /* Tx Errors */
1851         rte_stats->oerrors = stats->ecol + stats->latecol;
1852
1853         rte_stats->ipackets = stats->gprc;
1854         rte_stats->opackets = stats->gptc;
1855         rte_stats->ibytes   = stats->gorc;
1856         rte_stats->obytes   = stats->gotc;
1857 }
1858
1859 static void
1860 eth_igb_stats_reset(struct rte_eth_dev *dev)
1861 {
1862         struct e1000_hw_stats *hw_stats =
1863                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1864
1865         /* HW registers are cleared on read */
1866         eth_igb_stats_get(dev, NULL);
1867
1868         /* Reset software totals */
1869         memset(hw_stats, 0, sizeof(*hw_stats));
1870 }
1871
1872 static void
1873 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1874 {
1875         struct e1000_hw_stats *stats =
1876                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1877
1878         /* HW registers are cleared on read */
1879         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1880
1881         /* Reset software totals */
1882         memset(stats, 0, sizeof(*stats));
1883 }
1884
1885 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1886         struct rte_eth_xstat_name *xstats_names,
1887         __rte_unused unsigned int size)
1888 {
1889         unsigned i;
1890
1891         if (xstats_names == NULL)
1892                 return IGB_NB_XSTATS;
1893
1894         /* Note: limit checked in rte_eth_xstats_names() */
1895
1896         for (i = 0; i < IGB_NB_XSTATS; i++) {
1897                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1898                          "%s", rte_igb_stats_strings[i].name);
1899         }
1900
1901         return IGB_NB_XSTATS;
1902 }
1903
1904 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1905                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1906                 unsigned int limit)
1907 {
1908         unsigned int i;
1909
1910         if (!ids) {
1911                 if (xstats_names == NULL)
1912                         return IGB_NB_XSTATS;
1913
1914                 for (i = 0; i < IGB_NB_XSTATS; i++)
1915                         snprintf(xstats_names[i].name,
1916                                         sizeof(xstats_names[i].name),
1917                                         "%s", rte_igb_stats_strings[i].name);
1918
1919                 return IGB_NB_XSTATS;
1920
1921         } else {
1922                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1923
1924                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1925                                 IGB_NB_XSTATS);
1926
1927                 for (i = 0; i < limit; i++) {
1928                         if (ids[i] >= IGB_NB_XSTATS) {
1929                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1930                                 return -1;
1931                         }
1932                         strcpy(xstats_names[i].name,
1933                                         xstats_names_copy[ids[i]].name);
1934                 }
1935                 return limit;
1936         }
1937 }
1938
1939 static int
1940 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1941                    unsigned n)
1942 {
1943         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944         struct e1000_hw_stats *hw_stats =
1945                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1946         unsigned i;
1947
1948         if (n < IGB_NB_XSTATS)
1949                 return IGB_NB_XSTATS;
1950
1951         igb_read_stats_registers(hw, hw_stats);
1952
1953         /* If this is a reset xstats is NULL, and we have cleared the
1954          * registers by reading them.
1955          */
1956         if (!xstats)
1957                 return 0;
1958
1959         /* Extended stats */
1960         for (i = 0; i < IGB_NB_XSTATS; i++) {
1961                 xstats[i].id = i;
1962                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1963                         rte_igb_stats_strings[i].offset);
1964         }
1965
1966         return IGB_NB_XSTATS;
1967 }
1968
1969 static int
1970 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1971                 uint64_t *values, unsigned int n)
1972 {
1973         unsigned int i;
1974
1975         if (!ids) {
1976                 struct e1000_hw *hw =
1977                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978                 struct e1000_hw_stats *hw_stats =
1979                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1980
1981                 if (n < IGB_NB_XSTATS)
1982                         return IGB_NB_XSTATS;
1983
1984                 igb_read_stats_registers(hw, hw_stats);
1985
1986                 /* If this is a reset xstats is NULL, and we have cleared the
1987                  * registers by reading them.
1988                  */
1989                 if (!values)
1990                         return 0;
1991
1992                 /* Extended stats */
1993                 for (i = 0; i < IGB_NB_XSTATS; i++)
1994                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1995                                         rte_igb_stats_strings[i].offset);
1996
1997                 return IGB_NB_XSTATS;
1998
1999         } else {
2000                 uint64_t values_copy[IGB_NB_XSTATS];
2001
2002                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
2003                                 IGB_NB_XSTATS);
2004
2005                 for (i = 0; i < n; i++) {
2006                         if (ids[i] >= IGB_NB_XSTATS) {
2007                                 PMD_INIT_LOG(ERR, "id value isn't valid");
2008                                 return -1;
2009                         }
2010                         values[i] = values_copy[ids[i]];
2011                 }
2012                 return n;
2013         }
2014 }
2015
2016 static void
2017 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2018 {
2019         /* Good Rx packets, include VF loopback */
2020         UPDATE_VF_STAT(E1000_VFGPRC,
2021             hw_stats->last_gprc, hw_stats->gprc);
2022
2023         /* Good Rx octets, include VF loopback */
2024         UPDATE_VF_STAT(E1000_VFGORC,
2025             hw_stats->last_gorc, hw_stats->gorc);
2026
2027         /* Good Tx packets, include VF loopback */
2028         UPDATE_VF_STAT(E1000_VFGPTC,
2029             hw_stats->last_gptc, hw_stats->gptc);
2030
2031         /* Good Tx octets, include VF loopback */
2032         UPDATE_VF_STAT(E1000_VFGOTC,
2033             hw_stats->last_gotc, hw_stats->gotc);
2034
2035         /* Rx Multicst packets */
2036         UPDATE_VF_STAT(E1000_VFMPRC,
2037             hw_stats->last_mprc, hw_stats->mprc);
2038
2039         /* Good Rx loopback packets */
2040         UPDATE_VF_STAT(E1000_VFGPRLBC,
2041             hw_stats->last_gprlbc, hw_stats->gprlbc);
2042
2043         /* Good Rx loopback octets */
2044         UPDATE_VF_STAT(E1000_VFGORLBC,
2045             hw_stats->last_gorlbc, hw_stats->gorlbc);
2046
2047         /* Good Tx loopback packets */
2048         UPDATE_VF_STAT(E1000_VFGPTLBC,
2049             hw_stats->last_gptlbc, hw_stats->gptlbc);
2050
2051         /* Good Tx loopback octets */
2052         UPDATE_VF_STAT(E1000_VFGOTLBC,
2053             hw_stats->last_gotlbc, hw_stats->gotlbc);
2054 }
2055
2056 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2057                                      struct rte_eth_xstat_name *xstats_names,
2058                                      __rte_unused unsigned limit)
2059 {
2060         unsigned i;
2061
2062         if (xstats_names != NULL)
2063                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2064                         snprintf(xstats_names[i].name,
2065                                 sizeof(xstats_names[i].name), "%s",
2066                                 rte_igbvf_stats_strings[i].name);
2067                 }
2068         return IGBVF_NB_XSTATS;
2069 }
2070
2071 static int
2072 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2073                      unsigned n)
2074 {
2075         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2077                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2078         unsigned i;
2079
2080         if (n < IGBVF_NB_XSTATS)
2081                 return IGBVF_NB_XSTATS;
2082
2083         igbvf_read_stats_registers(hw, hw_stats);
2084
2085         if (!xstats)
2086                 return 0;
2087
2088         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2089                 xstats[i].id = i;
2090                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2091                         rte_igbvf_stats_strings[i].offset);
2092         }
2093
2094         return IGBVF_NB_XSTATS;
2095 }
2096
2097 static void
2098 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2099 {
2100         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2102                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2103
2104         igbvf_read_stats_registers(hw, hw_stats);
2105
2106         if (rte_stats == NULL)
2107                 return;
2108
2109         rte_stats->ipackets = hw_stats->gprc;
2110         rte_stats->ibytes = hw_stats->gorc;
2111         rte_stats->opackets = hw_stats->gptc;
2112         rte_stats->obytes = hw_stats->gotc;
2113 }
2114
2115 static void
2116 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2117 {
2118         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2119                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2120
2121         /* Sync HW register to the last stats */
2122         eth_igbvf_stats_get(dev, NULL);
2123
2124         /* reset HW current stats*/
2125         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2126                offsetof(struct e1000_vf_stats, gprc));
2127 }
2128
2129 static int
2130 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2131                        size_t fw_size)
2132 {
2133         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct e1000_fw_version fw;
2135         int ret;
2136
2137         e1000_get_fw_version(hw, &fw);
2138
2139         switch (hw->mac.type) {
2140         case e1000_i210:
2141         case e1000_i211:
2142                 if (!(e1000_get_flash_presence_i210(hw))) {
2143                         ret = snprintf(fw_version, fw_size,
2144                                  "%2d.%2d-%d",
2145                                  fw.invm_major, fw.invm_minor,
2146                                  fw.invm_img_type);
2147                         break;
2148                 }
2149                 /* fall through */
2150         default:
2151                 /* if option rom is valid, display its version too */
2152                 if (fw.or_valid) {
2153                         ret = snprintf(fw_version, fw_size,
2154                                  "%d.%d, 0x%08x, %d.%d.%d",
2155                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2156                                  fw.or_major, fw.or_build, fw.or_patch);
2157                 /* no option rom */
2158                 } else {
2159                         if (fw.etrack_id != 0X0000) {
2160                                 ret = snprintf(fw_version, fw_size,
2161                                          "%d.%d, 0x%08x",
2162                                          fw.eep_major, fw.eep_minor,
2163                                          fw.etrack_id);
2164                         } else {
2165                                 ret = snprintf(fw_version, fw_size,
2166                                          "%d.%d.%d",
2167                                          fw.eep_major, fw.eep_minor,
2168                                          fw.eep_build);
2169                         }
2170                 }
2171                 break;
2172         }
2173
2174         ret += 1; /* add the size of '\0' */
2175         if (fw_size < (u32)ret)
2176                 return ret;
2177         else
2178                 return 0;
2179 }
2180
2181 static void
2182 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2183 {
2184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2185
2186         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2187         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2188         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2189         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2190         dev_info->rx_offload_capa =
2191                 DEV_RX_OFFLOAD_VLAN_STRIP |
2192                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2193                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2194                 DEV_RX_OFFLOAD_TCP_CKSUM;
2195         dev_info->tx_offload_capa =
2196                 DEV_TX_OFFLOAD_VLAN_INSERT |
2197                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2198                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2199                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2200                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2201                 DEV_TX_OFFLOAD_TCP_TSO;
2202
2203         switch (hw->mac.type) {
2204         case e1000_82575:
2205                 dev_info->max_rx_queues = 4;
2206                 dev_info->max_tx_queues = 4;
2207                 dev_info->max_vmdq_pools = 0;
2208                 break;
2209
2210         case e1000_82576:
2211                 dev_info->max_rx_queues = 16;
2212                 dev_info->max_tx_queues = 16;
2213                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2214                 dev_info->vmdq_queue_num = 16;
2215                 break;
2216
2217         case e1000_82580:
2218                 dev_info->max_rx_queues = 8;
2219                 dev_info->max_tx_queues = 8;
2220                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2221                 dev_info->vmdq_queue_num = 8;
2222                 break;
2223
2224         case e1000_i350:
2225                 dev_info->max_rx_queues = 8;
2226                 dev_info->max_tx_queues = 8;
2227                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2228                 dev_info->vmdq_queue_num = 8;
2229                 break;
2230
2231         case e1000_i354:
2232                 dev_info->max_rx_queues = 8;
2233                 dev_info->max_tx_queues = 8;
2234                 break;
2235
2236         case e1000_i210:
2237                 dev_info->max_rx_queues = 4;
2238                 dev_info->max_tx_queues = 4;
2239                 dev_info->max_vmdq_pools = 0;
2240                 break;
2241
2242         case e1000_i211:
2243                 dev_info->max_rx_queues = 2;
2244                 dev_info->max_tx_queues = 2;
2245                 dev_info->max_vmdq_pools = 0;
2246                 break;
2247
2248         default:
2249                 /* Should not happen */
2250                 break;
2251         }
2252         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2253         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2254         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2255
2256         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2257                 .rx_thresh = {
2258                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2259                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2260                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2261                 },
2262                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2263                 .rx_drop_en = 0,
2264         };
2265
2266         dev_info->default_txconf = (struct rte_eth_txconf) {
2267                 .tx_thresh = {
2268                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2269                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2270                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2271                 },
2272                 .txq_flags = 0,
2273         };
2274
2275         dev_info->rx_desc_lim = rx_desc_lim;
2276         dev_info->tx_desc_lim = tx_desc_lim;
2277
2278         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2279                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2280                         ETH_LINK_SPEED_1G;
2281 }
2282
2283 static const uint32_t *
2284 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2285 {
2286         static const uint32_t ptypes[] = {
2287                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2288                 RTE_PTYPE_L2_ETHER,
2289                 RTE_PTYPE_L3_IPV4,
2290                 RTE_PTYPE_L3_IPV4_EXT,
2291                 RTE_PTYPE_L3_IPV6,
2292                 RTE_PTYPE_L3_IPV6_EXT,
2293                 RTE_PTYPE_L4_TCP,
2294                 RTE_PTYPE_L4_UDP,
2295                 RTE_PTYPE_L4_SCTP,
2296                 RTE_PTYPE_TUNNEL_IP,
2297                 RTE_PTYPE_INNER_L3_IPV6,
2298                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2299                 RTE_PTYPE_INNER_L4_TCP,
2300                 RTE_PTYPE_INNER_L4_UDP,
2301                 RTE_PTYPE_UNKNOWN
2302         };
2303
2304         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2305             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2306                 return ptypes;
2307         return NULL;
2308 }
2309
2310 static void
2311 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2312 {
2313         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314
2315         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2316         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2317         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2318         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2319         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2320                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2321                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2322                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2323         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2324                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2325                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2326                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2327                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2328                                 DEV_TX_OFFLOAD_TCP_TSO;
2329         switch (hw->mac.type) {
2330         case e1000_vfadapt:
2331                 dev_info->max_rx_queues = 2;
2332                 dev_info->max_tx_queues = 2;
2333                 break;
2334         case e1000_vfadapt_i350:
2335                 dev_info->max_rx_queues = 1;
2336                 dev_info->max_tx_queues = 1;
2337                 break;
2338         default:
2339                 /* Should not happen */
2340                 break;
2341         }
2342
2343         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2344                 .rx_thresh = {
2345                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2346                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2347                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2348                 },
2349                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2350                 .rx_drop_en = 0,
2351         };
2352
2353         dev_info->default_txconf = (struct rte_eth_txconf) {
2354                 .tx_thresh = {
2355                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2356                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2357                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2358                 },
2359                 .txq_flags = 0,
2360         };
2361
2362         dev_info->rx_desc_lim = rx_desc_lim;
2363         dev_info->tx_desc_lim = tx_desc_lim;
2364 }
2365
2366 /* return 0 means link status changed, -1 means not changed */
2367 static int
2368 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2369 {
2370         struct e1000_hw *hw =
2371                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct rte_eth_link link, old;
2373         int link_check, count;
2374
2375         link_check = 0;
2376         hw->mac.get_link_status = 1;
2377
2378         /* possible wait-to-complete in up to 9 seconds */
2379         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2380                 /* Read the real link status */
2381                 switch (hw->phy.media_type) {
2382                 case e1000_media_type_copper:
2383                         /* Do the work to read phy */
2384                         e1000_check_for_link(hw);
2385                         link_check = !hw->mac.get_link_status;
2386                         break;
2387
2388                 case e1000_media_type_fiber:
2389                         e1000_check_for_link(hw);
2390                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2391                                       E1000_STATUS_LU);
2392                         break;
2393
2394                 case e1000_media_type_internal_serdes:
2395                         e1000_check_for_link(hw);
2396                         link_check = hw->mac.serdes_has_link;
2397                         break;
2398
2399                 /* VF device is type_unknown */
2400                 case e1000_media_type_unknown:
2401                         eth_igbvf_link_update(hw);
2402                         link_check = !hw->mac.get_link_status;
2403                         break;
2404
2405                 default:
2406                         break;
2407                 }
2408                 if (link_check || wait_to_complete == 0)
2409                         break;
2410                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2411         }
2412         memset(&link, 0, sizeof(link));
2413         rte_igb_dev_atomic_read_link_status(dev, &link);
2414         old = link;
2415
2416         /* Now we check if a transition has happened */
2417         if (link_check) {
2418                 uint16_t duplex, speed;
2419                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2420                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2421                                 ETH_LINK_FULL_DUPLEX :
2422                                 ETH_LINK_HALF_DUPLEX;
2423                 link.link_speed = speed;
2424                 link.link_status = ETH_LINK_UP;
2425                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2426                                 ETH_LINK_SPEED_FIXED);
2427         } else if (!link_check) {
2428                 link.link_speed = 0;
2429                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2430                 link.link_status = ETH_LINK_DOWN;
2431                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2432         }
2433         rte_igb_dev_atomic_write_link_status(dev, &link);
2434
2435         /* not changed */
2436         if (old.link_status == link.link_status)
2437                 return -1;
2438
2439         /* changed */
2440         return 0;
2441 }
2442
2443 /*
2444  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2445  * For ASF and Pass Through versions of f/w this means
2446  * that the driver is loaded.
2447  */
2448 static void
2449 igb_hw_control_acquire(struct e1000_hw *hw)
2450 {
2451         uint32_t ctrl_ext;
2452
2453         /* Let firmware know the driver has taken over */
2454         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2455         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2456 }
2457
2458 /*
2459  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2460  * For ASF and Pass Through versions of f/w this means that the
2461  * driver is no longer loaded.
2462  */
2463 static void
2464 igb_hw_control_release(struct e1000_hw *hw)
2465 {
2466         uint32_t ctrl_ext;
2467
2468         /* Let firmware taken over control of h/w */
2469         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2470         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2471                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2472 }
2473
2474 /*
2475  * Bit of a misnomer, what this really means is
2476  * to enable OS management of the system... aka
2477  * to disable special hardware management features.
2478  */
2479 static void
2480 igb_init_manageability(struct e1000_hw *hw)
2481 {
2482         if (e1000_enable_mng_pass_thru(hw)) {
2483                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2484                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2485
2486                 /* disable hardware interception of ARP */
2487                 manc &= ~(E1000_MANC_ARP_EN);
2488
2489                 /* enable receiving management packets to the host */
2490                 manc |= E1000_MANC_EN_MNG2HOST;
2491                 manc2h |= 1 << 5;  /* Mng Port 623 */
2492                 manc2h |= 1 << 6;  /* Mng Port 664 */
2493                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2494                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2495         }
2496 }
2497
2498 static void
2499 igb_release_manageability(struct e1000_hw *hw)
2500 {
2501         if (e1000_enable_mng_pass_thru(hw)) {
2502                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2503
2504                 manc |= E1000_MANC_ARP_EN;
2505                 manc &= ~E1000_MANC_EN_MNG2HOST;
2506
2507                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2508         }
2509 }
2510
2511 static void
2512 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2513 {
2514         struct e1000_hw *hw =
2515                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         uint32_t rctl;
2517
2518         rctl = E1000_READ_REG(hw, E1000_RCTL);
2519         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2520         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2521 }
2522
2523 static void
2524 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2525 {
2526         struct e1000_hw *hw =
2527                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528         uint32_t rctl;
2529
2530         rctl = E1000_READ_REG(hw, E1000_RCTL);
2531         rctl &= (~E1000_RCTL_UPE);
2532         if (dev->data->all_multicast == 1)
2533                 rctl |= E1000_RCTL_MPE;
2534         else
2535                 rctl &= (~E1000_RCTL_MPE);
2536         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2537 }
2538
2539 static void
2540 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2541 {
2542         struct e1000_hw *hw =
2543                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544         uint32_t rctl;
2545
2546         rctl = E1000_READ_REG(hw, E1000_RCTL);
2547         rctl |= E1000_RCTL_MPE;
2548         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2549 }
2550
2551 static void
2552 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2553 {
2554         struct e1000_hw *hw =
2555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2556         uint32_t rctl;
2557
2558         if (dev->data->promiscuous == 1)
2559                 return; /* must remain in all_multicast mode */
2560         rctl = E1000_READ_REG(hw, E1000_RCTL);
2561         rctl &= (~E1000_RCTL_MPE);
2562         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2563 }
2564
2565 static int
2566 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2567 {
2568         struct e1000_hw *hw =
2569                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         struct e1000_vfta * shadow_vfta =
2571                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2572         uint32_t vfta;
2573         uint32_t vid_idx;
2574         uint32_t vid_bit;
2575
2576         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2577                               E1000_VFTA_ENTRY_MASK);
2578         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2579         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2580         if (on)
2581                 vfta |= vid_bit;
2582         else
2583                 vfta &= ~vid_bit;
2584         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2585
2586         /* update local VFTA copy */
2587         shadow_vfta->vfta[vid_idx] = vfta;
2588
2589         return 0;
2590 }
2591
2592 static int
2593 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2594                       enum rte_vlan_type vlan_type,
2595                       uint16_t tpid)
2596 {
2597         struct e1000_hw *hw =
2598                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2599         uint32_t reg, qinq;
2600
2601         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2602         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2603
2604         /* only outer TPID of double VLAN can be configured*/
2605         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2606                 reg = E1000_READ_REG(hw, E1000_VET);
2607                 reg = (reg & (~E1000_VET_VET_EXT)) |
2608                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2609                 E1000_WRITE_REG(hw, E1000_VET, reg);
2610
2611                 return 0;
2612         }
2613
2614         /* all other TPID values are read-only*/
2615         PMD_DRV_LOG(ERR, "Not supported");
2616
2617         return -ENOTSUP;
2618 }
2619
2620 static void
2621 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2622 {
2623         struct e1000_hw *hw =
2624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625         uint32_t reg;
2626
2627         /* Filter Table Disable */
2628         reg = E1000_READ_REG(hw, E1000_RCTL);
2629         reg &= ~E1000_RCTL_CFIEN;
2630         reg &= ~E1000_RCTL_VFE;
2631         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2632 }
2633
2634 static void
2635 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2636 {
2637         struct e1000_hw *hw =
2638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         struct e1000_vfta * shadow_vfta =
2640                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2641         uint32_t reg;
2642         int i;
2643
2644         /* Filter Table Enable, CFI not used for packet acceptance */
2645         reg = E1000_READ_REG(hw, E1000_RCTL);
2646         reg &= ~E1000_RCTL_CFIEN;
2647         reg |= E1000_RCTL_VFE;
2648         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2649
2650         /* restore VFTA table */
2651         for (i = 0; i < IGB_VFTA_SIZE; i++)
2652                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2653 }
2654
2655 static void
2656 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2657 {
2658         struct e1000_hw *hw =
2659                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660         uint32_t reg;
2661
2662         /* VLAN Mode Disable */
2663         reg = E1000_READ_REG(hw, E1000_CTRL);
2664         reg &= ~E1000_CTRL_VME;
2665         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2666 }
2667
2668 static void
2669 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2670 {
2671         struct e1000_hw *hw =
2672                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2673         uint32_t reg;
2674
2675         /* VLAN Mode Enable */
2676         reg = E1000_READ_REG(hw, E1000_CTRL);
2677         reg |= E1000_CTRL_VME;
2678         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2679 }
2680
2681 static void
2682 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2683 {
2684         struct e1000_hw *hw =
2685                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2686         uint32_t reg;
2687
2688         /* CTRL_EXT: Extended VLAN */
2689         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2690         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2691         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2692
2693         /* Update maximum packet length */
2694         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2695                 E1000_WRITE_REG(hw, E1000_RLPML,
2696                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2697                                                 VLAN_TAG_SIZE);
2698 }
2699
2700 static void
2701 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2702 {
2703         struct e1000_hw *hw =
2704                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         uint32_t reg;
2706
2707         /* CTRL_EXT: Extended VLAN */
2708         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2709         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2710         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2711
2712         /* Update maximum packet length */
2713         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2714                 E1000_WRITE_REG(hw, E1000_RLPML,
2715                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2716                                                 2 * VLAN_TAG_SIZE);
2717 }
2718
2719 static void
2720 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2721 {
2722         if(mask & ETH_VLAN_STRIP_MASK){
2723                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2724                         igb_vlan_hw_strip_enable(dev);
2725                 else
2726                         igb_vlan_hw_strip_disable(dev);
2727         }
2728
2729         if(mask & ETH_VLAN_FILTER_MASK){
2730                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2731                         igb_vlan_hw_filter_enable(dev);
2732                 else
2733                         igb_vlan_hw_filter_disable(dev);
2734         }
2735
2736         if(mask & ETH_VLAN_EXTEND_MASK){
2737                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2738                         igb_vlan_hw_extend_enable(dev);
2739                 else
2740                         igb_vlan_hw_extend_disable(dev);
2741         }
2742 }
2743
2744
2745 /**
2746  * It enables the interrupt mask and then enable the interrupt.
2747  *
2748  * @param dev
2749  *  Pointer to struct rte_eth_dev.
2750  *
2751  * @return
2752  *  - On success, zero.
2753  *  - On failure, a negative value.
2754  */
2755 static int
2756 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2757 {
2758         struct e1000_interrupt *intr =
2759                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2760
2761         intr->mask |= E1000_ICR_LSC;
2762
2763         return 0;
2764 }
2765
2766 /* It clears the interrupt causes and enables the interrupt.
2767  * It will be called once only during nic initialized.
2768  *
2769  * @param dev
2770  *  Pointer to struct rte_eth_dev.
2771  *
2772  * @return
2773  *  - On success, zero.
2774  *  - On failure, a negative value.
2775  */
2776 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2777 {
2778         uint32_t mask, regval;
2779         struct e1000_hw *hw =
2780                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781         struct rte_eth_dev_info dev_info;
2782
2783         memset(&dev_info, 0, sizeof(dev_info));
2784         eth_igb_infos_get(dev, &dev_info);
2785
2786         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2787         regval = E1000_READ_REG(hw, E1000_EIMS);
2788         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2789
2790         return 0;
2791 }
2792
2793 /*
2794  * It reads ICR and gets interrupt causes, check it and set a bit flag
2795  * to update link status.
2796  *
2797  * @param dev
2798  *  Pointer to struct rte_eth_dev.
2799  *
2800  * @return
2801  *  - On success, zero.
2802  *  - On failure, a negative value.
2803  */
2804 static int
2805 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2806 {
2807         uint32_t icr;
2808         struct e1000_hw *hw =
2809                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         struct e1000_interrupt *intr =
2811                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2812
2813         igb_intr_disable(hw);
2814
2815         /* read-on-clear nic registers here */
2816         icr = E1000_READ_REG(hw, E1000_ICR);
2817
2818         intr->flags = 0;
2819         if (icr & E1000_ICR_LSC) {
2820                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2821         }
2822
2823         if (icr & E1000_ICR_VMMB)
2824                 intr->flags |= E1000_FLAG_MAILBOX;
2825
2826         return 0;
2827 }
2828
2829 /*
2830  * It executes link_update after knowing an interrupt is prsent.
2831  *
2832  * @param dev
2833  *  Pointer to struct rte_eth_dev.
2834  *
2835  * @return
2836  *  - On success, zero.
2837  *  - On failure, a negative value.
2838  */
2839 static int
2840 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2841                          struct rte_intr_handle *intr_handle)
2842 {
2843         struct e1000_hw *hw =
2844                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845         struct e1000_interrupt *intr =
2846                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2848         uint32_t tctl, rctl;
2849         struct rte_eth_link link;
2850         int ret;
2851
2852         if (intr->flags & E1000_FLAG_MAILBOX) {
2853                 igb_pf_mbx_process(dev);
2854                 intr->flags &= ~E1000_FLAG_MAILBOX;
2855         }
2856
2857         igb_intr_enable(dev);
2858         rte_intr_enable(intr_handle);
2859
2860         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2861                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2862
2863                 /* set get_link_status to check register later */
2864                 hw->mac.get_link_status = 1;
2865                 ret = eth_igb_link_update(dev, 0);
2866
2867                 /* check if link has changed */
2868                 if (ret < 0)
2869                         return 0;
2870
2871                 memset(&link, 0, sizeof(link));
2872                 rte_igb_dev_atomic_read_link_status(dev, &link);
2873                 if (link.link_status) {
2874                         PMD_INIT_LOG(INFO,
2875                                      " Port %d: Link Up - speed %u Mbps - %s",
2876                                      dev->data->port_id,
2877                                      (unsigned)link.link_speed,
2878                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2879                                      "full-duplex" : "half-duplex");
2880                 } else {
2881                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2882                                      dev->data->port_id);
2883                 }
2884
2885                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2886                              pci_dev->addr.domain,
2887                              pci_dev->addr.bus,
2888                              pci_dev->addr.devid,
2889                              pci_dev->addr.function);
2890                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2891                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2892                 if (link.link_status) {
2893                         /* enable Tx/Rx */
2894                         tctl |= E1000_TCTL_EN;
2895                         rctl |= E1000_RCTL_EN;
2896                 } else {
2897                         /* disable Tx/Rx */
2898                         tctl &= ~E1000_TCTL_EN;
2899                         rctl &= ~E1000_RCTL_EN;
2900                 }
2901                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2902                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2903                 E1000_WRITE_FLUSH(hw);
2904                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2905         }
2906
2907         return 0;
2908 }
2909
2910 /**
2911  * Interrupt handler which shall be registered at first.
2912  *
2913  * @param handle
2914  *  Pointer to interrupt handle.
2915  * @param param
2916  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2917  *
2918  * @return
2919  *  void
2920  */
2921 static void
2922 eth_igb_interrupt_handler(void *param)
2923 {
2924         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2925
2926         eth_igb_interrupt_get_status(dev);
2927         eth_igb_interrupt_action(dev, dev->intr_handle);
2928 }
2929
2930 static int
2931 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2932 {
2933         uint32_t eicr;
2934         struct e1000_hw *hw =
2935                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2936         struct e1000_interrupt *intr =
2937                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2938
2939         igbvf_intr_disable(hw);
2940
2941         /* read-on-clear nic registers here */
2942         eicr = E1000_READ_REG(hw, E1000_EICR);
2943         intr->flags = 0;
2944
2945         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2946                 intr->flags |= E1000_FLAG_MAILBOX;
2947
2948         return 0;
2949 }
2950
2951 void igbvf_mbx_process(struct rte_eth_dev *dev)
2952 {
2953         struct e1000_hw *hw =
2954                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         struct e1000_mbx_info *mbx = &hw->mbx;
2956         u32 in_msg = 0;
2957
2958         if (mbx->ops.read(hw, &in_msg, 1, 0))
2959                 return;
2960
2961         /* PF reset VF event */
2962         if (in_msg == E1000_PF_CONTROL_MSG)
2963                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2964 }
2965
2966 static int
2967 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2968 {
2969         struct e1000_interrupt *intr =
2970                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2971
2972         if (intr->flags & E1000_FLAG_MAILBOX) {
2973                 igbvf_mbx_process(dev);
2974                 intr->flags &= ~E1000_FLAG_MAILBOX;
2975         }
2976
2977         igbvf_intr_enable(dev);
2978         rte_intr_enable(intr_handle);
2979
2980         return 0;
2981 }
2982
2983 static void
2984 eth_igbvf_interrupt_handler(void *param)
2985 {
2986         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2987
2988         eth_igbvf_interrupt_get_status(dev);
2989         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2990 }
2991
2992 static int
2993 eth_igb_led_on(struct rte_eth_dev *dev)
2994 {
2995         struct e1000_hw *hw;
2996
2997         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2999 }
3000
3001 static int
3002 eth_igb_led_off(struct rte_eth_dev *dev)
3003 {
3004         struct e1000_hw *hw;
3005
3006         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3008 }
3009
3010 static int
3011 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3012 {
3013         struct e1000_hw *hw;
3014         uint32_t ctrl;
3015         int tx_pause;
3016         int rx_pause;
3017
3018         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         fc_conf->pause_time = hw->fc.pause_time;
3020         fc_conf->high_water = hw->fc.high_water;
3021         fc_conf->low_water = hw->fc.low_water;
3022         fc_conf->send_xon = hw->fc.send_xon;
3023         fc_conf->autoneg = hw->mac.autoneg;
3024
3025         /*
3026          * Return rx_pause and tx_pause status according to actual setting of
3027          * the TFCE and RFCE bits in the CTRL register.
3028          */
3029         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3030         if (ctrl & E1000_CTRL_TFCE)
3031                 tx_pause = 1;
3032         else
3033                 tx_pause = 0;
3034
3035         if (ctrl & E1000_CTRL_RFCE)
3036                 rx_pause = 1;
3037         else
3038                 rx_pause = 0;
3039
3040         if (rx_pause && tx_pause)
3041                 fc_conf->mode = RTE_FC_FULL;
3042         else if (rx_pause)
3043                 fc_conf->mode = RTE_FC_RX_PAUSE;
3044         else if (tx_pause)
3045                 fc_conf->mode = RTE_FC_TX_PAUSE;
3046         else
3047                 fc_conf->mode = RTE_FC_NONE;
3048
3049         return 0;
3050 }
3051
3052 static int
3053 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3054 {
3055         struct e1000_hw *hw;
3056         int err;
3057         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3058                 e1000_fc_none,
3059                 e1000_fc_rx_pause,
3060                 e1000_fc_tx_pause,
3061                 e1000_fc_full
3062         };
3063         uint32_t rx_buf_size;
3064         uint32_t max_high_water;
3065         uint32_t rctl;
3066
3067         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         if (fc_conf->autoneg != hw->mac.autoneg)
3069                 return -ENOTSUP;
3070         rx_buf_size = igb_get_rx_buffer_size(hw);
3071         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3072
3073         /* At least reserve one Ethernet frame for watermark */
3074         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3075         if ((fc_conf->high_water > max_high_water) ||
3076             (fc_conf->high_water < fc_conf->low_water)) {
3077                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3078                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3079                 return -EINVAL;
3080         }
3081
3082         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3083         hw->fc.pause_time     = fc_conf->pause_time;
3084         hw->fc.high_water     = fc_conf->high_water;
3085         hw->fc.low_water      = fc_conf->low_water;
3086         hw->fc.send_xon       = fc_conf->send_xon;
3087
3088         err = e1000_setup_link_generic(hw);
3089         if (err == E1000_SUCCESS) {
3090
3091                 /* check if we want to forward MAC frames - driver doesn't have native
3092                  * capability to do that, so we'll write the registers ourselves */
3093
3094                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3095
3096                 /* set or clear MFLCN.PMCF bit depending on configuration */
3097                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3098                         rctl |= E1000_RCTL_PMCF;
3099                 else
3100                         rctl &= ~E1000_RCTL_PMCF;
3101
3102                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3103                 E1000_WRITE_FLUSH(hw);
3104
3105                 return 0;
3106         }
3107
3108         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3109         return -EIO;
3110 }
3111
3112 #define E1000_RAH_POOLSEL_SHIFT      (18)
3113 static int
3114 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3115                 uint32_t index, uint32_t pool)
3116 {
3117         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118         uint32_t rah;
3119
3120         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3121         rah = E1000_READ_REG(hw, E1000_RAH(index));
3122         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3123         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3124         return 0;
3125 }
3126
3127 static void
3128 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3129 {
3130         uint8_t addr[ETHER_ADDR_LEN];
3131         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132
3133         memset(addr, 0, sizeof(addr));
3134
3135         e1000_rar_set(hw, addr, index);
3136 }
3137
3138 static void
3139 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3140                                 struct ether_addr *addr)
3141 {
3142         eth_igb_rar_clear(dev, 0);
3143
3144         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3145 }
3146 /*
3147  * Virtual Function operations
3148  */
3149 static void
3150 igbvf_intr_disable(struct e1000_hw *hw)
3151 {
3152         PMD_INIT_FUNC_TRACE();
3153
3154         /* Clear interrupt mask to stop from interrupts being generated */
3155         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3156
3157         E1000_WRITE_FLUSH(hw);
3158 }
3159
3160 static void
3161 igbvf_stop_adapter(struct rte_eth_dev *dev)
3162 {
3163         u32 reg_val;
3164         u16 i;
3165         struct rte_eth_dev_info dev_info;
3166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3167
3168         memset(&dev_info, 0, sizeof(dev_info));
3169         eth_igbvf_infos_get(dev, &dev_info);
3170
3171         /* Clear interrupt mask to stop from interrupts being generated */
3172         igbvf_intr_disable(hw);
3173
3174         /* Clear any pending interrupts, flush previous writes */
3175         E1000_READ_REG(hw, E1000_EICR);
3176
3177         /* Disable the transmit unit.  Each queue must be disabled. */
3178         for (i = 0; i < dev_info.max_tx_queues; i++)
3179                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3180
3181         /* Disable the receive unit by stopping each queue */
3182         for (i = 0; i < dev_info.max_rx_queues; i++) {
3183                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3184                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3185                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3186                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3187                         ;
3188         }
3189
3190         /* flush all queues disables */
3191         E1000_WRITE_FLUSH(hw);
3192         msec_delay(2);
3193 }
3194
3195 static int eth_igbvf_link_update(struct e1000_hw *hw)
3196 {
3197         struct e1000_mbx_info *mbx = &hw->mbx;
3198         struct e1000_mac_info *mac = &hw->mac;
3199         int ret_val = E1000_SUCCESS;
3200
3201         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3202
3203         /*
3204          * We only want to run this if there has been a rst asserted.
3205          * in this case that could mean a link change, device reset,
3206          * or a virtual function reset
3207          */
3208
3209         /* If we were hit with a reset or timeout drop the link */
3210         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3211                 mac->get_link_status = TRUE;
3212
3213         if (!mac->get_link_status)
3214                 goto out;
3215
3216         /* if link status is down no point in checking to see if pf is up */
3217         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3218                 goto out;
3219
3220         /* if we passed all the tests above then the link is up and we no
3221          * longer need to check for link */
3222         mac->get_link_status = FALSE;
3223
3224 out:
3225         return ret_val;
3226 }
3227
3228
3229 static int
3230 igbvf_dev_configure(struct rte_eth_dev *dev)
3231 {
3232         struct rte_eth_conf* conf = &dev->data->dev_conf;
3233
3234         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3235                      dev->data->port_id);
3236
3237         /*
3238          * VF has no ability to enable/disable HW CRC
3239          * Keep the persistent behavior the same as Host PF
3240          */
3241 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3242         if (!conf->rxmode.hw_strip_crc) {
3243                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3244                 conf->rxmode.hw_strip_crc = 1;
3245         }
3246 #else
3247         if (conf->rxmode.hw_strip_crc) {
3248                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3249                 conf->rxmode.hw_strip_crc = 0;
3250         }
3251 #endif
3252
3253         return 0;
3254 }
3255
3256 static int
3257 igbvf_dev_start(struct rte_eth_dev *dev)
3258 {
3259         struct e1000_hw *hw =
3260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261         struct e1000_adapter *adapter =
3262                 E1000_DEV_PRIVATE(dev->data->dev_private);
3263         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3264         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3265         int ret;
3266         uint32_t intr_vector = 0;
3267
3268         PMD_INIT_FUNC_TRACE();
3269
3270         hw->mac.ops.reset_hw(hw);
3271         adapter->stopped = 0;
3272
3273         /* Set all vfta */
3274         igbvf_set_vfta_all(dev,1);
3275
3276         eth_igbvf_tx_init(dev);
3277
3278         /* This can fail when allocating mbufs for descriptor rings */
3279         ret = eth_igbvf_rx_init(dev);
3280         if (ret) {
3281                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3282                 igb_dev_clear_queues(dev);
3283                 return ret;
3284         }
3285
3286         /* check and configure queue intr-vector mapping */
3287         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3288                 intr_vector = dev->data->nb_rx_queues;
3289                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3290                 if (ret)
3291                         return ret;
3292         }
3293
3294         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3295                 intr_handle->intr_vec =
3296                         rte_zmalloc("intr_vec",
3297                                     dev->data->nb_rx_queues * sizeof(int), 0);
3298                 if (!intr_handle->intr_vec) {
3299                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3300                                      " intr_vec", dev->data->nb_rx_queues);
3301                         return -ENOMEM;
3302                 }
3303         }
3304
3305         eth_igbvf_configure_msix_intr(dev);
3306
3307         /* enable uio/vfio intr/eventfd mapping */
3308         rte_intr_enable(intr_handle);
3309
3310         /* resume enabled intr since hw reset */
3311         igbvf_intr_enable(dev);
3312
3313         return 0;
3314 }
3315
3316 static void
3317 igbvf_dev_stop(struct rte_eth_dev *dev)
3318 {
3319         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3320         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3321
3322         PMD_INIT_FUNC_TRACE();
3323
3324         igbvf_stop_adapter(dev);
3325
3326         /*
3327           * Clear what we set, but we still keep shadow_vfta to
3328           * restore after device starts
3329           */
3330         igbvf_set_vfta_all(dev,0);
3331
3332         igb_dev_clear_queues(dev);
3333
3334         /* disable intr eventfd mapping */
3335         rte_intr_disable(intr_handle);
3336
3337         /* Clean datapath event and queue/vec mapping */
3338         rte_intr_efd_disable(intr_handle);
3339         if (intr_handle->intr_vec) {
3340                 rte_free(intr_handle->intr_vec);
3341                 intr_handle->intr_vec = NULL;
3342         }
3343 }
3344
3345 static void
3346 igbvf_dev_close(struct rte_eth_dev *dev)
3347 {
3348         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349         struct e1000_adapter *adapter =
3350                 E1000_DEV_PRIVATE(dev->data->dev_private);
3351         struct ether_addr addr;
3352
3353         PMD_INIT_FUNC_TRACE();
3354
3355         e1000_reset_hw(hw);
3356
3357         igbvf_dev_stop(dev);
3358         adapter->stopped = 1;
3359         igb_dev_free_queues(dev);
3360
3361         /**
3362          * reprogram the RAR with a zero mac address,
3363          * to ensure that the VF traffic goes to the PF
3364          * after stop, close and detach of the VF.
3365          **/
3366
3367         memset(&addr, 0, sizeof(addr));
3368         igbvf_default_mac_addr_set(dev, &addr);
3369 }
3370
3371 static void
3372 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3373 {
3374         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375
3376         /* Set both unicast and multicast promisc */
3377         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3378 }
3379
3380 static void
3381 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3382 {
3383         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3384
3385         /* If in allmulticast mode leave multicast promisc */
3386         if (dev->data->all_multicast == 1)
3387                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3388         else
3389                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3390 }
3391
3392 static void
3393 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3394 {
3395         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396
3397         /* In promiscuous mode multicast promisc already set */
3398         if (dev->data->promiscuous == 0)
3399                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3400 }
3401
3402 static void
3403 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3404 {
3405         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406
3407         /* In promiscuous mode leave multicast promisc enabled */
3408         if (dev->data->promiscuous == 0)
3409                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3410 }
3411
3412 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3413 {
3414         struct e1000_mbx_info *mbx = &hw->mbx;
3415         uint32_t msgbuf[2];
3416         s32 err;
3417
3418         /* After set vlan, vlan strip will also be enabled in igb driver*/
3419         msgbuf[0] = E1000_VF_SET_VLAN;
3420         msgbuf[1] = vid;
3421         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3422         if (on)
3423                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3424
3425         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3426         if (err)
3427                 goto mbx_err;
3428
3429         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3430         if (err)
3431                 goto mbx_err;
3432
3433         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3434         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3435                 err = -EINVAL;
3436
3437 mbx_err:
3438         return err;
3439 }
3440
3441 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3442 {
3443         struct e1000_hw *hw =
3444                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct e1000_vfta * shadow_vfta =
3446                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3447         int i = 0, j = 0, vfta = 0, mask = 1;
3448
3449         for (i = 0; i < IGB_VFTA_SIZE; i++){
3450                 vfta = shadow_vfta->vfta[i];
3451                 if(vfta){
3452                         mask = 1;
3453                         for (j = 0; j < 32; j++){
3454                                 if(vfta & mask)
3455                                         igbvf_set_vfta(hw,
3456                                                 (uint16_t)((i<<5)+j), on);
3457                                 mask<<=1;
3458                         }
3459                 }
3460         }
3461
3462 }
3463
3464 static int
3465 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3466 {
3467         struct e1000_hw *hw =
3468                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3469         struct e1000_vfta * shadow_vfta =
3470                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3471         uint32_t vid_idx = 0;
3472         uint32_t vid_bit = 0;
3473         int ret = 0;
3474
3475         PMD_INIT_FUNC_TRACE();
3476
3477         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3478         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3479         if(ret){
3480                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3481                 return ret;
3482         }
3483         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3484         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3485
3486         /*Save what we set and retore it after device reset*/
3487         if (on)
3488                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3489         else
3490                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3491
3492         return 0;
3493 }
3494
3495 static void
3496 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3497 {
3498         struct e1000_hw *hw =
3499                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3500
3501         /* index is not used by rar_set() */
3502         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3503 }
3504
3505
3506 static int
3507 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3508                         struct rte_eth_rss_reta_entry64 *reta_conf,
3509                         uint16_t reta_size)
3510 {
3511         uint8_t i, j, mask;
3512         uint32_t reta, r;
3513         uint16_t idx, shift;
3514         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515
3516         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3517                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3518                         "(%d) doesn't match the number hardware can supported "
3519                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3520                 return -EINVAL;
3521         }
3522
3523         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3524                 idx = i / RTE_RETA_GROUP_SIZE;
3525                 shift = i % RTE_RETA_GROUP_SIZE;
3526                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3527                                                 IGB_4_BIT_MASK);
3528                 if (!mask)
3529                         continue;
3530                 if (mask == IGB_4_BIT_MASK)
3531                         r = 0;
3532                 else
3533                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3534                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3535                         if (mask & (0x1 << j))
3536                                 reta |= reta_conf[idx].reta[shift + j] <<
3537                                                         (CHAR_BIT * j);
3538                         else
3539                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3540                 }
3541                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3542         }
3543
3544         return 0;
3545 }
3546
3547 static int
3548 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3549                        struct rte_eth_rss_reta_entry64 *reta_conf,
3550                        uint16_t reta_size)
3551 {
3552         uint8_t i, j, mask;
3553         uint32_t reta;
3554         uint16_t idx, shift;
3555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3556
3557         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3558                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3559                         "(%d) doesn't match the number hardware can supported "
3560                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3561                 return -EINVAL;
3562         }
3563
3564         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3565                 idx = i / RTE_RETA_GROUP_SIZE;
3566                 shift = i % RTE_RETA_GROUP_SIZE;
3567                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3568                                                 IGB_4_BIT_MASK);
3569                 if (!mask)
3570                         continue;
3571                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3572                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3573                         if (mask & (0x1 << j))
3574                                 reta_conf[idx].reta[shift + j] =
3575                                         ((reta >> (CHAR_BIT * j)) &
3576                                                 IGB_8_BIT_MASK);
3577                 }
3578         }
3579
3580         return 0;
3581 }
3582
3583 static int
3584 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3585                         struct rte_eth_syn_filter *filter,
3586                         bool add)
3587 {
3588         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         struct e1000_filter_info *filter_info =
3590                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3591         uint32_t synqf, rfctl;
3592
3593         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3594                 return -EINVAL;
3595
3596         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3597
3598         if (add) {
3599                 if (synqf & E1000_SYN_FILTER_ENABLE)
3600                         return -EINVAL;
3601
3602                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3603                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3604
3605                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3606                 if (filter->hig_pri)
3607                         rfctl |= E1000_RFCTL_SYNQFP;
3608                 else
3609                         rfctl &= ~E1000_RFCTL_SYNQFP;
3610
3611                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3612         } else {
3613                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3614                         return -ENOENT;
3615                 synqf = 0;
3616         }
3617
3618         filter_info->syn_info = synqf;
3619         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3620         E1000_WRITE_FLUSH(hw);
3621         return 0;
3622 }
3623
3624 static int
3625 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3626                         struct rte_eth_syn_filter *filter)
3627 {
3628         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3629         uint32_t synqf, rfctl;
3630
3631         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3632         if (synqf & E1000_SYN_FILTER_ENABLE) {
3633                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3634                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3635                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3636                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3637                 return 0;
3638         }
3639
3640         return -ENOENT;
3641 }
3642
3643 static int
3644 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3645                         enum rte_filter_op filter_op,
3646                         void *arg)
3647 {
3648         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3649         int ret;
3650
3651         MAC_TYPE_FILTER_SUP(hw->mac.type);
3652
3653         if (filter_op == RTE_ETH_FILTER_NOP)
3654                 return 0;
3655
3656         if (arg == NULL) {
3657                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3658                             filter_op);
3659                 return -EINVAL;
3660         }
3661
3662         switch (filter_op) {
3663         case RTE_ETH_FILTER_ADD:
3664                 ret = eth_igb_syn_filter_set(dev,
3665                                 (struct rte_eth_syn_filter *)arg,
3666                                 TRUE);
3667                 break;
3668         case RTE_ETH_FILTER_DELETE:
3669                 ret = eth_igb_syn_filter_set(dev,
3670                                 (struct rte_eth_syn_filter *)arg,
3671                                 FALSE);
3672                 break;
3673         case RTE_ETH_FILTER_GET:
3674                 ret = eth_igb_syn_filter_get(dev,
3675                                 (struct rte_eth_syn_filter *)arg);
3676                 break;
3677         default:
3678                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3679                 ret = -EINVAL;
3680                 break;
3681         }
3682
3683         return ret;
3684 }
3685
3686 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3687 static inline int
3688 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3689                         struct e1000_2tuple_filter_info *filter_info)
3690 {
3691         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3692                 return -EINVAL;
3693         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3694                 return -EINVAL;  /* filter index is out of range. */
3695         if (filter->tcp_flags > TCP_FLAG_ALL)
3696                 return -EINVAL;  /* flags is invalid. */
3697
3698         switch (filter->dst_port_mask) {
3699         case UINT16_MAX:
3700                 filter_info->dst_port_mask = 0;
3701                 filter_info->dst_port = filter->dst_port;
3702                 break;
3703         case 0:
3704                 filter_info->dst_port_mask = 1;
3705                 break;
3706         default:
3707                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3708                 return -EINVAL;
3709         }
3710
3711         switch (filter->proto_mask) {
3712         case UINT8_MAX:
3713                 filter_info->proto_mask = 0;
3714                 filter_info->proto = filter->proto;
3715                 break;
3716         case 0:
3717                 filter_info->proto_mask = 1;
3718                 break;
3719         default:
3720                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3721                 return -EINVAL;
3722         }
3723
3724         filter_info->priority = (uint8_t)filter->priority;
3725         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3726                 filter_info->tcp_flags = filter->tcp_flags;
3727         else
3728                 filter_info->tcp_flags = 0;
3729
3730         return 0;
3731 }
3732
3733 static inline struct e1000_2tuple_filter *
3734 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3735                         struct e1000_2tuple_filter_info *key)
3736 {
3737         struct e1000_2tuple_filter *it;
3738
3739         TAILQ_FOREACH(it, filter_list, entries) {
3740                 if (memcmp(key, &it->filter_info,
3741                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3742                         return it;
3743                 }
3744         }
3745         return NULL;
3746 }
3747
3748 /* inject a igb 2tuple filter to HW */
3749 static inline void
3750 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3751                            struct e1000_2tuple_filter *filter)
3752 {
3753         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3755         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3756         int i;
3757
3758         i = filter->index;
3759         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3760         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3761                 imir |= E1000_IMIR_PORT_BP;
3762         else
3763                 imir &= ~E1000_IMIR_PORT_BP;
3764
3765         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3766
3767         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3768         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3769         ttqf |= (uint32_t)(filter->filter_info.proto &
3770                                                 E1000_TTQF_PROTOCOL_MASK);
3771         if (filter->filter_info.proto_mask == 0)
3772                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3773
3774         /* tcp flags bits setting. */
3775         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3776                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3777                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3778                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3779                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3780                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3781                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3782                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3783                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3784                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3785                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3786                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3787                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3788         } else {
3789                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3790         }
3791         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3792         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3793         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3794 }
3795
3796 /*
3797  * igb_add_2tuple_filter - add a 2tuple filter
3798  *
3799  * @param
3800  * dev: Pointer to struct rte_eth_dev.
3801  * ntuple_filter: ponter to the filter that will be added.
3802  *
3803  * @return
3804  *    - On success, zero.
3805  *    - On failure, a negative value.
3806  */
3807 static int
3808 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3809                         struct rte_eth_ntuple_filter *ntuple_filter)
3810 {
3811         struct e1000_filter_info *filter_info =
3812                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3813         struct e1000_2tuple_filter *filter;
3814         int i, ret;
3815
3816         filter = rte_zmalloc("e1000_2tuple_filter",
3817                         sizeof(struct e1000_2tuple_filter), 0);
3818         if (filter == NULL)
3819                 return -ENOMEM;
3820
3821         ret = ntuple_filter_to_2tuple(ntuple_filter,
3822                                       &filter->filter_info);
3823         if (ret < 0) {
3824                 rte_free(filter);
3825                 return ret;
3826         }
3827         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3828                                          &filter->filter_info) != NULL) {
3829                 PMD_DRV_LOG(ERR, "filter exists.");
3830                 rte_free(filter);
3831                 return -EEXIST;
3832         }
3833         filter->queue = ntuple_filter->queue;
3834
3835         /*
3836          * look for an unused 2tuple filter index,
3837          * and insert the filter to list.
3838          */
3839         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3840                 if (!(filter_info->twotuple_mask & (1 << i))) {
3841                         filter_info->twotuple_mask |= 1 << i;
3842                         filter->index = i;
3843                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3844                                           filter,
3845                                           entries);
3846                         break;
3847                 }
3848         }
3849         if (i >= E1000_MAX_TTQF_FILTERS) {
3850                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3851                 rte_free(filter);
3852                 return -ENOSYS;
3853         }
3854
3855         igb_inject_2uple_filter(dev, filter);
3856         return 0;
3857 }
3858
3859 /*
3860  * igb_remove_2tuple_filter - remove a 2tuple filter
3861  *
3862  * @param
3863  * dev: Pointer to struct rte_eth_dev.
3864  * ntuple_filter: ponter to the filter that will be removed.
3865  *
3866  * @return
3867  *    - On success, zero.
3868  *    - On failure, a negative value.
3869  */
3870 static int
3871 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3872                         struct rte_eth_ntuple_filter *ntuple_filter)
3873 {
3874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875         struct e1000_filter_info *filter_info =
3876                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3877         struct e1000_2tuple_filter_info filter_2tuple;
3878         struct e1000_2tuple_filter *filter;
3879         int ret;
3880
3881         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3882         ret = ntuple_filter_to_2tuple(ntuple_filter,
3883                                       &filter_2tuple);
3884         if (ret < 0)
3885                 return ret;
3886
3887         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3888                                          &filter_2tuple);
3889         if (filter == NULL) {
3890                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3891                 return -ENOENT;
3892         }
3893
3894         filter_info->twotuple_mask &= ~(1 << filter->index);
3895         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3896         rte_free(filter);
3897
3898         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3899         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3900         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3901         return 0;
3902 }
3903
3904 /* inject a igb flex filter to HW */
3905 static inline void
3906 igb_inject_flex_filter(struct rte_eth_dev *dev,
3907                            struct e1000_flex_filter *filter)
3908 {
3909         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910         uint32_t wufc, queueing;
3911         uint32_t reg_off;
3912         uint8_t i, j = 0;
3913
3914         wufc = E1000_READ_REG(hw, E1000_WUFC);
3915         if (filter->index < E1000_MAX_FHFT)
3916                 reg_off = E1000_FHFT(filter->index);
3917         else
3918                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3919
3920         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3921                         (E1000_WUFC_FLX0 << filter->index));
3922         queueing = filter->filter_info.len |
3923                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3924                 (filter->filter_info.priority <<
3925                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3926         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3927                         queueing);
3928
3929         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3930                 E1000_WRITE_REG(hw, reg_off,
3931                                 filter->filter_info.dwords[j]);
3932                 reg_off += sizeof(uint32_t);
3933                 E1000_WRITE_REG(hw, reg_off,
3934                                 filter->filter_info.dwords[++j]);
3935                 reg_off += sizeof(uint32_t);
3936                 E1000_WRITE_REG(hw, reg_off,
3937                         (uint32_t)filter->filter_info.mask[i]);
3938                 reg_off += sizeof(uint32_t) * 2;
3939                 ++j;
3940         }
3941 }
3942
3943 static inline struct e1000_flex_filter *
3944 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3945                         struct e1000_flex_filter_info *key)
3946 {
3947         struct e1000_flex_filter *it;
3948
3949         TAILQ_FOREACH(it, filter_list, entries) {
3950                 if (memcmp(key, &it->filter_info,
3951                         sizeof(struct e1000_flex_filter_info)) == 0)
3952                         return it;
3953         }
3954
3955         return NULL;
3956 }
3957
3958 /* remove a flex byte filter
3959  * @param
3960  * dev: Pointer to struct rte_eth_dev.
3961  * filter: the pointer of the filter will be removed.
3962  */
3963 static void
3964 igb_remove_flex_filter(struct rte_eth_dev *dev,
3965                         struct e1000_flex_filter *filter)
3966 {
3967         struct e1000_filter_info *filter_info =
3968                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3969         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970         uint32_t wufc, i;
3971         uint32_t reg_off;
3972
3973         wufc = E1000_READ_REG(hw, E1000_WUFC);
3974         if (filter->index < E1000_MAX_FHFT)
3975                 reg_off = E1000_FHFT(filter->index);
3976         else
3977                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3978
3979         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3980                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3981
3982         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3983                 (~(E1000_WUFC_FLX0 << filter->index)));
3984
3985         filter_info->flex_mask &= ~(1 << filter->index);
3986         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3987         rte_free(filter);
3988 }
3989
3990 int
3991 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3992                         struct rte_eth_flex_filter *filter,
3993                         bool add)
3994 {
3995         struct e1000_filter_info *filter_info =
3996                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3997         struct e1000_flex_filter *flex_filter, *it;
3998         uint32_t mask;
3999         uint8_t shift, i;
4000
4001         flex_filter = rte_zmalloc("e1000_flex_filter",
4002                         sizeof(struct e1000_flex_filter), 0);
4003         if (flex_filter == NULL)
4004                 return -ENOMEM;
4005
4006         flex_filter->filter_info.len = filter->len;
4007         flex_filter->filter_info.priority = filter->priority;
4008         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4009         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4010                 mask = 0;
4011                 /* reverse bits in flex filter's mask*/
4012                 for (shift = 0; shift < CHAR_BIT; shift++) {
4013                         if (filter->mask[i] & (0x01 << shift))
4014                                 mask |= (0x80 >> shift);
4015                 }
4016                 flex_filter->filter_info.mask[i] = mask;
4017         }
4018
4019         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4020                                 &flex_filter->filter_info);
4021         if (it == NULL && !add) {
4022                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4023                 rte_free(flex_filter);
4024                 return -ENOENT;
4025         }
4026         if (it != NULL && add) {
4027                 PMD_DRV_LOG(ERR, "filter exists.");
4028                 rte_free(flex_filter);
4029                 return -EEXIST;
4030         }
4031
4032         if (add) {
4033                 flex_filter->queue = filter->queue;
4034                 /*
4035                  * look for an unused flex filter index
4036                  * and insert the filter into the list.
4037                  */
4038                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4039                         if (!(filter_info->flex_mask & (1 << i))) {
4040                                 filter_info->flex_mask |= 1 << i;
4041                                 flex_filter->index = i;
4042                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4043                                         flex_filter,
4044                                         entries);
4045                                 break;
4046                         }
4047                 }
4048                 if (i >= E1000_MAX_FLEX_FILTERS) {
4049                         PMD_DRV_LOG(ERR, "flex filters are full.");
4050                         rte_free(flex_filter);
4051                         return -ENOSYS;
4052                 }
4053
4054                 igb_inject_flex_filter(dev, flex_filter);
4055
4056         } else {
4057                 igb_remove_flex_filter(dev, it);
4058                 rte_free(flex_filter);
4059         }
4060
4061         return 0;
4062 }
4063
4064 static int
4065 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4066                         struct rte_eth_flex_filter *filter)
4067 {
4068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4069         struct e1000_filter_info *filter_info =
4070                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4071         struct e1000_flex_filter flex_filter, *it;
4072         uint32_t wufc, queueing, wufc_en = 0;
4073
4074         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4075         flex_filter.filter_info.len = filter->len;
4076         flex_filter.filter_info.priority = filter->priority;
4077         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4078         memcpy(flex_filter.filter_info.mask, filter->mask,
4079                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4080
4081         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4082                                 &flex_filter.filter_info);
4083         if (it == NULL) {
4084                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4085                 return -ENOENT;
4086         }
4087
4088         wufc = E1000_READ_REG(hw, E1000_WUFC);
4089         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4090
4091         if ((wufc & wufc_en) == wufc_en) {
4092                 uint32_t reg_off = 0;
4093                 if (it->index < E1000_MAX_FHFT)
4094                         reg_off = E1000_FHFT(it->index);
4095                 else
4096                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4097
4098                 queueing = E1000_READ_REG(hw,
4099                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4100                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4101                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4102                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4103                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4104                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4105                 return 0;
4106         }
4107         return -ENOENT;
4108 }
4109
4110 static int
4111 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4112                         enum rte_filter_op filter_op,
4113                         void *arg)
4114 {
4115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4116         struct rte_eth_flex_filter *filter;
4117         int ret = 0;
4118
4119         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4120
4121         if (filter_op == RTE_ETH_FILTER_NOP)
4122                 return ret;
4123
4124         if (arg == NULL) {
4125                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4126                             filter_op);
4127                 return -EINVAL;
4128         }
4129
4130         filter = (struct rte_eth_flex_filter *)arg;
4131         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4132             || filter->len % sizeof(uint64_t) != 0) {
4133                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4134                 return -EINVAL;
4135         }
4136         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4137                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4138                 return -EINVAL;
4139         }
4140
4141         switch (filter_op) {
4142         case RTE_ETH_FILTER_ADD:
4143                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4144                 break;
4145         case RTE_ETH_FILTER_DELETE:
4146                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4147                 break;
4148         case RTE_ETH_FILTER_GET:
4149                 ret = eth_igb_get_flex_filter(dev, filter);
4150                 break;
4151         default:
4152                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4153                 ret = -EINVAL;
4154                 break;
4155         }
4156
4157         return ret;
4158 }
4159
4160 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4161 static inline int
4162 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4163                         struct e1000_5tuple_filter_info *filter_info)
4164 {
4165         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4166                 return -EINVAL;
4167         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4168                 return -EINVAL;  /* filter index is out of range. */
4169         if (filter->tcp_flags > TCP_FLAG_ALL)
4170                 return -EINVAL;  /* flags is invalid. */
4171
4172         switch (filter->dst_ip_mask) {
4173         case UINT32_MAX:
4174                 filter_info->dst_ip_mask = 0;
4175                 filter_info->dst_ip = filter->dst_ip;
4176                 break;
4177         case 0:
4178                 filter_info->dst_ip_mask = 1;
4179                 break;
4180         default:
4181                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4182                 return -EINVAL;
4183         }
4184
4185         switch (filter->src_ip_mask) {
4186         case UINT32_MAX:
4187                 filter_info->src_ip_mask = 0;
4188                 filter_info->src_ip = filter->src_ip;
4189                 break;
4190         case 0:
4191                 filter_info->src_ip_mask = 1;
4192                 break;
4193         default:
4194                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4195                 return -EINVAL;
4196         }
4197
4198         switch (filter->dst_port_mask) {
4199         case UINT16_MAX:
4200                 filter_info->dst_port_mask = 0;
4201                 filter_info->dst_port = filter->dst_port;
4202                 break;
4203         case 0:
4204                 filter_info->dst_port_mask = 1;
4205                 break;
4206         default:
4207                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4208                 return -EINVAL;
4209         }
4210
4211         switch (filter->src_port_mask) {
4212         case UINT16_MAX:
4213                 filter_info->src_port_mask = 0;
4214                 filter_info->src_port = filter->src_port;
4215                 break;
4216         case 0:
4217                 filter_info->src_port_mask = 1;
4218                 break;
4219         default:
4220                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4221                 return -EINVAL;
4222         }
4223
4224         switch (filter->proto_mask) {
4225         case UINT8_MAX:
4226                 filter_info->proto_mask = 0;
4227                 filter_info->proto = filter->proto;
4228                 break;
4229         case 0:
4230                 filter_info->proto_mask = 1;
4231                 break;
4232         default:
4233                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4234                 return -EINVAL;
4235         }
4236
4237         filter_info->priority = (uint8_t)filter->priority;
4238         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4239                 filter_info->tcp_flags = filter->tcp_flags;
4240         else
4241                 filter_info->tcp_flags = 0;
4242
4243         return 0;
4244 }
4245
4246 static inline struct e1000_5tuple_filter *
4247 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4248                         struct e1000_5tuple_filter_info *key)
4249 {
4250         struct e1000_5tuple_filter *it;
4251
4252         TAILQ_FOREACH(it, filter_list, entries) {
4253                 if (memcmp(key, &it->filter_info,
4254                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4255                         return it;
4256                 }
4257         }
4258         return NULL;
4259 }
4260
4261 /* inject a igb 5-tuple filter to HW */
4262 static inline void
4263 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4264                            struct e1000_5tuple_filter *filter)
4265 {
4266         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4267         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4268         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4269         uint8_t i;
4270
4271         i = filter->index;
4272         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4273         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4274                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4275         if (filter->filter_info.dst_ip_mask == 0)
4276                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4277         if (filter->filter_info.src_port_mask == 0)
4278                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4279         if (filter->filter_info.proto_mask == 0)
4280                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4281         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4282                 E1000_FTQF_QUEUE_MASK;
4283         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4284         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4285         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4286         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4287
4288         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4289         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4290
4291         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4292         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4293                 imir |= E1000_IMIR_PORT_BP;
4294         else
4295                 imir &= ~E1000_IMIR_PORT_BP;
4296         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4297
4298         /* tcp flags bits setting. */
4299         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4300                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4301                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4302                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4303                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4304                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4305                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4306                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4307                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4308                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4309                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4310                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4311                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4312         } else {
4313                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4314         }
4315         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4316         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4317 }
4318
4319 /*
4320  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4321  *
4322  * @param
4323  * dev: Pointer to struct rte_eth_dev.
4324  * ntuple_filter: ponter to the filter that will be added.
4325  *
4326  * @return
4327  *    - On success, zero.
4328  *    - On failure, a negative value.
4329  */
4330 static int
4331 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4332                         struct rte_eth_ntuple_filter *ntuple_filter)
4333 {
4334         struct e1000_filter_info *filter_info =
4335                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4336         struct e1000_5tuple_filter *filter;
4337         uint8_t i;
4338         int ret;
4339
4340         filter = rte_zmalloc("e1000_5tuple_filter",
4341                         sizeof(struct e1000_5tuple_filter), 0);
4342         if (filter == NULL)
4343                 return -ENOMEM;
4344
4345         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4346                                             &filter->filter_info);
4347         if (ret < 0) {
4348                 rte_free(filter);
4349                 return ret;
4350         }
4351
4352         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4353                                          &filter->filter_info) != NULL) {
4354                 PMD_DRV_LOG(ERR, "filter exists.");
4355                 rte_free(filter);
4356                 return -EEXIST;
4357         }
4358         filter->queue = ntuple_filter->queue;
4359
4360         /*
4361          * look for an unused 5tuple filter index,
4362          * and insert the filter to list.
4363          */
4364         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4365                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4366                         filter_info->fivetuple_mask |= 1 << i;
4367                         filter->index = i;
4368                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4369                                           filter,
4370                                           entries);
4371                         break;
4372                 }
4373         }
4374         if (i >= E1000_MAX_FTQF_FILTERS) {
4375                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4376                 rte_free(filter);
4377                 return -ENOSYS;
4378         }
4379
4380         igb_inject_5tuple_filter_82576(dev, filter);
4381         return 0;
4382 }
4383
4384 /*
4385  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4386  *
4387  * @param
4388  * dev: Pointer to struct rte_eth_dev.
4389  * ntuple_filter: ponter to the filter that will be removed.
4390  *
4391  * @return
4392  *    - On success, zero.
4393  *    - On failure, a negative value.
4394  */
4395 static int
4396 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4397                                 struct rte_eth_ntuple_filter *ntuple_filter)
4398 {
4399         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         struct e1000_filter_info *filter_info =
4401                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4402         struct e1000_5tuple_filter_info filter_5tuple;
4403         struct e1000_5tuple_filter *filter;
4404         int ret;
4405
4406         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4407         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4408                                             &filter_5tuple);
4409         if (ret < 0)
4410                 return ret;
4411
4412         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4413                                          &filter_5tuple);
4414         if (filter == NULL) {
4415                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4416                 return -ENOENT;
4417         }
4418
4419         filter_info->fivetuple_mask &= ~(1 << filter->index);
4420         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4421         rte_free(filter);
4422
4423         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4424                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4425         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4426         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4427         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4428         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4429         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4430         return 0;
4431 }
4432
4433 static int
4434 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4435 {
4436         uint32_t rctl;
4437         struct e1000_hw *hw;
4438         struct rte_eth_dev_info dev_info;
4439         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4440                                      VLAN_TAG_SIZE);
4441
4442         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443
4444 #ifdef RTE_LIBRTE_82571_SUPPORT
4445         /* XXX: not bigger than max_rx_pktlen */
4446         if (hw->mac.type == e1000_82571)
4447                 return -ENOTSUP;
4448 #endif
4449         eth_igb_infos_get(dev, &dev_info);
4450
4451         /* check that mtu is within the allowed range */
4452         if ((mtu < ETHER_MIN_MTU) ||
4453             (frame_size > dev_info.max_rx_pktlen))
4454                 return -EINVAL;
4455
4456         /* refuse mtu that requires the support of scattered packets when this
4457          * feature has not been enabled before. */
4458         if (!dev->data->scattered_rx &&
4459             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4460                 return -EINVAL;
4461
4462         rctl = E1000_READ_REG(hw, E1000_RCTL);
4463
4464         /* switch to jumbo mode if needed */
4465         if (frame_size > ETHER_MAX_LEN) {
4466                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4467                 rctl |= E1000_RCTL_LPE;
4468         } else {
4469                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4470                 rctl &= ~E1000_RCTL_LPE;
4471         }
4472         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4473
4474         /* update max frame size */
4475         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4476
4477         E1000_WRITE_REG(hw, E1000_RLPML,
4478                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4479
4480         return 0;
4481 }
4482
4483 /*
4484  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4485  *
4486  * @param
4487  * dev: Pointer to struct rte_eth_dev.
4488  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4489  * add: if true, add filter, if false, remove filter
4490  *
4491  * @return
4492  *    - On success, zero.
4493  *    - On failure, a negative value.
4494  */
4495 static int
4496 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4497                         struct rte_eth_ntuple_filter *ntuple_filter,
4498                         bool add)
4499 {
4500         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4501         int ret;
4502
4503         switch (ntuple_filter->flags) {
4504         case RTE_5TUPLE_FLAGS:
4505         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4506                 if (hw->mac.type != e1000_82576)
4507                         return -ENOTSUP;
4508                 if (add)
4509                         ret = igb_add_5tuple_filter_82576(dev,
4510                                                           ntuple_filter);
4511                 else
4512                         ret = igb_remove_5tuple_filter_82576(dev,
4513                                                              ntuple_filter);
4514                 break;
4515         case RTE_2TUPLE_FLAGS:
4516         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4517                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4518                         hw->mac.type != e1000_i210 &&
4519                         hw->mac.type != e1000_i211)
4520                         return -ENOTSUP;
4521                 if (add)
4522                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4523                 else
4524                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4525                 break;
4526         default:
4527                 ret = -EINVAL;
4528                 break;
4529         }
4530
4531         return ret;
4532 }
4533
4534 /*
4535  * igb_get_ntuple_filter - get a ntuple filter
4536  *
4537  * @param
4538  * dev: Pointer to struct rte_eth_dev.
4539  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4540  *
4541  * @return
4542  *    - On success, zero.
4543  *    - On failure, a negative value.
4544  */
4545 static int
4546 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4547                         struct rte_eth_ntuple_filter *ntuple_filter)
4548 {
4549         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4550         struct e1000_filter_info *filter_info =
4551                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4552         struct e1000_5tuple_filter_info filter_5tuple;
4553         struct e1000_2tuple_filter_info filter_2tuple;
4554         struct e1000_5tuple_filter *p_5tuple_filter;
4555         struct e1000_2tuple_filter *p_2tuple_filter;
4556         int ret;
4557
4558         switch (ntuple_filter->flags) {
4559         case RTE_5TUPLE_FLAGS:
4560         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4561                 if (hw->mac.type != e1000_82576)
4562                         return -ENOTSUP;
4563                 memset(&filter_5tuple,
4564                         0,
4565                         sizeof(struct e1000_5tuple_filter_info));
4566                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4567                                                     &filter_5tuple);
4568                 if (ret < 0)
4569                         return ret;
4570                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4571                                         &filter_info->fivetuple_list,
4572                                         &filter_5tuple);
4573                 if (p_5tuple_filter == NULL) {
4574                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4575                         return -ENOENT;
4576                 }
4577                 ntuple_filter->queue = p_5tuple_filter->queue;
4578                 break;
4579         case RTE_2TUPLE_FLAGS:
4580         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4581                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4582                         return -ENOTSUP;
4583                 memset(&filter_2tuple,
4584                         0,
4585                         sizeof(struct e1000_2tuple_filter_info));
4586                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4587                 if (ret < 0)
4588                         return ret;
4589                 p_2tuple_filter = igb_2tuple_filter_lookup(
4590                                         &filter_info->twotuple_list,
4591                                         &filter_2tuple);
4592                 if (p_2tuple_filter == NULL) {
4593                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4594                         return -ENOENT;
4595                 }
4596                 ntuple_filter->queue = p_2tuple_filter->queue;
4597                 break;
4598         default:
4599                 ret = -EINVAL;
4600                 break;
4601         }
4602
4603         return 0;
4604 }
4605
4606 /*
4607  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4608  * @dev: pointer to rte_eth_dev structure
4609  * @filter_op:operation will be taken.
4610  * @arg: a pointer to specific structure corresponding to the filter_op
4611  */
4612 static int
4613 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4614                                 enum rte_filter_op filter_op,
4615                                 void *arg)
4616 {
4617         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         int ret;
4619
4620         MAC_TYPE_FILTER_SUP(hw->mac.type);
4621
4622         if (filter_op == RTE_ETH_FILTER_NOP)
4623                 return 0;
4624
4625         if (arg == NULL) {
4626                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4627                             filter_op);
4628                 return -EINVAL;
4629         }
4630
4631         switch (filter_op) {
4632         case RTE_ETH_FILTER_ADD:
4633                 ret = igb_add_del_ntuple_filter(dev,
4634                         (struct rte_eth_ntuple_filter *)arg,
4635                         TRUE);
4636                 break;
4637         case RTE_ETH_FILTER_DELETE:
4638                 ret = igb_add_del_ntuple_filter(dev,
4639                         (struct rte_eth_ntuple_filter *)arg,
4640                         FALSE);
4641                 break;
4642         case RTE_ETH_FILTER_GET:
4643                 ret = igb_get_ntuple_filter(dev,
4644                         (struct rte_eth_ntuple_filter *)arg);
4645                 break;
4646         default:
4647                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4648                 ret = -EINVAL;
4649                 break;
4650         }
4651         return ret;
4652 }
4653
4654 static inline int
4655 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4656                         uint16_t ethertype)
4657 {
4658         int i;
4659
4660         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4661                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4662                     (filter_info->ethertype_mask & (1 << i)))
4663                         return i;
4664         }
4665         return -1;
4666 }
4667
4668 static inline int
4669 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4670                         uint16_t ethertype, uint32_t etqf)
4671 {
4672         int i;
4673
4674         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4675                 if (!(filter_info->ethertype_mask & (1 << i))) {
4676                         filter_info->ethertype_mask |= 1 << i;
4677                         filter_info->ethertype_filters[i].ethertype = ethertype;
4678                         filter_info->ethertype_filters[i].etqf = etqf;
4679                         return i;
4680                 }
4681         }
4682         return -1;
4683 }
4684
4685 static int
4686 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4687                         uint8_t idx)
4688 {
4689         if (idx >= E1000_MAX_ETQF_FILTERS)
4690                 return -1;
4691         filter_info->ethertype_mask &= ~(1 << idx);
4692         filter_info->ethertype_filters[idx].ethertype = 0;
4693         filter_info->ethertype_filters[idx].etqf = 0;
4694         return idx;
4695 }
4696
4697
4698 int
4699 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4700                         struct rte_eth_ethertype_filter *filter,
4701                         bool add)
4702 {
4703         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         struct e1000_filter_info *filter_info =
4705                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4706         uint32_t etqf = 0;
4707         int ret;
4708
4709         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4710                 filter->ether_type == ETHER_TYPE_IPv6) {
4711                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4712                         " ethertype filter.", filter->ether_type);
4713                 return -EINVAL;
4714         }
4715
4716         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4717                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4718                 return -EINVAL;
4719         }
4720         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4721                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4722                 return -EINVAL;
4723         }
4724
4725         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4726         if (ret >= 0 && add) {
4727                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4728                             filter->ether_type);
4729                 return -EEXIST;
4730         }
4731         if (ret < 0 && !add) {
4732                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4733                             filter->ether_type);
4734                 return -ENOENT;
4735         }
4736
4737         if (add) {
4738                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4739                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4740                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4741                 ret = igb_ethertype_filter_insert(filter_info,
4742                                 filter->ether_type, etqf);
4743                 if (ret < 0) {
4744                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4745                         return -ENOSYS;
4746                 }
4747         } else {
4748                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4749                 if (ret < 0)
4750                         return -ENOSYS;
4751         }
4752         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4753         E1000_WRITE_FLUSH(hw);
4754
4755         return 0;
4756 }
4757
4758 static int
4759 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4760                         struct rte_eth_ethertype_filter *filter)
4761 {
4762         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4763         struct e1000_filter_info *filter_info =
4764                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4765         uint32_t etqf;
4766         int ret;
4767
4768         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4769         if (ret < 0) {
4770                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4771                             filter->ether_type);
4772                 return -ENOENT;
4773         }
4774
4775         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4776         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4777                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4778                 filter->flags = 0;
4779                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4780                                 E1000_ETQF_QUEUE_SHIFT;
4781                 return 0;
4782         }
4783
4784         return -ENOENT;
4785 }
4786
4787 /*
4788  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4789  * @dev: pointer to rte_eth_dev structure
4790  * @filter_op:operation will be taken.
4791  * @arg: a pointer to specific structure corresponding to the filter_op
4792  */
4793 static int
4794 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4795                                 enum rte_filter_op filter_op,
4796                                 void *arg)
4797 {
4798         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799         int ret;
4800
4801         MAC_TYPE_FILTER_SUP(hw->mac.type);
4802
4803         if (filter_op == RTE_ETH_FILTER_NOP)
4804                 return 0;
4805
4806         if (arg == NULL) {
4807                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4808                             filter_op);
4809                 return -EINVAL;
4810         }
4811
4812         switch (filter_op) {
4813         case RTE_ETH_FILTER_ADD:
4814                 ret = igb_add_del_ethertype_filter(dev,
4815                         (struct rte_eth_ethertype_filter *)arg,
4816                         TRUE);
4817                 break;
4818         case RTE_ETH_FILTER_DELETE:
4819                 ret = igb_add_del_ethertype_filter(dev,
4820                         (struct rte_eth_ethertype_filter *)arg,
4821                         FALSE);
4822                 break;
4823         case RTE_ETH_FILTER_GET:
4824                 ret = igb_get_ethertype_filter(dev,
4825                         (struct rte_eth_ethertype_filter *)arg);
4826                 break;
4827         default:
4828                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4829                 ret = -EINVAL;
4830                 break;
4831         }
4832         return ret;
4833 }
4834
4835 static int
4836 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4837                      enum rte_filter_type filter_type,
4838                      enum rte_filter_op filter_op,
4839                      void *arg)
4840 {
4841         int ret = 0;
4842
4843         switch (filter_type) {
4844         case RTE_ETH_FILTER_NTUPLE:
4845                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4846                 break;
4847         case RTE_ETH_FILTER_ETHERTYPE:
4848                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4849                 break;
4850         case RTE_ETH_FILTER_SYN:
4851                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4852                 break;
4853         case RTE_ETH_FILTER_FLEXIBLE:
4854                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4855                 break;
4856         case RTE_ETH_FILTER_GENERIC:
4857                 if (filter_op != RTE_ETH_FILTER_GET)
4858                         return -EINVAL;
4859                 *(const void **)arg = &igb_flow_ops;
4860                 break;
4861         default:
4862                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4863                                                         filter_type);
4864                 break;
4865         }
4866
4867         return ret;
4868 }
4869
4870 static int
4871 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4872                          struct ether_addr *mc_addr_set,
4873                          uint32_t nb_mc_addr)
4874 {
4875         struct e1000_hw *hw;
4876
4877         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4878         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4879         return 0;
4880 }
4881
4882 static uint64_t
4883 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4884 {
4885         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         uint64_t systime_cycles;
4887
4888         switch (hw->mac.type) {
4889         case e1000_i210:
4890         case e1000_i211:
4891                 /*
4892                  * Need to read System Time Residue Register to be able
4893                  * to read the other two registers.
4894                  */
4895                 E1000_READ_REG(hw, E1000_SYSTIMR);
4896                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4897                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4898                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4899                                 * NSEC_PER_SEC;
4900                 break;
4901         case e1000_82580:
4902         case e1000_i350:
4903         case e1000_i354:
4904                 /*
4905                  * Need to read System Time Residue Register to be able
4906                  * to read the other two registers.
4907                  */
4908                 E1000_READ_REG(hw, E1000_SYSTIMR);
4909                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4910                 /* Only the 8 LSB are valid. */
4911                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4912                                 & 0xff) << 32;
4913                 break;
4914         default:
4915                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4916                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4917                                 << 32;
4918                 break;
4919         }
4920
4921         return systime_cycles;
4922 }
4923
4924 static uint64_t
4925 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4926 {
4927         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4928         uint64_t rx_tstamp_cycles;
4929
4930         switch (hw->mac.type) {
4931         case e1000_i210:
4932         case e1000_i211:
4933                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4934                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4935                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4936                                 * NSEC_PER_SEC;
4937                 break;
4938         case e1000_82580:
4939         case e1000_i350:
4940         case e1000_i354:
4941                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4942                 /* Only the 8 LSB are valid. */
4943                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4944                                 & 0xff) << 32;
4945                 break;
4946         default:
4947                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4948                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4949                                 << 32;
4950                 break;
4951         }
4952
4953         return rx_tstamp_cycles;
4954 }
4955
4956 static uint64_t
4957 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4958 {
4959         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960         uint64_t tx_tstamp_cycles;
4961
4962         switch (hw->mac.type) {
4963         case e1000_i210:
4964         case e1000_i211:
4965                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4966                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4967                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4968                                 * NSEC_PER_SEC;
4969                 break;
4970         case e1000_82580:
4971         case e1000_i350:
4972         case e1000_i354:
4973                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4974                 /* Only the 8 LSB are valid. */
4975                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4976                                 & 0xff) << 32;
4977                 break;
4978         default:
4979                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4980                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4981                                 << 32;
4982                 break;
4983         }
4984
4985         return tx_tstamp_cycles;
4986 }
4987
4988 static void
4989 igb_start_timecounters(struct rte_eth_dev *dev)
4990 {
4991         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992         struct e1000_adapter *adapter =
4993                 (struct e1000_adapter *)dev->data->dev_private;
4994         uint32_t incval = 1;
4995         uint32_t shift = 0;
4996         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4997
4998         switch (hw->mac.type) {
4999         case e1000_82580:
5000         case e1000_i350:
5001         case e1000_i354:
5002                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5003                 mask = (1ULL << 40) - 1;
5004                 /* fall-through */
5005         case e1000_i210:
5006         case e1000_i211:
5007                 /*
5008                  * Start incrementing the register
5009                  * used to timestamp PTP packets.
5010                  */
5011                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5012                 break;
5013         case e1000_82576:
5014                 incval = E1000_INCVALUE_82576;
5015                 shift = IGB_82576_TSYNC_SHIFT;
5016                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5017                                 E1000_INCPERIOD_82576 | incval);
5018                 break;
5019         default:
5020                 /* Not supported */
5021                 return;
5022         }
5023
5024         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5025         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5026         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5027
5028         adapter->systime_tc.cc_mask = mask;
5029         adapter->systime_tc.cc_shift = shift;
5030         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5031
5032         adapter->rx_tstamp_tc.cc_mask = mask;
5033         adapter->rx_tstamp_tc.cc_shift = shift;
5034         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5035
5036         adapter->tx_tstamp_tc.cc_mask = mask;
5037         adapter->tx_tstamp_tc.cc_shift = shift;
5038         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5039 }
5040
5041 static int
5042 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5043 {
5044         struct e1000_adapter *adapter =
5045                         (struct e1000_adapter *)dev->data->dev_private;
5046
5047         adapter->systime_tc.nsec += delta;
5048         adapter->rx_tstamp_tc.nsec += delta;
5049         adapter->tx_tstamp_tc.nsec += delta;
5050
5051         return 0;
5052 }
5053
5054 static int
5055 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5056 {
5057         uint64_t ns;
5058         struct e1000_adapter *adapter =
5059                         (struct e1000_adapter *)dev->data->dev_private;
5060
5061         ns = rte_timespec_to_ns(ts);
5062
5063         /* Set the timecounters to a new value. */
5064         adapter->systime_tc.nsec = ns;
5065         adapter->rx_tstamp_tc.nsec = ns;
5066         adapter->tx_tstamp_tc.nsec = ns;
5067
5068         return 0;
5069 }
5070
5071 static int
5072 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5073 {
5074         uint64_t ns, systime_cycles;
5075         struct e1000_adapter *adapter =
5076                         (struct e1000_adapter *)dev->data->dev_private;
5077
5078         systime_cycles = igb_read_systime_cyclecounter(dev);
5079         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5080         *ts = rte_ns_to_timespec(ns);
5081
5082         return 0;
5083 }
5084
5085 static int
5086 igb_timesync_enable(struct rte_eth_dev *dev)
5087 {
5088         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089         uint32_t tsync_ctl;
5090         uint32_t tsauxc;
5091
5092         /* Stop the timesync system time. */
5093         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5094         /* Reset the timesync system time value. */
5095         switch (hw->mac.type) {
5096         case e1000_82580:
5097         case e1000_i350:
5098         case e1000_i354:
5099         case e1000_i210:
5100         case e1000_i211:
5101                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5102                 /* fall-through */
5103         case e1000_82576:
5104                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5105                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5106                 break;
5107         default:
5108                 /* Not supported. */
5109                 return -ENOTSUP;
5110         }
5111
5112         /* Enable system time for it isn't on by default. */
5113         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5114         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5115         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5116
5117         igb_start_timecounters(dev);
5118
5119         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5120         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5121                         (ETHER_TYPE_1588 |
5122                          E1000_ETQF_FILTER_ENABLE |
5123                          E1000_ETQF_1588));
5124
5125         /* Enable timestamping of received PTP packets. */
5126         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5127         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5128         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5129
5130         /* Enable Timestamping of transmitted PTP packets. */
5131         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5132         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5133         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5134
5135         return 0;
5136 }
5137
5138 static int
5139 igb_timesync_disable(struct rte_eth_dev *dev)
5140 {
5141         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142         uint32_t tsync_ctl;
5143
5144         /* Disable timestamping of transmitted PTP packets. */
5145         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5146         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5147         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5148
5149         /* Disable timestamping of received PTP packets. */
5150         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5151         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5152         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5153
5154         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5155         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5156
5157         /* Stop incrementating the System Time registers. */
5158         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5159
5160         return 0;
5161 }
5162
5163 static int
5164 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5165                                struct timespec *timestamp,
5166                                uint32_t flags __rte_unused)
5167 {
5168         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169         struct e1000_adapter *adapter =
5170                         (struct e1000_adapter *)dev->data->dev_private;
5171         uint32_t tsync_rxctl;
5172         uint64_t rx_tstamp_cycles;
5173         uint64_t ns;
5174
5175         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5176         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5177                 return -EINVAL;
5178
5179         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5180         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5181         *timestamp = rte_ns_to_timespec(ns);
5182
5183         return  0;
5184 }
5185
5186 static int
5187 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5188                                struct timespec *timestamp)
5189 {
5190         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5191         struct e1000_adapter *adapter =
5192                         (struct e1000_adapter *)dev->data->dev_private;
5193         uint32_t tsync_txctl;
5194         uint64_t tx_tstamp_cycles;
5195         uint64_t ns;
5196
5197         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5198         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5199                 return -EINVAL;
5200
5201         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5202         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5203         *timestamp = rte_ns_to_timespec(ns);
5204
5205         return  0;
5206 }
5207
5208 static int
5209 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5210 {
5211         int count = 0;
5212         int g_ind = 0;
5213         const struct reg_info *reg_group;
5214
5215         while ((reg_group = igb_regs[g_ind++]))
5216                 count += igb_reg_group_count(reg_group);
5217
5218         return count;
5219 }
5220
5221 static int
5222 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5223 {
5224         int count = 0;
5225         int g_ind = 0;
5226         const struct reg_info *reg_group;
5227
5228         while ((reg_group = igbvf_regs[g_ind++]))
5229                 count += igb_reg_group_count(reg_group);
5230
5231         return count;
5232 }
5233
5234 static int
5235 eth_igb_get_regs(struct rte_eth_dev *dev,
5236         struct rte_dev_reg_info *regs)
5237 {
5238         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5239         uint32_t *data = regs->data;
5240         int g_ind = 0;
5241         int count = 0;
5242         const struct reg_info *reg_group;
5243
5244         if (data == NULL) {
5245                 regs->length = eth_igb_get_reg_length(dev);
5246                 regs->width = sizeof(uint32_t);
5247                 return 0;
5248         }
5249
5250         /* Support only full register dump */
5251         if ((regs->length == 0) ||
5252             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5253                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5254                         hw->device_id;
5255                 while ((reg_group = igb_regs[g_ind++]))
5256                         count += igb_read_regs_group(dev, &data[count],
5257                                                         reg_group);
5258                 return 0;
5259         }
5260
5261         return -ENOTSUP;
5262 }
5263
5264 static int
5265 igbvf_get_regs(struct rte_eth_dev *dev,
5266         struct rte_dev_reg_info *regs)
5267 {
5268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5269         uint32_t *data = regs->data;
5270         int g_ind = 0;
5271         int count = 0;
5272         const struct reg_info *reg_group;
5273
5274         if (data == NULL) {
5275                 regs->length = igbvf_get_reg_length(dev);
5276                 regs->width = sizeof(uint32_t);
5277                 return 0;
5278         }
5279
5280         /* Support only full register dump */
5281         if ((regs->length == 0) ||
5282             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5283                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5284                         hw->device_id;
5285                 while ((reg_group = igbvf_regs[g_ind++]))
5286                         count += igb_read_regs_group(dev, &data[count],
5287                                                         reg_group);
5288                 return 0;
5289         }
5290
5291         return -ENOTSUP;
5292 }
5293
5294 static int
5295 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5296 {
5297         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298
5299         /* Return unit is byte count */
5300         return hw->nvm.word_size * 2;
5301 }
5302
5303 static int
5304 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5305         struct rte_dev_eeprom_info *in_eeprom)
5306 {
5307         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308         struct e1000_nvm_info *nvm = &hw->nvm;
5309         uint16_t *data = in_eeprom->data;
5310         int first, length;
5311
5312         first = in_eeprom->offset >> 1;
5313         length = in_eeprom->length >> 1;
5314         if ((first >= hw->nvm.word_size) ||
5315             ((first + length) >= hw->nvm.word_size))
5316                 return -EINVAL;
5317
5318         in_eeprom->magic = hw->vendor_id |
5319                 ((uint32_t)hw->device_id << 16);
5320
5321         if ((nvm->ops.read) == NULL)
5322                 return -ENOTSUP;
5323
5324         return nvm->ops.read(hw, first, length, data);
5325 }
5326
5327 static int
5328 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5329         struct rte_dev_eeprom_info *in_eeprom)
5330 {
5331         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5332         struct e1000_nvm_info *nvm = &hw->nvm;
5333         uint16_t *data = in_eeprom->data;
5334         int first, length;
5335
5336         first = in_eeprom->offset >> 1;
5337         length = in_eeprom->length >> 1;
5338         if ((first >= hw->nvm.word_size) ||
5339             ((first + length) >= hw->nvm.word_size))
5340                 return -EINVAL;
5341
5342         in_eeprom->magic = (uint32_t)hw->vendor_id |
5343                 ((uint32_t)hw->device_id << 16);
5344
5345         if ((nvm->ops.write) == NULL)
5346                 return -ENOTSUP;
5347         return nvm->ops.write(hw,  first, length, data);
5348 }
5349
5350 static int
5351 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5352 {
5353         struct e1000_hw *hw =
5354                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5355         uint32_t mask = 1 << queue_id;
5356
5357         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5358         E1000_WRITE_FLUSH(hw);
5359
5360         return 0;
5361 }
5362
5363 static int
5364 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5365 {
5366         struct e1000_hw *hw =
5367                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5369         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5370         uint32_t mask = 1 << queue_id;
5371         uint32_t regval;
5372
5373         regval = E1000_READ_REG(hw, E1000_EIMS);
5374         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5375         E1000_WRITE_FLUSH(hw);
5376
5377         rte_intr_enable(intr_handle);
5378
5379         return 0;
5380 }
5381
5382 static void
5383 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5384                    uint8_t index, uint8_t offset)
5385 {
5386         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5387
5388         /* clear bits */
5389         val &= ~((uint32_t)0xFF << offset);
5390
5391         /* write vector and valid bit */
5392         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5393
5394         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5395 }
5396
5397 static void
5398 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5399                            uint8_t queue, uint8_t msix_vector)
5400 {
5401         uint32_t tmp = 0;
5402
5403         if (hw->mac.type == e1000_82575) {
5404                 if (direction == 0)
5405                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5406                 else if (direction == 1)
5407                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5408                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5409         } else if (hw->mac.type == e1000_82576) {
5410                 if ((direction == 0) || (direction == 1))
5411                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5412                                            ((queue & 0x8) << 1) +
5413                                            8 * direction);
5414         } else if ((hw->mac.type == e1000_82580) ||
5415                         (hw->mac.type == e1000_i350) ||
5416                         (hw->mac.type == e1000_i354) ||
5417                         (hw->mac.type == e1000_i210) ||
5418                         (hw->mac.type == e1000_i211)) {
5419                 if ((direction == 0) || (direction == 1))
5420                         eth_igb_write_ivar(hw, msix_vector,
5421                                            queue >> 1,
5422                                            ((queue & 0x1) << 4) +
5423                                            8 * direction);
5424         }
5425 }
5426
5427 /* Sets up the hardware to generate MSI-X interrupts properly
5428  * @hw
5429  *  board private structure
5430  */
5431 static void
5432 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5433 {
5434         int queue_id;
5435         uint32_t tmpval, regval, intr_mask;
5436         struct e1000_hw *hw =
5437                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5438         uint32_t vec = E1000_MISC_VEC_ID;
5439         uint32_t base = E1000_MISC_VEC_ID;
5440         uint32_t misc_shift = 0;
5441         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5442         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5443
5444         /* won't configure msix register if no mapping is done
5445          * between intr vector and event fd
5446          */
5447         if (!rte_intr_dp_is_en(intr_handle))
5448                 return;
5449
5450         if (rte_intr_allow_others(intr_handle)) {
5451                 vec = base = E1000_RX_VEC_START;
5452                 misc_shift = 1;
5453         }
5454
5455         /* set interrupt vector for other causes */
5456         if (hw->mac.type == e1000_82575) {
5457                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5458                 /* enable MSI-X PBA support */
5459                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5460
5461                 /* Auto-Mask interrupts upon ICR read */
5462                 tmpval |= E1000_CTRL_EXT_EIAME;
5463                 tmpval |= E1000_CTRL_EXT_IRCA;
5464
5465                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5466
5467                 /* enable msix_other interrupt */
5468                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5469                 regval = E1000_READ_REG(hw, E1000_EIAC);
5470                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5471                 regval = E1000_READ_REG(hw, E1000_EIAM);
5472                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5473         } else if ((hw->mac.type == e1000_82576) ||
5474                         (hw->mac.type == e1000_82580) ||
5475                         (hw->mac.type == e1000_i350) ||
5476                         (hw->mac.type == e1000_i354) ||
5477                         (hw->mac.type == e1000_i210) ||
5478                         (hw->mac.type == e1000_i211)) {
5479                 /* turn on MSI-X capability first */
5480                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5481                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5482                                         E1000_GPIE_NSICR);
5483                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5484                         misc_shift;
5485                 regval = E1000_READ_REG(hw, E1000_EIAC);
5486                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5487
5488                 /* enable msix_other interrupt */
5489                 regval = E1000_READ_REG(hw, E1000_EIMS);
5490                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5491                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5492                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5493         }
5494
5495         /* use EIAM to auto-mask when MSI-X interrupt
5496          * is asserted, this saves a register write for every interrupt
5497          */
5498         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5499                 misc_shift;
5500         regval = E1000_READ_REG(hw, E1000_EIAM);
5501         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5502
5503         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5504                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5505                 intr_handle->intr_vec[queue_id] = vec;
5506                 if (vec < base + intr_handle->nb_efd - 1)
5507                         vec++;
5508         }
5509
5510         E1000_WRITE_FLUSH(hw);
5511 }
5512
5513 /* restore n-tuple filter */
5514 static inline void
5515 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5516 {
5517         struct e1000_filter_info *filter_info =
5518                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5519         struct e1000_5tuple_filter *p_5tuple;
5520         struct e1000_2tuple_filter *p_2tuple;
5521
5522         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5523                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5524         }
5525
5526         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5527                 igb_inject_2uple_filter(dev, p_2tuple);
5528         }
5529 }
5530
5531 /* restore SYN filter */
5532 static inline void
5533 igb_syn_filter_restore(struct rte_eth_dev *dev)
5534 {
5535         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5536         struct e1000_filter_info *filter_info =
5537                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5538         uint32_t synqf;
5539
5540         synqf = filter_info->syn_info;
5541
5542         if (synqf & E1000_SYN_FILTER_ENABLE) {
5543                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5544                 E1000_WRITE_FLUSH(hw);
5545         }
5546 }
5547
5548 /* restore ethernet type filter */
5549 static inline void
5550 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5551 {
5552         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5553         struct e1000_filter_info *filter_info =
5554                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5555         int i;
5556
5557         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5558                 if (filter_info->ethertype_mask & (1 << i)) {
5559                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5560                                 filter_info->ethertype_filters[i].etqf);
5561                         E1000_WRITE_FLUSH(hw);
5562                 }
5563         }
5564 }
5565
5566 /* restore flex byte filter */
5567 static inline void
5568 igb_flex_filter_restore(struct rte_eth_dev *dev)
5569 {
5570         struct e1000_filter_info *filter_info =
5571                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5572         struct e1000_flex_filter *flex_filter;
5573
5574         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5575                 igb_inject_flex_filter(dev, flex_filter);
5576         }
5577 }
5578
5579 /* restore all types filter */
5580 static int
5581 igb_filter_restore(struct rte_eth_dev *dev)
5582 {
5583         igb_ntuple_filter_restore(dev);
5584         igb_ethertype_filter_restore(dev);
5585         igb_syn_filter_restore(dev);
5586         igb_flex_filter_restore(dev);
5587
5588         return 0;
5589 }
5590
5591 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5592 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5593 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5594 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5595 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5596 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");