drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29 #include "igb_regs.h"
  30
  31 /*
  32  * Default values for port configuration
  33  */
  34 #define IGB_DEFAULT_RX_FREE_THRESH  32
  35
  36 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  37 #define IGB_DEFAULT_RX_HTHRESH      8
  38 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  39
  40 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  41 #define IGB_DEFAULT_TX_HTHRESH      1
  42 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  43
  44 #define IGB_HKEY_MAX_INDEX 10
  45
  46 /* Bit shift and mask */
  47 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  48 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  49 #define IGB_8_BIT_WIDTH  CHAR_BIT
  50 #define IGB_8_BIT_MASK   UINT8_MAX
  51
  52 /* Additional timesync values. */
  53 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  54 #define E1000_ETQF_FILTER_1588       3
  55 #define IGB_82576_TSYNC_SHIFT        16
  56 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  57 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  58 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  59
  60 #define E1000_VTIVAR_MISC                0x01740
  61 #define E1000_VTIVAR_MISC_MASK           0xFF
  62 #define E1000_VTIVAR_VALID               0x80
  63 #define E1000_VTIVAR_MISC_MAILBOX        0
  64 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  65
  66 /* External VLAN Enable bit mask */
  67 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  68
  69 /* External VLAN Ether Type bit mask and shift */
  70 #define E1000_VET_VET_EXT            0xFFFF0000
  71 #define E1000_VET_VET_EXT_SHIFT      16
  72
  73 static int  eth_igb_configure(struct rte_eth_dev *dev);
  74 static int  eth_igb_start(struct rte_eth_dev *dev);
  75 static void eth_igb_stop(struct rte_eth_dev *dev);
  76 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  77 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  78 static void eth_igb_close(struct rte_eth_dev *dev);
  79 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  80 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  81 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  82 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  83 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  84                                 int wait_to_complete);
  85 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  86                                 struct rte_eth_stats *rte_stats);
  87 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  88                               struct rte_eth_xstat *xstats, unsigned n);
  89 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  90                 const uint64_t *ids,
  91                 uint64_t *values, unsigned int n);
  92 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  93                                     struct rte_eth_xstat_name *xstats_names,
  94                                     unsigned int size);
  95 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  96                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
  97                 unsigned int limit);
  98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  99 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 100 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 101                                    char *fw_version, size_t fw_size);
 102 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 103                               struct rte_eth_dev_info *dev_info);
 104 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 115                                     struct rte_intr_handle *handle);
 116 static void eth_igb_interrupt_handler(void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 128                                  enum rte_vlan_type vlan_type,
 129                                  uint16_t tpid_id);
 130 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 131
 132 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 138
 139 static int eth_igb_led_on(struct rte_eth_dev *dev);
 140 static int eth_igb_led_off(struct rte_eth_dev *dev);
 141
 142 static void igb_intr_disable(struct e1000_hw *hw);
 143 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 144 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 145                            struct ether_addr *mac_addr,
 146                            uint32_t index, uint32_t pool);
 147 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 148 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 149                 struct ether_addr *addr);
 150
 151 static void igbvf_intr_disable(struct e1000_hw *hw);
 152 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 153 static int igbvf_dev_start(struct rte_eth_dev *dev);
 154 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 155 static void igbvf_dev_close(struct rte_eth_dev *dev);
 156 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 158 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 160 static int eth_igbvf_link_update(struct e1000_hw *hw);
 161 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 162                                 struct rte_eth_stats *rte_stats);
 163 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 164                                 struct rte_eth_xstat *xstats, unsigned n);
 165 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 166                                       struct rte_eth_xstat_name *xstats_names,
 167                                       unsigned limit);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter);
 188 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 189                         enum rte_filter_op filter_op,
 190                         void *arg);
 191 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_flex_filter *filter);
 197 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 198                         enum rte_filter_op filter_op,
 199                         void *arg);
 200 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *ntuple_filter);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 213                         struct rte_eth_ethertype_filter *filter);
 214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 215                      enum rte_filter_type filter_type,
 216                      enum rte_filter_op filter_op,
 217                      void *arg);
 218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 220                 struct rte_dev_reg_info *regs);
 221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 225                 struct rte_dev_eeprom_info *eeprom);
 226 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 227                                     struct ether_addr *mc_addr_set,
 228                                     uint32_t nb_mc_addr);
 229 static int igb_timesync_enable(struct rte_eth_dev *dev);
 230 static int igb_timesync_disable(struct rte_eth_dev *dev);
 231 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp,
 233                                           uint32_t flags);
 234 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp);
 236 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 237 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 238                                   struct timespec *timestamp);
 239 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 240                                    const struct timespec *timestamp);
 241 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 242                                         uint16_t queue_id);
 243 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 244                                          uint16_t queue_id);
 245 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 246                                        uint8_t queue, uint8_t msix_vector);
 247 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 248                                uint8_t index, uint8_t offset);
 249 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 250 static void eth_igbvf_interrupt_handler(void *param);
 251 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 252 static int igb_filter_restore(struct rte_eth_dev *dev);
 253
 254 /*
 255  * Define VF Stats MACRO for Non "cleared on read" register
 256  */
 257 #define UPDATE_VF_STAT(reg, last, cur)            \
 258 {                                                 \
 259         u32 latest = E1000_READ_REG(hw, reg);     \
 260         cur += (latest - last) & UINT_MAX;        \
 261         last = latest;                            \
 262 }
 263
 264 #define IGB_FC_PAUSE_TIME 0x0680
 265 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 266 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 267
 268 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 269
 270 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 271
 272 /*
 273  * The set of PCI devices this driver supports
 274  */
 275 static const struct rte_pci_id pci_id_igb_map[] = {
 276         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 284
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 288
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 317         { .vendor_id = 0, /* sentinel */ },
 318 };
 319
 320 /*
 321  * The set of PCI devices this driver supports (for 82576&I350 VF)
 322  */
 323 static const struct rte_pci_id pci_id_igbvf_map[] = {
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 328         { .vendor_id = 0, /* sentinel */ },
 329 };
 330
 331 static const struct rte_eth_desc_lim rx_desc_lim = {
 332         .nb_max = E1000_MAX_RING_DESC,
 333         .nb_min = E1000_MIN_RING_DESC,
 334         .nb_align = IGB_RXD_ALIGN,
 335 };
 336
 337 static const struct rte_eth_desc_lim tx_desc_lim = {
 338         .nb_max = E1000_MAX_RING_DESC,
 339         .nb_min = E1000_MIN_RING_DESC,
 340         .nb_align = IGB_RXD_ALIGN,
 341         .nb_seg_max = IGB_TX_MAX_SEG,
 342         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 343 };
 344
 345 static const struct eth_dev_ops eth_igb_ops = {
 346         .dev_configure        = eth_igb_configure,
 347         .dev_start            = eth_igb_start,
 348         .dev_stop             = eth_igb_stop,
 349         .dev_set_link_up      = eth_igb_dev_set_link_up,
 350         .dev_set_link_down    = eth_igb_dev_set_link_down,
 351         .dev_close            = eth_igb_close,
 352         .promiscuous_enable   = eth_igb_promiscuous_enable,
 353         .promiscuous_disable  = eth_igb_promiscuous_disable,
 354         .allmulticast_enable  = eth_igb_allmulticast_enable,
 355         .allmulticast_disable = eth_igb_allmulticast_disable,
 356         .link_update          = eth_igb_link_update,
 357         .stats_get            = eth_igb_stats_get,
 358         .xstats_get           = eth_igb_xstats_get,
 359         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 360         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 361         .xstats_get_names     = eth_igb_xstats_get_names,
 362         .stats_reset          = eth_igb_stats_reset,
 363         .xstats_reset         = eth_igb_xstats_reset,
 364         .fw_version_get       = eth_igb_fw_version_get,
 365         .dev_infos_get        = eth_igb_infos_get,
 366         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 367         .mtu_set              = eth_igb_mtu_set,
 368         .vlan_filter_set      = eth_igb_vlan_filter_set,
 369         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 370         .vlan_offload_set     = eth_igb_vlan_offload_set,
 371         .rx_queue_setup       = eth_igb_rx_queue_setup,
 372         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 373         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 374         .rx_queue_release     = eth_igb_rx_queue_release,
 375         .rx_queue_count       = eth_igb_rx_queue_count,
 376         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 377         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 378         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 379         .tx_queue_setup       = eth_igb_tx_queue_setup,
 380         .tx_queue_release     = eth_igb_tx_queue_release,
 381         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 382         .dev_led_on           = eth_igb_led_on,
 383         .dev_led_off          = eth_igb_led_off,
 384         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 385         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 386         .mac_addr_add         = eth_igb_rar_set,
 387         .mac_addr_remove      = eth_igb_rar_clear,
 388         .mac_addr_set         = eth_igb_default_mac_addr_set,
 389         .reta_update          = eth_igb_rss_reta_update,
 390         .reta_query           = eth_igb_rss_reta_query,
 391         .rss_hash_update      = eth_igb_rss_hash_update,
 392         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 393         .filter_ctrl          = eth_igb_filter_ctrl,
 394         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 395         .rxq_info_get         = igb_rxq_info_get,
 396         .txq_info_get         = igb_txq_info_get,
 397         .timesync_enable      = igb_timesync_enable,
 398         .timesync_disable     = igb_timesync_disable,
 399         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 400         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 401         .get_reg              = eth_igb_get_regs,
 402         .get_eeprom_length    = eth_igb_get_eeprom_length,
 403         .get_eeprom           = eth_igb_get_eeprom,
 404         .set_eeprom           = eth_igb_set_eeprom,
 405         .timesync_adjust_time = igb_timesync_adjust_time,
 406         .timesync_read_time   = igb_timesync_read_time,
 407         .timesync_write_time  = igb_timesync_write_time,
 408 };
 409
 410 /*
 411  * dev_ops for virtual function, bare necessities for basic vf
 412  * operation have been implemented
 413  */
 414 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 415         .dev_configure        = igbvf_dev_configure,
 416         .dev_start            = igbvf_dev_start,
 417         .dev_stop             = igbvf_dev_stop,
 418         .dev_close            = igbvf_dev_close,
 419         .promiscuous_enable   = igbvf_promiscuous_enable,
 420         .promiscuous_disable  = igbvf_promiscuous_disable,
 421         .allmulticast_enable  = igbvf_allmulticast_enable,
 422         .allmulticast_disable = igbvf_allmulticast_disable,
 423         .link_update          = eth_igb_link_update,
 424         .stats_get            = eth_igbvf_stats_get,
 425         .xstats_get           = eth_igbvf_xstats_get,
 426         .xstats_get_names     = eth_igbvf_xstats_get_names,
 427         .stats_reset          = eth_igbvf_stats_reset,
 428         .xstats_reset         = eth_igbvf_stats_reset,
 429         .vlan_filter_set      = igbvf_vlan_filter_set,
 430         .dev_infos_get        = eth_igbvf_infos_get,
 431         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 432         .rx_queue_setup       = eth_igb_rx_queue_setup,
 433         .rx_queue_release     = eth_igb_rx_queue_release,
 434         .tx_queue_setup       = eth_igb_tx_queue_setup,
 435         .tx_queue_release     = eth_igb_tx_queue_release,
 436         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 437         .rxq_info_get         = igb_rxq_info_get,
 438         .txq_info_get         = igb_txq_info_get,
 439         .mac_addr_set         = igbvf_default_mac_addr_set,
 440         .get_reg              = igbvf_get_regs,
 441 };
 442
 443 /* store statistics names and its offset in stats structure */
 444 struct rte_igb_xstats_name_off {
 445         char name[RTE_ETH_XSTATS_NAME_SIZE];
 446         unsigned offset;
 447 };
 448
 449 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 450         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 451         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 452         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 453         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 454         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 455         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 456         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 457                 ecol)},
 458         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 459         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 460         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 461         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 462         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 463         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 464         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 465         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 466         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 467         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 468         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 469                 fcruc)},
 470         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 471         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 472         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 473         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 474         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 475                 prc1023)},
 476         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 477                 prc1522)},
 478         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 479         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 480         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 481         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 482         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 483         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 484         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 485         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 486         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 487         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 488         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 489         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 490         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 491         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 492         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 493         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 494         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 495         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 496                 ptc1023)},
 497         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 498                 ptc1522)},
 499         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 500         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 501         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 502         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 503         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 504         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 505         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 506
 507         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 508 };
 509
 510 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 511                 sizeof(rte_igb_stats_strings[0]))
 512
 513 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 514         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 515         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 516         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 517         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 518         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 519 };
 520
 521 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 522                 sizeof(rte_igbvf_stats_strings[0]))
 523
 524
 525 static inline void
 526 igb_intr_enable(struct rte_eth_dev *dev)
 527 {
 528         struct e1000_interrupt *intr =
 529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530         struct e1000_hw *hw =
 531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 534         E1000_WRITE_FLUSH(hw);
 535 }
 536
 537 static void
 538 igb_intr_disable(struct e1000_hw *hw)
 539 {
 540         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 541         E1000_WRITE_FLUSH(hw);
 542 }
 543
 544 static inline void
 545 igbvf_intr_enable(struct rte_eth_dev *dev)
 546 {
 547         struct e1000_hw *hw =
 548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 549
 550         /* only for mailbox */
 551         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 552         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 553         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 558 static void
 559 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 560 {
 561         uint32_t tmp = 0;
 562
 563         /* mailbox */
 564         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 565         tmp |= E1000_VTIVAR_VALID;
 566         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 567 }
 568
 569 static void
 570 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 571 {
 572         struct e1000_hw *hw =
 573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 574
 575         /* Configure VF other cause ivar */
 576         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 577 }
 578
 579 static inline int32_t
 580 igb_pf_reset_hw(struct e1000_hw *hw)
 581 {
 582         uint32_t ctrl_ext;
 583         int32_t status;
 584
 585         status = e1000_reset_hw(hw);
 586
 587         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 588         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 589         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 590         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 591         E1000_WRITE_FLUSH(hw);
 592
 593         return status;
 594 }
 595
 596 static void
 597 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 598 {
 599         struct e1000_hw *hw =
 600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 601
 602
 603         hw->vendor_id = pci_dev->id.vendor_id;
 604         hw->device_id = pci_dev->id.device_id;
 605         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 606         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 607
 608         e1000_set_mac_type(hw);
 609
 610         /* need to check if it is a vf device below */
 611 }
 612
 613 static int
 614 igb_reset_swfw_lock(struct e1000_hw *hw)
 615 {
 616         int ret_val;
 617
 618         /*
 619          * Do mac ops initialization manually here, since we will need
 620          * some function pointers set by this call.
 621          */
 622         ret_val = e1000_init_mac_params(hw);
 623         if (ret_val)
 624                 return ret_val;
 625
 626         /*
 627          * SMBI lock should not fail in this early stage. If this is the case,
 628          * it is due to an improper exit of the application.
 629          * So force the release of the faulty lock.
 630          */
 631         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 632                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 633         }
 634         e1000_put_hw_semaphore_generic(hw);
 635
 636         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 637                 uint16_t mask;
 638
 639                 /*
 640                  * Phy lock should not fail in this early stage. If this is the case,
 641                  * it is due to an improper exit of the application.
 642                  * So force the release of the faulty lock.
 643                  */
 644                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 645                 if (hw->bus.func > E1000_FUNC_1)
 646                         mask <<= 2;
 647                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 648                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 649                                     hw->bus.func);
 650                 }
 651                 hw->mac.ops.release_swfw_sync(hw, mask);
 652
 653                 /*
 654                  * This one is more tricky since it is common to all ports; but
 655                  * swfw_sync retries last long enough (1s) to be almost sure that if
 656                  * lock can not be taken it is due to an improper lock of the
 657                  * semaphore.
 658                  */
 659                 mask = E1000_SWFW_EEP_SM;
 660                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 661                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 662                 }
 663                 hw->mac.ops.release_swfw_sync(hw, mask);
 664         }
 665
 666         return E1000_SUCCESS;
 667 }
 668
 669 /* Remove all ntuple filters of the device */
 670 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 671 {
 672         struct e1000_filter_info *filter_info =
 673                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 674         struct e1000_5tuple_filter *p_5tuple;
 675         struct e1000_2tuple_filter *p_2tuple;
 676
 677         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 678                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 679                         p_5tuple, entries);
 680                         rte_free(p_5tuple);
 681         }
 682         filter_info->fivetuple_mask = 0;
 683         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 684                 TAILQ_REMOVE(&filter_info->twotuple_list,
 685                         p_2tuple, entries);
 686                         rte_free(p_2tuple);
 687         }
 688         filter_info->twotuple_mask = 0;
 689
 690         return 0;
 691 }
 692
 693 /* Remove all flex filters of the device */
 694 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_flex_filter *p_flex;
 699
 700         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 701                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 702                 rte_free(p_flex);
 703         }
 704         filter_info->flex_mask = 0;
 705
 706         return 0;
 707 }
 708
 709 static int
 710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         int error = 0;
 713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 714         struct e1000_hw *hw =
 715                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 716         struct e1000_vfta * shadow_vfta =
 717                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 718         struct e1000_filter_info *filter_info =
 719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 720         struct e1000_adapter *adapter =
 721                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 722
 723         uint32_t ctrl_ext;
 724
 725         eth_dev->dev_ops = &eth_igb_ops;
 726         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 727         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 728         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 729
 730         /* for secondary processes, we don't initialise any further as primary
 731          * has already done this work. Only check we don't need a different
 732          * RX function */
 733         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 734                 if (eth_dev->data->scattered_rx)
 735                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 736                 return 0;
 737         }
 738
 739         rte_eth_copy_pci_info(eth_dev, pci_dev);
 740
 741         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 742
 743         igb_identify_hardware(eth_dev, pci_dev);
 744         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 745                 error = -EIO;
 746                 goto err_late;
 747         }
 748
 749         e1000_get_bus_info(hw);
 750
 751         /* Reset any pending lock */
 752         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 753                 error = -EIO;
 754                 goto err_late;
 755         }
 756
 757         /* Finish initialization */
 758         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 759                 error = -EIO;
 760                 goto err_late;
 761         }
 762
 763         hw->mac.autoneg = 1;
 764         hw->phy.autoneg_wait_to_complete = 0;
 765         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 766
 767         /* Copper options */
 768         if (hw->phy.media_type == e1000_media_type_copper) {
 769                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 770                 hw->phy.disable_polarity_correction = 0;
 771                 hw->phy.ms_type = e1000_ms_hw_default;
 772         }
 773
 774         /*
 775          * Start from a known state, this is important in reading the nvm
 776          * and mac from that.
 777          */
 778         igb_pf_reset_hw(hw);
 779
 780         /* Make sure we have a good EEPROM before we read from it */
 781         if (e1000_validate_nvm_checksum(hw) < 0) {
 782                 /*
 783                  * Some PCI-E parts fail the first check due to
 784                  * the link being in sleep state, call it again,
 785                  * if it fails a second time its a real issue.
 786                  */
 787                 if (e1000_validate_nvm_checksum(hw) < 0) {
 788                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 789                         error = -EIO;
 790                         goto err_late;
 791                 }
 792         }
 793
 794         /* Read the permanent MAC address out of the EEPROM */
 795         if (e1000_read_mac_addr(hw) != 0) {
 796                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         /* Allocate memory for storing MAC addresses */
 802         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 803                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 804         if (eth_dev->data->mac_addrs == NULL) {
 805                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 806                                                 "store MAC addresses",
 807                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 808                 error = -ENOMEM;
 809                 goto err_late;
 810         }
 811
 812         /* Copy the permanent MAC address */
 813         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 814
 815         /* initialize the vfta */
 816         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 817
 818         /* Now initialize the hardware */
 819         if (igb_hardware_init(hw) != 0) {
 820                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 821                 rte_free(eth_dev->data->mac_addrs);
 822                 eth_dev->data->mac_addrs = NULL;
 823                 error = -ENODEV;
 824                 goto err_late;
 825         }
 826         hw->mac.get_link_status = 1;
 827         adapter->stopped = 0;
 828
 829         /* Indicate SOL/IDER usage */
 830         if (e1000_check_reset_block(hw) < 0) {
 831                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 832                                         "SOL/IDER session");
 833         }
 834
 835         /* initialize PF if max_vfs not zero */
 836         igb_pf_host_init(eth_dev);
 837
 838         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 839         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 840         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 841         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 842         E1000_WRITE_FLUSH(hw);
 843
 844         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 845                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 846                      pci_dev->id.device_id);
 847
 848         rte_intr_callback_register(&pci_dev->intr_handle,
 849                                    eth_igb_interrupt_handler,
 850                                    (void *)eth_dev);
 851
 852         /* enable uio/vfio intr/eventfd mapping */
 853         rte_intr_enable(&pci_dev->intr_handle);
 854
 855         /* enable support intr */
 856         igb_intr_enable(eth_dev);
 857
 858         /* initialize filter info */
 859         memset(filter_info, 0,
 860                sizeof(struct e1000_filter_info));
 861
 862         TAILQ_INIT(&filter_info->flex_list);
 863         TAILQ_INIT(&filter_info->twotuple_list);
 864         TAILQ_INIT(&filter_info->fivetuple_list);
 865
 866         TAILQ_INIT(&igb_filter_ntuple_list);
 867         TAILQ_INIT(&igb_filter_ethertype_list);
 868         TAILQ_INIT(&igb_filter_syn_list);
 869         TAILQ_INIT(&igb_filter_flex_list);
 870         TAILQ_INIT(&igb_filter_rss_list);
 871         TAILQ_INIT(&igb_flow_list);
 872
 873         return 0;
 874
 875 err_late:
 876         igb_hw_control_release(hw);
 877
 878         return error;
 879 }
 880
 881 static int
 882 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 883 {
 884         struct rte_pci_device *pci_dev;
 885         struct rte_intr_handle *intr_handle;
 886         struct e1000_hw *hw;
 887         struct e1000_adapter *adapter =
 888                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 889         struct e1000_filter_info *filter_info =
 890                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 891
 892         PMD_INIT_FUNC_TRACE();
 893
 894         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 895                 return -EPERM;
 896
 897         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 898         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 899         intr_handle = &pci_dev->intr_handle;
 900
 901         if (adapter->stopped == 0)
 902                 eth_igb_close(eth_dev);
 903
 904         eth_dev->dev_ops = NULL;
 905         eth_dev->rx_pkt_burst = NULL;
 906         eth_dev->tx_pkt_burst = NULL;
 907
 908         /* Reset any pending lock */
 909         igb_reset_swfw_lock(hw);
 910
 911         rte_free(eth_dev->data->mac_addrs);
 912         eth_dev->data->mac_addrs = NULL;
 913
 914         /* uninitialize PF if max_vfs not zero */
 915         igb_pf_host_uninit(eth_dev);
 916
 917         /* disable uio intr before callback unregister */
 918         rte_intr_disable(intr_handle);
 919         rte_intr_callback_unregister(intr_handle,
 920                                      eth_igb_interrupt_handler, eth_dev);
 921
 922         /* clear the SYN filter info */
 923         filter_info->syn_info = 0;
 924
 925         /* clear the ethertype filters info */
 926         filter_info->ethertype_mask = 0;
 927         memset(filter_info->ethertype_filters, 0,
 928                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 929
 930         /* clear the rss filter info */
 931         memset(&filter_info->rss_info, 0,
 932                 sizeof(struct igb_rte_flow_rss_conf));
 933
 934         /* remove all ntuple filters of the device */
 935         igb_ntuple_filter_uninit(eth_dev);
 936
 937         /* remove all flex filters of the device */
 938         igb_flex_filter_uninit(eth_dev);
 939
 940         /* clear all the filters list */
 941         igb_filterlist_flush(eth_dev);
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Virtual Function device init
 948  */
 949 static int
 950 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 951 {
 952         struct rte_pci_device *pci_dev;
 953         struct rte_intr_handle *intr_handle;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 967
 968         /* for secondary processes, we don't initialise any further as primary
 969          * has already done this work. Only check we don't need a different
 970          * RX function */
 971         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 972                 if (eth_dev->data->scattered_rx)
 973                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 974                 return 0;
 975         }
 976
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1027         if (diag) {
1028                 rte_free(eth_dev->data->mac_addrs);
1029                 eth_dev->data->mac_addrs = NULL;
1030                 return diag;
1031         }
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         intr_handle = &pci_dev->intr_handle;
1042         rte_intr_callback_register(intr_handle,
1043                                    eth_igbvf_interrupt_handler, eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1080         struct rte_pci_device *pci_dev)
1081 {
1082         return rte_eth_dev_pci_generic_probe(pci_dev,
1083                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1084 }
1085
1086 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1087 {
1088         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1089 }
1090
1091 static struct rte_pci_driver rte_igb_pmd = {
1092         .id_table = pci_id_igb_map,
1093         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1094                      RTE_PCI_DRV_IOVA_AS_VA,
1095         .probe = eth_igb_pci_probe,
1096         .remove = eth_igb_pci_remove,
1097 };
1098
1099
1100 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101         struct rte_pci_device *pci_dev)
1102 {
1103         return rte_eth_dev_pci_generic_probe(pci_dev,
1104                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1105 }
1106
1107 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1110 }
1111
1112 /*
1113  * virtual function driver struct
1114  */
1115 static struct rte_pci_driver rte_igbvf_pmd = {
1116         .id_table = pci_id_igbvf_map,
1117         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1118         .probe = eth_igbvf_pci_probe,
1119         .remove = eth_igbvf_pci_remove,
1120 };
1121
1122 static void
1123 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1128         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1129         rctl |= E1000_RCTL_VFE;
1130         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1131 }
1132
1133 static int
1134 igb_check_mq_mode(struct rte_eth_dev *dev)
1135 {
1136         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1137         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1138         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1139         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1140
1141         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1142             tx_mq_mode == ETH_MQ_TX_DCB ||
1143             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1144                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1145                 return -EINVAL;
1146         }
1147         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1148                 /* Check multi-queue mode.
1149                  * To no break software we accept ETH_MQ_RX_NONE as this might
1150                  * be used to turn off VLAN filter.
1151                  */
1152
1153                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1154                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1155                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1156                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1157                 } else {
1158                         /* Only support one queue on VFs.
1159                          * RSS together with SRIOV is not supported.
1160                          */
1161                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1162                                         " wrong mq_mode rx %d.",
1163                                         rx_mq_mode);
1164                         return -EINVAL;
1165                 }
1166                 /* TX mode is not used here, so mode might be ignored.*/
1167                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1168                         /* SRIOV only works in VMDq enable mode */
1169                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1170                                         " TX mode %d is not supported. "
1171                                         " Driver will behave as %d mode.",
1172                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1173                 }
1174
1175                 /* check valid queue number */
1176                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1177                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1178                                         " only support one queue on VFs.");
1179                         return -EINVAL;
1180                 }
1181         } else {
1182                 /* To no break software that set invalid mode, only display
1183                  * warning if invalid mode is used.
1184                  */
1185                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1186                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1187                     rx_mq_mode != ETH_MQ_RX_RSS) {
1188                         /* RSS together with VMDq not supported*/
1189                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1190                                      rx_mq_mode);
1191                         return -EINVAL;
1192                 }
1193
1194                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1195                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1196                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1197                                         " Due to txmode is meaningless in this"
1198                                         " driver, just ignore.",
1199                                         tx_mq_mode);
1200                 }
1201         }
1202         return 0;
1203 }
1204
1205 static int
1206 eth_igb_configure(struct rte_eth_dev *dev)
1207 {
1208         struct e1000_interrupt *intr =
1209                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1210         int ret;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* multipe queue mode checking */
1215         ret  = igb_check_mq_mode(dev);
1216         if (ret != 0) {
1217                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1218                             ret);
1219                 return ret;
1220         }
1221
1222         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1223         PMD_INIT_FUNC_TRACE();
1224
1225         return 0;
1226 }
1227
1228 static void
1229 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1230                      bool enable)
1231 {
1232         struct e1000_hw *hw =
1233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t tctl, rctl;
1235
1236         tctl = E1000_READ_REG(hw, E1000_TCTL);
1237         rctl = E1000_READ_REG(hw, E1000_RCTL);
1238
1239         if (enable) {
1240                 /* enable Tx/Rx */
1241                 tctl |= E1000_TCTL_EN;
1242                 rctl |= E1000_RCTL_EN;
1243         } else {
1244                 /* disable Tx/Rx */
1245                 tctl &= ~E1000_TCTL_EN;
1246                 rctl &= ~E1000_RCTL_EN;
1247         }
1248         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1249         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1250         E1000_WRITE_FLUSH(hw);
1251 }
1252
1253 static int
1254 eth_igb_start(struct rte_eth_dev *dev)
1255 {
1256         struct e1000_hw *hw =
1257                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258         struct e1000_adapter *adapter =
1259                 E1000_DEV_PRIVATE(dev->data->dev_private);
1260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1262         int ret, mask;
1263         uint32_t intr_vector = 0;
1264         uint32_t ctrl_ext;
1265         uint32_t *speeds;
1266         int num_speeds;
1267         bool autoneg;
1268
1269         PMD_INIT_FUNC_TRACE();
1270
1271         /* disable uio/vfio intr/eventfd mapping */
1272         rte_intr_disable(intr_handle);
1273
1274         /* Power up the phy. Needed to make the link go Up */
1275         eth_igb_dev_set_link_up(dev);
1276
1277         /*
1278          * Packet Buffer Allocation (PBA)
1279          * Writing PBA sets the receive portion of the buffer
1280          * the remainder is used for the transmit buffer.
1281          */
1282         if (hw->mac.type == e1000_82575) {
1283                 uint32_t pba;
1284
1285                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1286                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1287         }
1288
1289         /* Put the address into the Receive Address Array */
1290         e1000_rar_set(hw, hw->mac.addr, 0);
1291
1292         /* Initialize the hardware */
1293         if (igb_hardware_init(hw)) {
1294                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1295                 return -EIO;
1296         }
1297         adapter->stopped = 0;
1298
1299         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1300
1301         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1304         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1305         E1000_WRITE_FLUSH(hw);
1306
1307         /* configure PF module if SRIOV enabled */
1308         igb_pf_host_configure(dev);
1309
1310         /* check and configure queue intr-vector mapping */
1311         if ((rte_intr_cap_multiple(intr_handle) ||
1312              !RTE_ETH_DEV_SRIOV(dev).active) &&
1313             dev->data->dev_conf.intr_conf.rxq != 0) {
1314                 intr_vector = dev->data->nb_rx_queues;
1315                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1316                         return -1;
1317         }
1318
1319         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1320                 intr_handle->intr_vec =
1321                         rte_zmalloc("intr_vec",
1322                                     dev->data->nb_rx_queues * sizeof(int), 0);
1323                 if (intr_handle->intr_vec == NULL) {
1324                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1325                                      " intr_vec", dev->data->nb_rx_queues);
1326                         return -ENOMEM;
1327                 }
1328         }
1329
1330         /* confiugre msix for rx interrupt */
1331         eth_igb_configure_msix_intr(dev);
1332
1333         /* Configure for OS presence */
1334         igb_init_manageability(hw);
1335
1336         eth_igb_tx_init(dev);
1337
1338         /* This can fail when allocating mbufs for descriptor rings */
1339         ret = eth_igb_rx_init(dev);
1340         if (ret) {
1341                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1342                 igb_dev_clear_queues(dev);
1343                 return ret;
1344         }
1345
1346         e1000_clear_hw_cntrs_base_generic(hw);
1347
1348         /*
1349          * VLAN Offload Settings
1350          */
1351         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1352                         ETH_VLAN_EXTEND_MASK;
1353         ret = eth_igb_vlan_offload_set(dev, mask);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1356                 igb_dev_clear_queues(dev);
1357                 return ret;
1358         }
1359
1360         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361                 /* Enable VLAN filter since VMDq always use VLAN filter */
1362                 igb_vmdq_vlan_hw_filter_enable(dev);
1363         }
1364
1365         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1366                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1367                 (hw->mac.type == e1000_i211)) {
1368                 /* Configure EITR with the maximum possible value (0xFFFF) */
1369                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1370         }
1371
1372         /* Setup link speed and duplex */
1373         speeds = &dev->data->dev_conf.link_speeds;
1374         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1375                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1376                 hw->mac.autoneg = 1;
1377         } else {
1378                 num_speeds = 0;
1379                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1380
1381                 /* Reset */
1382                 hw->phy.autoneg_advertised = 0;
1383
1384                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1385                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1386                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1387                         num_speeds = -1;
1388                         goto error_invalid_config;
1389                 }
1390                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1391                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1392                         num_speeds++;
1393                 }
1394                 if (*speeds & ETH_LINK_SPEED_10M) {
1395                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1396                         num_speeds++;
1397                 }
1398                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1399                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1400                         num_speeds++;
1401                 }
1402                 if (*speeds & ETH_LINK_SPEED_100M) {
1403                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1404                         num_speeds++;
1405                 }
1406                 if (*speeds & ETH_LINK_SPEED_1G) {
1407                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1408                         num_speeds++;
1409                 }
1410                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1411                         goto error_invalid_config;
1412
1413                 /* Set/reset the mac.autoneg based on the link speed,
1414                  * fixed or not
1415                  */
1416                 if (!autoneg) {
1417                         hw->mac.autoneg = 0;
1418                         hw->mac.forced_speed_duplex =
1419                                         hw->phy.autoneg_advertised;
1420                 } else {
1421                         hw->mac.autoneg = 1;
1422                 }
1423         }
1424
1425         e1000_setup_link(hw);
1426
1427         if (rte_intr_allow_others(intr_handle)) {
1428                 /* check if lsc interrupt is enabled */
1429                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1430                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1431                 else
1432                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1433         } else {
1434                 rte_intr_callback_unregister(intr_handle,
1435                                              eth_igb_interrupt_handler,
1436                                              (void *)dev);
1437                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1438                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1439                                      " no intr multiplex");
1440         }
1441
1442         /* check if rxq interrupt is enabled */
1443         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1444             rte_intr_dp_is_en(intr_handle))
1445                 eth_igb_rxq_interrupt_setup(dev);
1446
1447         /* enable uio/vfio intr/eventfd mapping */
1448         rte_intr_enable(intr_handle);
1449
1450         /* resume enabled intr since hw reset */
1451         igb_intr_enable(dev);
1452
1453         /* restore all types filter */
1454         igb_filter_restore(dev);
1455
1456         eth_igb_rxtx_control(dev, true);
1457         eth_igb_link_update(dev, 0);
1458
1459         PMD_INIT_LOG(DEBUG, "<<");
1460
1461         return 0;
1462
1463 error_invalid_config:
1464         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1465                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1466         igb_dev_clear_queues(dev);
1467         return -EINVAL;
1468 }
1469
1470 /*********************************************************************
1471  *
1472  *  This routine disables all traffic on the adapter by issuing a
1473  *  global reset on the MAC.
1474  *
1475  **********************************************************************/
1476 static void
1477 eth_igb_stop(struct rte_eth_dev *dev)
1478 {
1479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1481         struct rte_eth_link link;
1482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483
1484         eth_igb_rxtx_control(dev, false);
1485
1486         igb_intr_disable(hw);
1487
1488         /* disable intr eventfd mapping */
1489         rte_intr_disable(intr_handle);
1490
1491         igb_pf_reset_hw(hw);
1492         E1000_WRITE_REG(hw, E1000_WUC, 0);
1493
1494         /* Set bit for Go Link disconnect */
1495         if (hw->mac.type >= e1000_82580) {
1496                 uint32_t phpm_reg;
1497
1498                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1499                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1500                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1501         }
1502
1503         /* Power down the phy. Needed to make the link go Down */
1504         eth_igb_dev_set_link_down(dev);
1505
1506         igb_dev_clear_queues(dev);
1507
1508         /* clear the recorded link status */
1509         memset(&link, 0, sizeof(link));
1510         rte_eth_linkstatus_set(dev, &link);
1511
1512         if (!rte_intr_allow_others(intr_handle))
1513                 /* resume to the default handler */
1514                 rte_intr_callback_register(intr_handle,
1515                                            eth_igb_interrupt_handler,
1516                                            (void *)dev);
1517
1518         /* Clean datapath event and queue/vec mapping */
1519         rte_intr_efd_disable(intr_handle);
1520         if (intr_handle->intr_vec != NULL) {
1521                 rte_free(intr_handle->intr_vec);
1522                 intr_handle->intr_vec = NULL;
1523         }
1524 }
1525
1526 static int
1527 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1528 {
1529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         if (hw->phy.media_type == e1000_media_type_copper)
1532                 e1000_power_up_phy(hw);
1533         else
1534                 e1000_power_up_fiber_serdes_link(hw);
1535
1536         return 0;
1537 }
1538
1539 static int
1540 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1541 {
1542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543
1544         if (hw->phy.media_type == e1000_media_type_copper)
1545                 e1000_power_down_phy(hw);
1546         else
1547                 e1000_shutdown_fiber_serdes_link(hw);
1548
1549         return 0;
1550 }
1551
1552 static void
1553 eth_igb_close(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_adapter *adapter =
1557                 E1000_DEV_PRIVATE(dev->data->dev_private);
1558         struct rte_eth_link link;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561
1562         eth_igb_stop(dev);
1563         adapter->stopped = 1;
1564
1565         e1000_phy_hw_reset(hw);
1566         igb_release_manageability(hw);
1567         igb_hw_control_release(hw);
1568
1569         /* Clear bit for Go Link disconnect */
1570         if (hw->mac.type >= e1000_82580) {
1571                 uint32_t phpm_reg;
1572
1573                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1574                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1575                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1576         }
1577
1578         igb_dev_free_queues(dev);
1579
1580         if (intr_handle->intr_vec) {
1581                 rte_free(intr_handle->intr_vec);
1582                 intr_handle->intr_vec = NULL;
1583         }
1584
1585         memset(&link, 0, sizeof(link));
1586         rte_eth_linkstatus_set(dev, &link);
1587 }
1588
1589 static int
1590 igb_get_rx_buffer_size(struct e1000_hw *hw)
1591 {
1592         uint32_t rx_buf_size;
1593         if (hw->mac.type == e1000_82576) {
1594                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1595         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1596                 /* PBS needs to be translated according to a lookup table */
1597                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1598                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1599                 rx_buf_size = (rx_buf_size << 10);
1600         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1601                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1602         } else {
1603                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1604         }
1605
1606         return rx_buf_size;
1607 }
1608
1609 /*********************************************************************
1610  *
1611  *  Initialize the hardware
1612  *
1613  **********************************************************************/
1614 static int
1615 igb_hardware_init(struct e1000_hw *hw)
1616 {
1617         uint32_t rx_buf_size;
1618         int diag;
1619
1620         /* Let the firmware know the OS is in control */
1621         igb_hw_control_acquire(hw);
1622
1623         /*
1624          * These parameters control the automatic generation (Tx) and
1625          * response (Rx) to Ethernet PAUSE frames.
1626          * - High water mark should allow for at least two standard size (1518)
1627          *   frames to be received after sending an XOFF.
1628          * - Low water mark works best when it is very near the high water mark.
1629          *   This allows the receiver to restart by sending XON when it has
1630          *   drained a bit. Here we use an arbitrary value of 1500 which will
1631          *   restart after one full frame is pulled from the buffer. There
1632          *   could be several smaller frames in the buffer and if so they will
1633          *   not trigger the XON until their total number reduces the buffer
1634          *   by 1500.
1635          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1636          */
1637         rx_buf_size = igb_get_rx_buffer_size(hw);
1638
1639         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1640         hw->fc.low_water = hw->fc.high_water - 1500;
1641         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1642         hw->fc.send_xon = 1;
1643
1644         /* Set Flow control, use the tunable location if sane */
1645         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1646                 hw->fc.requested_mode = igb_fc_setting;
1647         else
1648                 hw->fc.requested_mode = e1000_fc_none;
1649
1650         /* Issue a global reset */
1651         igb_pf_reset_hw(hw);
1652         E1000_WRITE_REG(hw, E1000_WUC, 0);
1653
1654         diag = e1000_init_hw(hw);
1655         if (diag < 0)
1656                 return diag;
1657
1658         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1659         e1000_get_phy_info(hw);
1660         e1000_check_for_link(hw);
1661
1662         return 0;
1663 }
1664
1665 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1666 static void
1667 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1668 {
1669         int pause_frames;
1670
1671         uint64_t old_gprc  = stats->gprc;
1672         uint64_t old_gptc  = stats->gptc;
1673         uint64_t old_tpr   = stats->tpr;
1674         uint64_t old_tpt   = stats->tpt;
1675         uint64_t old_rpthc = stats->rpthc;
1676         uint64_t old_hgptc = stats->hgptc;
1677
1678         if(hw->phy.media_type == e1000_media_type_copper ||
1679             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1680                 stats->symerrs +=
1681                     E1000_READ_REG(hw,E1000_SYMERRS);
1682                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1683         }
1684
1685         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1686         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1687         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1688         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1689
1690         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1691         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1692         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1693         stats->dc += E1000_READ_REG(hw, E1000_DC);
1694         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1695         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1696         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1697         /*
1698         ** For watchdog management we need to know if we have been
1699         ** paused during the last interval, so capture that here.
1700         */
1701         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1702         stats->xoffrxc += pause_frames;
1703         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1704         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1705         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1706         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1707         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1708         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1709         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1710         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1711         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1712         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1713         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1714         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1715
1716         /* For the 64-bit byte counters the low dword must be read first. */
1717         /* Both registers clear on the read of the high dword */
1718
1719         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1720         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1721         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1722         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1723         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1724         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1725         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1726
1727         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1728         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1729         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1730         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1731         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1732
1733         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1734         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1735
1736         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1737         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1738         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1739         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1740         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1741         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1742
1743         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1744         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1745         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1746         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1747         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1748         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1749         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1750         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1751
1752         /* Interrupt Counts */
1753
1754         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1755         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1756         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1757         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1758         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1759         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1760         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1761         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1762         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1763
1764         /* Host to Card Statistics */
1765
1766         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1767         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1768         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1769         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1770         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1771         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1772         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1773         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1774         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1775         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1776         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1777         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1778         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1779         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1780         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1781         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1782
1783         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1784         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1785         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1786         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1787         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1788         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1789 }
1790
1791 static int
1792 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         struct e1000_hw_stats *stats =
1796                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1797
1798         igb_read_stats_registers(hw, stats);
1799
1800         if (rte_stats == NULL)
1801                 return -EINVAL;
1802
1803         /* Rx Errors */
1804         rte_stats->imissed = stats->mpc;
1805         rte_stats->ierrors = stats->crcerrs +
1806                              stats->rlec + stats->ruc + stats->roc +
1807                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1808
1809         /* Tx Errors */
1810         rte_stats->oerrors = stats->ecol + stats->latecol;
1811
1812         rte_stats->ipackets = stats->gprc;
1813         rte_stats->opackets = stats->gptc;
1814         rte_stats->ibytes   = stats->gorc;
1815         rte_stats->obytes   = stats->gotc;
1816         return 0;
1817 }
1818
1819 static void
1820 eth_igb_stats_reset(struct rte_eth_dev *dev)
1821 {
1822         struct e1000_hw_stats *hw_stats =
1823                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1824
1825         /* HW registers are cleared on read */
1826         eth_igb_stats_get(dev, NULL);
1827
1828         /* Reset software totals */
1829         memset(hw_stats, 0, sizeof(*hw_stats));
1830 }
1831
1832 static void
1833 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1834 {
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         /* HW registers are cleared on read */
1839         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1840
1841         /* Reset software totals */
1842         memset(stats, 0, sizeof(*stats));
1843 }
1844
1845 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1846         struct rte_eth_xstat_name *xstats_names,
1847         __rte_unused unsigned int size)
1848 {
1849         unsigned i;
1850
1851         if (xstats_names == NULL)
1852                 return IGB_NB_XSTATS;
1853
1854         /* Note: limit checked in rte_eth_xstats_names() */
1855
1856         for (i = 0; i < IGB_NB_XSTATS; i++) {
1857                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1858                          "%s", rte_igb_stats_strings[i].name);
1859         }
1860
1861         return IGB_NB_XSTATS;
1862 }
1863
1864 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1865                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1866                 unsigned int limit)
1867 {
1868         unsigned int i;
1869
1870         if (!ids) {
1871                 if (xstats_names == NULL)
1872                         return IGB_NB_XSTATS;
1873
1874                 for (i = 0; i < IGB_NB_XSTATS; i++)
1875                         snprintf(xstats_names[i].name,
1876                                         sizeof(xstats_names[i].name),
1877                                         "%s", rte_igb_stats_strings[i].name);
1878
1879                 return IGB_NB_XSTATS;
1880
1881         } else {
1882                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1883
1884                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1885                                 IGB_NB_XSTATS);
1886
1887                 for (i = 0; i < limit; i++) {
1888                         if (ids[i] >= IGB_NB_XSTATS) {
1889                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1890                                 return -1;
1891                         }
1892                         strcpy(xstats_names[i].name,
1893                                         xstats_names_copy[ids[i]].name);
1894                 }
1895                 return limit;
1896         }
1897 }
1898
1899 static int
1900 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1901                    unsigned n)
1902 {
1903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct e1000_hw_stats *hw_stats =
1905                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1906         unsigned i;
1907
1908         if (n < IGB_NB_XSTATS)
1909                 return IGB_NB_XSTATS;
1910
1911         igb_read_stats_registers(hw, hw_stats);
1912
1913         /* If this is a reset xstats is NULL, and we have cleared the
1914          * registers by reading them.
1915          */
1916         if (!xstats)
1917                 return 0;
1918
1919         /* Extended stats */
1920         for (i = 0; i < IGB_NB_XSTATS; i++) {
1921                 xstats[i].id = i;
1922                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1923                         rte_igb_stats_strings[i].offset);
1924         }
1925
1926         return IGB_NB_XSTATS;
1927 }
1928
1929 static int
1930 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1931                 uint64_t *values, unsigned int n)
1932 {
1933         unsigned int i;
1934
1935         if (!ids) {
1936                 struct e1000_hw *hw =
1937                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938                 struct e1000_hw_stats *hw_stats =
1939                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1940
1941                 if (n < IGB_NB_XSTATS)
1942                         return IGB_NB_XSTATS;
1943
1944                 igb_read_stats_registers(hw, hw_stats);
1945
1946                 /* If this is a reset xstats is NULL, and we have cleared the
1947                  * registers by reading them.
1948                  */
1949                 if (!values)
1950                         return 0;
1951
1952                 /* Extended stats */
1953                 for (i = 0; i < IGB_NB_XSTATS; i++)
1954                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1955                                         rte_igb_stats_strings[i].offset);
1956
1957                 return IGB_NB_XSTATS;
1958
1959         } else {
1960                 uint64_t values_copy[IGB_NB_XSTATS];
1961
1962                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1963                                 IGB_NB_XSTATS);
1964
1965                 for (i = 0; i < n; i++) {
1966                         if (ids[i] >= IGB_NB_XSTATS) {
1967                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1968                                 return -1;
1969                         }
1970                         values[i] = values_copy[ids[i]];
1971                 }
1972                 return n;
1973         }
1974 }
1975
1976 static void
1977 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1978 {
1979         /* Good Rx packets, include VF loopback */
1980         UPDATE_VF_STAT(E1000_VFGPRC,
1981             hw_stats->last_gprc, hw_stats->gprc);
1982
1983         /* Good Rx octets, include VF loopback */
1984         UPDATE_VF_STAT(E1000_VFGORC,
1985             hw_stats->last_gorc, hw_stats->gorc);
1986
1987         /* Good Tx packets, include VF loopback */
1988         UPDATE_VF_STAT(E1000_VFGPTC,
1989             hw_stats->last_gptc, hw_stats->gptc);
1990
1991         /* Good Tx octets, include VF loopback */
1992         UPDATE_VF_STAT(E1000_VFGOTC,
1993             hw_stats->last_gotc, hw_stats->gotc);
1994
1995         /* Rx Multicst packets */
1996         UPDATE_VF_STAT(E1000_VFMPRC,
1997             hw_stats->last_mprc, hw_stats->mprc);
1998
1999         /* Good Rx loopback packets */
2000         UPDATE_VF_STAT(E1000_VFGPRLBC,
2001             hw_stats->last_gprlbc, hw_stats->gprlbc);
2002
2003         /* Good Rx loopback octets */
2004         UPDATE_VF_STAT(E1000_VFGORLBC,
2005             hw_stats->last_gorlbc, hw_stats->gorlbc);
2006
2007         /* Good Tx loopback packets */
2008         UPDATE_VF_STAT(E1000_VFGPTLBC,
2009             hw_stats->last_gptlbc, hw_stats->gptlbc);
2010
2011         /* Good Tx loopback octets */
2012         UPDATE_VF_STAT(E1000_VFGOTLBC,
2013             hw_stats->last_gotlbc, hw_stats->gotlbc);
2014 }
2015
2016 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2017                                      struct rte_eth_xstat_name *xstats_names,
2018                                      __rte_unused unsigned limit)
2019 {
2020         unsigned i;
2021
2022         if (xstats_names != NULL)
2023                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2024                         snprintf(xstats_names[i].name,
2025                                 sizeof(xstats_names[i].name), "%s",
2026                                 rte_igbvf_stats_strings[i].name);
2027                 }
2028         return IGBVF_NB_XSTATS;
2029 }
2030
2031 static int
2032 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2033                      unsigned n)
2034 {
2035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2037                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2038         unsigned i;
2039
2040         if (n < IGBVF_NB_XSTATS)
2041                 return IGBVF_NB_XSTATS;
2042
2043         igbvf_read_stats_registers(hw, hw_stats);
2044
2045         if (!xstats)
2046                 return 0;
2047
2048         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2049                 xstats[i].id = i;
2050                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2051                         rte_igbvf_stats_strings[i].offset);
2052         }
2053
2054         return IGBVF_NB_XSTATS;
2055 }
2056
2057 static int
2058 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2059 {
2060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2062                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2063
2064         igbvf_read_stats_registers(hw, hw_stats);
2065
2066         if (rte_stats == NULL)
2067                 return -EINVAL;
2068
2069         rte_stats->ipackets = hw_stats->gprc;
2070         rte_stats->ibytes = hw_stats->gorc;
2071         rte_stats->opackets = hw_stats->gptc;
2072         rte_stats->obytes = hw_stats->gotc;
2073         return 0;
2074 }
2075
2076 static void
2077 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2078 {
2079         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2080                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081
2082         /* Sync HW register to the last stats */
2083         eth_igbvf_stats_get(dev, NULL);
2084
2085         /* reset HW current stats*/
2086         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2087                offsetof(struct e1000_vf_stats, gprc));
2088 }
2089
2090 static int
2091 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2092                        size_t fw_size)
2093 {
2094         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct e1000_fw_version fw;
2096         int ret;
2097
2098         e1000_get_fw_version(hw, &fw);
2099
2100         switch (hw->mac.type) {
2101         case e1000_i210:
2102         case e1000_i211:
2103                 if (!(e1000_get_flash_presence_i210(hw))) {
2104                         ret = snprintf(fw_version, fw_size,
2105                                  "%2d.%2d-%d",
2106                                  fw.invm_major, fw.invm_minor,
2107                                  fw.invm_img_type);
2108                         break;
2109                 }
2110                 /* fall through */
2111         default:
2112                 /* if option rom is valid, display its version too */
2113                 if (fw.or_valid) {
2114                         ret = snprintf(fw_version, fw_size,
2115                                  "%d.%d, 0x%08x, %d.%d.%d",
2116                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2117                                  fw.or_major, fw.or_build, fw.or_patch);
2118                 /* no option rom */
2119                 } else {
2120                         if (fw.etrack_id != 0X0000) {
2121                                 ret = snprintf(fw_version, fw_size,
2122                                          "%d.%d, 0x%08x",
2123                                          fw.eep_major, fw.eep_minor,
2124                                          fw.etrack_id);
2125                         } else {
2126                                 ret = snprintf(fw_version, fw_size,
2127                                          "%d.%d.%d",
2128                                          fw.eep_major, fw.eep_minor,
2129                                          fw.eep_build);
2130                         }
2131                 }
2132                 break;
2133         }
2134
2135         ret += 1; /* add the size of '\0' */
2136         if (fw_size < (u32)ret)
2137                 return ret;
2138         else
2139                 return 0;
2140 }
2141
2142 static void
2143 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2144 {
2145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146
2147         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2148         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2149         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2150         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2151         dev_info->rx_offload_capa =
2152                 DEV_RX_OFFLOAD_VLAN_STRIP |
2153                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2154                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2155                 DEV_RX_OFFLOAD_TCP_CKSUM;
2156         dev_info->tx_offload_capa =
2157                 DEV_TX_OFFLOAD_VLAN_INSERT |
2158                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2159                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2160                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2161                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2162                 DEV_TX_OFFLOAD_TCP_TSO;
2163
2164         switch (hw->mac.type) {
2165         case e1000_82575:
2166                 dev_info->max_rx_queues = 4;
2167                 dev_info->max_tx_queues = 4;
2168                 dev_info->max_vmdq_pools = 0;
2169                 break;
2170
2171         case e1000_82576:
2172                 dev_info->max_rx_queues = 16;
2173                 dev_info->max_tx_queues = 16;
2174                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2175                 dev_info->vmdq_queue_num = 16;
2176                 break;
2177
2178         case e1000_82580:
2179                 dev_info->max_rx_queues = 8;
2180                 dev_info->max_tx_queues = 8;
2181                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2182                 dev_info->vmdq_queue_num = 8;
2183                 break;
2184
2185         case e1000_i350:
2186                 dev_info->max_rx_queues = 8;
2187                 dev_info->max_tx_queues = 8;
2188                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2189                 dev_info->vmdq_queue_num = 8;
2190                 break;
2191
2192         case e1000_i354:
2193                 dev_info->max_rx_queues = 8;
2194                 dev_info->max_tx_queues = 8;
2195                 break;
2196
2197         case e1000_i210:
2198                 dev_info->max_rx_queues = 4;
2199                 dev_info->max_tx_queues = 4;
2200                 dev_info->max_vmdq_pools = 0;
2201                 break;
2202
2203         case e1000_i211:
2204                 dev_info->max_rx_queues = 2;
2205                 dev_info->max_tx_queues = 2;
2206                 dev_info->max_vmdq_pools = 0;
2207                 break;
2208
2209         default:
2210                 /* Should not happen */
2211                 break;
2212         }
2213         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2214         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2215         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2216
2217         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2218                 .rx_thresh = {
2219                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2220                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2221                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2222                 },
2223                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2224                 .rx_drop_en = 0,
2225         };
2226
2227         dev_info->default_txconf = (struct rte_eth_txconf) {
2228                 .tx_thresh = {
2229                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2230                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2231                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2232                 },
2233                 .txq_flags = 0,
2234         };
2235
2236         dev_info->rx_desc_lim = rx_desc_lim;
2237         dev_info->tx_desc_lim = tx_desc_lim;
2238
2239         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2240                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2241                         ETH_LINK_SPEED_1G;
2242 }
2243
2244 static const uint32_t *
2245 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2246 {
2247         static const uint32_t ptypes[] = {
2248                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2249                 RTE_PTYPE_L2_ETHER,
2250                 RTE_PTYPE_L3_IPV4,
2251                 RTE_PTYPE_L3_IPV4_EXT,
2252                 RTE_PTYPE_L3_IPV6,
2253                 RTE_PTYPE_L3_IPV6_EXT,
2254                 RTE_PTYPE_L4_TCP,
2255                 RTE_PTYPE_L4_UDP,
2256                 RTE_PTYPE_L4_SCTP,
2257                 RTE_PTYPE_TUNNEL_IP,
2258                 RTE_PTYPE_INNER_L3_IPV6,
2259                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2260                 RTE_PTYPE_INNER_L4_TCP,
2261                 RTE_PTYPE_INNER_L4_UDP,
2262                 RTE_PTYPE_UNKNOWN
2263         };
2264
2265         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2266             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2267                 return ptypes;
2268         return NULL;
2269 }
2270
2271 static void
2272 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2273 {
2274         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275
2276         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2277         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2278         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2279         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2280         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2281                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2282                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2283                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2284         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2285                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2286                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2287                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2288                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2289                                 DEV_TX_OFFLOAD_TCP_TSO;
2290         switch (hw->mac.type) {
2291         case e1000_vfadapt:
2292                 dev_info->max_rx_queues = 2;
2293                 dev_info->max_tx_queues = 2;
2294                 break;
2295         case e1000_vfadapt_i350:
2296                 dev_info->max_rx_queues = 1;
2297                 dev_info->max_tx_queues = 1;
2298                 break;
2299         default:
2300                 /* Should not happen */
2301                 break;
2302         }
2303
2304         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2305                 .rx_thresh = {
2306                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2307                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2308                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2309                 },
2310                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2311                 .rx_drop_en = 0,
2312         };
2313
2314         dev_info->default_txconf = (struct rte_eth_txconf) {
2315                 .tx_thresh = {
2316                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2317                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2318                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2319                 },
2320                 .txq_flags = 0,
2321         };
2322
2323         dev_info->rx_desc_lim = rx_desc_lim;
2324         dev_info->tx_desc_lim = tx_desc_lim;
2325 }
2326
2327 /* return 0 means link status changed, -1 means not changed */
2328 static int
2329 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2330 {
2331         struct e1000_hw *hw =
2332                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333         struct rte_eth_link link;
2334         int link_check, count;
2335
2336         link_check = 0;
2337         hw->mac.get_link_status = 1;
2338
2339         /* possible wait-to-complete in up to 9 seconds */
2340         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2341                 /* Read the real link status */
2342                 switch (hw->phy.media_type) {
2343                 case e1000_media_type_copper:
2344                         /* Do the work to read phy */
2345                         e1000_check_for_link(hw);
2346                         link_check = !hw->mac.get_link_status;
2347                         break;
2348
2349                 case e1000_media_type_fiber:
2350                         e1000_check_for_link(hw);
2351                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2352                                       E1000_STATUS_LU);
2353                         break;
2354
2355                 case e1000_media_type_internal_serdes:
2356                         e1000_check_for_link(hw);
2357                         link_check = hw->mac.serdes_has_link;
2358                         break;
2359
2360                 /* VF device is type_unknown */
2361                 case e1000_media_type_unknown:
2362                         eth_igbvf_link_update(hw);
2363                         link_check = !hw->mac.get_link_status;
2364                         break;
2365
2366                 default:
2367                         break;
2368                 }
2369                 if (link_check || wait_to_complete == 0)
2370                         break;
2371                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2372         }
2373         memset(&link, 0, sizeof(link));
2374
2375         /* Now we check if a transition has happened */
2376         if (link_check) {
2377                 uint16_t duplex, speed;
2378                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2379                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2380                                 ETH_LINK_FULL_DUPLEX :
2381                                 ETH_LINK_HALF_DUPLEX;
2382                 link.link_speed = speed;
2383                 link.link_status = ETH_LINK_UP;
2384                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2385                                 ETH_LINK_SPEED_FIXED);
2386         } else if (!link_check) {
2387                 link.link_speed = 0;
2388                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2389                 link.link_status = ETH_LINK_DOWN;
2390                 link.link_autoneg = ETH_LINK_FIXED;
2391         }
2392
2393         return rte_eth_linkstatus_set(dev, &link);
2394 }
2395
2396 /*
2397  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2398  * For ASF and Pass Through versions of f/w this means
2399  * that the driver is loaded.
2400  */
2401 static void
2402 igb_hw_control_acquire(struct e1000_hw *hw)
2403 {
2404         uint32_t ctrl_ext;
2405
2406         /* Let firmware know the driver has taken over */
2407         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2408         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2409 }
2410
2411 /*
2412  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2413  * For ASF and Pass Through versions of f/w this means that the
2414  * driver is no longer loaded.
2415  */
2416 static void
2417 igb_hw_control_release(struct e1000_hw *hw)
2418 {
2419         uint32_t ctrl_ext;
2420
2421         /* Let firmware taken over control of h/w */
2422         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2423         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2424                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2425 }
2426
2427 /*
2428  * Bit of a misnomer, what this really means is
2429  * to enable OS management of the system... aka
2430  * to disable special hardware management features.
2431  */
2432 static void
2433 igb_init_manageability(struct e1000_hw *hw)
2434 {
2435         if (e1000_enable_mng_pass_thru(hw)) {
2436                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2437                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2438
2439                 /* disable hardware interception of ARP */
2440                 manc &= ~(E1000_MANC_ARP_EN);
2441
2442                 /* enable receiving management packets to the host */
2443                 manc |= E1000_MANC_EN_MNG2HOST;
2444                 manc2h |= 1 << 5;  /* Mng Port 623 */
2445                 manc2h |= 1 << 6;  /* Mng Port 664 */
2446                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2447                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2448         }
2449 }
2450
2451 static void
2452 igb_release_manageability(struct e1000_hw *hw)
2453 {
2454         if (e1000_enable_mng_pass_thru(hw)) {
2455                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2456
2457                 manc |= E1000_MANC_ARP_EN;
2458                 manc &= ~E1000_MANC_EN_MNG2HOST;
2459
2460                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2461         }
2462 }
2463
2464 static void
2465 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2466 {
2467         struct e1000_hw *hw =
2468                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         uint32_t rctl;
2470
2471         rctl = E1000_READ_REG(hw, E1000_RCTL);
2472         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2473         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2474 }
2475
2476 static void
2477 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2478 {
2479         struct e1000_hw *hw =
2480                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         uint32_t rctl;
2482
2483         rctl = E1000_READ_REG(hw, E1000_RCTL);
2484         rctl &= (~E1000_RCTL_UPE);
2485         if (dev->data->all_multicast == 1)
2486                 rctl |= E1000_RCTL_MPE;
2487         else
2488                 rctl &= (~E1000_RCTL_MPE);
2489         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2490 }
2491
2492 static void
2493 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2494 {
2495         struct e1000_hw *hw =
2496                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497         uint32_t rctl;
2498
2499         rctl = E1000_READ_REG(hw, E1000_RCTL);
2500         rctl |= E1000_RCTL_MPE;
2501         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2502 }
2503
2504 static void
2505 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2506 {
2507         struct e1000_hw *hw =
2508                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509         uint32_t rctl;
2510
2511         if (dev->data->promiscuous == 1)
2512                 return; /* must remain in all_multicast mode */
2513         rctl = E1000_READ_REG(hw, E1000_RCTL);
2514         rctl &= (~E1000_RCTL_MPE);
2515         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2516 }
2517
2518 static int
2519 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct e1000_vfta * shadow_vfta =
2524                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2525         uint32_t vfta;
2526         uint32_t vid_idx;
2527         uint32_t vid_bit;
2528
2529         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2530                               E1000_VFTA_ENTRY_MASK);
2531         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2532         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2533         if (on)
2534                 vfta |= vid_bit;
2535         else
2536                 vfta &= ~vid_bit;
2537         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2538
2539         /* update local VFTA copy */
2540         shadow_vfta->vfta[vid_idx] = vfta;
2541
2542         return 0;
2543 }
2544
2545 static int
2546 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2547                       enum rte_vlan_type vlan_type,
2548                       uint16_t tpid)
2549 {
2550         struct e1000_hw *hw =
2551                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         uint32_t reg, qinq;
2553
2554         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2555         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2556
2557         /* only outer TPID of double VLAN can be configured*/
2558         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2559                 reg = E1000_READ_REG(hw, E1000_VET);
2560                 reg = (reg & (~E1000_VET_VET_EXT)) |
2561                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2562                 E1000_WRITE_REG(hw, E1000_VET, reg);
2563
2564                 return 0;
2565         }
2566
2567         /* all other TPID values are read-only*/
2568         PMD_DRV_LOG(ERR, "Not supported");
2569
2570         return -ENOTSUP;
2571 }
2572
2573 static void
2574 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2575 {
2576         struct e1000_hw *hw =
2577                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         uint32_t reg;
2579
2580         /* Filter Table Disable */
2581         reg = E1000_READ_REG(hw, E1000_RCTL);
2582         reg &= ~E1000_RCTL_CFIEN;
2583         reg &= ~E1000_RCTL_VFE;
2584         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2585 }
2586
2587 static void
2588 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2589 {
2590         struct e1000_hw *hw =
2591                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2592         struct e1000_vfta * shadow_vfta =
2593                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2594         uint32_t reg;
2595         int i;
2596
2597         /* Filter Table Enable, CFI not used for packet acceptance */
2598         reg = E1000_READ_REG(hw, E1000_RCTL);
2599         reg &= ~E1000_RCTL_CFIEN;
2600         reg |= E1000_RCTL_VFE;
2601         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2602
2603         /* restore VFTA table */
2604         for (i = 0; i < IGB_VFTA_SIZE; i++)
2605                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2606 }
2607
2608 static void
2609 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2610 {
2611         struct e1000_hw *hw =
2612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613         uint32_t reg;
2614
2615         /* VLAN Mode Disable */
2616         reg = E1000_READ_REG(hw, E1000_CTRL);
2617         reg &= ~E1000_CTRL_VME;
2618         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2619 }
2620
2621 static void
2622 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2623 {
2624         struct e1000_hw *hw =
2625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626         uint32_t reg;
2627
2628         /* VLAN Mode Enable */
2629         reg = E1000_READ_REG(hw, E1000_CTRL);
2630         reg |= E1000_CTRL_VME;
2631         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2632 }
2633
2634 static void
2635 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2636 {
2637         struct e1000_hw *hw =
2638                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         uint32_t reg;
2640
2641         /* CTRL_EXT: Extended VLAN */
2642         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2643         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2644         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2645
2646         /* Update maximum packet length */
2647         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2648                 E1000_WRITE_REG(hw, E1000_RLPML,
2649                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2650                                                 VLAN_TAG_SIZE);
2651 }
2652
2653 static void
2654 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2655 {
2656         struct e1000_hw *hw =
2657                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658         uint32_t reg;
2659
2660         /* CTRL_EXT: Extended VLAN */
2661         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2662         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2663         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2664
2665         /* Update maximum packet length */
2666         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2667                 E1000_WRITE_REG(hw, E1000_RLPML,
2668                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2669                                                 2 * VLAN_TAG_SIZE);
2670 }
2671
2672 static int
2673 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2674 {
2675         if(mask & ETH_VLAN_STRIP_MASK){
2676                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2677                         igb_vlan_hw_strip_enable(dev);
2678                 else
2679                         igb_vlan_hw_strip_disable(dev);
2680         }
2681
2682         if(mask & ETH_VLAN_FILTER_MASK){
2683                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2684                         igb_vlan_hw_filter_enable(dev);
2685                 else
2686                         igb_vlan_hw_filter_disable(dev);
2687         }
2688
2689         if(mask & ETH_VLAN_EXTEND_MASK){
2690                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2691                         igb_vlan_hw_extend_enable(dev);
2692                 else
2693                         igb_vlan_hw_extend_disable(dev);
2694         }
2695
2696         return 0;
2697 }
2698
2699
2700 /**
2701  * It enables the interrupt mask and then enable the interrupt.
2702  *
2703  * @param dev
2704  *  Pointer to struct rte_eth_dev.
2705  * @param on
2706  *  Enable or Disable
2707  *
2708  * @return
2709  *  - On success, zero.
2710  *  - On failure, a negative value.
2711  */
2712 static int
2713 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2714 {
2715         struct e1000_interrupt *intr =
2716                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2717
2718         if (on)
2719                 intr->mask |= E1000_ICR_LSC;
2720         else
2721                 intr->mask &= ~E1000_ICR_LSC;
2722
2723         return 0;
2724 }
2725
2726 /* It clears the interrupt causes and enables the interrupt.
2727  * It will be called once only during nic initialized.
2728  *
2729  * @param dev
2730  *  Pointer to struct rte_eth_dev.
2731  *
2732  * @return
2733  *  - On success, zero.
2734  *  - On failure, a negative value.
2735  */
2736 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2737 {
2738         uint32_t mask, regval;
2739         struct e1000_hw *hw =
2740                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741         struct rte_eth_dev_info dev_info;
2742
2743         memset(&dev_info, 0, sizeof(dev_info));
2744         eth_igb_infos_get(dev, &dev_info);
2745
2746         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2747         regval = E1000_READ_REG(hw, E1000_EIMS);
2748         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2749
2750         return 0;
2751 }
2752
2753 /*
2754  * It reads ICR and gets interrupt causes, check it and set a bit flag
2755  * to update link status.
2756  *
2757  * @param dev
2758  *  Pointer to struct rte_eth_dev.
2759  *
2760  * @return
2761  *  - On success, zero.
2762  *  - On failure, a negative value.
2763  */
2764 static int
2765 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2766 {
2767         uint32_t icr;
2768         struct e1000_hw *hw =
2769                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         struct e1000_interrupt *intr =
2771                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2772
2773         igb_intr_disable(hw);
2774
2775         /* read-on-clear nic registers here */
2776         icr = E1000_READ_REG(hw, E1000_ICR);
2777
2778         intr->flags = 0;
2779         if (icr & E1000_ICR_LSC) {
2780                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2781         }
2782
2783         if (icr & E1000_ICR_VMMB)
2784                 intr->flags |= E1000_FLAG_MAILBOX;
2785
2786         return 0;
2787 }
2788
2789 /*
2790  * It executes link_update after knowing an interrupt is prsent.
2791  *
2792  * @param dev
2793  *  Pointer to struct rte_eth_dev.
2794  *
2795  * @return
2796  *  - On success, zero.
2797  *  - On failure, a negative value.
2798  */
2799 static int
2800 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2801                          struct rte_intr_handle *intr_handle)
2802 {
2803         struct e1000_hw *hw =
2804                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2805         struct e1000_interrupt *intr =
2806                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2807         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2808         struct rte_eth_link link;
2809         int ret;
2810
2811         if (intr->flags & E1000_FLAG_MAILBOX) {
2812                 igb_pf_mbx_process(dev);
2813                 intr->flags &= ~E1000_FLAG_MAILBOX;
2814         }
2815
2816         igb_intr_enable(dev);
2817         rte_intr_enable(intr_handle);
2818
2819         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2820                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2821
2822                 /* set get_link_status to check register later */
2823                 hw->mac.get_link_status = 1;
2824                 ret = eth_igb_link_update(dev, 0);
2825
2826                 /* check if link has changed */
2827                 if (ret < 0)
2828                         return 0;
2829
2830                 rte_eth_linkstatus_get(dev, &link);
2831                 if (link.link_status) {
2832                         PMD_INIT_LOG(INFO,
2833                                      " Port %d: Link Up - speed %u Mbps - %s",
2834                                      dev->data->port_id,
2835                                      (unsigned)link.link_speed,
2836                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2837                                      "full-duplex" : "half-duplex");
2838                 } else {
2839                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2840                                      dev->data->port_id);
2841                 }
2842
2843                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2844                              pci_dev->addr.domain,
2845                              pci_dev->addr.bus,
2846                              pci_dev->addr.devid,
2847                              pci_dev->addr.function);
2848                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2849                                               NULL);
2850         }
2851
2852         return 0;
2853 }
2854
2855 /**
2856  * Interrupt handler which shall be registered at first.
2857  *
2858  * @param handle
2859  *  Pointer to interrupt handle.
2860  * @param param
2861  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2862  *
2863  * @return
2864  *  void
2865  */
2866 static void
2867 eth_igb_interrupt_handler(void *param)
2868 {
2869         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2870
2871         eth_igb_interrupt_get_status(dev);
2872         eth_igb_interrupt_action(dev, dev->intr_handle);
2873 }
2874
2875 static int
2876 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2877 {
2878         uint32_t eicr;
2879         struct e1000_hw *hw =
2880                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2881         struct e1000_interrupt *intr =
2882                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2883
2884         igbvf_intr_disable(hw);
2885
2886         /* read-on-clear nic registers here */
2887         eicr = E1000_READ_REG(hw, E1000_EICR);
2888         intr->flags = 0;
2889
2890         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2891                 intr->flags |= E1000_FLAG_MAILBOX;
2892
2893         return 0;
2894 }
2895
2896 void igbvf_mbx_process(struct rte_eth_dev *dev)
2897 {
2898         struct e1000_hw *hw =
2899                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900         struct e1000_mbx_info *mbx = &hw->mbx;
2901         u32 in_msg = 0;
2902
2903         /* peek the message first */
2904         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2905
2906         /* PF reset VF event */
2907         if (in_msg == E1000_PF_CONTROL_MSG) {
2908                 /* dummy mbx read to ack pf */
2909                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2910                         return;
2911                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2912                                               NULL);
2913         }
2914 }
2915
2916 static int
2917 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2918 {
2919         struct e1000_interrupt *intr =
2920                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2921
2922         if (intr->flags & E1000_FLAG_MAILBOX) {
2923                 igbvf_mbx_process(dev);
2924                 intr->flags &= ~E1000_FLAG_MAILBOX;
2925         }
2926
2927         igbvf_intr_enable(dev);
2928         rte_intr_enable(intr_handle);
2929
2930         return 0;
2931 }
2932
2933 static void
2934 eth_igbvf_interrupt_handler(void *param)
2935 {
2936         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2937
2938         eth_igbvf_interrupt_get_status(dev);
2939         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2940 }
2941
2942 static int
2943 eth_igb_led_on(struct rte_eth_dev *dev)
2944 {
2945         struct e1000_hw *hw;
2946
2947         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2949 }
2950
2951 static int
2952 eth_igb_led_off(struct rte_eth_dev *dev)
2953 {
2954         struct e1000_hw *hw;
2955
2956         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2958 }
2959
2960 static int
2961 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2962 {
2963         struct e1000_hw *hw;
2964         uint32_t ctrl;
2965         int tx_pause;
2966         int rx_pause;
2967
2968         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2969         fc_conf->pause_time = hw->fc.pause_time;
2970         fc_conf->high_water = hw->fc.high_water;
2971         fc_conf->low_water = hw->fc.low_water;
2972         fc_conf->send_xon = hw->fc.send_xon;
2973         fc_conf->autoneg = hw->mac.autoneg;
2974
2975         /*
2976          * Return rx_pause and tx_pause status according to actual setting of
2977          * the TFCE and RFCE bits in the CTRL register.
2978          */
2979         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2980         if (ctrl & E1000_CTRL_TFCE)
2981                 tx_pause = 1;
2982         else
2983                 tx_pause = 0;
2984
2985         if (ctrl & E1000_CTRL_RFCE)
2986                 rx_pause = 1;
2987         else
2988                 rx_pause = 0;
2989
2990         if (rx_pause && tx_pause)
2991                 fc_conf->mode = RTE_FC_FULL;
2992         else if (rx_pause)
2993                 fc_conf->mode = RTE_FC_RX_PAUSE;
2994         else if (tx_pause)
2995                 fc_conf->mode = RTE_FC_TX_PAUSE;
2996         else
2997                 fc_conf->mode = RTE_FC_NONE;
2998
2999         return 0;
3000 }
3001
3002 static int
3003 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3004 {
3005         struct e1000_hw *hw;
3006         int err;
3007         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3008                 e1000_fc_none,
3009                 e1000_fc_rx_pause,
3010                 e1000_fc_tx_pause,
3011                 e1000_fc_full
3012         };
3013         uint32_t rx_buf_size;
3014         uint32_t max_high_water;
3015         uint32_t rctl;
3016
3017         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3018         if (fc_conf->autoneg != hw->mac.autoneg)
3019                 return -ENOTSUP;
3020         rx_buf_size = igb_get_rx_buffer_size(hw);
3021         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3022
3023         /* At least reserve one Ethernet frame for watermark */
3024         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3025         if ((fc_conf->high_water > max_high_water) ||
3026             (fc_conf->high_water < fc_conf->low_water)) {
3027                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3028                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3029                 return -EINVAL;
3030         }
3031
3032         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3033         hw->fc.pause_time     = fc_conf->pause_time;
3034         hw->fc.high_water     = fc_conf->high_water;
3035         hw->fc.low_water      = fc_conf->low_water;
3036         hw->fc.send_xon       = fc_conf->send_xon;
3037
3038         err = e1000_setup_link_generic(hw);
3039         if (err == E1000_SUCCESS) {
3040
3041                 /* check if we want to forward MAC frames - driver doesn't have native
3042                  * capability to do that, so we'll write the registers ourselves */
3043
3044                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3045
3046                 /* set or clear MFLCN.PMCF bit depending on configuration */
3047                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3048                         rctl |= E1000_RCTL_PMCF;
3049                 else
3050                         rctl &= ~E1000_RCTL_PMCF;
3051
3052                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3053                 E1000_WRITE_FLUSH(hw);
3054
3055                 return 0;
3056         }
3057
3058         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3059         return -EIO;
3060 }
3061
3062 #define E1000_RAH_POOLSEL_SHIFT      (18)
3063 static int
3064 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3065                 uint32_t index, uint32_t pool)
3066 {
3067         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         uint32_t rah;
3069
3070         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3071         rah = E1000_READ_REG(hw, E1000_RAH(index));
3072         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3073         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3074         return 0;
3075 }
3076
3077 static void
3078 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3079 {
3080         uint8_t addr[ETHER_ADDR_LEN];
3081         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3082
3083         memset(addr, 0, sizeof(addr));
3084
3085         e1000_rar_set(hw, addr, index);
3086 }
3087
3088 static void
3089 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3090                                 struct ether_addr *addr)
3091 {
3092         eth_igb_rar_clear(dev, 0);
3093
3094         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3095 }
3096 /*
3097  * Virtual Function operations
3098  */
3099 static void
3100 igbvf_intr_disable(struct e1000_hw *hw)
3101 {
3102         PMD_INIT_FUNC_TRACE();
3103
3104         /* Clear interrupt mask to stop from interrupts being generated */
3105         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3106
3107         E1000_WRITE_FLUSH(hw);
3108 }
3109
3110 static void
3111 igbvf_stop_adapter(struct rte_eth_dev *dev)
3112 {
3113         u32 reg_val;
3114         u16 i;
3115         struct rte_eth_dev_info dev_info;
3116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117
3118         memset(&dev_info, 0, sizeof(dev_info));
3119         eth_igbvf_infos_get(dev, &dev_info);
3120
3121         /* Clear interrupt mask to stop from interrupts being generated */
3122         igbvf_intr_disable(hw);
3123
3124         /* Clear any pending interrupts, flush previous writes */
3125         E1000_READ_REG(hw, E1000_EICR);
3126
3127         /* Disable the transmit unit.  Each queue must be disabled. */
3128         for (i = 0; i < dev_info.max_tx_queues; i++)
3129                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3130
3131         /* Disable the receive unit by stopping each queue */
3132         for (i = 0; i < dev_info.max_rx_queues; i++) {
3133                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3134                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3135                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3136                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3137                         ;
3138         }
3139
3140         /* flush all queues disables */
3141         E1000_WRITE_FLUSH(hw);
3142         msec_delay(2);
3143 }
3144
3145 static int eth_igbvf_link_update(struct e1000_hw *hw)
3146 {
3147         struct e1000_mbx_info *mbx = &hw->mbx;
3148         struct e1000_mac_info *mac = &hw->mac;
3149         int ret_val = E1000_SUCCESS;
3150
3151         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3152
3153         /*
3154          * We only want to run this if there has been a rst asserted.
3155          * in this case that could mean a link change, device reset,
3156          * or a virtual function reset
3157          */
3158
3159         /* If we were hit with a reset or timeout drop the link */
3160         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3161                 mac->get_link_status = TRUE;
3162
3163         if (!mac->get_link_status)
3164                 goto out;
3165
3166         /* if link status is down no point in checking to see if pf is up */
3167         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3168                 goto out;
3169
3170         /* if we passed all the tests above then the link is up and we no
3171          * longer need to check for link */
3172         mac->get_link_status = FALSE;
3173
3174 out:
3175         return ret_val;
3176 }
3177
3178
3179 static int
3180 igbvf_dev_configure(struct rte_eth_dev *dev)
3181 {
3182         struct rte_eth_conf* conf = &dev->data->dev_conf;
3183
3184         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3185                      dev->data->port_id);
3186
3187         /*
3188          * VF has no ability to enable/disable HW CRC
3189          * Keep the persistent behavior the same as Host PF
3190          */
3191 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3192         if (!conf->rxmode.hw_strip_crc) {
3193                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3194                 conf->rxmode.hw_strip_crc = 1;
3195         }
3196 #else
3197         if (conf->rxmode.hw_strip_crc) {
3198                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3199                 conf->rxmode.hw_strip_crc = 0;
3200         }
3201 #endif
3202
3203         return 0;
3204 }
3205
3206 static int
3207 igbvf_dev_start(struct rte_eth_dev *dev)
3208 {
3209         struct e1000_hw *hw =
3210                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211         struct e1000_adapter *adapter =
3212                 E1000_DEV_PRIVATE(dev->data->dev_private);
3213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3214         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3215         int ret;
3216         uint32_t intr_vector = 0;
3217
3218         PMD_INIT_FUNC_TRACE();
3219
3220         hw->mac.ops.reset_hw(hw);
3221         adapter->stopped = 0;
3222
3223         /* Set all vfta */
3224         igbvf_set_vfta_all(dev,1);
3225
3226         eth_igbvf_tx_init(dev);
3227
3228         /* This can fail when allocating mbufs for descriptor rings */
3229         ret = eth_igbvf_rx_init(dev);
3230         if (ret) {
3231                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3232                 igb_dev_clear_queues(dev);
3233                 return ret;
3234         }
3235
3236         /* check and configure queue intr-vector mapping */
3237         if (rte_intr_cap_multiple(intr_handle) &&
3238             dev->data->dev_conf.intr_conf.rxq) {
3239                 intr_vector = dev->data->nb_rx_queues;
3240                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3241                 if (ret)
3242                         return ret;
3243         }
3244
3245         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3246                 intr_handle->intr_vec =
3247                         rte_zmalloc("intr_vec",
3248                                     dev->data->nb_rx_queues * sizeof(int), 0);
3249                 if (!intr_handle->intr_vec) {
3250                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3251                                      " intr_vec", dev->data->nb_rx_queues);
3252                         return -ENOMEM;
3253                 }
3254         }
3255
3256         eth_igbvf_configure_msix_intr(dev);
3257
3258         /* enable uio/vfio intr/eventfd mapping */
3259         rte_intr_enable(intr_handle);
3260
3261         /* resume enabled intr since hw reset */
3262         igbvf_intr_enable(dev);
3263
3264         return 0;
3265 }
3266
3267 static void
3268 igbvf_dev_stop(struct rte_eth_dev *dev)
3269 {
3270         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3271         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3272
3273         PMD_INIT_FUNC_TRACE();
3274
3275         igbvf_stop_adapter(dev);
3276
3277         /*
3278           * Clear what we set, but we still keep shadow_vfta to
3279           * restore after device starts
3280           */
3281         igbvf_set_vfta_all(dev,0);
3282
3283         igb_dev_clear_queues(dev);
3284
3285         /* disable intr eventfd mapping */
3286         rte_intr_disable(intr_handle);
3287
3288         /* Clean datapath event and queue/vec mapping */
3289         rte_intr_efd_disable(intr_handle);
3290         if (intr_handle->intr_vec) {
3291                 rte_free(intr_handle->intr_vec);
3292                 intr_handle->intr_vec = NULL;
3293         }
3294 }
3295
3296 static void
3297 igbvf_dev_close(struct rte_eth_dev *dev)
3298 {
3299         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct e1000_adapter *adapter =
3301                 E1000_DEV_PRIVATE(dev->data->dev_private);
3302         struct ether_addr addr;
3303
3304         PMD_INIT_FUNC_TRACE();
3305
3306         e1000_reset_hw(hw);
3307
3308         igbvf_dev_stop(dev);
3309         adapter->stopped = 1;
3310         igb_dev_free_queues(dev);
3311
3312         /**
3313          * reprogram the RAR with a zero mac address,
3314          * to ensure that the VF traffic goes to the PF
3315          * after stop, close and detach of the VF.
3316          **/
3317
3318         memset(&addr, 0, sizeof(addr));
3319         igbvf_default_mac_addr_set(dev, &addr);
3320 }
3321
3322 static void
3323 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3324 {
3325         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326
3327         /* Set both unicast and multicast promisc */
3328         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3329 }
3330
3331 static void
3332 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3333 {
3334         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335
3336         /* If in allmulticast mode leave multicast promisc */
3337         if (dev->data->all_multicast == 1)
3338                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3339         else
3340                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3341 }
3342
3343 static void
3344 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3345 {
3346         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347
3348         /* In promiscuous mode multicast promisc already set */
3349         if (dev->data->promiscuous == 0)
3350                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3351 }
3352
3353 static void
3354 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3355 {
3356         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3357
3358         /* In promiscuous mode leave multicast promisc enabled */
3359         if (dev->data->promiscuous == 0)
3360                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3361 }
3362
3363 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3364 {
3365         struct e1000_mbx_info *mbx = &hw->mbx;
3366         uint32_t msgbuf[2];
3367         s32 err;
3368
3369         /* After set vlan, vlan strip will also be enabled in igb driver*/
3370         msgbuf[0] = E1000_VF_SET_VLAN;
3371         msgbuf[1] = vid;
3372         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3373         if (on)
3374                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3375
3376         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3377         if (err)
3378                 goto mbx_err;
3379
3380         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3381         if (err)
3382                 goto mbx_err;
3383
3384         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3385         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3386                 err = -EINVAL;
3387
3388 mbx_err:
3389         return err;
3390 }
3391
3392 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3393 {
3394         struct e1000_hw *hw =
3395                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3396         struct e1000_vfta * shadow_vfta =
3397                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3398         int i = 0, j = 0, vfta = 0, mask = 1;
3399
3400         for (i = 0; i < IGB_VFTA_SIZE; i++){
3401                 vfta = shadow_vfta->vfta[i];
3402                 if(vfta){
3403                         mask = 1;
3404                         for (j = 0; j < 32; j++){
3405                                 if(vfta & mask)
3406                                         igbvf_set_vfta(hw,
3407                                                 (uint16_t)((i<<5)+j), on);
3408                                 mask<<=1;
3409                         }
3410                 }
3411         }
3412
3413 }
3414
3415 static int
3416 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3417 {
3418         struct e1000_hw *hw =
3419                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420         struct e1000_vfta * shadow_vfta =
3421                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3422         uint32_t vid_idx = 0;
3423         uint32_t vid_bit = 0;
3424         int ret = 0;
3425
3426         PMD_INIT_FUNC_TRACE();
3427
3428         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3429         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3430         if(ret){
3431                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3432                 return ret;
3433         }
3434         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3435         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3436
3437         /*Save what we set and retore it after device reset*/
3438         if (on)
3439                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3440         else
3441                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3442
3443         return 0;
3444 }
3445
3446 static void
3447 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3448 {
3449         struct e1000_hw *hw =
3450                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451
3452         /* index is not used by rar_set() */
3453         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3454 }
3455
3456
3457 static int
3458 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3459                         struct rte_eth_rss_reta_entry64 *reta_conf,
3460                         uint16_t reta_size)
3461 {
3462         uint8_t i, j, mask;
3463         uint32_t reta, r;
3464         uint16_t idx, shift;
3465         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3466
3467         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3468                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3469                         "(%d) doesn't match the number hardware can supported "
3470                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3471                 return -EINVAL;
3472         }
3473
3474         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3475                 idx = i / RTE_RETA_GROUP_SIZE;
3476                 shift = i % RTE_RETA_GROUP_SIZE;
3477                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3478                                                 IGB_4_BIT_MASK);
3479                 if (!mask)
3480                         continue;
3481                 if (mask == IGB_4_BIT_MASK)
3482                         r = 0;
3483                 else
3484                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3485                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3486                         if (mask & (0x1 << j))
3487                                 reta |= reta_conf[idx].reta[shift + j] <<
3488                                                         (CHAR_BIT * j);
3489                         else
3490                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3491                 }
3492                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int
3499 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3500                        struct rte_eth_rss_reta_entry64 *reta_conf,
3501                        uint16_t reta_size)
3502 {
3503         uint8_t i, j, mask;
3504         uint32_t reta;
3505         uint16_t idx, shift;
3506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507
3508         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3509                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3510                         "(%d) doesn't match the number hardware can supported "
3511                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3512                 return -EINVAL;
3513         }
3514
3515         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3516                 idx = i / RTE_RETA_GROUP_SIZE;
3517                 shift = i % RTE_RETA_GROUP_SIZE;
3518                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3519                                                 IGB_4_BIT_MASK);
3520                 if (!mask)
3521                         continue;
3522                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3523                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3524                         if (mask & (0x1 << j))
3525                                 reta_conf[idx].reta[shift + j] =
3526                                         ((reta >> (CHAR_BIT * j)) &
3527                                                 IGB_8_BIT_MASK);
3528                 }
3529         }
3530
3531         return 0;
3532 }
3533
3534 int
3535 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3536                         struct rte_eth_syn_filter *filter,
3537                         bool add)
3538 {
3539         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         struct e1000_filter_info *filter_info =
3541                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3542         uint32_t synqf, rfctl;
3543
3544         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3545                 return -EINVAL;
3546
3547         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3548
3549         if (add) {
3550                 if (synqf & E1000_SYN_FILTER_ENABLE)
3551                         return -EINVAL;
3552
3553                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3554                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3555
3556                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3557                 if (filter->hig_pri)
3558                         rfctl |= E1000_RFCTL_SYNQFP;
3559                 else
3560                         rfctl &= ~E1000_RFCTL_SYNQFP;
3561
3562                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3563         } else {
3564                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3565                         return -ENOENT;
3566                 synqf = 0;
3567         }
3568
3569         filter_info->syn_info = synqf;
3570         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3571         E1000_WRITE_FLUSH(hw);
3572         return 0;
3573 }
3574
3575 static int
3576 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3577                         struct rte_eth_syn_filter *filter)
3578 {
3579         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3580         uint32_t synqf, rfctl;
3581
3582         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3583         if (synqf & E1000_SYN_FILTER_ENABLE) {
3584                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3585                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3586                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3587                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3588                 return 0;
3589         }
3590
3591         return -ENOENT;
3592 }
3593
3594 static int
3595 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3596                         enum rte_filter_op filter_op,
3597                         void *arg)
3598 {
3599         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3600         int ret;
3601
3602         MAC_TYPE_FILTER_SUP(hw->mac.type);
3603
3604         if (filter_op == RTE_ETH_FILTER_NOP)
3605                 return 0;
3606
3607         if (arg == NULL) {
3608                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3609                             filter_op);
3610                 return -EINVAL;
3611         }
3612
3613         switch (filter_op) {
3614         case RTE_ETH_FILTER_ADD:
3615                 ret = eth_igb_syn_filter_set(dev,
3616                                 (struct rte_eth_syn_filter *)arg,
3617                                 TRUE);
3618                 break;
3619         case RTE_ETH_FILTER_DELETE:
3620                 ret = eth_igb_syn_filter_set(dev,
3621                                 (struct rte_eth_syn_filter *)arg,
3622                                 FALSE);
3623                 break;
3624         case RTE_ETH_FILTER_GET:
3625                 ret = eth_igb_syn_filter_get(dev,
3626                                 (struct rte_eth_syn_filter *)arg);
3627                 break;
3628         default:
3629                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3630                 ret = -EINVAL;
3631                 break;
3632         }
3633
3634         return ret;
3635 }
3636
3637 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3638 static inline int
3639 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3640                         struct e1000_2tuple_filter_info *filter_info)
3641 {
3642         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3643                 return -EINVAL;
3644         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3645                 return -EINVAL;  /* filter index is out of range. */
3646         if (filter->tcp_flags > TCP_FLAG_ALL)
3647                 return -EINVAL;  /* flags is invalid. */
3648
3649         switch (filter->dst_port_mask) {
3650         case UINT16_MAX:
3651                 filter_info->dst_port_mask = 0;
3652                 filter_info->dst_port = filter->dst_port;
3653                 break;
3654         case 0:
3655                 filter_info->dst_port_mask = 1;
3656                 break;
3657         default:
3658                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3659                 return -EINVAL;
3660         }
3661
3662         switch (filter->proto_mask) {
3663         case UINT8_MAX:
3664                 filter_info->proto_mask = 0;
3665                 filter_info->proto = filter->proto;
3666                 break;
3667         case 0:
3668                 filter_info->proto_mask = 1;
3669                 break;
3670         default:
3671                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3672                 return -EINVAL;
3673         }
3674
3675         filter_info->priority = (uint8_t)filter->priority;
3676         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3677                 filter_info->tcp_flags = filter->tcp_flags;
3678         else
3679                 filter_info->tcp_flags = 0;
3680
3681         return 0;
3682 }
3683
3684 static inline struct e1000_2tuple_filter *
3685 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3686                         struct e1000_2tuple_filter_info *key)
3687 {
3688         struct e1000_2tuple_filter *it;
3689
3690         TAILQ_FOREACH(it, filter_list, entries) {
3691                 if (memcmp(key, &it->filter_info,
3692                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3693                         return it;
3694                 }
3695         }
3696         return NULL;
3697 }
3698
3699 /* inject a igb 2tuple filter to HW */
3700 static inline void
3701 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3702                            struct e1000_2tuple_filter *filter)
3703 {
3704         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3706         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3707         int i;
3708
3709         i = filter->index;
3710         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3711         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3712                 imir |= E1000_IMIR_PORT_BP;
3713         else
3714                 imir &= ~E1000_IMIR_PORT_BP;
3715
3716         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3717
3718         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3719         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3720         ttqf |= (uint32_t)(filter->filter_info.proto &
3721                                                 E1000_TTQF_PROTOCOL_MASK);
3722         if (filter->filter_info.proto_mask == 0)
3723                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3724
3725         /* tcp flags bits setting. */
3726         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3727                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3728                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3729                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3730                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3731                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3732                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3733                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3734                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3735                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3736                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3737                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3738                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3739         } else {
3740                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3741         }
3742         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3743         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3744         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3745 }
3746
3747 /*
3748  * igb_add_2tuple_filter - add a 2tuple filter
3749  *
3750  * @param
3751  * dev: Pointer to struct rte_eth_dev.
3752  * ntuple_filter: ponter to the filter that will be added.
3753  *
3754  * @return
3755  *    - On success, zero.
3756  *    - On failure, a negative value.
3757  */
3758 static int
3759 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3760                         struct rte_eth_ntuple_filter *ntuple_filter)
3761 {
3762         struct e1000_filter_info *filter_info =
3763                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3764         struct e1000_2tuple_filter *filter;
3765         int i, ret;
3766
3767         filter = rte_zmalloc("e1000_2tuple_filter",
3768                         sizeof(struct e1000_2tuple_filter), 0);
3769         if (filter == NULL)
3770                 return -ENOMEM;
3771
3772         ret = ntuple_filter_to_2tuple(ntuple_filter,
3773                                       &filter->filter_info);
3774         if (ret < 0) {
3775                 rte_free(filter);
3776                 return ret;
3777         }
3778         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3779                                          &filter->filter_info) != NULL) {
3780                 PMD_DRV_LOG(ERR, "filter exists.");
3781                 rte_free(filter);
3782                 return -EEXIST;
3783         }
3784         filter->queue = ntuple_filter->queue;
3785
3786         /*
3787          * look for an unused 2tuple filter index,
3788          * and insert the filter to list.
3789          */
3790         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3791                 if (!(filter_info->twotuple_mask & (1 << i))) {
3792                         filter_info->twotuple_mask |= 1 << i;
3793                         filter->index = i;
3794                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3795                                           filter,
3796                                           entries);
3797                         break;
3798                 }
3799         }
3800         if (i >= E1000_MAX_TTQF_FILTERS) {
3801                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3802                 rte_free(filter);
3803                 return -ENOSYS;
3804         }
3805
3806         igb_inject_2uple_filter(dev, filter);
3807         return 0;
3808 }
3809
3810 int
3811 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3812                         struct e1000_2tuple_filter *filter)
3813 {
3814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         struct e1000_filter_info *filter_info =
3816                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3817
3818         filter_info->twotuple_mask &= ~(1 << filter->index);
3819         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3820         rte_free(filter);
3821
3822         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3823         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3824         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3825         return 0;
3826 }
3827
3828 /*
3829  * igb_remove_2tuple_filter - remove a 2tuple filter
3830  *
3831  * @param
3832  * dev: Pointer to struct rte_eth_dev.
3833  * ntuple_filter: ponter to the filter that will be removed.
3834  *
3835  * @return
3836  *    - On success, zero.
3837  *    - On failure, a negative value.
3838  */
3839 static int
3840 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3841                         struct rte_eth_ntuple_filter *ntuple_filter)
3842 {
3843         struct e1000_filter_info *filter_info =
3844                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3845         struct e1000_2tuple_filter_info filter_2tuple;
3846         struct e1000_2tuple_filter *filter;
3847         int ret;
3848
3849         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3850         ret = ntuple_filter_to_2tuple(ntuple_filter,
3851                                       &filter_2tuple);
3852         if (ret < 0)
3853                 return ret;
3854
3855         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3856                                          &filter_2tuple);
3857         if (filter == NULL) {
3858                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3859                 return -ENOENT;
3860         }
3861
3862         igb_delete_2tuple_filter(dev, filter);
3863
3864         return 0;
3865 }
3866
3867 /* inject a igb flex filter to HW */
3868 static inline void
3869 igb_inject_flex_filter(struct rte_eth_dev *dev,
3870                            struct e1000_flex_filter *filter)
3871 {
3872         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873         uint32_t wufc, queueing;
3874         uint32_t reg_off;
3875         uint8_t i, j = 0;
3876
3877         wufc = E1000_READ_REG(hw, E1000_WUFC);
3878         if (filter->index < E1000_MAX_FHFT)
3879                 reg_off = E1000_FHFT(filter->index);
3880         else
3881                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3882
3883         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3884                         (E1000_WUFC_FLX0 << filter->index));
3885         queueing = filter->filter_info.len |
3886                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3887                 (filter->filter_info.priority <<
3888                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3889         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3890                         queueing);
3891
3892         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3893                 E1000_WRITE_REG(hw, reg_off,
3894                                 filter->filter_info.dwords[j]);
3895                 reg_off += sizeof(uint32_t);
3896                 E1000_WRITE_REG(hw, reg_off,
3897                                 filter->filter_info.dwords[++j]);
3898                 reg_off += sizeof(uint32_t);
3899                 E1000_WRITE_REG(hw, reg_off,
3900                         (uint32_t)filter->filter_info.mask[i]);
3901                 reg_off += sizeof(uint32_t) * 2;
3902                 ++j;
3903         }
3904 }
3905
3906 static inline struct e1000_flex_filter *
3907 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3908                         struct e1000_flex_filter_info *key)
3909 {
3910         struct e1000_flex_filter *it;
3911
3912         TAILQ_FOREACH(it, filter_list, entries) {
3913                 if (memcmp(key, &it->filter_info,
3914                         sizeof(struct e1000_flex_filter_info)) == 0)
3915                         return it;
3916         }
3917
3918         return NULL;
3919 }
3920
3921 /* remove a flex byte filter
3922  * @param
3923  * dev: Pointer to struct rte_eth_dev.
3924  * filter: the pointer of the filter will be removed.
3925  */
3926 void
3927 igb_remove_flex_filter(struct rte_eth_dev *dev,
3928                         struct e1000_flex_filter *filter)
3929 {
3930         struct e1000_filter_info *filter_info =
3931                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3932         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         uint32_t wufc, i;
3934         uint32_t reg_off;
3935
3936         wufc = E1000_READ_REG(hw, E1000_WUFC);
3937         if (filter->index < E1000_MAX_FHFT)
3938                 reg_off = E1000_FHFT(filter->index);
3939         else
3940                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3941
3942         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3943                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3944
3945         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3946                 (~(E1000_WUFC_FLX0 << filter->index)));
3947
3948         filter_info->flex_mask &= ~(1 << filter->index);
3949         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3950         rte_free(filter);
3951 }
3952
3953 int
3954 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3955                         struct rte_eth_flex_filter *filter,
3956                         bool add)
3957 {
3958         struct e1000_filter_info *filter_info =
3959                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3960         struct e1000_flex_filter *flex_filter, *it;
3961         uint32_t mask;
3962         uint8_t shift, i;
3963
3964         flex_filter = rte_zmalloc("e1000_flex_filter",
3965                         sizeof(struct e1000_flex_filter), 0);
3966         if (flex_filter == NULL)
3967                 return -ENOMEM;
3968
3969         flex_filter->filter_info.len = filter->len;
3970         flex_filter->filter_info.priority = filter->priority;
3971         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3972         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3973                 mask = 0;
3974                 /* reverse bits in flex filter's mask*/
3975                 for (shift = 0; shift < CHAR_BIT; shift++) {
3976                         if (filter->mask[i] & (0x01 << shift))
3977                                 mask |= (0x80 >> shift);
3978                 }
3979                 flex_filter->filter_info.mask[i] = mask;
3980         }
3981
3982         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3983                                 &flex_filter->filter_info);
3984         if (it == NULL && !add) {
3985                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3986                 rte_free(flex_filter);
3987                 return -ENOENT;
3988         }
3989         if (it != NULL && add) {
3990                 PMD_DRV_LOG(ERR, "filter exists.");
3991                 rte_free(flex_filter);
3992                 return -EEXIST;
3993         }
3994
3995         if (add) {
3996                 flex_filter->queue = filter->queue;
3997                 /*
3998                  * look for an unused flex filter index
3999                  * and insert the filter into the list.
4000                  */
4001                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4002                         if (!(filter_info->flex_mask & (1 << i))) {
4003                                 filter_info->flex_mask |= 1 << i;
4004                                 flex_filter->index = i;
4005                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4006                                         flex_filter,
4007                                         entries);
4008                                 break;
4009                         }
4010                 }
4011                 if (i >= E1000_MAX_FLEX_FILTERS) {
4012                         PMD_DRV_LOG(ERR, "flex filters are full.");
4013                         rte_free(flex_filter);
4014                         return -ENOSYS;
4015                 }
4016
4017                 igb_inject_flex_filter(dev, flex_filter);
4018
4019         } else {
4020                 igb_remove_flex_filter(dev, it);
4021                 rte_free(flex_filter);
4022         }
4023
4024         return 0;
4025 }
4026
4027 static int
4028 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4029                         struct rte_eth_flex_filter *filter)
4030 {
4031         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032         struct e1000_filter_info *filter_info =
4033                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4034         struct e1000_flex_filter flex_filter, *it;
4035         uint32_t wufc, queueing, wufc_en = 0;
4036
4037         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4038         flex_filter.filter_info.len = filter->len;
4039         flex_filter.filter_info.priority = filter->priority;
4040         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4041         memcpy(flex_filter.filter_info.mask, filter->mask,
4042                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4043
4044         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4045                                 &flex_filter.filter_info);
4046         if (it == NULL) {
4047                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4048                 return -ENOENT;
4049         }
4050
4051         wufc = E1000_READ_REG(hw, E1000_WUFC);
4052         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4053
4054         if ((wufc & wufc_en) == wufc_en) {
4055                 uint32_t reg_off = 0;
4056                 if (it->index < E1000_MAX_FHFT)
4057                         reg_off = E1000_FHFT(it->index);
4058                 else
4059                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4060
4061                 queueing = E1000_READ_REG(hw,
4062                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4063                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4064                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4065                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4066                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4067                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4068                 return 0;
4069         }
4070         return -ENOENT;
4071 }
4072
4073 static int
4074 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4075                         enum rte_filter_op filter_op,
4076                         void *arg)
4077 {
4078         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         struct rte_eth_flex_filter *filter;
4080         int ret = 0;
4081
4082         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4083
4084         if (filter_op == RTE_ETH_FILTER_NOP)
4085                 return ret;
4086
4087         if (arg == NULL) {
4088                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4089                             filter_op);
4090                 return -EINVAL;
4091         }
4092
4093         filter = (struct rte_eth_flex_filter *)arg;
4094         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4095             || filter->len % sizeof(uint64_t) != 0) {
4096                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4097                 return -EINVAL;
4098         }
4099         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4100                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4101                 return -EINVAL;
4102         }
4103
4104         switch (filter_op) {
4105         case RTE_ETH_FILTER_ADD:
4106                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4107                 break;
4108         case RTE_ETH_FILTER_DELETE:
4109                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4110                 break;
4111         case RTE_ETH_FILTER_GET:
4112                 ret = eth_igb_get_flex_filter(dev, filter);
4113                 break;
4114         default:
4115                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4116                 ret = -EINVAL;
4117                 break;
4118         }
4119
4120         return ret;
4121 }
4122
4123 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4124 static inline int
4125 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4126                         struct e1000_5tuple_filter_info *filter_info)
4127 {
4128         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4129                 return -EINVAL;
4130         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4131                 return -EINVAL;  /* filter index is out of range. */
4132         if (filter->tcp_flags > TCP_FLAG_ALL)
4133                 return -EINVAL;  /* flags is invalid. */
4134
4135         switch (filter->dst_ip_mask) {
4136         case UINT32_MAX:
4137                 filter_info->dst_ip_mask = 0;
4138                 filter_info->dst_ip = filter->dst_ip;
4139                 break;
4140         case 0:
4141                 filter_info->dst_ip_mask = 1;
4142                 break;
4143         default:
4144                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4145                 return -EINVAL;
4146         }
4147
4148         switch (filter->src_ip_mask) {
4149         case UINT32_MAX:
4150                 filter_info->src_ip_mask = 0;
4151                 filter_info->src_ip = filter->src_ip;
4152                 break;
4153         case 0:
4154                 filter_info->src_ip_mask = 1;
4155                 break;
4156         default:
4157                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4158                 return -EINVAL;
4159         }
4160
4161         switch (filter->dst_port_mask) {
4162         case UINT16_MAX:
4163                 filter_info->dst_port_mask = 0;
4164                 filter_info->dst_port = filter->dst_port;
4165                 break;
4166         case 0:
4167                 filter_info->dst_port_mask = 1;
4168                 break;
4169         default:
4170                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4171                 return -EINVAL;
4172         }
4173
4174         switch (filter->src_port_mask) {
4175         case UINT16_MAX:
4176                 filter_info->src_port_mask = 0;
4177                 filter_info->src_port = filter->src_port;
4178                 break;
4179         case 0:
4180                 filter_info->src_port_mask = 1;
4181                 break;
4182         default:
4183                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4184                 return -EINVAL;
4185         }
4186
4187         switch (filter->proto_mask) {
4188         case UINT8_MAX:
4189                 filter_info->proto_mask = 0;
4190                 filter_info->proto = filter->proto;
4191                 break;
4192         case 0:
4193                 filter_info->proto_mask = 1;
4194                 break;
4195         default:
4196                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4197                 return -EINVAL;
4198         }
4199
4200         filter_info->priority = (uint8_t)filter->priority;
4201         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4202                 filter_info->tcp_flags = filter->tcp_flags;
4203         else
4204                 filter_info->tcp_flags = 0;
4205
4206         return 0;
4207 }
4208
4209 static inline struct e1000_5tuple_filter *
4210 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4211                         struct e1000_5tuple_filter_info *key)
4212 {
4213         struct e1000_5tuple_filter *it;
4214
4215         TAILQ_FOREACH(it, filter_list, entries) {
4216                 if (memcmp(key, &it->filter_info,
4217                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4218                         return it;
4219                 }
4220         }
4221         return NULL;
4222 }
4223
4224 /* inject a igb 5-tuple filter to HW */
4225 static inline void
4226 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4227                            struct e1000_5tuple_filter *filter)
4228 {
4229         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4230         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4231         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4232         uint8_t i;
4233
4234         i = filter->index;
4235         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4236         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4237                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4238         if (filter->filter_info.dst_ip_mask == 0)
4239                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4240         if (filter->filter_info.src_port_mask == 0)
4241                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4242         if (filter->filter_info.proto_mask == 0)
4243                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4244         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4245                 E1000_FTQF_QUEUE_MASK;
4246         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4247         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4248         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4249         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4250
4251         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4252         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4253
4254         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4255         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4256                 imir |= E1000_IMIR_PORT_BP;
4257         else
4258                 imir &= ~E1000_IMIR_PORT_BP;
4259         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4260
4261         /* tcp flags bits setting. */
4262         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4263                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4264                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4265                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4266                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4267                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4268                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4269                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4270                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4271                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4272                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4273                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4274                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4275         } else {
4276                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4277         }
4278         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4279         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4280 }
4281
4282 /*
4283  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4284  *
4285  * @param
4286  * dev: Pointer to struct rte_eth_dev.
4287  * ntuple_filter: ponter to the filter that will be added.
4288  *
4289  * @return
4290  *    - On success, zero.
4291  *    - On failure, a negative value.
4292  */
4293 static int
4294 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4295                         struct rte_eth_ntuple_filter *ntuple_filter)
4296 {
4297         struct e1000_filter_info *filter_info =
4298                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4299         struct e1000_5tuple_filter *filter;
4300         uint8_t i;
4301         int ret;
4302
4303         filter = rte_zmalloc("e1000_5tuple_filter",
4304                         sizeof(struct e1000_5tuple_filter), 0);
4305         if (filter == NULL)
4306                 return -ENOMEM;
4307
4308         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4309                                             &filter->filter_info);
4310         if (ret < 0) {
4311                 rte_free(filter);
4312                 return ret;
4313         }
4314
4315         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4316                                          &filter->filter_info) != NULL) {
4317                 PMD_DRV_LOG(ERR, "filter exists.");
4318                 rte_free(filter);
4319                 return -EEXIST;
4320         }
4321         filter->queue = ntuple_filter->queue;
4322
4323         /*
4324          * look for an unused 5tuple filter index,
4325          * and insert the filter to list.
4326          */
4327         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4328                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4329                         filter_info->fivetuple_mask |= 1 << i;
4330                         filter->index = i;
4331                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4332                                           filter,
4333                                           entries);
4334                         break;
4335                 }
4336         }
4337         if (i >= E1000_MAX_FTQF_FILTERS) {
4338                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4339                 rte_free(filter);
4340                 return -ENOSYS;
4341         }
4342
4343         igb_inject_5tuple_filter_82576(dev, filter);
4344         return 0;
4345 }
4346
4347 int
4348 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4349                                 struct e1000_5tuple_filter *filter)
4350 {
4351         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352         struct e1000_filter_info *filter_info =
4353                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4354
4355         filter_info->fivetuple_mask &= ~(1 << filter->index);
4356         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4357         rte_free(filter);
4358
4359         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4360                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4361         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4362         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4363         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4364         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4365         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4366         return 0;
4367 }
4368
4369 /*
4370  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4371  *
4372  * @param
4373  * dev: Pointer to struct rte_eth_dev.
4374  * ntuple_filter: ponter to the filter that will be removed.
4375  *
4376  * @return
4377  *    - On success, zero.
4378  *    - On failure, a negative value.
4379  */
4380 static int
4381 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4382                                 struct rte_eth_ntuple_filter *ntuple_filter)
4383 {
4384         struct e1000_filter_info *filter_info =
4385                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4386         struct e1000_5tuple_filter_info filter_5tuple;
4387         struct e1000_5tuple_filter *filter;
4388         int ret;
4389
4390         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4391         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4392                                             &filter_5tuple);
4393         if (ret < 0)
4394                 return ret;
4395
4396         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4397                                          &filter_5tuple);
4398         if (filter == NULL) {
4399                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4400                 return -ENOENT;
4401         }
4402
4403         igb_delete_5tuple_filter_82576(dev, filter);
4404
4405         return 0;
4406 }
4407
4408 static int
4409 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4410 {
4411         uint32_t rctl;
4412         struct e1000_hw *hw;
4413         struct rte_eth_dev_info dev_info;
4414         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4415                                      VLAN_TAG_SIZE);
4416
4417         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418
4419 #ifdef RTE_LIBRTE_82571_SUPPORT
4420         /* XXX: not bigger than max_rx_pktlen */
4421         if (hw->mac.type == e1000_82571)
4422                 return -ENOTSUP;
4423 #endif
4424         eth_igb_infos_get(dev, &dev_info);
4425
4426         /* check that mtu is within the allowed range */
4427         if ((mtu < ETHER_MIN_MTU) ||
4428             (frame_size > dev_info.max_rx_pktlen))
4429                 return -EINVAL;
4430
4431         /* refuse mtu that requires the support of scattered packets when this
4432          * feature has not been enabled before. */
4433         if (!dev->data->scattered_rx &&
4434             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4435                 return -EINVAL;
4436
4437         rctl = E1000_READ_REG(hw, E1000_RCTL);
4438
4439         /* switch to jumbo mode if needed */
4440         if (frame_size > ETHER_MAX_LEN) {
4441                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4442                 rctl |= E1000_RCTL_LPE;
4443         } else {
4444                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4445                 rctl &= ~E1000_RCTL_LPE;
4446         }
4447         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4448
4449         /* update max frame size */
4450         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4451
4452         E1000_WRITE_REG(hw, E1000_RLPML,
4453                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4454
4455         return 0;
4456 }
4457
4458 /*
4459  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4460  *
4461  * @param
4462  * dev: Pointer to struct rte_eth_dev.
4463  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4464  * add: if true, add filter, if false, remove filter
4465  *
4466  * @return
4467  *    - On success, zero.
4468  *    - On failure, a negative value.
4469  */
4470 int
4471 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4472                         struct rte_eth_ntuple_filter *ntuple_filter,
4473                         bool add)
4474 {
4475         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476         int ret;
4477
4478         switch (ntuple_filter->flags) {
4479         case RTE_5TUPLE_FLAGS:
4480         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4481                 if (hw->mac.type != e1000_82576)
4482                         return -ENOTSUP;
4483                 if (add)
4484                         ret = igb_add_5tuple_filter_82576(dev,
4485                                                           ntuple_filter);
4486                 else
4487                         ret = igb_remove_5tuple_filter_82576(dev,
4488                                                              ntuple_filter);
4489                 break;
4490         case RTE_2TUPLE_FLAGS:
4491         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4492                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4493                         hw->mac.type != e1000_i210 &&
4494                         hw->mac.type != e1000_i211)
4495                         return -ENOTSUP;
4496                 if (add)
4497                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4498                 else
4499                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4500                 break;
4501         default:
4502                 ret = -EINVAL;
4503                 break;
4504         }
4505
4506         return ret;
4507 }
4508
4509 /*
4510  * igb_get_ntuple_filter - get a ntuple filter
4511  *
4512  * @param
4513  * dev: Pointer to struct rte_eth_dev.
4514  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4515  *
4516  * @return
4517  *    - On success, zero.
4518  *    - On failure, a negative value.
4519  */
4520 static int
4521 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4522                         struct rte_eth_ntuple_filter *ntuple_filter)
4523 {
4524         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525         struct e1000_filter_info *filter_info =
4526                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4527         struct e1000_5tuple_filter_info filter_5tuple;
4528         struct e1000_2tuple_filter_info filter_2tuple;
4529         struct e1000_5tuple_filter *p_5tuple_filter;
4530         struct e1000_2tuple_filter *p_2tuple_filter;
4531         int ret;
4532
4533         switch (ntuple_filter->flags) {
4534         case RTE_5TUPLE_FLAGS:
4535         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4536                 if (hw->mac.type != e1000_82576)
4537                         return -ENOTSUP;
4538                 memset(&filter_5tuple,
4539                         0,
4540                         sizeof(struct e1000_5tuple_filter_info));
4541                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4542                                                     &filter_5tuple);
4543                 if (ret < 0)
4544                         return ret;
4545                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4546                                         &filter_info->fivetuple_list,
4547                                         &filter_5tuple);
4548                 if (p_5tuple_filter == NULL) {
4549                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4550                         return -ENOENT;
4551                 }
4552                 ntuple_filter->queue = p_5tuple_filter->queue;
4553                 break;
4554         case RTE_2TUPLE_FLAGS:
4555         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4556                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4557                         return -ENOTSUP;
4558                 memset(&filter_2tuple,
4559                         0,
4560                         sizeof(struct e1000_2tuple_filter_info));
4561                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4562                 if (ret < 0)
4563                         return ret;
4564                 p_2tuple_filter = igb_2tuple_filter_lookup(
4565                                         &filter_info->twotuple_list,
4566                                         &filter_2tuple);
4567                 if (p_2tuple_filter == NULL) {
4568                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4569                         return -ENOENT;
4570                 }
4571                 ntuple_filter->queue = p_2tuple_filter->queue;
4572                 break;
4573         default:
4574                 ret = -EINVAL;
4575                 break;
4576         }
4577
4578         return 0;
4579 }
4580
4581 /*
4582  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4583  * @dev: pointer to rte_eth_dev structure
4584  * @filter_op:operation will be taken.
4585  * @arg: a pointer to specific structure corresponding to the filter_op
4586  */
4587 static int
4588 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4589                                 enum rte_filter_op filter_op,
4590                                 void *arg)
4591 {
4592         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4593         int ret;
4594
4595         MAC_TYPE_FILTER_SUP(hw->mac.type);
4596
4597         if (filter_op == RTE_ETH_FILTER_NOP)
4598                 return 0;
4599
4600         if (arg == NULL) {
4601                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4602                             filter_op);
4603                 return -EINVAL;
4604         }
4605
4606         switch (filter_op) {
4607         case RTE_ETH_FILTER_ADD:
4608                 ret = igb_add_del_ntuple_filter(dev,
4609                         (struct rte_eth_ntuple_filter *)arg,
4610                         TRUE);
4611                 break;
4612         case RTE_ETH_FILTER_DELETE:
4613                 ret = igb_add_del_ntuple_filter(dev,
4614                         (struct rte_eth_ntuple_filter *)arg,
4615                         FALSE);
4616                 break;
4617         case RTE_ETH_FILTER_GET:
4618                 ret = igb_get_ntuple_filter(dev,
4619                         (struct rte_eth_ntuple_filter *)arg);
4620                 break;
4621         default:
4622                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4623                 ret = -EINVAL;
4624                 break;
4625         }
4626         return ret;
4627 }
4628
4629 static inline int
4630 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4631                         uint16_t ethertype)
4632 {
4633         int i;
4634
4635         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4636                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4637                     (filter_info->ethertype_mask & (1 << i)))
4638                         return i;
4639         }
4640         return -1;
4641 }
4642
4643 static inline int
4644 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4645                         uint16_t ethertype, uint32_t etqf)
4646 {
4647         int i;
4648
4649         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4650                 if (!(filter_info->ethertype_mask & (1 << i))) {
4651                         filter_info->ethertype_mask |= 1 << i;
4652                         filter_info->ethertype_filters[i].ethertype = ethertype;
4653                         filter_info->ethertype_filters[i].etqf = etqf;
4654                         return i;
4655                 }
4656         }
4657         return -1;
4658 }
4659
4660 int
4661 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4662                         uint8_t idx)
4663 {
4664         if (idx >= E1000_MAX_ETQF_FILTERS)
4665                 return -1;
4666         filter_info->ethertype_mask &= ~(1 << idx);
4667         filter_info->ethertype_filters[idx].ethertype = 0;
4668         filter_info->ethertype_filters[idx].etqf = 0;
4669         return idx;
4670 }
4671
4672
4673 int
4674 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4675                         struct rte_eth_ethertype_filter *filter,
4676                         bool add)
4677 {
4678         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4679         struct e1000_filter_info *filter_info =
4680                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4681         uint32_t etqf = 0;
4682         int ret;
4683
4684         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4685                 filter->ether_type == ETHER_TYPE_IPv6) {
4686                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4687                         " ethertype filter.", filter->ether_type);
4688                 return -EINVAL;
4689         }
4690
4691         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4692                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4693                 return -EINVAL;
4694         }
4695         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4696                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4697                 return -EINVAL;
4698         }
4699
4700         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4701         if (ret >= 0 && add) {
4702                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4703                             filter->ether_type);
4704                 return -EEXIST;
4705         }
4706         if (ret < 0 && !add) {
4707                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4708                             filter->ether_type);
4709                 return -ENOENT;
4710         }
4711
4712         if (add) {
4713                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4714                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4715                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4716                 ret = igb_ethertype_filter_insert(filter_info,
4717                                 filter->ether_type, etqf);
4718                 if (ret < 0) {
4719                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4720                         return -ENOSYS;
4721                 }
4722         } else {
4723                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4724                 if (ret < 0)
4725                         return -ENOSYS;
4726         }
4727         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4728         E1000_WRITE_FLUSH(hw);
4729
4730         return 0;
4731 }
4732
4733 static int
4734 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4735                         struct rte_eth_ethertype_filter *filter)
4736 {
4737         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4738         struct e1000_filter_info *filter_info =
4739                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4740         uint32_t etqf;
4741         int ret;
4742
4743         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4744         if (ret < 0) {
4745                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4746                             filter->ether_type);
4747                 return -ENOENT;
4748         }
4749
4750         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4751         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4752                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4753                 filter->flags = 0;
4754                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4755                                 E1000_ETQF_QUEUE_SHIFT;
4756                 return 0;
4757         }
4758
4759         return -ENOENT;
4760 }
4761
4762 /*
4763  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4764  * @dev: pointer to rte_eth_dev structure
4765  * @filter_op:operation will be taken.
4766  * @arg: a pointer to specific structure corresponding to the filter_op
4767  */
4768 static int
4769 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4770                                 enum rte_filter_op filter_op,
4771                                 void *arg)
4772 {
4773         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774         int ret;
4775
4776         MAC_TYPE_FILTER_SUP(hw->mac.type);
4777
4778         if (filter_op == RTE_ETH_FILTER_NOP)
4779                 return 0;
4780
4781         if (arg == NULL) {
4782                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4783                             filter_op);
4784                 return -EINVAL;
4785         }
4786
4787         switch (filter_op) {
4788         case RTE_ETH_FILTER_ADD:
4789                 ret = igb_add_del_ethertype_filter(dev,
4790                         (struct rte_eth_ethertype_filter *)arg,
4791                         TRUE);
4792                 break;
4793         case RTE_ETH_FILTER_DELETE:
4794                 ret = igb_add_del_ethertype_filter(dev,
4795                         (struct rte_eth_ethertype_filter *)arg,
4796                         FALSE);
4797                 break;
4798         case RTE_ETH_FILTER_GET:
4799                 ret = igb_get_ethertype_filter(dev,
4800                         (struct rte_eth_ethertype_filter *)arg);
4801                 break;
4802         default:
4803                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4804                 ret = -EINVAL;
4805                 break;
4806         }
4807         return ret;
4808 }
4809
4810 static int
4811 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4812                      enum rte_filter_type filter_type,
4813                      enum rte_filter_op filter_op,
4814                      void *arg)
4815 {
4816         int ret = 0;
4817
4818         switch (filter_type) {
4819         case RTE_ETH_FILTER_NTUPLE:
4820                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4821                 break;
4822         case RTE_ETH_FILTER_ETHERTYPE:
4823                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4824                 break;
4825         case RTE_ETH_FILTER_SYN:
4826                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4827                 break;
4828         case RTE_ETH_FILTER_FLEXIBLE:
4829                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4830                 break;
4831         case RTE_ETH_FILTER_GENERIC:
4832                 if (filter_op != RTE_ETH_FILTER_GET)
4833                         return -EINVAL;
4834                 *(const void **)arg = &igb_flow_ops;
4835                 break;
4836         default:
4837                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4838                                                         filter_type);
4839                 break;
4840         }
4841
4842         return ret;
4843 }
4844
4845 static int
4846 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4847                          struct ether_addr *mc_addr_set,
4848                          uint32_t nb_mc_addr)
4849 {
4850         struct e1000_hw *hw;
4851
4852         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4854         return 0;
4855 }
4856
4857 static uint64_t
4858 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4859 {
4860         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         uint64_t systime_cycles;
4862
4863         switch (hw->mac.type) {
4864         case e1000_i210:
4865         case e1000_i211:
4866                 /*
4867                  * Need to read System Time Residue Register to be able
4868                  * to read the other two registers.
4869                  */
4870                 E1000_READ_REG(hw, E1000_SYSTIMR);
4871                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4872                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4873                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4874                                 * NSEC_PER_SEC;
4875                 break;
4876         case e1000_82580:
4877         case e1000_i350:
4878         case e1000_i354:
4879                 /*
4880                  * Need to read System Time Residue Register to be able
4881                  * to read the other two registers.
4882                  */
4883                 E1000_READ_REG(hw, E1000_SYSTIMR);
4884                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4885                 /* Only the 8 LSB are valid. */
4886                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4887                                 & 0xff) << 32;
4888                 break;
4889         default:
4890                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4891                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4892                                 << 32;
4893                 break;
4894         }
4895
4896         return systime_cycles;
4897 }
4898
4899 static uint64_t
4900 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4901 {
4902         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4903         uint64_t rx_tstamp_cycles;
4904
4905         switch (hw->mac.type) {
4906         case e1000_i210:
4907         case e1000_i211:
4908                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4909                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4910                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4911                                 * NSEC_PER_SEC;
4912                 break;
4913         case e1000_82580:
4914         case e1000_i350:
4915         case e1000_i354:
4916                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4917                 /* Only the 8 LSB are valid. */
4918                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4919                                 & 0xff) << 32;
4920                 break;
4921         default:
4922                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4923                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4924                                 << 32;
4925                 break;
4926         }
4927
4928         return rx_tstamp_cycles;
4929 }
4930
4931 static uint64_t
4932 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4933 {
4934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935         uint64_t tx_tstamp_cycles;
4936
4937         switch (hw->mac.type) {
4938         case e1000_i210:
4939         case e1000_i211:
4940                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4941                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4942                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4943                                 * NSEC_PER_SEC;
4944                 break;
4945         case e1000_82580:
4946         case e1000_i350:
4947         case e1000_i354:
4948                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4949                 /* Only the 8 LSB are valid. */
4950                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4951                                 & 0xff) << 32;
4952                 break;
4953         default:
4954                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4955                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4956                                 << 32;
4957                 break;
4958         }
4959
4960         return tx_tstamp_cycles;
4961 }
4962
4963 static void
4964 igb_start_timecounters(struct rte_eth_dev *dev)
4965 {
4966         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         struct e1000_adapter *adapter =
4968                 (struct e1000_adapter *)dev->data->dev_private;
4969         uint32_t incval = 1;
4970         uint32_t shift = 0;
4971         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4972
4973         switch (hw->mac.type) {
4974         case e1000_82580:
4975         case e1000_i350:
4976         case e1000_i354:
4977                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4978                 mask = (1ULL << 40) - 1;
4979                 /* fall-through */
4980         case e1000_i210:
4981         case e1000_i211:
4982                 /*
4983                  * Start incrementing the register
4984                  * used to timestamp PTP packets.
4985                  */
4986                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4987                 break;
4988         case e1000_82576:
4989                 incval = E1000_INCVALUE_82576;
4990                 shift = IGB_82576_TSYNC_SHIFT;
4991                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4992                                 E1000_INCPERIOD_82576 | incval);
4993                 break;
4994         default:
4995                 /* Not supported */
4996                 return;
4997         }
4998
4999         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5000         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5001         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5002
5003         adapter->systime_tc.cc_mask = mask;
5004         adapter->systime_tc.cc_shift = shift;
5005         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5006
5007         adapter->rx_tstamp_tc.cc_mask = mask;
5008         adapter->rx_tstamp_tc.cc_shift = shift;
5009         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5010
5011         adapter->tx_tstamp_tc.cc_mask = mask;
5012         adapter->tx_tstamp_tc.cc_shift = shift;
5013         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5014 }
5015
5016 static int
5017 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5018 {
5019         struct e1000_adapter *adapter =
5020                         (struct e1000_adapter *)dev->data->dev_private;
5021
5022         adapter->systime_tc.nsec += delta;
5023         adapter->rx_tstamp_tc.nsec += delta;
5024         adapter->tx_tstamp_tc.nsec += delta;
5025
5026         return 0;
5027 }
5028
5029 static int
5030 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5031 {
5032         uint64_t ns;
5033         struct e1000_adapter *adapter =
5034                         (struct e1000_adapter *)dev->data->dev_private;
5035
5036         ns = rte_timespec_to_ns(ts);
5037
5038         /* Set the timecounters to a new value. */
5039         adapter->systime_tc.nsec = ns;
5040         adapter->rx_tstamp_tc.nsec = ns;
5041         adapter->tx_tstamp_tc.nsec = ns;
5042
5043         return 0;
5044 }
5045
5046 static int
5047 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5048 {
5049         uint64_t ns, systime_cycles;
5050         struct e1000_adapter *adapter =
5051                         (struct e1000_adapter *)dev->data->dev_private;
5052
5053         systime_cycles = igb_read_systime_cyclecounter(dev);
5054         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5055         *ts = rte_ns_to_timespec(ns);
5056
5057         return 0;
5058 }
5059
5060 static int
5061 igb_timesync_enable(struct rte_eth_dev *dev)
5062 {
5063         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064         uint32_t tsync_ctl;
5065         uint32_t tsauxc;
5066
5067         /* Stop the timesync system time. */
5068         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5069         /* Reset the timesync system time value. */
5070         switch (hw->mac.type) {
5071         case e1000_82580:
5072         case e1000_i350:
5073         case e1000_i354:
5074         case e1000_i210:
5075         case e1000_i211:
5076                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5077                 /* fall-through */
5078         case e1000_82576:
5079                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5080                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5081                 break;
5082         default:
5083                 /* Not supported. */
5084                 return -ENOTSUP;
5085         }
5086
5087         /* Enable system time for it isn't on by default. */
5088         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5089         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5090         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5091
5092         igb_start_timecounters(dev);
5093
5094         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5095         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5096                         (ETHER_TYPE_1588 |
5097                          E1000_ETQF_FILTER_ENABLE |
5098                          E1000_ETQF_1588));
5099
5100         /* Enable timestamping of received PTP packets. */
5101         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5102         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5103         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5104
5105         /* Enable Timestamping of transmitted PTP packets. */
5106         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5107         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5108         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5109
5110         return 0;
5111 }
5112
5113 static int
5114 igb_timesync_disable(struct rte_eth_dev *dev)
5115 {
5116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117         uint32_t tsync_ctl;
5118
5119         /* Disable timestamping of transmitted PTP packets. */
5120         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5121         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5122         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5123
5124         /* Disable timestamping of received PTP packets. */
5125         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5126         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5127         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5128
5129         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5130         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5131
5132         /* Stop incrementating the System Time registers. */
5133         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5134
5135         return 0;
5136 }
5137
5138 static int
5139 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5140                                struct timespec *timestamp,
5141                                uint32_t flags __rte_unused)
5142 {
5143         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5144         struct e1000_adapter *adapter =
5145                         (struct e1000_adapter *)dev->data->dev_private;
5146         uint32_t tsync_rxctl;
5147         uint64_t rx_tstamp_cycles;
5148         uint64_t ns;
5149
5150         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5151         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5152                 return -EINVAL;
5153
5154         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5155         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5156         *timestamp = rte_ns_to_timespec(ns);
5157
5158         return  0;
5159 }
5160
5161 static int
5162 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5163                                struct timespec *timestamp)
5164 {
5165         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         struct e1000_adapter *adapter =
5167                         (struct e1000_adapter *)dev->data->dev_private;
5168         uint32_t tsync_txctl;
5169         uint64_t tx_tstamp_cycles;
5170         uint64_t ns;
5171
5172         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5173         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5174                 return -EINVAL;
5175
5176         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5177         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5178         *timestamp = rte_ns_to_timespec(ns);
5179
5180         return  0;
5181 }
5182
5183 static int
5184 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5185 {
5186         int count = 0;
5187         int g_ind = 0;
5188         const struct reg_info *reg_group;
5189
5190         while ((reg_group = igb_regs[g_ind++]))
5191                 count += igb_reg_group_count(reg_group);
5192
5193         return count;
5194 }
5195
5196 static int
5197 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5198 {
5199         int count = 0;
5200         int g_ind = 0;
5201         const struct reg_info *reg_group;
5202
5203         while ((reg_group = igbvf_regs[g_ind++]))
5204                 count += igb_reg_group_count(reg_group);
5205
5206         return count;
5207 }
5208
5209 static int
5210 eth_igb_get_regs(struct rte_eth_dev *dev,
5211         struct rte_dev_reg_info *regs)
5212 {
5213         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214         uint32_t *data = regs->data;
5215         int g_ind = 0;
5216         int count = 0;
5217         const struct reg_info *reg_group;
5218
5219         if (data == NULL) {
5220                 regs->length = eth_igb_get_reg_length(dev);
5221                 regs->width = sizeof(uint32_t);
5222                 return 0;
5223         }
5224
5225         /* Support only full register dump */
5226         if ((regs->length == 0) ||
5227             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5228                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5229                         hw->device_id;
5230                 while ((reg_group = igb_regs[g_ind++]))
5231                         count += igb_read_regs_group(dev, &data[count],
5232                                                         reg_group);
5233                 return 0;
5234         }
5235
5236         return -ENOTSUP;
5237 }
5238
5239 static int
5240 igbvf_get_regs(struct rte_eth_dev *dev,
5241         struct rte_dev_reg_info *regs)
5242 {
5243         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244         uint32_t *data = regs->data;
5245         int g_ind = 0;
5246         int count = 0;
5247         const struct reg_info *reg_group;
5248
5249         if (data == NULL) {
5250                 regs->length = igbvf_get_reg_length(dev);
5251                 regs->width = sizeof(uint32_t);
5252                 return 0;
5253         }
5254
5255         /* Support only full register dump */
5256         if ((regs->length == 0) ||
5257             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5258                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5259                         hw->device_id;
5260                 while ((reg_group = igbvf_regs[g_ind++]))
5261                         count += igb_read_regs_group(dev, &data[count],
5262                                                         reg_group);
5263                 return 0;
5264         }
5265
5266         return -ENOTSUP;
5267 }
5268
5269 static int
5270 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5271 {
5272         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5273
5274         /* Return unit is byte count */
5275         return hw->nvm.word_size * 2;
5276 }
5277
5278 static int
5279 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5280         struct rte_dev_eeprom_info *in_eeprom)
5281 {
5282         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5283         struct e1000_nvm_info *nvm = &hw->nvm;
5284         uint16_t *data = in_eeprom->data;
5285         int first, length;
5286
5287         first = in_eeprom->offset >> 1;
5288         length = in_eeprom->length >> 1;
5289         if ((first >= hw->nvm.word_size) ||
5290             ((first + length) >= hw->nvm.word_size))
5291                 return -EINVAL;
5292
5293         in_eeprom->magic = hw->vendor_id |
5294                 ((uint32_t)hw->device_id << 16);
5295
5296         if ((nvm->ops.read) == NULL)
5297                 return -ENOTSUP;
5298
5299         return nvm->ops.read(hw, first, length, data);
5300 }
5301
5302 static int
5303 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5304         struct rte_dev_eeprom_info *in_eeprom)
5305 {
5306         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307         struct e1000_nvm_info *nvm = &hw->nvm;
5308         uint16_t *data = in_eeprom->data;
5309         int first, length;
5310
5311         first = in_eeprom->offset >> 1;
5312         length = in_eeprom->length >> 1;
5313         if ((first >= hw->nvm.word_size) ||
5314             ((first + length) >= hw->nvm.word_size))
5315                 return -EINVAL;
5316
5317         in_eeprom->magic = (uint32_t)hw->vendor_id |
5318                 ((uint32_t)hw->device_id << 16);
5319
5320         if ((nvm->ops.write) == NULL)
5321                 return -ENOTSUP;
5322         return nvm->ops.write(hw,  first, length, data);
5323 }
5324
5325 static int
5326 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5327 {
5328         struct e1000_hw *hw =
5329                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5330         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5331         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5332         uint32_t vec = E1000_MISC_VEC_ID;
5333
5334         if (rte_intr_allow_others(intr_handle))
5335                 vec = E1000_RX_VEC_START;
5336
5337         uint32_t mask = 1 << (queue_id + vec);
5338
5339         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5340         E1000_WRITE_FLUSH(hw);
5341
5342         return 0;
5343 }
5344
5345 static int
5346 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5347 {
5348         struct e1000_hw *hw =
5349                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5350         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5351         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5352         uint32_t vec = E1000_MISC_VEC_ID;
5353
5354         if (rte_intr_allow_others(intr_handle))
5355                 vec = E1000_RX_VEC_START;
5356
5357         uint32_t mask = 1 << (queue_id + vec);
5358         uint32_t regval;
5359
5360         regval = E1000_READ_REG(hw, E1000_EIMS);
5361         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5362         E1000_WRITE_FLUSH(hw);
5363
5364         rte_intr_enable(intr_handle);
5365
5366         return 0;
5367 }
5368
5369 static void
5370 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5371                    uint8_t index, uint8_t offset)
5372 {
5373         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5374
5375         /* clear bits */
5376         val &= ~((uint32_t)0xFF << offset);
5377
5378         /* write vector and valid bit */
5379         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5380
5381         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5382 }
5383
5384 static void
5385 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5386                            uint8_t queue, uint8_t msix_vector)
5387 {
5388         uint32_t tmp = 0;
5389
5390         if (hw->mac.type == e1000_82575) {
5391                 if (direction == 0)
5392                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5393                 else if (direction == 1)
5394                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5395                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5396         } else if (hw->mac.type == e1000_82576) {
5397                 if ((direction == 0) || (direction == 1))
5398                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5399                                            ((queue & 0x8) << 1) +
5400                                            8 * direction);
5401         } else if ((hw->mac.type == e1000_82580) ||
5402                         (hw->mac.type == e1000_i350) ||
5403                         (hw->mac.type == e1000_i354) ||
5404                         (hw->mac.type == e1000_i210) ||
5405                         (hw->mac.type == e1000_i211)) {
5406                 if ((direction == 0) || (direction == 1))
5407                         eth_igb_write_ivar(hw, msix_vector,
5408                                            queue >> 1,
5409                                            ((queue & 0x1) << 4) +
5410                                            8 * direction);
5411         }
5412 }
5413
5414 /* Sets up the hardware to generate MSI-X interrupts properly
5415  * @hw
5416  *  board private structure
5417  */
5418 static void
5419 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5420 {
5421         int queue_id;
5422         uint32_t tmpval, regval, intr_mask;
5423         struct e1000_hw *hw =
5424                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5425         uint32_t vec = E1000_MISC_VEC_ID;
5426         uint32_t base = E1000_MISC_VEC_ID;
5427         uint32_t misc_shift = 0;
5428         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5429         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5430
5431         /* won't configure msix register if no mapping is done
5432          * between intr vector and event fd
5433          */
5434         if (!rte_intr_dp_is_en(intr_handle))
5435                 return;
5436
5437         if (rte_intr_allow_others(intr_handle)) {
5438                 vec = base = E1000_RX_VEC_START;
5439                 misc_shift = 1;
5440         }
5441
5442         /* set interrupt vector for other causes */
5443         if (hw->mac.type == e1000_82575) {
5444                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5445                 /* enable MSI-X PBA support */
5446                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5447
5448                 /* Auto-Mask interrupts upon ICR read */
5449                 tmpval |= E1000_CTRL_EXT_EIAME;
5450                 tmpval |= E1000_CTRL_EXT_IRCA;
5451
5452                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5453
5454                 /* enable msix_other interrupt */
5455                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5456                 regval = E1000_READ_REG(hw, E1000_EIAC);
5457                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5458                 regval = E1000_READ_REG(hw, E1000_EIAM);
5459                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5460         } else if ((hw->mac.type == e1000_82576) ||
5461                         (hw->mac.type == e1000_82580) ||
5462                         (hw->mac.type == e1000_i350) ||
5463                         (hw->mac.type == e1000_i354) ||
5464                         (hw->mac.type == e1000_i210) ||
5465                         (hw->mac.type == e1000_i211)) {
5466                 /* turn on MSI-X capability first */
5467                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5468                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5469                                         E1000_GPIE_NSICR);
5470                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5471                         misc_shift;
5472                 regval = E1000_READ_REG(hw, E1000_EIAC);
5473                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5474
5475                 /* enable msix_other interrupt */
5476                 regval = E1000_READ_REG(hw, E1000_EIMS);
5477                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5478                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5479                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5480         }
5481
5482         /* use EIAM to auto-mask when MSI-X interrupt
5483          * is asserted, this saves a register write for every interrupt
5484          */
5485         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5486                 misc_shift;
5487         regval = E1000_READ_REG(hw, E1000_EIAM);
5488         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5489
5490         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5491                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5492                 intr_handle->intr_vec[queue_id] = vec;
5493                 if (vec < base + intr_handle->nb_efd - 1)
5494                         vec++;
5495         }
5496
5497         E1000_WRITE_FLUSH(hw);
5498 }
5499
5500 /* restore n-tuple filter */
5501 static inline void
5502 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5503 {
5504         struct e1000_filter_info *filter_info =
5505                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5506         struct e1000_5tuple_filter *p_5tuple;
5507         struct e1000_2tuple_filter *p_2tuple;
5508
5509         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5510                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5511         }
5512
5513         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5514                 igb_inject_2uple_filter(dev, p_2tuple);
5515         }
5516 }
5517
5518 /* restore SYN filter */
5519 static inline void
5520 igb_syn_filter_restore(struct rte_eth_dev *dev)
5521 {
5522         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5523         struct e1000_filter_info *filter_info =
5524                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5525         uint32_t synqf;
5526
5527         synqf = filter_info->syn_info;
5528
5529         if (synqf & E1000_SYN_FILTER_ENABLE) {
5530                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5531                 E1000_WRITE_FLUSH(hw);
5532         }
5533 }
5534
5535 /* restore ethernet type filter */
5536 static inline void
5537 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5538 {
5539         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         struct e1000_filter_info *filter_info =
5541                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5542         int i;
5543
5544         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5545                 if (filter_info->ethertype_mask & (1 << i)) {
5546                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5547                                 filter_info->ethertype_filters[i].etqf);
5548                         E1000_WRITE_FLUSH(hw);
5549                 }
5550         }
5551 }
5552
5553 /* restore flex byte filter */
5554 static inline void
5555 igb_flex_filter_restore(struct rte_eth_dev *dev)
5556 {
5557         struct e1000_filter_info *filter_info =
5558                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5559         struct e1000_flex_filter *flex_filter;
5560
5561         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5562                 igb_inject_flex_filter(dev, flex_filter);
5563         }
5564 }
5565
5566 /* restore rss filter */
5567 static inline void
5568 igb_rss_filter_restore(struct rte_eth_dev *dev)
5569 {
5570         struct e1000_filter_info *filter_info =
5571                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5572
5573         if (filter_info->rss_info.num)
5574                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5575 }
5576
5577 /* restore all types filter */
5578 static int
5579 igb_filter_restore(struct rte_eth_dev *dev)
5580 {
5581         igb_ntuple_filter_restore(dev);
5582         igb_ethertype_filter_restore(dev);
5583         igb_syn_filter_restore(dev);
5584         igb_flex_filter_restore(dev);
5585         igb_rss_filter_restore(dev);
5586
5587         return 0;
5588 }
5589
5590 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5591 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5592 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5593 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5594 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5595 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");