drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static void eth_igb_close(struct rte_eth_dev *dev);
 106 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 107 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 108 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 110 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 111                                 int wait_to_complete);
 112 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 113                                 struct rte_eth_stats *rte_stats);
 114 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 115                               struct rte_eth_xstat *xstats, unsigned n);
 116 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 117                                     struct rte_eth_xstat_name *xstats_names,
 118                                     unsigned limit);
 119 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 120 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 121 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 122                               struct rte_eth_dev_info *dev_info);
 123 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 124 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 125                                 struct rte_eth_dev_info *dev_info);
 126 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 127                                 struct rte_eth_fc_conf *fc_conf);
 128 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 129                                 struct rte_eth_fc_conf *fc_conf);
 130 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 131 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 132 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 133 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 134 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 135                                                         void *param);
 136 static int  igb_hardware_init(struct e1000_hw *hw);
 137 static void igb_hw_control_acquire(struct e1000_hw *hw);
 138 static void igb_hw_control_release(struct e1000_hw *hw);
 139 static void igb_init_manageability(struct e1000_hw *hw);
 140 static void igb_release_manageability(struct e1000_hw *hw);
 141
 142 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 143
 144 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 145                 uint16_t vlan_id, int on);
 146 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 147                                  enum rte_vlan_type vlan_type,
 148                                  uint16_t tpid_id);
 149 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 150
 151 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 152 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 153 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 154 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 155 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int eth_igb_led_on(struct rte_eth_dev *dev);
 159 static int eth_igb_led_off(struct rte_eth_dev *dev);
 160
 161 static void igb_intr_disable(struct e1000_hw *hw);
 162 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 163 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 164                 struct ether_addr *mac_addr,
 165                 uint32_t index, uint32_t pool);
 166 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 167 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 168                 struct ether_addr *addr);
 169
 170 static void igbvf_intr_disable(struct e1000_hw *hw);
 171 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 172 static int igbvf_dev_start(struct rte_eth_dev *dev);
 173 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 174 static void igbvf_dev_close(struct rte_eth_dev *dev);
 175 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 176 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 177 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 178 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 179 static int eth_igbvf_link_update(struct e1000_hw *hw);
 180 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *rte_stats);
 182 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 185                                       struct rte_eth_xstat_name *xstats_names,
 186                                       unsigned limit);
 187 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 188 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 189                 uint16_t vlan_id, int on);
 190 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 191 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 192 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 193                 struct ether_addr *addr);
 194 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 195 static int igbvf_get_regs(struct rte_eth_dev *dev,
 196                 struct rte_dev_reg_info *regs);
 197
 198 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 199                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 200                                    uint16_t reta_size);
 201 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 202                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 203                                   uint16_t reta_size);
 204
 205 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 206                         struct rte_eth_syn_filter *filter,
 207                         bool add);
 208 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 209                         struct rte_eth_syn_filter *filter);
 210 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 211                         enum rte_filter_op filter_op,
 212                         void *arg);
 213 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 214                         struct rte_eth_ntuple_filter *ntuple_filter);
 215 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ntuple_filter *ntuple_filter);
 217 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 218                         struct rte_eth_flex_filter *filter,
 219                         bool add);
 220 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_flex_filter *filter);
 222 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 223                         enum rte_filter_op filter_op,
 224                         void *arg);
 225 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 226                         struct rte_eth_ntuple_filter *ntuple_filter);
 227 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 228                         struct rte_eth_ntuple_filter *ntuple_filter);
 229 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 230                         struct rte_eth_ntuple_filter *filter,
 231                         bool add);
 232 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *filter);
 234 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 235                                 enum rte_filter_op filter_op,
 236                                 void *arg);
 237 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 238                         struct rte_eth_ethertype_filter *filter,
 239                         bool add);
 240 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 241                                 enum rte_filter_op filter_op,
 242                                 void *arg);
 243 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ethertype_filter *filter);
 245 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 246                      enum rte_filter_type filter_type,
 247                      enum rte_filter_op filter_op,
 248                      void *arg);
 249 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 250 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 251                 struct rte_dev_reg_info *regs);
 252 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 253 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 254                 struct rte_dev_eeprom_info *eeprom);
 255 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 256                 struct rte_dev_eeprom_info *eeprom);
 257 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 258                                     struct ether_addr *mc_addr_set,
 259                                     uint32_t nb_mc_addr);
 260 static int igb_timesync_enable(struct rte_eth_dev *dev);
 261 static int igb_timesync_disable(struct rte_eth_dev *dev);
 262 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 263                                           struct timespec *timestamp,
 264                                           uint32_t flags);
 265 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 266                                           struct timespec *timestamp);
 267 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 268 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 269                                   struct timespec *timestamp);
 270 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 271                                    const struct timespec *timestamp);
 272 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 273                                         uint16_t queue_id);
 274 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 275                                          uint16_t queue_id);
 276 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 277                                        uint8_t queue, uint8_t msix_vector);
 278 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 279                                uint8_t index, uint8_t offset);
 280 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 281 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 282                                         void *param);
 283 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 284
 285 /*
 286  * Define VF Stats MACRO for Non "cleared on read" register
 287  */
 288 #define UPDATE_VF_STAT(reg, last, cur)            \
 289 {                                                 \
 290         u32 latest = E1000_READ_REG(hw, reg);     \
 291         cur += (latest - last) & UINT_MAX;        \
 292         last = latest;                            \
 293 }
 294
 295 #define IGB_FC_PAUSE_TIME 0x0680
 296 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 297 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 298
 299 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 300
 301 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 302
 303 /*
 304  * The set of PCI devices this driver supports
 305  */
 306 static const struct rte_pci_id pci_id_igb_map[] = {
 307
 308 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 309 #include "rte_pci_dev_ids.h"
 310
 311 {0},
 312 };
 313
 314 /*
 315  * The set of PCI devices this driver supports (for 82576&I350 VF)
 316  */
 317 static const struct rte_pci_id pci_id_igbvf_map[] = {
 318
 319 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 320 #include "rte_pci_dev_ids.h"
 321
 322 {0},
 323 };
 324
 325 static const struct rte_eth_desc_lim rx_desc_lim = {
 326         .nb_max = E1000_MAX_RING_DESC,
 327         .nb_min = E1000_MIN_RING_DESC,
 328         .nb_align = IGB_RXD_ALIGN,
 329 };
 330
 331 static const struct rte_eth_desc_lim tx_desc_lim = {
 332         .nb_max = E1000_MAX_RING_DESC,
 333         .nb_min = E1000_MIN_RING_DESC,
 334         .nb_align = IGB_RXD_ALIGN,
 335 };
 336
 337 static const struct eth_dev_ops eth_igb_ops = {
 338         .dev_configure        = eth_igb_configure,
 339         .dev_start            = eth_igb_start,
 340         .dev_stop             = eth_igb_stop,
 341         .dev_close            = eth_igb_close,
 342         .promiscuous_enable   = eth_igb_promiscuous_enable,
 343         .promiscuous_disable  = eth_igb_promiscuous_disable,
 344         .allmulticast_enable  = eth_igb_allmulticast_enable,
 345         .allmulticast_disable = eth_igb_allmulticast_disable,
 346         .link_update          = eth_igb_link_update,
 347         .stats_get            = eth_igb_stats_get,
 348         .xstats_get           = eth_igb_xstats_get,
 349         .xstats_get_names     = eth_igb_xstats_get_names,
 350         .stats_reset          = eth_igb_stats_reset,
 351         .xstats_reset         = eth_igb_xstats_reset,
 352         .dev_infos_get        = eth_igb_infos_get,
 353         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 354         .mtu_set              = eth_igb_mtu_set,
 355         .vlan_filter_set      = eth_igb_vlan_filter_set,
 356         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 357         .vlan_offload_set     = eth_igb_vlan_offload_set,
 358         .rx_queue_setup       = eth_igb_rx_queue_setup,
 359         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 360         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 361         .rx_queue_release     = eth_igb_rx_queue_release,
 362         .rx_queue_count       = eth_igb_rx_queue_count,
 363         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 364         .tx_queue_setup       = eth_igb_tx_queue_setup,
 365         .tx_queue_release     = eth_igb_tx_queue_release,
 366         .dev_led_on           = eth_igb_led_on,
 367         .dev_led_off          = eth_igb_led_off,
 368         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 369         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 370         .mac_addr_add         = eth_igb_rar_set,
 371         .mac_addr_remove      = eth_igb_rar_clear,
 372         .mac_addr_set         = eth_igb_default_mac_addr_set,
 373         .reta_update          = eth_igb_rss_reta_update,
 374         .reta_query           = eth_igb_rss_reta_query,
 375         .rss_hash_update      = eth_igb_rss_hash_update,
 376         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 377         .filter_ctrl          = eth_igb_filter_ctrl,
 378         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 379         .rxq_info_get         = igb_rxq_info_get,
 380         .txq_info_get         = igb_txq_info_get,
 381         .timesync_enable      = igb_timesync_enable,
 382         .timesync_disable     = igb_timesync_disable,
 383         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 384         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 385         .get_reg_length       = eth_igb_get_reg_length,
 386         .get_reg              = eth_igb_get_regs,
 387         .get_eeprom_length    = eth_igb_get_eeprom_length,
 388         .get_eeprom           = eth_igb_get_eeprom,
 389         .set_eeprom           = eth_igb_set_eeprom,
 390         .timesync_adjust_time = igb_timesync_adjust_time,
 391         .timesync_read_time   = igb_timesync_read_time,
 392         .timesync_write_time  = igb_timesync_write_time,
 393 };
 394
 395 /*
 396  * dev_ops for virtual function, bare necessities for basic vf
 397  * operation have been implemented
 398  */
 399 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 400         .dev_configure        = igbvf_dev_configure,
 401         .dev_start            = igbvf_dev_start,
 402         .dev_stop             = igbvf_dev_stop,
 403         .dev_close            = igbvf_dev_close,
 404         .promiscuous_enable   = igbvf_promiscuous_enable,
 405         .promiscuous_disable  = igbvf_promiscuous_disable,
 406         .allmulticast_enable  = igbvf_allmulticast_enable,
 407         .allmulticast_disable = igbvf_allmulticast_disable,
 408         .link_update          = eth_igb_link_update,
 409         .stats_get            = eth_igbvf_stats_get,
 410         .xstats_get           = eth_igbvf_xstats_get,
 411         .xstats_get_names     = eth_igbvf_xstats_get_names,
 412         .stats_reset          = eth_igbvf_stats_reset,
 413         .xstats_reset         = eth_igbvf_stats_reset,
 414         .vlan_filter_set      = igbvf_vlan_filter_set,
 415         .dev_infos_get        = eth_igbvf_infos_get,
 416         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 417         .rx_queue_setup       = eth_igb_rx_queue_setup,
 418         .rx_queue_release     = eth_igb_rx_queue_release,
 419         .tx_queue_setup       = eth_igb_tx_queue_setup,
 420         .tx_queue_release     = eth_igb_tx_queue_release,
 421         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 422         .rxq_info_get         = igb_rxq_info_get,
 423         .txq_info_get         = igb_txq_info_get,
 424         .mac_addr_set         = igbvf_default_mac_addr_set,
 425         .get_reg_length       = igbvf_get_reg_length,
 426         .get_reg              = igbvf_get_regs,
 427 };
 428
 429 /* store statistics names and its offset in stats structure */
 430 struct rte_igb_xstats_name_off {
 431         char name[RTE_ETH_XSTATS_NAME_SIZE];
 432         unsigned offset;
 433 };
 434
 435 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 436         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 437         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 438         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 439         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 440         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 441         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 442         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 443                 ecol)},
 444         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 445         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 446         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 447         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 448         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 449         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 450         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 451         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 452         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 453         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 454         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 455                 fcruc)},
 456         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 457         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 458         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 459         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 460         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 461                 prc1023)},
 462         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 463                 prc1522)},
 464         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 465         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 466         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 467         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 468         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 469         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 470         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 471         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 472         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 473         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 474         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 475         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 476         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 477         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 478         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 479         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 480         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 481         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 482                 ptc1023)},
 483         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 484                 ptc1522)},
 485         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 486         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 487         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 488         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 489         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 490         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 491         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 492
 493         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 494 };
 495
 496 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 497                 sizeof(rte_igb_stats_strings[0]))
 498
 499 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 500         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 501         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 502         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 503         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 504         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 505 };
 506
 507 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 508                 sizeof(rte_igbvf_stats_strings[0]))
 509
 510 /**
 511  * Atomically reads the link status information from global
 512  * structure rte_eth_dev.
 513  *
 514  * @param dev
 515  *   - Pointer to the structure rte_eth_dev to read from.
 516  *   - Pointer to the buffer to be saved with the link status.
 517  *
 518  * @return
 519  *   - On success, zero.
 520  *   - On failure, negative value.
 521  */
 522 static inline int
 523 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 524                                 struct rte_eth_link *link)
 525 {
 526         struct rte_eth_link *dst = link;
 527         struct rte_eth_link *src = &(dev->data->dev_link);
 528
 529         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 530                                         *(uint64_t *)src) == 0)
 531                 return -1;
 532
 533         return 0;
 534 }
 535
 536 /**
 537  * Atomically writes the link status information into global
 538  * structure rte_eth_dev.
 539  *
 540  * @param dev
 541  *   - Pointer to the structure rte_eth_dev to read from.
 542  *   - Pointer to the buffer to be saved with the link status.
 543  *
 544  * @return
 545  *   - On success, zero.
 546  *   - On failure, negative value.
 547  */
 548 static inline int
 549 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 550                                 struct rte_eth_link *link)
 551 {
 552         struct rte_eth_link *dst = &(dev->data->dev_link);
 553         struct rte_eth_link *src = link;
 554
 555         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 556                                         *(uint64_t *)src) == 0)
 557                 return -1;
 558
 559         return 0;
 560 }
 561
 562 static inline void
 563 igb_intr_enable(struct rte_eth_dev *dev)
 564 {
 565         struct e1000_interrupt *intr =
 566                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 567         struct e1000_hw *hw =
 568                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 569
 570         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 571         E1000_WRITE_FLUSH(hw);
 572 }
 573
 574 static void
 575 igb_intr_disable(struct e1000_hw *hw)
 576 {
 577         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 578         E1000_WRITE_FLUSH(hw);
 579 }
 580
 581 static inline void
 582 igbvf_intr_enable(struct rte_eth_dev *dev)
 583 {
 584         struct e1000_hw *hw =
 585                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 586
 587         /* only for mailbox */
 588         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 589         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 590         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 591         E1000_WRITE_FLUSH(hw);
 592 }
 593
 594 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 595 static void
 596 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 597 {
 598         uint32_t tmp = 0;
 599
 600         /* mailbox */
 601         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 602         tmp |= E1000_VTIVAR_VALID;
 603         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 604 }
 605
 606 static void
 607 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_hw *hw =
 610                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 611
 612         /* Configure VF other cause ivar */
 613         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 614 }
 615
 616 static inline int32_t
 617 igb_pf_reset_hw(struct e1000_hw *hw)
 618 {
 619         uint32_t ctrl_ext;
 620         int32_t status;
 621
 622         status = e1000_reset_hw(hw);
 623
 624         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 625         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 626         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 627         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 628         E1000_WRITE_FLUSH(hw);
 629
 630         return status;
 631 }
 632
 633 static void
 634 igb_identify_hardware(struct rte_eth_dev *dev)
 635 {
 636         struct e1000_hw *hw =
 637                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 638
 639         hw->vendor_id = dev->pci_dev->id.vendor_id;
 640         hw->device_id = dev->pci_dev->id.device_id;
 641         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 642         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 643
 644         e1000_set_mac_type(hw);
 645
 646         /* need to check if it is a vf device below */
 647 }
 648
 649 static int
 650 igb_reset_swfw_lock(struct e1000_hw *hw)
 651 {
 652         int ret_val;
 653
 654         /*
 655          * Do mac ops initialization manually here, since we will need
 656          * some function pointers set by this call.
 657          */
 658         ret_val = e1000_init_mac_params(hw);
 659         if (ret_val)
 660                 return ret_val;
 661
 662         /*
 663          * SMBI lock should not fail in this early stage. If this is the case,
 664          * it is due to an improper exit of the application.
 665          * So force the release of the faulty lock.
 666          */
 667         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 668                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 669         }
 670         e1000_put_hw_semaphore_generic(hw);
 671
 672         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 673                 uint16_t mask;
 674
 675                 /*
 676                  * Phy lock should not fail in this early stage. If this is the case,
 677                  * it is due to an improper exit of the application.
 678                  * So force the release of the faulty lock.
 679                  */
 680                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 681                 if (hw->bus.func > E1000_FUNC_1)
 682                         mask <<= 2;
 683                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 684                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 685                                     hw->bus.func);
 686                 }
 687                 hw->mac.ops.release_swfw_sync(hw, mask);
 688
 689                 /*
 690                  * This one is more tricky since it is common to all ports; but
 691                  * swfw_sync retries last long enough (1s) to be almost sure that if
 692                  * lock can not be taken it is due to an improper lock of the
 693                  * semaphore.
 694                  */
 695                 mask = E1000_SWFW_EEP_SM;
 696                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 697                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 698                 }
 699                 hw->mac.ops.release_swfw_sync(hw, mask);
 700         }
 701
 702         return E1000_SUCCESS;
 703 }
 704
 705 static int
 706 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 707 {
 708         int error = 0;
 709         struct rte_pci_device *pci_dev;
 710         struct e1000_hw *hw =
 711                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 712         struct e1000_vfta * shadow_vfta =
 713                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 714         struct e1000_filter_info *filter_info =
 715                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 716         struct e1000_adapter *adapter =
 717                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 718
 719         uint32_t ctrl_ext;
 720
 721         pci_dev = eth_dev->pci_dev;
 722
 723         eth_dev->dev_ops = &eth_igb_ops;
 724         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 725         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 726
 727         /* for secondary processes, we don't initialise any further as primary
 728          * has already done this work. Only check we don't need a different
 729          * RX function */
 730         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 731                 if (eth_dev->data->scattered_rx)
 732                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 733                 return 0;
 734         }
 735
 736         rte_eth_copy_pci_info(eth_dev, pci_dev);
 737
 738         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 739
 740         igb_identify_hardware(eth_dev);
 741         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 742                 error = -EIO;
 743                 goto err_late;
 744         }
 745
 746         e1000_get_bus_info(hw);
 747
 748         /* Reset any pending lock */
 749         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 750                 error = -EIO;
 751                 goto err_late;
 752         }
 753
 754         /* Finish initialization */
 755         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 756                 error = -EIO;
 757                 goto err_late;
 758         }
 759
 760         hw->mac.autoneg = 1;
 761         hw->phy.autoneg_wait_to_complete = 0;
 762         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 763
 764         /* Copper options */
 765         if (hw->phy.media_type == e1000_media_type_copper) {
 766                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 767                 hw->phy.disable_polarity_correction = 0;
 768                 hw->phy.ms_type = e1000_ms_hw_default;
 769         }
 770
 771         /*
 772          * Start from a known state, this is important in reading the nvm
 773          * and mac from that.
 774          */
 775         igb_pf_reset_hw(hw);
 776
 777         /* Make sure we have a good EEPROM before we read from it */
 778         if (e1000_validate_nvm_checksum(hw) < 0) {
 779                 /*
 780                  * Some PCI-E parts fail the first check due to
 781                  * the link being in sleep state, call it again,
 782                  * if it fails a second time its a real issue.
 783                  */
 784                 if (e1000_validate_nvm_checksum(hw) < 0) {
 785                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 786                         error = -EIO;
 787                         goto err_late;
 788                 }
 789         }
 790
 791         /* Read the permanent MAC address out of the EEPROM */
 792         if (e1000_read_mac_addr(hw) != 0) {
 793                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 794                 error = -EIO;
 795                 goto err_late;
 796         }
 797
 798         /* Allocate memory for storing MAC addresses */
 799         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 800                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 801         if (eth_dev->data->mac_addrs == NULL) {
 802                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 803                                                 "store MAC addresses",
 804                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 805                 error = -ENOMEM;
 806                 goto err_late;
 807         }
 808
 809         /* Copy the permanent MAC address */
 810         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 811
 812         /* initialize the vfta */
 813         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 814
 815         /* Now initialize the hardware */
 816         if (igb_hardware_init(hw) != 0) {
 817                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 818                 rte_free(eth_dev->data->mac_addrs);
 819                 eth_dev->data->mac_addrs = NULL;
 820                 error = -ENODEV;
 821                 goto err_late;
 822         }
 823         hw->mac.get_link_status = 1;
 824         adapter->stopped = 0;
 825
 826         /* Indicate SOL/IDER usage */
 827         if (e1000_check_reset_block(hw) < 0) {
 828                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 829                                         "SOL/IDER session");
 830         }
 831
 832         /* initialize PF if max_vfs not zero */
 833         igb_pf_host_init(eth_dev);
 834
 835         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 836         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 837         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 838         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 839         E1000_WRITE_FLUSH(hw);
 840
 841         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 842                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 843                      pci_dev->id.device_id);
 844
 845         rte_intr_callback_register(&pci_dev->intr_handle,
 846                                    eth_igb_interrupt_handler,
 847                                    (void *)eth_dev);
 848
 849         /* enable uio/vfio intr/eventfd mapping */
 850         rte_intr_enable(&pci_dev->intr_handle);
 851
 852         /* enable support intr */
 853         igb_intr_enable(eth_dev);
 854
 855         TAILQ_INIT(&filter_info->flex_list);
 856         filter_info->flex_mask = 0;
 857         TAILQ_INIT(&filter_info->twotuple_list);
 858         filter_info->twotuple_mask = 0;
 859         TAILQ_INIT(&filter_info->fivetuple_list);
 860         filter_info->fivetuple_mask = 0;
 861
 862         return 0;
 863
 864 err_late:
 865         igb_hw_control_release(hw);
 866
 867         return error;
 868 }
 869
 870 static int
 871 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 872 {
 873         struct rte_pci_device *pci_dev;
 874         struct e1000_hw *hw;
 875         struct e1000_adapter *adapter =
 876                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 881                 return -EPERM;
 882
 883         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 884         pci_dev = eth_dev->pci_dev;
 885
 886         if (adapter->stopped == 0)
 887                 eth_igb_close(eth_dev);
 888
 889         eth_dev->dev_ops = NULL;
 890         eth_dev->rx_pkt_burst = NULL;
 891         eth_dev->tx_pkt_burst = NULL;
 892
 893         /* Reset any pending lock */
 894         igb_reset_swfw_lock(hw);
 895
 896         rte_free(eth_dev->data->mac_addrs);
 897         eth_dev->data->mac_addrs = NULL;
 898
 899         /* uninitialize PF if max_vfs not zero */
 900         igb_pf_host_uninit(eth_dev);
 901
 902         /* disable uio intr before callback unregister */
 903         rte_intr_disable(&(pci_dev->intr_handle));
 904         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 905                 eth_igb_interrupt_handler, (void *)eth_dev);
 906
 907         return 0;
 908 }
 909
 910 /*
 911  * Virtual Function device init
 912  */
 913 static int
 914 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 915 {
 916         struct rte_pci_device *pci_dev;
 917         struct e1000_adapter *adapter =
 918                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 919         struct e1000_hw *hw =
 920                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         int diag;
 922         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 923
 924         PMD_INIT_FUNC_TRACE();
 925
 926         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 927         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 928         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 929
 930         /* for secondary processes, we don't initialise any further as primary
 931          * has already done this work. Only check we don't need a different
 932          * RX function */
 933         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 934                 if (eth_dev->data->scattered_rx)
 935                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 936                 return 0;
 937         }
 938
 939         pci_dev = eth_dev->pci_dev;
 940
 941         rte_eth_copy_pci_info(eth_dev, pci_dev);
 942
 943         hw->device_id = pci_dev->id.device_id;
 944         hw->vendor_id = pci_dev->id.vendor_id;
 945         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 946         adapter->stopped = 0;
 947
 948         /* Initialize the shared code (base driver) */
 949         diag = e1000_setup_init_funcs(hw, TRUE);
 950         if (diag != 0) {
 951                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 952                         diag);
 953                 return -EIO;
 954         }
 955
 956         /* init_mailbox_params */
 957         hw->mbx.ops.init_params(hw);
 958
 959         /* Disable the interrupts for VF */
 960         igbvf_intr_disable(hw);
 961
 962         diag = hw->mac.ops.reset_hw(hw);
 963
 964         /* Allocate memory for storing MAC addresses */
 965         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 966                 hw->mac.rar_entry_count, 0);
 967         if (eth_dev->data->mac_addrs == NULL) {
 968                 PMD_INIT_LOG(ERR,
 969                         "Failed to allocate %d bytes needed to store MAC "
 970                         "addresses",
 971                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 972                 return -ENOMEM;
 973         }
 974
 975         /* Generate a random MAC address, if none was assigned by PF. */
 976         if (is_zero_ether_addr(perm_addr)) {
 977                 eth_random_addr(perm_addr->addr_bytes);
 978                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
 979                 if (diag) {
 980                         rte_free(eth_dev->data->mac_addrs);
 981                         eth_dev->data->mac_addrs = NULL;
 982                         return diag;
 983                 }
 984                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
 985                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
 986                              "%02x:%02x:%02x:%02x:%02x:%02x",
 987                              perm_addr->addr_bytes[0],
 988                              perm_addr->addr_bytes[1],
 989                              perm_addr->addr_bytes[2],
 990                              perm_addr->addr_bytes[3],
 991                              perm_addr->addr_bytes[4],
 992                              perm_addr->addr_bytes[5]);
 993         }
 994
 995         /* Copy the permanent MAC address */
 996         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 997                         &eth_dev->data->mac_addrs[0]);
 998
 999         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1000                      "mac.type=%s",
1001                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1002                      pci_dev->id.device_id, "igb_mac_82576_vf");
1003
1004         rte_intr_callback_register(&pci_dev->intr_handle,
1005                                    eth_igbvf_interrupt_handler,
1006                                    (void *)eth_dev);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1013 {
1014         struct e1000_adapter *adapter =
1015                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1016         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1017
1018         PMD_INIT_FUNC_TRACE();
1019
1020         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1021                 return -EPERM;
1022
1023         if (adapter->stopped == 0)
1024                 igbvf_dev_close(eth_dev);
1025
1026         eth_dev->dev_ops = NULL;
1027         eth_dev->rx_pkt_burst = NULL;
1028         eth_dev->tx_pkt_burst = NULL;
1029
1030         rte_free(eth_dev->data->mac_addrs);
1031         eth_dev->data->mac_addrs = NULL;
1032
1033         /* disable uio intr before callback unregister */
1034         rte_intr_disable(&pci_dev->intr_handle);
1035         rte_intr_callback_unregister(&pci_dev->intr_handle,
1036                                      eth_igbvf_interrupt_handler,
1037                                      (void *)eth_dev);
1038
1039         return 0;
1040 }
1041
1042 static struct eth_driver rte_igb_pmd = {
1043         .pci_drv = {
1044                 .name = "rte_igb_pmd",
1045                 .id_table = pci_id_igb_map,
1046                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1047                         RTE_PCI_DRV_DETACHABLE,
1048         },
1049         .eth_dev_init = eth_igb_dev_init,
1050         .eth_dev_uninit = eth_igb_dev_uninit,
1051         .dev_private_size = sizeof(struct e1000_adapter),
1052 };
1053
1054 /*
1055  * virtual function driver struct
1056  */
1057 static struct eth_driver rte_igbvf_pmd = {
1058         .pci_drv = {
1059                 .name = "rte_igbvf_pmd",
1060                 .id_table = pci_id_igbvf_map,
1061                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1062         },
1063         .eth_dev_init = eth_igbvf_dev_init,
1064         .eth_dev_uninit = eth_igbvf_dev_uninit,
1065         .dev_private_size = sizeof(struct e1000_adapter),
1066 };
1067
1068 static int
1069 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1070 {
1071         rte_eth_driver_register(&rte_igb_pmd);
1072         return 0;
1073 }
1074
1075 static void
1076 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1077 {
1078         struct e1000_hw *hw =
1079                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1080         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1081         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1082         rctl |= E1000_RCTL_VFE;
1083         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1084 }
1085
1086 /*
1087  * VF Driver initialization routine.
1088  * Invoked one at EAL init time.
1089  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
1090  */
1091 static int
1092 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1093 {
1094         PMD_INIT_FUNC_TRACE();
1095
1096         rte_eth_driver_register(&rte_igbvf_pmd);
1097         return 0;
1098 }
1099
1100 static int
1101 igb_check_mq_mode(struct rte_eth_dev *dev)
1102 {
1103         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1104         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1105         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1106         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1107
1108         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1109             tx_mq_mode == ETH_MQ_TX_DCB ||
1110             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1111                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1112                 return -EINVAL;
1113         }
1114         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1115                 /* Check multi-queue mode.
1116                  * To no break software we accept ETH_MQ_RX_NONE as this might
1117                  * be used to turn off VLAN filter.
1118                  */
1119
1120                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1121                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1122                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1123                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1124                 } else {
1125                         /* Only support one queue on VFs.
1126                          * RSS together with SRIOV is not supported.
1127                          */
1128                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1129                                         " wrong mq_mode rx %d.",
1130                                         rx_mq_mode);
1131                         return -EINVAL;
1132                 }
1133                 /* TX mode is not used here, so mode might be ignored.*/
1134                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1135                         /* SRIOV only works in VMDq enable mode */
1136                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1137                                         " TX mode %d is not supported. "
1138                                         " Driver will behave as %d mode.",
1139                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1140                 }
1141
1142                 /* check valid queue number */
1143                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1144                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1145                                         " only support one queue on VFs.");
1146                         return -EINVAL;
1147                 }
1148         } else {
1149                 /* To no break software that set invalid mode, only display
1150                  * warning if invalid mode is used.
1151                  */
1152                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1153                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1154                     rx_mq_mode != ETH_MQ_RX_RSS) {
1155                         /* RSS together with VMDq not supported*/
1156                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1157                                      rx_mq_mode);
1158                         return -EINVAL;
1159                 }
1160
1161                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1162                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1163                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1164                                         " Due to txmode is meaningless in this"
1165                                         " driver, just ignore.",
1166                                         tx_mq_mode);
1167                 }
1168         }
1169         return 0;
1170 }
1171
1172 static int
1173 eth_igb_configure(struct rte_eth_dev *dev)
1174 {
1175         struct e1000_interrupt *intr =
1176                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1177         int ret;
1178
1179         PMD_INIT_FUNC_TRACE();
1180
1181         /* multipe queue mode checking */
1182         ret  = igb_check_mq_mode(dev);
1183         if (ret != 0) {
1184                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1185                             ret);
1186                 return ret;
1187         }
1188
1189         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1190         PMD_INIT_FUNC_TRACE();
1191
1192         return 0;
1193 }
1194
1195 static int
1196 eth_igb_start(struct rte_eth_dev *dev)
1197 {
1198         struct e1000_hw *hw =
1199                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1200         struct e1000_adapter *adapter =
1201                 E1000_DEV_PRIVATE(dev->data->dev_private);
1202         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1203         int ret, mask;
1204         uint32_t intr_vector = 0;
1205         uint32_t ctrl_ext;
1206         uint32_t *speeds;
1207         int num_speeds;
1208         bool autoneg;
1209
1210         PMD_INIT_FUNC_TRACE();
1211
1212         /* disable uio/vfio intr/eventfd mapping */
1213         rte_intr_disable(intr_handle);
1214
1215         /* Power up the phy. Needed to make the link go Up */
1216         e1000_power_up_phy(hw);
1217
1218         /*
1219          * Packet Buffer Allocation (PBA)
1220          * Writing PBA sets the receive portion of the buffer
1221          * the remainder is used for the transmit buffer.
1222          */
1223         if (hw->mac.type == e1000_82575) {
1224                 uint32_t pba;
1225
1226                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1227                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1228         }
1229
1230         /* Put the address into the Receive Address Array */
1231         e1000_rar_set(hw, hw->mac.addr, 0);
1232
1233         /* Initialize the hardware */
1234         if (igb_hardware_init(hw)) {
1235                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1236                 return -EIO;
1237         }
1238         adapter->stopped = 0;
1239
1240         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1241
1242         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1243         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1244         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1245         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1246         E1000_WRITE_FLUSH(hw);
1247
1248         /* configure PF module if SRIOV enabled */
1249         igb_pf_host_configure(dev);
1250
1251         /* check and configure queue intr-vector mapping */
1252         if ((rte_intr_cap_multiple(intr_handle) ||
1253              !RTE_ETH_DEV_SRIOV(dev).active) &&
1254             dev->data->dev_conf.intr_conf.rxq != 0) {
1255                 intr_vector = dev->data->nb_rx_queues;
1256                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1257                         return -1;
1258         }
1259
1260         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1261                 intr_handle->intr_vec =
1262                         rte_zmalloc("intr_vec",
1263                                     dev->data->nb_rx_queues * sizeof(int), 0);
1264                 if (intr_handle->intr_vec == NULL) {
1265                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1266                                      " intr_vec\n", dev->data->nb_rx_queues);
1267                         return -ENOMEM;
1268                 }
1269         }
1270
1271         /* confiugre msix for rx interrupt */
1272         eth_igb_configure_msix_intr(dev);
1273
1274         /* Configure for OS presence */
1275         igb_init_manageability(hw);
1276
1277         eth_igb_tx_init(dev);
1278
1279         /* This can fail when allocating mbufs for descriptor rings */
1280         ret = eth_igb_rx_init(dev);
1281         if (ret) {
1282                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1283                 igb_dev_clear_queues(dev);
1284                 return ret;
1285         }
1286
1287         e1000_clear_hw_cntrs_base_generic(hw);
1288
1289         /*
1290          * VLAN Offload Settings
1291          */
1292         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1293                         ETH_VLAN_EXTEND_MASK;
1294         eth_igb_vlan_offload_set(dev, mask);
1295
1296         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1297                 /* Enable VLAN filter since VMDq always use VLAN filter */
1298                 igb_vmdq_vlan_hw_filter_enable(dev);
1299         }
1300
1301         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1302                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1303                 (hw->mac.type == e1000_i211)) {
1304                 /* Configure EITR with the maximum possible value (0xFFFF) */
1305                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1306         }
1307
1308         /* Setup link speed and duplex */
1309         speeds = &dev->data->dev_conf.link_speeds;
1310         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1311                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1312         } else {
1313                 num_speeds = 0;
1314                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1315
1316                 /* Reset */
1317                 hw->phy.autoneg_advertised = 0;
1318
1319                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1320                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1321                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1322                         num_speeds = -1;
1323                         goto error_invalid_config;
1324                 }
1325                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1326                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1327                         num_speeds++;
1328                 }
1329                 if (*speeds & ETH_LINK_SPEED_10M) {
1330                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1331                         num_speeds++;
1332                 }
1333                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1334                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1335                         num_speeds++;
1336                 }
1337                 if (*speeds & ETH_LINK_SPEED_100M) {
1338                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1339                         num_speeds++;
1340                 }
1341                 if (*speeds & ETH_LINK_SPEED_1G) {
1342                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1343                         num_speeds++;
1344                 }
1345                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1346                         goto error_invalid_config;
1347         }
1348
1349         e1000_setup_link(hw);
1350
1351         if (rte_intr_allow_others(intr_handle)) {
1352                 /* check if lsc interrupt is enabled */
1353                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1354                         eth_igb_lsc_interrupt_setup(dev);
1355         } else {
1356                 rte_intr_callback_unregister(intr_handle,
1357                                              eth_igb_interrupt_handler,
1358                                              (void *)dev);
1359                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1360                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1361                                      " no intr multiplex\n");
1362         }
1363
1364         /* check if rxq interrupt is enabled */
1365         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1366             rte_intr_dp_is_en(intr_handle))
1367                 eth_igb_rxq_interrupt_setup(dev);
1368
1369         /* enable uio/vfio intr/eventfd mapping */
1370         rte_intr_enable(intr_handle);
1371
1372         /* resume enabled intr since hw reset */
1373         igb_intr_enable(dev);
1374
1375         PMD_INIT_LOG(DEBUG, "<<");
1376
1377         return 0;
1378
1379 error_invalid_config:
1380         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1381                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1382         igb_dev_clear_queues(dev);
1383         return -EINVAL;
1384 }
1385
1386 /*********************************************************************
1387  *
1388  *  This routine disables all traffic on the adapter by issuing a
1389  *  global reset on the MAC.
1390  *
1391  **********************************************************************/
1392 static void
1393 eth_igb_stop(struct rte_eth_dev *dev)
1394 {
1395         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct e1000_filter_info *filter_info =
1397                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1398         struct rte_eth_link link;
1399         struct e1000_flex_filter *p_flex;
1400         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1401         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1402         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1403
1404         igb_intr_disable(hw);
1405
1406         /* disable intr eventfd mapping */
1407         rte_intr_disable(intr_handle);
1408
1409         igb_pf_reset_hw(hw);
1410         E1000_WRITE_REG(hw, E1000_WUC, 0);
1411
1412         /* Set bit for Go Link disconnect */
1413         if (hw->mac.type >= e1000_82580) {
1414                 uint32_t phpm_reg;
1415
1416                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1417                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1418                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1419         }
1420
1421         /* Power down the phy. Needed to make the link go Down */
1422         if (hw->phy.media_type == e1000_media_type_copper)
1423                 e1000_power_down_phy(hw);
1424         else
1425                 e1000_shutdown_fiber_serdes_link(hw);
1426
1427         igb_dev_clear_queues(dev);
1428
1429         /* clear the recorded link status */
1430         memset(&link, 0, sizeof(link));
1431         rte_igb_dev_atomic_write_link_status(dev, &link);
1432
1433         /* Remove all flex filters of the device */
1434         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1435                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1436                 rte_free(p_flex);
1437         }
1438         filter_info->flex_mask = 0;
1439
1440         /* Remove all ntuple filters of the device */
1441         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1442              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1443                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1444                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1445                              p_5tuple, entries);
1446                 rte_free(p_5tuple);
1447         }
1448         filter_info->fivetuple_mask = 0;
1449         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1450              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1451                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1452                 TAILQ_REMOVE(&filter_info->twotuple_list,
1453                              p_2tuple, entries);
1454                 rte_free(p_2tuple);
1455         }
1456         filter_info->twotuple_mask = 0;
1457
1458         if (!rte_intr_allow_others(intr_handle))
1459                 /* resume to the default handler */
1460                 rte_intr_callback_register(intr_handle,
1461                                            eth_igb_interrupt_handler,
1462                                            (void *)dev);
1463
1464         /* Clean datapath event and queue/vec mapping */
1465         rte_intr_efd_disable(intr_handle);
1466         if (intr_handle->intr_vec != NULL) {
1467                 rte_free(intr_handle->intr_vec);
1468                 intr_handle->intr_vec = NULL;
1469         }
1470 }
1471
1472 static void
1473 eth_igb_close(struct rte_eth_dev *dev)
1474 {
1475         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1476         struct e1000_adapter *adapter =
1477                 E1000_DEV_PRIVATE(dev->data->dev_private);
1478         struct rte_eth_link link;
1479         struct rte_pci_device *pci_dev;
1480
1481         eth_igb_stop(dev);
1482         adapter->stopped = 1;
1483
1484         e1000_phy_hw_reset(hw);
1485         igb_release_manageability(hw);
1486         igb_hw_control_release(hw);
1487
1488         /* Clear bit for Go Link disconnect */
1489         if (hw->mac.type >= e1000_82580) {
1490                 uint32_t phpm_reg;
1491
1492                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1493                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1494                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1495         }
1496
1497         igb_dev_free_queues(dev);
1498
1499         pci_dev = dev->pci_dev;
1500         if (pci_dev->intr_handle.intr_vec) {
1501                 rte_free(pci_dev->intr_handle.intr_vec);
1502                 pci_dev->intr_handle.intr_vec = NULL;
1503         }
1504
1505         memset(&link, 0, sizeof(link));
1506         rte_igb_dev_atomic_write_link_status(dev, &link);
1507 }
1508
1509 static int
1510 igb_get_rx_buffer_size(struct e1000_hw *hw)
1511 {
1512         uint32_t rx_buf_size;
1513         if (hw->mac.type == e1000_82576) {
1514                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1515         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1516                 /* PBS needs to be translated according to a lookup table */
1517                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1518                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1519                 rx_buf_size = (rx_buf_size << 10);
1520         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1521                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1522         } else {
1523                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1524         }
1525
1526         return rx_buf_size;
1527 }
1528
1529 /*********************************************************************
1530  *
1531  *  Initialize the hardware
1532  *
1533  **********************************************************************/
1534 static int
1535 igb_hardware_init(struct e1000_hw *hw)
1536 {
1537         uint32_t rx_buf_size;
1538         int diag;
1539
1540         /* Let the firmware know the OS is in control */
1541         igb_hw_control_acquire(hw);
1542
1543         /*
1544          * These parameters control the automatic generation (Tx) and
1545          * response (Rx) to Ethernet PAUSE frames.
1546          * - High water mark should allow for at least two standard size (1518)
1547          *   frames to be received after sending an XOFF.
1548          * - Low water mark works best when it is very near the high water mark.
1549          *   This allows the receiver to restart by sending XON when it has
1550          *   drained a bit. Here we use an arbitrary value of 1500 which will
1551          *   restart after one full frame is pulled from the buffer. There
1552          *   could be several smaller frames in the buffer and if so they will
1553          *   not trigger the XON until their total number reduces the buffer
1554          *   by 1500.
1555          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1556          */
1557         rx_buf_size = igb_get_rx_buffer_size(hw);
1558
1559         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1560         hw->fc.low_water = hw->fc.high_water - 1500;
1561         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1562         hw->fc.send_xon = 1;
1563
1564         /* Set Flow control, use the tunable location if sane */
1565         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1566                 hw->fc.requested_mode = igb_fc_setting;
1567         else
1568                 hw->fc.requested_mode = e1000_fc_none;
1569
1570         /* Issue a global reset */
1571         igb_pf_reset_hw(hw);
1572         E1000_WRITE_REG(hw, E1000_WUC, 0);
1573
1574         diag = e1000_init_hw(hw);
1575         if (diag < 0)
1576                 return diag;
1577
1578         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1579         e1000_get_phy_info(hw);
1580         e1000_check_for_link(hw);
1581
1582         return 0;
1583 }
1584
1585 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1586 static void
1587 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1588 {
1589         int pause_frames;
1590
1591         uint64_t old_gprc  = stats->gprc;
1592         uint64_t old_gptc  = stats->gptc;
1593         uint64_t old_tpr   = stats->tpr;
1594         uint64_t old_tpt   = stats->tpt;
1595         uint64_t old_rpthc = stats->rpthc;
1596         uint64_t old_hgptc = stats->hgptc;
1597
1598         if(hw->phy.media_type == e1000_media_type_copper ||
1599             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1600                 stats->symerrs +=
1601                     E1000_READ_REG(hw,E1000_SYMERRS);
1602                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1603         }
1604
1605         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1606         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1607         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1608         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1609
1610         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1611         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1612         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1613         stats->dc += E1000_READ_REG(hw, E1000_DC);
1614         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1615         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1616         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1617         /*
1618         ** For watchdog management we need to know if we have been
1619         ** paused during the last interval, so capture that here.
1620         */
1621         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1622         stats->xoffrxc += pause_frames;
1623         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1624         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1625         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1626         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1627         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1628         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1629         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1630         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1631         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1632         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1633         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1634         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1635
1636         /* For the 64-bit byte counters the low dword must be read first. */
1637         /* Both registers clear on the read of the high dword */
1638
1639         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1640         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1641         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1642         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1643         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1644         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1645         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1646
1647         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1648         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1649         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1650         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1651         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1652
1653         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1654         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1655
1656         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1657         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1658         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1659         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1660         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1661         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1662
1663         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1664         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1665         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1666         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1667         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1668         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1669         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1670         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1671
1672         /* Interrupt Counts */
1673
1674         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1675         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1676         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1677         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1678         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1679         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1680         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1681         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1682         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1683
1684         /* Host to Card Statistics */
1685
1686         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1687         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1688         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1689         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1690         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1691         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1692         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1693         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1694         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1695         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1696         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1697         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1698         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1699         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1700         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1701         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1702
1703         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1704         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1705         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1706         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1707         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1708         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1709 }
1710
1711 static void
1712 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1713 {
1714         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715         struct e1000_hw_stats *stats =
1716                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1717
1718         igb_read_stats_registers(hw, stats);
1719
1720         if (rte_stats == NULL)
1721                 return;
1722
1723         /* Rx Errors */
1724         rte_stats->imissed = stats->mpc;
1725         rte_stats->ierrors = stats->crcerrs +
1726                              stats->rlec + stats->ruc + stats->roc +
1727                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1728
1729         /* Tx Errors */
1730         rte_stats->oerrors = stats->ecol + stats->latecol;
1731
1732         rte_stats->ipackets = stats->gprc;
1733         rte_stats->opackets = stats->gptc;
1734         rte_stats->ibytes   = stats->gorc;
1735         rte_stats->obytes   = stats->gotc;
1736 }
1737
1738 static void
1739 eth_igb_stats_reset(struct rte_eth_dev *dev)
1740 {
1741         struct e1000_hw_stats *hw_stats =
1742                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1743
1744         /* HW registers are cleared on read */
1745         eth_igb_stats_get(dev, NULL);
1746
1747         /* Reset software totals */
1748         memset(hw_stats, 0, sizeof(*hw_stats));
1749 }
1750
1751 static void
1752 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1753 {
1754         struct e1000_hw_stats *stats =
1755                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1756
1757         /* HW registers are cleared on read */
1758         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1759
1760         /* Reset software totals */
1761         memset(stats, 0, sizeof(*stats));
1762 }
1763
1764 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1765         struct rte_eth_xstat_name *xstats_names,
1766         __rte_unused unsigned limit)
1767 {
1768         unsigned i;
1769
1770         if (xstats_names == NULL)
1771                 return IGB_NB_XSTATS;
1772
1773         /* Note: limit checked in rte_eth_xstats_names() */
1774
1775         for (i = 0; i < IGB_NB_XSTATS; i++) {
1776                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1777                          "%s", rte_igb_stats_strings[i].name);
1778                 xstats_names[i].id = i;
1779         }
1780
1781         return IGB_NB_XSTATS;
1782 }
1783
1784 static int
1785 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1786                    unsigned n)
1787 {
1788         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1789         struct e1000_hw_stats *hw_stats =
1790                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1791         unsigned i;
1792
1793         if (n < IGB_NB_XSTATS)
1794                 return IGB_NB_XSTATS;
1795
1796         igb_read_stats_registers(hw, hw_stats);
1797
1798         /* If this is a reset xstats is NULL, and we have cleared the
1799          * registers by reading them.
1800          */
1801         if (!xstats)
1802                 return 0;
1803
1804         /* Extended stats */
1805         for (i = 0; i < IGB_NB_XSTATS; i++) {
1806                 xstats[i].id = i;
1807                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1808                         rte_igb_stats_strings[i].offset);
1809         }
1810
1811         return IGB_NB_XSTATS;
1812 }
1813
1814 static void
1815 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1816 {
1817         /* Good Rx packets, include VF loopback */
1818         UPDATE_VF_STAT(E1000_VFGPRC,
1819             hw_stats->last_gprc, hw_stats->gprc);
1820
1821         /* Good Rx octets, include VF loopback */
1822         UPDATE_VF_STAT(E1000_VFGORC,
1823             hw_stats->last_gorc, hw_stats->gorc);
1824
1825         /* Good Tx packets, include VF loopback */
1826         UPDATE_VF_STAT(E1000_VFGPTC,
1827             hw_stats->last_gptc, hw_stats->gptc);
1828
1829         /* Good Tx octets, include VF loopback */
1830         UPDATE_VF_STAT(E1000_VFGOTC,
1831             hw_stats->last_gotc, hw_stats->gotc);
1832
1833         /* Rx Multicst packets */
1834         UPDATE_VF_STAT(E1000_VFMPRC,
1835             hw_stats->last_mprc, hw_stats->mprc);
1836
1837         /* Good Rx loopback packets */
1838         UPDATE_VF_STAT(E1000_VFGPRLBC,
1839             hw_stats->last_gprlbc, hw_stats->gprlbc);
1840
1841         /* Good Rx loopback octets */
1842         UPDATE_VF_STAT(E1000_VFGORLBC,
1843             hw_stats->last_gorlbc, hw_stats->gorlbc);
1844
1845         /* Good Tx loopback packets */
1846         UPDATE_VF_STAT(E1000_VFGPTLBC,
1847             hw_stats->last_gptlbc, hw_stats->gptlbc);
1848
1849         /* Good Tx loopback octets */
1850         UPDATE_VF_STAT(E1000_VFGOTLBC,
1851             hw_stats->last_gotlbc, hw_stats->gotlbc);
1852 }
1853
1854 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1855                                      struct rte_eth_xstat_name *xstats_names,
1856                                      __rte_unused unsigned limit)
1857 {
1858         unsigned i;
1859
1860         if (xstats_names != NULL)
1861                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1862                         snprintf(xstats_names[i].name,
1863                                 sizeof(xstats_names[i].name), "%s",
1864                                 rte_igbvf_stats_strings[i].name);
1865                         xstats_names[i].id = i;
1866                 }
1867         return IGBVF_NB_XSTATS;
1868 }
1869
1870 static int
1871 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1872                      unsigned n)
1873 {
1874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1876                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1877         unsigned i;
1878
1879         if (n < IGBVF_NB_XSTATS)
1880                 return IGBVF_NB_XSTATS;
1881
1882         igbvf_read_stats_registers(hw, hw_stats);
1883
1884         if (!xstats)
1885                 return 0;
1886
1887         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1888                 xstats[i].id = i;
1889                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1890                         rte_igbvf_stats_strings[i].offset);
1891         }
1892
1893         return IGBVF_NB_XSTATS;
1894 }
1895
1896 static void
1897 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1898 {
1899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1901                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1902
1903         igbvf_read_stats_registers(hw, hw_stats);
1904
1905         if (rte_stats == NULL)
1906                 return;
1907
1908         rte_stats->ipackets = hw_stats->gprc;
1909         rte_stats->ibytes = hw_stats->gorc;
1910         rte_stats->opackets = hw_stats->gptc;
1911         rte_stats->obytes = hw_stats->gotc;
1912 }
1913
1914 static void
1915 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1916 {
1917         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1918                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1919
1920         /* Sync HW register to the last stats */
1921         eth_igbvf_stats_get(dev, NULL);
1922
1923         /* reset HW current stats*/
1924         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1925                offsetof(struct e1000_vf_stats, gprc));
1926 }
1927
1928 static void
1929 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1930 {
1931         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932
1933         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1934         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1935         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1936         dev_info->rx_offload_capa =
1937                 DEV_RX_OFFLOAD_VLAN_STRIP |
1938                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1939                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1940                 DEV_RX_OFFLOAD_TCP_CKSUM;
1941         dev_info->tx_offload_capa =
1942                 DEV_TX_OFFLOAD_VLAN_INSERT |
1943                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1944                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1945                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1946                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1947                 DEV_TX_OFFLOAD_TCP_TSO;
1948
1949         switch (hw->mac.type) {
1950         case e1000_82575:
1951                 dev_info->max_rx_queues = 4;
1952                 dev_info->max_tx_queues = 4;
1953                 dev_info->max_vmdq_pools = 0;
1954                 break;
1955
1956         case e1000_82576:
1957                 dev_info->max_rx_queues = 16;
1958                 dev_info->max_tx_queues = 16;
1959                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1960                 dev_info->vmdq_queue_num = 16;
1961                 break;
1962
1963         case e1000_82580:
1964                 dev_info->max_rx_queues = 8;
1965                 dev_info->max_tx_queues = 8;
1966                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1967                 dev_info->vmdq_queue_num = 8;
1968                 break;
1969
1970         case e1000_i350:
1971                 dev_info->max_rx_queues = 8;
1972                 dev_info->max_tx_queues = 8;
1973                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1974                 dev_info->vmdq_queue_num = 8;
1975                 break;
1976
1977         case e1000_i354:
1978                 dev_info->max_rx_queues = 8;
1979                 dev_info->max_tx_queues = 8;
1980                 break;
1981
1982         case e1000_i210:
1983                 dev_info->max_rx_queues = 4;
1984                 dev_info->max_tx_queues = 4;
1985                 dev_info->max_vmdq_pools = 0;
1986                 break;
1987
1988         case e1000_i211:
1989                 dev_info->max_rx_queues = 2;
1990                 dev_info->max_tx_queues = 2;
1991                 dev_info->max_vmdq_pools = 0;
1992                 break;
1993
1994         default:
1995                 /* Should not happen */
1996                 break;
1997         }
1998         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1999         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2000         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2001
2002         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2003                 .rx_thresh = {
2004                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2005                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2006                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2007                 },
2008                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2009                 .rx_drop_en = 0,
2010         };
2011
2012         dev_info->default_txconf = (struct rte_eth_txconf) {
2013                 .tx_thresh = {
2014                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2015                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2016                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2017                 },
2018                 .txq_flags = 0,
2019         };
2020
2021         dev_info->rx_desc_lim = rx_desc_lim;
2022         dev_info->tx_desc_lim = tx_desc_lim;
2023
2024         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2025                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2026                         ETH_LINK_SPEED_1G;
2027 }
2028
2029 static const uint32_t *
2030 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2031 {
2032         static const uint32_t ptypes[] = {
2033                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2034                 RTE_PTYPE_L2_ETHER,
2035                 RTE_PTYPE_L3_IPV4,
2036                 RTE_PTYPE_L3_IPV4_EXT,
2037                 RTE_PTYPE_L3_IPV6,
2038                 RTE_PTYPE_L3_IPV6_EXT,
2039                 RTE_PTYPE_L4_TCP,
2040                 RTE_PTYPE_L4_UDP,
2041                 RTE_PTYPE_L4_SCTP,
2042                 RTE_PTYPE_TUNNEL_IP,
2043                 RTE_PTYPE_INNER_L3_IPV6,
2044                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2045                 RTE_PTYPE_INNER_L4_TCP,
2046                 RTE_PTYPE_INNER_L4_UDP,
2047                 RTE_PTYPE_UNKNOWN
2048         };
2049
2050         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2051             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2052                 return ptypes;
2053         return NULL;
2054 }
2055
2056 static void
2057 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2058 {
2059         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060
2061         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2062         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2063         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2064         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2065                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2066                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2067                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2068         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2069                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2070                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2071                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2072                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2073                                 DEV_TX_OFFLOAD_TCP_TSO;
2074         switch (hw->mac.type) {
2075         case e1000_vfadapt:
2076                 dev_info->max_rx_queues = 2;
2077                 dev_info->max_tx_queues = 2;
2078                 break;
2079         case e1000_vfadapt_i350:
2080                 dev_info->max_rx_queues = 1;
2081                 dev_info->max_tx_queues = 1;
2082                 break;
2083         default:
2084                 /* Should not happen */
2085                 break;
2086         }
2087
2088         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2089                 .rx_thresh = {
2090                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2091                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2092                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2093                 },
2094                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2095                 .rx_drop_en = 0,
2096         };
2097
2098         dev_info->default_txconf = (struct rte_eth_txconf) {
2099                 .tx_thresh = {
2100                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2101                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2102                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2103                 },
2104                 .txq_flags = 0,
2105         };
2106
2107         dev_info->rx_desc_lim = rx_desc_lim;
2108         dev_info->tx_desc_lim = tx_desc_lim;
2109 }
2110
2111 /* return 0 means link status changed, -1 means not changed */
2112 static int
2113 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2114 {
2115         struct e1000_hw *hw =
2116                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct rte_eth_link link, old;
2118         int link_check, count;
2119
2120         link_check = 0;
2121         hw->mac.get_link_status = 1;
2122
2123         /* possible wait-to-complete in up to 9 seconds */
2124         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2125                 /* Read the real link status */
2126                 switch (hw->phy.media_type) {
2127                 case e1000_media_type_copper:
2128                         /* Do the work to read phy */
2129                         e1000_check_for_link(hw);
2130                         link_check = !hw->mac.get_link_status;
2131                         break;
2132
2133                 case e1000_media_type_fiber:
2134                         e1000_check_for_link(hw);
2135                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2136                                       E1000_STATUS_LU);
2137                         break;
2138
2139                 case e1000_media_type_internal_serdes:
2140                         e1000_check_for_link(hw);
2141                         link_check = hw->mac.serdes_has_link;
2142                         break;
2143
2144                 /* VF device is type_unknown */
2145                 case e1000_media_type_unknown:
2146                         eth_igbvf_link_update(hw);
2147                         link_check = !hw->mac.get_link_status;
2148                         break;
2149
2150                 default:
2151                         break;
2152                 }
2153                 if (link_check || wait_to_complete == 0)
2154                         break;
2155                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2156         }
2157         memset(&link, 0, sizeof(link));
2158         rte_igb_dev_atomic_read_link_status(dev, &link);
2159         old = link;
2160
2161         /* Now we check if a transition has happened */
2162         if (link_check) {
2163                 uint16_t duplex, speed;
2164                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2165                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2166                                 ETH_LINK_FULL_DUPLEX :
2167                                 ETH_LINK_HALF_DUPLEX;
2168                 link.link_speed = speed;
2169                 link.link_status = ETH_LINK_UP;
2170                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2171                                 ETH_LINK_SPEED_FIXED);
2172         } else if (!link_check) {
2173                 link.link_speed = 0;
2174                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2175                 link.link_status = ETH_LINK_DOWN;
2176                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2177         }
2178         rte_igb_dev_atomic_write_link_status(dev, &link);
2179
2180         /* not changed */
2181         if (old.link_status == link.link_status)
2182                 return -1;
2183
2184         /* changed */
2185         return 0;
2186 }
2187
2188 /*
2189  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2190  * For ASF and Pass Through versions of f/w this means
2191  * that the driver is loaded.
2192  */
2193 static void
2194 igb_hw_control_acquire(struct e1000_hw *hw)
2195 {
2196         uint32_t ctrl_ext;
2197
2198         /* Let firmware know the driver has taken over */
2199         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2200         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2201 }
2202
2203 /*
2204  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2205  * For ASF and Pass Through versions of f/w this means that the
2206  * driver is no longer loaded.
2207  */
2208 static void
2209 igb_hw_control_release(struct e1000_hw *hw)
2210 {
2211         uint32_t ctrl_ext;
2212
2213         /* Let firmware taken over control of h/w */
2214         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2215         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2216                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2217 }
2218
2219 /*
2220  * Bit of a misnomer, what this really means is
2221  * to enable OS management of the system... aka
2222  * to disable special hardware management features.
2223  */
2224 static void
2225 igb_init_manageability(struct e1000_hw *hw)
2226 {
2227         if (e1000_enable_mng_pass_thru(hw)) {
2228                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2229                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2230
2231                 /* disable hardware interception of ARP */
2232                 manc &= ~(E1000_MANC_ARP_EN);
2233
2234                 /* enable receiving management packets to the host */
2235                 manc |= E1000_MANC_EN_MNG2HOST;
2236                 manc2h |= 1 << 5;  /* Mng Port 623 */
2237                 manc2h |= 1 << 6;  /* Mng Port 664 */
2238                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2239                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2240         }
2241 }
2242
2243 static void
2244 igb_release_manageability(struct e1000_hw *hw)
2245 {
2246         if (e1000_enable_mng_pass_thru(hw)) {
2247                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2248
2249                 manc |= E1000_MANC_ARP_EN;
2250                 manc &= ~E1000_MANC_EN_MNG2HOST;
2251
2252                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2253         }
2254 }
2255
2256 static void
2257 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2258 {
2259         struct e1000_hw *hw =
2260                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         uint32_t rctl;
2262
2263         rctl = E1000_READ_REG(hw, E1000_RCTL);
2264         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2265         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2266 }
2267
2268 static void
2269 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2270 {
2271         struct e1000_hw *hw =
2272                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2273         uint32_t rctl;
2274
2275         rctl = E1000_READ_REG(hw, E1000_RCTL);
2276         rctl &= (~E1000_RCTL_UPE);
2277         if (dev->data->all_multicast == 1)
2278                 rctl |= E1000_RCTL_MPE;
2279         else
2280                 rctl &= (~E1000_RCTL_MPE);
2281         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2282 }
2283
2284 static void
2285 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2286 {
2287         struct e1000_hw *hw =
2288                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         uint32_t rctl;
2290
2291         rctl = E1000_READ_REG(hw, E1000_RCTL);
2292         rctl |= E1000_RCTL_MPE;
2293         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2294 }
2295
2296 static void
2297 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2298 {
2299         struct e1000_hw *hw =
2300                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2301         uint32_t rctl;
2302
2303         if (dev->data->promiscuous == 1)
2304                 return; /* must remain in all_multicast mode */
2305         rctl = E1000_READ_REG(hw, E1000_RCTL);
2306         rctl &= (~E1000_RCTL_MPE);
2307         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2308 }
2309
2310 static int
2311 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2312 {
2313         struct e1000_hw *hw =
2314                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         struct e1000_vfta * shadow_vfta =
2316                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2317         uint32_t vfta;
2318         uint32_t vid_idx;
2319         uint32_t vid_bit;
2320
2321         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2322                               E1000_VFTA_ENTRY_MASK);
2323         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2324         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2325         if (on)
2326                 vfta |= vid_bit;
2327         else
2328                 vfta &= ~vid_bit;
2329         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2330
2331         /* update local VFTA copy */
2332         shadow_vfta->vfta[vid_idx] = vfta;
2333
2334         return 0;
2335 }
2336
2337 static int
2338 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2339                       enum rte_vlan_type vlan_type,
2340                       uint16_t tpid)
2341 {
2342         struct e1000_hw *hw =
2343                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344         uint32_t reg, qinq;
2345
2346         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2347         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2348
2349         /* only outer TPID of double VLAN can be configured*/
2350         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2351                 reg = E1000_READ_REG(hw, E1000_VET);
2352                 reg = (reg & (~E1000_VET_VET_EXT)) |
2353                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2354                 E1000_WRITE_REG(hw, E1000_VET, reg);
2355
2356                 return 0;
2357         }
2358
2359         /* all other TPID values are read-only*/
2360         PMD_DRV_LOG(ERR, "Not supported");
2361
2362         return -ENOTSUP;
2363 }
2364
2365 static void
2366 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2367 {
2368         struct e1000_hw *hw =
2369                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2370         uint32_t reg;
2371
2372         /* Filter Table Disable */
2373         reg = E1000_READ_REG(hw, E1000_RCTL);
2374         reg &= ~E1000_RCTL_CFIEN;
2375         reg &= ~E1000_RCTL_VFE;
2376         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2377 }
2378
2379 static void
2380 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2381 {
2382         struct e1000_hw *hw =
2383                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2384         struct e1000_vfta * shadow_vfta =
2385                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2386         uint32_t reg;
2387         int i;
2388
2389         /* Filter Table Enable, CFI not used for packet acceptance */
2390         reg = E1000_READ_REG(hw, E1000_RCTL);
2391         reg &= ~E1000_RCTL_CFIEN;
2392         reg |= E1000_RCTL_VFE;
2393         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2394
2395         /* restore VFTA table */
2396         for (i = 0; i < IGB_VFTA_SIZE; i++)
2397                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2398 }
2399
2400 static void
2401 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2402 {
2403         struct e1000_hw *hw =
2404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         uint32_t reg;
2406
2407         /* VLAN Mode Disable */
2408         reg = E1000_READ_REG(hw, E1000_CTRL);
2409         reg &= ~E1000_CTRL_VME;
2410         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2411 }
2412
2413 static void
2414 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2415 {
2416         struct e1000_hw *hw =
2417                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2418         uint32_t reg;
2419
2420         /* VLAN Mode Enable */
2421         reg = E1000_READ_REG(hw, E1000_CTRL);
2422         reg |= E1000_CTRL_VME;
2423         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2424 }
2425
2426 static void
2427 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2428 {
2429         struct e1000_hw *hw =
2430                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         uint32_t reg;
2432
2433         /* CTRL_EXT: Extended VLAN */
2434         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2435         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2436         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2437
2438         /* Update maximum packet length */
2439         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2440                 E1000_WRITE_REG(hw, E1000_RLPML,
2441                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2442                                                 VLAN_TAG_SIZE);
2443 }
2444
2445 static void
2446 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2447 {
2448         struct e1000_hw *hw =
2449                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2450         uint32_t reg;
2451
2452         /* CTRL_EXT: Extended VLAN */
2453         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2454         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2455         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2456
2457         /* Update maximum packet length */
2458         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2459                 E1000_WRITE_REG(hw, E1000_RLPML,
2460                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2461                                                 2 * VLAN_TAG_SIZE);
2462 }
2463
2464 static void
2465 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2466 {
2467         if(mask & ETH_VLAN_STRIP_MASK){
2468                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2469                         igb_vlan_hw_strip_enable(dev);
2470                 else
2471                         igb_vlan_hw_strip_disable(dev);
2472         }
2473
2474         if(mask & ETH_VLAN_FILTER_MASK){
2475                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2476                         igb_vlan_hw_filter_enable(dev);
2477                 else
2478                         igb_vlan_hw_filter_disable(dev);
2479         }
2480
2481         if(mask & ETH_VLAN_EXTEND_MASK){
2482                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2483                         igb_vlan_hw_extend_enable(dev);
2484                 else
2485                         igb_vlan_hw_extend_disable(dev);
2486         }
2487 }
2488
2489
2490 /**
2491  * It enables the interrupt mask and then enable the interrupt.
2492  *
2493  * @param dev
2494  *  Pointer to struct rte_eth_dev.
2495  *
2496  * @return
2497  *  - On success, zero.
2498  *  - On failure, a negative value.
2499  */
2500 static int
2501 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2502 {
2503         struct e1000_interrupt *intr =
2504                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2505
2506         intr->mask |= E1000_ICR_LSC;
2507
2508         return 0;
2509 }
2510
2511 /* It clears the interrupt causes and enables the interrupt.
2512  * It will be called once only during nic initialized.
2513  *
2514  * @param dev
2515  *  Pointer to struct rte_eth_dev.
2516  *
2517  * @return
2518  *  - On success, zero.
2519  *  - On failure, a negative value.
2520  */
2521 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2522 {
2523         uint32_t mask, regval;
2524         struct e1000_hw *hw =
2525                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526         struct rte_eth_dev_info dev_info;
2527
2528         memset(&dev_info, 0, sizeof(dev_info));
2529         eth_igb_infos_get(dev, &dev_info);
2530
2531         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2532         regval = E1000_READ_REG(hw, E1000_EIMS);
2533         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2534
2535         return 0;
2536 }
2537
2538 /*
2539  * It reads ICR and gets interrupt causes, check it and set a bit flag
2540  * to update link status.
2541  *
2542  * @param dev
2543  *  Pointer to struct rte_eth_dev.
2544  *
2545  * @return
2546  *  - On success, zero.
2547  *  - On failure, a negative value.
2548  */
2549 static int
2550 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2551 {
2552         uint32_t icr;
2553         struct e1000_hw *hw =
2554                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         struct e1000_interrupt *intr =
2556                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2557
2558         igb_intr_disable(hw);
2559
2560         /* read-on-clear nic registers here */
2561         icr = E1000_READ_REG(hw, E1000_ICR);
2562
2563         intr->flags = 0;
2564         if (icr & E1000_ICR_LSC) {
2565                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2566         }
2567
2568         if (icr & E1000_ICR_VMMB)
2569                 intr->flags |= E1000_FLAG_MAILBOX;
2570
2571         return 0;
2572 }
2573
2574 /*
2575  * It executes link_update after knowing an interrupt is prsent.
2576  *
2577  * @param dev
2578  *  Pointer to struct rte_eth_dev.
2579  *
2580  * @return
2581  *  - On success, zero.
2582  *  - On failure, a negative value.
2583  */
2584 static int
2585 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2586 {
2587         struct e1000_hw *hw =
2588                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2589         struct e1000_interrupt *intr =
2590                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2591         uint32_t tctl, rctl;
2592         struct rte_eth_link link;
2593         int ret;
2594
2595         if (intr->flags & E1000_FLAG_MAILBOX) {
2596                 igb_pf_mbx_process(dev);
2597                 intr->flags &= ~E1000_FLAG_MAILBOX;
2598         }
2599
2600         igb_intr_enable(dev);
2601         rte_intr_enable(&(dev->pci_dev->intr_handle));
2602
2603         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2604                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2605
2606                 /* set get_link_status to check register later */
2607                 hw->mac.get_link_status = 1;
2608                 ret = eth_igb_link_update(dev, 0);
2609
2610                 /* check if link has changed */
2611                 if (ret < 0)
2612                         return 0;
2613
2614                 memset(&link, 0, sizeof(link));
2615                 rte_igb_dev_atomic_read_link_status(dev, &link);
2616                 if (link.link_status) {
2617                         PMD_INIT_LOG(INFO,
2618                                      " Port %d: Link Up - speed %u Mbps - %s",
2619                                      dev->data->port_id,
2620                                      (unsigned)link.link_speed,
2621                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2622                                      "full-duplex" : "half-duplex");
2623                 } else {
2624                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2625                                      dev->data->port_id);
2626                 }
2627
2628                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2629                              dev->pci_dev->addr.domain,
2630                              dev->pci_dev->addr.bus,
2631                              dev->pci_dev->addr.devid,
2632                              dev->pci_dev->addr.function);
2633                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2634                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2635                 if (link.link_status) {
2636                         /* enable Tx/Rx */
2637                         tctl |= E1000_TCTL_EN;
2638                         rctl |= E1000_RCTL_EN;
2639                 } else {
2640                         /* disable Tx/Rx */
2641                         tctl &= ~E1000_TCTL_EN;
2642                         rctl &= ~E1000_RCTL_EN;
2643                 }
2644                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2645                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2646                 E1000_WRITE_FLUSH(hw);
2647                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2648         }
2649
2650         return 0;
2651 }
2652
2653 /**
2654  * Interrupt handler which shall be registered at first.
2655  *
2656  * @param handle
2657  *  Pointer to interrupt handle.
2658  * @param param
2659  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2660  *
2661  * @return
2662  *  void
2663  */
2664 static void
2665 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2666                                                         void *param)
2667 {
2668         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2669
2670         eth_igb_interrupt_get_status(dev);
2671         eth_igb_interrupt_action(dev);
2672 }
2673
2674 static int
2675 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2676 {
2677         uint32_t eicr;
2678         struct e1000_hw *hw =
2679                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2680         struct e1000_interrupt *intr =
2681                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2682
2683         igbvf_intr_disable(hw);
2684
2685         /* read-on-clear nic registers here */
2686         eicr = E1000_READ_REG(hw, E1000_EICR);
2687         intr->flags = 0;
2688
2689         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2690                 intr->flags |= E1000_FLAG_MAILBOX;
2691
2692         return 0;
2693 }
2694
2695 void igbvf_mbx_process(struct rte_eth_dev *dev)
2696 {
2697         struct e1000_hw *hw =
2698                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699         struct e1000_mbx_info *mbx = &hw->mbx;
2700         u32 in_msg = 0;
2701
2702         if (mbx->ops.read(hw, &in_msg, 1, 0))
2703                 return;
2704
2705         /* PF reset VF event */
2706         if (in_msg == E1000_PF_CONTROL_MSG)
2707                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
2708 }
2709
2710 static int
2711 eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
2712 {
2713         struct e1000_interrupt *intr =
2714                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2715
2716         if (intr->flags & E1000_FLAG_MAILBOX) {
2717                 igbvf_mbx_process(dev);
2718                 intr->flags &= ~E1000_FLAG_MAILBOX;
2719         }
2720
2721         igbvf_intr_enable(dev);
2722         rte_intr_enable(&dev->pci_dev->intr_handle);
2723
2724         return 0;
2725 }
2726
2727 static void
2728 eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2729                             void *param)
2730 {
2731         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2732
2733         eth_igbvf_interrupt_get_status(dev);
2734         eth_igbvf_interrupt_action(dev);
2735 }
2736
2737 static int
2738 eth_igb_led_on(struct rte_eth_dev *dev)
2739 {
2740         struct e1000_hw *hw;
2741
2742         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2744 }
2745
2746 static int
2747 eth_igb_led_off(struct rte_eth_dev *dev)
2748 {
2749         struct e1000_hw *hw;
2750
2751         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2753 }
2754
2755 static int
2756 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2757 {
2758         struct e1000_hw *hw;
2759         uint32_t ctrl;
2760         int tx_pause;
2761         int rx_pause;
2762
2763         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2764         fc_conf->pause_time = hw->fc.pause_time;
2765         fc_conf->high_water = hw->fc.high_water;
2766         fc_conf->low_water = hw->fc.low_water;
2767         fc_conf->send_xon = hw->fc.send_xon;
2768         fc_conf->autoneg = hw->mac.autoneg;
2769
2770         /*
2771          * Return rx_pause and tx_pause status according to actual setting of
2772          * the TFCE and RFCE bits in the CTRL register.
2773          */
2774         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2775         if (ctrl & E1000_CTRL_TFCE)
2776                 tx_pause = 1;
2777         else
2778                 tx_pause = 0;
2779
2780         if (ctrl & E1000_CTRL_RFCE)
2781                 rx_pause = 1;
2782         else
2783                 rx_pause = 0;
2784
2785         if (rx_pause && tx_pause)
2786                 fc_conf->mode = RTE_FC_FULL;
2787         else if (rx_pause)
2788                 fc_conf->mode = RTE_FC_RX_PAUSE;
2789         else if (tx_pause)
2790                 fc_conf->mode = RTE_FC_TX_PAUSE;
2791         else
2792                 fc_conf->mode = RTE_FC_NONE;
2793
2794         return 0;
2795 }
2796
2797 static int
2798 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2799 {
2800         struct e1000_hw *hw;
2801         int err;
2802         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2803                 e1000_fc_none,
2804                 e1000_fc_rx_pause,
2805                 e1000_fc_tx_pause,
2806                 e1000_fc_full
2807         };
2808         uint32_t rx_buf_size;
2809         uint32_t max_high_water;
2810         uint32_t rctl;
2811
2812         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         if (fc_conf->autoneg != hw->mac.autoneg)
2814                 return -ENOTSUP;
2815         rx_buf_size = igb_get_rx_buffer_size(hw);
2816         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2817
2818         /* At least reserve one Ethernet frame for watermark */
2819         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2820         if ((fc_conf->high_water > max_high_water) ||
2821             (fc_conf->high_water < fc_conf->low_water)) {
2822                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2823                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2824                 return -EINVAL;
2825         }
2826
2827         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2828         hw->fc.pause_time     = fc_conf->pause_time;
2829         hw->fc.high_water     = fc_conf->high_water;
2830         hw->fc.low_water      = fc_conf->low_water;
2831         hw->fc.send_xon       = fc_conf->send_xon;
2832
2833         err = e1000_setup_link_generic(hw);
2834         if (err == E1000_SUCCESS) {
2835
2836                 /* check if we want to forward MAC frames - driver doesn't have native
2837                  * capability to do that, so we'll write the registers ourselves */
2838
2839                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2840
2841                 /* set or clear MFLCN.PMCF bit depending on configuration */
2842                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2843                         rctl |= E1000_RCTL_PMCF;
2844                 else
2845                         rctl &= ~E1000_RCTL_PMCF;
2846
2847                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2848                 E1000_WRITE_FLUSH(hw);
2849
2850                 return 0;
2851         }
2852
2853         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2854         return -EIO;
2855 }
2856
2857 #define E1000_RAH_POOLSEL_SHIFT      (18)
2858 static void
2859 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2860                 uint32_t index, __rte_unused uint32_t pool)
2861 {
2862         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863         uint32_t rah;
2864
2865         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2866         rah = E1000_READ_REG(hw, E1000_RAH(index));
2867         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2868         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2869 }
2870
2871 static void
2872 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2873 {
2874         uint8_t addr[ETHER_ADDR_LEN];
2875         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876
2877         memset(addr, 0, sizeof(addr));
2878
2879         e1000_rar_set(hw, addr, index);
2880 }
2881
2882 static void
2883 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2884                                 struct ether_addr *addr)
2885 {
2886         eth_igb_rar_clear(dev, 0);
2887
2888         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2889 }
2890 /*
2891  * Virtual Function operations
2892  */
2893 static void
2894 igbvf_intr_disable(struct e1000_hw *hw)
2895 {
2896         PMD_INIT_FUNC_TRACE();
2897
2898         /* Clear interrupt mask to stop from interrupts being generated */
2899         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2900
2901         E1000_WRITE_FLUSH(hw);
2902 }
2903
2904 static void
2905 igbvf_stop_adapter(struct rte_eth_dev *dev)
2906 {
2907         u32 reg_val;
2908         u16 i;
2909         struct rte_eth_dev_info dev_info;
2910         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2911
2912         memset(&dev_info, 0, sizeof(dev_info));
2913         eth_igbvf_infos_get(dev, &dev_info);
2914
2915         /* Clear interrupt mask to stop from interrupts being generated */
2916         igbvf_intr_disable(hw);
2917
2918         /* Clear any pending interrupts, flush previous writes */
2919         E1000_READ_REG(hw, E1000_EICR);
2920
2921         /* Disable the transmit unit.  Each queue must be disabled. */
2922         for (i = 0; i < dev_info.max_tx_queues; i++)
2923                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2924
2925         /* Disable the receive unit by stopping each queue */
2926         for (i = 0; i < dev_info.max_rx_queues; i++) {
2927                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2928                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2929                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2930                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2931                         ;
2932         }
2933
2934         /* flush all queues disables */
2935         E1000_WRITE_FLUSH(hw);
2936         msec_delay(2);
2937 }
2938
2939 static int eth_igbvf_link_update(struct e1000_hw *hw)
2940 {
2941         struct e1000_mbx_info *mbx = &hw->mbx;
2942         struct e1000_mac_info *mac = &hw->mac;
2943         int ret_val = E1000_SUCCESS;
2944
2945         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2946
2947         /*
2948          * We only want to run this if there has been a rst asserted.
2949          * in this case that could mean a link change, device reset,
2950          * or a virtual function reset
2951          */
2952
2953         /* If we were hit with a reset or timeout drop the link */
2954         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2955                 mac->get_link_status = TRUE;
2956
2957         if (!mac->get_link_status)
2958                 goto out;
2959
2960         /* if link status is down no point in checking to see if pf is up */
2961         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2962                 goto out;
2963
2964         /* if we passed all the tests above then the link is up and we no
2965          * longer need to check for link */
2966         mac->get_link_status = FALSE;
2967
2968 out:
2969         return ret_val;
2970 }
2971
2972
2973 static int
2974 igbvf_dev_configure(struct rte_eth_dev *dev)
2975 {
2976         struct rte_eth_conf* conf = &dev->data->dev_conf;
2977
2978         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2979                      dev->data->port_id);
2980
2981         /*
2982          * VF has no ability to enable/disable HW CRC
2983          * Keep the persistent behavior the same as Host PF
2984          */
2985 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2986         if (!conf->rxmode.hw_strip_crc) {
2987                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2988                 conf->rxmode.hw_strip_crc = 1;
2989         }
2990 #else
2991         if (conf->rxmode.hw_strip_crc) {
2992                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2993                 conf->rxmode.hw_strip_crc = 0;
2994         }
2995 #endif
2996
2997         return 0;
2998 }
2999
3000 static int
3001 igbvf_dev_start(struct rte_eth_dev *dev)
3002 {
3003         struct e1000_hw *hw =
3004                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3005         struct e1000_adapter *adapter =
3006                 E1000_DEV_PRIVATE(dev->data->dev_private);
3007         int ret;
3008         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3009         uint32_t intr_vector = 0;
3010
3011         PMD_INIT_FUNC_TRACE();
3012
3013         hw->mac.ops.reset_hw(hw);
3014         adapter->stopped = 0;
3015
3016         /* Set all vfta */
3017         igbvf_set_vfta_all(dev,1);
3018
3019         eth_igbvf_tx_init(dev);
3020
3021         /* This can fail when allocating mbufs for descriptor rings */
3022         ret = eth_igbvf_rx_init(dev);
3023         if (ret) {
3024                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3025                 igb_dev_clear_queues(dev);
3026                 return ret;
3027         }
3028
3029         /* check and configure queue intr-vector mapping */
3030         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3031                 intr_vector = dev->data->nb_rx_queues;
3032                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3033                 if (ret)
3034                         return ret;
3035         }
3036
3037         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3038                 intr_handle->intr_vec =
3039                         rte_zmalloc("intr_vec",
3040                                     dev->data->nb_rx_queues * sizeof(int), 0);
3041                 if (!intr_handle->intr_vec) {
3042                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3043                                      " intr_vec\n", dev->data->nb_rx_queues);
3044                         return -ENOMEM;
3045                 }
3046         }
3047
3048         eth_igbvf_configure_msix_intr(dev);
3049
3050         /* enable uio/vfio intr/eventfd mapping */
3051         rte_intr_enable(intr_handle);
3052
3053         /* resume enabled intr since hw reset */
3054         igbvf_intr_enable(dev);
3055
3056         return 0;
3057 }
3058
3059 static void
3060 igbvf_dev_stop(struct rte_eth_dev *dev)
3061 {
3062         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3063
3064         PMD_INIT_FUNC_TRACE();
3065
3066         igbvf_stop_adapter(dev);
3067
3068         /*
3069           * Clear what we set, but we still keep shadow_vfta to
3070           * restore after device starts
3071           */
3072         igbvf_set_vfta_all(dev,0);
3073
3074         igb_dev_clear_queues(dev);
3075
3076         /* disable intr eventfd mapping */
3077         rte_intr_disable(intr_handle);
3078
3079         /* Clean datapath event and queue/vec mapping */
3080         rte_intr_efd_disable(intr_handle);
3081         if (intr_handle->intr_vec) {
3082                 rte_free(intr_handle->intr_vec);
3083                 intr_handle->intr_vec = NULL;
3084         }
3085 }
3086
3087 static void
3088 igbvf_dev_close(struct rte_eth_dev *dev)
3089 {
3090         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         struct e1000_adapter *adapter =
3092                 E1000_DEV_PRIVATE(dev->data->dev_private);
3093         struct ether_addr addr;
3094
3095         PMD_INIT_FUNC_TRACE();
3096
3097         e1000_reset_hw(hw);
3098
3099         igbvf_dev_stop(dev);
3100         adapter->stopped = 1;
3101         igb_dev_free_queues(dev);
3102
3103         /**
3104          * reprogram the RAR with a zero mac address,
3105          * to ensure that the VF traffic goes to the PF
3106          * after stop, close and detach of the VF.
3107          **/
3108
3109         memset(&addr, 0, sizeof(addr));
3110         igbvf_default_mac_addr_set(dev, &addr);
3111 }
3112
3113 static void
3114 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3115 {
3116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117
3118         /* Set both unicast and multicast promisc */
3119         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3120 }
3121
3122 static void
3123 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3124 {
3125         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126
3127         /* If in allmulticast mode leave multicast promisc */
3128         if (dev->data->all_multicast == 1)
3129                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3130         else
3131                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3132 }
3133
3134 static void
3135 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3136 {
3137         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3138
3139         /* In promiscuous mode multicast promisc already set */
3140         if (dev->data->promiscuous == 0)
3141                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3142 }
3143
3144 static void
3145 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3146 {
3147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3148
3149         /* In promiscuous mode leave multicast promisc enabled */
3150         if (dev->data->promiscuous == 0)
3151                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3152 }
3153
3154 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3155 {
3156         struct e1000_mbx_info *mbx = &hw->mbx;
3157         uint32_t msgbuf[2];
3158         s32 err;
3159
3160         /* After set vlan, vlan strip will also be enabled in igb driver*/
3161         msgbuf[0] = E1000_VF_SET_VLAN;
3162         msgbuf[1] = vid;
3163         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3164         if (on)
3165                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3166
3167         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3168         if (err)
3169                 goto mbx_err;
3170
3171         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3172         if (err)
3173                 goto mbx_err;
3174
3175         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3176         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3177                 err = -EINVAL;
3178
3179 mbx_err:
3180         return err;
3181 }
3182
3183 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3184 {
3185         struct e1000_hw *hw =
3186                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         struct e1000_vfta * shadow_vfta =
3188                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3189         int i = 0, j = 0, vfta = 0, mask = 1;
3190
3191         for (i = 0; i < IGB_VFTA_SIZE; i++){
3192                 vfta = shadow_vfta->vfta[i];
3193                 if(vfta){
3194                         mask = 1;
3195                         for (j = 0; j < 32; j++){
3196                                 if(vfta & mask)
3197                                         igbvf_set_vfta(hw,
3198                                                 (uint16_t)((i<<5)+j), on);
3199                                 mask<<=1;
3200                         }
3201                 }
3202         }
3203
3204 }
3205
3206 static int
3207 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3208 {
3209         struct e1000_hw *hw =
3210                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3211         struct e1000_vfta * shadow_vfta =
3212                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3213         uint32_t vid_idx = 0;
3214         uint32_t vid_bit = 0;
3215         int ret = 0;
3216
3217         PMD_INIT_FUNC_TRACE();
3218
3219         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3220         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3221         if(ret){
3222                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3223                 return ret;
3224         }
3225         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3226         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3227
3228         /*Save what we set and retore it after device reset*/
3229         if (on)
3230                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3231         else
3232                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3233
3234         return 0;
3235 }
3236
3237 static void
3238 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3239 {
3240         struct e1000_hw *hw =
3241                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242
3243         /* index is not used by rar_set() */
3244         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3245 }
3246
3247
3248 static int
3249 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3250                         struct rte_eth_rss_reta_entry64 *reta_conf,
3251                         uint16_t reta_size)
3252 {
3253         uint8_t i, j, mask;
3254         uint32_t reta, r;
3255         uint16_t idx, shift;
3256         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257
3258         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3259                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3260                         "(%d) doesn't match the number hardware can supported "
3261                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3262                 return -EINVAL;
3263         }
3264
3265         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3266                 idx = i / RTE_RETA_GROUP_SIZE;
3267                 shift = i % RTE_RETA_GROUP_SIZE;
3268                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3269                                                 IGB_4_BIT_MASK);
3270                 if (!mask)
3271                         continue;
3272                 if (mask == IGB_4_BIT_MASK)
3273                         r = 0;
3274                 else
3275                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3276                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3277                         if (mask & (0x1 << j))
3278                                 reta |= reta_conf[idx].reta[shift + j] <<
3279                                                         (CHAR_BIT * j);
3280                         else
3281                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3282                 }
3283                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3284         }
3285
3286         return 0;
3287 }
3288
3289 static int
3290 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3291                        struct rte_eth_rss_reta_entry64 *reta_conf,
3292                        uint16_t reta_size)
3293 {
3294         uint8_t i, j, mask;
3295         uint32_t reta;
3296         uint16_t idx, shift;
3297         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298
3299         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3300                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3301                         "(%d) doesn't match the number hardware can supported "
3302                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3303                 return -EINVAL;
3304         }
3305
3306         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3307                 idx = i / RTE_RETA_GROUP_SIZE;
3308                 shift = i % RTE_RETA_GROUP_SIZE;
3309                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3310                                                 IGB_4_BIT_MASK);
3311                 if (!mask)
3312                         continue;
3313                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3314                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3315                         if (mask & (0x1 << j))
3316                                 reta_conf[idx].reta[shift + j] =
3317                                         ((reta >> (CHAR_BIT * j)) &
3318                                                 IGB_8_BIT_MASK);
3319                 }
3320         }
3321
3322         return 0;
3323 }
3324
3325 #define MAC_TYPE_FILTER_SUP(type)    do {\
3326         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3327                 (type) != e1000_82576)\
3328                 return -ENOTSUP;\
3329 } while (0)
3330
3331 static int
3332 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3333                         struct rte_eth_syn_filter *filter,
3334                         bool add)
3335 {
3336         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         uint32_t synqf, rfctl;
3338
3339         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3340                 return -EINVAL;
3341
3342         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3343
3344         if (add) {
3345                 if (synqf & E1000_SYN_FILTER_ENABLE)
3346                         return -EINVAL;
3347
3348                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3349                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3350
3351                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3352                 if (filter->hig_pri)
3353                         rfctl |= E1000_RFCTL_SYNQFP;
3354                 else
3355                         rfctl &= ~E1000_RFCTL_SYNQFP;
3356
3357                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3358         } else {
3359                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3360                         return -ENOENT;
3361                 synqf = 0;
3362         }
3363
3364         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3365         E1000_WRITE_FLUSH(hw);
3366         return 0;
3367 }
3368
3369 static int
3370 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3371                         struct rte_eth_syn_filter *filter)
3372 {
3373         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         uint32_t synqf, rfctl;
3375
3376         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3377         if (synqf & E1000_SYN_FILTER_ENABLE) {
3378                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3379                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3380                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3381                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3382                 return 0;
3383         }
3384
3385         return -ENOENT;
3386 }
3387
3388 static int
3389 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3390                         enum rte_filter_op filter_op,
3391                         void *arg)
3392 {
3393         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3394         int ret;
3395
3396         MAC_TYPE_FILTER_SUP(hw->mac.type);
3397
3398         if (filter_op == RTE_ETH_FILTER_NOP)
3399                 return 0;
3400
3401         if (arg == NULL) {
3402                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3403                             filter_op);
3404                 return -EINVAL;
3405         }
3406
3407         switch (filter_op) {
3408         case RTE_ETH_FILTER_ADD:
3409                 ret = eth_igb_syn_filter_set(dev,
3410                                 (struct rte_eth_syn_filter *)arg,
3411                                 TRUE);
3412                 break;
3413         case RTE_ETH_FILTER_DELETE:
3414                 ret = eth_igb_syn_filter_set(dev,
3415                                 (struct rte_eth_syn_filter *)arg,
3416                                 FALSE);
3417                 break;
3418         case RTE_ETH_FILTER_GET:
3419                 ret = eth_igb_syn_filter_get(dev,
3420                                 (struct rte_eth_syn_filter *)arg);
3421                 break;
3422         default:
3423                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3424                 ret = -EINVAL;
3425                 break;
3426         }
3427
3428         return ret;
3429 }
3430
3431 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3432         if ((type) != e1000_82580 && (type) != e1000_i350)\
3433                 return -ENOSYS; \
3434 } while (0)
3435
3436 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3437 static inline int
3438 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3439                         struct e1000_2tuple_filter_info *filter_info)
3440 {
3441         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3442                 return -EINVAL;
3443         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3444                 return -EINVAL;  /* filter index is out of range. */
3445         if (filter->tcp_flags > TCP_FLAG_ALL)
3446                 return -EINVAL;  /* flags is invalid. */
3447
3448         switch (filter->dst_port_mask) {
3449         case UINT16_MAX:
3450                 filter_info->dst_port_mask = 0;
3451                 filter_info->dst_port = filter->dst_port;
3452                 break;
3453         case 0:
3454                 filter_info->dst_port_mask = 1;
3455                 break;
3456         default:
3457                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3458                 return -EINVAL;
3459         }
3460
3461         switch (filter->proto_mask) {
3462         case UINT8_MAX:
3463                 filter_info->proto_mask = 0;
3464                 filter_info->proto = filter->proto;
3465                 break;
3466         case 0:
3467                 filter_info->proto_mask = 1;
3468                 break;
3469         default:
3470                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3471                 return -EINVAL;
3472         }
3473
3474         filter_info->priority = (uint8_t)filter->priority;
3475         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3476                 filter_info->tcp_flags = filter->tcp_flags;
3477         else
3478                 filter_info->tcp_flags = 0;
3479
3480         return 0;
3481 }
3482
3483 static inline struct e1000_2tuple_filter *
3484 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3485                         struct e1000_2tuple_filter_info *key)
3486 {
3487         struct e1000_2tuple_filter *it;
3488
3489         TAILQ_FOREACH(it, filter_list, entries) {
3490                 if (memcmp(key, &it->filter_info,
3491                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3492                         return it;
3493                 }
3494         }
3495         return NULL;
3496 }
3497
3498 /*
3499  * igb_add_2tuple_filter - add a 2tuple filter
3500  *
3501  * @param
3502  * dev: Pointer to struct rte_eth_dev.
3503  * ntuple_filter: ponter to the filter that will be added.
3504  *
3505  * @return
3506  *    - On success, zero.
3507  *    - On failure, a negative value.
3508  */
3509 static int
3510 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3511                         struct rte_eth_ntuple_filter *ntuple_filter)
3512 {
3513         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         struct e1000_filter_info *filter_info =
3515                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3516         struct e1000_2tuple_filter *filter;
3517         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3518         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3519         int i, ret;
3520
3521         filter = rte_zmalloc("e1000_2tuple_filter",
3522                         sizeof(struct e1000_2tuple_filter), 0);
3523         if (filter == NULL)
3524                 return -ENOMEM;
3525
3526         ret = ntuple_filter_to_2tuple(ntuple_filter,
3527                                       &filter->filter_info);
3528         if (ret < 0) {
3529                 rte_free(filter);
3530                 return ret;
3531         }
3532         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3533                                          &filter->filter_info) != NULL) {
3534                 PMD_DRV_LOG(ERR, "filter exists.");
3535                 rte_free(filter);
3536                 return -EEXIST;
3537         }
3538         filter->queue = ntuple_filter->queue;
3539
3540         /*
3541          * look for an unused 2tuple filter index,
3542          * and insert the filter to list.
3543          */
3544         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3545                 if (!(filter_info->twotuple_mask & (1 << i))) {
3546                         filter_info->twotuple_mask |= 1 << i;
3547                         filter->index = i;
3548                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3549                                           filter,
3550                                           entries);
3551                         break;
3552                 }
3553         }
3554         if (i >= E1000_MAX_TTQF_FILTERS) {
3555                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3556                 rte_free(filter);
3557                 return -ENOSYS;
3558         }
3559
3560         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3561         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3562                 imir |= E1000_IMIR_PORT_BP;
3563         else
3564                 imir &= ~E1000_IMIR_PORT_BP;
3565
3566         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3567
3568         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3569         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3570         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3571         if (filter->filter_info.proto_mask == 0)
3572                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3573
3574         /* tcp flags bits setting. */
3575         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3576                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3577                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3578                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3579                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3580                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3581                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3582                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3583                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3584                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3585                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3586                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3587                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3588         } else
3589                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3590         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3591         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3592         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3593         return 0;
3594 }
3595
3596 /*
3597  * igb_remove_2tuple_filter - remove a 2tuple filter
3598  *
3599  * @param
3600  * dev: Pointer to struct rte_eth_dev.
3601  * ntuple_filter: ponter to the filter that will be removed.
3602  *
3603  * @return
3604  *    - On success, zero.
3605  *    - On failure, a negative value.
3606  */
3607 static int
3608 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3609                         struct rte_eth_ntuple_filter *ntuple_filter)
3610 {
3611         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612         struct e1000_filter_info *filter_info =
3613                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3614         struct e1000_2tuple_filter_info filter_2tuple;
3615         struct e1000_2tuple_filter *filter;
3616         int ret;
3617
3618         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3619         ret = ntuple_filter_to_2tuple(ntuple_filter,
3620                                       &filter_2tuple);
3621         if (ret < 0)
3622                 return ret;
3623
3624         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3625                                          &filter_2tuple);
3626         if (filter == NULL) {
3627                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3628                 return -ENOENT;
3629         }
3630
3631         filter_info->twotuple_mask &= ~(1 << filter->index);
3632         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3633         rte_free(filter);
3634
3635         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3636         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3637         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3638         return 0;
3639 }
3640
3641 static inline struct e1000_flex_filter *
3642 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3643                         struct e1000_flex_filter_info *key)
3644 {
3645         struct e1000_flex_filter *it;
3646
3647         TAILQ_FOREACH(it, filter_list, entries) {
3648                 if (memcmp(key, &it->filter_info,
3649                         sizeof(struct e1000_flex_filter_info)) == 0)
3650                         return it;
3651         }
3652
3653         return NULL;
3654 }
3655
3656 static int
3657 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3658                         struct rte_eth_flex_filter *filter,
3659                         bool add)
3660 {
3661         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662         struct e1000_filter_info *filter_info =
3663                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3664         struct e1000_flex_filter *flex_filter, *it;
3665         uint32_t wufc, queueing, mask;
3666         uint32_t reg_off;
3667         uint8_t shift, i, j = 0;
3668
3669         flex_filter = rte_zmalloc("e1000_flex_filter",
3670                         sizeof(struct e1000_flex_filter), 0);
3671         if (flex_filter == NULL)
3672                 return -ENOMEM;
3673
3674         flex_filter->filter_info.len = filter->len;
3675         flex_filter->filter_info.priority = filter->priority;
3676         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3677         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3678                 mask = 0;
3679                 /* reverse bits in flex filter's mask*/
3680                 for (shift = 0; shift < CHAR_BIT; shift++) {
3681                         if (filter->mask[i] & (0x01 << shift))
3682                                 mask |= (0x80 >> shift);
3683                 }
3684                 flex_filter->filter_info.mask[i] = mask;
3685         }
3686
3687         wufc = E1000_READ_REG(hw, E1000_WUFC);
3688         if (flex_filter->index < E1000_MAX_FHFT)
3689                 reg_off = E1000_FHFT(flex_filter->index);
3690         else
3691                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3692
3693         if (add) {
3694                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3695                                 &flex_filter->filter_info) != NULL) {
3696                         PMD_DRV_LOG(ERR, "filter exists.");
3697                         rte_free(flex_filter);
3698                         return -EEXIST;
3699                 }
3700                 flex_filter->queue = filter->queue;
3701                 /*
3702                  * look for an unused flex filter index
3703                  * and insert the filter into the list.
3704                  */
3705                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3706                         if (!(filter_info->flex_mask & (1 << i))) {
3707                                 filter_info->flex_mask |= 1 << i;
3708                                 flex_filter->index = i;
3709                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3710                                         flex_filter,
3711                                         entries);
3712                                 break;
3713                         }
3714                 }
3715                 if (i >= E1000_MAX_FLEX_FILTERS) {
3716                         PMD_DRV_LOG(ERR, "flex filters are full.");
3717                         rte_free(flex_filter);
3718                         return -ENOSYS;
3719                 }
3720
3721                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3722                                 (E1000_WUFC_FLX0 << flex_filter->index));
3723                 queueing = filter->len |
3724                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3725                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3726                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3727                                 queueing);
3728                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3729                         E1000_WRITE_REG(hw, reg_off,
3730                                         flex_filter->filter_info.dwords[j]);
3731                         reg_off += sizeof(uint32_t);
3732                         E1000_WRITE_REG(hw, reg_off,
3733                                         flex_filter->filter_info.dwords[++j]);
3734                         reg_off += sizeof(uint32_t);
3735                         E1000_WRITE_REG(hw, reg_off,
3736                                 (uint32_t)flex_filter->filter_info.mask[i]);
3737                         reg_off += sizeof(uint32_t) * 2;
3738                         ++j;
3739                 }
3740         } else {
3741                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3742                                 &flex_filter->filter_info);
3743                 if (it == NULL) {
3744                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3745                         rte_free(flex_filter);
3746                         return -ENOENT;
3747                 }
3748
3749                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3750                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3751                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3752                         (~(E1000_WUFC_FLX0 << it->index)));
3753
3754                 filter_info->flex_mask &= ~(1 << it->index);
3755                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3756                 rte_free(it);
3757                 rte_free(flex_filter);
3758         }
3759
3760         return 0;
3761 }
3762
3763 static int
3764 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3765                         struct rte_eth_flex_filter *filter)
3766 {
3767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3768         struct e1000_filter_info *filter_info =
3769                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3770         struct e1000_flex_filter flex_filter, *it;
3771         uint32_t wufc, queueing, wufc_en = 0;
3772
3773         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3774         flex_filter.filter_info.len = filter->len;
3775         flex_filter.filter_info.priority = filter->priority;
3776         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3777         memcpy(flex_filter.filter_info.mask, filter->mask,
3778                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3779
3780         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3781                                 &flex_filter.filter_info);
3782         if (it == NULL) {
3783                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3784                 return -ENOENT;
3785         }
3786
3787         wufc = E1000_READ_REG(hw, E1000_WUFC);
3788         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3789
3790         if ((wufc & wufc_en) == wufc_en) {
3791                 uint32_t reg_off = 0;
3792                 if (it->index < E1000_MAX_FHFT)
3793                         reg_off = E1000_FHFT(it->index);
3794                 else
3795                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3796
3797                 queueing = E1000_READ_REG(hw,
3798                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3799                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3800                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3801                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3802                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3803                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3804                 return 0;
3805         }
3806         return -ENOENT;
3807 }
3808
3809 static int
3810 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3811                         enum rte_filter_op filter_op,
3812                         void *arg)
3813 {
3814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         struct rte_eth_flex_filter *filter;
3816         int ret = 0;
3817
3818         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3819
3820         if (filter_op == RTE_ETH_FILTER_NOP)
3821                 return ret;
3822
3823         if (arg == NULL) {
3824                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3825                             filter_op);
3826                 return -EINVAL;
3827         }
3828
3829         filter = (struct rte_eth_flex_filter *)arg;
3830         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3831             || filter->len % sizeof(uint64_t) != 0) {
3832                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3833                 return -EINVAL;
3834         }
3835         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3836                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3837                 return -EINVAL;
3838         }
3839
3840         switch (filter_op) {
3841         case RTE_ETH_FILTER_ADD:
3842                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3843                 break;
3844         case RTE_ETH_FILTER_DELETE:
3845                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3846                 break;
3847         case RTE_ETH_FILTER_GET:
3848                 ret = eth_igb_get_flex_filter(dev, filter);
3849                 break;
3850         default:
3851                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3852                 ret = -EINVAL;
3853                 break;
3854         }
3855
3856         return ret;
3857 }
3858
3859 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3860 static inline int
3861 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3862                         struct e1000_5tuple_filter_info *filter_info)
3863 {
3864         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3865                 return -EINVAL;
3866         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3867                 return -EINVAL;  /* filter index is out of range. */
3868         if (filter->tcp_flags > TCP_FLAG_ALL)
3869                 return -EINVAL;  /* flags is invalid. */
3870
3871         switch (filter->dst_ip_mask) {
3872         case UINT32_MAX:
3873                 filter_info->dst_ip_mask = 0;
3874                 filter_info->dst_ip = filter->dst_ip;
3875                 break;
3876         case 0:
3877                 filter_info->dst_ip_mask = 1;
3878                 break;
3879         default:
3880                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3881                 return -EINVAL;
3882         }
3883
3884         switch (filter->src_ip_mask) {
3885         case UINT32_MAX:
3886                 filter_info->src_ip_mask = 0;
3887                 filter_info->src_ip = filter->src_ip;
3888                 break;
3889         case 0:
3890                 filter_info->src_ip_mask = 1;
3891                 break;
3892         default:
3893                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3894                 return -EINVAL;
3895         }
3896
3897         switch (filter->dst_port_mask) {
3898         case UINT16_MAX:
3899                 filter_info->dst_port_mask = 0;
3900                 filter_info->dst_port = filter->dst_port;
3901                 break;
3902         case 0:
3903                 filter_info->dst_port_mask = 1;
3904                 break;
3905         default:
3906                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3907                 return -EINVAL;
3908         }
3909
3910         switch (filter->src_port_mask) {
3911         case UINT16_MAX:
3912                 filter_info->src_port_mask = 0;
3913                 filter_info->src_port = filter->src_port;
3914                 break;
3915         case 0:
3916                 filter_info->src_port_mask = 1;
3917                 break;
3918         default:
3919                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3920                 return -EINVAL;
3921         }
3922
3923         switch (filter->proto_mask) {
3924         case UINT8_MAX:
3925                 filter_info->proto_mask = 0;
3926                 filter_info->proto = filter->proto;
3927                 break;
3928         case 0:
3929                 filter_info->proto_mask = 1;
3930                 break;
3931         default:
3932                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3933                 return -EINVAL;
3934         }
3935
3936         filter_info->priority = (uint8_t)filter->priority;
3937         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3938                 filter_info->tcp_flags = filter->tcp_flags;
3939         else
3940                 filter_info->tcp_flags = 0;
3941
3942         return 0;
3943 }
3944
3945 static inline struct e1000_5tuple_filter *
3946 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3947                         struct e1000_5tuple_filter_info *key)
3948 {
3949         struct e1000_5tuple_filter *it;
3950
3951         TAILQ_FOREACH(it, filter_list, entries) {
3952                 if (memcmp(key, &it->filter_info,
3953                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3954                         return it;
3955                 }
3956         }
3957         return NULL;
3958 }
3959
3960 /*
3961  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3962  *
3963  * @param
3964  * dev: Pointer to struct rte_eth_dev.
3965  * ntuple_filter: ponter to the filter that will be added.
3966  *
3967  * @return
3968  *    - On success, zero.
3969  *    - On failure, a negative value.
3970  */
3971 static int
3972 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3973                         struct rte_eth_ntuple_filter *ntuple_filter)
3974 {
3975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3976         struct e1000_filter_info *filter_info =
3977                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3978         struct e1000_5tuple_filter *filter;
3979         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3980         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3981         uint8_t i;
3982         int ret;
3983
3984         filter = rte_zmalloc("e1000_5tuple_filter",
3985                         sizeof(struct e1000_5tuple_filter), 0);
3986         if (filter == NULL)
3987                 return -ENOMEM;
3988
3989         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3990                                             &filter->filter_info);
3991         if (ret < 0) {
3992                 rte_free(filter);
3993                 return ret;
3994         }
3995
3996         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3997                                          &filter->filter_info) != NULL) {
3998                 PMD_DRV_LOG(ERR, "filter exists.");
3999                 rte_free(filter);
4000                 return -EEXIST;
4001         }
4002         filter->queue = ntuple_filter->queue;
4003
4004         /*
4005          * look for an unused 5tuple filter index,
4006          * and insert the filter to list.
4007          */
4008         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4009                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4010                         filter_info->fivetuple_mask |= 1 << i;
4011                         filter->index = i;
4012                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4013                                           filter,
4014                                           entries);
4015                         break;
4016                 }
4017         }
4018         if (i >= E1000_MAX_FTQF_FILTERS) {
4019                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4020                 rte_free(filter);
4021                 return -ENOSYS;
4022         }
4023
4024         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4025         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4026                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4027         if (filter->filter_info.dst_ip_mask == 0)
4028                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4029         if (filter->filter_info.src_port_mask == 0)
4030                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4031         if (filter->filter_info.proto_mask == 0)
4032                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4033         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4034                 E1000_FTQF_QUEUE_MASK;
4035         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4036         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4037         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4038         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4039
4040         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4041         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4042
4043         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4044         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4045                 imir |= E1000_IMIR_PORT_BP;
4046         else
4047                 imir &= ~E1000_IMIR_PORT_BP;
4048         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4049
4050         /* tcp flags bits setting. */
4051         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4052                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4053                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4054                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4055                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4056                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4057                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4058                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4059                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4060                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4061                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4062                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4063                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4064         } else
4065                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4066         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4067         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4068         return 0;
4069 }
4070
4071 /*
4072  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4073  *
4074  * @param
4075  * dev: Pointer to struct rte_eth_dev.
4076  * ntuple_filter: ponter to the filter that will be removed.
4077  *
4078  * @return
4079  *    - On success, zero.
4080  *    - On failure, a negative value.
4081  */
4082 static int
4083 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4084                                 struct rte_eth_ntuple_filter *ntuple_filter)
4085 {
4086         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087         struct e1000_filter_info *filter_info =
4088                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4089         struct e1000_5tuple_filter_info filter_5tuple;
4090         struct e1000_5tuple_filter *filter;
4091         int ret;
4092
4093         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4094         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4095                                             &filter_5tuple);
4096         if (ret < 0)
4097                 return ret;
4098
4099         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4100                                          &filter_5tuple);
4101         if (filter == NULL) {
4102                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4103                 return -ENOENT;
4104         }
4105
4106         filter_info->fivetuple_mask &= ~(1 << filter->index);
4107         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4108         rte_free(filter);
4109
4110         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4111                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4112         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4113         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4114         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4115         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4116         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4117         return 0;
4118 }
4119
4120 static int
4121 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4122 {
4123         uint32_t rctl;
4124         struct e1000_hw *hw;
4125         struct rte_eth_dev_info dev_info;
4126         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4127                                      VLAN_TAG_SIZE);
4128
4129         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130
4131 #ifdef RTE_LIBRTE_82571_SUPPORT
4132         /* XXX: not bigger than max_rx_pktlen */
4133         if (hw->mac.type == e1000_82571)
4134                 return -ENOTSUP;
4135 #endif
4136         eth_igb_infos_get(dev, &dev_info);
4137
4138         /* check that mtu is within the allowed range */
4139         if ((mtu < ETHER_MIN_MTU) ||
4140             (frame_size > dev_info.max_rx_pktlen))
4141                 return -EINVAL;
4142
4143         /* refuse mtu that requires the support of scattered packets when this
4144          * feature has not been enabled before. */
4145         if (!dev->data->scattered_rx &&
4146             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4147                 return -EINVAL;
4148
4149         rctl = E1000_READ_REG(hw, E1000_RCTL);
4150
4151         /* switch to jumbo mode if needed */
4152         if (frame_size > ETHER_MAX_LEN) {
4153                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4154                 rctl |= E1000_RCTL_LPE;
4155         } else {
4156                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4157                 rctl &= ~E1000_RCTL_LPE;
4158         }
4159         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4160
4161         /* update max frame size */
4162         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4163
4164         E1000_WRITE_REG(hw, E1000_RLPML,
4165                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4166
4167         return 0;
4168 }
4169
4170 /*
4171  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4172  *
4173  * @param
4174  * dev: Pointer to struct rte_eth_dev.
4175  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4176  * add: if true, add filter, if false, remove filter
4177  *
4178  * @return
4179  *    - On success, zero.
4180  *    - On failure, a negative value.
4181  */
4182 static int
4183 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4184                         struct rte_eth_ntuple_filter *ntuple_filter,
4185                         bool add)
4186 {
4187         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         int ret;
4189
4190         switch (ntuple_filter->flags) {
4191         case RTE_5TUPLE_FLAGS:
4192         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4193                 if (hw->mac.type != e1000_82576)
4194                         return -ENOTSUP;
4195                 if (add)
4196                         ret = igb_add_5tuple_filter_82576(dev,
4197                                                           ntuple_filter);
4198                 else
4199                         ret = igb_remove_5tuple_filter_82576(dev,
4200                                                              ntuple_filter);
4201                 break;
4202         case RTE_2TUPLE_FLAGS:
4203         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4204                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4205                         return -ENOTSUP;
4206                 if (add)
4207                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4208                 else
4209                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4210                 break;
4211         default:
4212                 ret = -EINVAL;
4213                 break;
4214         }
4215
4216         return ret;
4217 }
4218
4219 /*
4220  * igb_get_ntuple_filter - get a ntuple filter
4221  *
4222  * @param
4223  * dev: Pointer to struct rte_eth_dev.
4224  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4225  *
4226  * @return
4227  *    - On success, zero.
4228  *    - On failure, a negative value.
4229  */
4230 static int
4231 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4232                         struct rte_eth_ntuple_filter *ntuple_filter)
4233 {
4234         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235         struct e1000_filter_info *filter_info =
4236                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4237         struct e1000_5tuple_filter_info filter_5tuple;
4238         struct e1000_2tuple_filter_info filter_2tuple;
4239         struct e1000_5tuple_filter *p_5tuple_filter;
4240         struct e1000_2tuple_filter *p_2tuple_filter;
4241         int ret;
4242
4243         switch (ntuple_filter->flags) {
4244         case RTE_5TUPLE_FLAGS:
4245         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4246                 if (hw->mac.type != e1000_82576)
4247                         return -ENOTSUP;
4248                 memset(&filter_5tuple,
4249                         0,
4250                         sizeof(struct e1000_5tuple_filter_info));
4251                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4252                                                     &filter_5tuple);
4253                 if (ret < 0)
4254                         return ret;
4255                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4256                                         &filter_info->fivetuple_list,
4257                                         &filter_5tuple);
4258                 if (p_5tuple_filter == NULL) {
4259                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4260                         return -ENOENT;
4261                 }
4262                 ntuple_filter->queue = p_5tuple_filter->queue;
4263                 break;
4264         case RTE_2TUPLE_FLAGS:
4265         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4266                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4267                         return -ENOTSUP;
4268                 memset(&filter_2tuple,
4269                         0,
4270                         sizeof(struct e1000_2tuple_filter_info));
4271                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4272                 if (ret < 0)
4273                         return ret;
4274                 p_2tuple_filter = igb_2tuple_filter_lookup(
4275                                         &filter_info->twotuple_list,
4276                                         &filter_2tuple);
4277                 if (p_2tuple_filter == NULL) {
4278                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4279                         return -ENOENT;
4280                 }
4281                 ntuple_filter->queue = p_2tuple_filter->queue;
4282                 break;
4283         default:
4284                 ret = -EINVAL;
4285                 break;
4286         }
4287
4288         return 0;
4289 }
4290
4291 /*
4292  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4293  * @dev: pointer to rte_eth_dev structure
4294  * @filter_op:operation will be taken.
4295  * @arg: a pointer to specific structure corresponding to the filter_op
4296  */
4297 static int
4298 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4299                                 enum rte_filter_op filter_op,
4300                                 void *arg)
4301 {
4302         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4303         int ret;
4304
4305         MAC_TYPE_FILTER_SUP(hw->mac.type);
4306
4307         if (filter_op == RTE_ETH_FILTER_NOP)
4308                 return 0;
4309
4310         if (arg == NULL) {
4311                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4312                             filter_op);
4313                 return -EINVAL;
4314         }
4315
4316         switch (filter_op) {
4317         case RTE_ETH_FILTER_ADD:
4318                 ret = igb_add_del_ntuple_filter(dev,
4319                         (struct rte_eth_ntuple_filter *)arg,
4320                         TRUE);
4321                 break;
4322         case RTE_ETH_FILTER_DELETE:
4323                 ret = igb_add_del_ntuple_filter(dev,
4324                         (struct rte_eth_ntuple_filter *)arg,
4325                         FALSE);
4326                 break;
4327         case RTE_ETH_FILTER_GET:
4328                 ret = igb_get_ntuple_filter(dev,
4329                         (struct rte_eth_ntuple_filter *)arg);
4330                 break;
4331         default:
4332                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4333                 ret = -EINVAL;
4334                 break;
4335         }
4336         return ret;
4337 }
4338
4339 static inline int
4340 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4341                         uint16_t ethertype)
4342 {
4343         int i;
4344
4345         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4346                 if (filter_info->ethertype_filters[i] == ethertype &&
4347                     (filter_info->ethertype_mask & (1 << i)))
4348                         return i;
4349         }
4350         return -1;
4351 }
4352
4353 static inline int
4354 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4355                         uint16_t ethertype)
4356 {
4357         int i;
4358
4359         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4360                 if (!(filter_info->ethertype_mask & (1 << i))) {
4361                         filter_info->ethertype_mask |= 1 << i;
4362                         filter_info->ethertype_filters[i] = ethertype;
4363                         return i;
4364                 }
4365         }
4366         return -1;
4367 }
4368
4369 static inline int
4370 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4371                         uint8_t idx)
4372 {
4373         if (idx >= E1000_MAX_ETQF_FILTERS)
4374                 return -1;
4375         filter_info->ethertype_mask &= ~(1 << idx);
4376         filter_info->ethertype_filters[idx] = 0;
4377         return idx;
4378 }
4379
4380
4381 static int
4382 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4383                         struct rte_eth_ethertype_filter *filter,
4384                         bool add)
4385 {
4386         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387         struct e1000_filter_info *filter_info =
4388                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4389         uint32_t etqf = 0;
4390         int ret;
4391
4392         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4393                 filter->ether_type == ETHER_TYPE_IPv6) {
4394                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4395                         " ethertype filter.", filter->ether_type);
4396                 return -EINVAL;
4397         }
4398
4399         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4400                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4401                 return -EINVAL;
4402         }
4403         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4404                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4405                 return -EINVAL;
4406         }
4407
4408         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4409         if (ret >= 0 && add) {
4410                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4411                             filter->ether_type);
4412                 return -EEXIST;
4413         }
4414         if (ret < 0 && !add) {
4415                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4416                             filter->ether_type);
4417                 return -ENOENT;
4418         }
4419
4420         if (add) {
4421                 ret = igb_ethertype_filter_insert(filter_info,
4422                         filter->ether_type);
4423                 if (ret < 0) {
4424                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4425                         return -ENOSYS;
4426                 }
4427
4428                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4429                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4430                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4431         } else {
4432                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4433                 if (ret < 0)
4434                         return -ENOSYS;
4435         }
4436         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4437         E1000_WRITE_FLUSH(hw);
4438
4439         return 0;
4440 }
4441
4442 static int
4443 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4444                         struct rte_eth_ethertype_filter *filter)
4445 {
4446         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         struct e1000_filter_info *filter_info =
4448                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4449         uint32_t etqf;
4450         int ret;
4451
4452         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4453         if (ret < 0) {
4454                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4455                             filter->ether_type);
4456                 return -ENOENT;
4457         }
4458
4459         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4460         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4461                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4462                 filter->flags = 0;
4463                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4464                                 E1000_ETQF_QUEUE_SHIFT;
4465                 return 0;
4466         }
4467
4468         return -ENOENT;
4469 }
4470
4471 /*
4472  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4473  * @dev: pointer to rte_eth_dev structure
4474  * @filter_op:operation will be taken.
4475  * @arg: a pointer to specific structure corresponding to the filter_op
4476  */
4477 static int
4478 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4479                                 enum rte_filter_op filter_op,
4480                                 void *arg)
4481 {
4482         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4483         int ret;
4484
4485         MAC_TYPE_FILTER_SUP(hw->mac.type);
4486
4487         if (filter_op == RTE_ETH_FILTER_NOP)
4488                 return 0;
4489
4490         if (arg == NULL) {
4491                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4492                             filter_op);
4493                 return -EINVAL;
4494         }
4495
4496         switch (filter_op) {
4497         case RTE_ETH_FILTER_ADD:
4498                 ret = igb_add_del_ethertype_filter(dev,
4499                         (struct rte_eth_ethertype_filter *)arg,
4500                         TRUE);
4501                 break;
4502         case RTE_ETH_FILTER_DELETE:
4503                 ret = igb_add_del_ethertype_filter(dev,
4504                         (struct rte_eth_ethertype_filter *)arg,
4505                         FALSE);
4506                 break;
4507         case RTE_ETH_FILTER_GET:
4508                 ret = igb_get_ethertype_filter(dev,
4509                         (struct rte_eth_ethertype_filter *)arg);
4510                 break;
4511         default:
4512                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4513                 ret = -EINVAL;
4514                 break;
4515         }
4516         return ret;
4517 }
4518
4519 static int
4520 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4521                      enum rte_filter_type filter_type,
4522                      enum rte_filter_op filter_op,
4523                      void *arg)
4524 {
4525         int ret = -EINVAL;
4526
4527         switch (filter_type) {
4528         case RTE_ETH_FILTER_NTUPLE:
4529                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4530                 break;
4531         case RTE_ETH_FILTER_ETHERTYPE:
4532                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4533                 break;
4534         case RTE_ETH_FILTER_SYN:
4535                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4536                 break;
4537         case RTE_ETH_FILTER_FLEXIBLE:
4538                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4539                 break;
4540         default:
4541                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4542                                                         filter_type);
4543                 break;
4544         }
4545
4546         return ret;
4547 }
4548
4549 static int
4550 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4551                          struct ether_addr *mc_addr_set,
4552                          uint32_t nb_mc_addr)
4553 {
4554         struct e1000_hw *hw;
4555
4556         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4557         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4558         return 0;
4559 }
4560
4561 static uint64_t
4562 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4563 {
4564         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565         uint64_t systime_cycles;
4566
4567         switch (hw->mac.type) {
4568         case e1000_i210:
4569         case e1000_i211:
4570                 /*
4571                  * Need to read System Time Residue Register to be able
4572                  * to read the other two registers.
4573                  */
4574                 E1000_READ_REG(hw, E1000_SYSTIMR);
4575                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4576                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4577                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4578                                 * NSEC_PER_SEC;
4579                 break;
4580         case e1000_82580:
4581         case e1000_i350:
4582         case e1000_i354:
4583                 /*
4584                  * Need to read System Time Residue Register to be able
4585                  * to read the other two registers.
4586                  */
4587                 E1000_READ_REG(hw, E1000_SYSTIMR);
4588                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4589                 /* Only the 8 LSB are valid. */
4590                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4591                                 & 0xff) << 32;
4592                 break;
4593         default:
4594                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4595                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4596                                 << 32;
4597                 break;
4598         }
4599
4600         return systime_cycles;
4601 }
4602
4603 static uint64_t
4604 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4605 {
4606         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607         uint64_t rx_tstamp_cycles;
4608
4609         switch (hw->mac.type) {
4610         case e1000_i210:
4611         case e1000_i211:
4612                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4613                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4614                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4615                                 * NSEC_PER_SEC;
4616                 break;
4617         case e1000_82580:
4618         case e1000_i350:
4619         case e1000_i354:
4620                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4621                 /* Only the 8 LSB are valid. */
4622                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4623                                 & 0xff) << 32;
4624                 break;
4625         default:
4626                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4627                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4628                                 << 32;
4629                 break;
4630         }
4631
4632         return rx_tstamp_cycles;
4633 }
4634
4635 static uint64_t
4636 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4637 {
4638         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4639         uint64_t tx_tstamp_cycles;
4640
4641         switch (hw->mac.type) {
4642         case e1000_i210:
4643         case e1000_i211:
4644                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4645                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4646                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4647                                 * NSEC_PER_SEC;
4648                 break;
4649         case e1000_82580:
4650         case e1000_i350:
4651         case e1000_i354:
4652                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4653                 /* Only the 8 LSB are valid. */
4654                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4655                                 & 0xff) << 32;
4656                 break;
4657         default:
4658                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4659                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4660                                 << 32;
4661                 break;
4662         }
4663
4664         return tx_tstamp_cycles;
4665 }
4666
4667 static void
4668 igb_start_timecounters(struct rte_eth_dev *dev)
4669 {
4670         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671         struct e1000_adapter *adapter =
4672                 (struct e1000_adapter *)dev->data->dev_private;
4673         uint32_t incval = 1;
4674         uint32_t shift = 0;
4675         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4676
4677         switch (hw->mac.type) {
4678         case e1000_82580:
4679         case e1000_i350:
4680         case e1000_i354:
4681                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4682                 mask = (1ULL << 40) - 1;
4683                 /* fall-through */
4684         case e1000_i210:
4685         case e1000_i211:
4686                 /*
4687                  * Start incrementing the register
4688                  * used to timestamp PTP packets.
4689                  */
4690                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4691                 break;
4692         case e1000_82576:
4693                 incval = E1000_INCVALUE_82576;
4694                 shift = IGB_82576_TSYNC_SHIFT;
4695                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4696                                 E1000_INCPERIOD_82576 | incval);
4697                 break;
4698         default:
4699                 /* Not supported */
4700                 return;
4701         }
4702
4703         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4704         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4705         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4706
4707         adapter->systime_tc.cc_mask = mask;
4708         adapter->systime_tc.cc_shift = shift;
4709         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4710
4711         adapter->rx_tstamp_tc.cc_mask = mask;
4712         adapter->rx_tstamp_tc.cc_shift = shift;
4713         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4714
4715         adapter->tx_tstamp_tc.cc_mask = mask;
4716         adapter->tx_tstamp_tc.cc_shift = shift;
4717         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4718 }
4719
4720 static int
4721 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4722 {
4723         struct e1000_adapter *adapter =
4724                         (struct e1000_adapter *)dev->data->dev_private;
4725
4726         adapter->systime_tc.nsec += delta;
4727         adapter->rx_tstamp_tc.nsec += delta;
4728         adapter->tx_tstamp_tc.nsec += delta;
4729
4730         return 0;
4731 }
4732
4733 static int
4734 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4735 {
4736         uint64_t ns;
4737         struct e1000_adapter *adapter =
4738                         (struct e1000_adapter *)dev->data->dev_private;
4739
4740         ns = rte_timespec_to_ns(ts);
4741
4742         /* Set the timecounters to a new value. */
4743         adapter->systime_tc.nsec = ns;
4744         adapter->rx_tstamp_tc.nsec = ns;
4745         adapter->tx_tstamp_tc.nsec = ns;
4746
4747         return 0;
4748 }
4749
4750 static int
4751 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4752 {
4753         uint64_t ns, systime_cycles;
4754         struct e1000_adapter *adapter =
4755                         (struct e1000_adapter *)dev->data->dev_private;
4756
4757         systime_cycles = igb_read_systime_cyclecounter(dev);
4758         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4759         *ts = rte_ns_to_timespec(ns);
4760
4761         return 0;
4762 }
4763
4764 static int
4765 igb_timesync_enable(struct rte_eth_dev *dev)
4766 {
4767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4768         uint32_t tsync_ctl;
4769         uint32_t tsauxc;
4770
4771         /* Stop the timesync system time. */
4772         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4773         /* Reset the timesync system time value. */
4774         switch (hw->mac.type) {
4775         case e1000_82580:
4776         case e1000_i350:
4777         case e1000_i354:
4778         case e1000_i210:
4779         case e1000_i211:
4780                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4781                 /* fall-through */
4782         case e1000_82576:
4783                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4784                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4785                 break;
4786         default:
4787                 /* Not supported. */
4788                 return -ENOTSUP;
4789         }
4790
4791         /* Enable system time for it isn't on by default. */
4792         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4793         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4794         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4795
4796         igb_start_timecounters(dev);
4797
4798         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4799         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4800                         (ETHER_TYPE_1588 |
4801                          E1000_ETQF_FILTER_ENABLE |
4802                          E1000_ETQF_1588));
4803
4804         /* Enable timestamping of received PTP packets. */
4805         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4806         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4807         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4808
4809         /* Enable Timestamping of transmitted PTP packets. */
4810         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4811         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4812         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4813
4814         return 0;
4815 }
4816
4817 static int
4818 igb_timesync_disable(struct rte_eth_dev *dev)
4819 {
4820         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4821         uint32_t tsync_ctl;
4822
4823         /* Disable timestamping of transmitted PTP packets. */
4824         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4825         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4826         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4827
4828         /* Disable timestamping of received PTP packets. */
4829         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4830         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4831         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4832
4833         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4834         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4835
4836         /* Stop incrementating the System Time registers. */
4837         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4838
4839         return 0;
4840 }
4841
4842 static int
4843 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4844                                struct timespec *timestamp,
4845                                uint32_t flags __rte_unused)
4846 {
4847         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         struct e1000_adapter *adapter =
4849                         (struct e1000_adapter *)dev->data->dev_private;
4850         uint32_t tsync_rxctl;
4851         uint64_t rx_tstamp_cycles;
4852         uint64_t ns;
4853
4854         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4855         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4856                 return -EINVAL;
4857
4858         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4859         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4860         *timestamp = rte_ns_to_timespec(ns);
4861
4862         return  0;
4863 }
4864
4865 static int
4866 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4867                                struct timespec *timestamp)
4868 {
4869         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4870         struct e1000_adapter *adapter =
4871                         (struct e1000_adapter *)dev->data->dev_private;
4872         uint32_t tsync_txctl;
4873         uint64_t tx_tstamp_cycles;
4874         uint64_t ns;
4875
4876         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4877         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4878                 return -EINVAL;
4879
4880         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
4881         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4882         *timestamp = rte_ns_to_timespec(ns);
4883
4884         return  0;
4885 }
4886
4887 static int
4888 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4889 {
4890         int count = 0;
4891         int g_ind = 0;
4892         const struct reg_info *reg_group;
4893
4894         while ((reg_group = igb_regs[g_ind++]))
4895                 count += igb_reg_group_count(reg_group);
4896
4897         return count;
4898 }
4899
4900 static int
4901 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4902 {
4903         int count = 0;
4904         int g_ind = 0;
4905         const struct reg_info *reg_group;
4906
4907         while ((reg_group = igbvf_regs[g_ind++]))
4908                 count += igb_reg_group_count(reg_group);
4909
4910         return count;
4911 }
4912
4913 static int
4914 eth_igb_get_regs(struct rte_eth_dev *dev,
4915         struct rte_dev_reg_info *regs)
4916 {
4917         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918         uint32_t *data = regs->data;
4919         int g_ind = 0;
4920         int count = 0;
4921         const struct reg_info *reg_group;
4922
4923         /* Support only full register dump */
4924         if ((regs->length == 0) ||
4925             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4926                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4927                         hw->device_id;
4928                 while ((reg_group = igb_regs[g_ind++]))
4929                         count += igb_read_regs_group(dev, &data[count],
4930                                                         reg_group);
4931                 return 0;
4932         }
4933
4934         return -ENOTSUP;
4935 }
4936
4937 static int
4938 igbvf_get_regs(struct rte_eth_dev *dev,
4939         struct rte_dev_reg_info *regs)
4940 {
4941         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942         uint32_t *data = regs->data;
4943         int g_ind = 0;
4944         int count = 0;
4945         const struct reg_info *reg_group;
4946
4947         /* Support only full register dump */
4948         if ((regs->length == 0) ||
4949             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4950                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4951                         hw->device_id;
4952                 while ((reg_group = igbvf_regs[g_ind++]))
4953                         count += igb_read_regs_group(dev, &data[count],
4954                                                         reg_group);
4955                 return 0;
4956         }
4957
4958         return -ENOTSUP;
4959 }
4960
4961 static int
4962 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4963 {
4964         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965
4966         /* Return unit is byte count */
4967         return hw->nvm.word_size * 2;
4968 }
4969
4970 static int
4971 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4972         struct rte_dev_eeprom_info *in_eeprom)
4973 {
4974         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975         struct e1000_nvm_info *nvm = &hw->nvm;
4976         uint16_t *data = in_eeprom->data;
4977         int first, length;
4978
4979         first = in_eeprom->offset >> 1;
4980         length = in_eeprom->length >> 1;
4981         if ((first >= hw->nvm.word_size) ||
4982             ((first + length) >= hw->nvm.word_size))
4983                 return -EINVAL;
4984
4985         in_eeprom->magic = hw->vendor_id |
4986                 ((uint32_t)hw->device_id << 16);
4987
4988         if ((nvm->ops.read) == NULL)
4989                 return -ENOTSUP;
4990
4991         return nvm->ops.read(hw, first, length, data);
4992 }
4993
4994 static int
4995 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4996         struct rte_dev_eeprom_info *in_eeprom)
4997 {
4998         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4999         struct e1000_nvm_info *nvm = &hw->nvm;
5000         uint16_t *data = in_eeprom->data;
5001         int first, length;
5002
5003         first = in_eeprom->offset >> 1;
5004         length = in_eeprom->length >> 1;
5005         if ((first >= hw->nvm.word_size) ||
5006             ((first + length) >= hw->nvm.word_size))
5007                 return -EINVAL;
5008
5009         in_eeprom->magic = (uint32_t)hw->vendor_id |
5010                 ((uint32_t)hw->device_id << 16);
5011
5012         if ((nvm->ops.write) == NULL)
5013                 return -ENOTSUP;
5014         return nvm->ops.write(hw,  first, length, data);
5015 }
5016
5017 static struct rte_driver pmd_igb_drv = {
5018         .type = PMD_PDEV,
5019         .init = rte_igb_pmd_init,
5020 };
5021
5022 static struct rte_driver pmd_igbvf_drv = {
5023         .type = PMD_PDEV,
5024         .init = rte_igbvf_pmd_init,
5025 };
5026
5027 static int
5028 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5029 {
5030         struct e1000_hw *hw =
5031                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5032         uint32_t mask = 1 << queue_id;
5033
5034         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5035         E1000_WRITE_FLUSH(hw);
5036
5037         return 0;
5038 }
5039
5040 static int
5041 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5042 {
5043         struct e1000_hw *hw =
5044                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         uint32_t mask = 1 << queue_id;
5046         uint32_t regval;
5047
5048         regval = E1000_READ_REG(hw, E1000_EIMS);
5049         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5050         E1000_WRITE_FLUSH(hw);
5051
5052         rte_intr_enable(&dev->pci_dev->intr_handle);
5053
5054         return 0;
5055 }
5056
5057 static void
5058 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5059                    uint8_t index, uint8_t offset)
5060 {
5061         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5062
5063         /* clear bits */
5064         val &= ~((uint32_t)0xFF << offset);
5065
5066         /* write vector and valid bit */
5067         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5068
5069         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5070 }
5071
5072 static void
5073 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5074                            uint8_t queue, uint8_t msix_vector)
5075 {
5076         uint32_t tmp = 0;
5077
5078         if (hw->mac.type == e1000_82575) {
5079                 if (direction == 0)
5080                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5081                 else if (direction == 1)
5082                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5083                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5084         } else if (hw->mac.type == e1000_82576) {
5085                 if ((direction == 0) || (direction == 1))
5086                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5087                                            ((queue & 0x8) << 1) +
5088                                            8 * direction);
5089         } else if ((hw->mac.type == e1000_82580) ||
5090                         (hw->mac.type == e1000_i350) ||
5091                         (hw->mac.type == e1000_i354) ||
5092                         (hw->mac.type == e1000_i210) ||
5093                         (hw->mac.type == e1000_i211)) {
5094                 if ((direction == 0) || (direction == 1))
5095                         eth_igb_write_ivar(hw, msix_vector,
5096                                            queue >> 1,
5097                                            ((queue & 0x1) << 4) +
5098                                            8 * direction);
5099         }
5100 }
5101
5102 /* Sets up the hardware to generate MSI-X interrupts properly
5103  * @hw
5104  *  board private structure
5105  */
5106 static void
5107 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5108 {
5109         int queue_id;
5110         uint32_t tmpval, regval, intr_mask;
5111         struct e1000_hw *hw =
5112                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5113         uint32_t vec = E1000_MISC_VEC_ID;
5114         uint32_t base = E1000_MISC_VEC_ID;
5115         uint32_t misc_shift = 0;
5116
5117         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
5118
5119         /* won't configure msix register if no mapping is done
5120          * between intr vector and event fd
5121          */
5122         if (!rte_intr_dp_is_en(intr_handle))
5123                 return;
5124
5125         if (rte_intr_allow_others(intr_handle)) {
5126                 vec = base = E1000_RX_VEC_START;
5127                 misc_shift = 1;
5128         }
5129
5130         /* set interrupt vector for other causes */
5131         if (hw->mac.type == e1000_82575) {
5132                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5133                 /* enable MSI-X PBA support */
5134                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5135
5136                 /* Auto-Mask interrupts upon ICR read */
5137                 tmpval |= E1000_CTRL_EXT_EIAME;
5138                 tmpval |= E1000_CTRL_EXT_IRCA;
5139
5140                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5141
5142                 /* enable msix_other interrupt */
5143                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5144                 regval = E1000_READ_REG(hw, E1000_EIAC);
5145                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5146                 regval = E1000_READ_REG(hw, E1000_EIAM);
5147                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5148         } else if ((hw->mac.type == e1000_82576) ||
5149                         (hw->mac.type == e1000_82580) ||
5150                         (hw->mac.type == e1000_i350) ||
5151                         (hw->mac.type == e1000_i354) ||
5152                         (hw->mac.type == e1000_i210) ||
5153                         (hw->mac.type == e1000_i211)) {
5154                 /* turn on MSI-X capability first */
5155                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5156                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5157                                         E1000_GPIE_NSICR);
5158                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5159                         misc_shift;
5160                 regval = E1000_READ_REG(hw, E1000_EIAC);
5161                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5162
5163                 /* enable msix_other interrupt */
5164                 regval = E1000_READ_REG(hw, E1000_EIMS);
5165                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5166                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5167                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5168         }
5169
5170         /* use EIAM to auto-mask when MSI-X interrupt
5171          * is asserted, this saves a register write for every interrupt
5172          */
5173         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5174                 misc_shift;
5175         regval = E1000_READ_REG(hw, E1000_EIAM);
5176         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5177
5178         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5179                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5180                 intr_handle->intr_vec[queue_id] = vec;
5181                 if (vec < base + intr_handle->nb_efd - 1)
5182                         vec++;
5183         }
5184
5185         E1000_WRITE_FLUSH(hw);
5186 }
5187
5188 PMD_REGISTER_DRIVER(pmd_igb_drv);
5189 PMD_REGISTER_DRIVER(pmd_igbvf_drv);