drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64
  65 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  66 #define IGB_DEFAULT_RX_HTHRESH      8
  67 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  68
  69 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  70 #define IGB_DEFAULT_TX_HTHRESH      1
  71 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  72
  73 #define IGB_HKEY_MAX_INDEX 10
  74
  75 /* Bit shift and mask */
  76 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  77 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  78 #define IGB_8_BIT_WIDTH  CHAR_BIT
  79 #define IGB_8_BIT_MASK   UINT8_MAX
  80
  81 /* Additional timesync values. */
  82 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  83 #define E1000_ETQF_FILTER_1588       3
  84 #define IGB_82576_TSYNC_SHIFT        16
  85 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  86 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  87 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  88
  89 #define E1000_VTIVAR_MISC                0x01740
  90 #define E1000_VTIVAR_MISC_MASK           0xFF
  91 #define E1000_VTIVAR_VALID               0x80
  92 #define E1000_VTIVAR_MISC_MAILBOX        0
  93 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  94
  95 /* External VLAN Enable bit mask */
  96 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  97
  98 /* External VLAN Ether Type bit mask and shift */
  99 #define E1000_VET_VET_EXT            0xFFFF0000
 100 #define E1000_VET_VET_EXT_SHIFT      16
 101
 102 static int  eth_igb_configure(struct rte_eth_dev *dev);
 103 static int  eth_igb_start(struct rte_eth_dev *dev);
 104 static void eth_igb_stop(struct rte_eth_dev *dev);
 105 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 107 static void eth_igb_close(struct rte_eth_dev *dev);
 108 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 110 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 112 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 113                                 int wait_to_complete);
 114 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 115                                 struct rte_eth_stats *rte_stats);
 116 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 117                               struct rte_eth_xstat *xstats, unsigned n);
 118 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 119                                     struct rte_eth_xstat_name *xstats_names,
 120                                     unsigned limit);
 121 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 122 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 123 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 124                                    char *fw_version, size_t fw_size);
 125 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 126                               struct rte_eth_dev_info *dev_info);
 127 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 128 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 129                                 struct rte_eth_dev_info *dev_info);
 130 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 131                                 struct rte_eth_fc_conf *fc_conf);
 132 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 133                                 struct rte_eth_fc_conf *fc_conf);
 134 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 135 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 136 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 137 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 138                                     struct rte_intr_handle *handle);
 139 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 140                                                         void *param);
 141 static int  igb_hardware_init(struct e1000_hw *hw);
 142 static void igb_hw_control_acquire(struct e1000_hw *hw);
 143 static void igb_hw_control_release(struct e1000_hw *hw);
 144 static void igb_init_manageability(struct e1000_hw *hw);
 145 static void igb_release_manageability(struct e1000_hw *hw);
 146
 147 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 148
 149 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 150                 uint16_t vlan_id, int on);
 151 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 152                                  enum rte_vlan_type vlan_type,
 153                                  uint16_t tpid_id);
 154 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 155
 156 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 157 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 158 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 159 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 160 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 161 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 162
 163 static int eth_igb_led_on(struct rte_eth_dev *dev);
 164 static int eth_igb_led_off(struct rte_eth_dev *dev);
 165
 166 static void igb_intr_disable(struct e1000_hw *hw);
 167 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 168 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 169                 struct ether_addr *mac_addr,
 170                 uint32_t index, uint32_t pool);
 171 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 172 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 173                 struct ether_addr *addr);
 174
 175 static void igbvf_intr_disable(struct e1000_hw *hw);
 176 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 177 static int igbvf_dev_start(struct rte_eth_dev *dev);
 178 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 179 static void igbvf_dev_close(struct rte_eth_dev *dev);
 180 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int eth_igbvf_link_update(struct e1000_hw *hw);
 185 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 186                                 struct rte_eth_stats *rte_stats);
 187 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 188                                 struct rte_eth_xstat *xstats, unsigned n);
 189 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 190                                       struct rte_eth_xstat_name *xstats_names,
 191                                       unsigned limit);
 192 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 193 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 194                 uint16_t vlan_id, int on);
 195 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 196 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 197 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 198                 struct ether_addr *addr);
 199 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 200 static int igbvf_get_regs(struct rte_eth_dev *dev,
 201                 struct rte_dev_reg_info *regs);
 202
 203 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 204                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 205                                    uint16_t reta_size);
 206 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 207                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 208                                   uint16_t reta_size);
 209
 210 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 211                         struct rte_eth_syn_filter *filter,
 212                         bool add);
 213 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 214                         struct rte_eth_syn_filter *filter);
 215 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 216                         enum rte_filter_op filter_op,
 217                         void *arg);
 218 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 219                         struct rte_eth_ntuple_filter *ntuple_filter);
 220 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 221                         struct rte_eth_ntuple_filter *ntuple_filter);
 222 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 223                         struct rte_eth_flex_filter *filter,
 224                         bool add);
 225 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 226                         struct rte_eth_flex_filter *filter);
 227 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 228                         enum rte_filter_op filter_op,
 229                         void *arg);
 230 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 231                         struct rte_eth_ntuple_filter *ntuple_filter);
 232 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 233                         struct rte_eth_ntuple_filter *ntuple_filter);
 234 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 235                         struct rte_eth_ntuple_filter *filter,
 236                         bool add);
 237 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 238                         struct rte_eth_ntuple_filter *filter);
 239 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 240                                 enum rte_filter_op filter_op,
 241                                 void *arg);
 242 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 243                         struct rte_eth_ethertype_filter *filter,
 244                         bool add);
 245 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter);
 250 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 251                      enum rte_filter_type filter_type,
 252                      enum rte_filter_op filter_op,
 253                      void *arg);
 254 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 255 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 256                 struct rte_dev_reg_info *regs);
 257 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 258 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 259                 struct rte_dev_eeprom_info *eeprom);
 260 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 261                 struct rte_dev_eeprom_info *eeprom);
 262 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 263                                     struct ether_addr *mc_addr_set,
 264                                     uint32_t nb_mc_addr);
 265 static int igb_timesync_enable(struct rte_eth_dev *dev);
 266 static int igb_timesync_disable(struct rte_eth_dev *dev);
 267 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 268                                           struct timespec *timestamp,
 269                                           uint32_t flags);
 270 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 271                                           struct timespec *timestamp);
 272 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 273 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 274                                   struct timespec *timestamp);
 275 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 276                                    const struct timespec *timestamp);
 277 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                         uint16_t queue_id);
 279 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                          uint16_t queue_id);
 281 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 282                                        uint8_t queue, uint8_t msix_vector);
 283 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 284                                uint8_t index, uint8_t offset);
 285 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 286 static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
 287                                         void *param);
 288 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 289
 290 /*
 291  * Define VF Stats MACRO for Non "cleared on read" register
 292  */
 293 #define UPDATE_VF_STAT(reg, last, cur)            \
 294 {                                                 \
 295         u32 latest = E1000_READ_REG(hw, reg);     \
 296         cur += (latest - last) & UINT_MAX;        \
 297         last = latest;                            \
 298 }
 299
 300 #define IGB_FC_PAUSE_TIME 0x0680
 301 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 302 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 303
 304 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 305
 306 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 307
 308 /*
 309  * The set of PCI devices this driver supports
 310  */
 311 static const struct rte_pci_id pci_id_igb_map[] = {
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 320
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 324
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 330         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 331
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 337         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 351         { .vendor_id = 0, /* sentinel */ },
 352 };
 353
 354 /*
 355  * The set of PCI devices this driver supports (for 82576&I350 VF)
 356  */
 357 static const struct rte_pci_id pci_id_igbvf_map[] = {
 358         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 359         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 360         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 361         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 362         { .vendor_id = 0, /* sentinel */ },
 363 };
 364
 365 static const struct rte_eth_desc_lim rx_desc_lim = {
 366         .nb_max = E1000_MAX_RING_DESC,
 367         .nb_min = E1000_MIN_RING_DESC,
 368         .nb_align = IGB_RXD_ALIGN,
 369 };
 370
 371 static const struct rte_eth_desc_lim tx_desc_lim = {
 372         .nb_max = E1000_MAX_RING_DESC,
 373         .nb_min = E1000_MIN_RING_DESC,
 374         .nb_align = IGB_RXD_ALIGN,
 375         .nb_seg_max = IGB_TX_MAX_SEG,
 376         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 377 };
 378
 379 static const struct eth_dev_ops eth_igb_ops = {
 380         .dev_configure        = eth_igb_configure,
 381         .dev_start            = eth_igb_start,
 382         .dev_stop             = eth_igb_stop,
 383         .dev_set_link_up      = eth_igb_dev_set_link_up,
 384         .dev_set_link_down    = eth_igb_dev_set_link_down,
 385         .dev_close            = eth_igb_close,
 386         .promiscuous_enable   = eth_igb_promiscuous_enable,
 387         .promiscuous_disable  = eth_igb_promiscuous_disable,
 388         .allmulticast_enable  = eth_igb_allmulticast_enable,
 389         .allmulticast_disable = eth_igb_allmulticast_disable,
 390         .link_update          = eth_igb_link_update,
 391         .stats_get            = eth_igb_stats_get,
 392         .xstats_get           = eth_igb_xstats_get,
 393         .xstats_get_names     = eth_igb_xstats_get_names,
 394         .stats_reset          = eth_igb_stats_reset,
 395         .xstats_reset         = eth_igb_xstats_reset,
 396         .fw_version_get       = eth_igb_fw_version_get,
 397         .dev_infos_get        = eth_igb_infos_get,
 398         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 399         .mtu_set              = eth_igb_mtu_set,
 400         .vlan_filter_set      = eth_igb_vlan_filter_set,
 401         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 402         .vlan_offload_set     = eth_igb_vlan_offload_set,
 403         .rx_queue_setup       = eth_igb_rx_queue_setup,
 404         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 405         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 406         .rx_queue_release     = eth_igb_rx_queue_release,
 407         .rx_queue_count       = eth_igb_rx_queue_count,
 408         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 409         .tx_queue_setup       = eth_igb_tx_queue_setup,
 410         .tx_queue_release     = eth_igb_tx_queue_release,
 411         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 412         .dev_led_on           = eth_igb_led_on,
 413         .dev_led_off          = eth_igb_led_off,
 414         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 415         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 416         .mac_addr_add         = eth_igb_rar_set,
 417         .mac_addr_remove      = eth_igb_rar_clear,
 418         .mac_addr_set         = eth_igb_default_mac_addr_set,
 419         .reta_update          = eth_igb_rss_reta_update,
 420         .reta_query           = eth_igb_rss_reta_query,
 421         .rss_hash_update      = eth_igb_rss_hash_update,
 422         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 423         .filter_ctrl          = eth_igb_filter_ctrl,
 424         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 425         .rxq_info_get         = igb_rxq_info_get,
 426         .txq_info_get         = igb_txq_info_get,
 427         .timesync_enable      = igb_timesync_enable,
 428         .timesync_disable     = igb_timesync_disable,
 429         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 430         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 431         .get_reg              = eth_igb_get_regs,
 432         .get_eeprom_length    = eth_igb_get_eeprom_length,
 433         .get_eeprom           = eth_igb_get_eeprom,
 434         .set_eeprom           = eth_igb_set_eeprom,
 435         .timesync_adjust_time = igb_timesync_adjust_time,
 436         .timesync_read_time   = igb_timesync_read_time,
 437         .timesync_write_time  = igb_timesync_write_time,
 438 };
 439
 440 /*
 441  * dev_ops for virtual function, bare necessities for basic vf
 442  * operation have been implemented
 443  */
 444 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 445         .dev_configure        = igbvf_dev_configure,
 446         .dev_start            = igbvf_dev_start,
 447         .dev_stop             = igbvf_dev_stop,
 448         .dev_close            = igbvf_dev_close,
 449         .promiscuous_enable   = igbvf_promiscuous_enable,
 450         .promiscuous_disable  = igbvf_promiscuous_disable,
 451         .allmulticast_enable  = igbvf_allmulticast_enable,
 452         .allmulticast_disable = igbvf_allmulticast_disable,
 453         .link_update          = eth_igb_link_update,
 454         .stats_get            = eth_igbvf_stats_get,
 455         .xstats_get           = eth_igbvf_xstats_get,
 456         .xstats_get_names     = eth_igbvf_xstats_get_names,
 457         .stats_reset          = eth_igbvf_stats_reset,
 458         .xstats_reset         = eth_igbvf_stats_reset,
 459         .vlan_filter_set      = igbvf_vlan_filter_set,
 460         .dev_infos_get        = eth_igbvf_infos_get,
 461         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 462         .rx_queue_setup       = eth_igb_rx_queue_setup,
 463         .rx_queue_release     = eth_igb_rx_queue_release,
 464         .tx_queue_setup       = eth_igb_tx_queue_setup,
 465         .tx_queue_release     = eth_igb_tx_queue_release,
 466         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 467         .rxq_info_get         = igb_rxq_info_get,
 468         .txq_info_get         = igb_txq_info_get,
 469         .mac_addr_set         = igbvf_default_mac_addr_set,
 470         .get_reg              = igbvf_get_regs,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_igb_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 480         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 481         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 482         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 483         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 484         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 485         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 486         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 487                 ecol)},
 488         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 489         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 490         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 491         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 492         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 493         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 494         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 495         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 496         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 497         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 498         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 499                 fcruc)},
 500         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 501         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 502         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 503         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 504         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 505                 prc1023)},
 506         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 507                 prc1522)},
 508         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 509         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 510         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 511         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 512         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 513         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 514         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 515         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 516         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 517         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 518         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 519         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 520         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 521         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 522         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 523         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 524         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 525         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 526                 ptc1023)},
 527         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 528                 ptc1522)},
 529         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 530         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 531         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 532         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 533         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 534         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 535         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 536
 537         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 538 };
 539
 540 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 541                 sizeof(rte_igb_stats_strings[0]))
 542
 543 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 544         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 545         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 546         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 547         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 548         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 549 };
 550
 551 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 552                 sizeof(rte_igbvf_stats_strings[0]))
 553
 554 /**
 555  * Atomically reads the link status information from global
 556  * structure rte_eth_dev.
 557  *
 558  * @param dev
 559  *   - Pointer to the structure rte_eth_dev to read from.
 560  *   - Pointer to the buffer to be saved with the link status.
 561  *
 562  * @return
 563  *   - On success, zero.
 564  *   - On failure, negative value.
 565  */
 566 static inline int
 567 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 568                                 struct rte_eth_link *link)
 569 {
 570         struct rte_eth_link *dst = link;
 571         struct rte_eth_link *src = &(dev->data->dev_link);
 572
 573         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 574                                         *(uint64_t *)src) == 0)
 575                 return -1;
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * Atomically writes the link status information into global
 582  * structure rte_eth_dev.
 583  *
 584  * @param dev
 585  *   - Pointer to the structure rte_eth_dev to read from.
 586  *   - Pointer to the buffer to be saved with the link status.
 587  *
 588  * @return
 589  *   - On success, zero.
 590  *   - On failure, negative value.
 591  */
 592 static inline int
 593 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 594                                 struct rte_eth_link *link)
 595 {
 596         struct rte_eth_link *dst = &(dev->data->dev_link);
 597         struct rte_eth_link *src = link;
 598
 599         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 600                                         *(uint64_t *)src) == 0)
 601                 return -1;
 602
 603         return 0;
 604 }
 605
 606 static inline void
 607 igb_intr_enable(struct rte_eth_dev *dev)
 608 {
 609         struct e1000_interrupt *intr =
 610                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 611         struct e1000_hw *hw =
 612                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 613
 614         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 615         E1000_WRITE_FLUSH(hw);
 616 }
 617
 618 static void
 619 igb_intr_disable(struct e1000_hw *hw)
 620 {
 621         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 622         E1000_WRITE_FLUSH(hw);
 623 }
 624
 625 static inline void
 626 igbvf_intr_enable(struct rte_eth_dev *dev)
 627 {
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630
 631         /* only for mailbox */
 632         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 633         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 634         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 635         E1000_WRITE_FLUSH(hw);
 636 }
 637
 638 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 639 static void
 640 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 641 {
 642         uint32_t tmp = 0;
 643
 644         /* mailbox */
 645         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 646         tmp |= E1000_VTIVAR_VALID;
 647         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 648 }
 649
 650 static void
 651 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 652 {
 653         struct e1000_hw *hw =
 654                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655
 656         /* Configure VF other cause ivar */
 657         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 658 }
 659
 660 static inline int32_t
 661 igb_pf_reset_hw(struct e1000_hw *hw)
 662 {
 663         uint32_t ctrl_ext;
 664         int32_t status;
 665
 666         status = e1000_reset_hw(hw);
 667
 668         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 669         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 670         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 671         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 672         E1000_WRITE_FLUSH(hw);
 673
 674         return status;
 675 }
 676
 677 static void
 678 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 679 {
 680         struct e1000_hw *hw =
 681                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 682
 683
 684         hw->vendor_id = pci_dev->id.vendor_id;
 685         hw->device_id = pci_dev->id.device_id;
 686         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 687         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 688
 689         e1000_set_mac_type(hw);
 690
 691         /* need to check if it is a vf device below */
 692 }
 693
 694 static int
 695 igb_reset_swfw_lock(struct e1000_hw *hw)
 696 {
 697         int ret_val;
 698
 699         /*
 700          * Do mac ops initialization manually here, since we will need
 701          * some function pointers set by this call.
 702          */
 703         ret_val = e1000_init_mac_params(hw);
 704         if (ret_val)
 705                 return ret_val;
 706
 707         /*
 708          * SMBI lock should not fail in this early stage. If this is the case,
 709          * it is due to an improper exit of the application.
 710          * So force the release of the faulty lock.
 711          */
 712         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 714         }
 715         e1000_put_hw_semaphore_generic(hw);
 716
 717         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 718                 uint16_t mask;
 719
 720                 /*
 721                  * Phy lock should not fail in this early stage. If this is the case,
 722                  * it is due to an improper exit of the application.
 723                  * So force the release of the faulty lock.
 724                  */
 725                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 726                 if (hw->bus.func > E1000_FUNC_1)
 727                         mask <<= 2;
 728                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 729                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 730                                     hw->bus.func);
 731                 }
 732                 hw->mac.ops.release_swfw_sync(hw, mask);
 733
 734                 /*
 735                  * This one is more tricky since it is common to all ports; but
 736                  * swfw_sync retries last long enough (1s) to be almost sure that if
 737                  * lock can not be taken it is due to an improper lock of the
 738                  * semaphore.
 739                  */
 740                 mask = E1000_SWFW_EEP_SM;
 741                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 742                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 743                 }
 744                 hw->mac.ops.release_swfw_sync(hw, mask);
 745         }
 746
 747         return E1000_SUCCESS;
 748 }
 749
 750 static int
 751 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 752 {
 753         int error = 0;
 754         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
 755         struct e1000_hw *hw =
 756                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 757         struct e1000_vfta * shadow_vfta =
 758                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 759         struct e1000_filter_info *filter_info =
 760                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 761         struct e1000_adapter *adapter =
 762                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 763
 764         uint32_t ctrl_ext;
 765
 766         eth_dev->dev_ops = &eth_igb_ops;
 767         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 768         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 769         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 770
 771         /* for secondary processes, we don't initialise any further as primary
 772          * has already done this work. Only check we don't need a different
 773          * RX function */
 774         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 775                 if (eth_dev->data->scattered_rx)
 776                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 777                 return 0;
 778         }
 779
 780         rte_eth_copy_pci_info(eth_dev, pci_dev);
 781         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 782
 783         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 784
 785         igb_identify_hardware(eth_dev, pci_dev);
 786         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 787                 error = -EIO;
 788                 goto err_late;
 789         }
 790
 791         e1000_get_bus_info(hw);
 792
 793         /* Reset any pending lock */
 794         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 795                 error = -EIO;
 796                 goto err_late;
 797         }
 798
 799         /* Finish initialization */
 800         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 801                 error = -EIO;
 802                 goto err_late;
 803         }
 804
 805         hw->mac.autoneg = 1;
 806         hw->phy.autoneg_wait_to_complete = 0;
 807         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 808
 809         /* Copper options */
 810         if (hw->phy.media_type == e1000_media_type_copper) {
 811                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 812                 hw->phy.disable_polarity_correction = 0;
 813                 hw->phy.ms_type = e1000_ms_hw_default;
 814         }
 815
 816         /*
 817          * Start from a known state, this is important in reading the nvm
 818          * and mac from that.
 819          */
 820         igb_pf_reset_hw(hw);
 821
 822         /* Make sure we have a good EEPROM before we read from it */
 823         if (e1000_validate_nvm_checksum(hw) < 0) {
 824                 /*
 825                  * Some PCI-E parts fail the first check due to
 826                  * the link being in sleep state, call it again,
 827                  * if it fails a second time its a real issue.
 828                  */
 829                 if (e1000_validate_nvm_checksum(hw) < 0) {
 830                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 831                         error = -EIO;
 832                         goto err_late;
 833                 }
 834         }
 835
 836         /* Read the permanent MAC address out of the EEPROM */
 837         if (e1000_read_mac_addr(hw) != 0) {
 838                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 839                 error = -EIO;
 840                 goto err_late;
 841         }
 842
 843         /* Allocate memory for storing MAC addresses */
 844         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 845                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 846         if (eth_dev->data->mac_addrs == NULL) {
 847                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 848                                                 "store MAC addresses",
 849                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 850                 error = -ENOMEM;
 851                 goto err_late;
 852         }
 853
 854         /* Copy the permanent MAC address */
 855         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 856
 857         /* initialize the vfta */
 858         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 859
 860         /* Now initialize the hardware */
 861         if (igb_hardware_init(hw) != 0) {
 862                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 863                 rte_free(eth_dev->data->mac_addrs);
 864                 eth_dev->data->mac_addrs = NULL;
 865                 error = -ENODEV;
 866                 goto err_late;
 867         }
 868         hw->mac.get_link_status = 1;
 869         adapter->stopped = 0;
 870
 871         /* Indicate SOL/IDER usage */
 872         if (e1000_check_reset_block(hw) < 0) {
 873                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 874                                         "SOL/IDER session");
 875         }
 876
 877         /* initialize PF if max_vfs not zero */
 878         igb_pf_host_init(eth_dev);
 879
 880         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 881         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 882         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 883         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 884         E1000_WRITE_FLUSH(hw);
 885
 886         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 887                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 888                      pci_dev->id.device_id);
 889
 890         rte_intr_callback_register(&pci_dev->intr_handle,
 891                                    eth_igb_interrupt_handler,
 892                                    (void *)eth_dev);
 893
 894         /* enable uio/vfio intr/eventfd mapping */
 895         rte_intr_enable(&pci_dev->intr_handle);
 896
 897         /* enable support intr */
 898         igb_intr_enable(eth_dev);
 899
 900         TAILQ_INIT(&filter_info->flex_list);
 901         filter_info->flex_mask = 0;
 902         TAILQ_INIT(&filter_info->twotuple_list);
 903         filter_info->twotuple_mask = 0;
 904         TAILQ_INIT(&filter_info->fivetuple_list);
 905         filter_info->fivetuple_mask = 0;
 906
 907         return 0;
 908
 909 err_late:
 910         igb_hw_control_release(hw);
 911
 912         return error;
 913 }
 914
 915 static int
 916 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 917 {
 918         struct rte_pci_device *pci_dev;
 919         struct rte_intr_handle *intr_handle;
 920         struct e1000_hw *hw;
 921         struct e1000_adapter *adapter =
 922                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 923
 924         PMD_INIT_FUNC_TRACE();
 925
 926         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 927                 return -EPERM;
 928
 929         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 930         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 931         intr_handle = &pci_dev->intr_handle;
 932
 933         if (adapter->stopped == 0)
 934                 eth_igb_close(eth_dev);
 935
 936         eth_dev->dev_ops = NULL;
 937         eth_dev->rx_pkt_burst = NULL;
 938         eth_dev->tx_pkt_burst = NULL;
 939
 940         /* Reset any pending lock */
 941         igb_reset_swfw_lock(hw);
 942
 943         rte_free(eth_dev->data->mac_addrs);
 944         eth_dev->data->mac_addrs = NULL;
 945
 946         /* uninitialize PF if max_vfs not zero */
 947         igb_pf_host_uninit(eth_dev);
 948
 949         /* disable uio intr before callback unregister */
 950         rte_intr_disable(intr_handle);
 951         rte_intr_callback_unregister(intr_handle,
 952                                      eth_igb_interrupt_handler, eth_dev);
 953
 954         return 0;
 955 }
 956
 957 /*
 958  * Virtual Function device init
 959  */
 960 static int
 961 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 962 {
 963         struct rte_pci_device *pci_dev;
 964         struct rte_intr_handle *intr_handle;
 965         struct e1000_adapter *adapter =
 966                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 967         struct e1000_hw *hw =
 968                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 969         int diag;
 970         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 975         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 976         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 977         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 978
 979         /* for secondary processes, we don't initialise any further as primary
 980          * has already done this work. Only check we don't need a different
 981          * RX function */
 982         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 983                 if (eth_dev->data->scattered_rx)
 984                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 985                 return 0;
 986         }
 987
 988         pci_dev = E1000_DEV_TO_PCI(eth_dev);
 989         rte_eth_copy_pci_info(eth_dev, pci_dev);
 990         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 991
 992         hw->device_id = pci_dev->id.device_id;
 993         hw->vendor_id = pci_dev->id.vendor_id;
 994         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 995         adapter->stopped = 0;
 996
 997         /* Initialize the shared code (base driver) */
 998         diag = e1000_setup_init_funcs(hw, TRUE);
 999         if (diag != 0) {
1000                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1001                         diag);
1002                 return -EIO;
1003         }
1004
1005         /* init_mailbox_params */
1006         hw->mbx.ops.init_params(hw);
1007
1008         /* Disable the interrupts for VF */
1009         igbvf_intr_disable(hw);
1010
1011         diag = hw->mac.ops.reset_hw(hw);
1012
1013         /* Allocate memory for storing MAC addresses */
1014         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1015                 hw->mac.rar_entry_count, 0);
1016         if (eth_dev->data->mac_addrs == NULL) {
1017                 PMD_INIT_LOG(ERR,
1018                         "Failed to allocate %d bytes needed to store MAC "
1019                         "addresses",
1020                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1021                 return -ENOMEM;
1022         }
1023
1024         /* Generate a random MAC address, if none was assigned by PF. */
1025         if (is_zero_ether_addr(perm_addr)) {
1026                 eth_random_addr(perm_addr->addr_bytes);
1027                 diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1028                 if (diag) {
1029                         rte_free(eth_dev->data->mac_addrs);
1030                         eth_dev->data->mac_addrs = NULL;
1031                         return diag;
1032                 }
1033                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1034                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1035                              "%02x:%02x:%02x:%02x:%02x:%02x",
1036                              perm_addr->addr_bytes[0],
1037                              perm_addr->addr_bytes[1],
1038                              perm_addr->addr_bytes[2],
1039                              perm_addr->addr_bytes[3],
1040                              perm_addr->addr_bytes[4],
1041                              perm_addr->addr_bytes[5]);
1042         }
1043
1044         /* Copy the permanent MAC address */
1045         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1046                         &eth_dev->data->mac_addrs[0]);
1047
1048         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1049                      "mac.type=%s",
1050                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1051                      pci_dev->id.device_id, "igb_mac_82576_vf");
1052
1053         intr_handle = &pci_dev->intr_handle;
1054         rte_intr_callback_register(intr_handle,
1055                                    eth_igbvf_interrupt_handler, eth_dev);
1056
1057         return 0;
1058 }
1059
1060 static int
1061 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1062 {
1063         struct e1000_adapter *adapter =
1064                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1065         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(eth_dev);
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1070                 return -EPERM;
1071
1072         if (adapter->stopped == 0)
1073                 igbvf_dev_close(eth_dev);
1074
1075         eth_dev->dev_ops = NULL;
1076         eth_dev->rx_pkt_burst = NULL;
1077         eth_dev->tx_pkt_burst = NULL;
1078
1079         rte_free(eth_dev->data->mac_addrs);
1080         eth_dev->data->mac_addrs = NULL;
1081
1082         /* disable uio intr before callback unregister */
1083         rte_intr_disable(&pci_dev->intr_handle);
1084         rte_intr_callback_unregister(&pci_dev->intr_handle,
1085                                      eth_igbvf_interrupt_handler,
1086                                      (void *)eth_dev);
1087
1088         return 0;
1089 }
1090
1091 static struct eth_driver rte_igb_pmd = {
1092         .pci_drv = {
1093                 .id_table = pci_id_igb_map,
1094                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1095                 .probe = rte_eth_dev_pci_probe,
1096                 .remove = rte_eth_dev_pci_remove,
1097         },
1098         .eth_dev_init = eth_igb_dev_init,
1099         .eth_dev_uninit = eth_igb_dev_uninit,
1100         .dev_private_size = sizeof(struct e1000_adapter),
1101 };
1102
1103 /*
1104  * virtual function driver struct
1105  */
1106 static struct eth_driver rte_igbvf_pmd = {
1107         .pci_drv = {
1108                 .id_table = pci_id_igbvf_map,
1109                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1110                 .probe = rte_eth_dev_pci_probe,
1111                 .remove = rte_eth_dev_pci_remove,
1112         },
1113         .eth_dev_init = eth_igbvf_dev_init,
1114         .eth_dev_uninit = eth_igbvf_dev_uninit,
1115         .dev_private_size = sizeof(struct e1000_adapter),
1116 };
1117
1118 static void
1119 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1120 {
1121         struct e1000_hw *hw =
1122                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1123         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1124         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1125         rctl |= E1000_RCTL_VFE;
1126         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1127 }
1128
1129 static int
1130 igb_check_mq_mode(struct rte_eth_dev *dev)
1131 {
1132         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1133         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1134         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1135         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1136
1137         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1138             tx_mq_mode == ETH_MQ_TX_DCB ||
1139             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1140                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1141                 return -EINVAL;
1142         }
1143         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1144                 /* Check multi-queue mode.
1145                  * To no break software we accept ETH_MQ_RX_NONE as this might
1146                  * be used to turn off VLAN filter.
1147                  */
1148
1149                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1150                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1151                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1152                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1153                 } else {
1154                         /* Only support one queue on VFs.
1155                          * RSS together with SRIOV is not supported.
1156                          */
1157                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1158                                         " wrong mq_mode rx %d.",
1159                                         rx_mq_mode);
1160                         return -EINVAL;
1161                 }
1162                 /* TX mode is not used here, so mode might be ignored.*/
1163                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1164                         /* SRIOV only works in VMDq enable mode */
1165                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1166                                         " TX mode %d is not supported. "
1167                                         " Driver will behave as %d mode.",
1168                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1169                 }
1170
1171                 /* check valid queue number */
1172                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1173                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1174                                         " only support one queue on VFs.");
1175                         return -EINVAL;
1176                 }
1177         } else {
1178                 /* To no break software that set invalid mode, only display
1179                  * warning if invalid mode is used.
1180                  */
1181                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1182                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1183                     rx_mq_mode != ETH_MQ_RX_RSS) {
1184                         /* RSS together with VMDq not supported*/
1185                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1186                                      rx_mq_mode);
1187                         return -EINVAL;
1188                 }
1189
1190                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1191                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1192                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1193                                         " Due to txmode is meaningless in this"
1194                                         " driver, just ignore.",
1195                                         tx_mq_mode);
1196                 }
1197         }
1198         return 0;
1199 }
1200
1201 static int
1202 eth_igb_configure(struct rte_eth_dev *dev)
1203 {
1204         struct e1000_interrupt *intr =
1205                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1206         int ret;
1207
1208         PMD_INIT_FUNC_TRACE();
1209
1210         /* multipe queue mode checking */
1211         ret  = igb_check_mq_mode(dev);
1212         if (ret != 0) {
1213                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1214                             ret);
1215                 return ret;
1216         }
1217
1218         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1219         PMD_INIT_FUNC_TRACE();
1220
1221         return 0;
1222 }
1223
1224 static int
1225 eth_igb_start(struct rte_eth_dev *dev)
1226 {
1227         struct e1000_hw *hw =
1228                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1229         struct e1000_adapter *adapter =
1230                 E1000_DEV_PRIVATE(dev->data->dev_private);
1231         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1232         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1233         int ret, mask;
1234         uint32_t intr_vector = 0;
1235         uint32_t ctrl_ext;
1236         uint32_t *speeds;
1237         int num_speeds;
1238         bool autoneg;
1239
1240         PMD_INIT_FUNC_TRACE();
1241
1242         /* disable uio/vfio intr/eventfd mapping */
1243         rte_intr_disable(intr_handle);
1244
1245         /* Power up the phy. Needed to make the link go Up */
1246         eth_igb_dev_set_link_up(dev);
1247
1248         /*
1249          * Packet Buffer Allocation (PBA)
1250          * Writing PBA sets the receive portion of the buffer
1251          * the remainder is used for the transmit buffer.
1252          */
1253         if (hw->mac.type == e1000_82575) {
1254                 uint32_t pba;
1255
1256                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1257                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1258         }
1259
1260         /* Put the address into the Receive Address Array */
1261         e1000_rar_set(hw, hw->mac.addr, 0);
1262
1263         /* Initialize the hardware */
1264         if (igb_hardware_init(hw)) {
1265                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1266                 return -EIO;
1267         }
1268         adapter->stopped = 0;
1269
1270         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1271
1272         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1273         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1274         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1275         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1276         E1000_WRITE_FLUSH(hw);
1277
1278         /* configure PF module if SRIOV enabled */
1279         igb_pf_host_configure(dev);
1280
1281         /* check and configure queue intr-vector mapping */
1282         if ((rte_intr_cap_multiple(intr_handle) ||
1283              !RTE_ETH_DEV_SRIOV(dev).active) &&
1284             dev->data->dev_conf.intr_conf.rxq != 0) {
1285                 intr_vector = dev->data->nb_rx_queues;
1286                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1287                         return -1;
1288         }
1289
1290         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1291                 intr_handle->intr_vec =
1292                         rte_zmalloc("intr_vec",
1293                                     dev->data->nb_rx_queues * sizeof(int), 0);
1294                 if (intr_handle->intr_vec == NULL) {
1295                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1296                                      " intr_vec", dev->data->nb_rx_queues);
1297                         return -ENOMEM;
1298                 }
1299         }
1300
1301         /* confiugre msix for rx interrupt */
1302         eth_igb_configure_msix_intr(dev);
1303
1304         /* Configure for OS presence */
1305         igb_init_manageability(hw);
1306
1307         eth_igb_tx_init(dev);
1308
1309         /* This can fail when allocating mbufs for descriptor rings */
1310         ret = eth_igb_rx_init(dev);
1311         if (ret) {
1312                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1313                 igb_dev_clear_queues(dev);
1314                 return ret;
1315         }
1316
1317         e1000_clear_hw_cntrs_base_generic(hw);
1318
1319         /*
1320          * VLAN Offload Settings
1321          */
1322         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1323                         ETH_VLAN_EXTEND_MASK;
1324         eth_igb_vlan_offload_set(dev, mask);
1325
1326         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1327                 /* Enable VLAN filter since VMDq always use VLAN filter */
1328                 igb_vmdq_vlan_hw_filter_enable(dev);
1329         }
1330
1331         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1332                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1333                 (hw->mac.type == e1000_i211)) {
1334                 /* Configure EITR with the maximum possible value (0xFFFF) */
1335                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1336         }
1337
1338         /* Setup link speed and duplex */
1339         speeds = &dev->data->dev_conf.link_speeds;
1340         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1341                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1342                 hw->mac.autoneg = 1;
1343         } else {
1344                 num_speeds = 0;
1345                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1346
1347                 /* Reset */
1348                 hw->phy.autoneg_advertised = 0;
1349
1350                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1351                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1352                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1353                         num_speeds = -1;
1354                         goto error_invalid_config;
1355                 }
1356                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1357                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1358                         num_speeds++;
1359                 }
1360                 if (*speeds & ETH_LINK_SPEED_10M) {
1361                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1362                         num_speeds++;
1363                 }
1364                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1365                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1366                         num_speeds++;
1367                 }
1368                 if (*speeds & ETH_LINK_SPEED_100M) {
1369                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1370                         num_speeds++;
1371                 }
1372                 if (*speeds & ETH_LINK_SPEED_1G) {
1373                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1374                         num_speeds++;
1375                 }
1376                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1377                         goto error_invalid_config;
1378
1379                 /* Set/reset the mac.autoneg based on the link speed,
1380                  * fixed or not
1381                  */
1382                 if (!autoneg) {
1383                         hw->mac.autoneg = 0;
1384                         hw->mac.forced_speed_duplex =
1385                                         hw->phy.autoneg_advertised;
1386                 } else {
1387                         hw->mac.autoneg = 1;
1388                 }
1389         }
1390
1391         e1000_setup_link(hw);
1392
1393         if (rte_intr_allow_others(intr_handle)) {
1394                 /* check if lsc interrupt is enabled */
1395                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1396                         eth_igb_lsc_interrupt_setup(dev);
1397         } else {
1398                 rte_intr_callback_unregister(intr_handle,
1399                                              eth_igb_interrupt_handler,
1400                                              (void *)dev);
1401                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1402                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1403                                      " no intr multiplex");
1404         }
1405
1406         /* check if rxq interrupt is enabled */
1407         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1408             rte_intr_dp_is_en(intr_handle))
1409                 eth_igb_rxq_interrupt_setup(dev);
1410
1411         /* enable uio/vfio intr/eventfd mapping */
1412         rte_intr_enable(intr_handle);
1413
1414         /* resume enabled intr since hw reset */
1415         igb_intr_enable(dev);
1416
1417         PMD_INIT_LOG(DEBUG, "<<");
1418
1419         return 0;
1420
1421 error_invalid_config:
1422         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1423                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1424         igb_dev_clear_queues(dev);
1425         return -EINVAL;
1426 }
1427
1428 /*********************************************************************
1429  *
1430  *  This routine disables all traffic on the adapter by issuing a
1431  *  global reset on the MAC.
1432  *
1433  **********************************************************************/
1434 static void
1435 eth_igb_stop(struct rte_eth_dev *dev)
1436 {
1437         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438         struct e1000_filter_info *filter_info =
1439                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1440         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1441         struct rte_eth_link link;
1442         struct e1000_flex_filter *p_flex;
1443         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1444         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1445         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1446
1447         igb_intr_disable(hw);
1448
1449         /* disable intr eventfd mapping */
1450         rte_intr_disable(intr_handle);
1451
1452         igb_pf_reset_hw(hw);
1453         E1000_WRITE_REG(hw, E1000_WUC, 0);
1454
1455         /* Set bit for Go Link disconnect */
1456         if (hw->mac.type >= e1000_82580) {
1457                 uint32_t phpm_reg;
1458
1459                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1460                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1461                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1462         }
1463
1464         /* Power down the phy. Needed to make the link go Down */
1465         eth_igb_dev_set_link_down(dev);
1466
1467         igb_dev_clear_queues(dev);
1468
1469         /* clear the recorded link status */
1470         memset(&link, 0, sizeof(link));
1471         rte_igb_dev_atomic_write_link_status(dev, &link);
1472
1473         /* Remove all flex filters of the device */
1474         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1475                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1476                 rte_free(p_flex);
1477         }
1478         filter_info->flex_mask = 0;
1479
1480         /* Remove all ntuple filters of the device */
1481         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1482              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1483                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1484                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1485                              p_5tuple, entries);
1486                 rte_free(p_5tuple);
1487         }
1488         filter_info->fivetuple_mask = 0;
1489         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1490              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1491                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1492                 TAILQ_REMOVE(&filter_info->twotuple_list,
1493                              p_2tuple, entries);
1494                 rte_free(p_2tuple);
1495         }
1496         filter_info->twotuple_mask = 0;
1497
1498         if (!rte_intr_allow_others(intr_handle))
1499                 /* resume to the default handler */
1500                 rte_intr_callback_register(intr_handle,
1501                                            eth_igb_interrupt_handler,
1502                                            (void *)dev);
1503
1504         /* Clean datapath event and queue/vec mapping */
1505         rte_intr_efd_disable(intr_handle);
1506         if (intr_handle->intr_vec != NULL) {
1507                 rte_free(intr_handle->intr_vec);
1508                 intr_handle->intr_vec = NULL;
1509         }
1510 }
1511
1512 static int
1513 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1514 {
1515         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1516
1517         if (hw->phy.media_type == e1000_media_type_copper)
1518                 e1000_power_up_phy(hw);
1519         else
1520                 e1000_power_up_fiber_serdes_link(hw);
1521
1522         return 0;
1523 }
1524
1525 static int
1526 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1527 {
1528         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529
1530         if (hw->phy.media_type == e1000_media_type_copper)
1531                 e1000_power_down_phy(hw);
1532         else
1533                 e1000_shutdown_fiber_serdes_link(hw);
1534
1535         return 0;
1536 }
1537
1538 static void
1539 eth_igb_close(struct rte_eth_dev *dev)
1540 {
1541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542         struct e1000_adapter *adapter =
1543                 E1000_DEV_PRIVATE(dev->data->dev_private);
1544         struct rte_eth_link link;
1545         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
1546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547
1548         eth_igb_stop(dev);
1549         adapter->stopped = 1;
1550
1551         e1000_phy_hw_reset(hw);
1552         igb_release_manageability(hw);
1553         igb_hw_control_release(hw);
1554
1555         /* Clear bit for Go Link disconnect */
1556         if (hw->mac.type >= e1000_82580) {
1557                 uint32_t phpm_reg;
1558
1559                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1560                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1561                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1562         }
1563
1564         igb_dev_free_queues(dev);
1565
1566         if (intr_handle->intr_vec) {
1567                 rte_free(intr_handle->intr_vec);
1568                 intr_handle->intr_vec = NULL;
1569         }
1570
1571         memset(&link, 0, sizeof(link));
1572         rte_igb_dev_atomic_write_link_status(dev, &link);
1573 }
1574
1575 static int
1576 igb_get_rx_buffer_size(struct e1000_hw *hw)
1577 {
1578         uint32_t rx_buf_size;
1579         if (hw->mac.type == e1000_82576) {
1580                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1581         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1582                 /* PBS needs to be translated according to a lookup table */
1583                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1584                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1585                 rx_buf_size = (rx_buf_size << 10);
1586         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1587                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1588         } else {
1589                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1590         }
1591
1592         return rx_buf_size;
1593 }
1594
1595 /*********************************************************************
1596  *
1597  *  Initialize the hardware
1598  *
1599  **********************************************************************/
1600 static int
1601 igb_hardware_init(struct e1000_hw *hw)
1602 {
1603         uint32_t rx_buf_size;
1604         int diag;
1605
1606         /* Let the firmware know the OS is in control */
1607         igb_hw_control_acquire(hw);
1608
1609         /*
1610          * These parameters control the automatic generation (Tx) and
1611          * response (Rx) to Ethernet PAUSE frames.
1612          * - High water mark should allow for at least two standard size (1518)
1613          *   frames to be received after sending an XOFF.
1614          * - Low water mark works best when it is very near the high water mark.
1615          *   This allows the receiver to restart by sending XON when it has
1616          *   drained a bit. Here we use an arbitrary value of 1500 which will
1617          *   restart after one full frame is pulled from the buffer. There
1618          *   could be several smaller frames in the buffer and if so they will
1619          *   not trigger the XON until their total number reduces the buffer
1620          *   by 1500.
1621          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1622          */
1623         rx_buf_size = igb_get_rx_buffer_size(hw);
1624
1625         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1626         hw->fc.low_water = hw->fc.high_water - 1500;
1627         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1628         hw->fc.send_xon = 1;
1629
1630         /* Set Flow control, use the tunable location if sane */
1631         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1632                 hw->fc.requested_mode = igb_fc_setting;
1633         else
1634                 hw->fc.requested_mode = e1000_fc_none;
1635
1636         /* Issue a global reset */
1637         igb_pf_reset_hw(hw);
1638         E1000_WRITE_REG(hw, E1000_WUC, 0);
1639
1640         diag = e1000_init_hw(hw);
1641         if (diag < 0)
1642                 return diag;
1643
1644         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1645         e1000_get_phy_info(hw);
1646         e1000_check_for_link(hw);
1647
1648         return 0;
1649 }
1650
1651 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1652 static void
1653 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1654 {
1655         int pause_frames;
1656
1657         uint64_t old_gprc  = stats->gprc;
1658         uint64_t old_gptc  = stats->gptc;
1659         uint64_t old_tpr   = stats->tpr;
1660         uint64_t old_tpt   = stats->tpt;
1661         uint64_t old_rpthc = stats->rpthc;
1662         uint64_t old_hgptc = stats->hgptc;
1663
1664         if(hw->phy.media_type == e1000_media_type_copper ||
1665             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1666                 stats->symerrs +=
1667                     E1000_READ_REG(hw,E1000_SYMERRS);
1668                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1669         }
1670
1671         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1672         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1673         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1674         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1675
1676         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1677         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1678         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1679         stats->dc += E1000_READ_REG(hw, E1000_DC);
1680         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1681         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1682         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1683         /*
1684         ** For watchdog management we need to know if we have been
1685         ** paused during the last interval, so capture that here.
1686         */
1687         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1688         stats->xoffrxc += pause_frames;
1689         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1690         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1691         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1692         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1693         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1694         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1695         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1696         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1697         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1698         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1699         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1700         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1701
1702         /* For the 64-bit byte counters the low dword must be read first. */
1703         /* Both registers clear on the read of the high dword */
1704
1705         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1706         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1707         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1708         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1709         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1710         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1711         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1712
1713         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1714         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1715         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1716         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1717         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1718
1719         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1720         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1721
1722         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1723         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1724         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1725         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1726         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1727         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1728
1729         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1730         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1731         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1732         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1733         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1734         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1735         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1736         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1737
1738         /* Interrupt Counts */
1739
1740         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1741         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1742         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1743         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1744         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1745         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1746         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1747         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1748         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1749
1750         /* Host to Card Statistics */
1751
1752         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1753         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1754         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1755         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1756         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1757         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1758         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1759         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1760         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1761         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1762         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1763         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1764         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1765         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1766         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1767         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1768
1769         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1770         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1771         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1772         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1773         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1774         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1775 }
1776
1777 static void
1778 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1779 {
1780         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781         struct e1000_hw_stats *stats =
1782                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1783
1784         igb_read_stats_registers(hw, stats);
1785
1786         if (rte_stats == NULL)
1787                 return;
1788
1789         /* Rx Errors */
1790         rte_stats->imissed = stats->mpc;
1791         rte_stats->ierrors = stats->crcerrs +
1792                              stats->rlec + stats->ruc + stats->roc +
1793                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1794
1795         /* Tx Errors */
1796         rte_stats->oerrors = stats->ecol + stats->latecol;
1797
1798         rte_stats->ipackets = stats->gprc;
1799         rte_stats->opackets = stats->gptc;
1800         rte_stats->ibytes   = stats->gorc;
1801         rte_stats->obytes   = stats->gotc;
1802 }
1803
1804 static void
1805 eth_igb_stats_reset(struct rte_eth_dev *dev)
1806 {
1807         struct e1000_hw_stats *hw_stats =
1808                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1809
1810         /* HW registers are cleared on read */
1811         eth_igb_stats_get(dev, NULL);
1812
1813         /* Reset software totals */
1814         memset(hw_stats, 0, sizeof(*hw_stats));
1815 }
1816
1817 static void
1818 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1819 {
1820         struct e1000_hw_stats *stats =
1821                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1822
1823         /* HW registers are cleared on read */
1824         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1825
1826         /* Reset software totals */
1827         memset(stats, 0, sizeof(*stats));
1828 }
1829
1830 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1831         struct rte_eth_xstat_name *xstats_names,
1832         __rte_unused unsigned limit)
1833 {
1834         unsigned i;
1835
1836         if (xstats_names == NULL)
1837                 return IGB_NB_XSTATS;
1838
1839         /* Note: limit checked in rte_eth_xstats_names() */
1840
1841         for (i = 0; i < IGB_NB_XSTATS; i++) {
1842                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1843                          "%s", rte_igb_stats_strings[i].name);
1844         }
1845
1846         return IGB_NB_XSTATS;
1847 }
1848
1849 static int
1850 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1851                    unsigned n)
1852 {
1853         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1854         struct e1000_hw_stats *hw_stats =
1855                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1856         unsigned i;
1857
1858         if (n < IGB_NB_XSTATS)
1859                 return IGB_NB_XSTATS;
1860
1861         igb_read_stats_registers(hw, hw_stats);
1862
1863         /* If this is a reset xstats is NULL, and we have cleared the
1864          * registers by reading them.
1865          */
1866         if (!xstats)
1867                 return 0;
1868
1869         /* Extended stats */
1870         for (i = 0; i < IGB_NB_XSTATS; i++) {
1871                 xstats[i].id = i;
1872                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1873                         rte_igb_stats_strings[i].offset);
1874         }
1875
1876         return IGB_NB_XSTATS;
1877 }
1878
1879 static void
1880 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1881 {
1882         /* Good Rx packets, include VF loopback */
1883         UPDATE_VF_STAT(E1000_VFGPRC,
1884             hw_stats->last_gprc, hw_stats->gprc);
1885
1886         /* Good Rx octets, include VF loopback */
1887         UPDATE_VF_STAT(E1000_VFGORC,
1888             hw_stats->last_gorc, hw_stats->gorc);
1889
1890         /* Good Tx packets, include VF loopback */
1891         UPDATE_VF_STAT(E1000_VFGPTC,
1892             hw_stats->last_gptc, hw_stats->gptc);
1893
1894         /* Good Tx octets, include VF loopback */
1895         UPDATE_VF_STAT(E1000_VFGOTC,
1896             hw_stats->last_gotc, hw_stats->gotc);
1897
1898         /* Rx Multicst packets */
1899         UPDATE_VF_STAT(E1000_VFMPRC,
1900             hw_stats->last_mprc, hw_stats->mprc);
1901
1902         /* Good Rx loopback packets */
1903         UPDATE_VF_STAT(E1000_VFGPRLBC,
1904             hw_stats->last_gprlbc, hw_stats->gprlbc);
1905
1906         /* Good Rx loopback octets */
1907         UPDATE_VF_STAT(E1000_VFGORLBC,
1908             hw_stats->last_gorlbc, hw_stats->gorlbc);
1909
1910         /* Good Tx loopback packets */
1911         UPDATE_VF_STAT(E1000_VFGPTLBC,
1912             hw_stats->last_gptlbc, hw_stats->gptlbc);
1913
1914         /* Good Tx loopback octets */
1915         UPDATE_VF_STAT(E1000_VFGOTLBC,
1916             hw_stats->last_gotlbc, hw_stats->gotlbc);
1917 }
1918
1919 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1920                                      struct rte_eth_xstat_name *xstats_names,
1921                                      __rte_unused unsigned limit)
1922 {
1923         unsigned i;
1924
1925         if (xstats_names != NULL)
1926                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1927                         snprintf(xstats_names[i].name,
1928                                 sizeof(xstats_names[i].name), "%s",
1929                                 rte_igbvf_stats_strings[i].name);
1930                 }
1931         return IGBVF_NB_XSTATS;
1932 }
1933
1934 static int
1935 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1936                      unsigned n)
1937 {
1938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1940                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1941         unsigned i;
1942
1943         if (n < IGBVF_NB_XSTATS)
1944                 return IGBVF_NB_XSTATS;
1945
1946         igbvf_read_stats_registers(hw, hw_stats);
1947
1948         if (!xstats)
1949                 return 0;
1950
1951         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1952                 xstats[i].id = i;
1953                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1954                         rte_igbvf_stats_strings[i].offset);
1955         }
1956
1957         return IGBVF_NB_XSTATS;
1958 }
1959
1960 static void
1961 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1962 {
1963         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1965                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1966
1967         igbvf_read_stats_registers(hw, hw_stats);
1968
1969         if (rte_stats == NULL)
1970                 return;
1971
1972         rte_stats->ipackets = hw_stats->gprc;
1973         rte_stats->ibytes = hw_stats->gorc;
1974         rte_stats->opackets = hw_stats->gptc;
1975         rte_stats->obytes = hw_stats->gotc;
1976 }
1977
1978 static void
1979 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1980 {
1981         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1982                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1983
1984         /* Sync HW register to the last stats */
1985         eth_igbvf_stats_get(dev, NULL);
1986
1987         /* reset HW current stats*/
1988         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1989                offsetof(struct e1000_vf_stats, gprc));
1990 }
1991
1992 static int
1993 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1994                        size_t fw_size)
1995 {
1996         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997         struct e1000_fw_version fw;
1998         int ret;
1999
2000         e1000_get_fw_version(hw, &fw);
2001
2002         switch (hw->mac.type) {
2003         case e1000_i210:
2004         case e1000_i211:
2005                 if (!(e1000_get_flash_presence_i210(hw))) {
2006                         ret = snprintf(fw_version, fw_size,
2007                                  "%2d.%2d-%d",
2008                                  fw.invm_major, fw.invm_minor,
2009                                  fw.invm_img_type);
2010                         break;
2011                 }
2012                 /* fall through */
2013         default:
2014                 /* if option rom is valid, display its version too */
2015                 if (fw.or_valid) {
2016                         ret = snprintf(fw_version, fw_size,
2017                                  "%d.%d, 0x%08x, %d.%d.%d",
2018                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2019                                  fw.or_major, fw.or_build, fw.or_patch);
2020                 /* no option rom */
2021                 } else {
2022                         if (fw.etrack_id != 0X0000) {
2023                                 ret = snprintf(fw_version, fw_size,
2024                                          "%d.%d, 0x%08x",
2025                                          fw.eep_major, fw.eep_minor,
2026                                          fw.etrack_id);
2027                         } else {
2028                                 ret = snprintf(fw_version, fw_size,
2029                                          "%d.%d.%d",
2030                                          fw.eep_major, fw.eep_minor,
2031                                          fw.eep_build);
2032                         }
2033                 }
2034                 break;
2035         }
2036
2037         ret += 1; /* add the size of '\0' */
2038         if (fw_size < (u32)ret)
2039                 return ret;
2040         else
2041                 return 0;
2042 }
2043
2044 static void
2045 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2046 {
2047         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048
2049         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2050         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2051         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2052         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2053         dev_info->rx_offload_capa =
2054                 DEV_RX_OFFLOAD_VLAN_STRIP |
2055                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2056                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2057                 DEV_RX_OFFLOAD_TCP_CKSUM;
2058         dev_info->tx_offload_capa =
2059                 DEV_TX_OFFLOAD_VLAN_INSERT |
2060                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2061                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2062                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2063                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2064                 DEV_TX_OFFLOAD_TCP_TSO;
2065
2066         switch (hw->mac.type) {
2067         case e1000_82575:
2068                 dev_info->max_rx_queues = 4;
2069                 dev_info->max_tx_queues = 4;
2070                 dev_info->max_vmdq_pools = 0;
2071                 break;
2072
2073         case e1000_82576:
2074                 dev_info->max_rx_queues = 16;
2075                 dev_info->max_tx_queues = 16;
2076                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2077                 dev_info->vmdq_queue_num = 16;
2078                 break;
2079
2080         case e1000_82580:
2081                 dev_info->max_rx_queues = 8;
2082                 dev_info->max_tx_queues = 8;
2083                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2084                 dev_info->vmdq_queue_num = 8;
2085                 break;
2086
2087         case e1000_i350:
2088                 dev_info->max_rx_queues = 8;
2089                 dev_info->max_tx_queues = 8;
2090                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2091                 dev_info->vmdq_queue_num = 8;
2092                 break;
2093
2094         case e1000_i354:
2095                 dev_info->max_rx_queues = 8;
2096                 dev_info->max_tx_queues = 8;
2097                 break;
2098
2099         case e1000_i210:
2100                 dev_info->max_rx_queues = 4;
2101                 dev_info->max_tx_queues = 4;
2102                 dev_info->max_vmdq_pools = 0;
2103                 break;
2104
2105         case e1000_i211:
2106                 dev_info->max_rx_queues = 2;
2107                 dev_info->max_tx_queues = 2;
2108                 dev_info->max_vmdq_pools = 0;
2109                 break;
2110
2111         default:
2112                 /* Should not happen */
2113                 break;
2114         }
2115         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2116         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2117         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2118
2119         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2120                 .rx_thresh = {
2121                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2122                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2123                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2124                 },
2125                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2126                 .rx_drop_en = 0,
2127         };
2128
2129         dev_info->default_txconf = (struct rte_eth_txconf) {
2130                 .tx_thresh = {
2131                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2132                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2133                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2134                 },
2135                 .txq_flags = 0,
2136         };
2137
2138         dev_info->rx_desc_lim = rx_desc_lim;
2139         dev_info->tx_desc_lim = tx_desc_lim;
2140
2141         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2142                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2143                         ETH_LINK_SPEED_1G;
2144 }
2145
2146 static const uint32_t *
2147 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2148 {
2149         static const uint32_t ptypes[] = {
2150                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2151                 RTE_PTYPE_L2_ETHER,
2152                 RTE_PTYPE_L3_IPV4,
2153                 RTE_PTYPE_L3_IPV4_EXT,
2154                 RTE_PTYPE_L3_IPV6,
2155                 RTE_PTYPE_L3_IPV6_EXT,
2156                 RTE_PTYPE_L4_TCP,
2157                 RTE_PTYPE_L4_UDP,
2158                 RTE_PTYPE_L4_SCTP,
2159                 RTE_PTYPE_TUNNEL_IP,
2160                 RTE_PTYPE_INNER_L3_IPV6,
2161                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2162                 RTE_PTYPE_INNER_L4_TCP,
2163                 RTE_PTYPE_INNER_L4_UDP,
2164                 RTE_PTYPE_UNKNOWN
2165         };
2166
2167         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2168             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2169                 return ptypes;
2170         return NULL;
2171 }
2172
2173 static void
2174 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2175 {
2176         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177
2178         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2179         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2180         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2181         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2182         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2183                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2184                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2185                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2186         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2187                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2188                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2189                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2190                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2191                                 DEV_TX_OFFLOAD_TCP_TSO;
2192         switch (hw->mac.type) {
2193         case e1000_vfadapt:
2194                 dev_info->max_rx_queues = 2;
2195                 dev_info->max_tx_queues = 2;
2196                 break;
2197         case e1000_vfadapt_i350:
2198                 dev_info->max_rx_queues = 1;
2199                 dev_info->max_tx_queues = 1;
2200                 break;
2201         default:
2202                 /* Should not happen */
2203                 break;
2204         }
2205
2206         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2207                 .rx_thresh = {
2208                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2209                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2210                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2211                 },
2212                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2213                 .rx_drop_en = 0,
2214         };
2215
2216         dev_info->default_txconf = (struct rte_eth_txconf) {
2217                 .tx_thresh = {
2218                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2219                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2220                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2221                 },
2222                 .txq_flags = 0,
2223         };
2224
2225         dev_info->rx_desc_lim = rx_desc_lim;
2226         dev_info->tx_desc_lim = tx_desc_lim;
2227 }
2228
2229 /* return 0 means link status changed, -1 means not changed */
2230 static int
2231 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2232 {
2233         struct e1000_hw *hw =
2234                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         struct rte_eth_link link, old;
2236         int link_check, count;
2237
2238         link_check = 0;
2239         hw->mac.get_link_status = 1;
2240
2241         /* possible wait-to-complete in up to 9 seconds */
2242         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2243                 /* Read the real link status */
2244                 switch (hw->phy.media_type) {
2245                 case e1000_media_type_copper:
2246                         /* Do the work to read phy */
2247                         e1000_check_for_link(hw);
2248                         link_check = !hw->mac.get_link_status;
2249                         break;
2250
2251                 case e1000_media_type_fiber:
2252                         e1000_check_for_link(hw);
2253                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2254                                       E1000_STATUS_LU);
2255                         break;
2256
2257                 case e1000_media_type_internal_serdes:
2258                         e1000_check_for_link(hw);
2259                         link_check = hw->mac.serdes_has_link;
2260                         break;
2261
2262                 /* VF device is type_unknown */
2263                 case e1000_media_type_unknown:
2264                         eth_igbvf_link_update(hw);
2265                         link_check = !hw->mac.get_link_status;
2266                         break;
2267
2268                 default:
2269                         break;
2270                 }
2271                 if (link_check || wait_to_complete == 0)
2272                         break;
2273                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2274         }
2275         memset(&link, 0, sizeof(link));
2276         rte_igb_dev_atomic_read_link_status(dev, &link);
2277         old = link;
2278
2279         /* Now we check if a transition has happened */
2280         if (link_check) {
2281                 uint16_t duplex, speed;
2282                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2283                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2284                                 ETH_LINK_FULL_DUPLEX :
2285                                 ETH_LINK_HALF_DUPLEX;
2286                 link.link_speed = speed;
2287                 link.link_status = ETH_LINK_UP;
2288                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2289                                 ETH_LINK_SPEED_FIXED);
2290         } else if (!link_check) {
2291                 link.link_speed = 0;
2292                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2293                 link.link_status = ETH_LINK_DOWN;
2294                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2295         }
2296         rte_igb_dev_atomic_write_link_status(dev, &link);
2297
2298         /* not changed */
2299         if (old.link_status == link.link_status)
2300                 return -1;
2301
2302         /* changed */
2303         return 0;
2304 }
2305
2306 /*
2307  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2308  * For ASF and Pass Through versions of f/w this means
2309  * that the driver is loaded.
2310  */
2311 static void
2312 igb_hw_control_acquire(struct e1000_hw *hw)
2313 {
2314         uint32_t ctrl_ext;
2315
2316         /* Let firmware know the driver has taken over */
2317         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2318         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2319 }
2320
2321 /*
2322  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2323  * For ASF and Pass Through versions of f/w this means that the
2324  * driver is no longer loaded.
2325  */
2326 static void
2327 igb_hw_control_release(struct e1000_hw *hw)
2328 {
2329         uint32_t ctrl_ext;
2330
2331         /* Let firmware taken over control of h/w */
2332         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2333         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2334                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2335 }
2336
2337 /*
2338  * Bit of a misnomer, what this really means is
2339  * to enable OS management of the system... aka
2340  * to disable special hardware management features.
2341  */
2342 static void
2343 igb_init_manageability(struct e1000_hw *hw)
2344 {
2345         if (e1000_enable_mng_pass_thru(hw)) {
2346                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2347                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2348
2349                 /* disable hardware interception of ARP */
2350                 manc &= ~(E1000_MANC_ARP_EN);
2351
2352                 /* enable receiving management packets to the host */
2353                 manc |= E1000_MANC_EN_MNG2HOST;
2354                 manc2h |= 1 << 5;  /* Mng Port 623 */
2355                 manc2h |= 1 << 6;  /* Mng Port 664 */
2356                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2357                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2358         }
2359 }
2360
2361 static void
2362 igb_release_manageability(struct e1000_hw *hw)
2363 {
2364         if (e1000_enable_mng_pass_thru(hw)) {
2365                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2366
2367                 manc |= E1000_MANC_ARP_EN;
2368                 manc &= ~E1000_MANC_EN_MNG2HOST;
2369
2370                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2371         }
2372 }
2373
2374 static void
2375 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2376 {
2377         struct e1000_hw *hw =
2378                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2379         uint32_t rctl;
2380
2381         rctl = E1000_READ_REG(hw, E1000_RCTL);
2382         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2383         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2384 }
2385
2386 static void
2387 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2388 {
2389         struct e1000_hw *hw =
2390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         uint32_t rctl;
2392
2393         rctl = E1000_READ_REG(hw, E1000_RCTL);
2394         rctl &= (~E1000_RCTL_UPE);
2395         if (dev->data->all_multicast == 1)
2396                 rctl |= E1000_RCTL_MPE;
2397         else
2398                 rctl &= (~E1000_RCTL_MPE);
2399         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2400 }
2401
2402 static void
2403 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2404 {
2405         struct e1000_hw *hw =
2406                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         uint32_t rctl;
2408
2409         rctl = E1000_READ_REG(hw, E1000_RCTL);
2410         rctl |= E1000_RCTL_MPE;
2411         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2412 }
2413
2414 static void
2415 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2416 {
2417         struct e1000_hw *hw =
2418                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419         uint32_t rctl;
2420
2421         if (dev->data->promiscuous == 1)
2422                 return; /* must remain in all_multicast mode */
2423         rctl = E1000_READ_REG(hw, E1000_RCTL);
2424         rctl &= (~E1000_RCTL_MPE);
2425         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2426 }
2427
2428 static int
2429 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2430 {
2431         struct e1000_hw *hw =
2432                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433         struct e1000_vfta * shadow_vfta =
2434                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2435         uint32_t vfta;
2436         uint32_t vid_idx;
2437         uint32_t vid_bit;
2438
2439         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2440                               E1000_VFTA_ENTRY_MASK);
2441         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2442         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2443         if (on)
2444                 vfta |= vid_bit;
2445         else
2446                 vfta &= ~vid_bit;
2447         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2448
2449         /* update local VFTA copy */
2450         shadow_vfta->vfta[vid_idx] = vfta;
2451
2452         return 0;
2453 }
2454
2455 static int
2456 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2457                       enum rte_vlan_type vlan_type,
2458                       uint16_t tpid)
2459 {
2460         struct e1000_hw *hw =
2461                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         uint32_t reg, qinq;
2463
2464         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2465         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2466
2467         /* only outer TPID of double VLAN can be configured*/
2468         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2469                 reg = E1000_READ_REG(hw, E1000_VET);
2470                 reg = (reg & (~E1000_VET_VET_EXT)) |
2471                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2472                 E1000_WRITE_REG(hw, E1000_VET, reg);
2473
2474                 return 0;
2475         }
2476
2477         /* all other TPID values are read-only*/
2478         PMD_DRV_LOG(ERR, "Not supported");
2479
2480         return -ENOTSUP;
2481 }
2482
2483 static void
2484 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2485 {
2486         struct e1000_hw *hw =
2487                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488         uint32_t reg;
2489
2490         /* Filter Table Disable */
2491         reg = E1000_READ_REG(hw, E1000_RCTL);
2492         reg &= ~E1000_RCTL_CFIEN;
2493         reg &= ~E1000_RCTL_VFE;
2494         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2495 }
2496
2497 static void
2498 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2499 {
2500         struct e1000_hw *hw =
2501                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502         struct e1000_vfta * shadow_vfta =
2503                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2504         uint32_t reg;
2505         int i;
2506
2507         /* Filter Table Enable, CFI not used for packet acceptance */
2508         reg = E1000_READ_REG(hw, E1000_RCTL);
2509         reg &= ~E1000_RCTL_CFIEN;
2510         reg |= E1000_RCTL_VFE;
2511         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2512
2513         /* restore VFTA table */
2514         for (i = 0; i < IGB_VFTA_SIZE; i++)
2515                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2516 }
2517
2518 static void
2519 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2520 {
2521         struct e1000_hw *hw =
2522                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         uint32_t reg;
2524
2525         /* VLAN Mode Disable */
2526         reg = E1000_READ_REG(hw, E1000_CTRL);
2527         reg &= ~E1000_CTRL_VME;
2528         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2529 }
2530
2531 static void
2532 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2533 {
2534         struct e1000_hw *hw =
2535                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         uint32_t reg;
2537
2538         /* VLAN Mode Enable */
2539         reg = E1000_READ_REG(hw, E1000_CTRL);
2540         reg |= E1000_CTRL_VME;
2541         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2542 }
2543
2544 static void
2545 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2546 {
2547         struct e1000_hw *hw =
2548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549         uint32_t reg;
2550
2551         /* CTRL_EXT: Extended VLAN */
2552         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2553         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2554         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2555
2556         /* Update maximum packet length */
2557         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2558                 E1000_WRITE_REG(hw, E1000_RLPML,
2559                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2560                                                 VLAN_TAG_SIZE);
2561 }
2562
2563 static void
2564 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2565 {
2566         struct e1000_hw *hw =
2567                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         uint32_t reg;
2569
2570         /* CTRL_EXT: Extended VLAN */
2571         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2572         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2573         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2574
2575         /* Update maximum packet length */
2576         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2577                 E1000_WRITE_REG(hw, E1000_RLPML,
2578                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2579                                                 2 * VLAN_TAG_SIZE);
2580 }
2581
2582 static void
2583 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2584 {
2585         if(mask & ETH_VLAN_STRIP_MASK){
2586                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2587                         igb_vlan_hw_strip_enable(dev);
2588                 else
2589                         igb_vlan_hw_strip_disable(dev);
2590         }
2591
2592         if(mask & ETH_VLAN_FILTER_MASK){
2593                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2594                         igb_vlan_hw_filter_enable(dev);
2595                 else
2596                         igb_vlan_hw_filter_disable(dev);
2597         }
2598
2599         if(mask & ETH_VLAN_EXTEND_MASK){
2600                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2601                         igb_vlan_hw_extend_enable(dev);
2602                 else
2603                         igb_vlan_hw_extend_disable(dev);
2604         }
2605 }
2606
2607
2608 /**
2609  * It enables the interrupt mask and then enable the interrupt.
2610  *
2611  * @param dev
2612  *  Pointer to struct rte_eth_dev.
2613  *
2614  * @return
2615  *  - On success, zero.
2616  *  - On failure, a negative value.
2617  */
2618 static int
2619 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2620 {
2621         struct e1000_interrupt *intr =
2622                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2623
2624         intr->mask |= E1000_ICR_LSC;
2625
2626         return 0;
2627 }
2628
2629 /* It clears the interrupt causes and enables the interrupt.
2630  * It will be called once only during nic initialized.
2631  *
2632  * @param dev
2633  *  Pointer to struct rte_eth_dev.
2634  *
2635  * @return
2636  *  - On success, zero.
2637  *  - On failure, a negative value.
2638  */
2639 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2640 {
2641         uint32_t mask, regval;
2642         struct e1000_hw *hw =
2643                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644         struct rte_eth_dev_info dev_info;
2645
2646         memset(&dev_info, 0, sizeof(dev_info));
2647         eth_igb_infos_get(dev, &dev_info);
2648
2649         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2650         regval = E1000_READ_REG(hw, E1000_EIMS);
2651         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2652
2653         return 0;
2654 }
2655
2656 /*
2657  * It reads ICR and gets interrupt causes, check it and set a bit flag
2658  * to update link status.
2659  *
2660  * @param dev
2661  *  Pointer to struct rte_eth_dev.
2662  *
2663  * @return
2664  *  - On success, zero.
2665  *  - On failure, a negative value.
2666  */
2667 static int
2668 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2669 {
2670         uint32_t icr;
2671         struct e1000_hw *hw =
2672                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2673         struct e1000_interrupt *intr =
2674                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2675
2676         igb_intr_disable(hw);
2677
2678         /* read-on-clear nic registers here */
2679         icr = E1000_READ_REG(hw, E1000_ICR);
2680
2681         intr->flags = 0;
2682         if (icr & E1000_ICR_LSC) {
2683                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2684         }
2685
2686         if (icr & E1000_ICR_VMMB)
2687                 intr->flags |= E1000_FLAG_MAILBOX;
2688
2689         return 0;
2690 }
2691
2692 /*
2693  * It executes link_update after knowing an interrupt is prsent.
2694  *
2695  * @param dev
2696  *  Pointer to struct rte_eth_dev.
2697  *
2698  * @return
2699  *  - On success, zero.
2700  *  - On failure, a negative value.
2701  */
2702 static int
2703 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2704                          struct rte_intr_handle *intr_handle)
2705 {
2706         struct e1000_hw *hw =
2707                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2708         struct e1000_interrupt *intr =
2709                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2710         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
2711         uint32_t tctl, rctl;
2712         struct rte_eth_link link;
2713         int ret;
2714
2715         if (intr->flags & E1000_FLAG_MAILBOX) {
2716                 igb_pf_mbx_process(dev);
2717                 intr->flags &= ~E1000_FLAG_MAILBOX;
2718         }
2719
2720         igb_intr_enable(dev);
2721         rte_intr_enable(intr_handle);
2722
2723         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2724                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2725
2726                 /* set get_link_status to check register later */
2727                 hw->mac.get_link_status = 1;
2728                 ret = eth_igb_link_update(dev, 0);
2729
2730                 /* check if link has changed */
2731                 if (ret < 0)
2732                         return 0;
2733
2734                 memset(&link, 0, sizeof(link));
2735                 rte_igb_dev_atomic_read_link_status(dev, &link);
2736                 if (link.link_status) {
2737                         PMD_INIT_LOG(INFO,
2738                                      " Port %d: Link Up - speed %u Mbps - %s",
2739                                      dev->data->port_id,
2740                                      (unsigned)link.link_speed,
2741                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2742                                      "full-duplex" : "half-duplex");
2743                 } else {
2744                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2745                                      dev->data->port_id);
2746                 }
2747
2748                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2749                              pci_dev->addr.domain,
2750                              pci_dev->addr.bus,
2751                              pci_dev->addr.devid,
2752                              pci_dev->addr.function);
2753                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2754                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2755                 if (link.link_status) {
2756                         /* enable Tx/Rx */
2757                         tctl |= E1000_TCTL_EN;
2758                         rctl |= E1000_RCTL_EN;
2759                 } else {
2760                         /* disable Tx/Rx */
2761                         tctl &= ~E1000_TCTL_EN;
2762                         rctl &= ~E1000_RCTL_EN;
2763                 }
2764                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2765                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2766                 E1000_WRITE_FLUSH(hw);
2767                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2768         }
2769
2770         return 0;
2771 }
2772
2773 /**
2774  * Interrupt handler which shall be registered at first.
2775  *
2776  * @param handle
2777  *  Pointer to interrupt handle.
2778  * @param param
2779  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2780  *
2781  * @return
2782  *  void
2783  */
2784 static void
2785 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
2786 {
2787         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2788
2789         eth_igb_interrupt_get_status(dev);
2790         eth_igb_interrupt_action(dev, handle);
2791 }
2792
2793 static int
2794 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2795 {
2796         uint32_t eicr;
2797         struct e1000_hw *hw =
2798                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         struct e1000_interrupt *intr =
2800                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2801
2802         igbvf_intr_disable(hw);
2803
2804         /* read-on-clear nic registers here */
2805         eicr = E1000_READ_REG(hw, E1000_EICR);
2806         intr->flags = 0;
2807
2808         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2809                 intr->flags |= E1000_FLAG_MAILBOX;
2810
2811         return 0;
2812 }
2813
2814 void igbvf_mbx_process(struct rte_eth_dev *dev)
2815 {
2816         struct e1000_hw *hw =
2817                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         struct e1000_mbx_info *mbx = &hw->mbx;
2819         u32 in_msg = 0;
2820
2821         if (mbx->ops.read(hw, &in_msg, 1, 0))
2822                 return;
2823
2824         /* PF reset VF event */
2825         if (in_msg == E1000_PF_CONTROL_MSG)
2826                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2827 }
2828
2829 static int
2830 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2831 {
2832         struct e1000_interrupt *intr =
2833                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2834
2835         if (intr->flags & E1000_FLAG_MAILBOX) {
2836                 igbvf_mbx_process(dev);
2837                 intr->flags &= ~E1000_FLAG_MAILBOX;
2838         }
2839
2840         igbvf_intr_enable(dev);
2841         rte_intr_enable(intr_handle);
2842
2843         return 0;
2844 }
2845
2846 static void
2847 eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
2848                             void *param)
2849 {
2850         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2851
2852         eth_igbvf_interrupt_get_status(dev);
2853         eth_igbvf_interrupt_action(dev, handle);
2854 }
2855
2856 static int
2857 eth_igb_led_on(struct rte_eth_dev *dev)
2858 {
2859         struct e1000_hw *hw;
2860
2861         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2863 }
2864
2865 static int
2866 eth_igb_led_off(struct rte_eth_dev *dev)
2867 {
2868         struct e1000_hw *hw;
2869
2870         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2872 }
2873
2874 static int
2875 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2876 {
2877         struct e1000_hw *hw;
2878         uint32_t ctrl;
2879         int tx_pause;
2880         int rx_pause;
2881
2882         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883         fc_conf->pause_time = hw->fc.pause_time;
2884         fc_conf->high_water = hw->fc.high_water;
2885         fc_conf->low_water = hw->fc.low_water;
2886         fc_conf->send_xon = hw->fc.send_xon;
2887         fc_conf->autoneg = hw->mac.autoneg;
2888
2889         /*
2890          * Return rx_pause and tx_pause status according to actual setting of
2891          * the TFCE and RFCE bits in the CTRL register.
2892          */
2893         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2894         if (ctrl & E1000_CTRL_TFCE)
2895                 tx_pause = 1;
2896         else
2897                 tx_pause = 0;
2898
2899         if (ctrl & E1000_CTRL_RFCE)
2900                 rx_pause = 1;
2901         else
2902                 rx_pause = 0;
2903
2904         if (rx_pause && tx_pause)
2905                 fc_conf->mode = RTE_FC_FULL;
2906         else if (rx_pause)
2907                 fc_conf->mode = RTE_FC_RX_PAUSE;
2908         else if (tx_pause)
2909                 fc_conf->mode = RTE_FC_TX_PAUSE;
2910         else
2911                 fc_conf->mode = RTE_FC_NONE;
2912
2913         return 0;
2914 }
2915
2916 static int
2917 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2918 {
2919         struct e1000_hw *hw;
2920         int err;
2921         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2922                 e1000_fc_none,
2923                 e1000_fc_rx_pause,
2924                 e1000_fc_tx_pause,
2925                 e1000_fc_full
2926         };
2927         uint32_t rx_buf_size;
2928         uint32_t max_high_water;
2929         uint32_t rctl;
2930
2931         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932         if (fc_conf->autoneg != hw->mac.autoneg)
2933                 return -ENOTSUP;
2934         rx_buf_size = igb_get_rx_buffer_size(hw);
2935         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2936
2937         /* At least reserve one Ethernet frame for watermark */
2938         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2939         if ((fc_conf->high_water > max_high_water) ||
2940             (fc_conf->high_water < fc_conf->low_water)) {
2941                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2942                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2943                 return -EINVAL;
2944         }
2945
2946         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2947         hw->fc.pause_time     = fc_conf->pause_time;
2948         hw->fc.high_water     = fc_conf->high_water;
2949         hw->fc.low_water      = fc_conf->low_water;
2950         hw->fc.send_xon       = fc_conf->send_xon;
2951
2952         err = e1000_setup_link_generic(hw);
2953         if (err == E1000_SUCCESS) {
2954
2955                 /* check if we want to forward MAC frames - driver doesn't have native
2956                  * capability to do that, so we'll write the registers ourselves */
2957
2958                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2959
2960                 /* set or clear MFLCN.PMCF bit depending on configuration */
2961                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2962                         rctl |= E1000_RCTL_PMCF;
2963                 else
2964                         rctl &= ~E1000_RCTL_PMCF;
2965
2966                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2967                 E1000_WRITE_FLUSH(hw);
2968
2969                 return 0;
2970         }
2971
2972         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2973         return -EIO;
2974 }
2975
2976 #define E1000_RAH_POOLSEL_SHIFT      (18)
2977 static void
2978 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2979                 uint32_t index, __rte_unused uint32_t pool)
2980 {
2981         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982         uint32_t rah;
2983
2984         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2985         rah = E1000_READ_REG(hw, E1000_RAH(index));
2986         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2987         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2988 }
2989
2990 static void
2991 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2992 {
2993         uint8_t addr[ETHER_ADDR_LEN];
2994         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995
2996         memset(addr, 0, sizeof(addr));
2997
2998         e1000_rar_set(hw, addr, index);
2999 }
3000
3001 static void
3002 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3003                                 struct ether_addr *addr)
3004 {
3005         eth_igb_rar_clear(dev, 0);
3006
3007         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3008 }
3009 /*
3010  * Virtual Function operations
3011  */
3012 static void
3013 igbvf_intr_disable(struct e1000_hw *hw)
3014 {
3015         PMD_INIT_FUNC_TRACE();
3016
3017         /* Clear interrupt mask to stop from interrupts being generated */
3018         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3019
3020         E1000_WRITE_FLUSH(hw);
3021 }
3022
3023 static void
3024 igbvf_stop_adapter(struct rte_eth_dev *dev)
3025 {
3026         u32 reg_val;
3027         u16 i;
3028         struct rte_eth_dev_info dev_info;
3029         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030
3031         memset(&dev_info, 0, sizeof(dev_info));
3032         eth_igbvf_infos_get(dev, &dev_info);
3033
3034         /* Clear interrupt mask to stop from interrupts being generated */
3035         igbvf_intr_disable(hw);
3036
3037         /* Clear any pending interrupts, flush previous writes */
3038         E1000_READ_REG(hw, E1000_EICR);
3039
3040         /* Disable the transmit unit.  Each queue must be disabled. */
3041         for (i = 0; i < dev_info.max_tx_queues; i++)
3042                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3043
3044         /* Disable the receive unit by stopping each queue */
3045         for (i = 0; i < dev_info.max_rx_queues; i++) {
3046                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3047                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3048                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3049                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3050                         ;
3051         }
3052
3053         /* flush all queues disables */
3054         E1000_WRITE_FLUSH(hw);
3055         msec_delay(2);
3056 }
3057
3058 static int eth_igbvf_link_update(struct e1000_hw *hw)
3059 {
3060         struct e1000_mbx_info *mbx = &hw->mbx;
3061         struct e1000_mac_info *mac = &hw->mac;
3062         int ret_val = E1000_SUCCESS;
3063
3064         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3065
3066         /*
3067          * We only want to run this if there has been a rst asserted.
3068          * in this case that could mean a link change, device reset,
3069          * or a virtual function reset
3070          */
3071
3072         /* If we were hit with a reset or timeout drop the link */
3073         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3074                 mac->get_link_status = TRUE;
3075
3076         if (!mac->get_link_status)
3077                 goto out;
3078
3079         /* if link status is down no point in checking to see if pf is up */
3080         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3081                 goto out;
3082
3083         /* if we passed all the tests above then the link is up and we no
3084          * longer need to check for link */
3085         mac->get_link_status = FALSE;
3086
3087 out:
3088         return ret_val;
3089 }
3090
3091
3092 static int
3093 igbvf_dev_configure(struct rte_eth_dev *dev)
3094 {
3095         struct rte_eth_conf* conf = &dev->data->dev_conf;
3096
3097         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3098                      dev->data->port_id);
3099
3100         /*
3101          * VF has no ability to enable/disable HW CRC
3102          * Keep the persistent behavior the same as Host PF
3103          */
3104 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3105         if (!conf->rxmode.hw_strip_crc) {
3106                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3107                 conf->rxmode.hw_strip_crc = 1;
3108         }
3109 #else
3110         if (conf->rxmode.hw_strip_crc) {
3111                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3112                 conf->rxmode.hw_strip_crc = 0;
3113         }
3114 #endif
3115
3116         return 0;
3117 }
3118
3119 static int
3120 igbvf_dev_start(struct rte_eth_dev *dev)
3121 {
3122         struct e1000_hw *hw =
3123                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         struct e1000_adapter *adapter =
3125                 E1000_DEV_PRIVATE(dev->data->dev_private);
3126         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3128         int ret;
3129         uint32_t intr_vector = 0;
3130
3131         PMD_INIT_FUNC_TRACE();
3132
3133         hw->mac.ops.reset_hw(hw);
3134         adapter->stopped = 0;
3135
3136         /* Set all vfta */
3137         igbvf_set_vfta_all(dev,1);
3138
3139         eth_igbvf_tx_init(dev);
3140
3141         /* This can fail when allocating mbufs for descriptor rings */
3142         ret = eth_igbvf_rx_init(dev);
3143         if (ret) {
3144                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3145                 igb_dev_clear_queues(dev);
3146                 return ret;
3147         }
3148
3149         /* check and configure queue intr-vector mapping */
3150         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3151                 intr_vector = dev->data->nb_rx_queues;
3152                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3153                 if (ret)
3154                         return ret;
3155         }
3156
3157         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3158                 intr_handle->intr_vec =
3159                         rte_zmalloc("intr_vec",
3160                                     dev->data->nb_rx_queues * sizeof(int), 0);
3161                 if (!intr_handle->intr_vec) {
3162                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3163                                      " intr_vec", dev->data->nb_rx_queues);
3164                         return -ENOMEM;
3165                 }
3166         }
3167
3168         eth_igbvf_configure_msix_intr(dev);
3169
3170         /* enable uio/vfio intr/eventfd mapping */
3171         rte_intr_enable(intr_handle);
3172
3173         /* resume enabled intr since hw reset */
3174         igbvf_intr_enable(dev);
3175
3176         return 0;
3177 }
3178
3179 static void
3180 igbvf_dev_stop(struct rte_eth_dev *dev)
3181 {
3182         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
3183         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3184
3185         PMD_INIT_FUNC_TRACE();
3186
3187         igbvf_stop_adapter(dev);
3188
3189         /*
3190           * Clear what we set, but we still keep shadow_vfta to
3191           * restore after device starts
3192           */
3193         igbvf_set_vfta_all(dev,0);
3194
3195         igb_dev_clear_queues(dev);
3196
3197         /* disable intr eventfd mapping */
3198         rte_intr_disable(intr_handle);
3199
3200         /* Clean datapath event and queue/vec mapping */
3201         rte_intr_efd_disable(intr_handle);
3202         if (intr_handle->intr_vec) {
3203                 rte_free(intr_handle->intr_vec);
3204                 intr_handle->intr_vec = NULL;
3205         }
3206 }
3207
3208 static void
3209 igbvf_dev_close(struct rte_eth_dev *dev)
3210 {
3211         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct e1000_adapter *adapter =
3213                 E1000_DEV_PRIVATE(dev->data->dev_private);
3214         struct ether_addr addr;
3215
3216         PMD_INIT_FUNC_TRACE();
3217
3218         e1000_reset_hw(hw);
3219
3220         igbvf_dev_stop(dev);
3221         adapter->stopped = 1;
3222         igb_dev_free_queues(dev);
3223
3224         /**
3225          * reprogram the RAR with a zero mac address,
3226          * to ensure that the VF traffic goes to the PF
3227          * after stop, close and detach of the VF.
3228          **/
3229
3230         memset(&addr, 0, sizeof(addr));
3231         igbvf_default_mac_addr_set(dev, &addr);
3232 }
3233
3234 static void
3235 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3236 {
3237         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238
3239         /* Set both unicast and multicast promisc */
3240         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3241 }
3242
3243 static void
3244 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3245 {
3246         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247
3248         /* If in allmulticast mode leave multicast promisc */
3249         if (dev->data->all_multicast == 1)
3250                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3251         else
3252                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3253 }
3254
3255 static void
3256 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3257 {
3258         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259
3260         /* In promiscuous mode multicast promisc already set */
3261         if (dev->data->promiscuous == 0)
3262                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3263 }
3264
3265 static void
3266 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3267 {
3268         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269
3270         /* In promiscuous mode leave multicast promisc enabled */
3271         if (dev->data->promiscuous == 0)
3272                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3273 }
3274
3275 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3276 {
3277         struct e1000_mbx_info *mbx = &hw->mbx;
3278         uint32_t msgbuf[2];
3279         s32 err;
3280
3281         /* After set vlan, vlan strip will also be enabled in igb driver*/
3282         msgbuf[0] = E1000_VF_SET_VLAN;
3283         msgbuf[1] = vid;
3284         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3285         if (on)
3286                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3287
3288         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3289         if (err)
3290                 goto mbx_err;
3291
3292         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3293         if (err)
3294                 goto mbx_err;
3295
3296         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3297         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3298                 err = -EINVAL;
3299
3300 mbx_err:
3301         return err;
3302 }
3303
3304 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3305 {
3306         struct e1000_hw *hw =
3307                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         struct e1000_vfta * shadow_vfta =
3309                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3310         int i = 0, j = 0, vfta = 0, mask = 1;
3311
3312         for (i = 0; i < IGB_VFTA_SIZE; i++){
3313                 vfta = shadow_vfta->vfta[i];
3314                 if(vfta){
3315                         mask = 1;
3316                         for (j = 0; j < 32; j++){
3317                                 if(vfta & mask)
3318                                         igbvf_set_vfta(hw,
3319                                                 (uint16_t)((i<<5)+j), on);
3320                                 mask<<=1;
3321                         }
3322                 }
3323         }
3324
3325 }
3326
3327 static int
3328 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3329 {
3330         struct e1000_hw *hw =
3331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3332         struct e1000_vfta * shadow_vfta =
3333                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3334         uint32_t vid_idx = 0;
3335         uint32_t vid_bit = 0;
3336         int ret = 0;
3337
3338         PMD_INIT_FUNC_TRACE();
3339
3340         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3341         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3342         if(ret){
3343                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3344                 return ret;
3345         }
3346         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3347         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3348
3349         /*Save what we set and retore it after device reset*/
3350         if (on)
3351                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3352         else
3353                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3354
3355         return 0;
3356 }
3357
3358 static void
3359 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3360 {
3361         struct e1000_hw *hw =
3362                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363
3364         /* index is not used by rar_set() */
3365         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3366 }
3367
3368
3369 static int
3370 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3371                         struct rte_eth_rss_reta_entry64 *reta_conf,
3372                         uint16_t reta_size)
3373 {
3374         uint8_t i, j, mask;
3375         uint32_t reta, r;
3376         uint16_t idx, shift;
3377         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378
3379         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3380                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3381                         "(%d) doesn't match the number hardware can supported "
3382                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3383                 return -EINVAL;
3384         }
3385
3386         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3387                 idx = i / RTE_RETA_GROUP_SIZE;
3388                 shift = i % RTE_RETA_GROUP_SIZE;
3389                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3390                                                 IGB_4_BIT_MASK);
3391                 if (!mask)
3392                         continue;
3393                 if (mask == IGB_4_BIT_MASK)
3394                         r = 0;
3395                 else
3396                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3397                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3398                         if (mask & (0x1 << j))
3399                                 reta |= reta_conf[idx].reta[shift + j] <<
3400                                                         (CHAR_BIT * j);
3401                         else
3402                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3403                 }
3404                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3405         }
3406
3407         return 0;
3408 }
3409
3410 static int
3411 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3412                        struct rte_eth_rss_reta_entry64 *reta_conf,
3413                        uint16_t reta_size)
3414 {
3415         uint8_t i, j, mask;
3416         uint32_t reta;
3417         uint16_t idx, shift;
3418         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419
3420         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3421                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3422                         "(%d) doesn't match the number hardware can supported "
3423                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3424                 return -EINVAL;
3425         }
3426
3427         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3428                 idx = i / RTE_RETA_GROUP_SIZE;
3429                 shift = i % RTE_RETA_GROUP_SIZE;
3430                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3431                                                 IGB_4_BIT_MASK);
3432                 if (!mask)
3433                         continue;
3434                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3435                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3436                         if (mask & (0x1 << j))
3437                                 reta_conf[idx].reta[shift + j] =
3438                                         ((reta >> (CHAR_BIT * j)) &
3439                                                 IGB_8_BIT_MASK);
3440                 }
3441         }
3442
3443         return 0;
3444 }
3445
3446 #define MAC_TYPE_FILTER_SUP(type)    do {\
3447         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3448                 (type) != e1000_82576)\
3449                 return -ENOTSUP;\
3450 } while (0)
3451
3452 static int
3453 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3454                         struct rte_eth_syn_filter *filter,
3455                         bool add)
3456 {
3457         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458         uint32_t synqf, rfctl;
3459
3460         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3461                 return -EINVAL;
3462
3463         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3464
3465         if (add) {
3466                 if (synqf & E1000_SYN_FILTER_ENABLE)
3467                         return -EINVAL;
3468
3469                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3470                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3471
3472                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3473                 if (filter->hig_pri)
3474                         rfctl |= E1000_RFCTL_SYNQFP;
3475                 else
3476                         rfctl &= ~E1000_RFCTL_SYNQFP;
3477
3478                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3479         } else {
3480                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3481                         return -ENOENT;
3482                 synqf = 0;
3483         }
3484
3485         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3486         E1000_WRITE_FLUSH(hw);
3487         return 0;
3488 }
3489
3490 static int
3491 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3492                         struct rte_eth_syn_filter *filter)
3493 {
3494         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495         uint32_t synqf, rfctl;
3496
3497         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3498         if (synqf & E1000_SYN_FILTER_ENABLE) {
3499                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3500                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3501                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3502                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3503                 return 0;
3504         }
3505
3506         return -ENOENT;
3507 }
3508
3509 static int
3510 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3511                         enum rte_filter_op filter_op,
3512                         void *arg)
3513 {
3514         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515         int ret;
3516
3517         MAC_TYPE_FILTER_SUP(hw->mac.type);
3518
3519         if (filter_op == RTE_ETH_FILTER_NOP)
3520                 return 0;
3521
3522         if (arg == NULL) {
3523                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3524                             filter_op);
3525                 return -EINVAL;
3526         }
3527
3528         switch (filter_op) {
3529         case RTE_ETH_FILTER_ADD:
3530                 ret = eth_igb_syn_filter_set(dev,
3531                                 (struct rte_eth_syn_filter *)arg,
3532                                 TRUE);
3533                 break;
3534         case RTE_ETH_FILTER_DELETE:
3535                 ret = eth_igb_syn_filter_set(dev,
3536                                 (struct rte_eth_syn_filter *)arg,
3537                                 FALSE);
3538                 break;
3539         case RTE_ETH_FILTER_GET:
3540                 ret = eth_igb_syn_filter_get(dev,
3541                                 (struct rte_eth_syn_filter *)arg);
3542                 break;
3543         default:
3544                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3545                 ret = -EINVAL;
3546                 break;
3547         }
3548
3549         return ret;
3550 }
3551
3552 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3553         if ((type) != e1000_82580 && (type) != e1000_i350)\
3554                 return -ENOSYS; \
3555 } while (0)
3556
3557 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3558 static inline int
3559 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3560                         struct e1000_2tuple_filter_info *filter_info)
3561 {
3562         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3563                 return -EINVAL;
3564         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3565                 return -EINVAL;  /* filter index is out of range. */
3566         if (filter->tcp_flags > TCP_FLAG_ALL)
3567                 return -EINVAL;  /* flags is invalid. */
3568
3569         switch (filter->dst_port_mask) {
3570         case UINT16_MAX:
3571                 filter_info->dst_port_mask = 0;
3572                 filter_info->dst_port = filter->dst_port;
3573                 break;
3574         case 0:
3575                 filter_info->dst_port_mask = 1;
3576                 break;
3577         default:
3578                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3579                 return -EINVAL;
3580         }
3581
3582         switch (filter->proto_mask) {
3583         case UINT8_MAX:
3584                 filter_info->proto_mask = 0;
3585                 filter_info->proto = filter->proto;
3586                 break;
3587         case 0:
3588                 filter_info->proto_mask = 1;
3589                 break;
3590         default:
3591                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3592                 return -EINVAL;
3593         }
3594
3595         filter_info->priority = (uint8_t)filter->priority;
3596         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3597                 filter_info->tcp_flags = filter->tcp_flags;
3598         else
3599                 filter_info->tcp_flags = 0;
3600
3601         return 0;
3602 }
3603
3604 static inline struct e1000_2tuple_filter *
3605 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3606                         struct e1000_2tuple_filter_info *key)
3607 {
3608         struct e1000_2tuple_filter *it;
3609
3610         TAILQ_FOREACH(it, filter_list, entries) {
3611                 if (memcmp(key, &it->filter_info,
3612                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3613                         return it;
3614                 }
3615         }
3616         return NULL;
3617 }
3618
3619 /*
3620  * igb_add_2tuple_filter - add a 2tuple filter
3621  *
3622  * @param
3623  * dev: Pointer to struct rte_eth_dev.
3624  * ntuple_filter: ponter to the filter that will be added.
3625  *
3626  * @return
3627  *    - On success, zero.
3628  *    - On failure, a negative value.
3629  */
3630 static int
3631 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3632                         struct rte_eth_ntuple_filter *ntuple_filter)
3633 {
3634         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3635         struct e1000_filter_info *filter_info =
3636                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3637         struct e1000_2tuple_filter *filter;
3638         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3639         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3640         int i, ret;
3641
3642         filter = rte_zmalloc("e1000_2tuple_filter",
3643                         sizeof(struct e1000_2tuple_filter), 0);
3644         if (filter == NULL)
3645                 return -ENOMEM;
3646
3647         ret = ntuple_filter_to_2tuple(ntuple_filter,
3648                                       &filter->filter_info);
3649         if (ret < 0) {
3650                 rte_free(filter);
3651                 return ret;
3652         }
3653         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3654                                          &filter->filter_info) != NULL) {
3655                 PMD_DRV_LOG(ERR, "filter exists.");
3656                 rte_free(filter);
3657                 return -EEXIST;
3658         }
3659         filter->queue = ntuple_filter->queue;
3660
3661         /*
3662          * look for an unused 2tuple filter index,
3663          * and insert the filter to list.
3664          */
3665         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3666                 if (!(filter_info->twotuple_mask & (1 << i))) {
3667                         filter_info->twotuple_mask |= 1 << i;
3668                         filter->index = i;
3669                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3670                                           filter,
3671                                           entries);
3672                         break;
3673                 }
3674         }
3675         if (i >= E1000_MAX_TTQF_FILTERS) {
3676                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3677                 rte_free(filter);
3678                 return -ENOSYS;
3679         }
3680
3681         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3682         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3683                 imir |= E1000_IMIR_PORT_BP;
3684         else
3685                 imir &= ~E1000_IMIR_PORT_BP;
3686
3687         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3688
3689         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3690         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3691         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3692         if (filter->filter_info.proto_mask == 0)
3693                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3694
3695         /* tcp flags bits setting. */
3696         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3697                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3698                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3699                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3700                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3701                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3702                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3703                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3704                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3705                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3706                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3707                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3708                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3709         } else
3710                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3711         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3712         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3713         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3714         return 0;
3715 }
3716
3717 /*
3718  * igb_remove_2tuple_filter - remove a 2tuple filter
3719  *
3720  * @param
3721  * dev: Pointer to struct rte_eth_dev.
3722  * ntuple_filter: ponter to the filter that will be removed.
3723  *
3724  * @return
3725  *    - On success, zero.
3726  *    - On failure, a negative value.
3727  */
3728 static int
3729 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3730                         struct rte_eth_ntuple_filter *ntuple_filter)
3731 {
3732         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733         struct e1000_filter_info *filter_info =
3734                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3735         struct e1000_2tuple_filter_info filter_2tuple;
3736         struct e1000_2tuple_filter *filter;
3737         int ret;
3738
3739         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3740         ret = ntuple_filter_to_2tuple(ntuple_filter,
3741                                       &filter_2tuple);
3742         if (ret < 0)
3743                 return ret;
3744
3745         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3746                                          &filter_2tuple);
3747         if (filter == NULL) {
3748                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3749                 return -ENOENT;
3750         }
3751
3752         filter_info->twotuple_mask &= ~(1 << filter->index);
3753         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3754         rte_free(filter);
3755
3756         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3757         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3758         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3759         return 0;
3760 }
3761
3762 static inline struct e1000_flex_filter *
3763 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3764                         struct e1000_flex_filter_info *key)
3765 {
3766         struct e1000_flex_filter *it;
3767
3768         TAILQ_FOREACH(it, filter_list, entries) {
3769                 if (memcmp(key, &it->filter_info,
3770                         sizeof(struct e1000_flex_filter_info)) == 0)
3771                         return it;
3772         }
3773
3774         return NULL;
3775 }
3776
3777 static int
3778 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3779                         struct rte_eth_flex_filter *filter,
3780                         bool add)
3781 {
3782         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         struct e1000_filter_info *filter_info =
3784                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3785         struct e1000_flex_filter *flex_filter, *it;
3786         uint32_t wufc, queueing, mask;
3787         uint32_t reg_off;
3788         uint8_t shift, i, j = 0;
3789
3790         flex_filter = rte_zmalloc("e1000_flex_filter",
3791                         sizeof(struct e1000_flex_filter), 0);
3792         if (flex_filter == NULL)
3793                 return -ENOMEM;
3794
3795         flex_filter->filter_info.len = filter->len;
3796         flex_filter->filter_info.priority = filter->priority;
3797         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3798         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3799                 mask = 0;
3800                 /* reverse bits in flex filter's mask*/
3801                 for (shift = 0; shift < CHAR_BIT; shift++) {
3802                         if (filter->mask[i] & (0x01 << shift))
3803                                 mask |= (0x80 >> shift);
3804                 }
3805                 flex_filter->filter_info.mask[i] = mask;
3806         }
3807
3808         wufc = E1000_READ_REG(hw, E1000_WUFC);
3809         if (flex_filter->index < E1000_MAX_FHFT)
3810                 reg_off = E1000_FHFT(flex_filter->index);
3811         else
3812                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3813
3814         if (add) {
3815                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3816                                 &flex_filter->filter_info) != NULL) {
3817                         PMD_DRV_LOG(ERR, "filter exists.");
3818                         rte_free(flex_filter);
3819                         return -EEXIST;
3820                 }
3821                 flex_filter->queue = filter->queue;
3822                 /*
3823                  * look for an unused flex filter index
3824                  * and insert the filter into the list.
3825                  */
3826                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3827                         if (!(filter_info->flex_mask & (1 << i))) {
3828                                 filter_info->flex_mask |= 1 << i;
3829                                 flex_filter->index = i;
3830                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3831                                         flex_filter,
3832                                         entries);
3833                                 break;
3834                         }
3835                 }
3836                 if (i >= E1000_MAX_FLEX_FILTERS) {
3837                         PMD_DRV_LOG(ERR, "flex filters are full.");
3838                         rte_free(flex_filter);
3839                         return -ENOSYS;
3840                 }
3841
3842                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3843                                 (E1000_WUFC_FLX0 << flex_filter->index));
3844                 queueing = filter->len |
3845                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3846                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3847                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3848                                 queueing);
3849                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3850                         E1000_WRITE_REG(hw, reg_off,
3851                                         flex_filter->filter_info.dwords[j]);
3852                         reg_off += sizeof(uint32_t);
3853                         E1000_WRITE_REG(hw, reg_off,
3854                                         flex_filter->filter_info.dwords[++j]);
3855                         reg_off += sizeof(uint32_t);
3856                         E1000_WRITE_REG(hw, reg_off,
3857                                 (uint32_t)flex_filter->filter_info.mask[i]);
3858                         reg_off += sizeof(uint32_t) * 2;
3859                         ++j;
3860                 }
3861         } else {
3862                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3863                                 &flex_filter->filter_info);
3864                 if (it == NULL) {
3865                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3866                         rte_free(flex_filter);
3867                         return -ENOENT;
3868                 }
3869
3870                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3871                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3872                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3873                         (~(E1000_WUFC_FLX0 << it->index)));
3874
3875                 filter_info->flex_mask &= ~(1 << it->index);
3876                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3877                 rte_free(it);
3878                 rte_free(flex_filter);
3879         }
3880
3881         return 0;
3882 }
3883
3884 static int
3885 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3886                         struct rte_eth_flex_filter *filter)
3887 {
3888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889         struct e1000_filter_info *filter_info =
3890                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3891         struct e1000_flex_filter flex_filter, *it;
3892         uint32_t wufc, queueing, wufc_en = 0;
3893
3894         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3895         flex_filter.filter_info.len = filter->len;
3896         flex_filter.filter_info.priority = filter->priority;
3897         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3898         memcpy(flex_filter.filter_info.mask, filter->mask,
3899                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3900
3901         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3902                                 &flex_filter.filter_info);
3903         if (it == NULL) {
3904                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3905                 return -ENOENT;
3906         }
3907
3908         wufc = E1000_READ_REG(hw, E1000_WUFC);
3909         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3910
3911         if ((wufc & wufc_en) == wufc_en) {
3912                 uint32_t reg_off = 0;
3913                 if (it->index < E1000_MAX_FHFT)
3914                         reg_off = E1000_FHFT(it->index);
3915                 else
3916                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3917
3918                 queueing = E1000_READ_REG(hw,
3919                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3920                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3921                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3922                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3923                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3924                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3925                 return 0;
3926         }
3927         return -ENOENT;
3928 }
3929
3930 static int
3931 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3932                         enum rte_filter_op filter_op,
3933                         void *arg)
3934 {
3935         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936         struct rte_eth_flex_filter *filter;
3937         int ret = 0;
3938
3939         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3940
3941         if (filter_op == RTE_ETH_FILTER_NOP)
3942                 return ret;
3943
3944         if (arg == NULL) {
3945                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3946                             filter_op);
3947                 return -EINVAL;
3948         }
3949
3950         filter = (struct rte_eth_flex_filter *)arg;
3951         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3952             || filter->len % sizeof(uint64_t) != 0) {
3953                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3954                 return -EINVAL;
3955         }
3956         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3957                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3958                 return -EINVAL;
3959         }
3960
3961         switch (filter_op) {
3962         case RTE_ETH_FILTER_ADD:
3963                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3964                 break;
3965         case RTE_ETH_FILTER_DELETE:
3966                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3967                 break;
3968         case RTE_ETH_FILTER_GET:
3969                 ret = eth_igb_get_flex_filter(dev, filter);
3970                 break;
3971         default:
3972                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3973                 ret = -EINVAL;
3974                 break;
3975         }
3976
3977         return ret;
3978 }
3979
3980 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3981 static inline int
3982 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3983                         struct e1000_5tuple_filter_info *filter_info)
3984 {
3985         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3986                 return -EINVAL;
3987         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3988                 return -EINVAL;  /* filter index is out of range. */
3989         if (filter->tcp_flags > TCP_FLAG_ALL)
3990                 return -EINVAL;  /* flags is invalid. */
3991
3992         switch (filter->dst_ip_mask) {
3993         case UINT32_MAX:
3994                 filter_info->dst_ip_mask = 0;
3995                 filter_info->dst_ip = filter->dst_ip;
3996                 break;
3997         case 0:
3998                 filter_info->dst_ip_mask = 1;
3999                 break;
4000         default:
4001                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4002                 return -EINVAL;
4003         }
4004
4005         switch (filter->src_ip_mask) {
4006         case UINT32_MAX:
4007                 filter_info->src_ip_mask = 0;
4008                 filter_info->src_ip = filter->src_ip;
4009                 break;
4010         case 0:
4011                 filter_info->src_ip_mask = 1;
4012                 break;
4013         default:
4014                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4015                 return -EINVAL;
4016         }
4017
4018         switch (filter->dst_port_mask) {
4019         case UINT16_MAX:
4020                 filter_info->dst_port_mask = 0;
4021                 filter_info->dst_port = filter->dst_port;
4022                 break;
4023         case 0:
4024                 filter_info->dst_port_mask = 1;
4025                 break;
4026         default:
4027                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4028                 return -EINVAL;
4029         }
4030
4031         switch (filter->src_port_mask) {
4032         case UINT16_MAX:
4033                 filter_info->src_port_mask = 0;
4034                 filter_info->src_port = filter->src_port;
4035                 break;
4036         case 0:
4037                 filter_info->src_port_mask = 1;
4038                 break;
4039         default:
4040                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4041                 return -EINVAL;
4042         }
4043
4044         switch (filter->proto_mask) {
4045         case UINT8_MAX:
4046                 filter_info->proto_mask = 0;
4047                 filter_info->proto = filter->proto;
4048                 break;
4049         case 0:
4050                 filter_info->proto_mask = 1;
4051                 break;
4052         default:
4053                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4054                 return -EINVAL;
4055         }
4056
4057         filter_info->priority = (uint8_t)filter->priority;
4058         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4059                 filter_info->tcp_flags = filter->tcp_flags;
4060         else
4061                 filter_info->tcp_flags = 0;
4062
4063         return 0;
4064 }
4065
4066 static inline struct e1000_5tuple_filter *
4067 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4068                         struct e1000_5tuple_filter_info *key)
4069 {
4070         struct e1000_5tuple_filter *it;
4071
4072         TAILQ_FOREACH(it, filter_list, entries) {
4073                 if (memcmp(key, &it->filter_info,
4074                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4075                         return it;
4076                 }
4077         }
4078         return NULL;
4079 }
4080
4081 /*
4082  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4083  *
4084  * @param
4085  * dev: Pointer to struct rte_eth_dev.
4086  * ntuple_filter: ponter to the filter that will be added.
4087  *
4088  * @return
4089  *    - On success, zero.
4090  *    - On failure, a negative value.
4091  */
4092 static int
4093 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4094                         struct rte_eth_ntuple_filter *ntuple_filter)
4095 {
4096         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097         struct e1000_filter_info *filter_info =
4098                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4099         struct e1000_5tuple_filter *filter;
4100         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4101         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4102         uint8_t i;
4103         int ret;
4104
4105         filter = rte_zmalloc("e1000_5tuple_filter",
4106                         sizeof(struct e1000_5tuple_filter), 0);
4107         if (filter == NULL)
4108                 return -ENOMEM;
4109
4110         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4111                                             &filter->filter_info);
4112         if (ret < 0) {
4113                 rte_free(filter);
4114                 return ret;
4115         }
4116
4117         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4118                                          &filter->filter_info) != NULL) {
4119                 PMD_DRV_LOG(ERR, "filter exists.");
4120                 rte_free(filter);
4121                 return -EEXIST;
4122         }
4123         filter->queue = ntuple_filter->queue;
4124
4125         /*
4126          * look for an unused 5tuple filter index,
4127          * and insert the filter to list.
4128          */
4129         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4130                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4131                         filter_info->fivetuple_mask |= 1 << i;
4132                         filter->index = i;
4133                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4134                                           filter,
4135                                           entries);
4136                         break;
4137                 }
4138         }
4139         if (i >= E1000_MAX_FTQF_FILTERS) {
4140                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4141                 rte_free(filter);
4142                 return -ENOSYS;
4143         }
4144
4145         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4146         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4147                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4148         if (filter->filter_info.dst_ip_mask == 0)
4149                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4150         if (filter->filter_info.src_port_mask == 0)
4151                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4152         if (filter->filter_info.proto_mask == 0)
4153                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4154         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4155                 E1000_FTQF_QUEUE_MASK;
4156         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4157         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4158         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4159         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4160
4161         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4162         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4163
4164         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4165         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4166                 imir |= E1000_IMIR_PORT_BP;
4167         else
4168                 imir &= ~E1000_IMIR_PORT_BP;
4169         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4170
4171         /* tcp flags bits setting. */
4172         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4173                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4174                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4175                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4176                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4177                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4178                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4179                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4180                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4181                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4182                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4183                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4184                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4185         } else
4186                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4187         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4188         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4189         return 0;
4190 }
4191
4192 /*
4193  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4194  *
4195  * @param
4196  * dev: Pointer to struct rte_eth_dev.
4197  * ntuple_filter: ponter to the filter that will be removed.
4198  *
4199  * @return
4200  *    - On success, zero.
4201  *    - On failure, a negative value.
4202  */
4203 static int
4204 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4205                                 struct rte_eth_ntuple_filter *ntuple_filter)
4206 {
4207         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4208         struct e1000_filter_info *filter_info =
4209                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4210         struct e1000_5tuple_filter_info filter_5tuple;
4211         struct e1000_5tuple_filter *filter;
4212         int ret;
4213
4214         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4215         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4216                                             &filter_5tuple);
4217         if (ret < 0)
4218                 return ret;
4219
4220         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4221                                          &filter_5tuple);
4222         if (filter == NULL) {
4223                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4224                 return -ENOENT;
4225         }
4226
4227         filter_info->fivetuple_mask &= ~(1 << filter->index);
4228         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4229         rte_free(filter);
4230
4231         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4232                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4233         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4234         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4235         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4236         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4237         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4238         return 0;
4239 }
4240
4241 static int
4242 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4243 {
4244         uint32_t rctl;
4245         struct e1000_hw *hw;
4246         struct rte_eth_dev_info dev_info;
4247         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4248                                      VLAN_TAG_SIZE);
4249
4250         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4251
4252 #ifdef RTE_LIBRTE_82571_SUPPORT
4253         /* XXX: not bigger than max_rx_pktlen */
4254         if (hw->mac.type == e1000_82571)
4255                 return -ENOTSUP;
4256 #endif
4257         eth_igb_infos_get(dev, &dev_info);
4258
4259         /* check that mtu is within the allowed range */
4260         if ((mtu < ETHER_MIN_MTU) ||
4261             (frame_size > dev_info.max_rx_pktlen))
4262                 return -EINVAL;
4263
4264         /* refuse mtu that requires the support of scattered packets when this
4265          * feature has not been enabled before. */
4266         if (!dev->data->scattered_rx &&
4267             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4268                 return -EINVAL;
4269
4270         rctl = E1000_READ_REG(hw, E1000_RCTL);
4271
4272         /* switch to jumbo mode if needed */
4273         if (frame_size > ETHER_MAX_LEN) {
4274                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4275                 rctl |= E1000_RCTL_LPE;
4276         } else {
4277                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4278                 rctl &= ~E1000_RCTL_LPE;
4279         }
4280         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4281
4282         /* update max frame size */
4283         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4284
4285         E1000_WRITE_REG(hw, E1000_RLPML,
4286                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4287
4288         return 0;
4289 }
4290
4291 /*
4292  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4293  *
4294  * @param
4295  * dev: Pointer to struct rte_eth_dev.
4296  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4297  * add: if true, add filter, if false, remove filter
4298  *
4299  * @return
4300  *    - On success, zero.
4301  *    - On failure, a negative value.
4302  */
4303 static int
4304 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4305                         struct rte_eth_ntuple_filter *ntuple_filter,
4306                         bool add)
4307 {
4308         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4309         int ret;
4310
4311         switch (ntuple_filter->flags) {
4312         case RTE_5TUPLE_FLAGS:
4313         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4314                 if (hw->mac.type != e1000_82576)
4315                         return -ENOTSUP;
4316                 if (add)
4317                         ret = igb_add_5tuple_filter_82576(dev,
4318                                                           ntuple_filter);
4319                 else
4320                         ret = igb_remove_5tuple_filter_82576(dev,
4321                                                              ntuple_filter);
4322                 break;
4323         case RTE_2TUPLE_FLAGS:
4324         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4325                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4326                         return -ENOTSUP;
4327                 if (add)
4328                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4329                 else
4330                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4331                 break;
4332         default:
4333                 ret = -EINVAL;
4334                 break;
4335         }
4336
4337         return ret;
4338 }
4339
4340 /*
4341  * igb_get_ntuple_filter - get a ntuple filter
4342  *
4343  * @param
4344  * dev: Pointer to struct rte_eth_dev.
4345  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4346  *
4347  * @return
4348  *    - On success, zero.
4349  *    - On failure, a negative value.
4350  */
4351 static int
4352 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4353                         struct rte_eth_ntuple_filter *ntuple_filter)
4354 {
4355         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356         struct e1000_filter_info *filter_info =
4357                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4358         struct e1000_5tuple_filter_info filter_5tuple;
4359         struct e1000_2tuple_filter_info filter_2tuple;
4360         struct e1000_5tuple_filter *p_5tuple_filter;
4361         struct e1000_2tuple_filter *p_2tuple_filter;
4362         int ret;
4363
4364         switch (ntuple_filter->flags) {
4365         case RTE_5TUPLE_FLAGS:
4366         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4367                 if (hw->mac.type != e1000_82576)
4368                         return -ENOTSUP;
4369                 memset(&filter_5tuple,
4370                         0,
4371                         sizeof(struct e1000_5tuple_filter_info));
4372                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4373                                                     &filter_5tuple);
4374                 if (ret < 0)
4375                         return ret;
4376                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4377                                         &filter_info->fivetuple_list,
4378                                         &filter_5tuple);
4379                 if (p_5tuple_filter == NULL) {
4380                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4381                         return -ENOENT;
4382                 }
4383                 ntuple_filter->queue = p_5tuple_filter->queue;
4384                 break;
4385         case RTE_2TUPLE_FLAGS:
4386         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4387                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4388                         return -ENOTSUP;
4389                 memset(&filter_2tuple,
4390                         0,
4391                         sizeof(struct e1000_2tuple_filter_info));
4392                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4393                 if (ret < 0)
4394                         return ret;
4395                 p_2tuple_filter = igb_2tuple_filter_lookup(
4396                                         &filter_info->twotuple_list,
4397                                         &filter_2tuple);
4398                 if (p_2tuple_filter == NULL) {
4399                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4400                         return -ENOENT;
4401                 }
4402                 ntuple_filter->queue = p_2tuple_filter->queue;
4403                 break;
4404         default:
4405                 ret = -EINVAL;
4406                 break;
4407         }
4408
4409         return 0;
4410 }
4411
4412 /*
4413  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4414  * @dev: pointer to rte_eth_dev structure
4415  * @filter_op:operation will be taken.
4416  * @arg: a pointer to specific structure corresponding to the filter_op
4417  */
4418 static int
4419 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4420                                 enum rte_filter_op filter_op,
4421                                 void *arg)
4422 {
4423         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         int ret;
4425
4426         MAC_TYPE_FILTER_SUP(hw->mac.type);
4427
4428         if (filter_op == RTE_ETH_FILTER_NOP)
4429                 return 0;
4430
4431         if (arg == NULL) {
4432                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4433                             filter_op);
4434                 return -EINVAL;
4435         }
4436
4437         switch (filter_op) {
4438         case RTE_ETH_FILTER_ADD:
4439                 ret = igb_add_del_ntuple_filter(dev,
4440                         (struct rte_eth_ntuple_filter *)arg,
4441                         TRUE);
4442                 break;
4443         case RTE_ETH_FILTER_DELETE:
4444                 ret = igb_add_del_ntuple_filter(dev,
4445                         (struct rte_eth_ntuple_filter *)arg,
4446                         FALSE);
4447                 break;
4448         case RTE_ETH_FILTER_GET:
4449                 ret = igb_get_ntuple_filter(dev,
4450                         (struct rte_eth_ntuple_filter *)arg);
4451                 break;
4452         default:
4453                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4454                 ret = -EINVAL;
4455                 break;
4456         }
4457         return ret;
4458 }
4459
4460 static inline int
4461 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4462                         uint16_t ethertype)
4463 {
4464         int i;
4465
4466         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4467                 if (filter_info->ethertype_filters[i] == ethertype &&
4468                     (filter_info->ethertype_mask & (1 << i)))
4469                         return i;
4470         }
4471         return -1;
4472 }
4473
4474 static inline int
4475 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4476                         uint16_t ethertype)
4477 {
4478         int i;
4479
4480         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4481                 if (!(filter_info->ethertype_mask & (1 << i))) {
4482                         filter_info->ethertype_mask |= 1 << i;
4483                         filter_info->ethertype_filters[i] = ethertype;
4484                         return i;
4485                 }
4486         }
4487         return -1;
4488 }
4489
4490 static inline int
4491 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4492                         uint8_t idx)
4493 {
4494         if (idx >= E1000_MAX_ETQF_FILTERS)
4495                 return -1;
4496         filter_info->ethertype_mask &= ~(1 << idx);
4497         filter_info->ethertype_filters[idx] = 0;
4498         return idx;
4499 }
4500
4501
4502 static int
4503 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4504                         struct rte_eth_ethertype_filter *filter,
4505                         bool add)
4506 {
4507         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4508         struct e1000_filter_info *filter_info =
4509                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4510         uint32_t etqf = 0;
4511         int ret;
4512
4513         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4514                 filter->ether_type == ETHER_TYPE_IPv6) {
4515                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4516                         " ethertype filter.", filter->ether_type);
4517                 return -EINVAL;
4518         }
4519
4520         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4521                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4522                 return -EINVAL;
4523         }
4524         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4525                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4526                 return -EINVAL;
4527         }
4528
4529         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4530         if (ret >= 0 && add) {
4531                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4532                             filter->ether_type);
4533                 return -EEXIST;
4534         }
4535         if (ret < 0 && !add) {
4536                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4537                             filter->ether_type);
4538                 return -ENOENT;
4539         }
4540
4541         if (add) {
4542                 ret = igb_ethertype_filter_insert(filter_info,
4543                         filter->ether_type);
4544                 if (ret < 0) {
4545                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4546                         return -ENOSYS;
4547                 }
4548
4549                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4550                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4551                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4552         } else {
4553                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4554                 if (ret < 0)
4555                         return -ENOSYS;
4556         }
4557         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4558         E1000_WRITE_FLUSH(hw);
4559
4560         return 0;
4561 }
4562
4563 static int
4564 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4565                         struct rte_eth_ethertype_filter *filter)
4566 {
4567         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4568         struct e1000_filter_info *filter_info =
4569                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4570         uint32_t etqf;
4571         int ret;
4572
4573         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4574         if (ret < 0) {
4575                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4576                             filter->ether_type);
4577                 return -ENOENT;
4578         }
4579
4580         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4581         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4582                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4583                 filter->flags = 0;
4584                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4585                                 E1000_ETQF_QUEUE_SHIFT;
4586                 return 0;
4587         }
4588
4589         return -ENOENT;
4590 }
4591
4592 /*
4593  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4594  * @dev: pointer to rte_eth_dev structure
4595  * @filter_op:operation will be taken.
4596  * @arg: a pointer to specific structure corresponding to the filter_op
4597  */
4598 static int
4599 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4600                                 enum rte_filter_op filter_op,
4601                                 void *arg)
4602 {
4603         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4604         int ret;
4605
4606         MAC_TYPE_FILTER_SUP(hw->mac.type);
4607
4608         if (filter_op == RTE_ETH_FILTER_NOP)
4609                 return 0;
4610
4611         if (arg == NULL) {
4612                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4613                             filter_op);
4614                 return -EINVAL;
4615         }
4616
4617         switch (filter_op) {
4618         case RTE_ETH_FILTER_ADD:
4619                 ret = igb_add_del_ethertype_filter(dev,
4620                         (struct rte_eth_ethertype_filter *)arg,
4621                         TRUE);
4622                 break;
4623         case RTE_ETH_FILTER_DELETE:
4624                 ret = igb_add_del_ethertype_filter(dev,
4625                         (struct rte_eth_ethertype_filter *)arg,
4626                         FALSE);
4627                 break;
4628         case RTE_ETH_FILTER_GET:
4629                 ret = igb_get_ethertype_filter(dev,
4630                         (struct rte_eth_ethertype_filter *)arg);
4631                 break;
4632         default:
4633                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4634                 ret = -EINVAL;
4635                 break;
4636         }
4637         return ret;
4638 }
4639
4640 static int
4641 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4642                      enum rte_filter_type filter_type,
4643                      enum rte_filter_op filter_op,
4644                      void *arg)
4645 {
4646         int ret = -EINVAL;
4647
4648         switch (filter_type) {
4649         case RTE_ETH_FILTER_NTUPLE:
4650                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4651                 break;
4652         case RTE_ETH_FILTER_ETHERTYPE:
4653                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4654                 break;
4655         case RTE_ETH_FILTER_SYN:
4656                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4657                 break;
4658         case RTE_ETH_FILTER_FLEXIBLE:
4659                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4660                 break;
4661         default:
4662                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4663                                                         filter_type);
4664                 break;
4665         }
4666
4667         return ret;
4668 }
4669
4670 static int
4671 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4672                          struct ether_addr *mc_addr_set,
4673                          uint32_t nb_mc_addr)
4674 {
4675         struct e1000_hw *hw;
4676
4677         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4679         return 0;
4680 }
4681
4682 static uint64_t
4683 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4684 {
4685         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686         uint64_t systime_cycles;
4687
4688         switch (hw->mac.type) {
4689         case e1000_i210:
4690         case e1000_i211:
4691                 /*
4692                  * Need to read System Time Residue Register to be able
4693                  * to read the other two registers.
4694                  */
4695                 E1000_READ_REG(hw, E1000_SYSTIMR);
4696                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4697                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4698                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4699                                 * NSEC_PER_SEC;
4700                 break;
4701         case e1000_82580:
4702         case e1000_i350:
4703         case e1000_i354:
4704                 /*
4705                  * Need to read System Time Residue Register to be able
4706                  * to read the other two registers.
4707                  */
4708                 E1000_READ_REG(hw, E1000_SYSTIMR);
4709                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4710                 /* Only the 8 LSB are valid. */
4711                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4712                                 & 0xff) << 32;
4713                 break;
4714         default:
4715                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4716                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4717                                 << 32;
4718                 break;
4719         }
4720
4721         return systime_cycles;
4722 }
4723
4724 static uint64_t
4725 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4726 {
4727         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728         uint64_t rx_tstamp_cycles;
4729
4730         switch (hw->mac.type) {
4731         case e1000_i210:
4732         case e1000_i211:
4733                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4734                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4735                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4736                                 * NSEC_PER_SEC;
4737                 break;
4738         case e1000_82580:
4739         case e1000_i350:
4740         case e1000_i354:
4741                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4742                 /* Only the 8 LSB are valid. */
4743                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4744                                 & 0xff) << 32;
4745                 break;
4746         default:
4747                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4748                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4749                                 << 32;
4750                 break;
4751         }
4752
4753         return rx_tstamp_cycles;
4754 }
4755
4756 static uint64_t
4757 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4758 {
4759         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4760         uint64_t tx_tstamp_cycles;
4761
4762         switch (hw->mac.type) {
4763         case e1000_i210:
4764         case e1000_i211:
4765                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4766                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4767                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4768                                 * NSEC_PER_SEC;
4769                 break;
4770         case e1000_82580:
4771         case e1000_i350:
4772         case e1000_i354:
4773                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4774                 /* Only the 8 LSB are valid. */
4775                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4776                                 & 0xff) << 32;
4777                 break;
4778         default:
4779                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4780                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4781                                 << 32;
4782                 break;
4783         }
4784
4785         return tx_tstamp_cycles;
4786 }
4787
4788 static void
4789 igb_start_timecounters(struct rte_eth_dev *dev)
4790 {
4791         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4792         struct e1000_adapter *adapter =
4793                 (struct e1000_adapter *)dev->data->dev_private;
4794         uint32_t incval = 1;
4795         uint32_t shift = 0;
4796         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4797
4798         switch (hw->mac.type) {
4799         case e1000_82580:
4800         case e1000_i350:
4801         case e1000_i354:
4802                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4803                 mask = (1ULL << 40) - 1;
4804                 /* fall-through */
4805         case e1000_i210:
4806         case e1000_i211:
4807                 /*
4808                  * Start incrementing the register
4809                  * used to timestamp PTP packets.
4810                  */
4811                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4812                 break;
4813         case e1000_82576:
4814                 incval = E1000_INCVALUE_82576;
4815                 shift = IGB_82576_TSYNC_SHIFT;
4816                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4817                                 E1000_INCPERIOD_82576 | incval);
4818                 break;
4819         default:
4820                 /* Not supported */
4821                 return;
4822         }
4823
4824         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4825         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4826         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4827
4828         adapter->systime_tc.cc_mask = mask;
4829         adapter->systime_tc.cc_shift = shift;
4830         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4831
4832         adapter->rx_tstamp_tc.cc_mask = mask;
4833         adapter->rx_tstamp_tc.cc_shift = shift;
4834         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4835
4836         adapter->tx_tstamp_tc.cc_mask = mask;
4837         adapter->tx_tstamp_tc.cc_shift = shift;
4838         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4839 }
4840
4841 static int
4842 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4843 {
4844         struct e1000_adapter *adapter =
4845                         (struct e1000_adapter *)dev->data->dev_private;
4846
4847         adapter->systime_tc.nsec += delta;
4848         adapter->rx_tstamp_tc.nsec += delta;
4849         adapter->tx_tstamp_tc.nsec += delta;
4850
4851         return 0;
4852 }
4853
4854 static int
4855 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4856 {
4857         uint64_t ns;
4858         struct e1000_adapter *adapter =
4859                         (struct e1000_adapter *)dev->data->dev_private;
4860
4861         ns = rte_timespec_to_ns(ts);
4862
4863         /* Set the timecounters to a new value. */
4864         adapter->systime_tc.nsec = ns;
4865         adapter->rx_tstamp_tc.nsec = ns;
4866         adapter->tx_tstamp_tc.nsec = ns;
4867
4868         return 0;
4869 }
4870
4871 static int
4872 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4873 {
4874         uint64_t ns, systime_cycles;
4875         struct e1000_adapter *adapter =
4876                         (struct e1000_adapter *)dev->data->dev_private;
4877
4878         systime_cycles = igb_read_systime_cyclecounter(dev);
4879         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4880         *ts = rte_ns_to_timespec(ns);
4881
4882         return 0;
4883 }
4884
4885 static int
4886 igb_timesync_enable(struct rte_eth_dev *dev)
4887 {
4888         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4889         uint32_t tsync_ctl;
4890         uint32_t tsauxc;
4891
4892         /* Stop the timesync system time. */
4893         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
4894         /* Reset the timesync system time value. */
4895         switch (hw->mac.type) {
4896         case e1000_82580:
4897         case e1000_i350:
4898         case e1000_i354:
4899         case e1000_i210:
4900         case e1000_i211:
4901                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
4902                 /* fall-through */
4903         case e1000_82576:
4904                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
4905                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
4906                 break;
4907         default:
4908                 /* Not supported. */
4909                 return -ENOTSUP;
4910         }
4911
4912         /* Enable system time for it isn't on by default. */
4913         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4914         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4915         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4916
4917         igb_start_timecounters(dev);
4918
4919         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4920         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4921                         (ETHER_TYPE_1588 |
4922                          E1000_ETQF_FILTER_ENABLE |
4923                          E1000_ETQF_1588));
4924
4925         /* Enable timestamping of received PTP packets. */
4926         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4927         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4928         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4929
4930         /* Enable Timestamping of transmitted PTP packets. */
4931         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4932         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4933         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4934
4935         return 0;
4936 }
4937
4938 static int
4939 igb_timesync_disable(struct rte_eth_dev *dev)
4940 {
4941         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4942         uint32_t tsync_ctl;
4943
4944         /* Disable timestamping of transmitted PTP packets. */
4945         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4946         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4947         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4948
4949         /* Disable timestamping of received PTP packets. */
4950         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4951         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4952         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4953
4954         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4955         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4956
4957         /* Stop incrementating the System Time registers. */
4958         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4959
4960         return 0;
4961 }
4962
4963 static int
4964 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4965                                struct timespec *timestamp,
4966                                uint32_t flags __rte_unused)
4967 {
4968         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4969         struct e1000_adapter *adapter =
4970                         (struct e1000_adapter *)dev->data->dev_private;
4971         uint32_t tsync_rxctl;
4972         uint64_t rx_tstamp_cycles;
4973         uint64_t ns;
4974
4975         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4976         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4977                 return -EINVAL;
4978
4979         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
4980         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4981         *timestamp = rte_ns_to_timespec(ns);
4982
4983         return  0;
4984 }
4985
4986 static int
4987 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4988                                struct timespec *timestamp)
4989 {
4990         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4991         struct e1000_adapter *adapter =
4992                         (struct e1000_adapter *)dev->data->dev_private;
4993         uint32_t tsync_txctl;
4994         uint64_t tx_tstamp_cycles;
4995         uint64_t ns;
4996
4997         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4998         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4999                 return -EINVAL;
5000
5001         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5002         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5003         *timestamp = rte_ns_to_timespec(ns);
5004
5005         return  0;
5006 }
5007
5008 static int
5009 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5010 {
5011         int count = 0;
5012         int g_ind = 0;
5013         const struct reg_info *reg_group;
5014
5015         while ((reg_group = igb_regs[g_ind++]))
5016                 count += igb_reg_group_count(reg_group);
5017
5018         return count;
5019 }
5020
5021 static int
5022 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5023 {
5024         int count = 0;
5025         int g_ind = 0;
5026         const struct reg_info *reg_group;
5027
5028         while ((reg_group = igbvf_regs[g_ind++]))
5029                 count += igb_reg_group_count(reg_group);
5030
5031         return count;
5032 }
5033
5034 static int
5035 eth_igb_get_regs(struct rte_eth_dev *dev,
5036         struct rte_dev_reg_info *regs)
5037 {
5038         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         uint32_t *data = regs->data;
5040         int g_ind = 0;
5041         int count = 0;
5042         const struct reg_info *reg_group;
5043
5044         if (data == NULL) {
5045                 regs->length = eth_igb_get_reg_length(dev);
5046                 regs->width = sizeof(uint32_t);
5047                 return 0;
5048         }
5049
5050         /* Support only full register dump */
5051         if ((regs->length == 0) ||
5052             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5053                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5054                         hw->device_id;
5055                 while ((reg_group = igb_regs[g_ind++]))
5056                         count += igb_read_regs_group(dev, &data[count],
5057                                                         reg_group);
5058                 return 0;
5059         }
5060
5061         return -ENOTSUP;
5062 }
5063
5064 static int
5065 igbvf_get_regs(struct rte_eth_dev *dev,
5066         struct rte_dev_reg_info *regs)
5067 {
5068         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069         uint32_t *data = regs->data;
5070         int g_ind = 0;
5071         int count = 0;
5072         const struct reg_info *reg_group;
5073
5074         if (data == NULL) {
5075                 regs->length = igbvf_get_reg_length(dev);
5076                 regs->width = sizeof(uint32_t);
5077                 return 0;
5078         }
5079
5080         /* Support only full register dump */
5081         if ((regs->length == 0) ||
5082             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5083                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5084                         hw->device_id;
5085                 while ((reg_group = igbvf_regs[g_ind++]))
5086                         count += igb_read_regs_group(dev, &data[count],
5087                                                         reg_group);
5088                 return 0;
5089         }
5090
5091         return -ENOTSUP;
5092 }
5093
5094 static int
5095 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5096 {
5097         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098
5099         /* Return unit is byte count */
5100         return hw->nvm.word_size * 2;
5101 }
5102
5103 static int
5104 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5105         struct rte_dev_eeprom_info *in_eeprom)
5106 {
5107         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5108         struct e1000_nvm_info *nvm = &hw->nvm;
5109         uint16_t *data = in_eeprom->data;
5110         int first, length;
5111
5112         first = in_eeprom->offset >> 1;
5113         length = in_eeprom->length >> 1;
5114         if ((first >= hw->nvm.word_size) ||
5115             ((first + length) >= hw->nvm.word_size))
5116                 return -EINVAL;
5117
5118         in_eeprom->magic = hw->vendor_id |
5119                 ((uint32_t)hw->device_id << 16);
5120
5121         if ((nvm->ops.read) == NULL)
5122                 return -ENOTSUP;
5123
5124         return nvm->ops.read(hw, first, length, data);
5125 }
5126
5127 static int
5128 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5129         struct rte_dev_eeprom_info *in_eeprom)
5130 {
5131         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132         struct e1000_nvm_info *nvm = &hw->nvm;
5133         uint16_t *data = in_eeprom->data;
5134         int first, length;
5135
5136         first = in_eeprom->offset >> 1;
5137         length = in_eeprom->length >> 1;
5138         if ((first >= hw->nvm.word_size) ||
5139             ((first + length) >= hw->nvm.word_size))
5140                 return -EINVAL;
5141
5142         in_eeprom->magic = (uint32_t)hw->vendor_id |
5143                 ((uint32_t)hw->device_id << 16);
5144
5145         if ((nvm->ops.write) == NULL)
5146                 return -ENOTSUP;
5147         return nvm->ops.write(hw,  first, length, data);
5148 }
5149
5150 static int
5151 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5152 {
5153         struct e1000_hw *hw =
5154                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         uint32_t mask = 1 << queue_id;
5156
5157         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5158         E1000_WRITE_FLUSH(hw);
5159
5160         return 0;
5161 }
5162
5163 static int
5164 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5165 {
5166         struct e1000_hw *hw =
5167                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5169         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5170         uint32_t mask = 1 << queue_id;
5171         uint32_t regval;
5172
5173         regval = E1000_READ_REG(hw, E1000_EIMS);
5174         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5175         E1000_WRITE_FLUSH(hw);
5176
5177         rte_intr_enable(intr_handle);
5178
5179         return 0;
5180 }
5181
5182 static void
5183 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5184                    uint8_t index, uint8_t offset)
5185 {
5186         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5187
5188         /* clear bits */
5189         val &= ~((uint32_t)0xFF << offset);
5190
5191         /* write vector and valid bit */
5192         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5193
5194         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5195 }
5196
5197 static void
5198 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5199                            uint8_t queue, uint8_t msix_vector)
5200 {
5201         uint32_t tmp = 0;
5202
5203         if (hw->mac.type == e1000_82575) {
5204                 if (direction == 0)
5205                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5206                 else if (direction == 1)
5207                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5208                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5209         } else if (hw->mac.type == e1000_82576) {
5210                 if ((direction == 0) || (direction == 1))
5211                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5212                                            ((queue & 0x8) << 1) +
5213                                            8 * direction);
5214         } else if ((hw->mac.type == e1000_82580) ||
5215                         (hw->mac.type == e1000_i350) ||
5216                         (hw->mac.type == e1000_i354) ||
5217                         (hw->mac.type == e1000_i210) ||
5218                         (hw->mac.type == e1000_i211)) {
5219                 if ((direction == 0) || (direction == 1))
5220                         eth_igb_write_ivar(hw, msix_vector,
5221                                            queue >> 1,
5222                                            ((queue & 0x1) << 4) +
5223                                            8 * direction);
5224         }
5225 }
5226
5227 /* Sets up the hardware to generate MSI-X interrupts properly
5228  * @hw
5229  *  board private structure
5230  */
5231 static void
5232 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5233 {
5234         int queue_id;
5235         uint32_t tmpval, regval, intr_mask;
5236         struct e1000_hw *hw =
5237                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238         uint32_t vec = E1000_MISC_VEC_ID;
5239         uint32_t base = E1000_MISC_VEC_ID;
5240         uint32_t misc_shift = 0;
5241         struct rte_pci_device *pci_dev = E1000_DEV_TO_PCI(dev);
5242         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5243
5244         /* won't configure msix register if no mapping is done
5245          * between intr vector and event fd
5246          */
5247         if (!rte_intr_dp_is_en(intr_handle))
5248                 return;
5249
5250         if (rte_intr_allow_others(intr_handle)) {
5251                 vec = base = E1000_RX_VEC_START;
5252                 misc_shift = 1;
5253         }
5254
5255         /* set interrupt vector for other causes */
5256         if (hw->mac.type == e1000_82575) {
5257                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5258                 /* enable MSI-X PBA support */
5259                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5260
5261                 /* Auto-Mask interrupts upon ICR read */
5262                 tmpval |= E1000_CTRL_EXT_EIAME;
5263                 tmpval |= E1000_CTRL_EXT_IRCA;
5264
5265                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5266
5267                 /* enable msix_other interrupt */
5268                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5269                 regval = E1000_READ_REG(hw, E1000_EIAC);
5270                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5271                 regval = E1000_READ_REG(hw, E1000_EIAM);
5272                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5273         } else if ((hw->mac.type == e1000_82576) ||
5274                         (hw->mac.type == e1000_82580) ||
5275                         (hw->mac.type == e1000_i350) ||
5276                         (hw->mac.type == e1000_i354) ||
5277                         (hw->mac.type == e1000_i210) ||
5278                         (hw->mac.type == e1000_i211)) {
5279                 /* turn on MSI-X capability first */
5280                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5281                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5282                                         E1000_GPIE_NSICR);
5283                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5284                         misc_shift;
5285                 regval = E1000_READ_REG(hw, E1000_EIAC);
5286                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5287
5288                 /* enable msix_other interrupt */
5289                 regval = E1000_READ_REG(hw, E1000_EIMS);
5290                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5291                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5292                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5293         }
5294
5295         /* use EIAM to auto-mask when MSI-X interrupt
5296          * is asserted, this saves a register write for every interrupt
5297          */
5298         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5299                 misc_shift;
5300         regval = E1000_READ_REG(hw, E1000_EIAM);
5301         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5302
5303         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5304                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5305                 intr_handle->intr_vec[queue_id] = vec;
5306                 if (vec < base + intr_handle->nb_efd - 1)
5307                         vec++;
5308         }
5309
5310         E1000_WRITE_FLUSH(hw);
5311 }
5312
5313 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd.pci_drv);
5314 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5315 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio");
5316 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd.pci_drv);
5317 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5318 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio");