drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memory.h>
  49 #include <rte_memzone.h>
  50 #include <rte_eal.h>
  51 #include <rte_atomic.h>
  52 #include <rte_malloc.h>
  53 #include <rte_dev.h>
  54
  55 #include "e1000_logs.h"
  56 #include "base/e1000_api.h"
  57 #include "e1000_ethdev.h"
  58 #include "igb_regs.h"
  59
  60 /*
  61  * Default values for port configuration
  62  */
  63 #define IGB_DEFAULT_RX_FREE_THRESH  32
  64 #define IGB_DEFAULT_RX_PTHRESH      8
  65 #define IGB_DEFAULT_RX_HTHRESH      8
  66 #define IGB_DEFAULT_RX_WTHRESH      0
  67
  68 #define IGB_DEFAULT_TX_PTHRESH      32
  69 #define IGB_DEFAULT_TX_HTHRESH      0
  70 #define IGB_DEFAULT_TX_WTHRESH      0
  71
  72 #define IGB_HKEY_MAX_INDEX 10
  73
  74 /* Bit shift and mask */
  75 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  76 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  77 #define IGB_8_BIT_WIDTH  CHAR_BIT
  78 #define IGB_8_BIT_MASK   UINT8_MAX
  79
  80 /* Additional timesync values. */
  81 #define E1000_ETQF_FILTER_1588 3
  82 #define E1000_TIMINCA_INCVALUE 16000000
  83 #define E1000_TIMINCA_INIT     ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
  84                                 | E1000_TIMINCA_INCVALUE)
  85 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  86
  87 static int  eth_igb_configure(struct rte_eth_dev *dev);
  88 static int  eth_igb_start(struct rte_eth_dev *dev);
  89 static void eth_igb_stop(struct rte_eth_dev *dev);
  90 static void eth_igb_close(struct rte_eth_dev *dev);
  91 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  92 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  93 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  94 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  95 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  96                                 int wait_to_complete);
  97 static void eth_igb_stats_get(struct rte_eth_dev *dev,
  98                                 struct rte_eth_stats *rte_stats);
  99 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 100                               struct rte_eth_xstats *xstats, unsigned n);
 101 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 102 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 104                               struct rte_eth_dev_info *dev_info);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
 115 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
 116                                                         void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 128 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 129
 130 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 131 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 132 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 136
 137 static int eth_igb_led_on(struct rte_eth_dev *dev);
 138 static int eth_igb_led_off(struct rte_eth_dev *dev);
 139
 140 static void igb_intr_disable(struct e1000_hw *hw);
 141 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 142 static void eth_igb_rar_set(struct rte_eth_dev *dev,
 143                 struct ether_addr *mac_addr,
 144                 uint32_t index, uint32_t pool);
 145 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 146 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 147                 struct ether_addr *addr);
 148
 149 static void igbvf_intr_disable(struct e1000_hw *hw);
 150 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 151 static int igbvf_dev_start(struct rte_eth_dev *dev);
 152 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 153 static void igbvf_dev_close(struct rte_eth_dev *dev);
 154 static int eth_igbvf_link_update(struct e1000_hw *hw);
 155 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *rte_stats);
 157 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 160 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 161                 uint16_t vlan_id, int on);
 162 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 163 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 164 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 165                 struct ether_addr *addr);
 166 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 167 static int igbvf_get_regs(struct rte_eth_dev *dev,
 168                 struct rte_dev_reg_info *regs);
 169
 170 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 171                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 172                                    uint16_t reta_size);
 173 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 174                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 175                                   uint16_t reta_size);
 176
 177 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 178                         struct rte_eth_syn_filter *filter,
 179                         bool add);
 180 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 181                         struct rte_eth_syn_filter *filter);
 182 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 183                         enum rte_filter_op filter_op,
 184                         void *arg);
 185 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 186                         struct rte_eth_ntuple_filter *ntuple_filter);
 187 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 188                         struct rte_eth_ntuple_filter *ntuple_filter);
 189 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 190                         struct rte_eth_flex_filter *filter,
 191                         bool add);
 192 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_flex_filter *filter);
 194 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 195                         enum rte_filter_op filter_op,
 196                         void *arg);
 197 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 198                         struct rte_eth_ntuple_filter *ntuple_filter);
 199 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 200                         struct rte_eth_ntuple_filter *ntuple_filter);
 201 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 202                         struct rte_eth_ntuple_filter *filter,
 203                         bool add);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 210                         struct rte_eth_ethertype_filter *filter,
 211                         bool add);
 212 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 213                                 enum rte_filter_op filter_op,
 214                                 void *arg);
 215 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 216                         struct rte_eth_ethertype_filter *filter);
 217 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 218                      enum rte_filter_type filter_type,
 219                      enum rte_filter_op filter_op,
 220                      void *arg);
 221 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 223                 struct rte_dev_reg_info *regs);
 224 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 225 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 228                 struct rte_dev_eeprom_info *eeprom);
 229 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 230                                     struct ether_addr *mc_addr_set,
 231                                     uint32_t nb_mc_addr);
 232 static int igb_timesync_enable(struct rte_eth_dev *dev);
 233 static int igb_timesync_disable(struct rte_eth_dev *dev);
 234 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp,
 236                                           uint32_t flags);
 237 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 238                                           struct timespec *timestamp);
 239 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 240                                         uint16_t queue_id);
 241 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 242                                          uint16_t queue_id);
 243 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 244                                        uint8_t queue, uint8_t msix_vector);
 245 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 246                                uint8_t index, uint8_t offset);
 247 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 248
 249 /*
 250  * Define VF Stats MACRO for Non "cleared on read" register
 251  */
 252 #define UPDATE_VF_STAT(reg, last, cur)            \
 253 {                                                 \
 254         u32 latest = E1000_READ_REG(hw, reg);     \
 255         cur += (latest - last) & UINT_MAX;        \
 256         last = latest;                            \
 257 }
 258
 259 #define IGB_FC_PAUSE_TIME 0x0680
 260 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 261 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 262
 263 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 264
 265 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 266
 267 /*
 268  * The set of PCI devices this driver supports
 269  */
 270 static const struct rte_pci_id pci_id_igb_map[] = {
 271
 272 #define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 273 #include "rte_pci_dev_ids.h"
 274
 275 {0},
 276 };
 277
 278 /*
 279  * The set of PCI devices this driver supports (for 82576&I350 VF)
 280  */
 281 static const struct rte_pci_id pci_id_igbvf_map[] = {
 282
 283 #define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 284 #include "rte_pci_dev_ids.h"
 285
 286 {0},
 287 };
 288
 289 static const struct rte_eth_desc_lim rx_desc_lim = {
 290         .nb_max = E1000_MAX_RING_DESC,
 291         .nb_min = E1000_MIN_RING_DESC,
 292         .nb_align = IGB_RXD_ALIGN,
 293 };
 294
 295 static const struct rte_eth_desc_lim tx_desc_lim = {
 296         .nb_max = E1000_MAX_RING_DESC,
 297         .nb_min = E1000_MIN_RING_DESC,
 298         .nb_align = IGB_RXD_ALIGN,
 299 };
 300
 301 static const struct eth_dev_ops eth_igb_ops = {
 302         .dev_configure        = eth_igb_configure,
 303         .dev_start            = eth_igb_start,
 304         .dev_stop             = eth_igb_stop,
 305         .dev_close            = eth_igb_close,
 306         .promiscuous_enable   = eth_igb_promiscuous_enable,
 307         .promiscuous_disable  = eth_igb_promiscuous_disable,
 308         .allmulticast_enable  = eth_igb_allmulticast_enable,
 309         .allmulticast_disable = eth_igb_allmulticast_disable,
 310         .link_update          = eth_igb_link_update,
 311         .stats_get            = eth_igb_stats_get,
 312         .xstats_get           = eth_igb_xstats_get,
 313         .stats_reset          = eth_igb_stats_reset,
 314         .xstats_reset         = eth_igb_xstats_reset,
 315         .dev_infos_get        = eth_igb_infos_get,
 316         .mtu_set              = eth_igb_mtu_set,
 317         .vlan_filter_set      = eth_igb_vlan_filter_set,
 318         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 319         .vlan_offload_set     = eth_igb_vlan_offload_set,
 320         .rx_queue_setup       = eth_igb_rx_queue_setup,
 321         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 322         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 323         .rx_queue_release     = eth_igb_rx_queue_release,
 324         .rx_queue_count       = eth_igb_rx_queue_count,
 325         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 326         .tx_queue_setup       = eth_igb_tx_queue_setup,
 327         .tx_queue_release     = eth_igb_tx_queue_release,
 328         .dev_led_on           = eth_igb_led_on,
 329         .dev_led_off          = eth_igb_led_off,
 330         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 331         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 332         .mac_addr_add         = eth_igb_rar_set,
 333         .mac_addr_remove      = eth_igb_rar_clear,
 334         .mac_addr_set         = eth_igb_default_mac_addr_set,
 335         .reta_update          = eth_igb_rss_reta_update,
 336         .reta_query           = eth_igb_rss_reta_query,
 337         .rss_hash_update      = eth_igb_rss_hash_update,
 338         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 339         .filter_ctrl          = eth_igb_filter_ctrl,
 340         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 341         .rxq_info_get         = igb_rxq_info_get,
 342         .txq_info_get         = igb_txq_info_get,
 343         .timesync_enable      = igb_timesync_enable,
 344         .timesync_disable     = igb_timesync_disable,
 345         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 346         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 347         .get_reg_length       = eth_igb_get_reg_length,
 348         .get_reg              = eth_igb_get_regs,
 349         .get_eeprom_length    = eth_igb_get_eeprom_length,
 350         .get_eeprom           = eth_igb_get_eeprom,
 351         .set_eeprom           = eth_igb_set_eeprom,
 352 };
 353
 354 /*
 355  * dev_ops for virtual function, bare necessities for basic vf
 356  * operation have been implemented
 357  */
 358 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 359         .dev_configure        = igbvf_dev_configure,
 360         .dev_start            = igbvf_dev_start,
 361         .dev_stop             = igbvf_dev_stop,
 362         .dev_close            = igbvf_dev_close,
 363         .link_update          = eth_igb_link_update,
 364         .stats_get            = eth_igbvf_stats_get,
 365         .xstats_get           = eth_igbvf_xstats_get,
 366         .stats_reset          = eth_igbvf_stats_reset,
 367         .xstats_reset         = eth_igbvf_stats_reset,
 368         .vlan_filter_set      = igbvf_vlan_filter_set,
 369         .dev_infos_get        = eth_igbvf_infos_get,
 370         .rx_queue_setup       = eth_igb_rx_queue_setup,
 371         .rx_queue_release     = eth_igb_rx_queue_release,
 372         .tx_queue_setup       = eth_igb_tx_queue_setup,
 373         .tx_queue_release     = eth_igb_tx_queue_release,
 374         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 375         .rxq_info_get         = igb_rxq_info_get,
 376         .txq_info_get         = igb_txq_info_get,
 377         .mac_addr_set         = igbvf_default_mac_addr_set,
 378         .get_reg_length       = igbvf_get_reg_length,
 379         .get_reg              = igbvf_get_regs,
 380 };
 381
 382 /* store statistics names and its offset in stats structure */
 383 struct rte_igb_xstats_name_off {
 384         char name[RTE_ETH_XSTATS_NAME_SIZE];
 385         unsigned offset;
 386 };
 387
 388 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 389         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 390         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 391         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 392         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 393         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 394         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 395         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 396                 ecol)},
 397         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 398         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 399         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 400         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 401         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 402         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 403         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 404         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 405         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 406         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 407         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 408                 fcruc)},
 409         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 410         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 411         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 412         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 413         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 414                 prc1023)},
 415         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 416                 prc1522)},
 417         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 418         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 419         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 420         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 421         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 422         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 423         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 424         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 425         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 426         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 427         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 428         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 429         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 430         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 431         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 432         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 433         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 434         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 435                 ptc1023)},
 436         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 437                 ptc1522)},
 438         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 439         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 440         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 441         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 442         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 443         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 444         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 445
 446         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 447 };
 448
 449 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 450                 sizeof(rte_igb_stats_strings[0]))
 451
 452 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 453         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 454         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 455         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 456         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 457         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 458 };
 459
 460 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 461                 sizeof(rte_igbvf_stats_strings[0]))
 462
 463 /**
 464  * Atomically reads the link status information from global
 465  * structure rte_eth_dev.
 466  *
 467  * @param dev
 468  *   - Pointer to the structure rte_eth_dev to read from.
 469  *   - Pointer to the buffer to be saved with the link status.
 470  *
 471  * @return
 472  *   - On success, zero.
 473  *   - On failure, negative value.
 474  */
 475 static inline int
 476 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 477                                 struct rte_eth_link *link)
 478 {
 479         struct rte_eth_link *dst = link;
 480         struct rte_eth_link *src = &(dev->data->dev_link);
 481
 482         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 483                                         *(uint64_t *)src) == 0)
 484                 return -1;
 485
 486         return 0;
 487 }
 488
 489 /**
 490  * Atomically writes the link status information into global
 491  * structure rte_eth_dev.
 492  *
 493  * @param dev
 494  *   - Pointer to the structure rte_eth_dev to read from.
 495  *   - Pointer to the buffer to be saved with the link status.
 496  *
 497  * @return
 498  *   - On success, zero.
 499  *   - On failure, negative value.
 500  */
 501 static inline int
 502 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 503                                 struct rte_eth_link *link)
 504 {
 505         struct rte_eth_link *dst = &(dev->data->dev_link);
 506         struct rte_eth_link *src = link;
 507
 508         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 509                                         *(uint64_t *)src) == 0)
 510                 return -1;
 511
 512         return 0;
 513 }
 514
 515 static inline void
 516 igb_intr_enable(struct rte_eth_dev *dev)
 517 {
 518         struct e1000_interrupt *intr =
 519                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 520         struct e1000_hw *hw =
 521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 522
 523         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 524         E1000_WRITE_FLUSH(hw);
 525 }
 526
 527 static void
 528 igb_intr_disable(struct e1000_hw *hw)
 529 {
 530         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 531         E1000_WRITE_FLUSH(hw);
 532 }
 533
 534 static inline int32_t
 535 igb_pf_reset_hw(struct e1000_hw *hw)
 536 {
 537         uint32_t ctrl_ext;
 538         int32_t status;
 539
 540         status = e1000_reset_hw(hw);
 541
 542         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 543         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 544         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 545         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 546         E1000_WRITE_FLUSH(hw);
 547
 548         return status;
 549 }
 550
 551 static void
 552 igb_identify_hardware(struct rte_eth_dev *dev)
 553 {
 554         struct e1000_hw *hw =
 555                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 556
 557         hw->vendor_id = dev->pci_dev->id.vendor_id;
 558         hw->device_id = dev->pci_dev->id.device_id;
 559         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
 560         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
 561
 562         e1000_set_mac_type(hw);
 563
 564         /* need to check if it is a vf device below */
 565 }
 566
 567 static int
 568 igb_reset_swfw_lock(struct e1000_hw *hw)
 569 {
 570         int ret_val;
 571
 572         /*
 573          * Do mac ops initialization manually here, since we will need
 574          * some function pointers set by this call.
 575          */
 576         ret_val = e1000_init_mac_params(hw);
 577         if (ret_val)
 578                 return ret_val;
 579
 580         /*
 581          * SMBI lock should not fail in this early stage. If this is the case,
 582          * it is due to an improper exit of the application.
 583          * So force the release of the faulty lock.
 584          */
 585         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 586                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 587         }
 588         e1000_put_hw_semaphore_generic(hw);
 589
 590         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 591                 uint16_t mask;
 592
 593                 /*
 594                  * Phy lock should not fail in this early stage. If this is the case,
 595                  * it is due to an improper exit of the application.
 596                  * So force the release of the faulty lock.
 597                  */
 598                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 599                 if (hw->bus.func > E1000_FUNC_1)
 600                         mask <<= 2;
 601                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 602                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 603                                     hw->bus.func);
 604                 }
 605                 hw->mac.ops.release_swfw_sync(hw, mask);
 606
 607                 /*
 608                  * This one is more tricky since it is common to all ports; but
 609                  * swfw_sync retries last long enough (1s) to be almost sure that if
 610                  * lock can not be taken it is due to an improper lock of the
 611                  * semaphore.
 612                  */
 613                 mask = E1000_SWFW_EEP_SM;
 614                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 615                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 616                 }
 617                 hw->mac.ops.release_swfw_sync(hw, mask);
 618         }
 619
 620         return E1000_SUCCESS;
 621 }
 622
 623 static int
 624 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 625 {
 626         int error = 0;
 627         struct rte_pci_device *pci_dev;
 628         struct e1000_hw *hw =
 629                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 630         struct e1000_vfta * shadow_vfta =
 631                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 632         struct e1000_filter_info *filter_info =
 633                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 634         struct e1000_adapter *adapter =
 635                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 636
 637         uint32_t ctrl_ext;
 638
 639         pci_dev = eth_dev->pci_dev;
 640         eth_dev->dev_ops = &eth_igb_ops;
 641         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 642         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 643
 644         /* for secondary processes, we don't initialise any further as primary
 645          * has already done this work. Only check we don't need a different
 646          * RX function */
 647         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 648                 if (eth_dev->data->scattered_rx)
 649                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 650                 return 0;
 651         }
 652
 653         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 654
 655         igb_identify_hardware(eth_dev);
 656         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 657                 error = -EIO;
 658                 goto err_late;
 659         }
 660
 661         e1000_get_bus_info(hw);
 662
 663         /* Reset any pending lock */
 664         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 665                 error = -EIO;
 666                 goto err_late;
 667         }
 668
 669         /* Finish initialization */
 670         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 671                 error = -EIO;
 672                 goto err_late;
 673         }
 674
 675         hw->mac.autoneg = 1;
 676         hw->phy.autoneg_wait_to_complete = 0;
 677         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 678
 679         /* Copper options */
 680         if (hw->phy.media_type == e1000_media_type_copper) {
 681                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 682                 hw->phy.disable_polarity_correction = 0;
 683                 hw->phy.ms_type = e1000_ms_hw_default;
 684         }
 685
 686         /*
 687          * Start from a known state, this is important in reading the nvm
 688          * and mac from that.
 689          */
 690         igb_pf_reset_hw(hw);
 691
 692         /* Make sure we have a good EEPROM before we read from it */
 693         if (e1000_validate_nvm_checksum(hw) < 0) {
 694                 /*
 695                  * Some PCI-E parts fail the first check due to
 696                  * the link being in sleep state, call it again,
 697                  * if it fails a second time its a real issue.
 698                  */
 699                 if (e1000_validate_nvm_checksum(hw) < 0) {
 700                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 701                         error = -EIO;
 702                         goto err_late;
 703                 }
 704         }
 705
 706         /* Read the permanent MAC address out of the EEPROM */
 707         if (e1000_read_mac_addr(hw) != 0) {
 708                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 709                 error = -EIO;
 710                 goto err_late;
 711         }
 712
 713         /* Allocate memory for storing MAC addresses */
 714         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 715                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 716         if (eth_dev->data->mac_addrs == NULL) {
 717                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 718                                                 "store MAC addresses",
 719                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 720                 error = -ENOMEM;
 721                 goto err_late;
 722         }
 723
 724         /* Copy the permanent MAC address */
 725         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 726
 727         /* initialize the vfta */
 728         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 729
 730         /* Now initialize the hardware */
 731         if (igb_hardware_init(hw) != 0) {
 732                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 733                 rte_free(eth_dev->data->mac_addrs);
 734                 eth_dev->data->mac_addrs = NULL;
 735                 error = -ENODEV;
 736                 goto err_late;
 737         }
 738         hw->mac.get_link_status = 1;
 739         adapter->stopped = 0;
 740
 741         /* Indicate SOL/IDER usage */
 742         if (e1000_check_reset_block(hw) < 0) {
 743                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 744                                         "SOL/IDER session");
 745         }
 746
 747         /* initialize PF if max_vfs not zero */
 748         igb_pf_host_init(eth_dev);
 749
 750         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 751         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 752         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 753         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 754         E1000_WRITE_FLUSH(hw);
 755
 756         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 757                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 758                      pci_dev->id.device_id);
 759
 760         /* enable support intr */
 761         igb_intr_enable(eth_dev);
 762
 763         TAILQ_INIT(&filter_info->flex_list);
 764         filter_info->flex_mask = 0;
 765         TAILQ_INIT(&filter_info->twotuple_list);
 766         filter_info->twotuple_mask = 0;
 767         TAILQ_INIT(&filter_info->fivetuple_list);
 768         filter_info->fivetuple_mask = 0;
 769
 770         return 0;
 771
 772 err_late:
 773         igb_hw_control_release(hw);
 774
 775         return (error);
 776 }
 777
 778 static int
 779 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 780 {
 781         struct rte_pci_device *pci_dev;
 782         struct e1000_hw *hw;
 783         struct e1000_adapter *adapter =
 784                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 785
 786         PMD_INIT_FUNC_TRACE();
 787
 788         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 789                 return -EPERM;
 790
 791         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 792         pci_dev = eth_dev->pci_dev;
 793
 794         if (adapter->stopped == 0)
 795                 eth_igb_close(eth_dev);
 796
 797         eth_dev->dev_ops = NULL;
 798         eth_dev->rx_pkt_burst = NULL;
 799         eth_dev->tx_pkt_burst = NULL;
 800
 801         /* Reset any pending lock */
 802         igb_reset_swfw_lock(hw);
 803
 804         rte_free(eth_dev->data->mac_addrs);
 805         eth_dev->data->mac_addrs = NULL;
 806
 807         /* uninitialize PF if max_vfs not zero */
 808         igb_pf_host_uninit(eth_dev);
 809
 810         /* disable uio intr before callback unregister */
 811         rte_intr_disable(&(pci_dev->intr_handle));
 812         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 813                 eth_igb_interrupt_handler, (void *)eth_dev);
 814
 815         return 0;
 816 }
 817
 818 /*
 819  * Virtual Function device init
 820  */
 821 static int
 822 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 823 {
 824         struct rte_pci_device *pci_dev;
 825         struct e1000_adapter *adapter =
 826                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 827         struct e1000_hw *hw =
 828                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 829         int diag;
 830
 831         PMD_INIT_FUNC_TRACE();
 832
 833         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 834         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 835         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 836
 837         /* for secondary processes, we don't initialise any further as primary
 838          * has already done this work. Only check we don't need a different
 839          * RX function */
 840         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 841                 if (eth_dev->data->scattered_rx)
 842                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 843                 return 0;
 844         }
 845
 846         pci_dev = eth_dev->pci_dev;
 847
 848         hw->device_id = pci_dev->id.device_id;
 849         hw->vendor_id = pci_dev->id.vendor_id;
 850         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 851         adapter->stopped = 0;
 852
 853         /* Initialize the shared code (base driver) */
 854         diag = e1000_setup_init_funcs(hw, TRUE);
 855         if (diag != 0) {
 856                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 857                         diag);
 858                 return -EIO;
 859         }
 860
 861         /* init_mailbox_params */
 862         hw->mbx.ops.init_params(hw);
 863
 864         /* Disable the interrupts for VF */
 865         igbvf_intr_disable(hw);
 866
 867         diag = hw->mac.ops.reset_hw(hw);
 868
 869         /* Allocate memory for storing MAC addresses */
 870         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
 871                 hw->mac.rar_entry_count, 0);
 872         if (eth_dev->data->mac_addrs == NULL) {
 873                 PMD_INIT_LOG(ERR,
 874                         "Failed to allocate %d bytes needed to store MAC "
 875                         "addresses",
 876                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 877                 return -ENOMEM;
 878         }
 879
 880         /* Copy the permanent MAC address */
 881         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 882                         &eth_dev->data->mac_addrs[0]);
 883
 884         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
 885                      "mac.type=%s",
 886                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 887                      pci_dev->id.device_id, "igb_mac_82576_vf");
 888
 889         return 0;
 890 }
 891
 892 static int
 893 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
 894 {
 895         struct e1000_adapter *adapter =
 896                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 897
 898         PMD_INIT_FUNC_TRACE();
 899
 900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 901                 return -EPERM;
 902
 903         if (adapter->stopped == 0)
 904                 igbvf_dev_close(eth_dev);
 905
 906         eth_dev->dev_ops = NULL;
 907         eth_dev->rx_pkt_burst = NULL;
 908         eth_dev->tx_pkt_burst = NULL;
 909
 910         rte_free(eth_dev->data->mac_addrs);
 911         eth_dev->data->mac_addrs = NULL;
 912
 913         return 0;
 914 }
 915
 916 static struct eth_driver rte_igb_pmd = {
 917         .pci_drv = {
 918                 .name = "rte_igb_pmd",
 919                 .id_table = pci_id_igb_map,
 920                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 921                         RTE_PCI_DRV_DETACHABLE,
 922         },
 923         .eth_dev_init = eth_igb_dev_init,
 924         .eth_dev_uninit = eth_igb_dev_uninit,
 925         .dev_private_size = sizeof(struct e1000_adapter),
 926 };
 927
 928 /*
 929  * virtual function driver struct
 930  */
 931 static struct eth_driver rte_igbvf_pmd = {
 932         .pci_drv = {
 933                 .name = "rte_igbvf_pmd",
 934                 .id_table = pci_id_igbvf_map,
 935                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
 936         },
 937         .eth_dev_init = eth_igbvf_dev_init,
 938         .eth_dev_uninit = eth_igbvf_dev_uninit,
 939         .dev_private_size = sizeof(struct e1000_adapter),
 940 };
 941
 942 static int
 943 rte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 944 {
 945         rte_eth_driver_register(&rte_igb_pmd);
 946         return 0;
 947 }
 948
 949 static void
 950 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 951 {
 952         struct e1000_hw *hw =
 953                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
 955         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
 956         rctl |= E1000_RCTL_VFE;
 957         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
 958 }
 959
 960 /*
 961  * VF Driver initialization routine.
 962  * Invoked one at EAL init time.
 963  * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.
 964  */
 965 static int
 966 rte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
 967 {
 968         PMD_INIT_FUNC_TRACE();
 969
 970         rte_eth_driver_register(&rte_igbvf_pmd);
 971         return (0);
 972 }
 973
 974 static int
 975 igb_check_mq_mode(struct rte_eth_dev *dev)
 976 {
 977         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 978         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 979         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 980         uint16_t nb_tx_q = dev->data->nb_rx_queues;
 981
 982         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
 983             tx_mq_mode == ETH_MQ_TX_DCB ||
 984             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
 985                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 986                 return -EINVAL;
 987         }
 988         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
 989                 /* Check multi-queue mode.
 990                  * To no break software we accept ETH_MQ_RX_NONE as this might
 991                  * be used to turn off VLAN filter.
 992                  */
 993
 994                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
 995                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
 996                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
 997                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
 998                 } else {
 999                         /* Only support one queue on VFs.
1000                          * RSS together with SRIOV is not supported.
1001                          */
1002                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1003                                         " wrong mq_mode rx %d.",
1004                                         rx_mq_mode);
1005                         return -EINVAL;
1006                 }
1007                 /* TX mode is not used here, so mode might be ignored.*/
1008                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1009                         /* SRIOV only works in VMDq enable mode */
1010                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1011                                         " TX mode %d is not supported. "
1012                                         " Driver will behave as %d mode.",
1013                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1014                 }
1015
1016                 /* check valid queue number */
1017                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1018                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1019                                         " only support one queue on VFs.");
1020                         return -EINVAL;
1021                 }
1022         } else {
1023                 /* To no break software that set invalid mode, only display
1024                  * warning if invalid mode is used.
1025                  */
1026                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1027                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1028                     rx_mq_mode != ETH_MQ_RX_RSS) {
1029                         /* RSS together with VMDq not supported*/
1030                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1031                                      rx_mq_mode);
1032                         return -EINVAL;
1033                 }
1034
1035                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1036                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1037                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1038                                         " Due to txmode is meaningless in this"
1039                                         " driver, just ignore.",
1040                                         tx_mq_mode);
1041                 }
1042         }
1043         return 0;
1044 }
1045
1046 static int
1047 eth_igb_configure(struct rte_eth_dev *dev)
1048 {
1049         struct e1000_interrupt *intr =
1050                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1051         int ret;
1052
1053         PMD_INIT_FUNC_TRACE();
1054
1055         /* multipe queue mode checking */
1056         ret  = igb_check_mq_mode(dev);
1057         if (ret != 0) {
1058                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1059                             ret);
1060                 return ret;
1061         }
1062
1063         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1064         PMD_INIT_FUNC_TRACE();
1065
1066         return 0;
1067 }
1068
1069 static int
1070 eth_igb_start(struct rte_eth_dev *dev)
1071 {
1072         struct e1000_hw *hw =
1073                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1074         struct e1000_adapter *adapter =
1075                 E1000_DEV_PRIVATE(dev->data->dev_private);
1076         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1077         int ret, mask;
1078         uint32_t intr_vector = 0;
1079         uint32_t ctrl_ext;
1080
1081         PMD_INIT_FUNC_TRACE();
1082
1083         /* Power up the phy. Needed to make the link go Up */
1084         e1000_power_up_phy(hw);
1085
1086         /*
1087          * Packet Buffer Allocation (PBA)
1088          * Writing PBA sets the receive portion of the buffer
1089          * the remainder is used for the transmit buffer.
1090          */
1091         if (hw->mac.type == e1000_82575) {
1092                 uint32_t pba;
1093
1094                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1095                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1096         }
1097
1098         /* Put the address into the Receive Address Array */
1099         e1000_rar_set(hw, hw->mac.addr, 0);
1100
1101         /* Initialize the hardware */
1102         if (igb_hardware_init(hw)) {
1103                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1104                 return (-EIO);
1105         }
1106         adapter->stopped = 0;
1107
1108         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1109
1110         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1111         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1112         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1113         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1114         E1000_WRITE_FLUSH(hw);
1115
1116         /* configure PF module if SRIOV enabled */
1117         igb_pf_host_configure(dev);
1118
1119         /* check and configure queue intr-vector mapping */
1120         if (dev->data->dev_conf.intr_conf.rxq != 0)
1121                 intr_vector = dev->data->nb_rx_queues;
1122
1123         if (rte_intr_efd_enable(intr_handle, intr_vector))
1124                 return -1;
1125
1126         if (rte_intr_dp_is_en(intr_handle)) {
1127                 intr_handle->intr_vec =
1128                         rte_zmalloc("intr_vec",
1129                                     dev->data->nb_rx_queues * sizeof(int), 0);
1130                 if (intr_handle->intr_vec == NULL) {
1131                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1132                                      " intr_vec\n", dev->data->nb_rx_queues);
1133                         return -ENOMEM;
1134                 }
1135         }
1136
1137         /* confiugre msix for rx interrupt */
1138         eth_igb_configure_msix_intr(dev);
1139
1140         /* Configure for OS presence */
1141         igb_init_manageability(hw);
1142
1143         eth_igb_tx_init(dev);
1144
1145         /* This can fail when allocating mbufs for descriptor rings */
1146         ret = eth_igb_rx_init(dev);
1147         if (ret) {
1148                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1149                 igb_dev_clear_queues(dev);
1150                 return ret;
1151         }
1152
1153         e1000_clear_hw_cntrs_base_generic(hw);
1154
1155         /*
1156          * VLAN Offload Settings
1157          */
1158         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1159                         ETH_VLAN_EXTEND_MASK;
1160         eth_igb_vlan_offload_set(dev, mask);
1161
1162         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1163                 /* Enable VLAN filter since VMDq always use VLAN filter */
1164                 igb_vmdq_vlan_hw_filter_enable(dev);
1165         }
1166
1167         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1168                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1169                 (hw->mac.type == e1000_i211)) {
1170                 /* Configure EITR with the maximum possible value (0xFFFF) */
1171                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1172         }
1173
1174         /* Setup link speed and duplex */
1175         switch (dev->data->dev_conf.link_speed) {
1176         case ETH_LINK_SPEED_AUTONEG:
1177                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1178                         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1179                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1180                         hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
1181                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1182                         hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
1183                 else
1184                         goto error_invalid_config;
1185                 break;
1186         case ETH_LINK_SPEED_10:
1187                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1188                         hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
1189                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1190                         hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
1191                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1192                         hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
1193                 else
1194                         goto error_invalid_config;
1195                 break;
1196         case ETH_LINK_SPEED_100:
1197                 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
1198                         hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
1199                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
1200                         hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
1201                 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
1202                         hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
1203                 else
1204                         goto error_invalid_config;
1205                 break;
1206         case ETH_LINK_SPEED_1000:
1207                 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
1208                                 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
1209                         hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
1210                 else
1211                         goto error_invalid_config;
1212                 break;
1213         case ETH_LINK_SPEED_10000:
1214         default:
1215                 goto error_invalid_config;
1216         }
1217         e1000_setup_link(hw);
1218
1219         /* check if lsc interrupt feature is enabled */
1220         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1221                 if (rte_intr_allow_others(intr_handle)) {
1222                         rte_intr_callback_register(intr_handle,
1223                                                    eth_igb_interrupt_handler,
1224                                                    (void *)dev);
1225                         eth_igb_lsc_interrupt_setup(dev);
1226                 } else
1227                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1228                                      " no intr multiplex\n");
1229         }
1230
1231         /* check if rxq interrupt is enabled */
1232         if (dev->data->dev_conf.intr_conf.rxq != 0)
1233                 eth_igb_rxq_interrupt_setup(dev);
1234
1235         /* enable uio/vfio intr/eventfd mapping */
1236         rte_intr_enable(intr_handle);
1237
1238         /* resume enabled intr since hw reset */
1239         igb_intr_enable(dev);
1240
1241         PMD_INIT_LOG(DEBUG, "<<");
1242
1243         return (0);
1244
1245 error_invalid_config:
1246         PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u",
1247                      dev->data->dev_conf.link_speed,
1248                      dev->data->dev_conf.link_duplex, dev->data->port_id);
1249         igb_dev_clear_queues(dev);
1250         return (-EINVAL);
1251 }
1252
1253 /*********************************************************************
1254  *
1255  *  This routine disables all traffic on the adapter by issuing a
1256  *  global reset on the MAC.
1257  *
1258  **********************************************************************/
1259 static void
1260 eth_igb_stop(struct rte_eth_dev *dev)
1261 {
1262         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         struct e1000_filter_info *filter_info =
1264                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1265         struct rte_eth_link link;
1266         struct e1000_flex_filter *p_flex;
1267         struct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;
1268         struct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;
1269         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1270
1271         igb_intr_disable(hw);
1272
1273         /* disable intr eventfd mapping */
1274         rte_intr_disable(intr_handle);
1275
1276         igb_pf_reset_hw(hw);
1277         E1000_WRITE_REG(hw, E1000_WUC, 0);
1278
1279         /* Set bit for Go Link disconnect */
1280         if (hw->mac.type >= e1000_82580) {
1281                 uint32_t phpm_reg;
1282
1283                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1284                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1285                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1286         }
1287
1288         /* Power down the phy. Needed to make the link go Down */
1289         if (hw->phy.media_type == e1000_media_type_copper)
1290                 e1000_power_down_phy(hw);
1291         else
1292                 e1000_shutdown_fiber_serdes_link(hw);
1293
1294         igb_dev_clear_queues(dev);
1295
1296         /* clear the recorded link status */
1297         memset(&link, 0, sizeof(link));
1298         rte_igb_dev_atomic_write_link_status(dev, &link);
1299
1300         /* Remove all flex filters of the device */
1301         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1302                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1303                 rte_free(p_flex);
1304         }
1305         filter_info->flex_mask = 0;
1306
1307         /* Remove all ntuple filters of the device */
1308         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1309              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1310                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1311                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1312                              p_5tuple, entries);
1313                 rte_free(p_5tuple);
1314         }
1315         filter_info->fivetuple_mask = 0;
1316         for (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);
1317              p_2tuple != NULL; p_2tuple = p_2tuple_next) {
1318                 p_2tuple_next = TAILQ_NEXT(p_2tuple, entries);
1319                 TAILQ_REMOVE(&filter_info->twotuple_list,
1320                              p_2tuple, entries);
1321                 rte_free(p_2tuple);
1322         }
1323         filter_info->twotuple_mask = 0;
1324
1325         /* Clean datapath event and queue/vec mapping */
1326         rte_intr_efd_disable(intr_handle);
1327         if (intr_handle->intr_vec != NULL) {
1328                 rte_free(intr_handle->intr_vec);
1329                 intr_handle->intr_vec = NULL;
1330         }
1331 }
1332
1333 static void
1334 eth_igb_close(struct rte_eth_dev *dev)
1335 {
1336         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         struct e1000_adapter *adapter =
1338                 E1000_DEV_PRIVATE(dev->data->dev_private);
1339         struct rte_eth_link link;
1340         struct rte_pci_device *pci_dev;
1341
1342         eth_igb_stop(dev);
1343         adapter->stopped = 1;
1344
1345         e1000_phy_hw_reset(hw);
1346         igb_release_manageability(hw);
1347         igb_hw_control_release(hw);
1348
1349         /* Clear bit for Go Link disconnect */
1350         if (hw->mac.type >= e1000_82580) {
1351                 uint32_t phpm_reg;
1352
1353                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1354                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1355                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1356         }
1357
1358         igb_dev_free_queues(dev);
1359
1360         pci_dev = dev->pci_dev;
1361         if (pci_dev->intr_handle.intr_vec) {
1362                 rte_free(pci_dev->intr_handle.intr_vec);
1363                 pci_dev->intr_handle.intr_vec = NULL;
1364         }
1365
1366         memset(&link, 0, sizeof(link));
1367         rte_igb_dev_atomic_write_link_status(dev, &link);
1368 }
1369
1370 static int
1371 igb_get_rx_buffer_size(struct e1000_hw *hw)
1372 {
1373         uint32_t rx_buf_size;
1374         if (hw->mac.type == e1000_82576) {
1375                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1376         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1377                 /* PBS needs to be translated according to a lookup table */
1378                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1379                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1380                 rx_buf_size = (rx_buf_size << 10);
1381         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1382                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1383         } else {
1384                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1385         }
1386
1387         return rx_buf_size;
1388 }
1389
1390 /*********************************************************************
1391  *
1392  *  Initialize the hardware
1393  *
1394  **********************************************************************/
1395 static int
1396 igb_hardware_init(struct e1000_hw *hw)
1397 {
1398         uint32_t rx_buf_size;
1399         int diag;
1400
1401         /* Let the firmware know the OS is in control */
1402         igb_hw_control_acquire(hw);
1403
1404         /*
1405          * These parameters control the automatic generation (Tx) and
1406          * response (Rx) to Ethernet PAUSE frames.
1407          * - High water mark should allow for at least two standard size (1518)
1408          *   frames to be received after sending an XOFF.
1409          * - Low water mark works best when it is very near the high water mark.
1410          *   This allows the receiver to restart by sending XON when it has
1411          *   drained a bit. Here we use an arbitrary value of 1500 which will
1412          *   restart after one full frame is pulled from the buffer. There
1413          *   could be several smaller frames in the buffer and if so they will
1414          *   not trigger the XON until their total number reduces the buffer
1415          *   by 1500.
1416          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1417          */
1418         rx_buf_size = igb_get_rx_buffer_size(hw);
1419
1420         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1421         hw->fc.low_water = hw->fc.high_water - 1500;
1422         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1423         hw->fc.send_xon = 1;
1424
1425         /* Set Flow control, use the tunable location if sane */
1426         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1427                 hw->fc.requested_mode = igb_fc_setting;
1428         else
1429                 hw->fc.requested_mode = e1000_fc_none;
1430
1431         /* Issue a global reset */
1432         igb_pf_reset_hw(hw);
1433         E1000_WRITE_REG(hw, E1000_WUC, 0);
1434
1435         diag = e1000_init_hw(hw);
1436         if (diag < 0)
1437                 return (diag);
1438
1439         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1440         e1000_get_phy_info(hw);
1441         e1000_check_for_link(hw);
1442
1443         return (0);
1444 }
1445
1446 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1447 static void
1448 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1449 {
1450         int pause_frames;
1451
1452         if(hw->phy.media_type == e1000_media_type_copper ||
1453             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1454                 stats->symerrs +=
1455                     E1000_READ_REG(hw,E1000_SYMERRS);
1456                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1457         }
1458
1459         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1460         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1461         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1462         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1463
1464         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1465         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1466         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1467         stats->dc += E1000_READ_REG(hw, E1000_DC);
1468         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1469         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1470         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1471         /*
1472         ** For watchdog management we need to know if we have been
1473         ** paused during the last interval, so capture that here.
1474         */
1475         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1476         stats->xoffrxc += pause_frames;
1477         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1478         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1479         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1480         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1481         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1482         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1483         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1484         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1485         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1486         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1487         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1488         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1489
1490         /* For the 64-bit byte counters the low dword must be read first. */
1491         /* Both registers clear on the read of the high dword */
1492
1493         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1494         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1495         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1496         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1497
1498         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1499         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1500         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1501         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1502         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1503
1504         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1505         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1506         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1507         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1508
1509         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1510         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1511         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1512         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1513         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1514         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1515         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1516         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1517         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1518         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1519
1520         /* Interrupt Counts */
1521
1522         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1523         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1524         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1525         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1526         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1527         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1528         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1529         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1530         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1531
1532         /* Host to Card Statistics */
1533
1534         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1535         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1536         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1537         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1538         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1539         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1540         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1541         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1542         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1543         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1544         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1545         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1546         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1547         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1548
1549         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1550         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1551         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1552         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1553         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1554         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1555 }
1556
1557 static void
1558 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1559 {
1560         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561         struct e1000_hw_stats *stats =
1562                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1563
1564         igb_read_stats_registers(hw, stats);
1565
1566         if (rte_stats == NULL)
1567                 return;
1568
1569         /* Rx Errors */
1570         rte_stats->ibadcrc = stats->crcerrs;
1571         rte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;
1572         rte_stats->imissed = stats->mpc;
1573         rte_stats->ierrors = rte_stats->ibadcrc +
1574                              rte_stats->ibadlen +
1575                              rte_stats->imissed +
1576                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1577
1578         /* Tx Errors */
1579         rte_stats->oerrors = stats->ecol + stats->latecol;
1580
1581         /* XON/XOFF pause frames */
1582         rte_stats->tx_pause_xon  = stats->xontxc;
1583         rte_stats->rx_pause_xon  = stats->xonrxc;
1584         rte_stats->tx_pause_xoff = stats->xofftxc;
1585         rte_stats->rx_pause_xoff = stats->xoffrxc;
1586
1587         rte_stats->ipackets = stats->gprc;
1588         rte_stats->opackets = stats->gptc;
1589         rte_stats->ibytes   = stats->gorc;
1590         rte_stats->obytes   = stats->gotc;
1591 }
1592
1593 static void
1594 eth_igb_stats_reset(struct rte_eth_dev *dev)
1595 {
1596         struct e1000_hw_stats *hw_stats =
1597                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1598
1599         /* HW registers are cleared on read */
1600         eth_igb_stats_get(dev, NULL);
1601
1602         /* Reset software totals */
1603         memset(hw_stats, 0, sizeof(*hw_stats));
1604 }
1605
1606 static void
1607 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1608 {
1609         struct e1000_hw_stats *stats =
1610                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1611
1612         /* HW registers are cleared on read */
1613         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1614
1615         /* Reset software totals */
1616         memset(stats, 0, sizeof(*stats));
1617 }
1618
1619 static int
1620 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1621                    unsigned n)
1622 {
1623         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624         struct e1000_hw_stats *hw_stats =
1625                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1626         unsigned i;
1627
1628         if (n < IGB_NB_XSTATS)
1629                 return IGB_NB_XSTATS;
1630
1631         igb_read_stats_registers(hw, hw_stats);
1632
1633         /* If this is a reset xstats is NULL, and we have cleared the
1634          * registers by reading them.
1635          */
1636         if (!xstats)
1637                 return 0;
1638
1639         /* Extended stats */
1640         for (i = 0; i < IGB_NB_XSTATS; i++) {
1641                 snprintf(xstats[i].name, sizeof(xstats[i].name),
1642                          "%s", rte_igb_stats_strings[i].name);
1643                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1644                         rte_igb_stats_strings[i].offset);
1645         }
1646
1647         return IGB_NB_XSTATS;
1648 }
1649
1650 static void
1651 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1652 {
1653         /* Good Rx packets, include VF loopback */
1654         UPDATE_VF_STAT(E1000_VFGPRC,
1655             hw_stats->last_gprc, hw_stats->gprc);
1656
1657         /* Good Rx octets, include VF loopback */
1658         UPDATE_VF_STAT(E1000_VFGORC,
1659             hw_stats->last_gorc, hw_stats->gorc);
1660
1661         /* Good Tx packets, include VF loopback */
1662         UPDATE_VF_STAT(E1000_VFGPTC,
1663             hw_stats->last_gptc, hw_stats->gptc);
1664
1665         /* Good Tx octets, include VF loopback */
1666         UPDATE_VF_STAT(E1000_VFGOTC,
1667             hw_stats->last_gotc, hw_stats->gotc);
1668
1669         /* Rx Multicst packets */
1670         UPDATE_VF_STAT(E1000_VFMPRC,
1671             hw_stats->last_mprc, hw_stats->mprc);
1672
1673         /* Good Rx loopback packets */
1674         UPDATE_VF_STAT(E1000_VFGPRLBC,
1675             hw_stats->last_gprlbc, hw_stats->gprlbc);
1676
1677         /* Good Rx loopback octets */
1678         UPDATE_VF_STAT(E1000_VFGORLBC,
1679             hw_stats->last_gorlbc, hw_stats->gorlbc);
1680
1681         /* Good Tx loopback packets */
1682         UPDATE_VF_STAT(E1000_VFGPTLBC,
1683             hw_stats->last_gptlbc, hw_stats->gptlbc);
1684
1685         /* Good Tx loopback octets */
1686         UPDATE_VF_STAT(E1000_VFGOTLBC,
1687             hw_stats->last_gotlbc, hw_stats->gotlbc);
1688 }
1689
1690 static int
1691 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1692                      unsigned n)
1693 {
1694         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1696                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1697         unsigned i;
1698
1699         if (n < IGBVF_NB_XSTATS)
1700                 return IGBVF_NB_XSTATS;
1701
1702         igbvf_read_stats_registers(hw, hw_stats);
1703
1704         if (!xstats)
1705                 return 0;
1706
1707         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
1708                 snprintf(xstats[i].name, sizeof(xstats[i].name), "%s",
1709                          rte_igbvf_stats_strings[i].name);
1710                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1711                         rte_igbvf_stats_strings[i].offset);
1712         }
1713
1714         return IGBVF_NB_XSTATS;
1715 }
1716
1717 static void
1718 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1719 {
1720         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
1722                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1723
1724         igbvf_read_stats_registers(hw, hw_stats);
1725
1726         if (rte_stats == NULL)
1727                 return;
1728
1729         rte_stats->ipackets = hw_stats->gprc;
1730         rte_stats->ibytes = hw_stats->gorc;
1731         rte_stats->opackets = hw_stats->gptc;
1732         rte_stats->obytes = hw_stats->gotc;
1733         rte_stats->imcasts = hw_stats->mprc;
1734         rte_stats->ilbpackets = hw_stats->gprlbc;
1735         rte_stats->ilbbytes = hw_stats->gorlbc;
1736         rte_stats->olbpackets = hw_stats->gptlbc;
1737         rte_stats->olbbytes = hw_stats->gotlbc;
1738 }
1739
1740 static void
1741 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
1742 {
1743         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
1744                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1745
1746         /* Sync HW register to the last stats */
1747         eth_igbvf_stats_get(dev, NULL);
1748
1749         /* reset HW current stats*/
1750         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
1751                offsetof(struct e1000_vf_stats, gprc));
1752 }
1753
1754 static void
1755 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1756 {
1757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1758
1759         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1760         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1761         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1762         dev_info->rx_offload_capa =
1763                 DEV_RX_OFFLOAD_VLAN_STRIP |
1764                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1765                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1766                 DEV_RX_OFFLOAD_TCP_CKSUM;
1767         dev_info->tx_offload_capa =
1768                 DEV_TX_OFFLOAD_VLAN_INSERT |
1769                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1770                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1771                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1772                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1773                 DEV_TX_OFFLOAD_TCP_TSO;
1774
1775         switch (hw->mac.type) {
1776         case e1000_82575:
1777                 dev_info->max_rx_queues = 4;
1778                 dev_info->max_tx_queues = 4;
1779                 dev_info->max_vmdq_pools = 0;
1780                 break;
1781
1782         case e1000_82576:
1783                 dev_info->max_rx_queues = 16;
1784                 dev_info->max_tx_queues = 16;
1785                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1786                 dev_info->vmdq_queue_num = 16;
1787                 break;
1788
1789         case e1000_82580:
1790                 dev_info->max_rx_queues = 8;
1791                 dev_info->max_tx_queues = 8;
1792                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1793                 dev_info->vmdq_queue_num = 8;
1794                 break;
1795
1796         case e1000_i350:
1797                 dev_info->max_rx_queues = 8;
1798                 dev_info->max_tx_queues = 8;
1799                 dev_info->max_vmdq_pools = ETH_8_POOLS;
1800                 dev_info->vmdq_queue_num = 8;
1801                 break;
1802
1803         case e1000_i354:
1804                 dev_info->max_rx_queues = 8;
1805                 dev_info->max_tx_queues = 8;
1806                 break;
1807
1808         case e1000_i210:
1809                 dev_info->max_rx_queues = 4;
1810                 dev_info->max_tx_queues = 4;
1811                 dev_info->max_vmdq_pools = 0;
1812                 break;
1813
1814         case e1000_i211:
1815                 dev_info->max_rx_queues = 2;
1816                 dev_info->max_tx_queues = 2;
1817                 dev_info->max_vmdq_pools = 0;
1818                 break;
1819
1820         default:
1821                 /* Should not happen */
1822                 break;
1823         }
1824         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
1825         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1826         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
1827
1828         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1829                 .rx_thresh = {
1830                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1831                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1832                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1833                 },
1834                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1835                 .rx_drop_en = 0,
1836         };
1837
1838         dev_info->default_txconf = (struct rte_eth_txconf) {
1839                 .tx_thresh = {
1840                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1841                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1842                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1843                 },
1844                 .txq_flags = 0,
1845         };
1846
1847         dev_info->rx_desc_lim = rx_desc_lim;
1848         dev_info->tx_desc_lim = tx_desc_lim;
1849 }
1850
1851 static void
1852 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1853 {
1854         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855
1856         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1857         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
1858         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1859         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
1860                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1861                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1862                                 DEV_RX_OFFLOAD_TCP_CKSUM;
1863         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
1864                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1865                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1866                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1867                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
1868                                 DEV_TX_OFFLOAD_TCP_TSO;
1869         switch (hw->mac.type) {
1870         case e1000_vfadapt:
1871                 dev_info->max_rx_queues = 2;
1872                 dev_info->max_tx_queues = 2;
1873                 break;
1874         case e1000_vfadapt_i350:
1875                 dev_info->max_rx_queues = 1;
1876                 dev_info->max_tx_queues = 1;
1877                 break;
1878         default:
1879                 /* Should not happen */
1880                 break;
1881         }
1882
1883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1884                 .rx_thresh = {
1885                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
1886                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
1887                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
1888                 },
1889                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
1890                 .rx_drop_en = 0,
1891         };
1892
1893         dev_info->default_txconf = (struct rte_eth_txconf) {
1894                 .tx_thresh = {
1895                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
1896                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
1897                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
1898                 },
1899                 .txq_flags = 0,
1900         };
1901
1902         dev_info->rx_desc_lim = rx_desc_lim;
1903         dev_info->tx_desc_lim = tx_desc_lim;
1904 }
1905
1906 /* return 0 means link status changed, -1 means not changed */
1907 static int
1908 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1909 {
1910         struct e1000_hw *hw =
1911                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912         struct rte_eth_link link, old;
1913         int link_check, count;
1914
1915         link_check = 0;
1916         hw->mac.get_link_status = 1;
1917
1918         /* possible wait-to-complete in up to 9 seconds */
1919         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
1920                 /* Read the real link status */
1921                 switch (hw->phy.media_type) {
1922                 case e1000_media_type_copper:
1923                         /* Do the work to read phy */
1924                         e1000_check_for_link(hw);
1925                         link_check = !hw->mac.get_link_status;
1926                         break;
1927
1928                 case e1000_media_type_fiber:
1929                         e1000_check_for_link(hw);
1930                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
1931                                       E1000_STATUS_LU);
1932                         break;
1933
1934                 case e1000_media_type_internal_serdes:
1935                         e1000_check_for_link(hw);
1936                         link_check = hw->mac.serdes_has_link;
1937                         break;
1938
1939                 /* VF device is type_unknown */
1940                 case e1000_media_type_unknown:
1941                         eth_igbvf_link_update(hw);
1942                         link_check = !hw->mac.get_link_status;
1943                         break;
1944
1945                 default:
1946                         break;
1947                 }
1948                 if (link_check || wait_to_complete == 0)
1949                         break;
1950                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
1951         }
1952         memset(&link, 0, sizeof(link));
1953         rte_igb_dev_atomic_read_link_status(dev, &link);
1954         old = link;
1955
1956         /* Now we check if a transition has happened */
1957         if (link_check) {
1958                 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
1959                                           &link.link_duplex);
1960                 link.link_status = 1;
1961         } else if (!link_check) {
1962                 link.link_speed = 0;
1963                 link.link_duplex = 0;
1964                 link.link_status = 0;
1965         }
1966         rte_igb_dev_atomic_write_link_status(dev, &link);
1967
1968         /* not changed */
1969         if (old.link_status == link.link_status)
1970                 return -1;
1971
1972         /* changed */
1973         return 0;
1974 }
1975
1976 /*
1977  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
1978  * For ASF and Pass Through versions of f/w this means
1979  * that the driver is loaded.
1980  */
1981 static void
1982 igb_hw_control_acquire(struct e1000_hw *hw)
1983 {
1984         uint32_t ctrl_ext;
1985
1986         /* Let firmware know the driver has taken over */
1987         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1988         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1989 }
1990
1991 /*
1992  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
1993  * For ASF and Pass Through versions of f/w this means that the
1994  * driver is no longer loaded.
1995  */
1996 static void
1997 igb_hw_control_release(struct e1000_hw *hw)
1998 {
1999         uint32_t ctrl_ext;
2000
2001         /* Let firmware taken over control of h/w */
2002         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2003         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2004                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2005 }
2006
2007 /*
2008  * Bit of a misnomer, what this really means is
2009  * to enable OS management of the system... aka
2010  * to disable special hardware management features.
2011  */
2012 static void
2013 igb_init_manageability(struct e1000_hw *hw)
2014 {
2015         if (e1000_enable_mng_pass_thru(hw)) {
2016                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2017                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2018
2019                 /* disable hardware interception of ARP */
2020                 manc &= ~(E1000_MANC_ARP_EN);
2021
2022                 /* enable receiving management packets to the host */
2023                 manc |= E1000_MANC_EN_MNG2HOST;
2024                 manc2h |= 1 << 5;  /* Mng Port 623 */
2025                 manc2h |= 1 << 6;  /* Mng Port 664 */
2026                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2027                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2028         }
2029 }
2030
2031 static void
2032 igb_release_manageability(struct e1000_hw *hw)
2033 {
2034         if (e1000_enable_mng_pass_thru(hw)) {
2035                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2036
2037                 manc |= E1000_MANC_ARP_EN;
2038                 manc &= ~E1000_MANC_EN_MNG2HOST;
2039
2040                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2041         }
2042 }
2043
2044 static void
2045 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2046 {
2047         struct e1000_hw *hw =
2048                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2049         uint32_t rctl;
2050
2051         rctl = E1000_READ_REG(hw, E1000_RCTL);
2052         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2053         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2054 }
2055
2056 static void
2057 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2058 {
2059         struct e1000_hw *hw =
2060                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         uint32_t rctl;
2062
2063         rctl = E1000_READ_REG(hw, E1000_RCTL);
2064         rctl &= (~E1000_RCTL_UPE);
2065         if (dev->data->all_multicast == 1)
2066                 rctl |= E1000_RCTL_MPE;
2067         else
2068                 rctl &= (~E1000_RCTL_MPE);
2069         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2070 }
2071
2072 static void
2073 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2074 {
2075         struct e1000_hw *hw =
2076                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         uint32_t rctl;
2078
2079         rctl = E1000_READ_REG(hw, E1000_RCTL);
2080         rctl |= E1000_RCTL_MPE;
2081         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2082 }
2083
2084 static void
2085 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2086 {
2087         struct e1000_hw *hw =
2088                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2089         uint32_t rctl;
2090
2091         if (dev->data->promiscuous == 1)
2092                 return; /* must remain in all_multicast mode */
2093         rctl = E1000_READ_REG(hw, E1000_RCTL);
2094         rctl &= (~E1000_RCTL_MPE);
2095         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2096 }
2097
2098 static int
2099 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2100 {
2101         struct e1000_hw *hw =
2102                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct e1000_vfta * shadow_vfta =
2104                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2105         uint32_t vfta;
2106         uint32_t vid_idx;
2107         uint32_t vid_bit;
2108
2109         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2110                               E1000_VFTA_ENTRY_MASK);
2111         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2112         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2113         if (on)
2114                 vfta |= vid_bit;
2115         else
2116                 vfta &= ~vid_bit;
2117         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2118
2119         /* update local VFTA copy */
2120         shadow_vfta->vfta[vid_idx] = vfta;
2121
2122         return 0;
2123 }
2124
2125 static void
2126 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
2127 {
2128         struct e1000_hw *hw =
2129                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2130         uint32_t reg = ETHER_TYPE_VLAN ;
2131
2132         reg |= (tpid << 16);
2133         E1000_WRITE_REG(hw, E1000_VET, reg);
2134 }
2135
2136 static void
2137 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2138 {
2139         struct e1000_hw *hw =
2140                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         uint32_t reg;
2142
2143         /* Filter Table Disable */
2144         reg = E1000_READ_REG(hw, E1000_RCTL);
2145         reg &= ~E1000_RCTL_CFIEN;
2146         reg &= ~E1000_RCTL_VFE;
2147         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2148 }
2149
2150 static void
2151 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2152 {
2153         struct e1000_hw *hw =
2154                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct e1000_vfta * shadow_vfta =
2156                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2157         uint32_t reg;
2158         int i;
2159
2160         /* Filter Table Enable, CFI not used for packet acceptance */
2161         reg = E1000_READ_REG(hw, E1000_RCTL);
2162         reg &= ~E1000_RCTL_CFIEN;
2163         reg |= E1000_RCTL_VFE;
2164         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2165
2166         /* restore VFTA table */
2167         for (i = 0; i < IGB_VFTA_SIZE; i++)
2168                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2169 }
2170
2171 static void
2172 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2173 {
2174         struct e1000_hw *hw =
2175                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176         uint32_t reg;
2177
2178         /* VLAN Mode Disable */
2179         reg = E1000_READ_REG(hw, E1000_CTRL);
2180         reg &= ~E1000_CTRL_VME;
2181         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2182 }
2183
2184 static void
2185 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2186 {
2187         struct e1000_hw *hw =
2188                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189         uint32_t reg;
2190
2191         /* VLAN Mode Enable */
2192         reg = E1000_READ_REG(hw, E1000_CTRL);
2193         reg |= E1000_CTRL_VME;
2194         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2195 }
2196
2197 static void
2198 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2199 {
2200         struct e1000_hw *hw =
2201                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint32_t reg;
2203
2204         /* CTRL_EXT: Extended VLAN */
2205         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2206         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2207         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2208
2209         /* Update maximum packet length */
2210         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2211                 E1000_WRITE_REG(hw, E1000_RLPML,
2212                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2213                                                 VLAN_TAG_SIZE);
2214 }
2215
2216 static void
2217 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2218 {
2219         struct e1000_hw *hw =
2220                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221         uint32_t reg;
2222
2223         /* CTRL_EXT: Extended VLAN */
2224         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2225         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2226         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2227
2228         /* Update maximum packet length */
2229         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2230                 E1000_WRITE_REG(hw, E1000_RLPML,
2231                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2232                                                 2 * VLAN_TAG_SIZE);
2233 }
2234
2235 static void
2236 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2237 {
2238         if(mask & ETH_VLAN_STRIP_MASK){
2239                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2240                         igb_vlan_hw_strip_enable(dev);
2241                 else
2242                         igb_vlan_hw_strip_disable(dev);
2243         }
2244
2245         if(mask & ETH_VLAN_FILTER_MASK){
2246                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2247                         igb_vlan_hw_filter_enable(dev);
2248                 else
2249                         igb_vlan_hw_filter_disable(dev);
2250         }
2251
2252         if(mask & ETH_VLAN_EXTEND_MASK){
2253                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2254                         igb_vlan_hw_extend_enable(dev);
2255                 else
2256                         igb_vlan_hw_extend_disable(dev);
2257         }
2258 }
2259
2260
2261 /**
2262  * It enables the interrupt mask and then enable the interrupt.
2263  *
2264  * @param dev
2265  *  Pointer to struct rte_eth_dev.
2266  *
2267  * @return
2268  *  - On success, zero.
2269  *  - On failure, a negative value.
2270  */
2271 static int
2272 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2273 {
2274         struct e1000_interrupt *intr =
2275                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2276
2277         intr->mask |= E1000_ICR_LSC;
2278
2279         return 0;
2280 }
2281
2282 /* It clears the interrupt causes and enables the interrupt.
2283  * It will be called once only during nic initialized.
2284  *
2285  * @param dev
2286  *  Pointer to struct rte_eth_dev.
2287  *
2288  * @return
2289  *  - On success, zero.
2290  *  - On failure, a negative value.
2291  */
2292 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2293 {
2294         uint32_t mask, regval;
2295         struct e1000_hw *hw =
2296                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297         struct rte_eth_dev_info dev_info;
2298
2299         memset(&dev_info, 0, sizeof(dev_info));
2300         eth_igb_infos_get(dev, &dev_info);
2301
2302         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2303         regval = E1000_READ_REG(hw, E1000_EIMS);
2304         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2305
2306         return 0;
2307 }
2308
2309 /*
2310  * It reads ICR and gets interrupt causes, check it and set a bit flag
2311  * to update link status.
2312  *
2313  * @param dev
2314  *  Pointer to struct rte_eth_dev.
2315  *
2316  * @return
2317  *  - On success, zero.
2318  *  - On failure, a negative value.
2319  */
2320 static int
2321 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2322 {
2323         uint32_t icr;
2324         struct e1000_hw *hw =
2325                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         struct e1000_interrupt *intr =
2327                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2328
2329         igb_intr_disable(hw);
2330
2331         /* read-on-clear nic registers here */
2332         icr = E1000_READ_REG(hw, E1000_ICR);
2333
2334         intr->flags = 0;
2335         if (icr & E1000_ICR_LSC) {
2336                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2337         }
2338
2339         if (icr & E1000_ICR_VMMB)
2340                 intr->flags |= E1000_FLAG_MAILBOX;
2341
2342         return 0;
2343 }
2344
2345 /*
2346  * It executes link_update after knowing an interrupt is prsent.
2347  *
2348  * @param dev
2349  *  Pointer to struct rte_eth_dev.
2350  *
2351  * @return
2352  *  - On success, zero.
2353  *  - On failure, a negative value.
2354  */
2355 static int
2356 eth_igb_interrupt_action(struct rte_eth_dev *dev)
2357 {
2358         struct e1000_hw *hw =
2359                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         struct e1000_interrupt *intr =
2361                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2362         uint32_t tctl, rctl;
2363         struct rte_eth_link link;
2364         int ret;
2365
2366         if (intr->flags & E1000_FLAG_MAILBOX) {
2367                 igb_pf_mbx_process(dev);
2368                 intr->flags &= ~E1000_FLAG_MAILBOX;
2369         }
2370
2371         igb_intr_enable(dev);
2372         rte_intr_enable(&(dev->pci_dev->intr_handle));
2373
2374         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2375                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2376
2377                 /* set get_link_status to check register later */
2378                 hw->mac.get_link_status = 1;
2379                 ret = eth_igb_link_update(dev, 0);
2380
2381                 /* check if link has changed */
2382                 if (ret < 0)
2383                         return 0;
2384
2385                 memset(&link, 0, sizeof(link));
2386                 rte_igb_dev_atomic_read_link_status(dev, &link);
2387                 if (link.link_status) {
2388                         PMD_INIT_LOG(INFO,
2389                                      " Port %d: Link Up - speed %u Mbps - %s",
2390                                      dev->data->port_id,
2391                                      (unsigned)link.link_speed,
2392                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2393                                      "full-duplex" : "half-duplex");
2394                 } else {
2395                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2396                                      dev->data->port_id);
2397                 }
2398
2399                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2400                              dev->pci_dev->addr.domain,
2401                              dev->pci_dev->addr.bus,
2402                              dev->pci_dev->addr.devid,
2403                              dev->pci_dev->addr.function);
2404                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2405                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2406                 if (link.link_status) {
2407                         /* enable Tx/Rx */
2408                         tctl |= E1000_TCTL_EN;
2409                         rctl |= E1000_RCTL_EN;
2410                 } else {
2411                         /* disable Tx/Rx */
2412                         tctl &= ~E1000_TCTL_EN;
2413                         rctl &= ~E1000_RCTL_EN;
2414                 }
2415                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2416                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2417                 E1000_WRITE_FLUSH(hw);
2418                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2419         }
2420
2421         return 0;
2422 }
2423
2424 /**
2425  * Interrupt handler which shall be registered at first.
2426  *
2427  * @param handle
2428  *  Pointer to interrupt handle.
2429  * @param param
2430  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2431  *
2432  * @return
2433  *  void
2434  */
2435 static void
2436 eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2437                                                         void *param)
2438 {
2439         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2440
2441         eth_igb_interrupt_get_status(dev);
2442         eth_igb_interrupt_action(dev);
2443 }
2444
2445 static int
2446 eth_igb_led_on(struct rte_eth_dev *dev)
2447 {
2448         struct e1000_hw *hw;
2449
2450         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451         return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2452 }
2453
2454 static int
2455 eth_igb_led_off(struct rte_eth_dev *dev)
2456 {
2457         struct e1000_hw *hw;
2458
2459         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
2461 }
2462
2463 static int
2464 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2465 {
2466         struct e1000_hw *hw;
2467         uint32_t ctrl;
2468         int tx_pause;
2469         int rx_pause;
2470
2471         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2472         fc_conf->pause_time = hw->fc.pause_time;
2473         fc_conf->high_water = hw->fc.high_water;
2474         fc_conf->low_water = hw->fc.low_water;
2475         fc_conf->send_xon = hw->fc.send_xon;
2476         fc_conf->autoneg = hw->mac.autoneg;
2477
2478         /*
2479          * Return rx_pause and tx_pause status according to actual setting of
2480          * the TFCE and RFCE bits in the CTRL register.
2481          */
2482         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2483         if (ctrl & E1000_CTRL_TFCE)
2484                 tx_pause = 1;
2485         else
2486                 tx_pause = 0;
2487
2488         if (ctrl & E1000_CTRL_RFCE)
2489                 rx_pause = 1;
2490         else
2491                 rx_pause = 0;
2492
2493         if (rx_pause && tx_pause)
2494                 fc_conf->mode = RTE_FC_FULL;
2495         else if (rx_pause)
2496                 fc_conf->mode = RTE_FC_RX_PAUSE;
2497         else if (tx_pause)
2498                 fc_conf->mode = RTE_FC_TX_PAUSE;
2499         else
2500                 fc_conf->mode = RTE_FC_NONE;
2501
2502         return 0;
2503 }
2504
2505 static int
2506 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2507 {
2508         struct e1000_hw *hw;
2509         int err;
2510         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
2511                 e1000_fc_none,
2512                 e1000_fc_rx_pause,
2513                 e1000_fc_tx_pause,
2514                 e1000_fc_full
2515         };
2516         uint32_t rx_buf_size;
2517         uint32_t max_high_water;
2518         uint32_t rctl;
2519
2520         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2521         if (fc_conf->autoneg != hw->mac.autoneg)
2522                 return -ENOTSUP;
2523         rx_buf_size = igb_get_rx_buffer_size(hw);
2524         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2525
2526         /* At least reserve one Ethernet frame for watermark */
2527         max_high_water = rx_buf_size - ETHER_MAX_LEN;
2528         if ((fc_conf->high_water > max_high_water) ||
2529             (fc_conf->high_water < fc_conf->low_water)) {
2530                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
2531                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
2532                 return (-EINVAL);
2533         }
2534
2535         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
2536         hw->fc.pause_time     = fc_conf->pause_time;
2537         hw->fc.high_water     = fc_conf->high_water;
2538         hw->fc.low_water      = fc_conf->low_water;
2539         hw->fc.send_xon       = fc_conf->send_xon;
2540
2541         err = e1000_setup_link_generic(hw);
2542         if (err == E1000_SUCCESS) {
2543
2544                 /* check if we want to forward MAC frames - driver doesn't have native
2545                  * capability to do that, so we'll write the registers ourselves */
2546
2547                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2548
2549                 /* set or clear MFLCN.PMCF bit depending on configuration */
2550                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2551                         rctl |= E1000_RCTL_PMCF;
2552                 else
2553                         rctl &= ~E1000_RCTL_PMCF;
2554
2555                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2556                 E1000_WRITE_FLUSH(hw);
2557
2558                 return 0;
2559         }
2560
2561         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
2562         return (-EIO);
2563 }
2564
2565 #define E1000_RAH_POOLSEL_SHIFT      (18)
2566 static void
2567 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2568                 uint32_t index, __rte_unused uint32_t pool)
2569 {
2570         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2571         uint32_t rah;
2572
2573         e1000_rar_set(hw, mac_addr->addr_bytes, index);
2574         rah = E1000_READ_REG(hw, E1000_RAH(index));
2575         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
2576         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
2577 }
2578
2579 static void
2580 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
2581 {
2582         uint8_t addr[ETHER_ADDR_LEN];
2583         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2584
2585         memset(addr, 0, sizeof(addr));
2586
2587         e1000_rar_set(hw, addr, index);
2588 }
2589
2590 static void
2591 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
2592                                 struct ether_addr *addr)
2593 {
2594         eth_igb_rar_clear(dev, 0);
2595
2596         eth_igb_rar_set(dev, (void *)addr, 0, 0);
2597 }
2598 /*
2599  * Virtual Function operations
2600  */
2601 static void
2602 igbvf_intr_disable(struct e1000_hw *hw)
2603 {
2604         PMD_INIT_FUNC_TRACE();
2605
2606         /* Clear interrupt mask to stop from interrupts being generated */
2607         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
2608
2609         E1000_WRITE_FLUSH(hw);
2610 }
2611
2612 static void
2613 igbvf_stop_adapter(struct rte_eth_dev *dev)
2614 {
2615         u32 reg_val;
2616         u16 i;
2617         struct rte_eth_dev_info dev_info;
2618         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2619
2620         memset(&dev_info, 0, sizeof(dev_info));
2621         eth_igbvf_infos_get(dev, &dev_info);
2622
2623         /* Clear interrupt mask to stop from interrupts being generated */
2624         igbvf_intr_disable(hw);
2625
2626         /* Clear any pending interrupts, flush previous writes */
2627         E1000_READ_REG(hw, E1000_EICR);
2628
2629         /* Disable the transmit unit.  Each queue must be disabled. */
2630         for (i = 0; i < dev_info.max_tx_queues; i++)
2631                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
2632
2633         /* Disable the receive unit by stopping each queue */
2634         for (i = 0; i < dev_info.max_rx_queues; i++) {
2635                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
2636                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
2637                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
2638                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
2639                         ;
2640         }
2641
2642         /* flush all queues disables */
2643         E1000_WRITE_FLUSH(hw);
2644         msec_delay(2);
2645 }
2646
2647 static int eth_igbvf_link_update(struct e1000_hw *hw)
2648 {
2649         struct e1000_mbx_info *mbx = &hw->mbx;
2650         struct e1000_mac_info *mac = &hw->mac;
2651         int ret_val = E1000_SUCCESS;
2652
2653         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
2654
2655         /*
2656          * We only want to run this if there has been a rst asserted.
2657          * in this case that could mean a link change, device reset,
2658          * or a virtual function reset
2659          */
2660
2661         /* If we were hit with a reset or timeout drop the link */
2662         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
2663                 mac->get_link_status = TRUE;
2664
2665         if (!mac->get_link_status)
2666                 goto out;
2667
2668         /* if link status is down no point in checking to see if pf is up */
2669         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
2670                 goto out;
2671
2672         /* if we passed all the tests above then the link is up and we no
2673          * longer need to check for link */
2674         mac->get_link_status = FALSE;
2675
2676 out:
2677         return ret_val;
2678 }
2679
2680
2681 static int
2682 igbvf_dev_configure(struct rte_eth_dev *dev)
2683 {
2684         struct rte_eth_conf* conf = &dev->data->dev_conf;
2685
2686         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2687                      dev->data->port_id);
2688
2689         /*
2690          * VF has no ability to enable/disable HW CRC
2691          * Keep the persistent behavior the same as Host PF
2692          */
2693 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
2694         if (!conf->rxmode.hw_strip_crc) {
2695                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
2696                 conf->rxmode.hw_strip_crc = 1;
2697         }
2698 #else
2699         if (conf->rxmode.hw_strip_crc) {
2700                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
2701                 conf->rxmode.hw_strip_crc = 0;
2702         }
2703 #endif
2704
2705         return 0;
2706 }
2707
2708 static int
2709 igbvf_dev_start(struct rte_eth_dev *dev)
2710 {
2711         struct e1000_hw *hw =
2712                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         struct e1000_adapter *adapter =
2714                 E1000_DEV_PRIVATE(dev->data->dev_private);
2715         int ret;
2716
2717         PMD_INIT_FUNC_TRACE();
2718
2719         hw->mac.ops.reset_hw(hw);
2720         adapter->stopped = 0;
2721
2722         /* Set all vfta */
2723         igbvf_set_vfta_all(dev,1);
2724
2725         eth_igbvf_tx_init(dev);
2726
2727         /* This can fail when allocating mbufs for descriptor rings */
2728         ret = eth_igbvf_rx_init(dev);
2729         if (ret) {
2730                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2731                 igb_dev_clear_queues(dev);
2732                 return ret;
2733         }
2734
2735         return 0;
2736 }
2737
2738 static void
2739 igbvf_dev_stop(struct rte_eth_dev *dev)
2740 {
2741         PMD_INIT_FUNC_TRACE();
2742
2743         igbvf_stop_adapter(dev);
2744
2745         /*
2746           * Clear what we set, but we still keep shadow_vfta to
2747           * restore after device starts
2748           */
2749         igbvf_set_vfta_all(dev,0);
2750
2751         igb_dev_clear_queues(dev);
2752 }
2753
2754 static void
2755 igbvf_dev_close(struct rte_eth_dev *dev)
2756 {
2757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758         struct e1000_adapter *adapter =
2759                 E1000_DEV_PRIVATE(dev->data->dev_private);
2760
2761         PMD_INIT_FUNC_TRACE();
2762
2763         e1000_reset_hw(hw);
2764
2765         igbvf_dev_stop(dev);
2766         adapter->stopped = 1;
2767         igb_dev_free_queues(dev);
2768 }
2769
2770 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
2771 {
2772         struct e1000_mbx_info *mbx = &hw->mbx;
2773         uint32_t msgbuf[2];
2774
2775         /* After set vlan, vlan strip will also be enabled in igb driver*/
2776         msgbuf[0] = E1000_VF_SET_VLAN;
2777         msgbuf[1] = vid;
2778         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
2779         if (on)
2780                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
2781
2782         return (mbx->ops.write_posted(hw, msgbuf, 2, 0));
2783 }
2784
2785 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2786 {
2787         struct e1000_hw *hw =
2788                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2789         struct e1000_vfta * shadow_vfta =
2790                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2791         int i = 0, j = 0, vfta = 0, mask = 1;
2792
2793         for (i = 0; i < IGB_VFTA_SIZE; i++){
2794                 vfta = shadow_vfta->vfta[i];
2795                 if(vfta){
2796                         mask = 1;
2797                         for (j = 0; j < 32; j++){
2798                                 if(vfta & mask)
2799                                         igbvf_set_vfta(hw,
2800                                                 (uint16_t)((i<<5)+j), on);
2801                                 mask<<=1;
2802                         }
2803                 }
2804         }
2805
2806 }
2807
2808 static int
2809 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2810 {
2811         struct e1000_hw *hw =
2812                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct e1000_vfta * shadow_vfta =
2814                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2815         uint32_t vid_idx = 0;
2816         uint32_t vid_bit = 0;
2817         int ret = 0;
2818
2819         PMD_INIT_FUNC_TRACE();
2820
2821         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
2822         ret = igbvf_set_vfta(hw, vlan_id, !!on);
2823         if(ret){
2824                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2825                 return ret;
2826         }
2827         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2828         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2829
2830         /*Save what we set and retore it after device reset*/
2831         if (on)
2832                 shadow_vfta->vfta[vid_idx] |= vid_bit;
2833         else
2834                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2835
2836         return 0;
2837 }
2838
2839 static void
2840 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
2841 {
2842         struct e1000_hw *hw =
2843                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844
2845         /* index is not used by rar_set() */
2846         hw->mac.ops.rar_set(hw, (void *)addr, 0);
2847 }
2848
2849
2850 static int
2851 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
2852                         struct rte_eth_rss_reta_entry64 *reta_conf,
2853                         uint16_t reta_size)
2854 {
2855         uint8_t i, j, mask;
2856         uint32_t reta, r;
2857         uint16_t idx, shift;
2858         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859
2860         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2861                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2862                         "(%d) doesn't match the number hardware can supported "
2863                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2864                 return -EINVAL;
2865         }
2866
2867         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2868                 idx = i / RTE_RETA_GROUP_SIZE;
2869                 shift = i % RTE_RETA_GROUP_SIZE;
2870                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2871                                                 IGB_4_BIT_MASK);
2872                 if (!mask)
2873                         continue;
2874                 if (mask == IGB_4_BIT_MASK)
2875                         r = 0;
2876                 else
2877                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2878                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
2879                         if (mask & (0x1 << j))
2880                                 reta |= reta_conf[idx].reta[shift + j] <<
2881                                                         (CHAR_BIT * j);
2882                         else
2883                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
2884                 }
2885                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
2886         }
2887
2888         return 0;
2889 }
2890
2891 static int
2892 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
2893                        struct rte_eth_rss_reta_entry64 *reta_conf,
2894                        uint16_t reta_size)
2895 {
2896         uint8_t i, j, mask;
2897         uint32_t reta;
2898         uint16_t idx, shift;
2899         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900
2901         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2902                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2903                         "(%d) doesn't match the number hardware can supported "
2904                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2905                 return -EINVAL;
2906         }
2907
2908         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
2909                 idx = i / RTE_RETA_GROUP_SIZE;
2910                 shift = i % RTE_RETA_GROUP_SIZE;
2911                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2912                                                 IGB_4_BIT_MASK);
2913                 if (!mask)
2914                         continue;
2915                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
2916                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
2917                         if (mask & (0x1 << j))
2918                                 reta_conf[idx].reta[shift + j] =
2919                                         ((reta >> (CHAR_BIT * j)) &
2920                                                 IGB_8_BIT_MASK);
2921                 }
2922         }
2923
2924         return 0;
2925 }
2926
2927 #define MAC_TYPE_FILTER_SUP(type)    do {\
2928         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
2929                 (type) != e1000_82576)\
2930                 return -ENOTSUP;\
2931 } while (0)
2932
2933 static int
2934 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
2935                         struct rte_eth_syn_filter *filter,
2936                         bool add)
2937 {
2938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2939         uint32_t synqf, rfctl;
2940
2941         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
2942                 return -EINVAL;
2943
2944         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2945
2946         if (add) {
2947                 if (synqf & E1000_SYN_FILTER_ENABLE)
2948                         return -EINVAL;
2949
2950                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
2951                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
2952
2953                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2954                 if (filter->hig_pri)
2955                         rfctl |= E1000_RFCTL_SYNQFP;
2956                 else
2957                         rfctl &= ~E1000_RFCTL_SYNQFP;
2958
2959                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2960         } else {
2961                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
2962                         return -ENOENT;
2963                 synqf = 0;
2964         }
2965
2966         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
2967         E1000_WRITE_FLUSH(hw);
2968         return 0;
2969 }
2970
2971 static int
2972 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
2973                         struct rte_eth_syn_filter *filter)
2974 {
2975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2976         uint32_t synqf, rfctl;
2977
2978         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
2979         if (synqf & E1000_SYN_FILTER_ENABLE) {
2980                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2981                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
2982                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
2983                                 E1000_SYN_FILTER_QUEUE_SHIFT);
2984                 return 0;
2985         }
2986
2987         return -ENOENT;
2988 }
2989
2990 static int
2991 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
2992                         enum rte_filter_op filter_op,
2993                         void *arg)
2994 {
2995         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996         int ret;
2997
2998         MAC_TYPE_FILTER_SUP(hw->mac.type);
2999
3000         if (filter_op == RTE_ETH_FILTER_NOP)
3001                 return 0;
3002
3003         if (arg == NULL) {
3004                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3005                             filter_op);
3006                 return -EINVAL;
3007         }
3008
3009         switch (filter_op) {
3010         case RTE_ETH_FILTER_ADD:
3011                 ret = eth_igb_syn_filter_set(dev,
3012                                 (struct rte_eth_syn_filter *)arg,
3013                                 TRUE);
3014                 break;
3015         case RTE_ETH_FILTER_DELETE:
3016                 ret = eth_igb_syn_filter_set(dev,
3017                                 (struct rte_eth_syn_filter *)arg,
3018                                 FALSE);
3019                 break;
3020         case RTE_ETH_FILTER_GET:
3021                 ret = eth_igb_syn_filter_get(dev,
3022                                 (struct rte_eth_syn_filter *)arg);
3023                 break;
3024         default:
3025                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3026                 ret = -EINVAL;
3027                 break;
3028         }
3029
3030         return ret;
3031 }
3032
3033 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3034         if ((type) != e1000_82580 && (type) != e1000_i350)\
3035                 return -ENOSYS; \
3036 } while (0)
3037
3038 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3039 static inline int
3040 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3041                         struct e1000_2tuple_filter_info *filter_info)
3042 {
3043         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3044                 return -EINVAL;
3045         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3046                 return -EINVAL;  /* filter index is out of range. */
3047         if (filter->tcp_flags > TCP_FLAG_ALL)
3048                 return -EINVAL;  /* flags is invalid. */
3049
3050         switch (filter->dst_port_mask) {
3051         case UINT16_MAX:
3052                 filter_info->dst_port_mask = 0;
3053                 filter_info->dst_port = filter->dst_port;
3054                 break;
3055         case 0:
3056                 filter_info->dst_port_mask = 1;
3057                 break;
3058         default:
3059                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3060                 return -EINVAL;
3061         }
3062
3063         switch (filter->proto_mask) {
3064         case UINT8_MAX:
3065                 filter_info->proto_mask = 0;
3066                 filter_info->proto = filter->proto;
3067                 break;
3068         case 0:
3069                 filter_info->proto_mask = 1;
3070                 break;
3071         default:
3072                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3073                 return -EINVAL;
3074         }
3075
3076         filter_info->priority = (uint8_t)filter->priority;
3077         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3078                 filter_info->tcp_flags = filter->tcp_flags;
3079         else
3080                 filter_info->tcp_flags = 0;
3081
3082         return 0;
3083 }
3084
3085 static inline struct e1000_2tuple_filter *
3086 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3087                         struct e1000_2tuple_filter_info *key)
3088 {
3089         struct e1000_2tuple_filter *it;
3090
3091         TAILQ_FOREACH(it, filter_list, entries) {
3092                 if (memcmp(key, &it->filter_info,
3093                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3094                         return it;
3095                 }
3096         }
3097         return NULL;
3098 }
3099
3100 /*
3101  * igb_add_2tuple_filter - add a 2tuple filter
3102  *
3103  * @param
3104  * dev: Pointer to struct rte_eth_dev.
3105  * ntuple_filter: ponter to the filter that will be added.
3106  *
3107  * @return
3108  *    - On success, zero.
3109  *    - On failure, a negative value.
3110  */
3111 static int
3112 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3113                         struct rte_eth_ntuple_filter *ntuple_filter)
3114 {
3115         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116         struct e1000_filter_info *filter_info =
3117                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3118         struct e1000_2tuple_filter *filter;
3119         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3120         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3121         int i, ret;
3122
3123         filter = rte_zmalloc("e1000_2tuple_filter",
3124                         sizeof(struct e1000_2tuple_filter), 0);
3125         if (filter == NULL)
3126                 return -ENOMEM;
3127
3128         ret = ntuple_filter_to_2tuple(ntuple_filter,
3129                                       &filter->filter_info);
3130         if (ret < 0) {
3131                 rte_free(filter);
3132                 return ret;
3133         }
3134         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3135                                          &filter->filter_info) != NULL) {
3136                 PMD_DRV_LOG(ERR, "filter exists.");
3137                 rte_free(filter);
3138                 return -EEXIST;
3139         }
3140         filter->queue = ntuple_filter->queue;
3141
3142         /*
3143          * look for an unused 2tuple filter index,
3144          * and insert the filter to list.
3145          */
3146         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3147                 if (!(filter_info->twotuple_mask & (1 << i))) {
3148                         filter_info->twotuple_mask |= 1 << i;
3149                         filter->index = i;
3150                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3151                                           filter,
3152                                           entries);
3153                         break;
3154                 }
3155         }
3156         if (i >= E1000_MAX_TTQF_FILTERS) {
3157                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3158                 rte_free(filter);
3159                 return -ENOSYS;
3160         }
3161
3162         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3163         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3164                 imir |= E1000_IMIR_PORT_BP;
3165         else
3166                 imir &= ~E1000_IMIR_PORT_BP;
3167
3168         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3169
3170         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3171         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3172         ttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);
3173         if (filter->filter_info.proto_mask == 0)
3174                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3175
3176         /* tcp flags bits setting. */
3177         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3178                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3179                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3180                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3181                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3182                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3183                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3184                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3185                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3186                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3187                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3188                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3189                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3190         } else
3191                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3192         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3193         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3194         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3195         return 0;
3196 }
3197
3198 /*
3199  * igb_remove_2tuple_filter - remove a 2tuple filter
3200  *
3201  * @param
3202  * dev: Pointer to struct rte_eth_dev.
3203  * ntuple_filter: ponter to the filter that will be removed.
3204  *
3205  * @return
3206  *    - On success, zero.
3207  *    - On failure, a negative value.
3208  */
3209 static int
3210 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3211                         struct rte_eth_ntuple_filter *ntuple_filter)
3212 {
3213         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         struct e1000_filter_info *filter_info =
3215                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3216         struct e1000_2tuple_filter_info filter_2tuple;
3217         struct e1000_2tuple_filter *filter;
3218         int ret;
3219
3220         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3221         ret = ntuple_filter_to_2tuple(ntuple_filter,
3222                                       &filter_2tuple);
3223         if (ret < 0)
3224                 return ret;
3225
3226         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3227                                          &filter_2tuple);
3228         if (filter == NULL) {
3229                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3230                 return -ENOENT;
3231         }
3232
3233         filter_info->twotuple_mask &= ~(1 << filter->index);
3234         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3235         rte_free(filter);
3236
3237         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3238         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3239         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3240         return 0;
3241 }
3242
3243 static inline struct e1000_flex_filter *
3244 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3245                         struct e1000_flex_filter_info *key)
3246 {
3247         struct e1000_flex_filter *it;
3248
3249         TAILQ_FOREACH(it, filter_list, entries) {
3250                 if (memcmp(key, &it->filter_info,
3251                         sizeof(struct e1000_flex_filter_info)) == 0)
3252                         return it;
3253         }
3254
3255         return NULL;
3256 }
3257
3258 static int
3259 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3260                         struct rte_eth_flex_filter *filter,
3261                         bool add)
3262 {
3263         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3264         struct e1000_filter_info *filter_info =
3265                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3266         struct e1000_flex_filter *flex_filter, *it;
3267         uint32_t wufc, queueing, mask;
3268         uint32_t reg_off;
3269         uint8_t shift, i, j = 0;
3270
3271         flex_filter = rte_zmalloc("e1000_flex_filter",
3272                         sizeof(struct e1000_flex_filter), 0);
3273         if (flex_filter == NULL)
3274                 return -ENOMEM;
3275
3276         flex_filter->filter_info.len = filter->len;
3277         flex_filter->filter_info.priority = filter->priority;
3278         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3279         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3280                 mask = 0;
3281                 /* reverse bits in flex filter's mask*/
3282                 for (shift = 0; shift < CHAR_BIT; shift++) {
3283                         if (filter->mask[i] & (0x01 << shift))
3284                                 mask |= (0x80 >> shift);
3285                 }
3286                 flex_filter->filter_info.mask[i] = mask;
3287         }
3288
3289         wufc = E1000_READ_REG(hw, E1000_WUFC);
3290         if (flex_filter->index < E1000_MAX_FHFT)
3291                 reg_off = E1000_FHFT(flex_filter->index);
3292         else
3293                 reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3294
3295         if (add) {
3296                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3297                                 &flex_filter->filter_info) != NULL) {
3298                         PMD_DRV_LOG(ERR, "filter exists.");
3299                         rte_free(flex_filter);
3300                         return -EEXIST;
3301                 }
3302                 flex_filter->queue = filter->queue;
3303                 /*
3304                  * look for an unused flex filter index
3305                  * and insert the filter into the list.
3306                  */
3307                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3308                         if (!(filter_info->flex_mask & (1 << i))) {
3309                                 filter_info->flex_mask |= 1 << i;
3310                                 flex_filter->index = i;
3311                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3312                                         flex_filter,
3313                                         entries);
3314                                 break;
3315                         }
3316                 }
3317                 if (i >= E1000_MAX_FLEX_FILTERS) {
3318                         PMD_DRV_LOG(ERR, "flex filters are full.");
3319                         rte_free(flex_filter);
3320                         return -ENOSYS;
3321                 }
3322
3323                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3324                                 (E1000_WUFC_FLX0 << flex_filter->index));
3325                 queueing = filter->len |
3326                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3327                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3328                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3329                                 queueing);
3330                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3331                         E1000_WRITE_REG(hw, reg_off,
3332                                         flex_filter->filter_info.dwords[j]);
3333                         reg_off += sizeof(uint32_t);
3334                         E1000_WRITE_REG(hw, reg_off,
3335                                         flex_filter->filter_info.dwords[++j]);
3336                         reg_off += sizeof(uint32_t);
3337                         E1000_WRITE_REG(hw, reg_off,
3338                                 (uint32_t)flex_filter->filter_info.mask[i]);
3339                         reg_off += sizeof(uint32_t) * 2;
3340                         ++j;
3341                 }
3342         } else {
3343                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3344                                 &flex_filter->filter_info);
3345                 if (it == NULL) {
3346                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3347                         rte_free(flex_filter);
3348                         return -ENOENT;
3349                 }
3350
3351                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3352                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3353                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3354                         (~(E1000_WUFC_FLX0 << it->index)));
3355
3356                 filter_info->flex_mask &= ~(1 << it->index);
3357                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
3358                 rte_free(it);
3359                 rte_free(flex_filter);
3360         }
3361
3362         return 0;
3363 }
3364
3365 static int
3366 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
3367                         struct rte_eth_flex_filter *filter)
3368 {
3369         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370         struct e1000_filter_info *filter_info =
3371                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3372         struct e1000_flex_filter flex_filter, *it;
3373         uint32_t wufc, queueing, wufc_en = 0;
3374
3375         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
3376         flex_filter.filter_info.len = filter->len;
3377         flex_filter.filter_info.priority = filter->priority;
3378         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
3379         memcpy(flex_filter.filter_info.mask, filter->mask,
3380                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
3381
3382         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3383                                 &flex_filter.filter_info);
3384         if (it == NULL) {
3385                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3386                 return -ENOENT;
3387         }
3388
3389         wufc = E1000_READ_REG(hw, E1000_WUFC);
3390         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
3391
3392         if ((wufc & wufc_en) == wufc_en) {
3393                 uint32_t reg_off = 0;
3394                 if (it->index < E1000_MAX_FHFT)
3395                         reg_off = E1000_FHFT(it->index);
3396                 else
3397                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
3398
3399                 queueing = E1000_READ_REG(hw,
3400                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
3401                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
3402                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
3403                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
3404                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
3405                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
3406                 return 0;
3407         }
3408         return -ENOENT;
3409 }
3410
3411 static int
3412 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
3413                         enum rte_filter_op filter_op,
3414                         void *arg)
3415 {
3416         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         struct rte_eth_flex_filter *filter;
3418         int ret = 0;
3419
3420         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
3421
3422         if (filter_op == RTE_ETH_FILTER_NOP)
3423                 return ret;
3424
3425         if (arg == NULL) {
3426                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3427                             filter_op);
3428                 return -EINVAL;
3429         }
3430
3431         filter = (struct rte_eth_flex_filter *)arg;
3432         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
3433             || filter->len % sizeof(uint64_t) != 0) {
3434                 PMD_DRV_LOG(ERR, "filter's length is out of range");
3435                 return -EINVAL;
3436         }
3437         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
3438                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
3439                 return -EINVAL;
3440         }
3441
3442         switch (filter_op) {
3443         case RTE_ETH_FILTER_ADD:
3444                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
3445                 break;
3446         case RTE_ETH_FILTER_DELETE:
3447                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
3448                 break;
3449         case RTE_ETH_FILTER_GET:
3450                 ret = eth_igb_get_flex_filter(dev, filter);
3451                 break;
3452         default:
3453                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3454                 ret = -EINVAL;
3455                 break;
3456         }
3457
3458         return ret;
3459 }
3460
3461 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
3462 static inline int
3463 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
3464                         struct e1000_5tuple_filter_info *filter_info)
3465 {
3466         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
3467                 return -EINVAL;
3468         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3469                 return -EINVAL;  /* filter index is out of range. */
3470         if (filter->tcp_flags > TCP_FLAG_ALL)
3471                 return -EINVAL;  /* flags is invalid. */
3472
3473         switch (filter->dst_ip_mask) {
3474         case UINT32_MAX:
3475                 filter_info->dst_ip_mask = 0;
3476                 filter_info->dst_ip = filter->dst_ip;
3477                 break;
3478         case 0:
3479                 filter_info->dst_ip_mask = 1;
3480                 break;
3481         default:
3482                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3483                 return -EINVAL;
3484         }
3485
3486         switch (filter->src_ip_mask) {
3487         case UINT32_MAX:
3488                 filter_info->src_ip_mask = 0;
3489                 filter_info->src_ip = filter->src_ip;
3490                 break;
3491         case 0:
3492                 filter_info->src_ip_mask = 1;
3493                 break;
3494         default:
3495                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3496                 return -EINVAL;
3497         }
3498
3499         switch (filter->dst_port_mask) {
3500         case UINT16_MAX:
3501                 filter_info->dst_port_mask = 0;
3502                 filter_info->dst_port = filter->dst_port;
3503                 break;
3504         case 0:
3505                 filter_info->dst_port_mask = 1;
3506                 break;
3507         default:
3508                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3509                 return -EINVAL;
3510         }
3511
3512         switch (filter->src_port_mask) {
3513         case UINT16_MAX:
3514                 filter_info->src_port_mask = 0;
3515                 filter_info->src_port = filter->src_port;
3516                 break;
3517         case 0:
3518                 filter_info->src_port_mask = 1;
3519                 break;
3520         default:
3521                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3522                 return -EINVAL;
3523         }
3524
3525         switch (filter->proto_mask) {
3526         case UINT8_MAX:
3527                 filter_info->proto_mask = 0;
3528                 filter_info->proto = filter->proto;
3529                 break;
3530         case 0:
3531                 filter_info->proto_mask = 1;
3532                 break;
3533         default:
3534                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3535                 return -EINVAL;
3536         }
3537
3538         filter_info->priority = (uint8_t)filter->priority;
3539         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3540                 filter_info->tcp_flags = filter->tcp_flags;
3541         else
3542                 filter_info->tcp_flags = 0;
3543
3544         return 0;
3545 }
3546
3547 static inline struct e1000_5tuple_filter *
3548 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
3549                         struct e1000_5tuple_filter_info *key)
3550 {
3551         struct e1000_5tuple_filter *it;
3552
3553         TAILQ_FOREACH(it, filter_list, entries) {
3554                 if (memcmp(key, &it->filter_info,
3555                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
3556                         return it;
3557                 }
3558         }
3559         return NULL;
3560 }
3561
3562 /*
3563  * igb_add_5tuple_filter_82576 - add a 5tuple filter
3564  *
3565  * @param
3566  * dev: Pointer to struct rte_eth_dev.
3567  * ntuple_filter: ponter to the filter that will be added.
3568  *
3569  * @return
3570  *    - On success, zero.
3571  *    - On failure, a negative value.
3572  */
3573 static int
3574 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
3575                         struct rte_eth_ntuple_filter *ntuple_filter)
3576 {
3577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578         struct e1000_filter_info *filter_info =
3579                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3580         struct e1000_5tuple_filter *filter;
3581         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
3582         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3583         uint8_t i;
3584         int ret;
3585
3586         filter = rte_zmalloc("e1000_5tuple_filter",
3587                         sizeof(struct e1000_5tuple_filter), 0);
3588         if (filter == NULL)
3589                 return -ENOMEM;
3590
3591         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3592                                             &filter->filter_info);
3593         if (ret < 0) {
3594                 rte_free(filter);
3595                 return ret;
3596         }
3597
3598         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3599                                          &filter->filter_info) != NULL) {
3600                 PMD_DRV_LOG(ERR, "filter exists.");
3601                 rte_free(filter);
3602                 return -EEXIST;
3603         }
3604         filter->queue = ntuple_filter->queue;
3605
3606         /*
3607          * look for an unused 5tuple filter index,
3608          * and insert the filter to list.
3609          */
3610         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
3611                 if (!(filter_info->fivetuple_mask & (1 << i))) {
3612                         filter_info->fivetuple_mask |= 1 << i;
3613                         filter->index = i;
3614                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3615                                           filter,
3616                                           entries);
3617                         break;
3618                 }
3619         }
3620         if (i >= E1000_MAX_FTQF_FILTERS) {
3621                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3622                 rte_free(filter);
3623                 return -ENOSYS;
3624         }
3625
3626         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
3627         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
3628                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
3629         if (filter->filter_info.dst_ip_mask == 0)
3630                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
3631         if (filter->filter_info.src_port_mask == 0)
3632                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
3633         if (filter->filter_info.proto_mask == 0)
3634                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
3635         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
3636                 E1000_FTQF_QUEUE_MASK;
3637         ftqf |= E1000_FTQF_QUEUE_ENABLE;
3638         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
3639         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
3640         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
3641
3642         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
3643         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
3644
3645         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3646         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3647                 imir |= E1000_IMIR_PORT_BP;
3648         else
3649                 imir &= ~E1000_IMIR_PORT_BP;
3650         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3651
3652         /* tcp flags bits setting. */
3653         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3654                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3655                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3656                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3657                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3658                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3659                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3660                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3661                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3662                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3663                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3664                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3665                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3666         } else
3667                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3668         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3669         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3670         return 0;
3671 }
3672
3673 /*
3674  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
3675  *
3676  * @param
3677  * dev: Pointer to struct rte_eth_dev.
3678  * ntuple_filter: ponter to the filter that will be removed.
3679  *
3680  * @return
3681  *    - On success, zero.
3682  *    - On failure, a negative value.
3683  */
3684 static int
3685 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
3686                                 struct rte_eth_ntuple_filter *ntuple_filter)
3687 {
3688         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689         struct e1000_filter_info *filter_info =
3690                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3691         struct e1000_5tuple_filter_info filter_5tuple;
3692         struct e1000_5tuple_filter *filter;
3693         int ret;
3694
3695         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
3696         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3697                                             &filter_5tuple);
3698         if (ret < 0)
3699                 return ret;
3700
3701         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
3702                                          &filter_5tuple);
3703         if (filter == NULL) {
3704                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3705                 return -ENOENT;
3706         }
3707
3708         filter_info->fivetuple_mask &= ~(1 << filter->index);
3709         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3710         rte_free(filter);
3711
3712         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
3713                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
3714         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
3715         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
3716         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
3717         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3718         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3719         return 0;
3720 }
3721
3722 static int
3723 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3724 {
3725         uint32_t rctl;
3726         struct e1000_hw *hw;
3727         struct rte_eth_dev_info dev_info;
3728         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
3729                                      VLAN_TAG_SIZE);
3730
3731         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732
3733 #ifdef RTE_LIBRTE_82571_SUPPORT
3734         /* XXX: not bigger than max_rx_pktlen */
3735         if (hw->mac.type == e1000_82571)
3736                 return -ENOTSUP;
3737 #endif
3738         eth_igb_infos_get(dev, &dev_info);
3739
3740         /* check that mtu is within the allowed range */
3741         if ((mtu < ETHER_MIN_MTU) ||
3742             (frame_size > dev_info.max_rx_pktlen))
3743                 return -EINVAL;
3744
3745         /* refuse mtu that requires the support of scattered packets when this
3746          * feature has not been enabled before. */
3747         if (!dev->data->scattered_rx &&
3748             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
3749                 return -EINVAL;
3750
3751         rctl = E1000_READ_REG(hw, E1000_RCTL);
3752
3753         /* switch to jumbo mode if needed */
3754         if (frame_size > ETHER_MAX_LEN) {
3755                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3756                 rctl |= E1000_RCTL_LPE;
3757         } else {
3758                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3759                 rctl &= ~E1000_RCTL_LPE;
3760         }
3761         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3762
3763         /* update max frame size */
3764         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3765
3766         E1000_WRITE_REG(hw, E1000_RLPML,
3767                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
3768
3769         return 0;
3770 }
3771
3772 /*
3773  * igb_add_del_ntuple_filter - add or delete a ntuple filter
3774  *
3775  * @param
3776  * dev: Pointer to struct rte_eth_dev.
3777  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3778  * add: if true, add filter, if false, remove filter
3779  *
3780  * @return
3781  *    - On success, zero.
3782  *    - On failure, a negative value.
3783  */
3784 static int
3785 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
3786                         struct rte_eth_ntuple_filter *ntuple_filter,
3787                         bool add)
3788 {
3789         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790         int ret;
3791
3792         switch (ntuple_filter->flags) {
3793         case RTE_5TUPLE_FLAGS:
3794         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3795                 if (hw->mac.type != e1000_82576)
3796                         return -ENOTSUP;
3797                 if (add)
3798                         ret = igb_add_5tuple_filter_82576(dev,
3799                                                           ntuple_filter);
3800                 else
3801                         ret = igb_remove_5tuple_filter_82576(dev,
3802                                                              ntuple_filter);
3803                 break;
3804         case RTE_2TUPLE_FLAGS:
3805         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3806                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3807                         return -ENOTSUP;
3808                 if (add)
3809                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
3810                 else
3811                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
3812                 break;
3813         default:
3814                 ret = -EINVAL;
3815                 break;
3816         }
3817
3818         return ret;
3819 }
3820
3821 /*
3822  * igb_get_ntuple_filter - get a ntuple filter
3823  *
3824  * @param
3825  * dev: Pointer to struct rte_eth_dev.
3826  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3827  *
3828  * @return
3829  *    - On success, zero.
3830  *    - On failure, a negative value.
3831  */
3832 static int
3833 igb_get_ntuple_filter(struct rte_eth_dev *dev,
3834                         struct rte_eth_ntuple_filter *ntuple_filter)
3835 {
3836         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837         struct e1000_filter_info *filter_info =
3838                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3839         struct e1000_5tuple_filter_info filter_5tuple;
3840         struct e1000_2tuple_filter_info filter_2tuple;
3841         struct e1000_5tuple_filter *p_5tuple_filter;
3842         struct e1000_2tuple_filter *p_2tuple_filter;
3843         int ret;
3844
3845         switch (ntuple_filter->flags) {
3846         case RTE_5TUPLE_FLAGS:
3847         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3848                 if (hw->mac.type != e1000_82576)
3849                         return -ENOTSUP;
3850                 memset(&filter_5tuple,
3851                         0,
3852                         sizeof(struct e1000_5tuple_filter_info));
3853                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
3854                                                     &filter_5tuple);
3855                 if (ret < 0)
3856                         return ret;
3857                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
3858                                         &filter_info->fivetuple_list,
3859                                         &filter_5tuple);
3860                 if (p_5tuple_filter == NULL) {
3861                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3862                         return -ENOENT;
3863                 }
3864                 ntuple_filter->queue = p_5tuple_filter->queue;
3865                 break;
3866         case RTE_2TUPLE_FLAGS:
3867         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
3868                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
3869                         return -ENOTSUP;
3870                 memset(&filter_2tuple,
3871                         0,
3872                         sizeof(struct e1000_2tuple_filter_info));
3873                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
3874                 if (ret < 0)
3875                         return ret;
3876                 p_2tuple_filter = igb_2tuple_filter_lookup(
3877                                         &filter_info->twotuple_list,
3878                                         &filter_2tuple);
3879                 if (p_2tuple_filter == NULL) {
3880                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
3881                         return -ENOENT;
3882                 }
3883                 ntuple_filter->queue = p_2tuple_filter->queue;
3884                 break;
3885         default:
3886                 ret = -EINVAL;
3887                 break;
3888         }
3889
3890         return 0;
3891 }
3892
3893 /*
3894  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
3895  * @dev: pointer to rte_eth_dev structure
3896  * @filter_op:operation will be taken.
3897  * @arg: a pointer to specific structure corresponding to the filter_op
3898  */
3899 static int
3900 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
3901                                 enum rte_filter_op filter_op,
3902                                 void *arg)
3903 {
3904         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905         int ret;
3906
3907         MAC_TYPE_FILTER_SUP(hw->mac.type);
3908
3909         if (filter_op == RTE_ETH_FILTER_NOP)
3910                 return 0;
3911
3912         if (arg == NULL) {
3913                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3914                             filter_op);
3915                 return -EINVAL;
3916         }
3917
3918         switch (filter_op) {
3919         case RTE_ETH_FILTER_ADD:
3920                 ret = igb_add_del_ntuple_filter(dev,
3921                         (struct rte_eth_ntuple_filter *)arg,
3922                         TRUE);
3923                 break;
3924         case RTE_ETH_FILTER_DELETE:
3925                 ret = igb_add_del_ntuple_filter(dev,
3926                         (struct rte_eth_ntuple_filter *)arg,
3927                         FALSE);
3928                 break;
3929         case RTE_ETH_FILTER_GET:
3930                 ret = igb_get_ntuple_filter(dev,
3931                         (struct rte_eth_ntuple_filter *)arg);
3932                 break;
3933         default:
3934                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3935                 ret = -EINVAL;
3936                 break;
3937         }
3938         return ret;
3939 }
3940
3941 static inline int
3942 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
3943                         uint16_t ethertype)
3944 {
3945         int i;
3946
3947         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3948                 if (filter_info->ethertype_filters[i] == ethertype &&
3949                     (filter_info->ethertype_mask & (1 << i)))
3950                         return i;
3951         }
3952         return -1;
3953 }
3954
3955 static inline int
3956 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
3957                         uint16_t ethertype)
3958 {
3959         int i;
3960
3961         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
3962                 if (!(filter_info->ethertype_mask & (1 << i))) {
3963                         filter_info->ethertype_mask |= 1 << i;
3964                         filter_info->ethertype_filters[i] = ethertype;
3965                         return i;
3966                 }
3967         }
3968         return -1;
3969 }
3970
3971 static inline int
3972 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
3973                         uint8_t idx)
3974 {
3975         if (idx >= E1000_MAX_ETQF_FILTERS)
3976                 return -1;
3977         filter_info->ethertype_mask &= ~(1 << idx);
3978         filter_info->ethertype_filters[idx] = 0;
3979         return idx;
3980 }
3981
3982
3983 static int
3984 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
3985                         struct rte_eth_ethertype_filter *filter,
3986                         bool add)
3987 {
3988         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3989         struct e1000_filter_info *filter_info =
3990                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3991         uint32_t etqf = 0;
3992         int ret;
3993
3994         if (filter->ether_type == ETHER_TYPE_IPv4 ||
3995                 filter->ether_type == ETHER_TYPE_IPv6) {
3996                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3997                         " ethertype filter.", filter->ether_type);
3998                 return -EINVAL;
3999         }
4000
4001         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4002                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4003                 return -EINVAL;
4004         }
4005         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4006                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4007                 return -EINVAL;
4008         }
4009
4010         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4011         if (ret >= 0 && add) {
4012                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4013                             filter->ether_type);
4014                 return -EEXIST;
4015         }
4016         if (ret < 0 && !add) {
4017                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4018                             filter->ether_type);
4019                 return -ENOENT;
4020         }
4021
4022         if (add) {
4023                 ret = igb_ethertype_filter_insert(filter_info,
4024                         filter->ether_type);
4025                 if (ret < 0) {
4026                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4027                         return -ENOSYS;
4028                 }
4029
4030                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4031                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4032                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4033         } else {
4034                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4035                 if (ret < 0)
4036                         return -ENOSYS;
4037         }
4038         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4039         E1000_WRITE_FLUSH(hw);
4040
4041         return 0;
4042 }
4043
4044 static int
4045 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4046                         struct rte_eth_ethertype_filter *filter)
4047 {
4048         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4049         struct e1000_filter_info *filter_info =
4050                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4051         uint32_t etqf;
4052         int ret;
4053
4054         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4055         if (ret < 0) {
4056                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4057                             filter->ether_type);
4058                 return -ENOENT;
4059         }
4060
4061         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4062         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4063                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4064                 filter->flags = 0;
4065                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4066                                 E1000_ETQF_QUEUE_SHIFT;
4067                 return 0;
4068         }
4069
4070         return -ENOENT;
4071 }
4072
4073 /*
4074  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4075  * @dev: pointer to rte_eth_dev structure
4076  * @filter_op:operation will be taken.
4077  * @arg: a pointer to specific structure corresponding to the filter_op
4078  */
4079 static int
4080 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4081                                 enum rte_filter_op filter_op,
4082                                 void *arg)
4083 {
4084         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         int ret;
4086
4087         MAC_TYPE_FILTER_SUP(hw->mac.type);
4088
4089         if (filter_op == RTE_ETH_FILTER_NOP)
4090                 return 0;
4091
4092         if (arg == NULL) {
4093                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4094                             filter_op);
4095                 return -EINVAL;
4096         }
4097
4098         switch (filter_op) {
4099         case RTE_ETH_FILTER_ADD:
4100                 ret = igb_add_del_ethertype_filter(dev,
4101                         (struct rte_eth_ethertype_filter *)arg,
4102                         TRUE);
4103                 break;
4104         case RTE_ETH_FILTER_DELETE:
4105                 ret = igb_add_del_ethertype_filter(dev,
4106                         (struct rte_eth_ethertype_filter *)arg,
4107                         FALSE);
4108                 break;
4109         case RTE_ETH_FILTER_GET:
4110                 ret = igb_get_ethertype_filter(dev,
4111                         (struct rte_eth_ethertype_filter *)arg);
4112                 break;
4113         default:
4114                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4115                 ret = -EINVAL;
4116                 break;
4117         }
4118         return ret;
4119 }
4120
4121 static int
4122 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4123                      enum rte_filter_type filter_type,
4124                      enum rte_filter_op filter_op,
4125                      void *arg)
4126 {
4127         int ret = -EINVAL;
4128
4129         switch (filter_type) {
4130         case RTE_ETH_FILTER_NTUPLE:
4131                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4132                 break;
4133         case RTE_ETH_FILTER_ETHERTYPE:
4134                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4135                 break;
4136         case RTE_ETH_FILTER_SYN:
4137                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4138                 break;
4139         case RTE_ETH_FILTER_FLEXIBLE:
4140                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4141                 break;
4142         default:
4143                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4144                                                         filter_type);
4145                 break;
4146         }
4147
4148         return ret;
4149 }
4150
4151 static int
4152 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4153                          struct ether_addr *mc_addr_set,
4154                          uint32_t nb_mc_addr)
4155 {
4156         struct e1000_hw *hw;
4157
4158         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4160         return 0;
4161 }
4162
4163 static int
4164 igb_timesync_enable(struct rte_eth_dev *dev)
4165 {
4166         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4167         uint32_t tsync_ctl;
4168         uint32_t tsauxc;
4169
4170         /* Enable system time for it isn't on by default. */
4171         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
4172         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
4173         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
4174
4175         /* Start incrementing the register used to timestamp PTP packets. */
4176         E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
4177
4178         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4179         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
4180                         (ETHER_TYPE_1588 |
4181                          E1000_ETQF_FILTER_ENABLE |
4182                          E1000_ETQF_1588));
4183
4184         /* Enable timestamping of received PTP packets. */
4185         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4186         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
4187         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4188
4189         /* Enable Timestamping of transmitted PTP packets. */
4190         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4191         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
4192         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4193
4194         return 0;
4195 }
4196
4197 static int
4198 igb_timesync_disable(struct rte_eth_dev *dev)
4199 {
4200         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         uint32_t tsync_ctl;
4202
4203         /* Disable timestamping of transmitted PTP packets. */
4204         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4205         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
4206         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
4207
4208         /* Disable timestamping of received PTP packets. */
4209         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4210         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
4211         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
4212
4213         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4214         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
4215
4216         /* Stop incrementating the System Time registers. */
4217         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
4218
4219         return 0;
4220 }
4221
4222 static int
4223 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4224                                struct timespec *timestamp,
4225                                uint32_t flags __rte_unused)
4226 {
4227         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4228         uint32_t tsync_rxctl;
4229         uint32_t rx_stmpl;
4230         uint32_t rx_stmph;
4231
4232         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
4233         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
4234                 return -EINVAL;
4235
4236         rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
4237         rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
4238
4239         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4240         timestamp->tv_nsec = 0;
4241
4242         return  0;
4243 }
4244
4245 static int
4246 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4247                                struct timespec *timestamp)
4248 {
4249         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4250         uint32_t tsync_txctl;
4251         uint32_t tx_stmpl;
4252         uint32_t tx_stmph;
4253
4254         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
4255         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
4256                 return -EINVAL;
4257
4258         tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
4259         tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
4260
4261         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4262         timestamp->tv_nsec = 0;
4263
4264         return  0;
4265 }
4266
4267 static int
4268 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4269 {
4270         int count = 0;
4271         int g_ind = 0;
4272         const struct reg_info *reg_group;
4273
4274         while ((reg_group = igb_regs[g_ind++]))
4275                 count += igb_reg_group_count(reg_group);
4276
4277         return count;
4278 }
4279
4280 static int
4281 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4282 {
4283         int count = 0;
4284         int g_ind = 0;
4285         const struct reg_info *reg_group;
4286
4287         while ((reg_group = igbvf_regs[g_ind++]))
4288                 count += igb_reg_group_count(reg_group);
4289
4290         return count;
4291 }
4292
4293 static int
4294 eth_igb_get_regs(struct rte_eth_dev *dev,
4295         struct rte_dev_reg_info *regs)
4296 {
4297         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298         uint32_t *data = regs->data;
4299         int g_ind = 0;
4300         int count = 0;
4301         const struct reg_info *reg_group;
4302
4303         /* Support only full register dump */
4304         if ((regs->length == 0) ||
4305             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
4306                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4307                         hw->device_id;
4308                 while ((reg_group = igb_regs[g_ind++]))
4309                         count += igb_read_regs_group(dev, &data[count],
4310                                                         reg_group);
4311                 return 0;
4312         }
4313
4314         return -ENOTSUP;
4315 }
4316
4317 static int
4318 igbvf_get_regs(struct rte_eth_dev *dev,
4319         struct rte_dev_reg_info *regs)
4320 {
4321         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322         uint32_t *data = regs->data;
4323         int g_ind = 0;
4324         int count = 0;
4325         const struct reg_info *reg_group;
4326
4327         /* Support only full register dump */
4328         if ((regs->length == 0) ||
4329             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
4330                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4331                         hw->device_id;
4332                 while ((reg_group = igbvf_regs[g_ind++]))
4333                         count += igb_read_regs_group(dev, &data[count],
4334                                                         reg_group);
4335                 return 0;
4336         }
4337
4338         return -ENOTSUP;
4339 }
4340
4341 static int
4342 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
4343 {
4344         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345
4346         /* Return unit is byte count */
4347         return hw->nvm.word_size * 2;
4348 }
4349
4350 static int
4351 eth_igb_get_eeprom(struct rte_eth_dev *dev,
4352         struct rte_dev_eeprom_info *in_eeprom)
4353 {
4354         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         struct e1000_nvm_info *nvm = &hw->nvm;
4356         uint16_t *data = in_eeprom->data;
4357         int first, length;
4358
4359         first = in_eeprom->offset >> 1;
4360         length = in_eeprom->length >> 1;
4361         if ((first >= hw->nvm.word_size) ||
4362             ((first + length) >= hw->nvm.word_size))
4363                 return -EINVAL;
4364
4365         in_eeprom->magic = hw->vendor_id |
4366                 ((uint32_t)hw->device_id << 16);
4367
4368         if ((nvm->ops.read) == NULL)
4369                 return -ENOTSUP;
4370
4371         return nvm->ops.read(hw, first, length, data);
4372 }
4373
4374 static int
4375 eth_igb_set_eeprom(struct rte_eth_dev *dev,
4376         struct rte_dev_eeprom_info *in_eeprom)
4377 {
4378         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379         struct e1000_nvm_info *nvm = &hw->nvm;
4380         uint16_t *data = in_eeprom->data;
4381         int first, length;
4382
4383         first = in_eeprom->offset >> 1;
4384         length = in_eeprom->length >> 1;
4385         if ((first >= hw->nvm.word_size) ||
4386             ((first + length) >= hw->nvm.word_size))
4387                 return -EINVAL;
4388
4389         in_eeprom->magic = (uint32_t)hw->vendor_id |
4390                 ((uint32_t)hw->device_id << 16);
4391
4392         if ((nvm->ops.write) == NULL)
4393                 return -ENOTSUP;
4394         return nvm->ops.write(hw,  first, length, data);
4395 }
4396
4397 static struct rte_driver pmd_igb_drv = {
4398         .type = PMD_PDEV,
4399         .init = rte_igb_pmd_init,
4400 };
4401
4402 static struct rte_driver pmd_igbvf_drv = {
4403         .type = PMD_PDEV,
4404         .init = rte_igbvf_pmd_init,
4405 };
4406
4407 static int
4408 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4409 {
4410         struct e1000_hw *hw =
4411                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         uint32_t mask = 1 << queue_id;
4413
4414         E1000_WRITE_REG(hw, E1000_EIMC, mask);
4415         E1000_WRITE_FLUSH(hw);
4416
4417         return 0;
4418 }
4419
4420 static int
4421 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4422 {
4423         struct e1000_hw *hw =
4424                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425         uint32_t mask = 1 << queue_id;
4426         uint32_t regval;
4427
4428         regval = E1000_READ_REG(hw, E1000_EIMS);
4429         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
4430         E1000_WRITE_FLUSH(hw);
4431
4432         rte_intr_enable(&dev->pci_dev->intr_handle);
4433
4434         return 0;
4435 }
4436
4437 static void
4438 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
4439                    uint8_t index, uint8_t offset)
4440 {
4441         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
4442
4443         /* clear bits */
4444         val &= ~((uint32_t)0xFF << offset);
4445
4446         /* write vector and valid bit */
4447         val |= (msix_vector | E1000_IVAR_VALID) << offset;
4448
4449         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
4450 }
4451
4452 static void
4453 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
4454                            uint8_t queue, uint8_t msix_vector)
4455 {
4456         uint32_t tmp = 0;
4457
4458         if (hw->mac.type == e1000_82575) {
4459                 if (direction == 0)
4460                         tmp = E1000_EICR_RX_QUEUE0 << queue;
4461                 else if (direction == 1)
4462                         tmp = E1000_EICR_TX_QUEUE0 << queue;
4463                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
4464         } else if (hw->mac.type == e1000_82576) {
4465                 if ((direction == 0) || (direction == 1))
4466                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
4467                                            ((queue & 0x8) << 1) +
4468                                            8 * direction);
4469         } else if ((hw->mac.type == e1000_82580) ||
4470                         (hw->mac.type == e1000_i350) ||
4471                         (hw->mac.type == e1000_i354) ||
4472                         (hw->mac.type == e1000_i210) ||
4473                         (hw->mac.type == e1000_i211)) {
4474                 if ((direction == 0) || (direction == 1))
4475                         eth_igb_write_ivar(hw, msix_vector,
4476                                            queue >> 1,
4477                                            ((queue & 0x1) << 4) +
4478                                            8 * direction);
4479         }
4480 }
4481
4482 /* Sets up the hardware to generate MSI-X interrupts properly
4483  * @hw
4484  *  board private structure
4485  */
4486 static void
4487 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
4488 {
4489         int queue_id;
4490         uint32_t tmpval, regval, intr_mask;
4491         struct e1000_hw *hw =
4492                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4493         uint32_t vec = 0;
4494         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4495
4496         /* won't configure msix register if no mapping is done
4497          * between intr vector and event fd
4498          */
4499         if (!rte_intr_dp_is_en(intr_handle))
4500                 return;
4501
4502         /* set interrupt vector for other causes */
4503         if (hw->mac.type == e1000_82575) {
4504                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
4505                 /* enable MSI-X PBA support */
4506                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
4507
4508                 /* Auto-Mask interrupts upon ICR read */
4509                 tmpval |= E1000_CTRL_EXT_EIAME;
4510                 tmpval |= E1000_CTRL_EXT_IRCA;
4511
4512                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
4513
4514                 /* enable msix_other interrupt */
4515                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
4516                 regval = E1000_READ_REG(hw, E1000_EIAC);
4517                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
4518                 regval = E1000_READ_REG(hw, E1000_EIAM);
4519                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
4520         } else if ((hw->mac.type == e1000_82576) ||
4521                         (hw->mac.type == e1000_82580) ||
4522                         (hw->mac.type == e1000_i350) ||
4523                         (hw->mac.type == e1000_i354) ||
4524                         (hw->mac.type == e1000_i210) ||
4525                         (hw->mac.type == e1000_i211)) {
4526                 /* turn on MSI-X capability first */
4527                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
4528                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
4529                                         E1000_GPIE_NSICR);
4530
4531                 intr_mask = (1 << intr_handle->max_intr) - 1;
4532                 regval = E1000_READ_REG(hw, E1000_EIAC);
4533                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
4534
4535                 /* enable msix_other interrupt */
4536                 regval = E1000_READ_REG(hw, E1000_EIMS);
4537                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
4538                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
4539                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
4540         }
4541
4542         /* use EIAM to auto-mask when MSI-X interrupt
4543          * is asserted, this saves a register write for every interrupt
4544          */
4545         intr_mask = (1 << intr_handle->nb_efd) - 1;
4546         regval = E1000_READ_REG(hw, E1000_EIAM);
4547         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
4548
4549         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
4550                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
4551                 intr_handle->intr_vec[queue_id] = vec;
4552                 if (vec < intr_handle->nb_efd - 1)
4553                         vec++;
4554         }
4555
4556         E1000_WRITE_FLUSH(hw);
4557 }
4558
4559 PMD_REGISTER_DRIVER(pmd_igb_drv);
4560 PMD_REGISTER_DRIVER(pmd_igbvf_drv);