drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_malloc.h>
  24 #include <rte_dev.h>
  25
  26 #include "e1000_logs.h"
  27 #include "base/e1000_api.h"
  28 #include "e1000_ethdev.h"
  29 #include "igb_regs.h"
  30
  31 /*
  32  * Default values for port configuration
  33  */
  34 #define IGB_DEFAULT_RX_FREE_THRESH  32
  35
  36 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  37 #define IGB_DEFAULT_RX_HTHRESH      8
  38 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  39
  40 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  41 #define IGB_DEFAULT_TX_HTHRESH      1
  42 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  43
  44 #define IGB_HKEY_MAX_INDEX 10
  45
  46 /* Bit shift and mask */
  47 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  48 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  49 #define IGB_8_BIT_WIDTH  CHAR_BIT
  50 #define IGB_8_BIT_MASK   UINT8_MAX
  51
  52 /* Additional timesync values. */
  53 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  54 #define E1000_ETQF_FILTER_1588       3
  55 #define IGB_82576_TSYNC_SHIFT        16
  56 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  57 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  58 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  59
  60 #define E1000_VTIVAR_MISC                0x01740
  61 #define E1000_VTIVAR_MISC_MASK           0xFF
  62 #define E1000_VTIVAR_VALID               0x80
  63 #define E1000_VTIVAR_MISC_MAILBOX        0
  64 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  65
  66 /* External VLAN Enable bit mask */
  67 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  68
  69 /* External VLAN Ether Type bit mask and shift */
  70 #define E1000_VET_VET_EXT            0xFFFF0000
  71 #define E1000_VET_VET_EXT_SHIFT      16
  72
  73 static int  eth_igb_configure(struct rte_eth_dev *dev);
  74 static int  eth_igb_start(struct rte_eth_dev *dev);
  75 static void eth_igb_stop(struct rte_eth_dev *dev);
  76 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  77 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  78 static void eth_igb_close(struct rte_eth_dev *dev);
  79 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  80 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  81 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  82 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  83 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  84                                 int wait_to_complete);
  85 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  86                                 struct rte_eth_stats *rte_stats);
  87 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  88                               struct rte_eth_xstat *xstats, unsigned n);
  89 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  90                 const uint64_t *ids,
  91                 uint64_t *values, unsigned int n);
  92 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  93                                     struct rte_eth_xstat_name *xstats_names,
  94                                     unsigned int size);
  95 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  96                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
  97                 unsigned int limit);
  98 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
  99 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 100 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 101                                    char *fw_version, size_t fw_size);
 102 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 103                               struct rte_eth_dev_info *dev_info);
 104 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 105 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_fc_conf *fc_conf);
 109 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 110                                 struct rte_eth_fc_conf *fc_conf);
 111 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 112 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 113 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 115                                     struct rte_intr_handle *handle);
 116 static void eth_igb_interrupt_handler(void *param);
 117 static int  igb_hardware_init(struct e1000_hw *hw);
 118 static void igb_hw_control_acquire(struct e1000_hw *hw);
 119 static void igb_hw_control_release(struct e1000_hw *hw);
 120 static void igb_init_manageability(struct e1000_hw *hw);
 121 static void igb_release_manageability(struct e1000_hw *hw);
 122
 123 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 124
 125 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 126                 uint16_t vlan_id, int on);
 127 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 128                                  enum rte_vlan_type vlan_type,
 129                                  uint16_t tpid_id);
 130 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 131
 132 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 133 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 138
 139 static int eth_igb_led_on(struct rte_eth_dev *dev);
 140 static int eth_igb_led_off(struct rte_eth_dev *dev);
 141
 142 static void igb_intr_disable(struct e1000_hw *hw);
 143 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 144 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 145                            struct ether_addr *mac_addr,
 146                            uint32_t index, uint32_t pool);
 147 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 148 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 149                 struct ether_addr *addr);
 150
 151 static void igbvf_intr_disable(struct e1000_hw *hw);
 152 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 153 static int igbvf_dev_start(struct rte_eth_dev *dev);
 154 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 155 static void igbvf_dev_close(struct rte_eth_dev *dev);
 156 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 158 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 160 static int eth_igbvf_link_update(struct e1000_hw *hw);
 161 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 162                                 struct rte_eth_stats *rte_stats);
 163 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 164                                 struct rte_eth_xstat *xstats, unsigned n);
 165 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 166                                       struct rte_eth_xstat_name *xstats_names,
 167                                       unsigned limit);
 168 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 169 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 170                 uint16_t vlan_id, int on);
 171 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 172 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 173 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 174                 struct ether_addr *addr);
 175 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 176 static int igbvf_get_regs(struct rte_eth_dev *dev,
 177                 struct rte_dev_reg_info *regs);
 178
 179 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 180                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 181                                    uint16_t reta_size);
 182 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 183                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 184                                   uint16_t reta_size);
 185
 186 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 187                         struct rte_eth_syn_filter *filter);
 188 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 189                         enum rte_filter_op filter_op,
 190                         void *arg);
 191 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 192                         struct rte_eth_ntuple_filter *ntuple_filter);
 193 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 194                         struct rte_eth_ntuple_filter *ntuple_filter);
 195 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 196                         struct rte_eth_flex_filter *filter);
 197 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 198                         enum rte_filter_op filter_op,
 199                         void *arg);
 200 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 201                         struct rte_eth_ntuple_filter *ntuple_filter);
 202 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 203                         struct rte_eth_ntuple_filter *ntuple_filter);
 204 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 205                         struct rte_eth_ntuple_filter *filter);
 206 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 207                                 enum rte_filter_op filter_op,
 208                                 void *arg);
 209 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 213                         struct rte_eth_ethertype_filter *filter);
 214 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 215                      enum rte_filter_type filter_type,
 216                      enum rte_filter_op filter_op,
 217                      void *arg);
 218 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 219 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 220                 struct rte_dev_reg_info *regs);
 221 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 222 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 223                 struct rte_dev_eeprom_info *eeprom);
 224 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 225                 struct rte_dev_eeprom_info *eeprom);
 226 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 227                                     struct ether_addr *mc_addr_set,
 228                                     uint32_t nb_mc_addr);
 229 static int igb_timesync_enable(struct rte_eth_dev *dev);
 230 static int igb_timesync_disable(struct rte_eth_dev *dev);
 231 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 232                                           struct timespec *timestamp,
 233                                           uint32_t flags);
 234 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 235                                           struct timespec *timestamp);
 236 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 237 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 238                                   struct timespec *timestamp);
 239 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 240                                    const struct timespec *timestamp);
 241 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 242                                         uint16_t queue_id);
 243 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 244                                          uint16_t queue_id);
 245 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 246                                        uint8_t queue, uint8_t msix_vector);
 247 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 248                                uint8_t index, uint8_t offset);
 249 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 250 static void eth_igbvf_interrupt_handler(void *param);
 251 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 252 static int igb_filter_restore(struct rte_eth_dev *dev);
 253
 254 /*
 255  * Define VF Stats MACRO for Non "cleared on read" register
 256  */
 257 #define UPDATE_VF_STAT(reg, last, cur)            \
 258 {                                                 \
 259         u32 latest = E1000_READ_REG(hw, reg);     \
 260         cur += (latest - last) & UINT_MAX;        \
 261         last = latest;                            \
 262 }
 263
 264 #define IGB_FC_PAUSE_TIME 0x0680
 265 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 266 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 267
 268 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 269
 270 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 271
 272 /*
 273  * The set of PCI devices this driver supports
 274  */
 275 static const struct rte_pci_id pci_id_igb_map[] = {
 276         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 284
 285         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 288
 289         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 295
 296         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 317         { .vendor_id = 0, /* sentinel */ },
 318 };
 319
 320 /*
 321  * The set of PCI devices this driver supports (for 82576&I350 VF)
 322  */
 323 static const struct rte_pci_id pci_id_igbvf_map[] = {
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 328         { .vendor_id = 0, /* sentinel */ },
 329 };
 330
 331 static const struct rte_eth_desc_lim rx_desc_lim = {
 332         .nb_max = E1000_MAX_RING_DESC,
 333         .nb_min = E1000_MIN_RING_DESC,
 334         .nb_align = IGB_RXD_ALIGN,
 335 };
 336
 337 static const struct rte_eth_desc_lim tx_desc_lim = {
 338         .nb_max = E1000_MAX_RING_DESC,
 339         .nb_min = E1000_MIN_RING_DESC,
 340         .nb_align = IGB_RXD_ALIGN,
 341         .nb_seg_max = IGB_TX_MAX_SEG,
 342         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 343 };
 344
 345 static const struct eth_dev_ops eth_igb_ops = {
 346         .dev_configure        = eth_igb_configure,
 347         .dev_start            = eth_igb_start,
 348         .dev_stop             = eth_igb_stop,
 349         .dev_set_link_up      = eth_igb_dev_set_link_up,
 350         .dev_set_link_down    = eth_igb_dev_set_link_down,
 351         .dev_close            = eth_igb_close,
 352         .promiscuous_enable   = eth_igb_promiscuous_enable,
 353         .promiscuous_disable  = eth_igb_promiscuous_disable,
 354         .allmulticast_enable  = eth_igb_allmulticast_enable,
 355         .allmulticast_disable = eth_igb_allmulticast_disable,
 356         .link_update          = eth_igb_link_update,
 357         .stats_get            = eth_igb_stats_get,
 358         .xstats_get           = eth_igb_xstats_get,
 359         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 360         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 361         .xstats_get_names     = eth_igb_xstats_get_names,
 362         .stats_reset          = eth_igb_stats_reset,
 363         .xstats_reset         = eth_igb_xstats_reset,
 364         .fw_version_get       = eth_igb_fw_version_get,
 365         .dev_infos_get        = eth_igb_infos_get,
 366         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 367         .mtu_set              = eth_igb_mtu_set,
 368         .vlan_filter_set      = eth_igb_vlan_filter_set,
 369         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 370         .vlan_offload_set     = eth_igb_vlan_offload_set,
 371         .rx_queue_setup       = eth_igb_rx_queue_setup,
 372         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 373         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 374         .rx_queue_release     = eth_igb_rx_queue_release,
 375         .rx_queue_count       = eth_igb_rx_queue_count,
 376         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 377         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 378         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 379         .tx_queue_setup       = eth_igb_tx_queue_setup,
 380         .tx_queue_release     = eth_igb_tx_queue_release,
 381         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 382         .dev_led_on           = eth_igb_led_on,
 383         .dev_led_off          = eth_igb_led_off,
 384         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 385         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 386         .mac_addr_add         = eth_igb_rar_set,
 387         .mac_addr_remove      = eth_igb_rar_clear,
 388         .mac_addr_set         = eth_igb_default_mac_addr_set,
 389         .reta_update          = eth_igb_rss_reta_update,
 390         .reta_query           = eth_igb_rss_reta_query,
 391         .rss_hash_update      = eth_igb_rss_hash_update,
 392         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 393         .filter_ctrl          = eth_igb_filter_ctrl,
 394         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 395         .rxq_info_get         = igb_rxq_info_get,
 396         .txq_info_get         = igb_txq_info_get,
 397         .timesync_enable      = igb_timesync_enable,
 398         .timesync_disable     = igb_timesync_disable,
 399         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 400         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 401         .get_reg              = eth_igb_get_regs,
 402         .get_eeprom_length    = eth_igb_get_eeprom_length,
 403         .get_eeprom           = eth_igb_get_eeprom,
 404         .set_eeprom           = eth_igb_set_eeprom,
 405         .timesync_adjust_time = igb_timesync_adjust_time,
 406         .timesync_read_time   = igb_timesync_read_time,
 407         .timesync_write_time  = igb_timesync_write_time,
 408 };
 409
 410 /*
 411  * dev_ops for virtual function, bare necessities for basic vf
 412  * operation have been implemented
 413  */
 414 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 415         .dev_configure        = igbvf_dev_configure,
 416         .dev_start            = igbvf_dev_start,
 417         .dev_stop             = igbvf_dev_stop,
 418         .dev_close            = igbvf_dev_close,
 419         .promiscuous_enable   = igbvf_promiscuous_enable,
 420         .promiscuous_disable  = igbvf_promiscuous_disable,
 421         .allmulticast_enable  = igbvf_allmulticast_enable,
 422         .allmulticast_disable = igbvf_allmulticast_disable,
 423         .link_update          = eth_igb_link_update,
 424         .stats_get            = eth_igbvf_stats_get,
 425         .xstats_get           = eth_igbvf_xstats_get,
 426         .xstats_get_names     = eth_igbvf_xstats_get_names,
 427         .stats_reset          = eth_igbvf_stats_reset,
 428         .xstats_reset         = eth_igbvf_stats_reset,
 429         .vlan_filter_set      = igbvf_vlan_filter_set,
 430         .dev_infos_get        = eth_igbvf_infos_get,
 431         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 432         .rx_queue_setup       = eth_igb_rx_queue_setup,
 433         .rx_queue_release     = eth_igb_rx_queue_release,
 434         .tx_queue_setup       = eth_igb_tx_queue_setup,
 435         .tx_queue_release     = eth_igb_tx_queue_release,
 436         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 437         .rxq_info_get         = igb_rxq_info_get,
 438         .txq_info_get         = igb_txq_info_get,
 439         .mac_addr_set         = igbvf_default_mac_addr_set,
 440         .get_reg              = igbvf_get_regs,
 441 };
 442
 443 /* store statistics names and its offset in stats structure */
 444 struct rte_igb_xstats_name_off {
 445         char name[RTE_ETH_XSTATS_NAME_SIZE];
 446         unsigned offset;
 447 };
 448
 449 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 450         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 451         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 452         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 453         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 454         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 455         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 456         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 457                 ecol)},
 458         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 459         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 460         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 461         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 462         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 463         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 464         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 465         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 466         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 467         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 468         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 469                 fcruc)},
 470         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 471         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 472         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 473         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 474         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 475                 prc1023)},
 476         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 477                 prc1522)},
 478         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 479         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 480         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 481         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 482         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 483         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 484         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 485         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 486         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 487         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 488         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 489         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 490         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 491         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 492         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 493         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 494         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 495         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 496                 ptc1023)},
 497         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 498                 ptc1522)},
 499         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 500         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 501         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 502         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 503         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 504         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 505         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 506
 507         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 508 };
 509
 510 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 511                 sizeof(rte_igb_stats_strings[0]))
 512
 513 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 514         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 515         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 516         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 517         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 518         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 519 };
 520
 521 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 522                 sizeof(rte_igbvf_stats_strings[0]))
 523
 524
 525 static inline void
 526 igb_intr_enable(struct rte_eth_dev *dev)
 527 {
 528         struct e1000_interrupt *intr =
 529                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530         struct e1000_hw *hw =
 531                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 534         E1000_WRITE_FLUSH(hw);
 535 }
 536
 537 static void
 538 igb_intr_disable(struct e1000_hw *hw)
 539 {
 540         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 541         E1000_WRITE_FLUSH(hw);
 542 }
 543
 544 static inline void
 545 igbvf_intr_enable(struct rte_eth_dev *dev)
 546 {
 547         struct e1000_hw *hw =
 548                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 549
 550         /* only for mailbox */
 551         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 552         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 553         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 554         E1000_WRITE_FLUSH(hw);
 555 }
 556
 557 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 558 static void
 559 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 560 {
 561         uint32_t tmp = 0;
 562
 563         /* mailbox */
 564         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 565         tmp |= E1000_VTIVAR_VALID;
 566         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 567 }
 568
 569 static void
 570 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 571 {
 572         struct e1000_hw *hw =
 573                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 574
 575         /* Configure VF other cause ivar */
 576         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 577 }
 578
 579 static inline int32_t
 580 igb_pf_reset_hw(struct e1000_hw *hw)
 581 {
 582         uint32_t ctrl_ext;
 583         int32_t status;
 584
 585         status = e1000_reset_hw(hw);
 586
 587         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 588         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 589         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 590         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 591         E1000_WRITE_FLUSH(hw);
 592
 593         return status;
 594 }
 595
 596 static void
 597 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 598 {
 599         struct e1000_hw *hw =
 600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 601
 602
 603         hw->vendor_id = pci_dev->id.vendor_id;
 604         hw->device_id = pci_dev->id.device_id;
 605         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 606         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 607
 608         e1000_set_mac_type(hw);
 609
 610         /* need to check if it is a vf device below */
 611 }
 612
 613 static int
 614 igb_reset_swfw_lock(struct e1000_hw *hw)
 615 {
 616         int ret_val;
 617
 618         /*
 619          * Do mac ops initialization manually here, since we will need
 620          * some function pointers set by this call.
 621          */
 622         ret_val = e1000_init_mac_params(hw);
 623         if (ret_val)
 624                 return ret_val;
 625
 626         /*
 627          * SMBI lock should not fail in this early stage. If this is the case,
 628          * it is due to an improper exit of the application.
 629          * So force the release of the faulty lock.
 630          */
 631         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 632                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 633         }
 634         e1000_put_hw_semaphore_generic(hw);
 635
 636         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 637                 uint16_t mask;
 638
 639                 /*
 640                  * Phy lock should not fail in this early stage. If this is the case,
 641                  * it is due to an improper exit of the application.
 642                  * So force the release of the faulty lock.
 643                  */
 644                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 645                 if (hw->bus.func > E1000_FUNC_1)
 646                         mask <<= 2;
 647                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 648                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 649                                     hw->bus.func);
 650                 }
 651                 hw->mac.ops.release_swfw_sync(hw, mask);
 652
 653                 /*
 654                  * This one is more tricky since it is common to all ports; but
 655                  * swfw_sync retries last long enough (1s) to be almost sure that if
 656                  * lock can not be taken it is due to an improper lock of the
 657                  * semaphore.
 658                  */
 659                 mask = E1000_SWFW_EEP_SM;
 660                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 661                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 662                 }
 663                 hw->mac.ops.release_swfw_sync(hw, mask);
 664         }
 665
 666         return E1000_SUCCESS;
 667 }
 668
 669 /* Remove all ntuple filters of the device */
 670 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 671 {
 672         struct e1000_filter_info *filter_info =
 673                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 674         struct e1000_5tuple_filter *p_5tuple;
 675         struct e1000_2tuple_filter *p_2tuple;
 676
 677         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 678                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 679                         p_5tuple, entries);
 680                         rte_free(p_5tuple);
 681         }
 682         filter_info->fivetuple_mask = 0;
 683         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 684                 TAILQ_REMOVE(&filter_info->twotuple_list,
 685                         p_2tuple, entries);
 686                         rte_free(p_2tuple);
 687         }
 688         filter_info->twotuple_mask = 0;
 689
 690         return 0;
 691 }
 692
 693 /* Remove all flex filters of the device */
 694 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 695 {
 696         struct e1000_filter_info *filter_info =
 697                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 698         struct e1000_flex_filter *p_flex;
 699
 700         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 701                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 702                 rte_free(p_flex);
 703         }
 704         filter_info->flex_mask = 0;
 705
 706         return 0;
 707 }
 708
 709 static int
 710 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 711 {
 712         int error = 0;
 713         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 714         struct e1000_hw *hw =
 715                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 716         struct e1000_vfta * shadow_vfta =
 717                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 718         struct e1000_filter_info *filter_info =
 719                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 720         struct e1000_adapter *adapter =
 721                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 722
 723         uint32_t ctrl_ext;
 724
 725         eth_dev->dev_ops = &eth_igb_ops;
 726         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 727         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 728         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 729
 730         /* for secondary processes, we don't initialise any further as primary
 731          * has already done this work. Only check we don't need a different
 732          * RX function */
 733         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 734                 if (eth_dev->data->scattered_rx)
 735                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 736                 return 0;
 737         }
 738
 739         rte_eth_copy_pci_info(eth_dev, pci_dev);
 740
 741         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 742
 743         igb_identify_hardware(eth_dev, pci_dev);
 744         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 745                 error = -EIO;
 746                 goto err_late;
 747         }
 748
 749         e1000_get_bus_info(hw);
 750
 751         /* Reset any pending lock */
 752         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 753                 error = -EIO;
 754                 goto err_late;
 755         }
 756
 757         /* Finish initialization */
 758         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 759                 error = -EIO;
 760                 goto err_late;
 761         }
 762
 763         hw->mac.autoneg = 1;
 764         hw->phy.autoneg_wait_to_complete = 0;
 765         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 766
 767         /* Copper options */
 768         if (hw->phy.media_type == e1000_media_type_copper) {
 769                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 770                 hw->phy.disable_polarity_correction = 0;
 771                 hw->phy.ms_type = e1000_ms_hw_default;
 772         }
 773
 774         /*
 775          * Start from a known state, this is important in reading the nvm
 776          * and mac from that.
 777          */
 778         igb_pf_reset_hw(hw);
 779
 780         /* Make sure we have a good EEPROM before we read from it */
 781         if (e1000_validate_nvm_checksum(hw) < 0) {
 782                 /*
 783                  * Some PCI-E parts fail the first check due to
 784                  * the link being in sleep state, call it again,
 785                  * if it fails a second time its a real issue.
 786                  */
 787                 if (e1000_validate_nvm_checksum(hw) < 0) {
 788                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 789                         error = -EIO;
 790                         goto err_late;
 791                 }
 792         }
 793
 794         /* Read the permanent MAC address out of the EEPROM */
 795         if (e1000_read_mac_addr(hw) != 0) {
 796                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         /* Allocate memory for storing MAC addresses */
 802         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 803                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 804         if (eth_dev->data->mac_addrs == NULL) {
 805                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 806                                                 "store MAC addresses",
 807                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 808                 error = -ENOMEM;
 809                 goto err_late;
 810         }
 811
 812         /* Copy the permanent MAC address */
 813         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 814
 815         /* initialize the vfta */
 816         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 817
 818         /* Now initialize the hardware */
 819         if (igb_hardware_init(hw) != 0) {
 820                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 821                 rte_free(eth_dev->data->mac_addrs);
 822                 eth_dev->data->mac_addrs = NULL;
 823                 error = -ENODEV;
 824                 goto err_late;
 825         }
 826         hw->mac.get_link_status = 1;
 827         adapter->stopped = 0;
 828
 829         /* Indicate SOL/IDER usage */
 830         if (e1000_check_reset_block(hw) < 0) {
 831                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 832                                         "SOL/IDER session");
 833         }
 834
 835         /* initialize PF if max_vfs not zero */
 836         igb_pf_host_init(eth_dev);
 837
 838         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 839         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 840         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 841         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 842         E1000_WRITE_FLUSH(hw);
 843
 844         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 845                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 846                      pci_dev->id.device_id);
 847
 848         rte_intr_callback_register(&pci_dev->intr_handle,
 849                                    eth_igb_interrupt_handler,
 850                                    (void *)eth_dev);
 851
 852         /* enable uio/vfio intr/eventfd mapping */
 853         rte_intr_enable(&pci_dev->intr_handle);
 854
 855         /* enable support intr */
 856         igb_intr_enable(eth_dev);
 857
 858         /* initialize filter info */
 859         memset(filter_info, 0,
 860                sizeof(struct e1000_filter_info));
 861
 862         TAILQ_INIT(&filter_info->flex_list);
 863         TAILQ_INIT(&filter_info->twotuple_list);
 864         TAILQ_INIT(&filter_info->fivetuple_list);
 865
 866         TAILQ_INIT(&igb_filter_ntuple_list);
 867         TAILQ_INIT(&igb_filter_ethertype_list);
 868         TAILQ_INIT(&igb_filter_syn_list);
 869         TAILQ_INIT(&igb_filter_flex_list);
 870         TAILQ_INIT(&igb_filter_rss_list);
 871         TAILQ_INIT(&igb_flow_list);
 872
 873         return 0;
 874
 875 err_late:
 876         igb_hw_control_release(hw);
 877
 878         return error;
 879 }
 880
 881 static int
 882 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 883 {
 884         struct rte_pci_device *pci_dev;
 885         struct rte_intr_handle *intr_handle;
 886         struct e1000_hw *hw;
 887         struct e1000_adapter *adapter =
 888                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 889         struct e1000_filter_info *filter_info =
 890                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 891
 892         PMD_INIT_FUNC_TRACE();
 893
 894         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 895                 return -EPERM;
 896
 897         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 898         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 899         intr_handle = &pci_dev->intr_handle;
 900
 901         if (adapter->stopped == 0)
 902                 eth_igb_close(eth_dev);
 903
 904         eth_dev->dev_ops = NULL;
 905         eth_dev->rx_pkt_burst = NULL;
 906         eth_dev->tx_pkt_burst = NULL;
 907
 908         /* Reset any pending lock */
 909         igb_reset_swfw_lock(hw);
 910
 911         rte_free(eth_dev->data->mac_addrs);
 912         eth_dev->data->mac_addrs = NULL;
 913
 914         /* uninitialize PF if max_vfs not zero */
 915         igb_pf_host_uninit(eth_dev);
 916
 917         /* disable uio intr before callback unregister */
 918         rte_intr_disable(intr_handle);
 919         rte_intr_callback_unregister(intr_handle,
 920                                      eth_igb_interrupt_handler, eth_dev);
 921
 922         /* clear the SYN filter info */
 923         filter_info->syn_info = 0;
 924
 925         /* clear the ethertype filters info */
 926         filter_info->ethertype_mask = 0;
 927         memset(filter_info->ethertype_filters, 0,
 928                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 929
 930         /* clear the rss filter info */
 931         memset(&filter_info->rss_info, 0,
 932                 sizeof(struct igb_rte_flow_rss_conf));
 933
 934         /* remove all ntuple filters of the device */
 935         igb_ntuple_filter_uninit(eth_dev);
 936
 937         /* remove all flex filters of the device */
 938         igb_flex_filter_uninit(eth_dev);
 939
 940         /* clear all the filters list */
 941         igb_filterlist_flush(eth_dev);
 942
 943         return 0;
 944 }
 945
 946 /*
 947  * Virtual Function device init
 948  */
 949 static int
 950 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
 951 {
 952         struct rte_pci_device *pci_dev;
 953         struct rte_intr_handle *intr_handle;
 954         struct e1000_adapter *adapter =
 955                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 956         struct e1000_hw *hw =
 957                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 958         int diag;
 959         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         eth_dev->dev_ops = &igbvf_eth_dev_ops;
 964         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 965         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 966         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 967
 968         /* for secondary processes, we don't initialise any further as primary
 969          * has already done this work. Only check we don't need a different
 970          * RX function */
 971         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 972                 if (eth_dev->data->scattered_rx)
 973                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 974                 return 0;
 975         }
 976
 977         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 978         rte_eth_copy_pci_info(eth_dev, pci_dev);
 979
 980         hw->device_id = pci_dev->id.device_id;
 981         hw->vendor_id = pci_dev->id.vendor_id;
 982         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 983         adapter->stopped = 0;
 984
 985         /* Initialize the shared code (base driver) */
 986         diag = e1000_setup_init_funcs(hw, TRUE);
 987         if (diag != 0) {
 988                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
 989                         diag);
 990                 return -EIO;
 991         }
 992
 993         /* init_mailbox_params */
 994         hw->mbx.ops.init_params(hw);
 995
 996         /* Disable the interrupts for VF */
 997         igbvf_intr_disable(hw);
 998
 999         diag = hw->mac.ops.reset_hw(hw);
1000
1001         /* Allocate memory for storing MAC addresses */
1002         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1003                 hw->mac.rar_entry_count, 0);
1004         if (eth_dev->data->mac_addrs == NULL) {
1005                 PMD_INIT_LOG(ERR,
1006                         "Failed to allocate %d bytes needed to store MAC "
1007                         "addresses",
1008                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1009                 return -ENOMEM;
1010         }
1011
1012         /* Generate a random MAC address, if none was assigned by PF. */
1013         if (is_zero_ether_addr(perm_addr)) {
1014                 eth_random_addr(perm_addr->addr_bytes);
1015                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1016                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1017                              "%02x:%02x:%02x:%02x:%02x:%02x",
1018                              perm_addr->addr_bytes[0],
1019                              perm_addr->addr_bytes[1],
1020                              perm_addr->addr_bytes[2],
1021                              perm_addr->addr_bytes[3],
1022                              perm_addr->addr_bytes[4],
1023                              perm_addr->addr_bytes[5]);
1024         }
1025
1026         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1027         if (diag) {
1028                 rte_free(eth_dev->data->mac_addrs);
1029                 eth_dev->data->mac_addrs = NULL;
1030                 return diag;
1031         }
1032         /* Copy the permanent MAC address */
1033         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1034                         &eth_dev->data->mac_addrs[0]);
1035
1036         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1037                      "mac.type=%s",
1038                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1039                      pci_dev->id.device_id, "igb_mac_82576_vf");
1040
1041         intr_handle = &pci_dev->intr_handle;
1042         rte_intr_callback_register(intr_handle,
1043                                    eth_igbvf_interrupt_handler, eth_dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1050 {
1051         struct e1000_adapter *adapter =
1052                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054
1055         PMD_INIT_FUNC_TRACE();
1056
1057         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1058                 return -EPERM;
1059
1060         if (adapter->stopped == 0)
1061                 igbvf_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         rte_free(eth_dev->data->mac_addrs);
1068         eth_dev->data->mac_addrs = NULL;
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&pci_dev->intr_handle);
1072         rte_intr_callback_unregister(&pci_dev->intr_handle,
1073                                      eth_igbvf_interrupt_handler,
1074                                      (void *)eth_dev);
1075
1076         return 0;
1077 }
1078
1079 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1080         struct rte_pci_device *pci_dev)
1081 {
1082         return rte_eth_dev_pci_generic_probe(pci_dev,
1083                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1084 }
1085
1086 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1087 {
1088         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1089 }
1090
1091 static struct rte_pci_driver rte_igb_pmd = {
1092         .id_table = pci_id_igb_map,
1093         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1094                      RTE_PCI_DRV_IOVA_AS_VA,
1095         .probe = eth_igb_pci_probe,
1096         .remove = eth_igb_pci_remove,
1097 };
1098
1099
1100 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1101         struct rte_pci_device *pci_dev)
1102 {
1103         return rte_eth_dev_pci_generic_probe(pci_dev,
1104                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1105 }
1106
1107 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1108 {
1109         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1110 }
1111
1112 /*
1113  * virtual function driver struct
1114  */
1115 static struct rte_pci_driver rte_igbvf_pmd = {
1116         .id_table = pci_id_igbvf_map,
1117         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1118         .probe = eth_igbvf_pci_probe,
1119         .remove = eth_igbvf_pci_remove,
1120 };
1121
1122 static void
1123 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1124 {
1125         struct e1000_hw *hw =
1126                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1128         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1129         rctl |= E1000_RCTL_VFE;
1130         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1131 }
1132
1133 static int
1134 igb_check_mq_mode(struct rte_eth_dev *dev)
1135 {
1136         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1137         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1138         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1139         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1140
1141         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1142             tx_mq_mode == ETH_MQ_TX_DCB ||
1143             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1144                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1145                 return -EINVAL;
1146         }
1147         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1148                 /* Check multi-queue mode.
1149                  * To no break software we accept ETH_MQ_RX_NONE as this might
1150                  * be used to turn off VLAN filter.
1151                  */
1152
1153                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1154                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1155                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1156                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1157                 } else {
1158                         /* Only support one queue on VFs.
1159                          * RSS together with SRIOV is not supported.
1160                          */
1161                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1162                                         " wrong mq_mode rx %d.",
1163                                         rx_mq_mode);
1164                         return -EINVAL;
1165                 }
1166                 /* TX mode is not used here, so mode might be ignored.*/
1167                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1168                         /* SRIOV only works in VMDq enable mode */
1169                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1170                                         " TX mode %d is not supported. "
1171                                         " Driver will behave as %d mode.",
1172                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1173                 }
1174
1175                 /* check valid queue number */
1176                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1177                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1178                                         " only support one queue on VFs.");
1179                         return -EINVAL;
1180                 }
1181         } else {
1182                 /* To no break software that set invalid mode, only display
1183                  * warning if invalid mode is used.
1184                  */
1185                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1186                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1187                     rx_mq_mode != ETH_MQ_RX_RSS) {
1188                         /* RSS together with VMDq not supported*/
1189                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1190                                      rx_mq_mode);
1191                         return -EINVAL;
1192                 }
1193
1194                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1195                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1196                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1197                                         " Due to txmode is meaningless in this"
1198                                         " driver, just ignore.",
1199                                         tx_mq_mode);
1200                 }
1201         }
1202         return 0;
1203 }
1204
1205 static int
1206 eth_igb_configure(struct rte_eth_dev *dev)
1207 {
1208         struct e1000_interrupt *intr =
1209                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1210         int ret;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         /* multipe queue mode checking */
1215         ret  = igb_check_mq_mode(dev);
1216         if (ret != 0) {
1217                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1218                             ret);
1219                 return ret;
1220         }
1221
1222         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1223         PMD_INIT_FUNC_TRACE();
1224
1225         return 0;
1226 }
1227
1228 static void
1229 eth_igb_rxtx_control(struct rte_eth_dev *dev,
1230                      bool enable)
1231 {
1232         struct e1000_hw *hw =
1233                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t tctl, rctl;
1235
1236         tctl = E1000_READ_REG(hw, E1000_TCTL);
1237         rctl = E1000_READ_REG(hw, E1000_RCTL);
1238
1239         if (enable) {
1240                 /* enable Tx/Rx */
1241                 tctl |= E1000_TCTL_EN;
1242                 rctl |= E1000_RCTL_EN;
1243         } else {
1244                 /* disable Tx/Rx */
1245                 tctl &= ~E1000_TCTL_EN;
1246                 rctl &= ~E1000_RCTL_EN;
1247         }
1248         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1249         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1250         E1000_WRITE_FLUSH(hw);
1251 }
1252
1253 static int
1254 eth_igb_start(struct rte_eth_dev *dev)
1255 {
1256         struct e1000_hw *hw =
1257                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1258         struct e1000_adapter *adapter =
1259                 E1000_DEV_PRIVATE(dev->data->dev_private);
1260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1262         int ret, mask;
1263         uint32_t intr_vector = 0;
1264         uint32_t ctrl_ext;
1265         uint32_t *speeds;
1266         int num_speeds;
1267         bool autoneg;
1268
1269         PMD_INIT_FUNC_TRACE();
1270
1271         /* disable uio/vfio intr/eventfd mapping */
1272         rte_intr_disable(intr_handle);
1273
1274         /* Power up the phy. Needed to make the link go Up */
1275         eth_igb_dev_set_link_up(dev);
1276
1277         /*
1278          * Packet Buffer Allocation (PBA)
1279          * Writing PBA sets the receive portion of the buffer
1280          * the remainder is used for the transmit buffer.
1281          */
1282         if (hw->mac.type == e1000_82575) {
1283                 uint32_t pba;
1284
1285                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1286                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1287         }
1288
1289         /* Put the address into the Receive Address Array */
1290         e1000_rar_set(hw, hw->mac.addr, 0);
1291
1292         /* Initialize the hardware */
1293         if (igb_hardware_init(hw)) {
1294                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1295                 return -EIO;
1296         }
1297         adapter->stopped = 0;
1298
1299         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1300
1301         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1302         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1304         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1305         E1000_WRITE_FLUSH(hw);
1306
1307         /* configure PF module if SRIOV enabled */
1308         igb_pf_host_configure(dev);
1309
1310         /* check and configure queue intr-vector mapping */
1311         if ((rte_intr_cap_multiple(intr_handle) ||
1312              !RTE_ETH_DEV_SRIOV(dev).active) &&
1313             dev->data->dev_conf.intr_conf.rxq != 0) {
1314                 intr_vector = dev->data->nb_rx_queues;
1315                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1316                         return -1;
1317         }
1318
1319         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1320                 intr_handle->intr_vec =
1321                         rte_zmalloc("intr_vec",
1322                                     dev->data->nb_rx_queues * sizeof(int), 0);
1323                 if (intr_handle->intr_vec == NULL) {
1324                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1325                                      " intr_vec", dev->data->nb_rx_queues);
1326                         return -ENOMEM;
1327                 }
1328         }
1329
1330         /* confiugre msix for rx interrupt */
1331         eth_igb_configure_msix_intr(dev);
1332
1333         /* Configure for OS presence */
1334         igb_init_manageability(hw);
1335
1336         eth_igb_tx_init(dev);
1337
1338         /* This can fail when allocating mbufs for descriptor rings */
1339         ret = eth_igb_rx_init(dev);
1340         if (ret) {
1341                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1342                 igb_dev_clear_queues(dev);
1343                 return ret;
1344         }
1345
1346         e1000_clear_hw_cntrs_base_generic(hw);
1347
1348         /*
1349          * VLAN Offload Settings
1350          */
1351         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1352                         ETH_VLAN_EXTEND_MASK;
1353         ret = eth_igb_vlan_offload_set(dev, mask);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1356                 igb_dev_clear_queues(dev);
1357                 return ret;
1358         }
1359
1360         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1361                 /* Enable VLAN filter since VMDq always use VLAN filter */
1362                 igb_vmdq_vlan_hw_filter_enable(dev);
1363         }
1364
1365         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1366                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1367                 (hw->mac.type == e1000_i211)) {
1368                 /* Configure EITR with the maximum possible value (0xFFFF) */
1369                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1370         }
1371
1372         /* Setup link speed and duplex */
1373         speeds = &dev->data->dev_conf.link_speeds;
1374         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1375                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1376                 hw->mac.autoneg = 1;
1377         } else {
1378                 num_speeds = 0;
1379                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1380
1381                 /* Reset */
1382                 hw->phy.autoneg_advertised = 0;
1383
1384                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1385                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1386                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1387                         num_speeds = -1;
1388                         goto error_invalid_config;
1389                 }
1390                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1391                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1392                         num_speeds++;
1393                 }
1394                 if (*speeds & ETH_LINK_SPEED_10M) {
1395                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1396                         num_speeds++;
1397                 }
1398                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1399                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1400                         num_speeds++;
1401                 }
1402                 if (*speeds & ETH_LINK_SPEED_100M) {
1403                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1404                         num_speeds++;
1405                 }
1406                 if (*speeds & ETH_LINK_SPEED_1G) {
1407                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1408                         num_speeds++;
1409                 }
1410                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1411                         goto error_invalid_config;
1412
1413                 /* Set/reset the mac.autoneg based on the link speed,
1414                  * fixed or not
1415                  */
1416                 if (!autoneg) {
1417                         hw->mac.autoneg = 0;
1418                         hw->mac.forced_speed_duplex =
1419                                         hw->phy.autoneg_advertised;
1420                 } else {
1421                         hw->mac.autoneg = 1;
1422                 }
1423         }
1424
1425         e1000_setup_link(hw);
1426
1427         if (rte_intr_allow_others(intr_handle)) {
1428                 /* check if lsc interrupt is enabled */
1429                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1430                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1431                 else
1432                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1433         } else {
1434                 rte_intr_callback_unregister(intr_handle,
1435                                              eth_igb_interrupt_handler,
1436                                              (void *)dev);
1437                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1438                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1439                                      " no intr multiplex");
1440         }
1441
1442         /* check if rxq interrupt is enabled */
1443         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1444             rte_intr_dp_is_en(intr_handle))
1445                 eth_igb_rxq_interrupt_setup(dev);
1446
1447         /* enable uio/vfio intr/eventfd mapping */
1448         rte_intr_enable(intr_handle);
1449
1450         /* resume enabled intr since hw reset */
1451         igb_intr_enable(dev);
1452
1453         /* restore all types filter */
1454         igb_filter_restore(dev);
1455
1456         eth_igb_rxtx_control(dev, true);
1457         eth_igb_link_update(dev, 0);
1458
1459         PMD_INIT_LOG(DEBUG, "<<");
1460
1461         return 0;
1462
1463 error_invalid_config:
1464         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1465                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1466         igb_dev_clear_queues(dev);
1467         return -EINVAL;
1468 }
1469
1470 /*********************************************************************
1471  *
1472  *  This routine disables all traffic on the adapter by issuing a
1473  *  global reset on the MAC.
1474  *
1475  **********************************************************************/
1476 static void
1477 eth_igb_stop(struct rte_eth_dev *dev)
1478 {
1479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1480         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1481         struct rte_eth_link link;
1482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1483
1484         eth_igb_rxtx_control(dev, false);
1485
1486         igb_intr_disable(hw);
1487
1488         /* disable intr eventfd mapping */
1489         rte_intr_disable(intr_handle);
1490
1491         igb_pf_reset_hw(hw);
1492         E1000_WRITE_REG(hw, E1000_WUC, 0);
1493
1494         /* Set bit for Go Link disconnect */
1495         if (hw->mac.type >= e1000_82580) {
1496                 uint32_t phpm_reg;
1497
1498                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1499                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1500                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1501         }
1502
1503         /* Power down the phy. Needed to make the link go Down */
1504         eth_igb_dev_set_link_down(dev);
1505
1506         igb_dev_clear_queues(dev);
1507
1508         /* clear the recorded link status */
1509         memset(&link, 0, sizeof(link));
1510         rte_eth_linkstatus_set(dev, &link);
1511
1512         if (!rte_intr_allow_others(intr_handle))
1513                 /* resume to the default handler */
1514                 rte_intr_callback_register(intr_handle,
1515                                            eth_igb_interrupt_handler,
1516                                            (void *)dev);
1517
1518         /* Clean datapath event and queue/vec mapping */
1519         rte_intr_efd_disable(intr_handle);
1520         if (intr_handle->intr_vec != NULL) {
1521                 rte_free(intr_handle->intr_vec);
1522                 intr_handle->intr_vec = NULL;
1523         }
1524 }
1525
1526 static int
1527 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1528 {
1529         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1530
1531         if (hw->phy.media_type == e1000_media_type_copper)
1532                 e1000_power_up_phy(hw);
1533         else
1534                 e1000_power_up_fiber_serdes_link(hw);
1535
1536         return 0;
1537 }
1538
1539 static int
1540 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1541 {
1542         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543
1544         if (hw->phy.media_type == e1000_media_type_copper)
1545                 e1000_power_down_phy(hw);
1546         else
1547                 e1000_shutdown_fiber_serdes_link(hw);
1548
1549         return 0;
1550 }
1551
1552 static void
1553 eth_igb_close(struct rte_eth_dev *dev)
1554 {
1555         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         struct e1000_adapter *adapter =
1557                 E1000_DEV_PRIVATE(dev->data->dev_private);
1558         struct rte_eth_link link;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561
1562         eth_igb_stop(dev);
1563         adapter->stopped = 1;
1564
1565         e1000_phy_hw_reset(hw);
1566         igb_release_manageability(hw);
1567         igb_hw_control_release(hw);
1568
1569         /* Clear bit for Go Link disconnect */
1570         if (hw->mac.type >= e1000_82580) {
1571                 uint32_t phpm_reg;
1572
1573                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1574                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1575                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1576         }
1577
1578         igb_dev_free_queues(dev);
1579
1580         if (intr_handle->intr_vec) {
1581                 rte_free(intr_handle->intr_vec);
1582                 intr_handle->intr_vec = NULL;
1583         }
1584
1585         memset(&link, 0, sizeof(link));
1586         rte_eth_linkstatus_set(dev, &link);
1587 }
1588
1589 static int
1590 igb_get_rx_buffer_size(struct e1000_hw *hw)
1591 {
1592         uint32_t rx_buf_size;
1593         if (hw->mac.type == e1000_82576) {
1594                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1595         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1596                 /* PBS needs to be translated according to a lookup table */
1597                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1598                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1599                 rx_buf_size = (rx_buf_size << 10);
1600         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1601                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1602         } else {
1603                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1604         }
1605
1606         return rx_buf_size;
1607 }
1608
1609 /*********************************************************************
1610  *
1611  *  Initialize the hardware
1612  *
1613  **********************************************************************/
1614 static int
1615 igb_hardware_init(struct e1000_hw *hw)
1616 {
1617         uint32_t rx_buf_size;
1618         int diag;
1619
1620         /* Let the firmware know the OS is in control */
1621         igb_hw_control_acquire(hw);
1622
1623         /*
1624          * These parameters control the automatic generation (Tx) and
1625          * response (Rx) to Ethernet PAUSE frames.
1626          * - High water mark should allow for at least two standard size (1518)
1627          *   frames to be received after sending an XOFF.
1628          * - Low water mark works best when it is very near the high water mark.
1629          *   This allows the receiver to restart by sending XON when it has
1630          *   drained a bit. Here we use an arbitrary value of 1500 which will
1631          *   restart after one full frame is pulled from the buffer. There
1632          *   could be several smaller frames in the buffer and if so they will
1633          *   not trigger the XON until their total number reduces the buffer
1634          *   by 1500.
1635          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1636          */
1637         rx_buf_size = igb_get_rx_buffer_size(hw);
1638
1639         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1640         hw->fc.low_water = hw->fc.high_water - 1500;
1641         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1642         hw->fc.send_xon = 1;
1643
1644         /* Set Flow control, use the tunable location if sane */
1645         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1646                 hw->fc.requested_mode = igb_fc_setting;
1647         else
1648                 hw->fc.requested_mode = e1000_fc_none;
1649
1650         /* Issue a global reset */
1651         igb_pf_reset_hw(hw);
1652         E1000_WRITE_REG(hw, E1000_WUC, 0);
1653
1654         diag = e1000_init_hw(hw);
1655         if (diag < 0)
1656                 return diag;
1657
1658         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1659         e1000_get_phy_info(hw);
1660         e1000_check_for_link(hw);
1661
1662         return 0;
1663 }
1664
1665 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1666 static void
1667 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1668 {
1669         int pause_frames;
1670
1671         uint64_t old_gprc  = stats->gprc;
1672         uint64_t old_gptc  = stats->gptc;
1673         uint64_t old_tpr   = stats->tpr;
1674         uint64_t old_tpt   = stats->tpt;
1675         uint64_t old_rpthc = stats->rpthc;
1676         uint64_t old_hgptc = stats->hgptc;
1677
1678         if(hw->phy.media_type == e1000_media_type_copper ||
1679             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1680                 stats->symerrs +=
1681                     E1000_READ_REG(hw,E1000_SYMERRS);
1682                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1683         }
1684
1685         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1686         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1687         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1688         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1689
1690         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1691         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1692         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1693         stats->dc += E1000_READ_REG(hw, E1000_DC);
1694         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1695         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1696         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1697         /*
1698         ** For watchdog management we need to know if we have been
1699         ** paused during the last interval, so capture that here.
1700         */
1701         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1702         stats->xoffrxc += pause_frames;
1703         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1704         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1705         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1706         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1707         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1708         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1709         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1710         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1711         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1712         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1713         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1714         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1715
1716         /* For the 64-bit byte counters the low dword must be read first. */
1717         /* Both registers clear on the read of the high dword */
1718
1719         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1720         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1721         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1722         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1723         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1724         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1725         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1726
1727         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1728         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1729         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1730         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1731         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1732
1733         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1734         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1735
1736         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1737         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1738         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1739         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1740         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1741         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1742
1743         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1744         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1745         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1746         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1747         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1748         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1749         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1750         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1751
1752         /* Interrupt Counts */
1753
1754         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1755         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1756         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1757         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1758         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1759         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1760         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1761         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1762         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1763
1764         /* Host to Card Statistics */
1765
1766         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1767         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1768         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1769         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1770         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1771         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1772         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1773         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1774         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1775         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1776         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1777         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1778         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1779         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1780         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1781         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1782
1783         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1784         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1785         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1786         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1787         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1788         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1789 }
1790
1791 static int
1792 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1793 {
1794         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795         struct e1000_hw_stats *stats =
1796                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1797
1798         igb_read_stats_registers(hw, stats);
1799
1800         if (rte_stats == NULL)
1801                 return -EINVAL;
1802
1803         /* Rx Errors */
1804         rte_stats->imissed = stats->mpc;
1805         rte_stats->ierrors = stats->crcerrs +
1806                              stats->rlec + stats->ruc + stats->roc +
1807                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1808
1809         /* Tx Errors */
1810         rte_stats->oerrors = stats->ecol + stats->latecol;
1811
1812         rte_stats->ipackets = stats->gprc;
1813         rte_stats->opackets = stats->gptc;
1814         rte_stats->ibytes   = stats->gorc;
1815         rte_stats->obytes   = stats->gotc;
1816         return 0;
1817 }
1818
1819 static void
1820 eth_igb_stats_reset(struct rte_eth_dev *dev)
1821 {
1822         struct e1000_hw_stats *hw_stats =
1823                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1824
1825         /* HW registers are cleared on read */
1826         eth_igb_stats_get(dev, NULL);
1827
1828         /* Reset software totals */
1829         memset(hw_stats, 0, sizeof(*hw_stats));
1830 }
1831
1832 static void
1833 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1834 {
1835         struct e1000_hw_stats *stats =
1836                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1837
1838         /* HW registers are cleared on read */
1839         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1840
1841         /* Reset software totals */
1842         memset(stats, 0, sizeof(*stats));
1843 }
1844
1845 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1846         struct rte_eth_xstat_name *xstats_names,
1847         __rte_unused unsigned int size)
1848 {
1849         unsigned i;
1850
1851         if (xstats_names == NULL)
1852                 return IGB_NB_XSTATS;
1853
1854         /* Note: limit checked in rte_eth_xstats_names() */
1855
1856         for (i = 0; i < IGB_NB_XSTATS; i++) {
1857                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1858                          "%s", rte_igb_stats_strings[i].name);
1859         }
1860
1861         return IGB_NB_XSTATS;
1862 }
1863
1864 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1865                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1866                 unsigned int limit)
1867 {
1868         unsigned int i;
1869
1870         if (!ids) {
1871                 if (xstats_names == NULL)
1872                         return IGB_NB_XSTATS;
1873
1874                 for (i = 0; i < IGB_NB_XSTATS; i++)
1875                         snprintf(xstats_names[i].name,
1876                                         sizeof(xstats_names[i].name),
1877                                         "%s", rte_igb_stats_strings[i].name);
1878
1879                 return IGB_NB_XSTATS;
1880
1881         } else {
1882                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1883
1884                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1885                                 IGB_NB_XSTATS);
1886
1887                 for (i = 0; i < limit; i++) {
1888                         if (ids[i] >= IGB_NB_XSTATS) {
1889                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1890                                 return -1;
1891                         }
1892                         strcpy(xstats_names[i].name,
1893                                         xstats_names_copy[ids[i]].name);
1894                 }
1895                 return limit;
1896         }
1897 }
1898
1899 static int
1900 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1901                    unsigned n)
1902 {
1903         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct e1000_hw_stats *hw_stats =
1905                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1906         unsigned i;
1907
1908         if (n < IGB_NB_XSTATS)
1909                 return IGB_NB_XSTATS;
1910
1911         igb_read_stats_registers(hw, hw_stats);
1912
1913         /* If this is a reset xstats is NULL, and we have cleared the
1914          * registers by reading them.
1915          */
1916         if (!xstats)
1917                 return 0;
1918
1919         /* Extended stats */
1920         for (i = 0; i < IGB_NB_XSTATS; i++) {
1921                 xstats[i].id = i;
1922                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1923                         rte_igb_stats_strings[i].offset);
1924         }
1925
1926         return IGB_NB_XSTATS;
1927 }
1928
1929 static int
1930 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1931                 uint64_t *values, unsigned int n)
1932 {
1933         unsigned int i;
1934
1935         if (!ids) {
1936                 struct e1000_hw *hw =
1937                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938                 struct e1000_hw_stats *hw_stats =
1939                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1940
1941                 if (n < IGB_NB_XSTATS)
1942                         return IGB_NB_XSTATS;
1943
1944                 igb_read_stats_registers(hw, hw_stats);
1945
1946                 /* If this is a reset xstats is NULL, and we have cleared the
1947                  * registers by reading them.
1948                  */
1949                 if (!values)
1950                         return 0;
1951
1952                 /* Extended stats */
1953                 for (i = 0; i < IGB_NB_XSTATS; i++)
1954                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1955                                         rte_igb_stats_strings[i].offset);
1956
1957                 return IGB_NB_XSTATS;
1958
1959         } else {
1960                 uint64_t values_copy[IGB_NB_XSTATS];
1961
1962                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1963                                 IGB_NB_XSTATS);
1964
1965                 for (i = 0; i < n; i++) {
1966                         if (ids[i] >= IGB_NB_XSTATS) {
1967                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1968                                 return -1;
1969                         }
1970                         values[i] = values_copy[ids[i]];
1971                 }
1972                 return n;
1973         }
1974 }
1975
1976 static void
1977 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
1978 {
1979         /* Good Rx packets, include VF loopback */
1980         UPDATE_VF_STAT(E1000_VFGPRC,
1981             hw_stats->last_gprc, hw_stats->gprc);
1982
1983         /* Good Rx octets, include VF loopback */
1984         UPDATE_VF_STAT(E1000_VFGORC,
1985             hw_stats->last_gorc, hw_stats->gorc);
1986
1987         /* Good Tx packets, include VF loopback */
1988         UPDATE_VF_STAT(E1000_VFGPTC,
1989             hw_stats->last_gptc, hw_stats->gptc);
1990
1991         /* Good Tx octets, include VF loopback */
1992         UPDATE_VF_STAT(E1000_VFGOTC,
1993             hw_stats->last_gotc, hw_stats->gotc);
1994
1995         /* Rx Multicst packets */
1996         UPDATE_VF_STAT(E1000_VFMPRC,
1997             hw_stats->last_mprc, hw_stats->mprc);
1998
1999         /* Good Rx loopback packets */
2000         UPDATE_VF_STAT(E1000_VFGPRLBC,
2001             hw_stats->last_gprlbc, hw_stats->gprlbc);
2002
2003         /* Good Rx loopback octets */
2004         UPDATE_VF_STAT(E1000_VFGORLBC,
2005             hw_stats->last_gorlbc, hw_stats->gorlbc);
2006
2007         /* Good Tx loopback packets */
2008         UPDATE_VF_STAT(E1000_VFGPTLBC,
2009             hw_stats->last_gptlbc, hw_stats->gptlbc);
2010
2011         /* Good Tx loopback octets */
2012         UPDATE_VF_STAT(E1000_VFGOTLBC,
2013             hw_stats->last_gotlbc, hw_stats->gotlbc);
2014 }
2015
2016 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2017                                      struct rte_eth_xstat_name *xstats_names,
2018                                      __rte_unused unsigned limit)
2019 {
2020         unsigned i;
2021
2022         if (xstats_names != NULL)
2023                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2024                         snprintf(xstats_names[i].name,
2025                                 sizeof(xstats_names[i].name), "%s",
2026                                 rte_igbvf_stats_strings[i].name);
2027                 }
2028         return IGBVF_NB_XSTATS;
2029 }
2030
2031 static int
2032 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2033                      unsigned n)
2034 {
2035         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2037                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2038         unsigned i;
2039
2040         if (n < IGBVF_NB_XSTATS)
2041                 return IGBVF_NB_XSTATS;
2042
2043         igbvf_read_stats_registers(hw, hw_stats);
2044
2045         if (!xstats)
2046                 return 0;
2047
2048         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2049                 xstats[i].id = i;
2050                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2051                         rte_igbvf_stats_strings[i].offset);
2052         }
2053
2054         return IGBVF_NB_XSTATS;
2055 }
2056
2057 static int
2058 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2059 {
2060         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2062                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2063
2064         igbvf_read_stats_registers(hw, hw_stats);
2065
2066         if (rte_stats == NULL)
2067                 return -EINVAL;
2068
2069         rte_stats->ipackets = hw_stats->gprc;
2070         rte_stats->ibytes = hw_stats->gorc;
2071         rte_stats->opackets = hw_stats->gptc;
2072         rte_stats->obytes = hw_stats->gotc;
2073         return 0;
2074 }
2075
2076 static void
2077 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2078 {
2079         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2080                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2081
2082         /* Sync HW register to the last stats */
2083         eth_igbvf_stats_get(dev, NULL);
2084
2085         /* reset HW current stats*/
2086         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2087                offsetof(struct e1000_vf_stats, gprc));
2088 }
2089
2090 static int
2091 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2092                        size_t fw_size)
2093 {
2094         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct e1000_fw_version fw;
2096         int ret;
2097
2098         e1000_get_fw_version(hw, &fw);
2099
2100         switch (hw->mac.type) {
2101         case e1000_i210:
2102         case e1000_i211:
2103                 if (!(e1000_get_flash_presence_i210(hw))) {
2104                         ret = snprintf(fw_version, fw_size,
2105                                  "%2d.%2d-%d",
2106                                  fw.invm_major, fw.invm_minor,
2107                                  fw.invm_img_type);
2108                         break;
2109                 }
2110                 /* fall through */
2111         default:
2112                 /* if option rom is valid, display its version too */
2113                 if (fw.or_valid) {
2114                         ret = snprintf(fw_version, fw_size,
2115                                  "%d.%d, 0x%08x, %d.%d.%d",
2116                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2117                                  fw.or_major, fw.or_build, fw.or_patch);
2118                 /* no option rom */
2119                 } else {
2120                         if (fw.etrack_id != 0X0000) {
2121                                 ret = snprintf(fw_version, fw_size,
2122                                          "%d.%d, 0x%08x",
2123                                          fw.eep_major, fw.eep_minor,
2124                                          fw.etrack_id);
2125                         } else {
2126                                 ret = snprintf(fw_version, fw_size,
2127                                          "%d.%d.%d",
2128                                          fw.eep_major, fw.eep_minor,
2129                                          fw.eep_build);
2130                         }
2131                 }
2132                 break;
2133         }
2134
2135         ret += 1; /* add the size of '\0' */
2136         if (fw_size < (u32)ret)
2137                 return ret;
2138         else
2139                 return 0;
2140 }
2141
2142 static void
2143 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2144 {
2145         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146
2147         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2148         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2149         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2150         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2151         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2152                                     dev_info->rx_queue_offload_capa;
2153         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2154         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2155                                     dev_info->tx_queue_offload_capa;
2156
2157         switch (hw->mac.type) {
2158         case e1000_82575:
2159                 dev_info->max_rx_queues = 4;
2160                 dev_info->max_tx_queues = 4;
2161                 dev_info->max_vmdq_pools = 0;
2162                 break;
2163
2164         case e1000_82576:
2165                 dev_info->max_rx_queues = 16;
2166                 dev_info->max_tx_queues = 16;
2167                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2168                 dev_info->vmdq_queue_num = 16;
2169                 break;
2170
2171         case e1000_82580:
2172                 dev_info->max_rx_queues = 8;
2173                 dev_info->max_tx_queues = 8;
2174                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2175                 dev_info->vmdq_queue_num = 8;
2176                 break;
2177
2178         case e1000_i350:
2179                 dev_info->max_rx_queues = 8;
2180                 dev_info->max_tx_queues = 8;
2181                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2182                 dev_info->vmdq_queue_num = 8;
2183                 break;
2184
2185         case e1000_i354:
2186                 dev_info->max_rx_queues = 8;
2187                 dev_info->max_tx_queues = 8;
2188                 break;
2189
2190         case e1000_i210:
2191                 dev_info->max_rx_queues = 4;
2192                 dev_info->max_tx_queues = 4;
2193                 dev_info->max_vmdq_pools = 0;
2194                 break;
2195
2196         case e1000_i211:
2197                 dev_info->max_rx_queues = 2;
2198                 dev_info->max_tx_queues = 2;
2199                 dev_info->max_vmdq_pools = 0;
2200                 break;
2201
2202         default:
2203                 /* Should not happen */
2204                 break;
2205         }
2206         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2207         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2208         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2209
2210         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2211                 .rx_thresh = {
2212                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2213                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2214                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2215                 },
2216                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2217                 .rx_drop_en = 0,
2218                 .offloads = 0,
2219         };
2220
2221         dev_info->default_txconf = (struct rte_eth_txconf) {
2222                 .tx_thresh = {
2223                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2224                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2225                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2226                 },
2227                 .txq_flags = 0,
2228                 .offloads = 0,
2229         };
2230
2231         dev_info->rx_desc_lim = rx_desc_lim;
2232         dev_info->tx_desc_lim = tx_desc_lim;
2233
2234         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2235                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2236                         ETH_LINK_SPEED_1G;
2237 }
2238
2239 static const uint32_t *
2240 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2241 {
2242         static const uint32_t ptypes[] = {
2243                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2244                 RTE_PTYPE_L2_ETHER,
2245                 RTE_PTYPE_L3_IPV4,
2246                 RTE_PTYPE_L3_IPV4_EXT,
2247                 RTE_PTYPE_L3_IPV6,
2248                 RTE_PTYPE_L3_IPV6_EXT,
2249                 RTE_PTYPE_L4_TCP,
2250                 RTE_PTYPE_L4_UDP,
2251                 RTE_PTYPE_L4_SCTP,
2252                 RTE_PTYPE_TUNNEL_IP,
2253                 RTE_PTYPE_INNER_L3_IPV6,
2254                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2255                 RTE_PTYPE_INNER_L4_TCP,
2256                 RTE_PTYPE_INNER_L4_UDP,
2257                 RTE_PTYPE_UNKNOWN
2258         };
2259
2260         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2261             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2262                 return ptypes;
2263         return NULL;
2264 }
2265
2266 static void
2267 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2268 {
2269         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270
2271         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2272         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2273         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2274         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2275                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2276                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2277                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2278                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2279                                 DEV_TX_OFFLOAD_TCP_TSO;
2280         switch (hw->mac.type) {
2281         case e1000_vfadapt:
2282                 dev_info->max_rx_queues = 2;
2283                 dev_info->max_tx_queues = 2;
2284                 break;
2285         case e1000_vfadapt_i350:
2286                 dev_info->max_rx_queues = 1;
2287                 dev_info->max_tx_queues = 1;
2288                 break;
2289         default:
2290                 /* Should not happen */
2291                 break;
2292         }
2293
2294         dev_info->rx_queue_offload_capa = igb_get_rx_queue_offloads_capa(dev);
2295         dev_info->rx_offload_capa = igb_get_rx_port_offloads_capa(dev) |
2296                                     dev_info->rx_queue_offload_capa;
2297         dev_info->tx_queue_offload_capa = igb_get_tx_queue_offloads_capa(dev);
2298         dev_info->tx_offload_capa = igb_get_tx_port_offloads_capa(dev) |
2299                                     dev_info->tx_queue_offload_capa;
2300
2301         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2302                 .rx_thresh = {
2303                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2304                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2305                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2306                 },
2307                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2308                 .rx_drop_en = 0,
2309                 .offloads = 0,
2310         };
2311
2312         dev_info->default_txconf = (struct rte_eth_txconf) {
2313                 .tx_thresh = {
2314                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2315                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2316                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2317                 },
2318                 .txq_flags = 0,
2319                 .offloads = 0,
2320         };
2321
2322         dev_info->rx_desc_lim = rx_desc_lim;
2323         dev_info->tx_desc_lim = tx_desc_lim;
2324 }
2325
2326 /* return 0 means link status changed, -1 means not changed */
2327 static int
2328 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2329 {
2330         struct e1000_hw *hw =
2331                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2332         struct rte_eth_link link;
2333         int link_check, count;
2334
2335         link_check = 0;
2336         hw->mac.get_link_status = 1;
2337
2338         /* possible wait-to-complete in up to 9 seconds */
2339         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2340                 /* Read the real link status */
2341                 switch (hw->phy.media_type) {
2342                 case e1000_media_type_copper:
2343                         /* Do the work to read phy */
2344                         e1000_check_for_link(hw);
2345                         link_check = !hw->mac.get_link_status;
2346                         break;
2347
2348                 case e1000_media_type_fiber:
2349                         e1000_check_for_link(hw);
2350                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2351                                       E1000_STATUS_LU);
2352                         break;
2353
2354                 case e1000_media_type_internal_serdes:
2355                         e1000_check_for_link(hw);
2356                         link_check = hw->mac.serdes_has_link;
2357                         break;
2358
2359                 /* VF device is type_unknown */
2360                 case e1000_media_type_unknown:
2361                         eth_igbvf_link_update(hw);
2362                         link_check = !hw->mac.get_link_status;
2363                         break;
2364
2365                 default:
2366                         break;
2367                 }
2368                 if (link_check || wait_to_complete == 0)
2369                         break;
2370                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2371         }
2372         memset(&link, 0, sizeof(link));
2373
2374         /* Now we check if a transition has happened */
2375         if (link_check) {
2376                 uint16_t duplex, speed;
2377                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2378                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2379                                 ETH_LINK_FULL_DUPLEX :
2380                                 ETH_LINK_HALF_DUPLEX;
2381                 link.link_speed = speed;
2382                 link.link_status = ETH_LINK_UP;
2383                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2384                                 ETH_LINK_SPEED_FIXED);
2385         } else if (!link_check) {
2386                 link.link_speed = 0;
2387                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2388                 link.link_status = ETH_LINK_DOWN;
2389                 link.link_autoneg = ETH_LINK_FIXED;
2390         }
2391
2392         return rte_eth_linkstatus_set(dev, &link);
2393 }
2394
2395 /*
2396  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2397  * For ASF and Pass Through versions of f/w this means
2398  * that the driver is loaded.
2399  */
2400 static void
2401 igb_hw_control_acquire(struct e1000_hw *hw)
2402 {
2403         uint32_t ctrl_ext;
2404
2405         /* Let firmware know the driver has taken over */
2406         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2407         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2408 }
2409
2410 /*
2411  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2412  * For ASF and Pass Through versions of f/w this means that the
2413  * driver is no longer loaded.
2414  */
2415 static void
2416 igb_hw_control_release(struct e1000_hw *hw)
2417 {
2418         uint32_t ctrl_ext;
2419
2420         /* Let firmware taken over control of h/w */
2421         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2422         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2423                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2424 }
2425
2426 /*
2427  * Bit of a misnomer, what this really means is
2428  * to enable OS management of the system... aka
2429  * to disable special hardware management features.
2430  */
2431 static void
2432 igb_init_manageability(struct e1000_hw *hw)
2433 {
2434         if (e1000_enable_mng_pass_thru(hw)) {
2435                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2436                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2437
2438                 /* disable hardware interception of ARP */
2439                 manc &= ~(E1000_MANC_ARP_EN);
2440
2441                 /* enable receiving management packets to the host */
2442                 manc |= E1000_MANC_EN_MNG2HOST;
2443                 manc2h |= 1 << 5;  /* Mng Port 623 */
2444                 manc2h |= 1 << 6;  /* Mng Port 664 */
2445                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2446                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2447         }
2448 }
2449
2450 static void
2451 igb_release_manageability(struct e1000_hw *hw)
2452 {
2453         if (e1000_enable_mng_pass_thru(hw)) {
2454                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2455
2456                 manc |= E1000_MANC_ARP_EN;
2457                 manc &= ~E1000_MANC_EN_MNG2HOST;
2458
2459                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2460         }
2461 }
2462
2463 static void
2464 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2465 {
2466         struct e1000_hw *hw =
2467                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         uint32_t rctl;
2469
2470         rctl = E1000_READ_REG(hw, E1000_RCTL);
2471         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2472         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2473 }
2474
2475 static void
2476 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2477 {
2478         struct e1000_hw *hw =
2479                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480         uint32_t rctl;
2481
2482         rctl = E1000_READ_REG(hw, E1000_RCTL);
2483         rctl &= (~E1000_RCTL_UPE);
2484         if (dev->data->all_multicast == 1)
2485                 rctl |= E1000_RCTL_MPE;
2486         else
2487                 rctl &= (~E1000_RCTL_MPE);
2488         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2489 }
2490
2491 static void
2492 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2493 {
2494         struct e1000_hw *hw =
2495                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         uint32_t rctl;
2497
2498         rctl = E1000_READ_REG(hw, E1000_RCTL);
2499         rctl |= E1000_RCTL_MPE;
2500         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2501 }
2502
2503 static void
2504 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2505 {
2506         struct e1000_hw *hw =
2507                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2508         uint32_t rctl;
2509
2510         if (dev->data->promiscuous == 1)
2511                 return; /* must remain in all_multicast mode */
2512         rctl = E1000_READ_REG(hw, E1000_RCTL);
2513         rctl &= (~E1000_RCTL_MPE);
2514         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2515 }
2516
2517 static int
2518 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2519 {
2520         struct e1000_hw *hw =
2521                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522         struct e1000_vfta * shadow_vfta =
2523                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2524         uint32_t vfta;
2525         uint32_t vid_idx;
2526         uint32_t vid_bit;
2527
2528         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2529                               E1000_VFTA_ENTRY_MASK);
2530         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2531         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2532         if (on)
2533                 vfta |= vid_bit;
2534         else
2535                 vfta &= ~vid_bit;
2536         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2537
2538         /* update local VFTA copy */
2539         shadow_vfta->vfta[vid_idx] = vfta;
2540
2541         return 0;
2542 }
2543
2544 static int
2545 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2546                       enum rte_vlan_type vlan_type,
2547                       uint16_t tpid)
2548 {
2549         struct e1000_hw *hw =
2550                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551         uint32_t reg, qinq;
2552
2553         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2554         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2555
2556         /* only outer TPID of double VLAN can be configured*/
2557         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2558                 reg = E1000_READ_REG(hw, E1000_VET);
2559                 reg = (reg & (~E1000_VET_VET_EXT)) |
2560                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2561                 E1000_WRITE_REG(hw, E1000_VET, reg);
2562
2563                 return 0;
2564         }
2565
2566         /* all other TPID values are read-only*/
2567         PMD_DRV_LOG(ERR, "Not supported");
2568
2569         return -ENOTSUP;
2570 }
2571
2572 static void
2573 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2574 {
2575         struct e1000_hw *hw =
2576                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577         uint32_t reg;
2578
2579         /* Filter Table Disable */
2580         reg = E1000_READ_REG(hw, E1000_RCTL);
2581         reg &= ~E1000_RCTL_CFIEN;
2582         reg &= ~E1000_RCTL_VFE;
2583         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2584 }
2585
2586 static void
2587 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2588 {
2589         struct e1000_hw *hw =
2590                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         struct e1000_vfta * shadow_vfta =
2592                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2593         uint32_t reg;
2594         int i;
2595
2596         /* Filter Table Enable, CFI not used for packet acceptance */
2597         reg = E1000_READ_REG(hw, E1000_RCTL);
2598         reg &= ~E1000_RCTL_CFIEN;
2599         reg |= E1000_RCTL_VFE;
2600         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2601
2602         /* restore VFTA table */
2603         for (i = 0; i < IGB_VFTA_SIZE; i++)
2604                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2605 }
2606
2607 static void
2608 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2609 {
2610         struct e1000_hw *hw =
2611                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         uint32_t reg;
2613
2614         /* VLAN Mode Disable */
2615         reg = E1000_READ_REG(hw, E1000_CTRL);
2616         reg &= ~E1000_CTRL_VME;
2617         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2618 }
2619
2620 static void
2621 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2622 {
2623         struct e1000_hw *hw =
2624                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625         uint32_t reg;
2626
2627         /* VLAN Mode Enable */
2628         reg = E1000_READ_REG(hw, E1000_CTRL);
2629         reg |= E1000_CTRL_VME;
2630         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2631 }
2632
2633 static void
2634 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2635 {
2636         struct e1000_hw *hw =
2637                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638         uint32_t reg;
2639
2640         /* CTRL_EXT: Extended VLAN */
2641         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2642         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2643         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2644
2645         /* Update maximum packet length */
2646         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2647                 E1000_WRITE_REG(hw, E1000_RLPML,
2648                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2649                                                 VLAN_TAG_SIZE);
2650 }
2651
2652 static void
2653 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2654 {
2655         struct e1000_hw *hw =
2656                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint32_t reg;
2658
2659         /* CTRL_EXT: Extended VLAN */
2660         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2661         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2662         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2663
2664         /* Update maximum packet length */
2665         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
2666                 E1000_WRITE_REG(hw, E1000_RLPML,
2667                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2668                                                 2 * VLAN_TAG_SIZE);
2669 }
2670
2671 static int
2672 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2673 {
2674         struct rte_eth_rxmode *rxmode;
2675
2676         rxmode = &dev->data->dev_conf.rxmode;
2677         if(mask & ETH_VLAN_STRIP_MASK){
2678                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2679                         igb_vlan_hw_strip_enable(dev);
2680                 else
2681                         igb_vlan_hw_strip_disable(dev);
2682         }
2683
2684         if(mask & ETH_VLAN_FILTER_MASK){
2685                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2686                         igb_vlan_hw_filter_enable(dev);
2687                 else
2688                         igb_vlan_hw_filter_disable(dev);
2689         }
2690
2691         if(mask & ETH_VLAN_EXTEND_MASK){
2692                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2693                         igb_vlan_hw_extend_enable(dev);
2694                 else
2695                         igb_vlan_hw_extend_disable(dev);
2696         }
2697
2698         return 0;
2699 }
2700
2701
2702 /**
2703  * It enables the interrupt mask and then enable the interrupt.
2704  *
2705  * @param dev
2706  *  Pointer to struct rte_eth_dev.
2707  * @param on
2708  *  Enable or Disable
2709  *
2710  * @return
2711  *  - On success, zero.
2712  *  - On failure, a negative value.
2713  */
2714 static int
2715 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2716 {
2717         struct e1000_interrupt *intr =
2718                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2719
2720         if (on)
2721                 intr->mask |= E1000_ICR_LSC;
2722         else
2723                 intr->mask &= ~E1000_ICR_LSC;
2724
2725         return 0;
2726 }
2727
2728 /* It clears the interrupt causes and enables the interrupt.
2729  * It will be called once only during nic initialized.
2730  *
2731  * @param dev
2732  *  Pointer to struct rte_eth_dev.
2733  *
2734  * @return
2735  *  - On success, zero.
2736  *  - On failure, a negative value.
2737  */
2738 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2739 {
2740         uint32_t mask, regval;
2741         struct e1000_hw *hw =
2742                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2743         struct rte_eth_dev_info dev_info;
2744
2745         memset(&dev_info, 0, sizeof(dev_info));
2746         eth_igb_infos_get(dev, &dev_info);
2747
2748         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2749         regval = E1000_READ_REG(hw, E1000_EIMS);
2750         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2751
2752         return 0;
2753 }
2754
2755 /*
2756  * It reads ICR and gets interrupt causes, check it and set a bit flag
2757  * to update link status.
2758  *
2759  * @param dev
2760  *  Pointer to struct rte_eth_dev.
2761  *
2762  * @return
2763  *  - On success, zero.
2764  *  - On failure, a negative value.
2765  */
2766 static int
2767 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2768 {
2769         uint32_t icr;
2770         struct e1000_hw *hw =
2771                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772         struct e1000_interrupt *intr =
2773                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2774
2775         igb_intr_disable(hw);
2776
2777         /* read-on-clear nic registers here */
2778         icr = E1000_READ_REG(hw, E1000_ICR);
2779
2780         intr->flags = 0;
2781         if (icr & E1000_ICR_LSC) {
2782                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2783         }
2784
2785         if (icr & E1000_ICR_VMMB)
2786                 intr->flags |= E1000_FLAG_MAILBOX;
2787
2788         return 0;
2789 }
2790
2791 /*
2792  * It executes link_update after knowing an interrupt is prsent.
2793  *
2794  * @param dev
2795  *  Pointer to struct rte_eth_dev.
2796  *
2797  * @return
2798  *  - On success, zero.
2799  *  - On failure, a negative value.
2800  */
2801 static int
2802 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2803                          struct rte_intr_handle *intr_handle)
2804 {
2805         struct e1000_hw *hw =
2806                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct e1000_interrupt *intr =
2808                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2809         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2810         struct rte_eth_link link;
2811         int ret;
2812
2813         if (intr->flags & E1000_FLAG_MAILBOX) {
2814                 igb_pf_mbx_process(dev);
2815                 intr->flags &= ~E1000_FLAG_MAILBOX;
2816         }
2817
2818         igb_intr_enable(dev);
2819         rte_intr_enable(intr_handle);
2820
2821         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2822                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2823
2824                 /* set get_link_status to check register later */
2825                 hw->mac.get_link_status = 1;
2826                 ret = eth_igb_link_update(dev, 0);
2827
2828                 /* check if link has changed */
2829                 if (ret < 0)
2830                         return 0;
2831
2832                 rte_eth_linkstatus_get(dev, &link);
2833                 if (link.link_status) {
2834                         PMD_INIT_LOG(INFO,
2835                                      " Port %d: Link Up - speed %u Mbps - %s",
2836                                      dev->data->port_id,
2837                                      (unsigned)link.link_speed,
2838                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2839                                      "full-duplex" : "half-duplex");
2840                 } else {
2841                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2842                                      dev->data->port_id);
2843                 }
2844
2845                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2846                              pci_dev->addr.domain,
2847                              pci_dev->addr.bus,
2848                              pci_dev->addr.devid,
2849                              pci_dev->addr.function);
2850                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2851                                               NULL);
2852         }
2853
2854         return 0;
2855 }
2856
2857 /**
2858  * Interrupt handler which shall be registered at first.
2859  *
2860  * @param handle
2861  *  Pointer to interrupt handle.
2862  * @param param
2863  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2864  *
2865  * @return
2866  *  void
2867  */
2868 static void
2869 eth_igb_interrupt_handler(void *param)
2870 {
2871         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2872
2873         eth_igb_interrupt_get_status(dev);
2874         eth_igb_interrupt_action(dev, dev->intr_handle);
2875 }
2876
2877 static int
2878 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2879 {
2880         uint32_t eicr;
2881         struct e1000_hw *hw =
2882                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883         struct e1000_interrupt *intr =
2884                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2885
2886         igbvf_intr_disable(hw);
2887
2888         /* read-on-clear nic registers here */
2889         eicr = E1000_READ_REG(hw, E1000_EICR);
2890         intr->flags = 0;
2891
2892         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2893                 intr->flags |= E1000_FLAG_MAILBOX;
2894
2895         return 0;
2896 }
2897
2898 void igbvf_mbx_process(struct rte_eth_dev *dev)
2899 {
2900         struct e1000_hw *hw =
2901                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902         struct e1000_mbx_info *mbx = &hw->mbx;
2903         u32 in_msg = 0;
2904
2905         /* peek the message first */
2906         in_msg = E1000_READ_REG(hw, E1000_VMBMEM(0));
2907
2908         /* PF reset VF event */
2909         if (in_msg == E1000_PF_CONTROL_MSG) {
2910                 /* dummy mbx read to ack pf */
2911                 if (mbx->ops.read(hw, &in_msg, 1, 0))
2912                         return;
2913                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2914                                               NULL);
2915         }
2916 }
2917
2918 static int
2919 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2920 {
2921         struct e1000_interrupt *intr =
2922                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2923
2924         if (intr->flags & E1000_FLAG_MAILBOX) {
2925                 igbvf_mbx_process(dev);
2926                 intr->flags &= ~E1000_FLAG_MAILBOX;
2927         }
2928
2929         igbvf_intr_enable(dev);
2930         rte_intr_enable(intr_handle);
2931
2932         return 0;
2933 }
2934
2935 static void
2936 eth_igbvf_interrupt_handler(void *param)
2937 {
2938         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2939
2940         eth_igbvf_interrupt_get_status(dev);
2941         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2942 }
2943
2944 static int
2945 eth_igb_led_on(struct rte_eth_dev *dev)
2946 {
2947         struct e1000_hw *hw;
2948
2949         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2950         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2951 }
2952
2953 static int
2954 eth_igb_led_off(struct rte_eth_dev *dev)
2955 {
2956         struct e1000_hw *hw;
2957
2958         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2959         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2960 }
2961
2962 static int
2963 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2964 {
2965         struct e1000_hw *hw;
2966         uint32_t ctrl;
2967         int tx_pause;
2968         int rx_pause;
2969
2970         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         fc_conf->pause_time = hw->fc.pause_time;
2972         fc_conf->high_water = hw->fc.high_water;
2973         fc_conf->low_water = hw->fc.low_water;
2974         fc_conf->send_xon = hw->fc.send_xon;
2975         fc_conf->autoneg = hw->mac.autoneg;
2976
2977         /*
2978          * Return rx_pause and tx_pause status according to actual setting of
2979          * the TFCE and RFCE bits in the CTRL register.
2980          */
2981         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2982         if (ctrl & E1000_CTRL_TFCE)
2983                 tx_pause = 1;
2984         else
2985                 tx_pause = 0;
2986
2987         if (ctrl & E1000_CTRL_RFCE)
2988                 rx_pause = 1;
2989         else
2990                 rx_pause = 0;
2991
2992         if (rx_pause && tx_pause)
2993                 fc_conf->mode = RTE_FC_FULL;
2994         else if (rx_pause)
2995                 fc_conf->mode = RTE_FC_RX_PAUSE;
2996         else if (tx_pause)
2997                 fc_conf->mode = RTE_FC_TX_PAUSE;
2998         else
2999                 fc_conf->mode = RTE_FC_NONE;
3000
3001         return 0;
3002 }
3003
3004 static int
3005 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3006 {
3007         struct e1000_hw *hw;
3008         int err;
3009         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3010                 e1000_fc_none,
3011                 e1000_fc_rx_pause,
3012                 e1000_fc_tx_pause,
3013                 e1000_fc_full
3014         };
3015         uint32_t rx_buf_size;
3016         uint32_t max_high_water;
3017         uint32_t rctl;
3018
3019         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3020         if (fc_conf->autoneg != hw->mac.autoneg)
3021                 return -ENOTSUP;
3022         rx_buf_size = igb_get_rx_buffer_size(hw);
3023         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3024
3025         /* At least reserve one Ethernet frame for watermark */
3026         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3027         if ((fc_conf->high_water > max_high_water) ||
3028             (fc_conf->high_water < fc_conf->low_water)) {
3029                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3030                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3031                 return -EINVAL;
3032         }
3033
3034         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3035         hw->fc.pause_time     = fc_conf->pause_time;
3036         hw->fc.high_water     = fc_conf->high_water;
3037         hw->fc.low_water      = fc_conf->low_water;
3038         hw->fc.send_xon       = fc_conf->send_xon;
3039
3040         err = e1000_setup_link_generic(hw);
3041         if (err == E1000_SUCCESS) {
3042
3043                 /* check if we want to forward MAC frames - driver doesn't have native
3044                  * capability to do that, so we'll write the registers ourselves */
3045
3046                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3047
3048                 /* set or clear MFLCN.PMCF bit depending on configuration */
3049                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3050                         rctl |= E1000_RCTL_PMCF;
3051                 else
3052                         rctl &= ~E1000_RCTL_PMCF;
3053
3054                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3055                 E1000_WRITE_FLUSH(hw);
3056
3057                 return 0;
3058         }
3059
3060         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3061         return -EIO;
3062 }
3063
3064 #define E1000_RAH_POOLSEL_SHIFT      (18)
3065 static int
3066 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3067                 uint32_t index, uint32_t pool)
3068 {
3069         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070         uint32_t rah;
3071
3072         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3073         rah = E1000_READ_REG(hw, E1000_RAH(index));
3074         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3075         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3076         return 0;
3077 }
3078
3079 static void
3080 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3081 {
3082         uint8_t addr[ETHER_ADDR_LEN];
3083         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3084
3085         memset(addr, 0, sizeof(addr));
3086
3087         e1000_rar_set(hw, addr, index);
3088 }
3089
3090 static void
3091 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3092                                 struct ether_addr *addr)
3093 {
3094         eth_igb_rar_clear(dev, 0);
3095
3096         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3097 }
3098 /*
3099  * Virtual Function operations
3100  */
3101 static void
3102 igbvf_intr_disable(struct e1000_hw *hw)
3103 {
3104         PMD_INIT_FUNC_TRACE();
3105
3106         /* Clear interrupt mask to stop from interrupts being generated */
3107         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3108
3109         E1000_WRITE_FLUSH(hw);
3110 }
3111
3112 static void
3113 igbvf_stop_adapter(struct rte_eth_dev *dev)
3114 {
3115         u32 reg_val;
3116         u16 i;
3117         struct rte_eth_dev_info dev_info;
3118         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119
3120         memset(&dev_info, 0, sizeof(dev_info));
3121         eth_igbvf_infos_get(dev, &dev_info);
3122
3123         /* Clear interrupt mask to stop from interrupts being generated */
3124         igbvf_intr_disable(hw);
3125
3126         /* Clear any pending interrupts, flush previous writes */
3127         E1000_READ_REG(hw, E1000_EICR);
3128
3129         /* Disable the transmit unit.  Each queue must be disabled. */
3130         for (i = 0; i < dev_info.max_tx_queues; i++)
3131                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3132
3133         /* Disable the receive unit by stopping each queue */
3134         for (i = 0; i < dev_info.max_rx_queues; i++) {
3135                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3136                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3137                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3138                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3139                         ;
3140         }
3141
3142         /* flush all queues disables */
3143         E1000_WRITE_FLUSH(hw);
3144         msec_delay(2);
3145 }
3146
3147 static int eth_igbvf_link_update(struct e1000_hw *hw)
3148 {
3149         struct e1000_mbx_info *mbx = &hw->mbx;
3150         struct e1000_mac_info *mac = &hw->mac;
3151         int ret_val = E1000_SUCCESS;
3152
3153         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3154
3155         /*
3156          * We only want to run this if there has been a rst asserted.
3157          * in this case that could mean a link change, device reset,
3158          * or a virtual function reset
3159          */
3160
3161         /* If we were hit with a reset or timeout drop the link */
3162         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3163                 mac->get_link_status = TRUE;
3164
3165         if (!mac->get_link_status)
3166                 goto out;
3167
3168         /* if link status is down no point in checking to see if pf is up */
3169         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3170                 goto out;
3171
3172         /* if we passed all the tests above then the link is up and we no
3173          * longer need to check for link */
3174         mac->get_link_status = FALSE;
3175
3176 out:
3177         return ret_val;
3178 }
3179
3180
3181 static int
3182 igbvf_dev_configure(struct rte_eth_dev *dev)
3183 {
3184         struct rte_eth_conf* conf = &dev->data->dev_conf;
3185
3186         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3187                      dev->data->port_id);
3188
3189         /*
3190          * VF has no ability to enable/disable HW CRC
3191          * Keep the persistent behavior the same as Host PF
3192          */
3193 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3194         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
3195                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3196                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
3197         }
3198 #else
3199         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
3200                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3201                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
3202         }
3203 #endif
3204
3205         return 0;
3206 }
3207
3208 static int
3209 igbvf_dev_start(struct rte_eth_dev *dev)
3210 {
3211         struct e1000_hw *hw =
3212                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213         struct e1000_adapter *adapter =
3214                 E1000_DEV_PRIVATE(dev->data->dev_private);
3215         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3216         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3217         int ret;
3218         uint32_t intr_vector = 0;
3219
3220         PMD_INIT_FUNC_TRACE();
3221
3222         hw->mac.ops.reset_hw(hw);
3223         adapter->stopped = 0;
3224
3225         /* Set all vfta */
3226         igbvf_set_vfta_all(dev,1);
3227
3228         eth_igbvf_tx_init(dev);
3229
3230         /* This can fail when allocating mbufs for descriptor rings */
3231         ret = eth_igbvf_rx_init(dev);
3232         if (ret) {
3233                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3234                 igb_dev_clear_queues(dev);
3235                 return ret;
3236         }
3237
3238         /* check and configure queue intr-vector mapping */
3239         if (rte_intr_cap_multiple(intr_handle) &&
3240             dev->data->dev_conf.intr_conf.rxq) {
3241                 intr_vector = dev->data->nb_rx_queues;
3242                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3243                 if (ret)
3244                         return ret;
3245         }
3246
3247         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3248                 intr_handle->intr_vec =
3249                         rte_zmalloc("intr_vec",
3250                                     dev->data->nb_rx_queues * sizeof(int), 0);
3251                 if (!intr_handle->intr_vec) {
3252                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3253                                      " intr_vec", dev->data->nb_rx_queues);
3254                         return -ENOMEM;
3255                 }
3256         }
3257
3258         eth_igbvf_configure_msix_intr(dev);
3259
3260         /* enable uio/vfio intr/eventfd mapping */
3261         rte_intr_enable(intr_handle);
3262
3263         /* resume enabled intr since hw reset */
3264         igbvf_intr_enable(dev);
3265
3266         return 0;
3267 }
3268
3269 static void
3270 igbvf_dev_stop(struct rte_eth_dev *dev)
3271 {
3272         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3273         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         igbvf_stop_adapter(dev);
3278
3279         /*
3280           * Clear what we set, but we still keep shadow_vfta to
3281           * restore after device starts
3282           */
3283         igbvf_set_vfta_all(dev,0);
3284
3285         igb_dev_clear_queues(dev);
3286
3287         /* disable intr eventfd mapping */
3288         rte_intr_disable(intr_handle);
3289
3290         /* Clean datapath event and queue/vec mapping */
3291         rte_intr_efd_disable(intr_handle);
3292         if (intr_handle->intr_vec) {
3293                 rte_free(intr_handle->intr_vec);
3294                 intr_handle->intr_vec = NULL;
3295         }
3296 }
3297
3298 static void
3299 igbvf_dev_close(struct rte_eth_dev *dev)
3300 {
3301         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct e1000_adapter *adapter =
3303                 E1000_DEV_PRIVATE(dev->data->dev_private);
3304         struct ether_addr addr;
3305
3306         PMD_INIT_FUNC_TRACE();
3307
3308         e1000_reset_hw(hw);
3309
3310         igbvf_dev_stop(dev);
3311         adapter->stopped = 1;
3312         igb_dev_free_queues(dev);
3313
3314         /**
3315          * reprogram the RAR with a zero mac address,
3316          * to ensure that the VF traffic goes to the PF
3317          * after stop, close and detach of the VF.
3318          **/
3319
3320         memset(&addr, 0, sizeof(addr));
3321         igbvf_default_mac_addr_set(dev, &addr);
3322 }
3323
3324 static void
3325 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3326 {
3327         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328
3329         /* Set both unicast and multicast promisc */
3330         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3331 }
3332
3333 static void
3334 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3335 {
3336         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337
3338         /* If in allmulticast mode leave multicast promisc */
3339         if (dev->data->all_multicast == 1)
3340                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3341         else
3342                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3343 }
3344
3345 static void
3346 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3347 {
3348         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349
3350         /* In promiscuous mode multicast promisc already set */
3351         if (dev->data->promiscuous == 0)
3352                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3353 }
3354
3355 static void
3356 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3357 {
3358         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359
3360         /* In promiscuous mode leave multicast promisc enabled */
3361         if (dev->data->promiscuous == 0)
3362                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3363 }
3364
3365 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3366 {
3367         struct e1000_mbx_info *mbx = &hw->mbx;
3368         uint32_t msgbuf[2];
3369         s32 err;
3370
3371         /* After set vlan, vlan strip will also be enabled in igb driver*/
3372         msgbuf[0] = E1000_VF_SET_VLAN;
3373         msgbuf[1] = vid;
3374         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3375         if (on)
3376                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3377
3378         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3379         if (err)
3380                 goto mbx_err;
3381
3382         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3383         if (err)
3384                 goto mbx_err;
3385
3386         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3387         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3388                 err = -EINVAL;
3389
3390 mbx_err:
3391         return err;
3392 }
3393
3394 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3395 {
3396         struct e1000_hw *hw =
3397                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398         struct e1000_vfta * shadow_vfta =
3399                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3400         int i = 0, j = 0, vfta = 0, mask = 1;
3401
3402         for (i = 0; i < IGB_VFTA_SIZE; i++){
3403                 vfta = shadow_vfta->vfta[i];
3404                 if(vfta){
3405                         mask = 1;
3406                         for (j = 0; j < 32; j++){
3407                                 if(vfta & mask)
3408                                         igbvf_set_vfta(hw,
3409                                                 (uint16_t)((i<<5)+j), on);
3410                                 mask<<=1;
3411                         }
3412                 }
3413         }
3414
3415 }
3416
3417 static int
3418 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3419 {
3420         struct e1000_hw *hw =
3421                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422         struct e1000_vfta * shadow_vfta =
3423                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3424         uint32_t vid_idx = 0;
3425         uint32_t vid_bit = 0;
3426         int ret = 0;
3427
3428         PMD_INIT_FUNC_TRACE();
3429
3430         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3431         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3432         if(ret){
3433                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3434                 return ret;
3435         }
3436         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3437         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3438
3439         /*Save what we set and retore it after device reset*/
3440         if (on)
3441                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3442         else
3443                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3444
3445         return 0;
3446 }
3447
3448 static void
3449 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3450 {
3451         struct e1000_hw *hw =
3452                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453
3454         /* index is not used by rar_set() */
3455         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3456 }
3457
3458
3459 static int
3460 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3461                         struct rte_eth_rss_reta_entry64 *reta_conf,
3462                         uint16_t reta_size)
3463 {
3464         uint8_t i, j, mask;
3465         uint32_t reta, r;
3466         uint16_t idx, shift;
3467         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468
3469         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3470                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3471                         "(%d) doesn't match the number hardware can supported "
3472                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3473                 return -EINVAL;
3474         }
3475
3476         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3477                 idx = i / RTE_RETA_GROUP_SIZE;
3478                 shift = i % RTE_RETA_GROUP_SIZE;
3479                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3480                                                 IGB_4_BIT_MASK);
3481                 if (!mask)
3482                         continue;
3483                 if (mask == IGB_4_BIT_MASK)
3484                         r = 0;
3485                 else
3486                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3487                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3488                         if (mask & (0x1 << j))
3489                                 reta |= reta_conf[idx].reta[shift + j] <<
3490                                                         (CHAR_BIT * j);
3491                         else
3492                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3493                 }
3494                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3495         }
3496
3497         return 0;
3498 }
3499
3500 static int
3501 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3502                        struct rte_eth_rss_reta_entry64 *reta_conf,
3503                        uint16_t reta_size)
3504 {
3505         uint8_t i, j, mask;
3506         uint32_t reta;
3507         uint16_t idx, shift;
3508         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509
3510         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3511                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3512                         "(%d) doesn't match the number hardware can supported "
3513                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3514                 return -EINVAL;
3515         }
3516
3517         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3518                 idx = i / RTE_RETA_GROUP_SIZE;
3519                 shift = i % RTE_RETA_GROUP_SIZE;
3520                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3521                                                 IGB_4_BIT_MASK);
3522                 if (!mask)
3523                         continue;
3524                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3525                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3526                         if (mask & (0x1 << j))
3527                                 reta_conf[idx].reta[shift + j] =
3528                                         ((reta >> (CHAR_BIT * j)) &
3529                                                 IGB_8_BIT_MASK);
3530                 }
3531         }
3532
3533         return 0;
3534 }
3535
3536 int
3537 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3538                         struct rte_eth_syn_filter *filter,
3539                         bool add)
3540 {
3541         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542         struct e1000_filter_info *filter_info =
3543                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3544         uint32_t synqf, rfctl;
3545
3546         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3547                 return -EINVAL;
3548
3549         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3550
3551         if (add) {
3552                 if (synqf & E1000_SYN_FILTER_ENABLE)
3553                         return -EINVAL;
3554
3555                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3556                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3557
3558                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3559                 if (filter->hig_pri)
3560                         rfctl |= E1000_RFCTL_SYNQFP;
3561                 else
3562                         rfctl &= ~E1000_RFCTL_SYNQFP;
3563
3564                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3565         } else {
3566                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3567                         return -ENOENT;
3568                 synqf = 0;
3569         }
3570
3571         filter_info->syn_info = synqf;
3572         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3573         E1000_WRITE_FLUSH(hw);
3574         return 0;
3575 }
3576
3577 static int
3578 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3579                         struct rte_eth_syn_filter *filter)
3580 {
3581         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3582         uint32_t synqf, rfctl;
3583
3584         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3585         if (synqf & E1000_SYN_FILTER_ENABLE) {
3586                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3587                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3588                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3589                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3590                 return 0;
3591         }
3592
3593         return -ENOENT;
3594 }
3595
3596 static int
3597 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3598                         enum rte_filter_op filter_op,
3599                         void *arg)
3600 {
3601         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602         int ret;
3603
3604         MAC_TYPE_FILTER_SUP(hw->mac.type);
3605
3606         if (filter_op == RTE_ETH_FILTER_NOP)
3607                 return 0;
3608
3609         if (arg == NULL) {
3610                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3611                             filter_op);
3612                 return -EINVAL;
3613         }
3614
3615         switch (filter_op) {
3616         case RTE_ETH_FILTER_ADD:
3617                 ret = eth_igb_syn_filter_set(dev,
3618                                 (struct rte_eth_syn_filter *)arg,
3619                                 TRUE);
3620                 break;
3621         case RTE_ETH_FILTER_DELETE:
3622                 ret = eth_igb_syn_filter_set(dev,
3623                                 (struct rte_eth_syn_filter *)arg,
3624                                 FALSE);
3625                 break;
3626         case RTE_ETH_FILTER_GET:
3627                 ret = eth_igb_syn_filter_get(dev,
3628                                 (struct rte_eth_syn_filter *)arg);
3629                 break;
3630         default:
3631                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3632                 ret = -EINVAL;
3633                 break;
3634         }
3635
3636         return ret;
3637 }
3638
3639 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3640 static inline int
3641 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3642                         struct e1000_2tuple_filter_info *filter_info)
3643 {
3644         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3645                 return -EINVAL;
3646         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3647                 return -EINVAL;  /* filter index is out of range. */
3648         if (filter->tcp_flags > TCP_FLAG_ALL)
3649                 return -EINVAL;  /* flags is invalid. */
3650
3651         switch (filter->dst_port_mask) {
3652         case UINT16_MAX:
3653                 filter_info->dst_port_mask = 0;
3654                 filter_info->dst_port = filter->dst_port;
3655                 break;
3656         case 0:
3657                 filter_info->dst_port_mask = 1;
3658                 break;
3659         default:
3660                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3661                 return -EINVAL;
3662         }
3663
3664         switch (filter->proto_mask) {
3665         case UINT8_MAX:
3666                 filter_info->proto_mask = 0;
3667                 filter_info->proto = filter->proto;
3668                 break;
3669         case 0:
3670                 filter_info->proto_mask = 1;
3671                 break;
3672         default:
3673                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3674                 return -EINVAL;
3675         }
3676
3677         filter_info->priority = (uint8_t)filter->priority;
3678         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3679                 filter_info->tcp_flags = filter->tcp_flags;
3680         else
3681                 filter_info->tcp_flags = 0;
3682
3683         return 0;
3684 }
3685
3686 static inline struct e1000_2tuple_filter *
3687 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3688                         struct e1000_2tuple_filter_info *key)
3689 {
3690         struct e1000_2tuple_filter *it;
3691
3692         TAILQ_FOREACH(it, filter_list, entries) {
3693                 if (memcmp(key, &it->filter_info,
3694                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3695                         return it;
3696                 }
3697         }
3698         return NULL;
3699 }
3700
3701 /* inject a igb 2tuple filter to HW */
3702 static inline void
3703 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3704                            struct e1000_2tuple_filter *filter)
3705 {
3706         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3708         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3709         int i;
3710
3711         i = filter->index;
3712         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3713         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3714                 imir |= E1000_IMIR_PORT_BP;
3715         else
3716                 imir &= ~E1000_IMIR_PORT_BP;
3717
3718         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3719
3720         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3721         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3722         ttqf |= (uint32_t)(filter->filter_info.proto &
3723                                                 E1000_TTQF_PROTOCOL_MASK);
3724         if (filter->filter_info.proto_mask == 0)
3725                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3726
3727         /* tcp flags bits setting. */
3728         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3729                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3730                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3731                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3732                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3733                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3734                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3735                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3736                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3737                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3738                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3739                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3740                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3741         } else {
3742                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3743         }
3744         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3745         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3746         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3747 }
3748
3749 /*
3750  * igb_add_2tuple_filter - add a 2tuple filter
3751  *
3752  * @param
3753  * dev: Pointer to struct rte_eth_dev.
3754  * ntuple_filter: ponter to the filter that will be added.
3755  *
3756  * @return
3757  *    - On success, zero.
3758  *    - On failure, a negative value.
3759  */
3760 static int
3761 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3762                         struct rte_eth_ntuple_filter *ntuple_filter)
3763 {
3764         struct e1000_filter_info *filter_info =
3765                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3766         struct e1000_2tuple_filter *filter;
3767         int i, ret;
3768
3769         filter = rte_zmalloc("e1000_2tuple_filter",
3770                         sizeof(struct e1000_2tuple_filter), 0);
3771         if (filter == NULL)
3772                 return -ENOMEM;
3773
3774         ret = ntuple_filter_to_2tuple(ntuple_filter,
3775                                       &filter->filter_info);
3776         if (ret < 0) {
3777                 rte_free(filter);
3778                 return ret;
3779         }
3780         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3781                                          &filter->filter_info) != NULL) {
3782                 PMD_DRV_LOG(ERR, "filter exists.");
3783                 rte_free(filter);
3784                 return -EEXIST;
3785         }
3786         filter->queue = ntuple_filter->queue;
3787
3788         /*
3789          * look for an unused 2tuple filter index,
3790          * and insert the filter to list.
3791          */
3792         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3793                 if (!(filter_info->twotuple_mask & (1 << i))) {
3794                         filter_info->twotuple_mask |= 1 << i;
3795                         filter->index = i;
3796                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3797                                           filter,
3798                                           entries);
3799                         break;
3800                 }
3801         }
3802         if (i >= E1000_MAX_TTQF_FILTERS) {
3803                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3804                 rte_free(filter);
3805                 return -ENOSYS;
3806         }
3807
3808         igb_inject_2uple_filter(dev, filter);
3809         return 0;
3810 }
3811
3812 int
3813 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3814                         struct e1000_2tuple_filter *filter)
3815 {
3816         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3817         struct e1000_filter_info *filter_info =
3818                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3819
3820         filter_info->twotuple_mask &= ~(1 << filter->index);
3821         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3822         rte_free(filter);
3823
3824         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3825         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3826         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3827         return 0;
3828 }
3829
3830 /*
3831  * igb_remove_2tuple_filter - remove a 2tuple filter
3832  *
3833  * @param
3834  * dev: Pointer to struct rte_eth_dev.
3835  * ntuple_filter: ponter to the filter that will be removed.
3836  *
3837  * @return
3838  *    - On success, zero.
3839  *    - On failure, a negative value.
3840  */
3841 static int
3842 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3843                         struct rte_eth_ntuple_filter *ntuple_filter)
3844 {
3845         struct e1000_filter_info *filter_info =
3846                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3847         struct e1000_2tuple_filter_info filter_2tuple;
3848         struct e1000_2tuple_filter *filter;
3849         int ret;
3850
3851         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3852         ret = ntuple_filter_to_2tuple(ntuple_filter,
3853                                       &filter_2tuple);
3854         if (ret < 0)
3855                 return ret;
3856
3857         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3858                                          &filter_2tuple);
3859         if (filter == NULL) {
3860                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3861                 return -ENOENT;
3862         }
3863
3864         igb_delete_2tuple_filter(dev, filter);
3865
3866         return 0;
3867 }
3868
3869 /* inject a igb flex filter to HW */
3870 static inline void
3871 igb_inject_flex_filter(struct rte_eth_dev *dev,
3872                            struct e1000_flex_filter *filter)
3873 {
3874         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875         uint32_t wufc, queueing;
3876         uint32_t reg_off;
3877         uint8_t i, j = 0;
3878
3879         wufc = E1000_READ_REG(hw, E1000_WUFC);
3880         if (filter->index < E1000_MAX_FHFT)
3881                 reg_off = E1000_FHFT(filter->index);
3882         else
3883                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3884
3885         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3886                         (E1000_WUFC_FLX0 << filter->index));
3887         queueing = filter->filter_info.len |
3888                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3889                 (filter->filter_info.priority <<
3890                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3891         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3892                         queueing);
3893
3894         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3895                 E1000_WRITE_REG(hw, reg_off,
3896                                 filter->filter_info.dwords[j]);
3897                 reg_off += sizeof(uint32_t);
3898                 E1000_WRITE_REG(hw, reg_off,
3899                                 filter->filter_info.dwords[++j]);
3900                 reg_off += sizeof(uint32_t);
3901                 E1000_WRITE_REG(hw, reg_off,
3902                         (uint32_t)filter->filter_info.mask[i]);
3903                 reg_off += sizeof(uint32_t) * 2;
3904                 ++j;
3905         }
3906 }
3907
3908 static inline struct e1000_flex_filter *
3909 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3910                         struct e1000_flex_filter_info *key)
3911 {
3912         struct e1000_flex_filter *it;
3913
3914         TAILQ_FOREACH(it, filter_list, entries) {
3915                 if (memcmp(key, &it->filter_info,
3916                         sizeof(struct e1000_flex_filter_info)) == 0)
3917                         return it;
3918         }
3919
3920         return NULL;
3921 }
3922
3923 /* remove a flex byte filter
3924  * @param
3925  * dev: Pointer to struct rte_eth_dev.
3926  * filter: the pointer of the filter will be removed.
3927  */
3928 void
3929 igb_remove_flex_filter(struct rte_eth_dev *dev,
3930                         struct e1000_flex_filter *filter)
3931 {
3932         struct e1000_filter_info *filter_info =
3933                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935         uint32_t wufc, i;
3936         uint32_t reg_off;
3937
3938         wufc = E1000_READ_REG(hw, E1000_WUFC);
3939         if (filter->index < E1000_MAX_FHFT)
3940                 reg_off = E1000_FHFT(filter->index);
3941         else
3942                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3943
3944         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3945                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3946
3947         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3948                 (~(E1000_WUFC_FLX0 << filter->index)));
3949
3950         filter_info->flex_mask &= ~(1 << filter->index);
3951         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3952         rte_free(filter);
3953 }
3954
3955 int
3956 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3957                         struct rte_eth_flex_filter *filter,
3958                         bool add)
3959 {
3960         struct e1000_filter_info *filter_info =
3961                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3962         struct e1000_flex_filter *flex_filter, *it;
3963         uint32_t mask;
3964         uint8_t shift, i;
3965
3966         flex_filter = rte_zmalloc("e1000_flex_filter",
3967                         sizeof(struct e1000_flex_filter), 0);
3968         if (flex_filter == NULL)
3969                 return -ENOMEM;
3970
3971         flex_filter->filter_info.len = filter->len;
3972         flex_filter->filter_info.priority = filter->priority;
3973         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3974         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3975                 mask = 0;
3976                 /* reverse bits in flex filter's mask*/
3977                 for (shift = 0; shift < CHAR_BIT; shift++) {
3978                         if (filter->mask[i] & (0x01 << shift))
3979                                 mask |= (0x80 >> shift);
3980                 }
3981                 flex_filter->filter_info.mask[i] = mask;
3982         }
3983
3984         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
3985                                 &flex_filter->filter_info);
3986         if (it == NULL && !add) {
3987                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3988                 rte_free(flex_filter);
3989                 return -ENOENT;
3990         }
3991         if (it != NULL && add) {
3992                 PMD_DRV_LOG(ERR, "filter exists.");
3993                 rte_free(flex_filter);
3994                 return -EEXIST;
3995         }
3996
3997         if (add) {
3998                 flex_filter->queue = filter->queue;
3999                 /*
4000                  * look for an unused flex filter index
4001                  * and insert the filter into the list.
4002                  */
4003                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4004                         if (!(filter_info->flex_mask & (1 << i))) {
4005                                 filter_info->flex_mask |= 1 << i;
4006                                 flex_filter->index = i;
4007                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4008                                         flex_filter,
4009                                         entries);
4010                                 break;
4011                         }
4012                 }
4013                 if (i >= E1000_MAX_FLEX_FILTERS) {
4014                         PMD_DRV_LOG(ERR, "flex filters are full.");
4015                         rte_free(flex_filter);
4016                         return -ENOSYS;
4017                 }
4018
4019                 igb_inject_flex_filter(dev, flex_filter);
4020
4021         } else {
4022                 igb_remove_flex_filter(dev, it);
4023                 rte_free(flex_filter);
4024         }
4025
4026         return 0;
4027 }
4028
4029 static int
4030 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4031                         struct rte_eth_flex_filter *filter)
4032 {
4033         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4034         struct e1000_filter_info *filter_info =
4035                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4036         struct e1000_flex_filter flex_filter, *it;
4037         uint32_t wufc, queueing, wufc_en = 0;
4038
4039         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4040         flex_filter.filter_info.len = filter->len;
4041         flex_filter.filter_info.priority = filter->priority;
4042         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4043         memcpy(flex_filter.filter_info.mask, filter->mask,
4044                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4045
4046         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4047                                 &flex_filter.filter_info);
4048         if (it == NULL) {
4049                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4050                 return -ENOENT;
4051         }
4052
4053         wufc = E1000_READ_REG(hw, E1000_WUFC);
4054         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4055
4056         if ((wufc & wufc_en) == wufc_en) {
4057                 uint32_t reg_off = 0;
4058                 if (it->index < E1000_MAX_FHFT)
4059                         reg_off = E1000_FHFT(it->index);
4060                 else
4061                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4062
4063                 queueing = E1000_READ_REG(hw,
4064                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4065                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4066                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4067                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4068                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4069                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4070                 return 0;
4071         }
4072         return -ENOENT;
4073 }
4074
4075 static int
4076 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4077                         enum rte_filter_op filter_op,
4078                         void *arg)
4079 {
4080         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081         struct rte_eth_flex_filter *filter;
4082         int ret = 0;
4083
4084         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4085
4086         if (filter_op == RTE_ETH_FILTER_NOP)
4087                 return ret;
4088
4089         if (arg == NULL) {
4090                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4091                             filter_op);
4092                 return -EINVAL;
4093         }
4094
4095         filter = (struct rte_eth_flex_filter *)arg;
4096         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4097             || filter->len % sizeof(uint64_t) != 0) {
4098                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4099                 return -EINVAL;
4100         }
4101         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4102                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4103                 return -EINVAL;
4104         }
4105
4106         switch (filter_op) {
4107         case RTE_ETH_FILTER_ADD:
4108                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4109                 break;
4110         case RTE_ETH_FILTER_DELETE:
4111                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4112                 break;
4113         case RTE_ETH_FILTER_GET:
4114                 ret = eth_igb_get_flex_filter(dev, filter);
4115                 break;
4116         default:
4117                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4118                 ret = -EINVAL;
4119                 break;
4120         }
4121
4122         return ret;
4123 }
4124
4125 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4126 static inline int
4127 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4128                         struct e1000_5tuple_filter_info *filter_info)
4129 {
4130         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4131                 return -EINVAL;
4132         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4133                 return -EINVAL;  /* filter index is out of range. */
4134         if (filter->tcp_flags > TCP_FLAG_ALL)
4135                 return -EINVAL;  /* flags is invalid. */
4136
4137         switch (filter->dst_ip_mask) {
4138         case UINT32_MAX:
4139                 filter_info->dst_ip_mask = 0;
4140                 filter_info->dst_ip = filter->dst_ip;
4141                 break;
4142         case 0:
4143                 filter_info->dst_ip_mask = 1;
4144                 break;
4145         default:
4146                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4147                 return -EINVAL;
4148         }
4149
4150         switch (filter->src_ip_mask) {
4151         case UINT32_MAX:
4152                 filter_info->src_ip_mask = 0;
4153                 filter_info->src_ip = filter->src_ip;
4154                 break;
4155         case 0:
4156                 filter_info->src_ip_mask = 1;
4157                 break;
4158         default:
4159                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4160                 return -EINVAL;
4161         }
4162
4163         switch (filter->dst_port_mask) {
4164         case UINT16_MAX:
4165                 filter_info->dst_port_mask = 0;
4166                 filter_info->dst_port = filter->dst_port;
4167                 break;
4168         case 0:
4169                 filter_info->dst_port_mask = 1;
4170                 break;
4171         default:
4172                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4173                 return -EINVAL;
4174         }
4175
4176         switch (filter->src_port_mask) {
4177         case UINT16_MAX:
4178                 filter_info->src_port_mask = 0;
4179                 filter_info->src_port = filter->src_port;
4180                 break;
4181         case 0:
4182                 filter_info->src_port_mask = 1;
4183                 break;
4184         default:
4185                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4186                 return -EINVAL;
4187         }
4188
4189         switch (filter->proto_mask) {
4190         case UINT8_MAX:
4191                 filter_info->proto_mask = 0;
4192                 filter_info->proto = filter->proto;
4193                 break;
4194         case 0:
4195                 filter_info->proto_mask = 1;
4196                 break;
4197         default:
4198                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4199                 return -EINVAL;
4200         }
4201
4202         filter_info->priority = (uint8_t)filter->priority;
4203         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4204                 filter_info->tcp_flags = filter->tcp_flags;
4205         else
4206                 filter_info->tcp_flags = 0;
4207
4208         return 0;
4209 }
4210
4211 static inline struct e1000_5tuple_filter *
4212 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4213                         struct e1000_5tuple_filter_info *key)
4214 {
4215         struct e1000_5tuple_filter *it;
4216
4217         TAILQ_FOREACH(it, filter_list, entries) {
4218                 if (memcmp(key, &it->filter_info,
4219                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4220                         return it;
4221                 }
4222         }
4223         return NULL;
4224 }
4225
4226 /* inject a igb 5-tuple filter to HW */
4227 static inline void
4228 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4229                            struct e1000_5tuple_filter *filter)
4230 {
4231         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4232         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4233         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4234         uint8_t i;
4235
4236         i = filter->index;
4237         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4238         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4239                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4240         if (filter->filter_info.dst_ip_mask == 0)
4241                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4242         if (filter->filter_info.src_port_mask == 0)
4243                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4244         if (filter->filter_info.proto_mask == 0)
4245                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4246         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4247                 E1000_FTQF_QUEUE_MASK;
4248         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4249         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4250         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4251         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4252
4253         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4254         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4255
4256         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4257         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4258                 imir |= E1000_IMIR_PORT_BP;
4259         else
4260                 imir &= ~E1000_IMIR_PORT_BP;
4261         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4262
4263         /* tcp flags bits setting. */
4264         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4265                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4266                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4267                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4268                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4269                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4270                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4271                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4272                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4273                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4274                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4275                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4276                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4277         } else {
4278                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4279         }
4280         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4281         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4282 }
4283
4284 /*
4285  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4286  *
4287  * @param
4288  * dev: Pointer to struct rte_eth_dev.
4289  * ntuple_filter: ponter to the filter that will be added.
4290  *
4291  * @return
4292  *    - On success, zero.
4293  *    - On failure, a negative value.
4294  */
4295 static int
4296 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4297                         struct rte_eth_ntuple_filter *ntuple_filter)
4298 {
4299         struct e1000_filter_info *filter_info =
4300                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4301         struct e1000_5tuple_filter *filter;
4302         uint8_t i;
4303         int ret;
4304
4305         filter = rte_zmalloc("e1000_5tuple_filter",
4306                         sizeof(struct e1000_5tuple_filter), 0);
4307         if (filter == NULL)
4308                 return -ENOMEM;
4309
4310         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4311                                             &filter->filter_info);
4312         if (ret < 0) {
4313                 rte_free(filter);
4314                 return ret;
4315         }
4316
4317         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4318                                          &filter->filter_info) != NULL) {
4319                 PMD_DRV_LOG(ERR, "filter exists.");
4320                 rte_free(filter);
4321                 return -EEXIST;
4322         }
4323         filter->queue = ntuple_filter->queue;
4324
4325         /*
4326          * look for an unused 5tuple filter index,
4327          * and insert the filter to list.
4328          */
4329         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4330                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4331                         filter_info->fivetuple_mask |= 1 << i;
4332                         filter->index = i;
4333                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4334                                           filter,
4335                                           entries);
4336                         break;
4337                 }
4338         }
4339         if (i >= E1000_MAX_FTQF_FILTERS) {
4340                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4341                 rte_free(filter);
4342                 return -ENOSYS;
4343         }
4344
4345         igb_inject_5tuple_filter_82576(dev, filter);
4346         return 0;
4347 }
4348
4349 int
4350 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4351                                 struct e1000_5tuple_filter *filter)
4352 {
4353         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354         struct e1000_filter_info *filter_info =
4355                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4356
4357         filter_info->fivetuple_mask &= ~(1 << filter->index);
4358         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4359         rte_free(filter);
4360
4361         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4362                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4363         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4364         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4365         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4366         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4367         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4368         return 0;
4369 }
4370
4371 /*
4372  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4373  *
4374  * @param
4375  * dev: Pointer to struct rte_eth_dev.
4376  * ntuple_filter: ponter to the filter that will be removed.
4377  *
4378  * @return
4379  *    - On success, zero.
4380  *    - On failure, a negative value.
4381  */
4382 static int
4383 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4384                                 struct rte_eth_ntuple_filter *ntuple_filter)
4385 {
4386         struct e1000_filter_info *filter_info =
4387                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4388         struct e1000_5tuple_filter_info filter_5tuple;
4389         struct e1000_5tuple_filter *filter;
4390         int ret;
4391
4392         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4393         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4394                                             &filter_5tuple);
4395         if (ret < 0)
4396                 return ret;
4397
4398         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4399                                          &filter_5tuple);
4400         if (filter == NULL) {
4401                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4402                 return -ENOENT;
4403         }
4404
4405         igb_delete_5tuple_filter_82576(dev, filter);
4406
4407         return 0;
4408 }
4409
4410 static int
4411 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4412 {
4413         uint32_t rctl;
4414         struct e1000_hw *hw;
4415         struct rte_eth_dev_info dev_info;
4416         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4417                                      VLAN_TAG_SIZE);
4418
4419         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420
4421 #ifdef RTE_LIBRTE_82571_SUPPORT
4422         /* XXX: not bigger than max_rx_pktlen */
4423         if (hw->mac.type == e1000_82571)
4424                 return -ENOTSUP;
4425 #endif
4426         eth_igb_infos_get(dev, &dev_info);
4427
4428         /* check that mtu is within the allowed range */
4429         if ((mtu < ETHER_MIN_MTU) ||
4430             (frame_size > dev_info.max_rx_pktlen))
4431                 return -EINVAL;
4432
4433         /* refuse mtu that requires the support of scattered packets when this
4434          * feature has not been enabled before. */
4435         if (!dev->data->scattered_rx &&
4436             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4437                 return -EINVAL;
4438
4439         rctl = E1000_READ_REG(hw, E1000_RCTL);
4440
4441         /* switch to jumbo mode if needed */
4442         if (frame_size > ETHER_MAX_LEN) {
4443                 dev->data->dev_conf.rxmode.offloads |=
4444                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4445                 rctl |= E1000_RCTL_LPE;
4446         } else {
4447                 dev->data->dev_conf.rxmode.offloads &=
4448                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4449                 rctl &= ~E1000_RCTL_LPE;
4450         }
4451         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4452
4453         /* update max frame size */
4454         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4455
4456         E1000_WRITE_REG(hw, E1000_RLPML,
4457                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4458
4459         return 0;
4460 }
4461
4462 /*
4463  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4464  *
4465  * @param
4466  * dev: Pointer to struct rte_eth_dev.
4467  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4468  * add: if true, add filter, if false, remove filter
4469  *
4470  * @return
4471  *    - On success, zero.
4472  *    - On failure, a negative value.
4473  */
4474 int
4475 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4476                         struct rte_eth_ntuple_filter *ntuple_filter,
4477                         bool add)
4478 {
4479         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480         int ret;
4481
4482         switch (ntuple_filter->flags) {
4483         case RTE_5TUPLE_FLAGS:
4484         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4485                 if (hw->mac.type != e1000_82576)
4486                         return -ENOTSUP;
4487                 if (add)
4488                         ret = igb_add_5tuple_filter_82576(dev,
4489                                                           ntuple_filter);
4490                 else
4491                         ret = igb_remove_5tuple_filter_82576(dev,
4492                                                              ntuple_filter);
4493                 break;
4494         case RTE_2TUPLE_FLAGS:
4495         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4496                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4497                         hw->mac.type != e1000_i210 &&
4498                         hw->mac.type != e1000_i211)
4499                         return -ENOTSUP;
4500                 if (add)
4501                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4502                 else
4503                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4504                 break;
4505         default:
4506                 ret = -EINVAL;
4507                 break;
4508         }
4509
4510         return ret;
4511 }
4512
4513 /*
4514  * igb_get_ntuple_filter - get a ntuple filter
4515  *
4516  * @param
4517  * dev: Pointer to struct rte_eth_dev.
4518  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4519  *
4520  * @return
4521  *    - On success, zero.
4522  *    - On failure, a negative value.
4523  */
4524 static int
4525 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4526                         struct rte_eth_ntuple_filter *ntuple_filter)
4527 {
4528         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4529         struct e1000_filter_info *filter_info =
4530                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4531         struct e1000_5tuple_filter_info filter_5tuple;
4532         struct e1000_2tuple_filter_info filter_2tuple;
4533         struct e1000_5tuple_filter *p_5tuple_filter;
4534         struct e1000_2tuple_filter *p_2tuple_filter;
4535         int ret;
4536
4537         switch (ntuple_filter->flags) {
4538         case RTE_5TUPLE_FLAGS:
4539         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4540                 if (hw->mac.type != e1000_82576)
4541                         return -ENOTSUP;
4542                 memset(&filter_5tuple,
4543                         0,
4544                         sizeof(struct e1000_5tuple_filter_info));
4545                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4546                                                     &filter_5tuple);
4547                 if (ret < 0)
4548                         return ret;
4549                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4550                                         &filter_info->fivetuple_list,
4551                                         &filter_5tuple);
4552                 if (p_5tuple_filter == NULL) {
4553                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4554                         return -ENOENT;
4555                 }
4556                 ntuple_filter->queue = p_5tuple_filter->queue;
4557                 break;
4558         case RTE_2TUPLE_FLAGS:
4559         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4560                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4561                         return -ENOTSUP;
4562                 memset(&filter_2tuple,
4563                         0,
4564                         sizeof(struct e1000_2tuple_filter_info));
4565                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4566                 if (ret < 0)
4567                         return ret;
4568                 p_2tuple_filter = igb_2tuple_filter_lookup(
4569                                         &filter_info->twotuple_list,
4570                                         &filter_2tuple);
4571                 if (p_2tuple_filter == NULL) {
4572                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4573                         return -ENOENT;
4574                 }
4575                 ntuple_filter->queue = p_2tuple_filter->queue;
4576                 break;
4577         default:
4578                 ret = -EINVAL;
4579                 break;
4580         }
4581
4582         return 0;
4583 }
4584
4585 /*
4586  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4587  * @dev: pointer to rte_eth_dev structure
4588  * @filter_op:operation will be taken.
4589  * @arg: a pointer to specific structure corresponding to the filter_op
4590  */
4591 static int
4592 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4593                                 enum rte_filter_op filter_op,
4594                                 void *arg)
4595 {
4596         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597         int ret;
4598
4599         MAC_TYPE_FILTER_SUP(hw->mac.type);
4600
4601         if (filter_op == RTE_ETH_FILTER_NOP)
4602                 return 0;
4603
4604         if (arg == NULL) {
4605                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4606                             filter_op);
4607                 return -EINVAL;
4608         }
4609
4610         switch (filter_op) {
4611         case RTE_ETH_FILTER_ADD:
4612                 ret = igb_add_del_ntuple_filter(dev,
4613                         (struct rte_eth_ntuple_filter *)arg,
4614                         TRUE);
4615                 break;
4616         case RTE_ETH_FILTER_DELETE:
4617                 ret = igb_add_del_ntuple_filter(dev,
4618                         (struct rte_eth_ntuple_filter *)arg,
4619                         FALSE);
4620                 break;
4621         case RTE_ETH_FILTER_GET:
4622                 ret = igb_get_ntuple_filter(dev,
4623                         (struct rte_eth_ntuple_filter *)arg);
4624                 break;
4625         default:
4626                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4627                 ret = -EINVAL;
4628                 break;
4629         }
4630         return ret;
4631 }
4632
4633 static inline int
4634 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4635                         uint16_t ethertype)
4636 {
4637         int i;
4638
4639         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4640                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4641                     (filter_info->ethertype_mask & (1 << i)))
4642                         return i;
4643         }
4644         return -1;
4645 }
4646
4647 static inline int
4648 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4649                         uint16_t ethertype, uint32_t etqf)
4650 {
4651         int i;
4652
4653         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4654                 if (!(filter_info->ethertype_mask & (1 << i))) {
4655                         filter_info->ethertype_mask |= 1 << i;
4656                         filter_info->ethertype_filters[i].ethertype = ethertype;
4657                         filter_info->ethertype_filters[i].etqf = etqf;
4658                         return i;
4659                 }
4660         }
4661         return -1;
4662 }
4663
4664 int
4665 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4666                         uint8_t idx)
4667 {
4668         if (idx >= E1000_MAX_ETQF_FILTERS)
4669                 return -1;
4670         filter_info->ethertype_mask &= ~(1 << idx);
4671         filter_info->ethertype_filters[idx].ethertype = 0;
4672         filter_info->ethertype_filters[idx].etqf = 0;
4673         return idx;
4674 }
4675
4676
4677 int
4678 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4679                         struct rte_eth_ethertype_filter *filter,
4680                         bool add)
4681 {
4682         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683         struct e1000_filter_info *filter_info =
4684                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4685         uint32_t etqf = 0;
4686         int ret;
4687
4688         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4689                 filter->ether_type == ETHER_TYPE_IPv6) {
4690                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4691                         " ethertype filter.", filter->ether_type);
4692                 return -EINVAL;
4693         }
4694
4695         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4696                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4697                 return -EINVAL;
4698         }
4699         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4700                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4701                 return -EINVAL;
4702         }
4703
4704         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4705         if (ret >= 0 && add) {
4706                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4707                             filter->ether_type);
4708                 return -EEXIST;
4709         }
4710         if (ret < 0 && !add) {
4711                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4712                             filter->ether_type);
4713                 return -ENOENT;
4714         }
4715
4716         if (add) {
4717                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4718                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4719                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4720                 ret = igb_ethertype_filter_insert(filter_info,
4721                                 filter->ether_type, etqf);
4722                 if (ret < 0) {
4723                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4724                         return -ENOSYS;
4725                 }
4726         } else {
4727                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4728                 if (ret < 0)
4729                         return -ENOSYS;
4730         }
4731         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4732         E1000_WRITE_FLUSH(hw);
4733
4734         return 0;
4735 }
4736
4737 static int
4738 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4739                         struct rte_eth_ethertype_filter *filter)
4740 {
4741         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         struct e1000_filter_info *filter_info =
4743                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4744         uint32_t etqf;
4745         int ret;
4746
4747         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4748         if (ret < 0) {
4749                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4750                             filter->ether_type);
4751                 return -ENOENT;
4752         }
4753
4754         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4755         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4756                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4757                 filter->flags = 0;
4758                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4759                                 E1000_ETQF_QUEUE_SHIFT;
4760                 return 0;
4761         }
4762
4763         return -ENOENT;
4764 }
4765
4766 /*
4767  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4768  * @dev: pointer to rte_eth_dev structure
4769  * @filter_op:operation will be taken.
4770  * @arg: a pointer to specific structure corresponding to the filter_op
4771  */
4772 static int
4773 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4774                                 enum rte_filter_op filter_op,
4775                                 void *arg)
4776 {
4777         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778         int ret;
4779
4780         MAC_TYPE_FILTER_SUP(hw->mac.type);
4781
4782         if (filter_op == RTE_ETH_FILTER_NOP)
4783                 return 0;
4784
4785         if (arg == NULL) {
4786                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4787                             filter_op);
4788                 return -EINVAL;
4789         }
4790
4791         switch (filter_op) {
4792         case RTE_ETH_FILTER_ADD:
4793                 ret = igb_add_del_ethertype_filter(dev,
4794                         (struct rte_eth_ethertype_filter *)arg,
4795                         TRUE);
4796                 break;
4797         case RTE_ETH_FILTER_DELETE:
4798                 ret = igb_add_del_ethertype_filter(dev,
4799                         (struct rte_eth_ethertype_filter *)arg,
4800                         FALSE);
4801                 break;
4802         case RTE_ETH_FILTER_GET:
4803                 ret = igb_get_ethertype_filter(dev,
4804                         (struct rte_eth_ethertype_filter *)arg);
4805                 break;
4806         default:
4807                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4808                 ret = -EINVAL;
4809                 break;
4810         }
4811         return ret;
4812 }
4813
4814 static int
4815 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4816                      enum rte_filter_type filter_type,
4817                      enum rte_filter_op filter_op,
4818                      void *arg)
4819 {
4820         int ret = 0;
4821
4822         switch (filter_type) {
4823         case RTE_ETH_FILTER_NTUPLE:
4824                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4825                 break;
4826         case RTE_ETH_FILTER_ETHERTYPE:
4827                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4828                 break;
4829         case RTE_ETH_FILTER_SYN:
4830                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4831                 break;
4832         case RTE_ETH_FILTER_FLEXIBLE:
4833                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4834                 break;
4835         case RTE_ETH_FILTER_GENERIC:
4836                 if (filter_op != RTE_ETH_FILTER_GET)
4837                         return -EINVAL;
4838                 *(const void **)arg = &igb_flow_ops;
4839                 break;
4840         default:
4841                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4842                                                         filter_type);
4843                 break;
4844         }
4845
4846         return ret;
4847 }
4848
4849 static int
4850 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4851                          struct ether_addr *mc_addr_set,
4852                          uint32_t nb_mc_addr)
4853 {
4854         struct e1000_hw *hw;
4855
4856         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4858         return 0;
4859 }
4860
4861 static uint64_t
4862 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4863 {
4864         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4865         uint64_t systime_cycles;
4866
4867         switch (hw->mac.type) {
4868         case e1000_i210:
4869         case e1000_i211:
4870                 /*
4871                  * Need to read System Time Residue Register to be able
4872                  * to read the other two registers.
4873                  */
4874                 E1000_READ_REG(hw, E1000_SYSTIMR);
4875                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4876                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4877                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4878                                 * NSEC_PER_SEC;
4879                 break;
4880         case e1000_82580:
4881         case e1000_i350:
4882         case e1000_i354:
4883                 /*
4884                  * Need to read System Time Residue Register to be able
4885                  * to read the other two registers.
4886                  */
4887                 E1000_READ_REG(hw, E1000_SYSTIMR);
4888                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4889                 /* Only the 8 LSB are valid. */
4890                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4891                                 & 0xff) << 32;
4892                 break;
4893         default:
4894                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4895                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4896                                 << 32;
4897                 break;
4898         }
4899
4900         return systime_cycles;
4901 }
4902
4903 static uint64_t
4904 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4905 {
4906         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907         uint64_t rx_tstamp_cycles;
4908
4909         switch (hw->mac.type) {
4910         case e1000_i210:
4911         case e1000_i211:
4912                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4913                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4914                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4915                                 * NSEC_PER_SEC;
4916                 break;
4917         case e1000_82580:
4918         case e1000_i350:
4919         case e1000_i354:
4920                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4921                 /* Only the 8 LSB are valid. */
4922                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4923                                 & 0xff) << 32;
4924                 break;
4925         default:
4926                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4927                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4928                                 << 32;
4929                 break;
4930         }
4931
4932         return rx_tstamp_cycles;
4933 }
4934
4935 static uint64_t
4936 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4937 {
4938         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint64_t tx_tstamp_cycles;
4940
4941         switch (hw->mac.type) {
4942         case e1000_i210:
4943         case e1000_i211:
4944                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4945                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4946                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4947                                 * NSEC_PER_SEC;
4948                 break;
4949         case e1000_82580:
4950         case e1000_i350:
4951         case e1000_i354:
4952                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4953                 /* Only the 8 LSB are valid. */
4954                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4955                                 & 0xff) << 32;
4956                 break;
4957         default:
4958                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4959                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4960                                 << 32;
4961                 break;
4962         }
4963
4964         return tx_tstamp_cycles;
4965 }
4966
4967 static void
4968 igb_start_timecounters(struct rte_eth_dev *dev)
4969 {
4970         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971         struct e1000_adapter *adapter =
4972                 (struct e1000_adapter *)dev->data->dev_private;
4973         uint32_t incval = 1;
4974         uint32_t shift = 0;
4975         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4976
4977         switch (hw->mac.type) {
4978         case e1000_82580:
4979         case e1000_i350:
4980         case e1000_i354:
4981                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4982                 mask = (1ULL << 40) - 1;
4983                 /* fall-through */
4984         case e1000_i210:
4985         case e1000_i211:
4986                 /*
4987                  * Start incrementing the register
4988                  * used to timestamp PTP packets.
4989                  */
4990                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4991                 break;
4992         case e1000_82576:
4993                 incval = E1000_INCVALUE_82576;
4994                 shift = IGB_82576_TSYNC_SHIFT;
4995                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4996                                 E1000_INCPERIOD_82576 | incval);
4997                 break;
4998         default:
4999                 /* Not supported */
5000                 return;
5001         }
5002
5003         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5004         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5005         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5006
5007         adapter->systime_tc.cc_mask = mask;
5008         adapter->systime_tc.cc_shift = shift;
5009         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5010
5011         adapter->rx_tstamp_tc.cc_mask = mask;
5012         adapter->rx_tstamp_tc.cc_shift = shift;
5013         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5014
5015         adapter->tx_tstamp_tc.cc_mask = mask;
5016         adapter->tx_tstamp_tc.cc_shift = shift;
5017         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5018 }
5019
5020 static int
5021 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5022 {
5023         struct e1000_adapter *adapter =
5024                         (struct e1000_adapter *)dev->data->dev_private;
5025
5026         adapter->systime_tc.nsec += delta;
5027         adapter->rx_tstamp_tc.nsec += delta;
5028         adapter->tx_tstamp_tc.nsec += delta;
5029
5030         return 0;
5031 }
5032
5033 static int
5034 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5035 {
5036         uint64_t ns;
5037         struct e1000_adapter *adapter =
5038                         (struct e1000_adapter *)dev->data->dev_private;
5039
5040         ns = rte_timespec_to_ns(ts);
5041
5042         /* Set the timecounters to a new value. */
5043         adapter->systime_tc.nsec = ns;
5044         adapter->rx_tstamp_tc.nsec = ns;
5045         adapter->tx_tstamp_tc.nsec = ns;
5046
5047         return 0;
5048 }
5049
5050 static int
5051 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5052 {
5053         uint64_t ns, systime_cycles;
5054         struct e1000_adapter *adapter =
5055                         (struct e1000_adapter *)dev->data->dev_private;
5056
5057         systime_cycles = igb_read_systime_cyclecounter(dev);
5058         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5059         *ts = rte_ns_to_timespec(ns);
5060
5061         return 0;
5062 }
5063
5064 static int
5065 igb_timesync_enable(struct rte_eth_dev *dev)
5066 {
5067         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5068         uint32_t tsync_ctl;
5069         uint32_t tsauxc;
5070
5071         /* Stop the timesync system time. */
5072         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5073         /* Reset the timesync system time value. */
5074         switch (hw->mac.type) {
5075         case e1000_82580:
5076         case e1000_i350:
5077         case e1000_i354:
5078         case e1000_i210:
5079         case e1000_i211:
5080                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5081                 /* fall-through */
5082         case e1000_82576:
5083                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5084                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5085                 break;
5086         default:
5087                 /* Not supported. */
5088                 return -ENOTSUP;
5089         }
5090
5091         /* Enable system time for it isn't on by default. */
5092         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5093         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5094         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5095
5096         igb_start_timecounters(dev);
5097
5098         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5099         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5100                         (ETHER_TYPE_1588 |
5101                          E1000_ETQF_FILTER_ENABLE |
5102                          E1000_ETQF_1588));
5103
5104         /* Enable timestamping of received PTP packets. */
5105         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5106         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5107         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5108
5109         /* Enable Timestamping of transmitted PTP packets. */
5110         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5111         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5112         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5113
5114         return 0;
5115 }
5116
5117 static int
5118 igb_timesync_disable(struct rte_eth_dev *dev)
5119 {
5120         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121         uint32_t tsync_ctl;
5122
5123         /* Disable timestamping of transmitted PTP packets. */
5124         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5125         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5126         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5127
5128         /* Disable timestamping of received PTP packets. */
5129         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5130         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5131         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5132
5133         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5134         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5135
5136         /* Stop incrementating the System Time registers. */
5137         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5138
5139         return 0;
5140 }
5141
5142 static int
5143 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5144                                struct timespec *timestamp,
5145                                uint32_t flags __rte_unused)
5146 {
5147         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5148         struct e1000_adapter *adapter =
5149                         (struct e1000_adapter *)dev->data->dev_private;
5150         uint32_t tsync_rxctl;
5151         uint64_t rx_tstamp_cycles;
5152         uint64_t ns;
5153
5154         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5155         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5156                 return -EINVAL;
5157
5158         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5159         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5160         *timestamp = rte_ns_to_timespec(ns);
5161
5162         return  0;
5163 }
5164
5165 static int
5166 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5167                                struct timespec *timestamp)
5168 {
5169         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5170         struct e1000_adapter *adapter =
5171                         (struct e1000_adapter *)dev->data->dev_private;
5172         uint32_t tsync_txctl;
5173         uint64_t tx_tstamp_cycles;
5174         uint64_t ns;
5175
5176         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5177         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5178                 return -EINVAL;
5179
5180         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5181         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5182         *timestamp = rte_ns_to_timespec(ns);
5183
5184         return  0;
5185 }
5186
5187 static int
5188 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5189 {
5190         int count = 0;
5191         int g_ind = 0;
5192         const struct reg_info *reg_group;
5193
5194         while ((reg_group = igb_regs[g_ind++]))
5195                 count += igb_reg_group_count(reg_group);
5196
5197         return count;
5198 }
5199
5200 static int
5201 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5202 {
5203         int count = 0;
5204         int g_ind = 0;
5205         const struct reg_info *reg_group;
5206
5207         while ((reg_group = igbvf_regs[g_ind++]))
5208                 count += igb_reg_group_count(reg_group);
5209
5210         return count;
5211 }
5212
5213 static int
5214 eth_igb_get_regs(struct rte_eth_dev *dev,
5215         struct rte_dev_reg_info *regs)
5216 {
5217         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5218         uint32_t *data = regs->data;
5219         int g_ind = 0;
5220         int count = 0;
5221         const struct reg_info *reg_group;
5222
5223         if (data == NULL) {
5224                 regs->length = eth_igb_get_reg_length(dev);
5225                 regs->width = sizeof(uint32_t);
5226                 return 0;
5227         }
5228
5229         /* Support only full register dump */
5230         if ((regs->length == 0) ||
5231             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5232                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5233                         hw->device_id;
5234                 while ((reg_group = igb_regs[g_ind++]))
5235                         count += igb_read_regs_group(dev, &data[count],
5236                                                         reg_group);
5237                 return 0;
5238         }
5239
5240         return -ENOTSUP;
5241 }
5242
5243 static int
5244 igbvf_get_regs(struct rte_eth_dev *dev,
5245         struct rte_dev_reg_info *regs)
5246 {
5247         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248         uint32_t *data = regs->data;
5249         int g_ind = 0;
5250         int count = 0;
5251         const struct reg_info *reg_group;
5252
5253         if (data == NULL) {
5254                 regs->length = igbvf_get_reg_length(dev);
5255                 regs->width = sizeof(uint32_t);
5256                 return 0;
5257         }
5258
5259         /* Support only full register dump */
5260         if ((regs->length == 0) ||
5261             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5262                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5263                         hw->device_id;
5264                 while ((reg_group = igbvf_regs[g_ind++]))
5265                         count += igb_read_regs_group(dev, &data[count],
5266                                                         reg_group);
5267                 return 0;
5268         }
5269
5270         return -ENOTSUP;
5271 }
5272
5273 static int
5274 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5275 {
5276         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5277
5278         /* Return unit is byte count */
5279         return hw->nvm.word_size * 2;
5280 }
5281
5282 static int
5283 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5284         struct rte_dev_eeprom_info *in_eeprom)
5285 {
5286         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5287         struct e1000_nvm_info *nvm = &hw->nvm;
5288         uint16_t *data = in_eeprom->data;
5289         int first, length;
5290
5291         first = in_eeprom->offset >> 1;
5292         length = in_eeprom->length >> 1;
5293         if ((first >= hw->nvm.word_size) ||
5294             ((first + length) >= hw->nvm.word_size))
5295                 return -EINVAL;
5296
5297         in_eeprom->magic = hw->vendor_id |
5298                 ((uint32_t)hw->device_id << 16);
5299
5300         if ((nvm->ops.read) == NULL)
5301                 return -ENOTSUP;
5302
5303         return nvm->ops.read(hw, first, length, data);
5304 }
5305
5306 static int
5307 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5308         struct rte_dev_eeprom_info *in_eeprom)
5309 {
5310         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5311         struct e1000_nvm_info *nvm = &hw->nvm;
5312         uint16_t *data = in_eeprom->data;
5313         int first, length;
5314
5315         first = in_eeprom->offset >> 1;
5316         length = in_eeprom->length >> 1;
5317         if ((first >= hw->nvm.word_size) ||
5318             ((first + length) >= hw->nvm.word_size))
5319                 return -EINVAL;
5320
5321         in_eeprom->magic = (uint32_t)hw->vendor_id |
5322                 ((uint32_t)hw->device_id << 16);
5323
5324         if ((nvm->ops.write) == NULL)
5325                 return -ENOTSUP;
5326         return nvm->ops.write(hw,  first, length, data);
5327 }
5328
5329 static int
5330 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5331 {
5332         struct e1000_hw *hw =
5333                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5335         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5336         uint32_t vec = E1000_MISC_VEC_ID;
5337
5338         if (rte_intr_allow_others(intr_handle))
5339                 vec = E1000_RX_VEC_START;
5340
5341         uint32_t mask = 1 << (queue_id + vec);
5342
5343         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5344         E1000_WRITE_FLUSH(hw);
5345
5346         return 0;
5347 }
5348
5349 static int
5350 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5351 {
5352         struct e1000_hw *hw =
5353                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5354         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5355         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5356         uint32_t vec = E1000_MISC_VEC_ID;
5357
5358         if (rte_intr_allow_others(intr_handle))
5359                 vec = E1000_RX_VEC_START;
5360
5361         uint32_t mask = 1 << (queue_id + vec);
5362         uint32_t regval;
5363
5364         regval = E1000_READ_REG(hw, E1000_EIMS);
5365         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5366         E1000_WRITE_FLUSH(hw);
5367
5368         rte_intr_enable(intr_handle);
5369
5370         return 0;
5371 }
5372
5373 static void
5374 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5375                    uint8_t index, uint8_t offset)
5376 {
5377         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5378
5379         /* clear bits */
5380         val &= ~((uint32_t)0xFF << offset);
5381
5382         /* write vector and valid bit */
5383         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5384
5385         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5386 }
5387
5388 static void
5389 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5390                            uint8_t queue, uint8_t msix_vector)
5391 {
5392         uint32_t tmp = 0;
5393
5394         if (hw->mac.type == e1000_82575) {
5395                 if (direction == 0)
5396                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5397                 else if (direction == 1)
5398                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5399                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5400         } else if (hw->mac.type == e1000_82576) {
5401                 if ((direction == 0) || (direction == 1))
5402                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5403                                            ((queue & 0x8) << 1) +
5404                                            8 * direction);
5405         } else if ((hw->mac.type == e1000_82580) ||
5406                         (hw->mac.type == e1000_i350) ||
5407                         (hw->mac.type == e1000_i354) ||
5408                         (hw->mac.type == e1000_i210) ||
5409                         (hw->mac.type == e1000_i211)) {
5410                 if ((direction == 0) || (direction == 1))
5411                         eth_igb_write_ivar(hw, msix_vector,
5412                                            queue >> 1,
5413                                            ((queue & 0x1) << 4) +
5414                                            8 * direction);
5415         }
5416 }
5417
5418 /* Sets up the hardware to generate MSI-X interrupts properly
5419  * @hw
5420  *  board private structure
5421  */
5422 static void
5423 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5424 {
5425         int queue_id;
5426         uint32_t tmpval, regval, intr_mask;
5427         struct e1000_hw *hw =
5428                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5429         uint32_t vec = E1000_MISC_VEC_ID;
5430         uint32_t base = E1000_MISC_VEC_ID;
5431         uint32_t misc_shift = 0;
5432         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5433         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5434
5435         /* won't configure msix register if no mapping is done
5436          * between intr vector and event fd
5437          */
5438         if (!rte_intr_dp_is_en(intr_handle))
5439                 return;
5440
5441         if (rte_intr_allow_others(intr_handle)) {
5442                 vec = base = E1000_RX_VEC_START;
5443                 misc_shift = 1;
5444         }
5445
5446         /* set interrupt vector for other causes */
5447         if (hw->mac.type == e1000_82575) {
5448                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5449                 /* enable MSI-X PBA support */
5450                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5451
5452                 /* Auto-Mask interrupts upon ICR read */
5453                 tmpval |= E1000_CTRL_EXT_EIAME;
5454                 tmpval |= E1000_CTRL_EXT_IRCA;
5455
5456                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5457
5458                 /* enable msix_other interrupt */
5459                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5460                 regval = E1000_READ_REG(hw, E1000_EIAC);
5461                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5462                 regval = E1000_READ_REG(hw, E1000_EIAM);
5463                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5464         } else if ((hw->mac.type == e1000_82576) ||
5465                         (hw->mac.type == e1000_82580) ||
5466                         (hw->mac.type == e1000_i350) ||
5467                         (hw->mac.type == e1000_i354) ||
5468                         (hw->mac.type == e1000_i210) ||
5469                         (hw->mac.type == e1000_i211)) {
5470                 /* turn on MSI-X capability first */
5471                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5472                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5473                                         E1000_GPIE_NSICR);
5474                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5475                         misc_shift;
5476                 regval = E1000_READ_REG(hw, E1000_EIAC);
5477                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5478
5479                 /* enable msix_other interrupt */
5480                 regval = E1000_READ_REG(hw, E1000_EIMS);
5481                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5482                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5483                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5484         }
5485
5486         /* use EIAM to auto-mask when MSI-X interrupt
5487          * is asserted, this saves a register write for every interrupt
5488          */
5489         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5490                 misc_shift;
5491         regval = E1000_READ_REG(hw, E1000_EIAM);
5492         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5493
5494         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5495                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5496                 intr_handle->intr_vec[queue_id] = vec;
5497                 if (vec < base + intr_handle->nb_efd - 1)
5498                         vec++;
5499         }
5500
5501         E1000_WRITE_FLUSH(hw);
5502 }
5503
5504 /* restore n-tuple filter */
5505 static inline void
5506 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5507 {
5508         struct e1000_filter_info *filter_info =
5509                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5510         struct e1000_5tuple_filter *p_5tuple;
5511         struct e1000_2tuple_filter *p_2tuple;
5512
5513         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5514                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5515         }
5516
5517         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5518                 igb_inject_2uple_filter(dev, p_2tuple);
5519         }
5520 }
5521
5522 /* restore SYN filter */
5523 static inline void
5524 igb_syn_filter_restore(struct rte_eth_dev *dev)
5525 {
5526         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527         struct e1000_filter_info *filter_info =
5528                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5529         uint32_t synqf;
5530
5531         synqf = filter_info->syn_info;
5532
5533         if (synqf & E1000_SYN_FILTER_ENABLE) {
5534                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5535                 E1000_WRITE_FLUSH(hw);
5536         }
5537 }
5538
5539 /* restore ethernet type filter */
5540 static inline void
5541 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5542 {
5543         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5544         struct e1000_filter_info *filter_info =
5545                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5546         int i;
5547
5548         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5549                 if (filter_info->ethertype_mask & (1 << i)) {
5550                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5551                                 filter_info->ethertype_filters[i].etqf);
5552                         E1000_WRITE_FLUSH(hw);
5553                 }
5554         }
5555 }
5556
5557 /* restore flex byte filter */
5558 static inline void
5559 igb_flex_filter_restore(struct rte_eth_dev *dev)
5560 {
5561         struct e1000_filter_info *filter_info =
5562                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5563         struct e1000_flex_filter *flex_filter;
5564
5565         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5566                 igb_inject_flex_filter(dev, flex_filter);
5567         }
5568 }
5569
5570 /* restore rss filter */
5571 static inline void
5572 igb_rss_filter_restore(struct rte_eth_dev *dev)
5573 {
5574         struct e1000_filter_info *filter_info =
5575                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5576
5577         if (filter_info->rss_info.num)
5578                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5579 }
5580
5581 /* restore all types filter */
5582 static int
5583 igb_filter_restore(struct rte_eth_dev *dev)
5584 {
5585         igb_ntuple_filter_restore(dev);
5586         igb_ethertype_filter_restore(dev);
5587         igb_syn_filter_restore(dev);
5588         igb_flex_filter_restore(dev);
5589         igb_rss_filter_restore(dev);
5590
5591         return 0;
5592 }
5593
5594 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5595 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5596 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5597 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5598 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5599 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");