drivers/net/e1000/igb_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <stdarg.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_interrupts.h>
  13 #include <rte_byteorder.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memory.h>
  22 #include <rte_eal.h>
  23 #include <rte_atomic.h>
  24 #include <rte_malloc.h>
  25 #include <rte_dev.h>
  26
  27 #include "e1000_logs.h"
  28 #include "base/e1000_api.h"
  29 #include "e1000_ethdev.h"
  30 #include "igb_regs.h"
  31
  32 /*
  33  * Default values for port configuration
  34  */
  35 #define IGB_DEFAULT_RX_FREE_THRESH  32
  36
  37 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  38 #define IGB_DEFAULT_RX_HTHRESH      8
  39 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  40
  41 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  42 #define IGB_DEFAULT_TX_HTHRESH      1
  43 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  44
  45 #define IGB_HKEY_MAX_INDEX 10
  46
  47 /* Bit shift and mask */
  48 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  49 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  50 #define IGB_8_BIT_WIDTH  CHAR_BIT
  51 #define IGB_8_BIT_MASK   UINT8_MAX
  52
  53 /* Additional timesync values. */
  54 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  55 #define E1000_ETQF_FILTER_1588       3
  56 #define IGB_82576_TSYNC_SHIFT        16
  57 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  58 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  59 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  60
  61 #define E1000_VTIVAR_MISC                0x01740
  62 #define E1000_VTIVAR_MISC_MASK           0xFF
  63 #define E1000_VTIVAR_VALID               0x80
  64 #define E1000_VTIVAR_MISC_MAILBOX        0
  65 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  66
  67 /* External VLAN Enable bit mask */
  68 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  69
  70 /* External VLAN Ether Type bit mask and shift */
  71 #define E1000_VET_VET_EXT            0xFFFF0000
  72 #define E1000_VET_VET_EXT_SHIFT      16
  73
  74 static int  eth_igb_configure(struct rte_eth_dev *dev);
  75 static int  eth_igb_start(struct rte_eth_dev *dev);
  76 static void eth_igb_stop(struct rte_eth_dev *dev);
  77 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
  78 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
  79 static void eth_igb_close(struct rte_eth_dev *dev);
  80 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
  81 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
  82 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
  83 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
  84 static int  eth_igb_link_update(struct rte_eth_dev *dev,
  85                                 int wait_to_complete);
  86 static int eth_igb_stats_get(struct rte_eth_dev *dev,
  87                                 struct rte_eth_stats *rte_stats);
  88 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
  89                               struct rte_eth_xstat *xstats, unsigned n);
  90 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
  91                 const uint64_t *ids,
  92                 uint64_t *values, unsigned int n);
  93 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
  94                                     struct rte_eth_xstat_name *xstats_names,
  95                                     unsigned int size);
  96 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
  97                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
  98                 unsigned int limit);
  99 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 100 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 101 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 102                                    char *fw_version, size_t fw_size);
 103 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 104                               struct rte_eth_dev_info *dev_info);
 105 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 106 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 107                                 struct rte_eth_dev_info *dev_info);
 108 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 109                                 struct rte_eth_fc_conf *fc_conf);
 110 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 111                                 struct rte_eth_fc_conf *fc_conf);
 112 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 113 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 114 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 115 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 116                                     struct rte_intr_handle *handle);
 117 static void eth_igb_interrupt_handler(void *param);
 118 static int  igb_hardware_init(struct e1000_hw *hw);
 119 static void igb_hw_control_acquire(struct e1000_hw *hw);
 120 static void igb_hw_control_release(struct e1000_hw *hw);
 121 static void igb_init_manageability(struct e1000_hw *hw);
 122 static void igb_release_manageability(struct e1000_hw *hw);
 123
 124 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 125
 126 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 127                 uint16_t vlan_id, int on);
 128 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 129                                  enum rte_vlan_type vlan_type,
 130                                  uint16_t tpid_id);
 131 static int eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 132
 133 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 134 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 135 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 136 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 137 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 138 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 139
 140 static int eth_igb_led_on(struct rte_eth_dev *dev);
 141 static int eth_igb_led_off(struct rte_eth_dev *dev);
 142
 143 static void igb_intr_disable(struct e1000_hw *hw);
 144 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 145 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 146                            struct ether_addr *mac_addr,
 147                            uint32_t index, uint32_t pool);
 148 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 149 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 150                 struct ether_addr *addr);
 151
 152 static void igbvf_intr_disable(struct e1000_hw *hw);
 153 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 154 static int igbvf_dev_start(struct rte_eth_dev *dev);
 155 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 156 static void igbvf_dev_close(struct rte_eth_dev *dev);
 157 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 158 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 159 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 160 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 161 static int eth_igbvf_link_update(struct e1000_hw *hw);
 162 static int eth_igbvf_stats_get(struct rte_eth_dev *dev,
 163                                 struct rte_eth_stats *rte_stats);
 164 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 165                                 struct rte_eth_xstat *xstats, unsigned n);
 166 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 167                                       struct rte_eth_xstat_name *xstats_names,
 168                                       unsigned limit);
 169 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 170 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 171                 uint16_t vlan_id, int on);
 172 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 173 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 174 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 175                 struct ether_addr *addr);
 176 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 177 static int igbvf_get_regs(struct rte_eth_dev *dev,
 178                 struct rte_dev_reg_info *regs);
 179
 180 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 181                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                    uint16_t reta_size);
 183 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 184                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 185                                   uint16_t reta_size);
 186
 187 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 188                         struct rte_eth_syn_filter *filter);
 189 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 190                         enum rte_filter_op filter_op,
 191                         void *arg);
 192 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 193                         struct rte_eth_ntuple_filter *ntuple_filter);
 194 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 195                         struct rte_eth_ntuple_filter *ntuple_filter);
 196 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 197                         struct rte_eth_flex_filter *filter);
 198 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 199                         enum rte_filter_op filter_op,
 200                         void *arg);
 201 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 202                         struct rte_eth_ntuple_filter *ntuple_filter);
 203 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 204                         struct rte_eth_ntuple_filter *ntuple_filter);
 205 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 206                         struct rte_eth_ntuple_filter *filter);
 207 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 208                                 enum rte_filter_op filter_op,
 209                                 void *arg);
 210 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 211                                 enum rte_filter_op filter_op,
 212                                 void *arg);
 213 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 214                         struct rte_eth_ethertype_filter *filter);
 215 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 216                      enum rte_filter_type filter_type,
 217                      enum rte_filter_op filter_op,
 218                      void *arg);
 219 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 220 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 221                 struct rte_dev_reg_info *regs);
 222 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 223 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 224                 struct rte_dev_eeprom_info *eeprom);
 225 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 226                 struct rte_dev_eeprom_info *eeprom);
 227 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 228                                     struct ether_addr *mc_addr_set,
 229                                     uint32_t nb_mc_addr);
 230 static int igb_timesync_enable(struct rte_eth_dev *dev);
 231 static int igb_timesync_disable(struct rte_eth_dev *dev);
 232 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 233                                           struct timespec *timestamp,
 234                                           uint32_t flags);
 235 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 236                                           struct timespec *timestamp);
 237 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 238 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 239                                   struct timespec *timestamp);
 240 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 241                                    const struct timespec *timestamp);
 242 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 243                                         uint16_t queue_id);
 244 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 245                                          uint16_t queue_id);
 246 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 247                                        uint8_t queue, uint8_t msix_vector);
 248 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 249                                uint8_t index, uint8_t offset);
 250 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 251 static void eth_igbvf_interrupt_handler(void *param);
 252 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 253 static int igb_filter_restore(struct rte_eth_dev *dev);
 254
 255 /*
 256  * Define VF Stats MACRO for Non "cleared on read" register
 257  */
 258 #define UPDATE_VF_STAT(reg, last, cur)            \
 259 {                                                 \
 260         u32 latest = E1000_READ_REG(hw, reg);     \
 261         cur += (latest - last) & UINT_MAX;        \
 262         last = latest;                            \
 263 }
 264
 265 #define IGB_FC_PAUSE_TIME 0x0680
 266 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 267 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 268
 269 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 270
 271 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 272
 273 /*
 274  * The set of PCI devices this driver supports
 275  */
 276 static const struct rte_pci_id pci_id_igb_map[] = {
 277         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 278         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 279         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 280         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 281         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 282         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 283         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 284         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 285
 286         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 287         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 288         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 289
 290         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 291         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 292         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 293         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 294         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 295         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 296
 297         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 298         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 299         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 300         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 301         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 302         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 303         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 304         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 305         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 306         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 307         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 308         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_FLASHLESS) },
 309         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES_FLASHLESS) },
 310         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 311         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 312         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 313         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 314         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 315         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 316         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 317         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 318         { .vendor_id = 0, /* sentinel */ },
 319 };
 320
 321 /*
 322  * The set of PCI devices this driver supports (for 82576&I350 VF)
 323  */
 324 static const struct rte_pci_id pci_id_igbvf_map[] = {
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 326         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 329         { .vendor_id = 0, /* sentinel */ },
 330 };
 331
 332 static const struct rte_eth_desc_lim rx_desc_lim = {
 333         .nb_max = E1000_MAX_RING_DESC,
 334         .nb_min = E1000_MIN_RING_DESC,
 335         .nb_align = IGB_RXD_ALIGN,
 336 };
 337
 338 static const struct rte_eth_desc_lim tx_desc_lim = {
 339         .nb_max = E1000_MAX_RING_DESC,
 340         .nb_min = E1000_MIN_RING_DESC,
 341         .nb_align = IGB_RXD_ALIGN,
 342         .nb_seg_max = IGB_TX_MAX_SEG,
 343         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 344 };
 345
 346 static const struct eth_dev_ops eth_igb_ops = {
 347         .dev_configure        = eth_igb_configure,
 348         .dev_start            = eth_igb_start,
 349         .dev_stop             = eth_igb_stop,
 350         .dev_set_link_up      = eth_igb_dev_set_link_up,
 351         .dev_set_link_down    = eth_igb_dev_set_link_down,
 352         .dev_close            = eth_igb_close,
 353         .promiscuous_enable   = eth_igb_promiscuous_enable,
 354         .promiscuous_disable  = eth_igb_promiscuous_disable,
 355         .allmulticast_enable  = eth_igb_allmulticast_enable,
 356         .allmulticast_disable = eth_igb_allmulticast_disable,
 357         .link_update          = eth_igb_link_update,
 358         .stats_get            = eth_igb_stats_get,
 359         .xstats_get           = eth_igb_xstats_get,
 360         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 361         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 362         .xstats_get_names     = eth_igb_xstats_get_names,
 363         .stats_reset          = eth_igb_stats_reset,
 364         .xstats_reset         = eth_igb_xstats_reset,
 365         .fw_version_get       = eth_igb_fw_version_get,
 366         .dev_infos_get        = eth_igb_infos_get,
 367         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 368         .mtu_set              = eth_igb_mtu_set,
 369         .vlan_filter_set      = eth_igb_vlan_filter_set,
 370         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 371         .vlan_offload_set     = eth_igb_vlan_offload_set,
 372         .rx_queue_setup       = eth_igb_rx_queue_setup,
 373         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 374         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 375         .rx_queue_release     = eth_igb_rx_queue_release,
 376         .rx_queue_count       = eth_igb_rx_queue_count,
 377         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 378         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 379         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 380         .tx_queue_setup       = eth_igb_tx_queue_setup,
 381         .tx_queue_release     = eth_igb_tx_queue_release,
 382         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 383         .dev_led_on           = eth_igb_led_on,
 384         .dev_led_off          = eth_igb_led_off,
 385         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 386         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 387         .mac_addr_add         = eth_igb_rar_set,
 388         .mac_addr_remove      = eth_igb_rar_clear,
 389         .mac_addr_set         = eth_igb_default_mac_addr_set,
 390         .reta_update          = eth_igb_rss_reta_update,
 391         .reta_query           = eth_igb_rss_reta_query,
 392         .rss_hash_update      = eth_igb_rss_hash_update,
 393         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 394         .filter_ctrl          = eth_igb_filter_ctrl,
 395         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 396         .rxq_info_get         = igb_rxq_info_get,
 397         .txq_info_get         = igb_txq_info_get,
 398         .timesync_enable      = igb_timesync_enable,
 399         .timesync_disable     = igb_timesync_disable,
 400         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 401         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 402         .get_reg              = eth_igb_get_regs,
 403         .get_eeprom_length    = eth_igb_get_eeprom_length,
 404         .get_eeprom           = eth_igb_get_eeprom,
 405         .set_eeprom           = eth_igb_set_eeprom,
 406         .timesync_adjust_time = igb_timesync_adjust_time,
 407         .timesync_read_time   = igb_timesync_read_time,
 408         .timesync_write_time  = igb_timesync_write_time,
 409 };
 410
 411 /*
 412  * dev_ops for virtual function, bare necessities for basic vf
 413  * operation have been implemented
 414  */
 415 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 416         .dev_configure        = igbvf_dev_configure,
 417         .dev_start            = igbvf_dev_start,
 418         .dev_stop             = igbvf_dev_stop,
 419         .dev_close            = igbvf_dev_close,
 420         .promiscuous_enable   = igbvf_promiscuous_enable,
 421         .promiscuous_disable  = igbvf_promiscuous_disable,
 422         .allmulticast_enable  = igbvf_allmulticast_enable,
 423         .allmulticast_disable = igbvf_allmulticast_disable,
 424         .link_update          = eth_igb_link_update,
 425         .stats_get            = eth_igbvf_stats_get,
 426         .xstats_get           = eth_igbvf_xstats_get,
 427         .xstats_get_names     = eth_igbvf_xstats_get_names,
 428         .stats_reset          = eth_igbvf_stats_reset,
 429         .xstats_reset         = eth_igbvf_stats_reset,
 430         .vlan_filter_set      = igbvf_vlan_filter_set,
 431         .dev_infos_get        = eth_igbvf_infos_get,
 432         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 433         .rx_queue_setup       = eth_igb_rx_queue_setup,
 434         .rx_queue_release     = eth_igb_rx_queue_release,
 435         .tx_queue_setup       = eth_igb_tx_queue_setup,
 436         .tx_queue_release     = eth_igb_tx_queue_release,
 437         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 438         .rxq_info_get         = igb_rxq_info_get,
 439         .txq_info_get         = igb_txq_info_get,
 440         .mac_addr_set         = igbvf_default_mac_addr_set,
 441         .get_reg              = igbvf_get_regs,
 442 };
 443
 444 /* store statistics names and its offset in stats structure */
 445 struct rte_igb_xstats_name_off {
 446         char name[RTE_ETH_XSTATS_NAME_SIZE];
 447         unsigned offset;
 448 };
 449
 450 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 451         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 452         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 453         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 454         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 455         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 456         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 457         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 458                 ecol)},
 459         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 460         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 461         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 462         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 463         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 464         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 465         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 466         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 467         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 468         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 469         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 470                 fcruc)},
 471         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 472         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 473         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 474         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 475         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 476                 prc1023)},
 477         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 478                 prc1522)},
 479         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 480         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 481         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 482         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 483         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 484         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 485         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 486         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 487         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 488         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 489         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 490         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 491         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 492         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 493         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 494         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 495         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 496         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 497                 ptc1023)},
 498         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 499                 ptc1522)},
 500         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 501         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 502         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 503         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 504         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 505         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 506         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 507
 508         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 509 };
 510
 511 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 512                 sizeof(rte_igb_stats_strings[0]))
 513
 514 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 515         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 516         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 517         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 518         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 519         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 520 };
 521
 522 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 523                 sizeof(rte_igbvf_stats_strings[0]))
 524
 525 /**
 526  * Atomically reads the link status information from global
 527  * structure rte_eth_dev.
 528  *
 529  * @param dev
 530  *   - Pointer to the structure rte_eth_dev to read from.
 531  *   - Pointer to the buffer to be saved with the link status.
 532  *
 533  * @return
 534  *   - On success, zero.
 535  *   - On failure, negative value.
 536  */
 537 static inline int
 538 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 539                                 struct rte_eth_link *link)
 540 {
 541         struct rte_eth_link *dst = link;
 542         struct rte_eth_link *src = &(dev->data->dev_link);
 543
 544         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 545                                         *(uint64_t *)src) == 0)
 546                 return -1;
 547
 548         return 0;
 549 }
 550
 551 /**
 552  * Atomically writes the link status information into global
 553  * structure rte_eth_dev.
 554  *
 555  * @param dev
 556  *   - Pointer to the structure rte_eth_dev to read from.
 557  *   - Pointer to the buffer to be saved with the link status.
 558  *
 559  * @return
 560  *   - On success, zero.
 561  *   - On failure, negative value.
 562  */
 563 static inline int
 564 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 565                                 struct rte_eth_link *link)
 566 {
 567         struct rte_eth_link *dst = &(dev->data->dev_link);
 568         struct rte_eth_link *src = link;
 569
 570         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 571                                         *(uint64_t *)src) == 0)
 572                 return -1;
 573
 574         return 0;
 575 }
 576
 577 static inline void
 578 igb_intr_enable(struct rte_eth_dev *dev)
 579 {
 580         struct e1000_interrupt *intr =
 581                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 582         struct e1000_hw *hw =
 583                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 584
 585         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 586         E1000_WRITE_FLUSH(hw);
 587 }
 588
 589 static void
 590 igb_intr_disable(struct e1000_hw *hw)
 591 {
 592         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 593         E1000_WRITE_FLUSH(hw);
 594 }
 595
 596 static inline void
 597 igbvf_intr_enable(struct rte_eth_dev *dev)
 598 {
 599         struct e1000_hw *hw =
 600                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 601
 602         /* only for mailbox */
 603         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 604         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 605         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 606         E1000_WRITE_FLUSH(hw);
 607 }
 608
 609 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 610 static void
 611 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 612 {
 613         uint32_t tmp = 0;
 614
 615         /* mailbox */
 616         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 617         tmp |= E1000_VTIVAR_VALID;
 618         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 619 }
 620
 621 static void
 622 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 623 {
 624         struct e1000_hw *hw =
 625                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 626
 627         /* Configure VF other cause ivar */
 628         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 629 }
 630
 631 static inline int32_t
 632 igb_pf_reset_hw(struct e1000_hw *hw)
 633 {
 634         uint32_t ctrl_ext;
 635         int32_t status;
 636
 637         status = e1000_reset_hw(hw);
 638
 639         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 640         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 641         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 642         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 643         E1000_WRITE_FLUSH(hw);
 644
 645         return status;
 646 }
 647
 648 static void
 649 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 650 {
 651         struct e1000_hw *hw =
 652                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653
 654
 655         hw->vendor_id = pci_dev->id.vendor_id;
 656         hw->device_id = pci_dev->id.device_id;
 657         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 658         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 659
 660         e1000_set_mac_type(hw);
 661
 662         /* need to check if it is a vf device below */
 663 }
 664
 665 static int
 666 igb_reset_swfw_lock(struct e1000_hw *hw)
 667 {
 668         int ret_val;
 669
 670         /*
 671          * Do mac ops initialization manually here, since we will need
 672          * some function pointers set by this call.
 673          */
 674         ret_val = e1000_init_mac_params(hw);
 675         if (ret_val)
 676                 return ret_val;
 677
 678         /*
 679          * SMBI lock should not fail in this early stage. If this is the case,
 680          * it is due to an improper exit of the application.
 681          * So force the release of the faulty lock.
 682          */
 683         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 684                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 685         }
 686         e1000_put_hw_semaphore_generic(hw);
 687
 688         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 689                 uint16_t mask;
 690
 691                 /*
 692                  * Phy lock should not fail in this early stage. If this is the case,
 693                  * it is due to an improper exit of the application.
 694                  * So force the release of the faulty lock.
 695                  */
 696                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 697                 if (hw->bus.func > E1000_FUNC_1)
 698                         mask <<= 2;
 699                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 700                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 701                                     hw->bus.func);
 702                 }
 703                 hw->mac.ops.release_swfw_sync(hw, mask);
 704
 705                 /*
 706                  * This one is more tricky since it is common to all ports; but
 707                  * swfw_sync retries last long enough (1s) to be almost sure that if
 708                  * lock can not be taken it is due to an improper lock of the
 709                  * semaphore.
 710                  */
 711                 mask = E1000_SWFW_EEP_SM;
 712                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 713                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 714                 }
 715                 hw->mac.ops.release_swfw_sync(hw, mask);
 716         }
 717
 718         return E1000_SUCCESS;
 719 }
 720
 721 /* Remove all ntuple filters of the device */
 722 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 723 {
 724         struct e1000_filter_info *filter_info =
 725                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 726         struct e1000_5tuple_filter *p_5tuple;
 727         struct e1000_2tuple_filter *p_2tuple;
 728
 729         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 730                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 731                         p_5tuple, entries);
 732                         rte_free(p_5tuple);
 733         }
 734         filter_info->fivetuple_mask = 0;
 735         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 736                 TAILQ_REMOVE(&filter_info->twotuple_list,
 737                         p_2tuple, entries);
 738                         rte_free(p_2tuple);
 739         }
 740         filter_info->twotuple_mask = 0;
 741
 742         return 0;
 743 }
 744
 745 /* Remove all flex filters of the device */
 746 static int igb_flex_filter_uninit(struct rte_eth_dev *eth_dev)
 747 {
 748         struct e1000_filter_info *filter_info =
 749                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 750         struct e1000_flex_filter *p_flex;
 751
 752         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
 753                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
 754                 rte_free(p_flex);
 755         }
 756         filter_info->flex_mask = 0;
 757
 758         return 0;
 759 }
 760
 761 static int
 762 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 763 {
 764         int error = 0;
 765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 766         struct e1000_hw *hw =
 767                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 768         struct e1000_vfta * shadow_vfta =
 769                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 770         struct e1000_filter_info *filter_info =
 771                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 772         struct e1000_adapter *adapter =
 773                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 774
 775         uint32_t ctrl_ext;
 776
 777         eth_dev->dev_ops = &eth_igb_ops;
 778         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 779         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 780         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 781
 782         /* for secondary processes, we don't initialise any further as primary
 783          * has already done this work. Only check we don't need a different
 784          * RX function */
 785         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 786                 if (eth_dev->data->scattered_rx)
 787                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 788                 return 0;
 789         }
 790
 791         rte_eth_copy_pci_info(eth_dev, pci_dev);
 792
 793         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 794
 795         igb_identify_hardware(eth_dev, pci_dev);
 796         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 797                 error = -EIO;
 798                 goto err_late;
 799         }
 800
 801         e1000_get_bus_info(hw);
 802
 803         /* Reset any pending lock */
 804         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 805                 error = -EIO;
 806                 goto err_late;
 807         }
 808
 809         /* Finish initialization */
 810         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 811                 error = -EIO;
 812                 goto err_late;
 813         }
 814
 815         hw->mac.autoneg = 1;
 816         hw->phy.autoneg_wait_to_complete = 0;
 817         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 818
 819         /* Copper options */
 820         if (hw->phy.media_type == e1000_media_type_copper) {
 821                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 822                 hw->phy.disable_polarity_correction = 0;
 823                 hw->phy.ms_type = e1000_ms_hw_default;
 824         }
 825
 826         /*
 827          * Start from a known state, this is important in reading the nvm
 828          * and mac from that.
 829          */
 830         igb_pf_reset_hw(hw);
 831
 832         /* Make sure we have a good EEPROM before we read from it */
 833         if (e1000_validate_nvm_checksum(hw) < 0) {
 834                 /*
 835                  * Some PCI-E parts fail the first check due to
 836                  * the link being in sleep state, call it again,
 837                  * if it fails a second time its a real issue.
 838                  */
 839                 if (e1000_validate_nvm_checksum(hw) < 0) {
 840                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 841                         error = -EIO;
 842                         goto err_late;
 843                 }
 844         }
 845
 846         /* Read the permanent MAC address out of the EEPROM */
 847         if (e1000_read_mac_addr(hw) != 0) {
 848                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 849                 error = -EIO;
 850                 goto err_late;
 851         }
 852
 853         /* Allocate memory for storing MAC addresses */
 854         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 855                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 856         if (eth_dev->data->mac_addrs == NULL) {
 857                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 858                                                 "store MAC addresses",
 859                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 860                 error = -ENOMEM;
 861                 goto err_late;
 862         }
 863
 864         /* Copy the permanent MAC address */
 865         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 866
 867         /* initialize the vfta */
 868         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 869
 870         /* Now initialize the hardware */
 871         if (igb_hardware_init(hw) != 0) {
 872                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 873                 rte_free(eth_dev->data->mac_addrs);
 874                 eth_dev->data->mac_addrs = NULL;
 875                 error = -ENODEV;
 876                 goto err_late;
 877         }
 878         hw->mac.get_link_status = 1;
 879         adapter->stopped = 0;
 880
 881         /* Indicate SOL/IDER usage */
 882         if (e1000_check_reset_block(hw) < 0) {
 883                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 884                                         "SOL/IDER session");
 885         }
 886
 887         /* initialize PF if max_vfs not zero */
 888         igb_pf_host_init(eth_dev);
 889
 890         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 893         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 894         E1000_WRITE_FLUSH(hw);
 895
 896         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 897                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 898                      pci_dev->id.device_id);
 899
 900         rte_intr_callback_register(&pci_dev->intr_handle,
 901                                    eth_igb_interrupt_handler,
 902                                    (void *)eth_dev);
 903
 904         /* enable uio/vfio intr/eventfd mapping */
 905         rte_intr_enable(&pci_dev->intr_handle);
 906
 907         /* enable support intr */
 908         igb_intr_enable(eth_dev);
 909
 910         /* initialize filter info */
 911         memset(filter_info, 0,
 912                sizeof(struct e1000_filter_info));
 913
 914         TAILQ_INIT(&filter_info->flex_list);
 915         TAILQ_INIT(&filter_info->twotuple_list);
 916         TAILQ_INIT(&filter_info->fivetuple_list);
 917
 918         TAILQ_INIT(&igb_filter_ntuple_list);
 919         TAILQ_INIT(&igb_filter_ethertype_list);
 920         TAILQ_INIT(&igb_filter_syn_list);
 921         TAILQ_INIT(&igb_filter_flex_list);
 922         TAILQ_INIT(&igb_filter_rss_list);
 923         TAILQ_INIT(&igb_flow_list);
 924
 925         return 0;
 926
 927 err_late:
 928         igb_hw_control_release(hw);
 929
 930         return error;
 931 }
 932
 933 static int
 934 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 935 {
 936         struct rte_pci_device *pci_dev;
 937         struct rte_intr_handle *intr_handle;
 938         struct e1000_hw *hw;
 939         struct e1000_adapter *adapter =
 940                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 941         struct e1000_filter_info *filter_info =
 942                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 943
 944         PMD_INIT_FUNC_TRACE();
 945
 946         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 947                 return -EPERM;
 948
 949         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 950         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 951         intr_handle = &pci_dev->intr_handle;
 952
 953         if (adapter->stopped == 0)
 954                 eth_igb_close(eth_dev);
 955
 956         eth_dev->dev_ops = NULL;
 957         eth_dev->rx_pkt_burst = NULL;
 958         eth_dev->tx_pkt_burst = NULL;
 959
 960         /* Reset any pending lock */
 961         igb_reset_swfw_lock(hw);
 962
 963         rte_free(eth_dev->data->mac_addrs);
 964         eth_dev->data->mac_addrs = NULL;
 965
 966         /* uninitialize PF if max_vfs not zero */
 967         igb_pf_host_uninit(eth_dev);
 968
 969         /* disable uio intr before callback unregister */
 970         rte_intr_disable(intr_handle);
 971         rte_intr_callback_unregister(intr_handle,
 972                                      eth_igb_interrupt_handler, eth_dev);
 973
 974         /* clear the SYN filter info */
 975         filter_info->syn_info = 0;
 976
 977         /* clear the ethertype filters info */
 978         filter_info->ethertype_mask = 0;
 979         memset(filter_info->ethertype_filters, 0,
 980                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 981
 982         /* clear the rss filter info */
 983         memset(&filter_info->rss_info, 0,
 984                 sizeof(struct igb_rte_flow_rss_conf));
 985
 986         /* remove all ntuple filters of the device */
 987         igb_ntuple_filter_uninit(eth_dev);
 988
 989         /* remove all flex filters of the device */
 990         igb_flex_filter_uninit(eth_dev);
 991
 992         /* clear all the filters list */
 993         igb_filterlist_flush(eth_dev);
 994
 995         return 0;
 996 }
 997
 998 /*
 999  * Virtual Function device init
1000  */
1001 static int
1002 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1003 {
1004         struct rte_pci_device *pci_dev;
1005         struct rte_intr_handle *intr_handle;
1006         struct e1000_adapter *adapter =
1007                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1008         struct e1000_hw *hw =
1009                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1010         int diag;
1011         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1012
1013         PMD_INIT_FUNC_TRACE();
1014
1015         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1016         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1017         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1018         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1019
1020         /* for secondary processes, we don't initialise any further as primary
1021          * has already done this work. Only check we don't need a different
1022          * RX function */
1023         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1024                 if (eth_dev->data->scattered_rx)
1025                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1026                 return 0;
1027         }
1028
1029         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1030         rte_eth_copy_pci_info(eth_dev, pci_dev);
1031
1032         hw->device_id = pci_dev->id.device_id;
1033         hw->vendor_id = pci_dev->id.vendor_id;
1034         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1035         adapter->stopped = 0;
1036
1037         /* Initialize the shared code (base driver) */
1038         diag = e1000_setup_init_funcs(hw, TRUE);
1039         if (diag != 0) {
1040                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1041                         diag);
1042                 return -EIO;
1043         }
1044
1045         /* init_mailbox_params */
1046         hw->mbx.ops.init_params(hw);
1047
1048         /* Disable the interrupts for VF */
1049         igbvf_intr_disable(hw);
1050
1051         diag = hw->mac.ops.reset_hw(hw);
1052
1053         /* Allocate memory for storing MAC addresses */
1054         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1055                 hw->mac.rar_entry_count, 0);
1056         if (eth_dev->data->mac_addrs == NULL) {
1057                 PMD_INIT_LOG(ERR,
1058                         "Failed to allocate %d bytes needed to store MAC "
1059                         "addresses",
1060                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1061                 return -ENOMEM;
1062         }
1063
1064         /* Generate a random MAC address, if none was assigned by PF. */
1065         if (is_zero_ether_addr(perm_addr)) {
1066                 eth_random_addr(perm_addr->addr_bytes);
1067                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1068                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1069                              "%02x:%02x:%02x:%02x:%02x:%02x",
1070                              perm_addr->addr_bytes[0],
1071                              perm_addr->addr_bytes[1],
1072                              perm_addr->addr_bytes[2],
1073                              perm_addr->addr_bytes[3],
1074                              perm_addr->addr_bytes[4],
1075                              perm_addr->addr_bytes[5]);
1076         }
1077
1078         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1079         if (diag) {
1080                 rte_free(eth_dev->data->mac_addrs);
1081                 eth_dev->data->mac_addrs = NULL;
1082                 return diag;
1083         }
1084         /* Copy the permanent MAC address */
1085         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1086                         &eth_dev->data->mac_addrs[0]);
1087
1088         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1089                      "mac.type=%s",
1090                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1091                      pci_dev->id.device_id, "igb_mac_82576_vf");
1092
1093         intr_handle = &pci_dev->intr_handle;
1094         rte_intr_callback_register(intr_handle,
1095                                    eth_igbvf_interrupt_handler, eth_dev);
1096
1097         return 0;
1098 }
1099
1100 static int
1101 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1102 {
1103         struct e1000_adapter *adapter =
1104                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1106
1107         PMD_INIT_FUNC_TRACE();
1108
1109         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1110                 return -EPERM;
1111
1112         if (adapter->stopped == 0)
1113                 igbvf_dev_close(eth_dev);
1114
1115         eth_dev->dev_ops = NULL;
1116         eth_dev->rx_pkt_burst = NULL;
1117         eth_dev->tx_pkt_burst = NULL;
1118
1119         rte_free(eth_dev->data->mac_addrs);
1120         eth_dev->data->mac_addrs = NULL;
1121
1122         /* disable uio intr before callback unregister */
1123         rte_intr_disable(&pci_dev->intr_handle);
1124         rte_intr_callback_unregister(&pci_dev->intr_handle,
1125                                      eth_igbvf_interrupt_handler,
1126                                      (void *)eth_dev);
1127
1128         return 0;
1129 }
1130
1131 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1132         struct rte_pci_device *pci_dev)
1133 {
1134         return rte_eth_dev_pci_generic_probe(pci_dev,
1135                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1136 }
1137
1138 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1139 {
1140         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1141 }
1142
1143 static struct rte_pci_driver rte_igb_pmd = {
1144         .id_table = pci_id_igb_map,
1145         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1146                      RTE_PCI_DRV_IOVA_AS_VA,
1147         .probe = eth_igb_pci_probe,
1148         .remove = eth_igb_pci_remove,
1149 };
1150
1151
1152 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1153         struct rte_pci_device *pci_dev)
1154 {
1155         return rte_eth_dev_pci_generic_probe(pci_dev,
1156                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1157 }
1158
1159 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1160 {
1161         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1162 }
1163
1164 /*
1165  * virtual function driver struct
1166  */
1167 static struct rte_pci_driver rte_igbvf_pmd = {
1168         .id_table = pci_id_igbvf_map,
1169         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1170         .probe = eth_igbvf_pci_probe,
1171         .remove = eth_igbvf_pci_remove,
1172 };
1173
1174 static void
1175 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1176 {
1177         struct e1000_hw *hw =
1178                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1180         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1181         rctl |= E1000_RCTL_VFE;
1182         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1183 }
1184
1185 static int
1186 igb_check_mq_mode(struct rte_eth_dev *dev)
1187 {
1188         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1189         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1190         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1191         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1192
1193         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1194             tx_mq_mode == ETH_MQ_TX_DCB ||
1195             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1196                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1197                 return -EINVAL;
1198         }
1199         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1200                 /* Check multi-queue mode.
1201                  * To no break software we accept ETH_MQ_RX_NONE as this might
1202                  * be used to turn off VLAN filter.
1203                  */
1204
1205                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1206                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1207                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1208                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1209                 } else {
1210                         /* Only support one queue on VFs.
1211                          * RSS together with SRIOV is not supported.
1212                          */
1213                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1214                                         " wrong mq_mode rx %d.",
1215                                         rx_mq_mode);
1216                         return -EINVAL;
1217                 }
1218                 /* TX mode is not used here, so mode might be ignored.*/
1219                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1220                         /* SRIOV only works in VMDq enable mode */
1221                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1222                                         " TX mode %d is not supported. "
1223                                         " Driver will behave as %d mode.",
1224                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1225                 }
1226
1227                 /* check valid queue number */
1228                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1229                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1230                                         " only support one queue on VFs.");
1231                         return -EINVAL;
1232                 }
1233         } else {
1234                 /* To no break software that set invalid mode, only display
1235                  * warning if invalid mode is used.
1236                  */
1237                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1238                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1239                     rx_mq_mode != ETH_MQ_RX_RSS) {
1240                         /* RSS together with VMDq not supported*/
1241                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1242                                      rx_mq_mode);
1243                         return -EINVAL;
1244                 }
1245
1246                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1247                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1248                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1249                                         " Due to txmode is meaningless in this"
1250                                         " driver, just ignore.",
1251                                         tx_mq_mode);
1252                 }
1253         }
1254         return 0;
1255 }
1256
1257 static int
1258 eth_igb_configure(struct rte_eth_dev *dev)
1259 {
1260         struct e1000_interrupt *intr =
1261                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1262         int ret;
1263
1264         PMD_INIT_FUNC_TRACE();
1265
1266         /* multipe queue mode checking */
1267         ret  = igb_check_mq_mode(dev);
1268         if (ret != 0) {
1269                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1270                             ret);
1271                 return ret;
1272         }
1273
1274         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1275         PMD_INIT_FUNC_TRACE();
1276
1277         return 0;
1278 }
1279
1280 static int
1281 eth_igb_start(struct rte_eth_dev *dev)
1282 {
1283         struct e1000_hw *hw =
1284                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1285         struct e1000_adapter *adapter =
1286                 E1000_DEV_PRIVATE(dev->data->dev_private);
1287         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1288         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289         int ret, mask;
1290         uint32_t intr_vector = 0;
1291         uint32_t ctrl_ext;
1292         uint32_t *speeds;
1293         int num_speeds;
1294         bool autoneg;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         /* disable uio/vfio intr/eventfd mapping */
1299         rte_intr_disable(intr_handle);
1300
1301         /* Power up the phy. Needed to make the link go Up */
1302         eth_igb_dev_set_link_up(dev);
1303
1304         /*
1305          * Packet Buffer Allocation (PBA)
1306          * Writing PBA sets the receive portion of the buffer
1307          * the remainder is used for the transmit buffer.
1308          */
1309         if (hw->mac.type == e1000_82575) {
1310                 uint32_t pba;
1311
1312                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1313                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1314         }
1315
1316         /* Put the address into the Receive Address Array */
1317         e1000_rar_set(hw, hw->mac.addr, 0);
1318
1319         /* Initialize the hardware */
1320         if (igb_hardware_init(hw)) {
1321                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1322                 return -EIO;
1323         }
1324         adapter->stopped = 0;
1325
1326         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1327
1328         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1329         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1330         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1331         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1332         E1000_WRITE_FLUSH(hw);
1333
1334         /* configure PF module if SRIOV enabled */
1335         igb_pf_host_configure(dev);
1336
1337         /* check and configure queue intr-vector mapping */
1338         if ((rte_intr_cap_multiple(intr_handle) ||
1339              !RTE_ETH_DEV_SRIOV(dev).active) &&
1340             dev->data->dev_conf.intr_conf.rxq != 0) {
1341                 intr_vector = dev->data->nb_rx_queues;
1342                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1343                         return -1;
1344         }
1345
1346         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1347                 intr_handle->intr_vec =
1348                         rte_zmalloc("intr_vec",
1349                                     dev->data->nb_rx_queues * sizeof(int), 0);
1350                 if (intr_handle->intr_vec == NULL) {
1351                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1352                                      " intr_vec", dev->data->nb_rx_queues);
1353                         return -ENOMEM;
1354                 }
1355         }
1356
1357         /* confiugre msix for rx interrupt */
1358         eth_igb_configure_msix_intr(dev);
1359
1360         /* Configure for OS presence */
1361         igb_init_manageability(hw);
1362
1363         eth_igb_tx_init(dev);
1364
1365         /* This can fail when allocating mbufs for descriptor rings */
1366         ret = eth_igb_rx_init(dev);
1367         if (ret) {
1368                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1369                 igb_dev_clear_queues(dev);
1370                 return ret;
1371         }
1372
1373         e1000_clear_hw_cntrs_base_generic(hw);
1374
1375         /*
1376          * VLAN Offload Settings
1377          */
1378         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1379                         ETH_VLAN_EXTEND_MASK;
1380         ret = eth_igb_vlan_offload_set(dev, mask);
1381         if (ret) {
1382                 PMD_INIT_LOG(ERR, "Unable to set vlan offload");
1383                 igb_dev_clear_queues(dev);
1384                 return ret;
1385         }
1386
1387         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1388                 /* Enable VLAN filter since VMDq always use VLAN filter */
1389                 igb_vmdq_vlan_hw_filter_enable(dev);
1390         }
1391
1392         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1393                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1394                 (hw->mac.type == e1000_i211)) {
1395                 /* Configure EITR with the maximum possible value (0xFFFF) */
1396                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1397         }
1398
1399         /* Setup link speed and duplex */
1400         speeds = &dev->data->dev_conf.link_speeds;
1401         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1402                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1403                 hw->mac.autoneg = 1;
1404         } else {
1405                 num_speeds = 0;
1406                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1407
1408                 /* Reset */
1409                 hw->phy.autoneg_advertised = 0;
1410
1411                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1412                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1413                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1414                         num_speeds = -1;
1415                         goto error_invalid_config;
1416                 }
1417                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1418                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1419                         num_speeds++;
1420                 }
1421                 if (*speeds & ETH_LINK_SPEED_10M) {
1422                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1423                         num_speeds++;
1424                 }
1425                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1426                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1427                         num_speeds++;
1428                 }
1429                 if (*speeds & ETH_LINK_SPEED_100M) {
1430                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1431                         num_speeds++;
1432                 }
1433                 if (*speeds & ETH_LINK_SPEED_1G) {
1434                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1435                         num_speeds++;
1436                 }
1437                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1438                         goto error_invalid_config;
1439
1440                 /* Set/reset the mac.autoneg based on the link speed,
1441                  * fixed or not
1442                  */
1443                 if (!autoneg) {
1444                         hw->mac.autoneg = 0;
1445                         hw->mac.forced_speed_duplex =
1446                                         hw->phy.autoneg_advertised;
1447                 } else {
1448                         hw->mac.autoneg = 1;
1449                 }
1450         }
1451
1452         e1000_setup_link(hw);
1453
1454         if (rte_intr_allow_others(intr_handle)) {
1455                 /* check if lsc interrupt is enabled */
1456                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1457                         eth_igb_lsc_interrupt_setup(dev, TRUE);
1458                 else
1459                         eth_igb_lsc_interrupt_setup(dev, FALSE);
1460         } else {
1461                 rte_intr_callback_unregister(intr_handle,
1462                                              eth_igb_interrupt_handler,
1463                                              (void *)dev);
1464                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1465                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1466                                      " no intr multiplex");
1467         }
1468
1469         /* check if rxq interrupt is enabled */
1470         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1471             rte_intr_dp_is_en(intr_handle))
1472                 eth_igb_rxq_interrupt_setup(dev);
1473
1474         /* enable uio/vfio intr/eventfd mapping */
1475         rte_intr_enable(intr_handle);
1476
1477         /* resume enabled intr since hw reset */
1478         igb_intr_enable(dev);
1479
1480         /* restore all types filter */
1481         igb_filter_restore(dev);
1482
1483         PMD_INIT_LOG(DEBUG, "<<");
1484
1485         return 0;
1486
1487 error_invalid_config:
1488         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1489                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1490         igb_dev_clear_queues(dev);
1491         return -EINVAL;
1492 }
1493
1494 /*********************************************************************
1495  *
1496  *  This routine disables all traffic on the adapter by issuing a
1497  *  global reset on the MAC.
1498  *
1499  **********************************************************************/
1500 static void
1501 eth_igb_stop(struct rte_eth_dev *dev)
1502 {
1503         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1505         struct rte_eth_link link;
1506         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1507
1508         igb_intr_disable(hw);
1509
1510         /* disable intr eventfd mapping */
1511         rte_intr_disable(intr_handle);
1512
1513         igb_pf_reset_hw(hw);
1514         E1000_WRITE_REG(hw, E1000_WUC, 0);
1515
1516         /* Set bit for Go Link disconnect */
1517         if (hw->mac.type >= e1000_82580) {
1518                 uint32_t phpm_reg;
1519
1520                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1521                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1522                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1523         }
1524
1525         /* Power down the phy. Needed to make the link go Down */
1526         eth_igb_dev_set_link_down(dev);
1527
1528         igb_dev_clear_queues(dev);
1529
1530         /* clear the recorded link status */
1531         memset(&link, 0, sizeof(link));
1532         rte_igb_dev_atomic_write_link_status(dev, &link);
1533
1534         if (!rte_intr_allow_others(intr_handle))
1535                 /* resume to the default handler */
1536                 rte_intr_callback_register(intr_handle,
1537                                            eth_igb_interrupt_handler,
1538                                            (void *)dev);
1539
1540         /* Clean datapath event and queue/vec mapping */
1541         rte_intr_efd_disable(intr_handle);
1542         if (intr_handle->intr_vec != NULL) {
1543                 rte_free(intr_handle->intr_vec);
1544                 intr_handle->intr_vec = NULL;
1545         }
1546 }
1547
1548 static int
1549 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1550 {
1551         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1552
1553         if (hw->phy.media_type == e1000_media_type_copper)
1554                 e1000_power_up_phy(hw);
1555         else
1556                 e1000_power_up_fiber_serdes_link(hw);
1557
1558         return 0;
1559 }
1560
1561 static int
1562 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1563 {
1564         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565
1566         if (hw->phy.media_type == e1000_media_type_copper)
1567                 e1000_power_down_phy(hw);
1568         else
1569                 e1000_shutdown_fiber_serdes_link(hw);
1570
1571         return 0;
1572 }
1573
1574 static void
1575 eth_igb_close(struct rte_eth_dev *dev)
1576 {
1577         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1578         struct e1000_adapter *adapter =
1579                 E1000_DEV_PRIVATE(dev->data->dev_private);
1580         struct rte_eth_link link;
1581         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1582         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1583
1584         eth_igb_stop(dev);
1585         adapter->stopped = 1;
1586
1587         e1000_phy_hw_reset(hw);
1588         igb_release_manageability(hw);
1589         igb_hw_control_release(hw);
1590
1591         /* Clear bit for Go Link disconnect */
1592         if (hw->mac.type >= e1000_82580) {
1593                 uint32_t phpm_reg;
1594
1595                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1596                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1597                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1598         }
1599
1600         igb_dev_free_queues(dev);
1601
1602         if (intr_handle->intr_vec) {
1603                 rte_free(intr_handle->intr_vec);
1604                 intr_handle->intr_vec = NULL;
1605         }
1606
1607         memset(&link, 0, sizeof(link));
1608         rte_igb_dev_atomic_write_link_status(dev, &link);
1609 }
1610
1611 static int
1612 igb_get_rx_buffer_size(struct e1000_hw *hw)
1613 {
1614         uint32_t rx_buf_size;
1615         if (hw->mac.type == e1000_82576) {
1616                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1617         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1618                 /* PBS needs to be translated according to a lookup table */
1619                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1620                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1621                 rx_buf_size = (rx_buf_size << 10);
1622         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1623                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1624         } else {
1625                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1626         }
1627
1628         return rx_buf_size;
1629 }
1630
1631 /*********************************************************************
1632  *
1633  *  Initialize the hardware
1634  *
1635  **********************************************************************/
1636 static int
1637 igb_hardware_init(struct e1000_hw *hw)
1638 {
1639         uint32_t rx_buf_size;
1640         int diag;
1641
1642         /* Let the firmware know the OS is in control */
1643         igb_hw_control_acquire(hw);
1644
1645         /*
1646          * These parameters control the automatic generation (Tx) and
1647          * response (Rx) to Ethernet PAUSE frames.
1648          * - High water mark should allow for at least two standard size (1518)
1649          *   frames to be received after sending an XOFF.
1650          * - Low water mark works best when it is very near the high water mark.
1651          *   This allows the receiver to restart by sending XON when it has
1652          *   drained a bit. Here we use an arbitrary value of 1500 which will
1653          *   restart after one full frame is pulled from the buffer. There
1654          *   could be several smaller frames in the buffer and if so they will
1655          *   not trigger the XON until their total number reduces the buffer
1656          *   by 1500.
1657          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1658          */
1659         rx_buf_size = igb_get_rx_buffer_size(hw);
1660
1661         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1662         hw->fc.low_water = hw->fc.high_water - 1500;
1663         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1664         hw->fc.send_xon = 1;
1665
1666         /* Set Flow control, use the tunable location if sane */
1667         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1668                 hw->fc.requested_mode = igb_fc_setting;
1669         else
1670                 hw->fc.requested_mode = e1000_fc_none;
1671
1672         /* Issue a global reset */
1673         igb_pf_reset_hw(hw);
1674         E1000_WRITE_REG(hw, E1000_WUC, 0);
1675
1676         diag = e1000_init_hw(hw);
1677         if (diag < 0)
1678                 return diag;
1679
1680         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1681         e1000_get_phy_info(hw);
1682         e1000_check_for_link(hw);
1683
1684         return 0;
1685 }
1686
1687 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1688 static void
1689 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1690 {
1691         int pause_frames;
1692
1693         uint64_t old_gprc  = stats->gprc;
1694         uint64_t old_gptc  = stats->gptc;
1695         uint64_t old_tpr   = stats->tpr;
1696         uint64_t old_tpt   = stats->tpt;
1697         uint64_t old_rpthc = stats->rpthc;
1698         uint64_t old_hgptc = stats->hgptc;
1699
1700         if(hw->phy.media_type == e1000_media_type_copper ||
1701             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1702                 stats->symerrs +=
1703                     E1000_READ_REG(hw,E1000_SYMERRS);
1704                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1705         }
1706
1707         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1708         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1709         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1710         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1711
1712         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1713         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1714         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1715         stats->dc += E1000_READ_REG(hw, E1000_DC);
1716         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1717         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1718         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1719         /*
1720         ** For watchdog management we need to know if we have been
1721         ** paused during the last interval, so capture that here.
1722         */
1723         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1724         stats->xoffrxc += pause_frames;
1725         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1726         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1727         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1728         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1729         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1730         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1731         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1732         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1733         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1734         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1735         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1736         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1737
1738         /* For the 64-bit byte counters the low dword must be read first. */
1739         /* Both registers clear on the read of the high dword */
1740
1741         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1742         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1743         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1744         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1745         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1746         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1747         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1748
1749         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1750         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1751         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1752         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1753         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1754
1755         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1756         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1757
1758         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1759         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1760         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1761         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1762         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1763         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1764
1765         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1766         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1767         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1768         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1769         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1770         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1771         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1772         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1773
1774         /* Interrupt Counts */
1775
1776         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1777         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1778         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1779         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1780         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1781         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1782         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1783         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1784         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1785
1786         /* Host to Card Statistics */
1787
1788         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1789         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1790         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1791         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1792         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1793         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1794         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1795         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1796         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1797         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1798         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1799         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1800         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1801         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1802         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1803         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1804
1805         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1806         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1807         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1808         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1809         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1810         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1811 }
1812
1813 static int
1814 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1815 {
1816         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817         struct e1000_hw_stats *stats =
1818                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1819
1820         igb_read_stats_registers(hw, stats);
1821
1822         if (rte_stats == NULL)
1823                 return -EINVAL;
1824
1825         /* Rx Errors */
1826         rte_stats->imissed = stats->mpc;
1827         rte_stats->ierrors = stats->crcerrs +
1828                              stats->rlec + stats->ruc + stats->roc +
1829                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1830
1831         /* Tx Errors */
1832         rte_stats->oerrors = stats->ecol + stats->latecol;
1833
1834         rte_stats->ipackets = stats->gprc;
1835         rte_stats->opackets = stats->gptc;
1836         rte_stats->ibytes   = stats->gorc;
1837         rte_stats->obytes   = stats->gotc;
1838         return 0;
1839 }
1840
1841 static void
1842 eth_igb_stats_reset(struct rte_eth_dev *dev)
1843 {
1844         struct e1000_hw_stats *hw_stats =
1845                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1846
1847         /* HW registers are cleared on read */
1848         eth_igb_stats_get(dev, NULL);
1849
1850         /* Reset software totals */
1851         memset(hw_stats, 0, sizeof(*hw_stats));
1852 }
1853
1854 static void
1855 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1856 {
1857         struct e1000_hw_stats *stats =
1858                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1859
1860         /* HW registers are cleared on read */
1861         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1862
1863         /* Reset software totals */
1864         memset(stats, 0, sizeof(*stats));
1865 }
1866
1867 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1868         struct rte_eth_xstat_name *xstats_names,
1869         __rte_unused unsigned int size)
1870 {
1871         unsigned i;
1872
1873         if (xstats_names == NULL)
1874                 return IGB_NB_XSTATS;
1875
1876         /* Note: limit checked in rte_eth_xstats_names() */
1877
1878         for (i = 0; i < IGB_NB_XSTATS; i++) {
1879                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1880                          "%s", rte_igb_stats_strings[i].name);
1881         }
1882
1883         return IGB_NB_XSTATS;
1884 }
1885
1886 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1887                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1888                 unsigned int limit)
1889 {
1890         unsigned int i;
1891
1892         if (!ids) {
1893                 if (xstats_names == NULL)
1894                         return IGB_NB_XSTATS;
1895
1896                 for (i = 0; i < IGB_NB_XSTATS; i++)
1897                         snprintf(xstats_names[i].name,
1898                                         sizeof(xstats_names[i].name),
1899                                         "%s", rte_igb_stats_strings[i].name);
1900
1901                 return IGB_NB_XSTATS;
1902
1903         } else {
1904                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1905
1906                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1907                                 IGB_NB_XSTATS);
1908
1909                 for (i = 0; i < limit; i++) {
1910                         if (ids[i] >= IGB_NB_XSTATS) {
1911                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1912                                 return -1;
1913                         }
1914                         strcpy(xstats_names[i].name,
1915                                         xstats_names_copy[ids[i]].name);
1916                 }
1917                 return limit;
1918         }
1919 }
1920
1921 static int
1922 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1923                    unsigned n)
1924 {
1925         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct e1000_hw_stats *hw_stats =
1927                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1928         unsigned i;
1929
1930         if (n < IGB_NB_XSTATS)
1931                 return IGB_NB_XSTATS;
1932
1933         igb_read_stats_registers(hw, hw_stats);
1934
1935         /* If this is a reset xstats is NULL, and we have cleared the
1936          * registers by reading them.
1937          */
1938         if (!xstats)
1939                 return 0;
1940
1941         /* Extended stats */
1942         for (i = 0; i < IGB_NB_XSTATS; i++) {
1943                 xstats[i].id = i;
1944                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1945                         rte_igb_stats_strings[i].offset);
1946         }
1947
1948         return IGB_NB_XSTATS;
1949 }
1950
1951 static int
1952 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1953                 uint64_t *values, unsigned int n)
1954 {
1955         unsigned int i;
1956
1957         if (!ids) {
1958                 struct e1000_hw *hw =
1959                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1960                 struct e1000_hw_stats *hw_stats =
1961                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1962
1963                 if (n < IGB_NB_XSTATS)
1964                         return IGB_NB_XSTATS;
1965
1966                 igb_read_stats_registers(hw, hw_stats);
1967
1968                 /* If this is a reset xstats is NULL, and we have cleared the
1969                  * registers by reading them.
1970                  */
1971                 if (!values)
1972                         return 0;
1973
1974                 /* Extended stats */
1975                 for (i = 0; i < IGB_NB_XSTATS; i++)
1976                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1977                                         rte_igb_stats_strings[i].offset);
1978
1979                 return IGB_NB_XSTATS;
1980
1981         } else {
1982                 uint64_t values_copy[IGB_NB_XSTATS];
1983
1984                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1985                                 IGB_NB_XSTATS);
1986
1987                 for (i = 0; i < n; i++) {
1988                         if (ids[i] >= IGB_NB_XSTATS) {
1989                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1990                                 return -1;
1991                         }
1992                         values[i] = values_copy[ids[i]];
1993                 }
1994                 return n;
1995         }
1996 }
1997
1998 static void
1999 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2000 {
2001         /* Good Rx packets, include VF loopback */
2002         UPDATE_VF_STAT(E1000_VFGPRC,
2003             hw_stats->last_gprc, hw_stats->gprc);
2004
2005         /* Good Rx octets, include VF loopback */
2006         UPDATE_VF_STAT(E1000_VFGORC,
2007             hw_stats->last_gorc, hw_stats->gorc);
2008
2009         /* Good Tx packets, include VF loopback */
2010         UPDATE_VF_STAT(E1000_VFGPTC,
2011             hw_stats->last_gptc, hw_stats->gptc);
2012
2013         /* Good Tx octets, include VF loopback */
2014         UPDATE_VF_STAT(E1000_VFGOTC,
2015             hw_stats->last_gotc, hw_stats->gotc);
2016
2017         /* Rx Multicst packets */
2018         UPDATE_VF_STAT(E1000_VFMPRC,
2019             hw_stats->last_mprc, hw_stats->mprc);
2020
2021         /* Good Rx loopback packets */
2022         UPDATE_VF_STAT(E1000_VFGPRLBC,
2023             hw_stats->last_gprlbc, hw_stats->gprlbc);
2024
2025         /* Good Rx loopback octets */
2026         UPDATE_VF_STAT(E1000_VFGORLBC,
2027             hw_stats->last_gorlbc, hw_stats->gorlbc);
2028
2029         /* Good Tx loopback packets */
2030         UPDATE_VF_STAT(E1000_VFGPTLBC,
2031             hw_stats->last_gptlbc, hw_stats->gptlbc);
2032
2033         /* Good Tx loopback octets */
2034         UPDATE_VF_STAT(E1000_VFGOTLBC,
2035             hw_stats->last_gotlbc, hw_stats->gotlbc);
2036 }
2037
2038 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2039                                      struct rte_eth_xstat_name *xstats_names,
2040                                      __rte_unused unsigned limit)
2041 {
2042         unsigned i;
2043
2044         if (xstats_names != NULL)
2045                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2046                         snprintf(xstats_names[i].name,
2047                                 sizeof(xstats_names[i].name), "%s",
2048                                 rte_igbvf_stats_strings[i].name);
2049                 }
2050         return IGBVF_NB_XSTATS;
2051 }
2052
2053 static int
2054 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2055                      unsigned n)
2056 {
2057         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2059                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2060         unsigned i;
2061
2062         if (n < IGBVF_NB_XSTATS)
2063                 return IGBVF_NB_XSTATS;
2064
2065         igbvf_read_stats_registers(hw, hw_stats);
2066
2067         if (!xstats)
2068                 return 0;
2069
2070         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2071                 xstats[i].id = i;
2072                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2073                         rte_igbvf_stats_strings[i].offset);
2074         }
2075
2076         return IGBVF_NB_XSTATS;
2077 }
2078
2079 static int
2080 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2081 {
2082         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2084                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2085
2086         igbvf_read_stats_registers(hw, hw_stats);
2087
2088         if (rte_stats == NULL)
2089                 return -EINVAL;
2090
2091         rte_stats->ipackets = hw_stats->gprc;
2092         rte_stats->ibytes = hw_stats->gorc;
2093         rte_stats->opackets = hw_stats->gptc;
2094         rte_stats->obytes = hw_stats->gotc;
2095         return 0;
2096 }
2097
2098 static void
2099 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2100 {
2101         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2102                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2103
2104         /* Sync HW register to the last stats */
2105         eth_igbvf_stats_get(dev, NULL);
2106
2107         /* reset HW current stats*/
2108         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2109                offsetof(struct e1000_vf_stats, gprc));
2110 }
2111
2112 static int
2113 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2114                        size_t fw_size)
2115 {
2116         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct e1000_fw_version fw;
2118         int ret;
2119
2120         e1000_get_fw_version(hw, &fw);
2121
2122         switch (hw->mac.type) {
2123         case e1000_i210:
2124         case e1000_i211:
2125                 if (!(e1000_get_flash_presence_i210(hw))) {
2126                         ret = snprintf(fw_version, fw_size,
2127                                  "%2d.%2d-%d",
2128                                  fw.invm_major, fw.invm_minor,
2129                                  fw.invm_img_type);
2130                         break;
2131                 }
2132                 /* fall through */
2133         default:
2134                 /* if option rom is valid, display its version too */
2135                 if (fw.or_valid) {
2136                         ret = snprintf(fw_version, fw_size,
2137                                  "%d.%d, 0x%08x, %d.%d.%d",
2138                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2139                                  fw.or_major, fw.or_build, fw.or_patch);
2140                 /* no option rom */
2141                 } else {
2142                         if (fw.etrack_id != 0X0000) {
2143                                 ret = snprintf(fw_version, fw_size,
2144                                          "%d.%d, 0x%08x",
2145                                          fw.eep_major, fw.eep_minor,
2146                                          fw.etrack_id);
2147                         } else {
2148                                 ret = snprintf(fw_version, fw_size,
2149                                          "%d.%d.%d",
2150                                          fw.eep_major, fw.eep_minor,
2151                                          fw.eep_build);
2152                         }
2153                 }
2154                 break;
2155         }
2156
2157         ret += 1; /* add the size of '\0' */
2158         if (fw_size < (u32)ret)
2159                 return ret;
2160         else
2161                 return 0;
2162 }
2163
2164 static void
2165 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2166 {
2167         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168
2169         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2170         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2171         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2172         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2173         dev_info->rx_offload_capa =
2174                 DEV_RX_OFFLOAD_VLAN_STRIP |
2175                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2176                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2177                 DEV_RX_OFFLOAD_TCP_CKSUM;
2178         dev_info->tx_offload_capa =
2179                 DEV_TX_OFFLOAD_VLAN_INSERT |
2180                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2181                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2182                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2183                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2184                 DEV_TX_OFFLOAD_TCP_TSO;
2185
2186         switch (hw->mac.type) {
2187         case e1000_82575:
2188                 dev_info->max_rx_queues = 4;
2189                 dev_info->max_tx_queues = 4;
2190                 dev_info->max_vmdq_pools = 0;
2191                 break;
2192
2193         case e1000_82576:
2194                 dev_info->max_rx_queues = 16;
2195                 dev_info->max_tx_queues = 16;
2196                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2197                 dev_info->vmdq_queue_num = 16;
2198                 break;
2199
2200         case e1000_82580:
2201                 dev_info->max_rx_queues = 8;
2202                 dev_info->max_tx_queues = 8;
2203                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2204                 dev_info->vmdq_queue_num = 8;
2205                 break;
2206
2207         case e1000_i350:
2208                 dev_info->max_rx_queues = 8;
2209                 dev_info->max_tx_queues = 8;
2210                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2211                 dev_info->vmdq_queue_num = 8;
2212                 break;
2213
2214         case e1000_i354:
2215                 dev_info->max_rx_queues = 8;
2216                 dev_info->max_tx_queues = 8;
2217                 break;
2218
2219         case e1000_i210:
2220                 dev_info->max_rx_queues = 4;
2221                 dev_info->max_tx_queues = 4;
2222                 dev_info->max_vmdq_pools = 0;
2223                 break;
2224
2225         case e1000_i211:
2226                 dev_info->max_rx_queues = 2;
2227                 dev_info->max_tx_queues = 2;
2228                 dev_info->max_vmdq_pools = 0;
2229                 break;
2230
2231         default:
2232                 /* Should not happen */
2233                 break;
2234         }
2235         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2236         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2237         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2238
2239         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2240                 .rx_thresh = {
2241                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2242                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2243                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2244                 },
2245                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2246                 .rx_drop_en = 0,
2247         };
2248
2249         dev_info->default_txconf = (struct rte_eth_txconf) {
2250                 .tx_thresh = {
2251                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2252                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2253                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2254                 },
2255                 .txq_flags = 0,
2256         };
2257
2258         dev_info->rx_desc_lim = rx_desc_lim;
2259         dev_info->tx_desc_lim = tx_desc_lim;
2260
2261         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2262                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2263                         ETH_LINK_SPEED_1G;
2264 }
2265
2266 static const uint32_t *
2267 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2268 {
2269         static const uint32_t ptypes[] = {
2270                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2271                 RTE_PTYPE_L2_ETHER,
2272                 RTE_PTYPE_L3_IPV4,
2273                 RTE_PTYPE_L3_IPV4_EXT,
2274                 RTE_PTYPE_L3_IPV6,
2275                 RTE_PTYPE_L3_IPV6_EXT,
2276                 RTE_PTYPE_L4_TCP,
2277                 RTE_PTYPE_L4_UDP,
2278                 RTE_PTYPE_L4_SCTP,
2279                 RTE_PTYPE_TUNNEL_IP,
2280                 RTE_PTYPE_INNER_L3_IPV6,
2281                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2282                 RTE_PTYPE_INNER_L4_TCP,
2283                 RTE_PTYPE_INNER_L4_UDP,
2284                 RTE_PTYPE_UNKNOWN
2285         };
2286
2287         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2288             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2289                 return ptypes;
2290         return NULL;
2291 }
2292
2293 static void
2294 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2295 {
2296         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297
2298         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2299         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2300         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2301         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2302         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2303                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2304                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2305                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2306         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2307                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2308                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2309                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2310                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2311                                 DEV_TX_OFFLOAD_TCP_TSO;
2312         switch (hw->mac.type) {
2313         case e1000_vfadapt:
2314                 dev_info->max_rx_queues = 2;
2315                 dev_info->max_tx_queues = 2;
2316                 break;
2317         case e1000_vfadapt_i350:
2318                 dev_info->max_rx_queues = 1;
2319                 dev_info->max_tx_queues = 1;
2320                 break;
2321         default:
2322                 /* Should not happen */
2323                 break;
2324         }
2325
2326         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2327                 .rx_thresh = {
2328                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2329                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2330                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2331                 },
2332                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2333                 .rx_drop_en = 0,
2334         };
2335
2336         dev_info->default_txconf = (struct rte_eth_txconf) {
2337                 .tx_thresh = {
2338                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2339                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2340                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2341                 },
2342                 .txq_flags = 0,
2343         };
2344
2345         dev_info->rx_desc_lim = rx_desc_lim;
2346         dev_info->tx_desc_lim = tx_desc_lim;
2347 }
2348
2349 /* return 0 means link status changed, -1 means not changed */
2350 static int
2351 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2352 {
2353         struct e1000_hw *hw =
2354                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2355         struct rte_eth_link link, old;
2356         int link_check, count;
2357
2358         link_check = 0;
2359         hw->mac.get_link_status = 1;
2360
2361         /* possible wait-to-complete in up to 9 seconds */
2362         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2363                 /* Read the real link status */
2364                 switch (hw->phy.media_type) {
2365                 case e1000_media_type_copper:
2366                         /* Do the work to read phy */
2367                         e1000_check_for_link(hw);
2368                         link_check = !hw->mac.get_link_status;
2369                         break;
2370
2371                 case e1000_media_type_fiber:
2372                         e1000_check_for_link(hw);
2373                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2374                                       E1000_STATUS_LU);
2375                         break;
2376
2377                 case e1000_media_type_internal_serdes:
2378                         e1000_check_for_link(hw);
2379                         link_check = hw->mac.serdes_has_link;
2380                         break;
2381
2382                 /* VF device is type_unknown */
2383                 case e1000_media_type_unknown:
2384                         eth_igbvf_link_update(hw);
2385                         link_check = !hw->mac.get_link_status;
2386                         break;
2387
2388                 default:
2389                         break;
2390                 }
2391                 if (link_check || wait_to_complete == 0)
2392                         break;
2393                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2394         }
2395         memset(&link, 0, sizeof(link));
2396         rte_igb_dev_atomic_read_link_status(dev, &link);
2397         old = link;
2398
2399         /* Now we check if a transition has happened */
2400         if (link_check) {
2401                 uint16_t duplex, speed;
2402                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2403                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2404                                 ETH_LINK_FULL_DUPLEX :
2405                                 ETH_LINK_HALF_DUPLEX;
2406                 link.link_speed = speed;
2407                 link.link_status = ETH_LINK_UP;
2408                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2409                                 ETH_LINK_SPEED_FIXED);
2410         } else if (!link_check) {
2411                 link.link_speed = 0;
2412                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2413                 link.link_status = ETH_LINK_DOWN;
2414                 link.link_autoneg = ETH_LINK_FIXED;
2415         }
2416         rte_igb_dev_atomic_write_link_status(dev, &link);
2417
2418         /* not changed */
2419         if (old.link_status == link.link_status)
2420                 return -1;
2421
2422         /* changed */
2423         return 0;
2424 }
2425
2426 /*
2427  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2428  * For ASF and Pass Through versions of f/w this means
2429  * that the driver is loaded.
2430  */
2431 static void
2432 igb_hw_control_acquire(struct e1000_hw *hw)
2433 {
2434         uint32_t ctrl_ext;
2435
2436         /* Let firmware know the driver has taken over */
2437         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2438         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2439 }
2440
2441 /*
2442  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2443  * For ASF and Pass Through versions of f/w this means that the
2444  * driver is no longer loaded.
2445  */
2446 static void
2447 igb_hw_control_release(struct e1000_hw *hw)
2448 {
2449         uint32_t ctrl_ext;
2450
2451         /* Let firmware taken over control of h/w */
2452         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2453         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2454                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2455 }
2456
2457 /*
2458  * Bit of a misnomer, what this really means is
2459  * to enable OS management of the system... aka
2460  * to disable special hardware management features.
2461  */
2462 static void
2463 igb_init_manageability(struct e1000_hw *hw)
2464 {
2465         if (e1000_enable_mng_pass_thru(hw)) {
2466                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2467                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2468
2469                 /* disable hardware interception of ARP */
2470                 manc &= ~(E1000_MANC_ARP_EN);
2471
2472                 /* enable receiving management packets to the host */
2473                 manc |= E1000_MANC_EN_MNG2HOST;
2474                 manc2h |= 1 << 5;  /* Mng Port 623 */
2475                 manc2h |= 1 << 6;  /* Mng Port 664 */
2476                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2477                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2478         }
2479 }
2480
2481 static void
2482 igb_release_manageability(struct e1000_hw *hw)
2483 {
2484         if (e1000_enable_mng_pass_thru(hw)) {
2485                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2486
2487                 manc |= E1000_MANC_ARP_EN;
2488                 manc &= ~E1000_MANC_EN_MNG2HOST;
2489
2490                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2491         }
2492 }
2493
2494 static void
2495 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2496 {
2497         struct e1000_hw *hw =
2498                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2499         uint32_t rctl;
2500
2501         rctl = E1000_READ_REG(hw, E1000_RCTL);
2502         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2503         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2504 }
2505
2506 static void
2507 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2508 {
2509         struct e1000_hw *hw =
2510                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         uint32_t rctl;
2512
2513         rctl = E1000_READ_REG(hw, E1000_RCTL);
2514         rctl &= (~E1000_RCTL_UPE);
2515         if (dev->data->all_multicast == 1)
2516                 rctl |= E1000_RCTL_MPE;
2517         else
2518                 rctl &= (~E1000_RCTL_MPE);
2519         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2520 }
2521
2522 static void
2523 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2524 {
2525         struct e1000_hw *hw =
2526                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         uint32_t rctl;
2528
2529         rctl = E1000_READ_REG(hw, E1000_RCTL);
2530         rctl |= E1000_RCTL_MPE;
2531         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2532 }
2533
2534 static void
2535 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2536 {
2537         struct e1000_hw *hw =
2538                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         uint32_t rctl;
2540
2541         if (dev->data->promiscuous == 1)
2542                 return; /* must remain in all_multicast mode */
2543         rctl = E1000_READ_REG(hw, E1000_RCTL);
2544         rctl &= (~E1000_RCTL_MPE);
2545         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2546 }
2547
2548 static int
2549 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2550 {
2551         struct e1000_hw *hw =
2552                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         struct e1000_vfta * shadow_vfta =
2554                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2555         uint32_t vfta;
2556         uint32_t vid_idx;
2557         uint32_t vid_bit;
2558
2559         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2560                               E1000_VFTA_ENTRY_MASK);
2561         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2562         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2563         if (on)
2564                 vfta |= vid_bit;
2565         else
2566                 vfta &= ~vid_bit;
2567         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2568
2569         /* update local VFTA copy */
2570         shadow_vfta->vfta[vid_idx] = vfta;
2571
2572         return 0;
2573 }
2574
2575 static int
2576 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2577                       enum rte_vlan_type vlan_type,
2578                       uint16_t tpid)
2579 {
2580         struct e1000_hw *hw =
2581                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2582         uint32_t reg, qinq;
2583
2584         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2585         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2586
2587         /* only outer TPID of double VLAN can be configured*/
2588         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2589                 reg = E1000_READ_REG(hw, E1000_VET);
2590                 reg = (reg & (~E1000_VET_VET_EXT)) |
2591                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2592                 E1000_WRITE_REG(hw, E1000_VET, reg);
2593
2594                 return 0;
2595         }
2596
2597         /* all other TPID values are read-only*/
2598         PMD_DRV_LOG(ERR, "Not supported");
2599
2600         return -ENOTSUP;
2601 }
2602
2603 static void
2604 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2605 {
2606         struct e1000_hw *hw =
2607                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2608         uint32_t reg;
2609
2610         /* Filter Table Disable */
2611         reg = E1000_READ_REG(hw, E1000_RCTL);
2612         reg &= ~E1000_RCTL_CFIEN;
2613         reg &= ~E1000_RCTL_VFE;
2614         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2615 }
2616
2617 static void
2618 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2619 {
2620         struct e1000_hw *hw =
2621                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2622         struct e1000_vfta * shadow_vfta =
2623                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2624         uint32_t reg;
2625         int i;
2626
2627         /* Filter Table Enable, CFI not used for packet acceptance */
2628         reg = E1000_READ_REG(hw, E1000_RCTL);
2629         reg &= ~E1000_RCTL_CFIEN;
2630         reg |= E1000_RCTL_VFE;
2631         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2632
2633         /* restore VFTA table */
2634         for (i = 0; i < IGB_VFTA_SIZE; i++)
2635                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2636 }
2637
2638 static void
2639 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2640 {
2641         struct e1000_hw *hw =
2642                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2643         uint32_t reg;
2644
2645         /* VLAN Mode Disable */
2646         reg = E1000_READ_REG(hw, E1000_CTRL);
2647         reg &= ~E1000_CTRL_VME;
2648         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2649 }
2650
2651 static void
2652 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2653 {
2654         struct e1000_hw *hw =
2655                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         uint32_t reg;
2657
2658         /* VLAN Mode Enable */
2659         reg = E1000_READ_REG(hw, E1000_CTRL);
2660         reg |= E1000_CTRL_VME;
2661         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2662 }
2663
2664 static void
2665 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2666 {
2667         struct e1000_hw *hw =
2668                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669         uint32_t reg;
2670
2671         /* CTRL_EXT: Extended VLAN */
2672         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2673         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2674         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2675
2676         /* Update maximum packet length */
2677         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2678                 E1000_WRITE_REG(hw, E1000_RLPML,
2679                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2680                                                 VLAN_TAG_SIZE);
2681 }
2682
2683 static void
2684 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2685 {
2686         struct e1000_hw *hw =
2687                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688         uint32_t reg;
2689
2690         /* CTRL_EXT: Extended VLAN */
2691         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2692         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2693         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2694
2695         /* Update maximum packet length */
2696         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2697                 E1000_WRITE_REG(hw, E1000_RLPML,
2698                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2699                                                 2 * VLAN_TAG_SIZE);
2700 }
2701
2702 static int
2703 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2704 {
2705         if(mask & ETH_VLAN_STRIP_MASK){
2706                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2707                         igb_vlan_hw_strip_enable(dev);
2708                 else
2709                         igb_vlan_hw_strip_disable(dev);
2710         }
2711
2712         if(mask & ETH_VLAN_FILTER_MASK){
2713                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2714                         igb_vlan_hw_filter_enable(dev);
2715                 else
2716                         igb_vlan_hw_filter_disable(dev);
2717         }
2718
2719         if(mask & ETH_VLAN_EXTEND_MASK){
2720                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2721                         igb_vlan_hw_extend_enable(dev);
2722                 else
2723                         igb_vlan_hw_extend_disable(dev);
2724         }
2725
2726         return 0;
2727 }
2728
2729
2730 /**
2731  * It enables the interrupt mask and then enable the interrupt.
2732  *
2733  * @param dev
2734  *  Pointer to struct rte_eth_dev.
2735  * @param on
2736  *  Enable or Disable
2737  *
2738  * @return
2739  *  - On success, zero.
2740  *  - On failure, a negative value.
2741  */
2742 static int
2743 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2744 {
2745         struct e1000_interrupt *intr =
2746                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2747
2748         if (on)
2749                 intr->mask |= E1000_ICR_LSC;
2750         else
2751                 intr->mask &= ~E1000_ICR_LSC;
2752
2753         return 0;
2754 }
2755
2756 /* It clears the interrupt causes and enables the interrupt.
2757  * It will be called once only during nic initialized.
2758  *
2759  * @param dev
2760  *  Pointer to struct rte_eth_dev.
2761  *
2762  * @return
2763  *  - On success, zero.
2764  *  - On failure, a negative value.
2765  */
2766 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2767 {
2768         uint32_t mask, regval;
2769         struct e1000_hw *hw =
2770                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771         struct rte_eth_dev_info dev_info;
2772
2773         memset(&dev_info, 0, sizeof(dev_info));
2774         eth_igb_infos_get(dev, &dev_info);
2775
2776         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2777         regval = E1000_READ_REG(hw, E1000_EIMS);
2778         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2779
2780         return 0;
2781 }
2782
2783 /*
2784  * It reads ICR and gets interrupt causes, check it and set a bit flag
2785  * to update link status.
2786  *
2787  * @param dev
2788  *  Pointer to struct rte_eth_dev.
2789  *
2790  * @return
2791  *  - On success, zero.
2792  *  - On failure, a negative value.
2793  */
2794 static int
2795 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2796 {
2797         uint32_t icr;
2798         struct e1000_hw *hw =
2799                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800         struct e1000_interrupt *intr =
2801                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2802
2803         igb_intr_disable(hw);
2804
2805         /* read-on-clear nic registers here */
2806         icr = E1000_READ_REG(hw, E1000_ICR);
2807
2808         intr->flags = 0;
2809         if (icr & E1000_ICR_LSC) {
2810                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2811         }
2812
2813         if (icr & E1000_ICR_VMMB)
2814                 intr->flags |= E1000_FLAG_MAILBOX;
2815
2816         return 0;
2817 }
2818
2819 /*
2820  * It executes link_update after knowing an interrupt is prsent.
2821  *
2822  * @param dev
2823  *  Pointer to struct rte_eth_dev.
2824  *
2825  * @return
2826  *  - On success, zero.
2827  *  - On failure, a negative value.
2828  */
2829 static int
2830 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2831                          struct rte_intr_handle *intr_handle)
2832 {
2833         struct e1000_hw *hw =
2834                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835         struct e1000_interrupt *intr =
2836                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2838         uint32_t tctl, rctl;
2839         struct rte_eth_link link;
2840         int ret;
2841
2842         if (intr->flags & E1000_FLAG_MAILBOX) {
2843                 igb_pf_mbx_process(dev);
2844                 intr->flags &= ~E1000_FLAG_MAILBOX;
2845         }
2846
2847         igb_intr_enable(dev);
2848         rte_intr_enable(intr_handle);
2849
2850         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2851                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2852
2853                 /* set get_link_status to check register later */
2854                 hw->mac.get_link_status = 1;
2855                 ret = eth_igb_link_update(dev, 0);
2856
2857                 /* check if link has changed */
2858                 if (ret < 0)
2859                         return 0;
2860
2861                 memset(&link, 0, sizeof(link));
2862                 rte_igb_dev_atomic_read_link_status(dev, &link);
2863                 if (link.link_status) {
2864                         PMD_INIT_LOG(INFO,
2865                                      " Port %d: Link Up - speed %u Mbps - %s",
2866                                      dev->data->port_id,
2867                                      (unsigned)link.link_speed,
2868                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2869                                      "full-duplex" : "half-duplex");
2870                 } else {
2871                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2872                                      dev->data->port_id);
2873                 }
2874
2875                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2876                              pci_dev->addr.domain,
2877                              pci_dev->addr.bus,
2878                              pci_dev->addr.devid,
2879                              pci_dev->addr.function);
2880                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2881                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2882                 if (link.link_status) {
2883                         /* enable Tx/Rx */
2884                         tctl |= E1000_TCTL_EN;
2885                         rctl |= E1000_RCTL_EN;
2886                 } else {
2887                         /* disable Tx/Rx */
2888                         tctl &= ~E1000_TCTL_EN;
2889                         rctl &= ~E1000_RCTL_EN;
2890                 }
2891                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2892                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2893                 E1000_WRITE_FLUSH(hw);
2894                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2895                                               NULL);
2896         }
2897
2898         return 0;
2899 }
2900
2901 /**
2902  * Interrupt handler which shall be registered at first.
2903  *
2904  * @param handle
2905  *  Pointer to interrupt handle.
2906  * @param param
2907  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2908  *
2909  * @return
2910  *  void
2911  */
2912 static void
2913 eth_igb_interrupt_handler(void *param)
2914 {
2915         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2916
2917         eth_igb_interrupt_get_status(dev);
2918         eth_igb_interrupt_action(dev, dev->intr_handle);
2919 }
2920
2921 static int
2922 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2923 {
2924         uint32_t eicr;
2925         struct e1000_hw *hw =
2926                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927         struct e1000_interrupt *intr =
2928                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2929
2930         igbvf_intr_disable(hw);
2931
2932         /* read-on-clear nic registers here */
2933         eicr = E1000_READ_REG(hw, E1000_EICR);
2934         intr->flags = 0;
2935
2936         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2937                 intr->flags |= E1000_FLAG_MAILBOX;
2938
2939         return 0;
2940 }
2941
2942 void igbvf_mbx_process(struct rte_eth_dev *dev)
2943 {
2944         struct e1000_hw *hw =
2945                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946         struct e1000_mbx_info *mbx = &hw->mbx;
2947         u32 in_msg = 0;
2948
2949         if (mbx->ops.read(hw, &in_msg, 1, 0))
2950                 return;
2951
2952         /* PF reset VF event */
2953         if (in_msg == E1000_PF_CONTROL_MSG)
2954                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
2955                                               NULL);
2956 }
2957
2958 static int
2959 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2960 {
2961         struct e1000_interrupt *intr =
2962                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2963
2964         if (intr->flags & E1000_FLAG_MAILBOX) {
2965                 igbvf_mbx_process(dev);
2966                 intr->flags &= ~E1000_FLAG_MAILBOX;
2967         }
2968
2969         igbvf_intr_enable(dev);
2970         rte_intr_enable(intr_handle);
2971
2972         return 0;
2973 }
2974
2975 static void
2976 eth_igbvf_interrupt_handler(void *param)
2977 {
2978         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2979
2980         eth_igbvf_interrupt_get_status(dev);
2981         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2982 }
2983
2984 static int
2985 eth_igb_led_on(struct rte_eth_dev *dev)
2986 {
2987         struct e1000_hw *hw;
2988
2989         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2990         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2991 }
2992
2993 static int
2994 eth_igb_led_off(struct rte_eth_dev *dev)
2995 {
2996         struct e1000_hw *hw;
2997
2998         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
3000 }
3001
3002 static int
3003 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3004 {
3005         struct e1000_hw *hw;
3006         uint32_t ctrl;
3007         int tx_pause;
3008         int rx_pause;
3009
3010         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3011         fc_conf->pause_time = hw->fc.pause_time;
3012         fc_conf->high_water = hw->fc.high_water;
3013         fc_conf->low_water = hw->fc.low_water;
3014         fc_conf->send_xon = hw->fc.send_xon;
3015         fc_conf->autoneg = hw->mac.autoneg;
3016
3017         /*
3018          * Return rx_pause and tx_pause status according to actual setting of
3019          * the TFCE and RFCE bits in the CTRL register.
3020          */
3021         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3022         if (ctrl & E1000_CTRL_TFCE)
3023                 tx_pause = 1;
3024         else
3025                 tx_pause = 0;
3026
3027         if (ctrl & E1000_CTRL_RFCE)
3028                 rx_pause = 1;
3029         else
3030                 rx_pause = 0;
3031
3032         if (rx_pause && tx_pause)
3033                 fc_conf->mode = RTE_FC_FULL;
3034         else if (rx_pause)
3035                 fc_conf->mode = RTE_FC_RX_PAUSE;
3036         else if (tx_pause)
3037                 fc_conf->mode = RTE_FC_TX_PAUSE;
3038         else
3039                 fc_conf->mode = RTE_FC_NONE;
3040
3041         return 0;
3042 }
3043
3044 static int
3045 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3046 {
3047         struct e1000_hw *hw;
3048         int err;
3049         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3050                 e1000_fc_none,
3051                 e1000_fc_rx_pause,
3052                 e1000_fc_tx_pause,
3053                 e1000_fc_full
3054         };
3055         uint32_t rx_buf_size;
3056         uint32_t max_high_water;
3057         uint32_t rctl;
3058
3059         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         if (fc_conf->autoneg != hw->mac.autoneg)
3061                 return -ENOTSUP;
3062         rx_buf_size = igb_get_rx_buffer_size(hw);
3063         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3064
3065         /* At least reserve one Ethernet frame for watermark */
3066         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3067         if ((fc_conf->high_water > max_high_water) ||
3068             (fc_conf->high_water < fc_conf->low_water)) {
3069                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3070                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3071                 return -EINVAL;
3072         }
3073
3074         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3075         hw->fc.pause_time     = fc_conf->pause_time;
3076         hw->fc.high_water     = fc_conf->high_water;
3077         hw->fc.low_water      = fc_conf->low_water;
3078         hw->fc.send_xon       = fc_conf->send_xon;
3079
3080         err = e1000_setup_link_generic(hw);
3081         if (err == E1000_SUCCESS) {
3082
3083                 /* check if we want to forward MAC frames - driver doesn't have native
3084                  * capability to do that, so we'll write the registers ourselves */
3085
3086                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3087
3088                 /* set or clear MFLCN.PMCF bit depending on configuration */
3089                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3090                         rctl |= E1000_RCTL_PMCF;
3091                 else
3092                         rctl &= ~E1000_RCTL_PMCF;
3093
3094                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3095                 E1000_WRITE_FLUSH(hw);
3096
3097                 return 0;
3098         }
3099
3100         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3101         return -EIO;
3102 }
3103
3104 #define E1000_RAH_POOLSEL_SHIFT      (18)
3105 static int
3106 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3107                 uint32_t index, uint32_t pool)
3108 {
3109         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3110         uint32_t rah;
3111
3112         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3113         rah = E1000_READ_REG(hw, E1000_RAH(index));
3114         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3115         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3116         return 0;
3117 }
3118
3119 static void
3120 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3121 {
3122         uint8_t addr[ETHER_ADDR_LEN];
3123         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124
3125         memset(addr, 0, sizeof(addr));
3126
3127         e1000_rar_set(hw, addr, index);
3128 }
3129
3130 static void
3131 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3132                                 struct ether_addr *addr)
3133 {
3134         eth_igb_rar_clear(dev, 0);
3135
3136         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3137 }
3138 /*
3139  * Virtual Function operations
3140  */
3141 static void
3142 igbvf_intr_disable(struct e1000_hw *hw)
3143 {
3144         PMD_INIT_FUNC_TRACE();
3145
3146         /* Clear interrupt mask to stop from interrupts being generated */
3147         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3148
3149         E1000_WRITE_FLUSH(hw);
3150 }
3151
3152 static void
3153 igbvf_stop_adapter(struct rte_eth_dev *dev)
3154 {
3155         u32 reg_val;
3156         u16 i;
3157         struct rte_eth_dev_info dev_info;
3158         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159
3160         memset(&dev_info, 0, sizeof(dev_info));
3161         eth_igbvf_infos_get(dev, &dev_info);
3162
3163         /* Clear interrupt mask to stop from interrupts being generated */
3164         igbvf_intr_disable(hw);
3165
3166         /* Clear any pending interrupts, flush previous writes */
3167         E1000_READ_REG(hw, E1000_EICR);
3168
3169         /* Disable the transmit unit.  Each queue must be disabled. */
3170         for (i = 0; i < dev_info.max_tx_queues; i++)
3171                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3172
3173         /* Disable the receive unit by stopping each queue */
3174         for (i = 0; i < dev_info.max_rx_queues; i++) {
3175                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3176                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3177                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3178                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3179                         ;
3180         }
3181
3182         /* flush all queues disables */
3183         E1000_WRITE_FLUSH(hw);
3184         msec_delay(2);
3185 }
3186
3187 static int eth_igbvf_link_update(struct e1000_hw *hw)
3188 {
3189         struct e1000_mbx_info *mbx = &hw->mbx;
3190         struct e1000_mac_info *mac = &hw->mac;
3191         int ret_val = E1000_SUCCESS;
3192
3193         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3194
3195         /*
3196          * We only want to run this if there has been a rst asserted.
3197          * in this case that could mean a link change, device reset,
3198          * or a virtual function reset
3199          */
3200
3201         /* If we were hit with a reset or timeout drop the link */
3202         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3203                 mac->get_link_status = TRUE;
3204
3205         if (!mac->get_link_status)
3206                 goto out;
3207
3208         /* if link status is down no point in checking to see if pf is up */
3209         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3210                 goto out;
3211
3212         /* if we passed all the tests above then the link is up and we no
3213          * longer need to check for link */
3214         mac->get_link_status = FALSE;
3215
3216 out:
3217         return ret_val;
3218 }
3219
3220
3221 static int
3222 igbvf_dev_configure(struct rte_eth_dev *dev)
3223 {
3224         struct rte_eth_conf* conf = &dev->data->dev_conf;
3225
3226         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3227                      dev->data->port_id);
3228
3229         /*
3230          * VF has no ability to enable/disable HW CRC
3231          * Keep the persistent behavior the same as Host PF
3232          */
3233 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3234         if (!conf->rxmode.hw_strip_crc) {
3235                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3236                 conf->rxmode.hw_strip_crc = 1;
3237         }
3238 #else
3239         if (conf->rxmode.hw_strip_crc) {
3240                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3241                 conf->rxmode.hw_strip_crc = 0;
3242         }
3243 #endif
3244
3245         return 0;
3246 }
3247
3248 static int
3249 igbvf_dev_start(struct rte_eth_dev *dev)
3250 {
3251         struct e1000_hw *hw =
3252                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253         struct e1000_adapter *adapter =
3254                 E1000_DEV_PRIVATE(dev->data->dev_private);
3255         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3256         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3257         int ret;
3258         uint32_t intr_vector = 0;
3259
3260         PMD_INIT_FUNC_TRACE();
3261
3262         hw->mac.ops.reset_hw(hw);
3263         adapter->stopped = 0;
3264
3265         /* Set all vfta */
3266         igbvf_set_vfta_all(dev,1);
3267
3268         eth_igbvf_tx_init(dev);
3269
3270         /* This can fail when allocating mbufs for descriptor rings */
3271         ret = eth_igbvf_rx_init(dev);
3272         if (ret) {
3273                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3274                 igb_dev_clear_queues(dev);
3275                 return ret;
3276         }
3277
3278         /* check and configure queue intr-vector mapping */
3279         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3280                 intr_vector = dev->data->nb_rx_queues;
3281                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3282                 if (ret)
3283                         return ret;
3284         }
3285
3286         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3287                 intr_handle->intr_vec =
3288                         rte_zmalloc("intr_vec",
3289                                     dev->data->nb_rx_queues * sizeof(int), 0);
3290                 if (!intr_handle->intr_vec) {
3291                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3292                                      " intr_vec", dev->data->nb_rx_queues);
3293                         return -ENOMEM;
3294                 }
3295         }
3296
3297         eth_igbvf_configure_msix_intr(dev);
3298
3299         /* enable uio/vfio intr/eventfd mapping */
3300         rte_intr_enable(intr_handle);
3301
3302         /* resume enabled intr since hw reset */
3303         igbvf_intr_enable(dev);
3304
3305         return 0;
3306 }
3307
3308 static void
3309 igbvf_dev_stop(struct rte_eth_dev *dev)
3310 {
3311         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3312         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3313
3314         PMD_INIT_FUNC_TRACE();
3315
3316         igbvf_stop_adapter(dev);
3317
3318         /*
3319           * Clear what we set, but we still keep shadow_vfta to
3320           * restore after device starts
3321           */
3322         igbvf_set_vfta_all(dev,0);
3323
3324         igb_dev_clear_queues(dev);
3325
3326         /* disable intr eventfd mapping */
3327         rte_intr_disable(intr_handle);
3328
3329         /* Clean datapath event and queue/vec mapping */
3330         rte_intr_efd_disable(intr_handle);
3331         if (intr_handle->intr_vec) {
3332                 rte_free(intr_handle->intr_vec);
3333                 intr_handle->intr_vec = NULL;
3334         }
3335 }
3336
3337 static void
3338 igbvf_dev_close(struct rte_eth_dev *dev)
3339 {
3340         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341         struct e1000_adapter *adapter =
3342                 E1000_DEV_PRIVATE(dev->data->dev_private);
3343         struct ether_addr addr;
3344
3345         PMD_INIT_FUNC_TRACE();
3346
3347         e1000_reset_hw(hw);
3348
3349         igbvf_dev_stop(dev);
3350         adapter->stopped = 1;
3351         igb_dev_free_queues(dev);
3352
3353         /**
3354          * reprogram the RAR with a zero mac address,
3355          * to ensure that the VF traffic goes to the PF
3356          * after stop, close and detach of the VF.
3357          **/
3358
3359         memset(&addr, 0, sizeof(addr));
3360         igbvf_default_mac_addr_set(dev, &addr);
3361 }
3362
3363 static void
3364 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3365 {
3366         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367
3368         /* Set both unicast and multicast promisc */
3369         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3370 }
3371
3372 static void
3373 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3374 {
3375         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3376
3377         /* If in allmulticast mode leave multicast promisc */
3378         if (dev->data->all_multicast == 1)
3379                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3380         else
3381                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3382 }
3383
3384 static void
3385 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3386 {
3387         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388
3389         /* In promiscuous mode multicast promisc already set */
3390         if (dev->data->promiscuous == 0)
3391                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3392 }
3393
3394 static void
3395 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3396 {
3397         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398
3399         /* In promiscuous mode leave multicast promisc enabled */
3400         if (dev->data->promiscuous == 0)
3401                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3402 }
3403
3404 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3405 {
3406         struct e1000_mbx_info *mbx = &hw->mbx;
3407         uint32_t msgbuf[2];
3408         s32 err;
3409
3410         /* After set vlan, vlan strip will also be enabled in igb driver*/
3411         msgbuf[0] = E1000_VF_SET_VLAN;
3412         msgbuf[1] = vid;
3413         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3414         if (on)
3415                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3416
3417         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3418         if (err)
3419                 goto mbx_err;
3420
3421         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3422         if (err)
3423                 goto mbx_err;
3424
3425         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3426         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3427                 err = -EINVAL;
3428
3429 mbx_err:
3430         return err;
3431 }
3432
3433 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3434 {
3435         struct e1000_hw *hw =
3436                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437         struct e1000_vfta * shadow_vfta =
3438                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3439         int i = 0, j = 0, vfta = 0, mask = 1;
3440
3441         for (i = 0; i < IGB_VFTA_SIZE; i++){
3442                 vfta = shadow_vfta->vfta[i];
3443                 if(vfta){
3444                         mask = 1;
3445                         for (j = 0; j < 32; j++){
3446                                 if(vfta & mask)
3447                                         igbvf_set_vfta(hw,
3448                                                 (uint16_t)((i<<5)+j), on);
3449                                 mask<<=1;
3450                         }
3451                 }
3452         }
3453
3454 }
3455
3456 static int
3457 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3458 {
3459         struct e1000_hw *hw =
3460                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461         struct e1000_vfta * shadow_vfta =
3462                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3463         uint32_t vid_idx = 0;
3464         uint32_t vid_bit = 0;
3465         int ret = 0;
3466
3467         PMD_INIT_FUNC_TRACE();
3468
3469         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3470         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3471         if(ret){
3472                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3473                 return ret;
3474         }
3475         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3476         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3477
3478         /*Save what we set and retore it after device reset*/
3479         if (on)
3480                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3481         else
3482                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3483
3484         return 0;
3485 }
3486
3487 static void
3488 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3489 {
3490         struct e1000_hw *hw =
3491                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3492
3493         /* index is not used by rar_set() */
3494         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3495 }
3496
3497
3498 static int
3499 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3500                         struct rte_eth_rss_reta_entry64 *reta_conf,
3501                         uint16_t reta_size)
3502 {
3503         uint8_t i, j, mask;
3504         uint32_t reta, r;
3505         uint16_t idx, shift;
3506         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507
3508         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3509                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3510                         "(%d) doesn't match the number hardware can supported "
3511                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3512                 return -EINVAL;
3513         }
3514
3515         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3516                 idx = i / RTE_RETA_GROUP_SIZE;
3517                 shift = i % RTE_RETA_GROUP_SIZE;
3518                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3519                                                 IGB_4_BIT_MASK);
3520                 if (!mask)
3521                         continue;
3522                 if (mask == IGB_4_BIT_MASK)
3523                         r = 0;
3524                 else
3525                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3526                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3527                         if (mask & (0x1 << j))
3528                                 reta |= reta_conf[idx].reta[shift + j] <<
3529                                                         (CHAR_BIT * j);
3530                         else
3531                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3532                 }
3533                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3534         }
3535
3536         return 0;
3537 }
3538
3539 static int
3540 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3541                        struct rte_eth_rss_reta_entry64 *reta_conf,
3542                        uint16_t reta_size)
3543 {
3544         uint8_t i, j, mask;
3545         uint32_t reta;
3546         uint16_t idx, shift;
3547         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548
3549         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3550                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3551                         "(%d) doesn't match the number hardware can supported "
3552                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3553                 return -EINVAL;
3554         }
3555
3556         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3557                 idx = i / RTE_RETA_GROUP_SIZE;
3558                 shift = i % RTE_RETA_GROUP_SIZE;
3559                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3560                                                 IGB_4_BIT_MASK);
3561                 if (!mask)
3562                         continue;
3563                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3564                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3565                         if (mask & (0x1 << j))
3566                                 reta_conf[idx].reta[shift + j] =
3567                                         ((reta >> (CHAR_BIT * j)) &
3568                                                 IGB_8_BIT_MASK);
3569                 }
3570         }
3571
3572         return 0;
3573 }
3574
3575 int
3576 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3577                         struct rte_eth_syn_filter *filter,
3578                         bool add)
3579 {
3580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581         struct e1000_filter_info *filter_info =
3582                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3583         uint32_t synqf, rfctl;
3584
3585         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3586                 return -EINVAL;
3587
3588         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3589
3590         if (add) {
3591                 if (synqf & E1000_SYN_FILTER_ENABLE)
3592                         return -EINVAL;
3593
3594                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3595                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3596
3597                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3598                 if (filter->hig_pri)
3599                         rfctl |= E1000_RFCTL_SYNQFP;
3600                 else
3601                         rfctl &= ~E1000_RFCTL_SYNQFP;
3602
3603                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3604         } else {
3605                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3606                         return -ENOENT;
3607                 synqf = 0;
3608         }
3609
3610         filter_info->syn_info = synqf;
3611         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3612         E1000_WRITE_FLUSH(hw);
3613         return 0;
3614 }
3615
3616 static int
3617 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3618                         struct rte_eth_syn_filter *filter)
3619 {
3620         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621         uint32_t synqf, rfctl;
3622
3623         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3624         if (synqf & E1000_SYN_FILTER_ENABLE) {
3625                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3626                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3627                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3628                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3629                 return 0;
3630         }
3631
3632         return -ENOENT;
3633 }
3634
3635 static int
3636 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3637                         enum rte_filter_op filter_op,
3638                         void *arg)
3639 {
3640         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         int ret;
3642
3643         MAC_TYPE_FILTER_SUP(hw->mac.type);
3644
3645         if (filter_op == RTE_ETH_FILTER_NOP)
3646                 return 0;
3647
3648         if (arg == NULL) {
3649                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3650                             filter_op);
3651                 return -EINVAL;
3652         }
3653
3654         switch (filter_op) {
3655         case RTE_ETH_FILTER_ADD:
3656                 ret = eth_igb_syn_filter_set(dev,
3657                                 (struct rte_eth_syn_filter *)arg,
3658                                 TRUE);
3659                 break;
3660         case RTE_ETH_FILTER_DELETE:
3661                 ret = eth_igb_syn_filter_set(dev,
3662                                 (struct rte_eth_syn_filter *)arg,
3663                                 FALSE);
3664                 break;
3665         case RTE_ETH_FILTER_GET:
3666                 ret = eth_igb_syn_filter_get(dev,
3667                                 (struct rte_eth_syn_filter *)arg);
3668                 break;
3669         default:
3670                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3671                 ret = -EINVAL;
3672                 break;
3673         }
3674
3675         return ret;
3676 }
3677
3678 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3679 static inline int
3680 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3681                         struct e1000_2tuple_filter_info *filter_info)
3682 {
3683         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3684                 return -EINVAL;
3685         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3686                 return -EINVAL;  /* filter index is out of range. */
3687         if (filter->tcp_flags > TCP_FLAG_ALL)
3688                 return -EINVAL;  /* flags is invalid. */
3689
3690         switch (filter->dst_port_mask) {
3691         case UINT16_MAX:
3692                 filter_info->dst_port_mask = 0;
3693                 filter_info->dst_port = filter->dst_port;
3694                 break;
3695         case 0:
3696                 filter_info->dst_port_mask = 1;
3697                 break;
3698         default:
3699                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3700                 return -EINVAL;
3701         }
3702
3703         switch (filter->proto_mask) {
3704         case UINT8_MAX:
3705                 filter_info->proto_mask = 0;
3706                 filter_info->proto = filter->proto;
3707                 break;
3708         case 0:
3709                 filter_info->proto_mask = 1;
3710                 break;
3711         default:
3712                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3713                 return -EINVAL;
3714         }
3715
3716         filter_info->priority = (uint8_t)filter->priority;
3717         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3718                 filter_info->tcp_flags = filter->tcp_flags;
3719         else
3720                 filter_info->tcp_flags = 0;
3721
3722         return 0;
3723 }
3724
3725 static inline struct e1000_2tuple_filter *
3726 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3727                         struct e1000_2tuple_filter_info *key)
3728 {
3729         struct e1000_2tuple_filter *it;
3730
3731         TAILQ_FOREACH(it, filter_list, entries) {
3732                 if (memcmp(key, &it->filter_info,
3733                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3734                         return it;
3735                 }
3736         }
3737         return NULL;
3738 }
3739
3740 /* inject a igb 2tuple filter to HW */
3741 static inline void
3742 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3743                            struct e1000_2tuple_filter *filter)
3744 {
3745         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3747         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3748         int i;
3749
3750         i = filter->index;
3751         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3752         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3753                 imir |= E1000_IMIR_PORT_BP;
3754         else
3755                 imir &= ~E1000_IMIR_PORT_BP;
3756
3757         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3758
3759         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3760         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3761         ttqf |= (uint32_t)(filter->filter_info.proto &
3762                                                 E1000_TTQF_PROTOCOL_MASK);
3763         if (filter->filter_info.proto_mask == 0)
3764                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3765
3766         /* tcp flags bits setting. */
3767         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3768                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3769                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3770                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3771                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3772                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3773                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3774                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3775                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3776                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3777                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3778                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3779                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3780         } else {
3781                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3782         }
3783         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3784         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3785         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3786 }
3787
3788 /*
3789  * igb_add_2tuple_filter - add a 2tuple filter
3790  *
3791  * @param
3792  * dev: Pointer to struct rte_eth_dev.
3793  * ntuple_filter: ponter to the filter that will be added.
3794  *
3795  * @return
3796  *    - On success, zero.
3797  *    - On failure, a negative value.
3798  */
3799 static int
3800 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3801                         struct rte_eth_ntuple_filter *ntuple_filter)
3802 {
3803         struct e1000_filter_info *filter_info =
3804                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3805         struct e1000_2tuple_filter *filter;
3806         int i, ret;
3807
3808         filter = rte_zmalloc("e1000_2tuple_filter",
3809                         sizeof(struct e1000_2tuple_filter), 0);
3810         if (filter == NULL)
3811                 return -ENOMEM;
3812
3813         ret = ntuple_filter_to_2tuple(ntuple_filter,
3814                                       &filter->filter_info);
3815         if (ret < 0) {
3816                 rte_free(filter);
3817                 return ret;
3818         }
3819         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3820                                          &filter->filter_info) != NULL) {
3821                 PMD_DRV_LOG(ERR, "filter exists.");
3822                 rte_free(filter);
3823                 return -EEXIST;
3824         }
3825         filter->queue = ntuple_filter->queue;
3826
3827         /*
3828          * look for an unused 2tuple filter index,
3829          * and insert the filter to list.
3830          */
3831         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3832                 if (!(filter_info->twotuple_mask & (1 << i))) {
3833                         filter_info->twotuple_mask |= 1 << i;
3834                         filter->index = i;
3835                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3836                                           filter,
3837                                           entries);
3838                         break;
3839                 }
3840         }
3841         if (i >= E1000_MAX_TTQF_FILTERS) {
3842                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3843                 rte_free(filter);
3844                 return -ENOSYS;
3845         }
3846
3847         igb_inject_2uple_filter(dev, filter);
3848         return 0;
3849 }
3850
3851 int
3852 igb_delete_2tuple_filter(struct rte_eth_dev *dev,
3853                         struct e1000_2tuple_filter *filter)
3854 {
3855         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856         struct e1000_filter_info *filter_info =
3857                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3858
3859         filter_info->twotuple_mask &= ~(1 << filter->index);
3860         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3861         rte_free(filter);
3862
3863         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3864         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3865         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3866         return 0;
3867 }
3868
3869 /*
3870  * igb_remove_2tuple_filter - remove a 2tuple filter
3871  *
3872  * @param
3873  * dev: Pointer to struct rte_eth_dev.
3874  * ntuple_filter: ponter to the filter that will be removed.
3875  *
3876  * @return
3877  *    - On success, zero.
3878  *    - On failure, a negative value.
3879  */
3880 static int
3881 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3882                         struct rte_eth_ntuple_filter *ntuple_filter)
3883 {
3884         struct e1000_filter_info *filter_info =
3885                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3886         struct e1000_2tuple_filter_info filter_2tuple;
3887         struct e1000_2tuple_filter *filter;
3888         int ret;
3889
3890         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3891         ret = ntuple_filter_to_2tuple(ntuple_filter,
3892                                       &filter_2tuple);
3893         if (ret < 0)
3894                 return ret;
3895
3896         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3897                                          &filter_2tuple);
3898         if (filter == NULL) {
3899                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3900                 return -ENOENT;
3901         }
3902
3903         igb_delete_2tuple_filter(dev, filter);
3904
3905         return 0;
3906 }
3907
3908 /* inject a igb flex filter to HW */
3909 static inline void
3910 igb_inject_flex_filter(struct rte_eth_dev *dev,
3911                            struct e1000_flex_filter *filter)
3912 {
3913         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3914         uint32_t wufc, queueing;
3915         uint32_t reg_off;
3916         uint8_t i, j = 0;
3917
3918         wufc = E1000_READ_REG(hw, E1000_WUFC);
3919         if (filter->index < E1000_MAX_FHFT)
3920                 reg_off = E1000_FHFT(filter->index);
3921         else
3922                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3923
3924         E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3925                         (E1000_WUFC_FLX0 << filter->index));
3926         queueing = filter->filter_info.len |
3927                 (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3928                 (filter->filter_info.priority <<
3929                         E1000_FHFT_QUEUEING_PRIO_SHIFT);
3930         E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3931                         queueing);
3932
3933         for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3934                 E1000_WRITE_REG(hw, reg_off,
3935                                 filter->filter_info.dwords[j]);
3936                 reg_off += sizeof(uint32_t);
3937                 E1000_WRITE_REG(hw, reg_off,
3938                                 filter->filter_info.dwords[++j]);
3939                 reg_off += sizeof(uint32_t);
3940                 E1000_WRITE_REG(hw, reg_off,
3941                         (uint32_t)filter->filter_info.mask[i]);
3942                 reg_off += sizeof(uint32_t) * 2;
3943                 ++j;
3944         }
3945 }
3946
3947 static inline struct e1000_flex_filter *
3948 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3949                         struct e1000_flex_filter_info *key)
3950 {
3951         struct e1000_flex_filter *it;
3952
3953         TAILQ_FOREACH(it, filter_list, entries) {
3954                 if (memcmp(key, &it->filter_info,
3955                         sizeof(struct e1000_flex_filter_info)) == 0)
3956                         return it;
3957         }
3958
3959         return NULL;
3960 }
3961
3962 /* remove a flex byte filter
3963  * @param
3964  * dev: Pointer to struct rte_eth_dev.
3965  * filter: the pointer of the filter will be removed.
3966  */
3967 void
3968 igb_remove_flex_filter(struct rte_eth_dev *dev,
3969                         struct e1000_flex_filter *filter)
3970 {
3971         struct e1000_filter_info *filter_info =
3972                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3973         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3974         uint32_t wufc, i;
3975         uint32_t reg_off;
3976
3977         wufc = E1000_READ_REG(hw, E1000_WUFC);
3978         if (filter->index < E1000_MAX_FHFT)
3979                 reg_off = E1000_FHFT(filter->index);
3980         else
3981                 reg_off = E1000_FHFT_EXT(filter->index - E1000_MAX_FHFT);
3982
3983         for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
3984                 E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
3985
3986         E1000_WRITE_REG(hw, E1000_WUFC, wufc &
3987                 (~(E1000_WUFC_FLX0 << filter->index)));
3988
3989         filter_info->flex_mask &= ~(1 << filter->index);
3990         TAILQ_REMOVE(&filter_info->flex_list, filter, entries);
3991         rte_free(filter);
3992 }
3993
3994 int
3995 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3996                         struct rte_eth_flex_filter *filter,
3997                         bool add)
3998 {
3999         struct e1000_filter_info *filter_info =
4000                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4001         struct e1000_flex_filter *flex_filter, *it;
4002         uint32_t mask;
4003         uint8_t shift, i;
4004
4005         flex_filter = rte_zmalloc("e1000_flex_filter",
4006                         sizeof(struct e1000_flex_filter), 0);
4007         if (flex_filter == NULL)
4008                 return -ENOMEM;
4009
4010         flex_filter->filter_info.len = filter->len;
4011         flex_filter->filter_info.priority = filter->priority;
4012         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
4013         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
4014                 mask = 0;
4015                 /* reverse bits in flex filter's mask*/
4016                 for (shift = 0; shift < CHAR_BIT; shift++) {
4017                         if (filter->mask[i] & (0x01 << shift))
4018                                 mask |= (0x80 >> shift);
4019                 }
4020                 flex_filter->filter_info.mask[i] = mask;
4021         }
4022
4023         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4024                                 &flex_filter->filter_info);
4025         if (it == NULL && !add) {
4026                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4027                 rte_free(flex_filter);
4028                 return -ENOENT;
4029         }
4030         if (it != NULL && add) {
4031                 PMD_DRV_LOG(ERR, "filter exists.");
4032                 rte_free(flex_filter);
4033                 return -EEXIST;
4034         }
4035
4036         if (add) {
4037                 flex_filter->queue = filter->queue;
4038                 /*
4039                  * look for an unused flex filter index
4040                  * and insert the filter into the list.
4041                  */
4042                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
4043                         if (!(filter_info->flex_mask & (1 << i))) {
4044                                 filter_info->flex_mask |= 1 << i;
4045                                 flex_filter->index = i;
4046                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
4047                                         flex_filter,
4048                                         entries);
4049                                 break;
4050                         }
4051                 }
4052                 if (i >= E1000_MAX_FLEX_FILTERS) {
4053                         PMD_DRV_LOG(ERR, "flex filters are full.");
4054                         rte_free(flex_filter);
4055                         return -ENOSYS;
4056                 }
4057
4058                 igb_inject_flex_filter(dev, flex_filter);
4059
4060         } else {
4061                 igb_remove_flex_filter(dev, it);
4062                 rte_free(flex_filter);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static int
4069 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4070                         struct rte_eth_flex_filter *filter)
4071 {
4072         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073         struct e1000_filter_info *filter_info =
4074                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4075         struct e1000_flex_filter flex_filter, *it;
4076         uint32_t wufc, queueing, wufc_en = 0;
4077
4078         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4079         flex_filter.filter_info.len = filter->len;
4080         flex_filter.filter_info.priority = filter->priority;
4081         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4082         memcpy(flex_filter.filter_info.mask, filter->mask,
4083                         RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT);
4084
4085         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4086                                 &flex_filter.filter_info);
4087         if (it == NULL) {
4088                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4089                 return -ENOENT;
4090         }
4091
4092         wufc = E1000_READ_REG(hw, E1000_WUFC);
4093         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4094
4095         if ((wufc & wufc_en) == wufc_en) {
4096                 uint32_t reg_off = 0;
4097                 if (it->index < E1000_MAX_FHFT)
4098                         reg_off = E1000_FHFT(it->index);
4099                 else
4100                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4101
4102                 queueing = E1000_READ_REG(hw,
4103                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4104                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4105                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4106                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4107                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4108                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4109                 return 0;
4110         }
4111         return -ENOENT;
4112 }
4113
4114 static int
4115 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4116                         enum rte_filter_op filter_op,
4117                         void *arg)
4118 {
4119         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4120         struct rte_eth_flex_filter *filter;
4121         int ret = 0;
4122
4123         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4124
4125         if (filter_op == RTE_ETH_FILTER_NOP)
4126                 return ret;
4127
4128         if (arg == NULL) {
4129                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4130                             filter_op);
4131                 return -EINVAL;
4132         }
4133
4134         filter = (struct rte_eth_flex_filter *)arg;
4135         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4136             || filter->len % sizeof(uint64_t) != 0) {
4137                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4138                 return -EINVAL;
4139         }
4140         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4141                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4142                 return -EINVAL;
4143         }
4144
4145         switch (filter_op) {
4146         case RTE_ETH_FILTER_ADD:
4147                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4148                 break;
4149         case RTE_ETH_FILTER_DELETE:
4150                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4151                 break;
4152         case RTE_ETH_FILTER_GET:
4153                 ret = eth_igb_get_flex_filter(dev, filter);
4154                 break;
4155         default:
4156                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4157                 ret = -EINVAL;
4158                 break;
4159         }
4160
4161         return ret;
4162 }
4163
4164 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4165 static inline int
4166 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4167                         struct e1000_5tuple_filter_info *filter_info)
4168 {
4169         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4170                 return -EINVAL;
4171         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4172                 return -EINVAL;  /* filter index is out of range. */
4173         if (filter->tcp_flags > TCP_FLAG_ALL)
4174                 return -EINVAL;  /* flags is invalid. */
4175
4176         switch (filter->dst_ip_mask) {
4177         case UINT32_MAX:
4178                 filter_info->dst_ip_mask = 0;
4179                 filter_info->dst_ip = filter->dst_ip;
4180                 break;
4181         case 0:
4182                 filter_info->dst_ip_mask = 1;
4183                 break;
4184         default:
4185                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4186                 return -EINVAL;
4187         }
4188
4189         switch (filter->src_ip_mask) {
4190         case UINT32_MAX:
4191                 filter_info->src_ip_mask = 0;
4192                 filter_info->src_ip = filter->src_ip;
4193                 break;
4194         case 0:
4195                 filter_info->src_ip_mask = 1;
4196                 break;
4197         default:
4198                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4199                 return -EINVAL;
4200         }
4201
4202         switch (filter->dst_port_mask) {
4203         case UINT16_MAX:
4204                 filter_info->dst_port_mask = 0;
4205                 filter_info->dst_port = filter->dst_port;
4206                 break;
4207         case 0:
4208                 filter_info->dst_port_mask = 1;
4209                 break;
4210         default:
4211                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4212                 return -EINVAL;
4213         }
4214
4215         switch (filter->src_port_mask) {
4216         case UINT16_MAX:
4217                 filter_info->src_port_mask = 0;
4218                 filter_info->src_port = filter->src_port;
4219                 break;
4220         case 0:
4221                 filter_info->src_port_mask = 1;
4222                 break;
4223         default:
4224                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4225                 return -EINVAL;
4226         }
4227
4228         switch (filter->proto_mask) {
4229         case UINT8_MAX:
4230                 filter_info->proto_mask = 0;
4231                 filter_info->proto = filter->proto;
4232                 break;
4233         case 0:
4234                 filter_info->proto_mask = 1;
4235                 break;
4236         default:
4237                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4238                 return -EINVAL;
4239         }
4240
4241         filter_info->priority = (uint8_t)filter->priority;
4242         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4243                 filter_info->tcp_flags = filter->tcp_flags;
4244         else
4245                 filter_info->tcp_flags = 0;
4246
4247         return 0;
4248 }
4249
4250 static inline struct e1000_5tuple_filter *
4251 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4252                         struct e1000_5tuple_filter_info *key)
4253 {
4254         struct e1000_5tuple_filter *it;
4255
4256         TAILQ_FOREACH(it, filter_list, entries) {
4257                 if (memcmp(key, &it->filter_info,
4258                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4259                         return it;
4260                 }
4261         }
4262         return NULL;
4263 }
4264
4265 /* inject a igb 5-tuple filter to HW */
4266 static inline void
4267 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4268                            struct e1000_5tuple_filter *filter)
4269 {
4270         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4272         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4273         uint8_t i;
4274
4275         i = filter->index;
4276         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4277         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4278                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4279         if (filter->filter_info.dst_ip_mask == 0)
4280                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4281         if (filter->filter_info.src_port_mask == 0)
4282                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4283         if (filter->filter_info.proto_mask == 0)
4284                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4285         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4286                 E1000_FTQF_QUEUE_MASK;
4287         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4288         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4289         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4290         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4291
4292         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4293         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4294
4295         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4296         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4297                 imir |= E1000_IMIR_PORT_BP;
4298         else
4299                 imir &= ~E1000_IMIR_PORT_BP;
4300         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4301
4302         /* tcp flags bits setting. */
4303         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4304                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4305                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4306                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4307                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4308                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4309                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4310                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4311                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4312                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4313                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4314                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4315                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4316         } else {
4317                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4318         }
4319         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4320         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4321 }
4322
4323 /*
4324  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4325  *
4326  * @param
4327  * dev: Pointer to struct rte_eth_dev.
4328  * ntuple_filter: ponter to the filter that will be added.
4329  *
4330  * @return
4331  *    - On success, zero.
4332  *    - On failure, a negative value.
4333  */
4334 static int
4335 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4336                         struct rte_eth_ntuple_filter *ntuple_filter)
4337 {
4338         struct e1000_filter_info *filter_info =
4339                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4340         struct e1000_5tuple_filter *filter;
4341         uint8_t i;
4342         int ret;
4343
4344         filter = rte_zmalloc("e1000_5tuple_filter",
4345                         sizeof(struct e1000_5tuple_filter), 0);
4346         if (filter == NULL)
4347                 return -ENOMEM;
4348
4349         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4350                                             &filter->filter_info);
4351         if (ret < 0) {
4352                 rte_free(filter);
4353                 return ret;
4354         }
4355
4356         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4357                                          &filter->filter_info) != NULL) {
4358                 PMD_DRV_LOG(ERR, "filter exists.");
4359                 rte_free(filter);
4360                 return -EEXIST;
4361         }
4362         filter->queue = ntuple_filter->queue;
4363
4364         /*
4365          * look for an unused 5tuple filter index,
4366          * and insert the filter to list.
4367          */
4368         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4369                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4370                         filter_info->fivetuple_mask |= 1 << i;
4371                         filter->index = i;
4372                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4373                                           filter,
4374                                           entries);
4375                         break;
4376                 }
4377         }
4378         if (i >= E1000_MAX_FTQF_FILTERS) {
4379                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4380                 rte_free(filter);
4381                 return -ENOSYS;
4382         }
4383
4384         igb_inject_5tuple_filter_82576(dev, filter);
4385         return 0;
4386 }
4387
4388 int
4389 igb_delete_5tuple_filter_82576(struct rte_eth_dev *dev,
4390                                 struct e1000_5tuple_filter *filter)
4391 {
4392         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393         struct e1000_filter_info *filter_info =
4394                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4395
4396         filter_info->fivetuple_mask &= ~(1 << filter->index);
4397         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4398         rte_free(filter);
4399
4400         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4401                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4402         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4403         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4404         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4405         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4406         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4407         return 0;
4408 }
4409
4410 /*
4411  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4412  *
4413  * @param
4414  * dev: Pointer to struct rte_eth_dev.
4415  * ntuple_filter: ponter to the filter that will be removed.
4416  *
4417  * @return
4418  *    - On success, zero.
4419  *    - On failure, a negative value.
4420  */
4421 static int
4422 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4423                                 struct rte_eth_ntuple_filter *ntuple_filter)
4424 {
4425         struct e1000_filter_info *filter_info =
4426                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4427         struct e1000_5tuple_filter_info filter_5tuple;
4428         struct e1000_5tuple_filter *filter;
4429         int ret;
4430
4431         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4432         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4433                                             &filter_5tuple);
4434         if (ret < 0)
4435                 return ret;
4436
4437         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4438                                          &filter_5tuple);
4439         if (filter == NULL) {
4440                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4441                 return -ENOENT;
4442         }
4443
4444         igb_delete_5tuple_filter_82576(dev, filter);
4445
4446         return 0;
4447 }
4448
4449 static int
4450 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4451 {
4452         uint32_t rctl;
4453         struct e1000_hw *hw;
4454         struct rte_eth_dev_info dev_info;
4455         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4456                                      VLAN_TAG_SIZE);
4457
4458         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459
4460 #ifdef RTE_LIBRTE_82571_SUPPORT
4461         /* XXX: not bigger than max_rx_pktlen */
4462         if (hw->mac.type == e1000_82571)
4463                 return -ENOTSUP;
4464 #endif
4465         eth_igb_infos_get(dev, &dev_info);
4466
4467         /* check that mtu is within the allowed range */
4468         if ((mtu < ETHER_MIN_MTU) ||
4469             (frame_size > dev_info.max_rx_pktlen))
4470                 return -EINVAL;
4471
4472         /* refuse mtu that requires the support of scattered packets when this
4473          * feature has not been enabled before. */
4474         if (!dev->data->scattered_rx &&
4475             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4476                 return -EINVAL;
4477
4478         rctl = E1000_READ_REG(hw, E1000_RCTL);
4479
4480         /* switch to jumbo mode if needed */
4481         if (frame_size > ETHER_MAX_LEN) {
4482                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4483                 rctl |= E1000_RCTL_LPE;
4484         } else {
4485                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4486                 rctl &= ~E1000_RCTL_LPE;
4487         }
4488         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4489
4490         /* update max frame size */
4491         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4492
4493         E1000_WRITE_REG(hw, E1000_RLPML,
4494                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4495
4496         return 0;
4497 }
4498
4499 /*
4500  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4501  *
4502  * @param
4503  * dev: Pointer to struct rte_eth_dev.
4504  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4505  * add: if true, add filter, if false, remove filter
4506  *
4507  * @return
4508  *    - On success, zero.
4509  *    - On failure, a negative value.
4510  */
4511 int
4512 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4513                         struct rte_eth_ntuple_filter *ntuple_filter,
4514                         bool add)
4515 {
4516         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4517         int ret;
4518
4519         switch (ntuple_filter->flags) {
4520         case RTE_5TUPLE_FLAGS:
4521         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4522                 if (hw->mac.type != e1000_82576)
4523                         return -ENOTSUP;
4524                 if (add)
4525                         ret = igb_add_5tuple_filter_82576(dev,
4526                                                           ntuple_filter);
4527                 else
4528                         ret = igb_remove_5tuple_filter_82576(dev,
4529                                                              ntuple_filter);
4530                 break;
4531         case RTE_2TUPLE_FLAGS:
4532         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4533                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4534                         hw->mac.type != e1000_i210 &&
4535                         hw->mac.type != e1000_i211)
4536                         return -ENOTSUP;
4537                 if (add)
4538                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4539                 else
4540                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4541                 break;
4542         default:
4543                 ret = -EINVAL;
4544                 break;
4545         }
4546
4547         return ret;
4548 }
4549
4550 /*
4551  * igb_get_ntuple_filter - get a ntuple filter
4552  *
4553  * @param
4554  * dev: Pointer to struct rte_eth_dev.
4555  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4556  *
4557  * @return
4558  *    - On success, zero.
4559  *    - On failure, a negative value.
4560  */
4561 static int
4562 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4563                         struct rte_eth_ntuple_filter *ntuple_filter)
4564 {
4565         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4566         struct e1000_filter_info *filter_info =
4567                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4568         struct e1000_5tuple_filter_info filter_5tuple;
4569         struct e1000_2tuple_filter_info filter_2tuple;
4570         struct e1000_5tuple_filter *p_5tuple_filter;
4571         struct e1000_2tuple_filter *p_2tuple_filter;
4572         int ret;
4573
4574         switch (ntuple_filter->flags) {
4575         case RTE_5TUPLE_FLAGS:
4576         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4577                 if (hw->mac.type != e1000_82576)
4578                         return -ENOTSUP;
4579                 memset(&filter_5tuple,
4580                         0,
4581                         sizeof(struct e1000_5tuple_filter_info));
4582                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4583                                                     &filter_5tuple);
4584                 if (ret < 0)
4585                         return ret;
4586                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4587                                         &filter_info->fivetuple_list,
4588                                         &filter_5tuple);
4589                 if (p_5tuple_filter == NULL) {
4590                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4591                         return -ENOENT;
4592                 }
4593                 ntuple_filter->queue = p_5tuple_filter->queue;
4594                 break;
4595         case RTE_2TUPLE_FLAGS:
4596         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4597                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4598                         return -ENOTSUP;
4599                 memset(&filter_2tuple,
4600                         0,
4601                         sizeof(struct e1000_2tuple_filter_info));
4602                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4603                 if (ret < 0)
4604                         return ret;
4605                 p_2tuple_filter = igb_2tuple_filter_lookup(
4606                                         &filter_info->twotuple_list,
4607                                         &filter_2tuple);
4608                 if (p_2tuple_filter == NULL) {
4609                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4610                         return -ENOENT;
4611                 }
4612                 ntuple_filter->queue = p_2tuple_filter->queue;
4613                 break;
4614         default:
4615                 ret = -EINVAL;
4616                 break;
4617         }
4618
4619         return 0;
4620 }
4621
4622 /*
4623  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4624  * @dev: pointer to rte_eth_dev structure
4625  * @filter_op:operation will be taken.
4626  * @arg: a pointer to specific structure corresponding to the filter_op
4627  */
4628 static int
4629 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4630                                 enum rte_filter_op filter_op,
4631                                 void *arg)
4632 {
4633         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         int ret;
4635
4636         MAC_TYPE_FILTER_SUP(hw->mac.type);
4637
4638         if (filter_op == RTE_ETH_FILTER_NOP)
4639                 return 0;
4640
4641         if (arg == NULL) {
4642                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4643                             filter_op);
4644                 return -EINVAL;
4645         }
4646
4647         switch (filter_op) {
4648         case RTE_ETH_FILTER_ADD:
4649                 ret = igb_add_del_ntuple_filter(dev,
4650                         (struct rte_eth_ntuple_filter *)arg,
4651                         TRUE);
4652                 break;
4653         case RTE_ETH_FILTER_DELETE:
4654                 ret = igb_add_del_ntuple_filter(dev,
4655                         (struct rte_eth_ntuple_filter *)arg,
4656                         FALSE);
4657                 break;
4658         case RTE_ETH_FILTER_GET:
4659                 ret = igb_get_ntuple_filter(dev,
4660                         (struct rte_eth_ntuple_filter *)arg);
4661                 break;
4662         default:
4663                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4664                 ret = -EINVAL;
4665                 break;
4666         }
4667         return ret;
4668 }
4669
4670 static inline int
4671 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4672                         uint16_t ethertype)
4673 {
4674         int i;
4675
4676         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4677                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4678                     (filter_info->ethertype_mask & (1 << i)))
4679                         return i;
4680         }
4681         return -1;
4682 }
4683
4684 static inline int
4685 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4686                         uint16_t ethertype, uint32_t etqf)
4687 {
4688         int i;
4689
4690         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4691                 if (!(filter_info->ethertype_mask & (1 << i))) {
4692                         filter_info->ethertype_mask |= 1 << i;
4693                         filter_info->ethertype_filters[i].ethertype = ethertype;
4694                         filter_info->ethertype_filters[i].etqf = etqf;
4695                         return i;
4696                 }
4697         }
4698         return -1;
4699 }
4700
4701 int
4702 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4703                         uint8_t idx)
4704 {
4705         if (idx >= E1000_MAX_ETQF_FILTERS)
4706                 return -1;
4707         filter_info->ethertype_mask &= ~(1 << idx);
4708         filter_info->ethertype_filters[idx].ethertype = 0;
4709         filter_info->ethertype_filters[idx].etqf = 0;
4710         return idx;
4711 }
4712
4713
4714 int
4715 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4716                         struct rte_eth_ethertype_filter *filter,
4717                         bool add)
4718 {
4719         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720         struct e1000_filter_info *filter_info =
4721                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4722         uint32_t etqf = 0;
4723         int ret;
4724
4725         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4726                 filter->ether_type == ETHER_TYPE_IPv6) {
4727                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4728                         " ethertype filter.", filter->ether_type);
4729                 return -EINVAL;
4730         }
4731
4732         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4733                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4734                 return -EINVAL;
4735         }
4736         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4737                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4738                 return -EINVAL;
4739         }
4740
4741         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4742         if (ret >= 0 && add) {
4743                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4744                             filter->ether_type);
4745                 return -EEXIST;
4746         }
4747         if (ret < 0 && !add) {
4748                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4749                             filter->ether_type);
4750                 return -ENOENT;
4751         }
4752
4753         if (add) {
4754                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4755                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4756                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4757                 ret = igb_ethertype_filter_insert(filter_info,
4758                                 filter->ether_type, etqf);
4759                 if (ret < 0) {
4760                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4761                         return -ENOSYS;
4762                 }
4763         } else {
4764                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4765                 if (ret < 0)
4766                         return -ENOSYS;
4767         }
4768         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4769         E1000_WRITE_FLUSH(hw);
4770
4771         return 0;
4772 }
4773
4774 static int
4775 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4776                         struct rte_eth_ethertype_filter *filter)
4777 {
4778         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         struct e1000_filter_info *filter_info =
4780                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4781         uint32_t etqf;
4782         int ret;
4783
4784         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4785         if (ret < 0) {
4786                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4787                             filter->ether_type);
4788                 return -ENOENT;
4789         }
4790
4791         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4792         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4793                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4794                 filter->flags = 0;
4795                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4796                                 E1000_ETQF_QUEUE_SHIFT;
4797                 return 0;
4798         }
4799
4800         return -ENOENT;
4801 }
4802
4803 /*
4804  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4805  * @dev: pointer to rte_eth_dev structure
4806  * @filter_op:operation will be taken.
4807  * @arg: a pointer to specific structure corresponding to the filter_op
4808  */
4809 static int
4810 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4811                                 enum rte_filter_op filter_op,
4812                                 void *arg)
4813 {
4814         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815         int ret;
4816
4817         MAC_TYPE_FILTER_SUP(hw->mac.type);
4818
4819         if (filter_op == RTE_ETH_FILTER_NOP)
4820                 return 0;
4821
4822         if (arg == NULL) {
4823                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4824                             filter_op);
4825                 return -EINVAL;
4826         }
4827
4828         switch (filter_op) {
4829         case RTE_ETH_FILTER_ADD:
4830                 ret = igb_add_del_ethertype_filter(dev,
4831                         (struct rte_eth_ethertype_filter *)arg,
4832                         TRUE);
4833                 break;
4834         case RTE_ETH_FILTER_DELETE:
4835                 ret = igb_add_del_ethertype_filter(dev,
4836                         (struct rte_eth_ethertype_filter *)arg,
4837                         FALSE);
4838                 break;
4839         case RTE_ETH_FILTER_GET:
4840                 ret = igb_get_ethertype_filter(dev,
4841                         (struct rte_eth_ethertype_filter *)arg);
4842                 break;
4843         default:
4844                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4845                 ret = -EINVAL;
4846                 break;
4847         }
4848         return ret;
4849 }
4850
4851 static int
4852 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4853                      enum rte_filter_type filter_type,
4854                      enum rte_filter_op filter_op,
4855                      void *arg)
4856 {
4857         int ret = 0;
4858
4859         switch (filter_type) {
4860         case RTE_ETH_FILTER_NTUPLE:
4861                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4862                 break;
4863         case RTE_ETH_FILTER_ETHERTYPE:
4864                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4865                 break;
4866         case RTE_ETH_FILTER_SYN:
4867                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4868                 break;
4869         case RTE_ETH_FILTER_FLEXIBLE:
4870                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4871                 break;
4872         case RTE_ETH_FILTER_GENERIC:
4873                 if (filter_op != RTE_ETH_FILTER_GET)
4874                         return -EINVAL;
4875                 *(const void **)arg = &igb_flow_ops;
4876                 break;
4877         default:
4878                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4879                                                         filter_type);
4880                 break;
4881         }
4882
4883         return ret;
4884 }
4885
4886 static int
4887 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4888                          struct ether_addr *mc_addr_set,
4889                          uint32_t nb_mc_addr)
4890 {
4891         struct e1000_hw *hw;
4892
4893         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4895         return 0;
4896 }
4897
4898 static uint64_t
4899 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4900 {
4901         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4902         uint64_t systime_cycles;
4903
4904         switch (hw->mac.type) {
4905         case e1000_i210:
4906         case e1000_i211:
4907                 /*
4908                  * Need to read System Time Residue Register to be able
4909                  * to read the other two registers.
4910                  */
4911                 E1000_READ_REG(hw, E1000_SYSTIMR);
4912                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4913                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4914                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4915                                 * NSEC_PER_SEC;
4916                 break;
4917         case e1000_82580:
4918         case e1000_i350:
4919         case e1000_i354:
4920                 /*
4921                  * Need to read System Time Residue Register to be able
4922                  * to read the other two registers.
4923                  */
4924                 E1000_READ_REG(hw, E1000_SYSTIMR);
4925                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4926                 /* Only the 8 LSB are valid. */
4927                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4928                                 & 0xff) << 32;
4929                 break;
4930         default:
4931                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4932                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4933                                 << 32;
4934                 break;
4935         }
4936
4937         return systime_cycles;
4938 }
4939
4940 static uint64_t
4941 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4942 {
4943         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944         uint64_t rx_tstamp_cycles;
4945
4946         switch (hw->mac.type) {
4947         case e1000_i210:
4948         case e1000_i211:
4949                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4950                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4951                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4952                                 * NSEC_PER_SEC;
4953                 break;
4954         case e1000_82580:
4955         case e1000_i350:
4956         case e1000_i354:
4957                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4958                 /* Only the 8 LSB are valid. */
4959                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4960                                 & 0xff) << 32;
4961                 break;
4962         default:
4963                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4964                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4965                                 << 32;
4966                 break;
4967         }
4968
4969         return rx_tstamp_cycles;
4970 }
4971
4972 static uint64_t
4973 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4974 {
4975         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         uint64_t tx_tstamp_cycles;
4977
4978         switch (hw->mac.type) {
4979         case e1000_i210:
4980         case e1000_i211:
4981                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4982                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4983                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4984                                 * NSEC_PER_SEC;
4985                 break;
4986         case e1000_82580:
4987         case e1000_i350:
4988         case e1000_i354:
4989                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4990                 /* Only the 8 LSB are valid. */
4991                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4992                                 & 0xff) << 32;
4993                 break;
4994         default:
4995                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4996                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4997                                 << 32;
4998                 break;
4999         }
5000
5001         return tx_tstamp_cycles;
5002 }
5003
5004 static void
5005 igb_start_timecounters(struct rte_eth_dev *dev)
5006 {
5007         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         struct e1000_adapter *adapter =
5009                 (struct e1000_adapter *)dev->data->dev_private;
5010         uint32_t incval = 1;
5011         uint32_t shift = 0;
5012         uint64_t mask = E1000_CYCLECOUNTER_MASK;
5013
5014         switch (hw->mac.type) {
5015         case e1000_82580:
5016         case e1000_i350:
5017         case e1000_i354:
5018                 /* 32 LSB bits + 8 MSB bits = 40 bits */
5019                 mask = (1ULL << 40) - 1;
5020                 /* fall-through */
5021         case e1000_i210:
5022         case e1000_i211:
5023                 /*
5024                  * Start incrementing the register
5025                  * used to timestamp PTP packets.
5026                  */
5027                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
5028                 break;
5029         case e1000_82576:
5030                 incval = E1000_INCVALUE_82576;
5031                 shift = IGB_82576_TSYNC_SHIFT;
5032                 E1000_WRITE_REG(hw, E1000_TIMINCA,
5033                                 E1000_INCPERIOD_82576 | incval);
5034                 break;
5035         default:
5036                 /* Not supported */
5037                 return;
5038         }
5039
5040         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5041         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5042         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5043
5044         adapter->systime_tc.cc_mask = mask;
5045         adapter->systime_tc.cc_shift = shift;
5046         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5047
5048         adapter->rx_tstamp_tc.cc_mask = mask;
5049         adapter->rx_tstamp_tc.cc_shift = shift;
5050         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5051
5052         adapter->tx_tstamp_tc.cc_mask = mask;
5053         adapter->tx_tstamp_tc.cc_shift = shift;
5054         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5055 }
5056
5057 static int
5058 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5059 {
5060         struct e1000_adapter *adapter =
5061                         (struct e1000_adapter *)dev->data->dev_private;
5062
5063         adapter->systime_tc.nsec += delta;
5064         adapter->rx_tstamp_tc.nsec += delta;
5065         adapter->tx_tstamp_tc.nsec += delta;
5066
5067         return 0;
5068 }
5069
5070 static int
5071 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5072 {
5073         uint64_t ns;
5074         struct e1000_adapter *adapter =
5075                         (struct e1000_adapter *)dev->data->dev_private;
5076
5077         ns = rte_timespec_to_ns(ts);
5078
5079         /* Set the timecounters to a new value. */
5080         adapter->systime_tc.nsec = ns;
5081         adapter->rx_tstamp_tc.nsec = ns;
5082         adapter->tx_tstamp_tc.nsec = ns;
5083
5084         return 0;
5085 }
5086
5087 static int
5088 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5089 {
5090         uint64_t ns, systime_cycles;
5091         struct e1000_adapter *adapter =
5092                         (struct e1000_adapter *)dev->data->dev_private;
5093
5094         systime_cycles = igb_read_systime_cyclecounter(dev);
5095         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5096         *ts = rte_ns_to_timespec(ns);
5097
5098         return 0;
5099 }
5100
5101 static int
5102 igb_timesync_enable(struct rte_eth_dev *dev)
5103 {
5104         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105         uint32_t tsync_ctl;
5106         uint32_t tsauxc;
5107
5108         /* Stop the timesync system time. */
5109         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5110         /* Reset the timesync system time value. */
5111         switch (hw->mac.type) {
5112         case e1000_82580:
5113         case e1000_i350:
5114         case e1000_i354:
5115         case e1000_i210:
5116         case e1000_i211:
5117                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5118                 /* fall-through */
5119         case e1000_82576:
5120                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5121                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5122                 break;
5123         default:
5124                 /* Not supported. */
5125                 return -ENOTSUP;
5126         }
5127
5128         /* Enable system time for it isn't on by default. */
5129         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5130         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5131         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5132
5133         igb_start_timecounters(dev);
5134
5135         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5136         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5137                         (ETHER_TYPE_1588 |
5138                          E1000_ETQF_FILTER_ENABLE |
5139                          E1000_ETQF_1588));
5140
5141         /* Enable timestamping of received PTP packets. */
5142         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5143         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5144         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5145
5146         /* Enable Timestamping of transmitted PTP packets. */
5147         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5148         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5149         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5150
5151         return 0;
5152 }
5153
5154 static int
5155 igb_timesync_disable(struct rte_eth_dev *dev)
5156 {
5157         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5158         uint32_t tsync_ctl;
5159
5160         /* Disable timestamping of transmitted PTP packets. */
5161         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5162         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5163         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5164
5165         /* Disable timestamping of received PTP packets. */
5166         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5167         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5168         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5169
5170         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5171         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5172
5173         /* Stop incrementating the System Time registers. */
5174         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5175
5176         return 0;
5177 }
5178
5179 static int
5180 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5181                                struct timespec *timestamp,
5182                                uint32_t flags __rte_unused)
5183 {
5184         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185         struct e1000_adapter *adapter =
5186                         (struct e1000_adapter *)dev->data->dev_private;
5187         uint32_t tsync_rxctl;
5188         uint64_t rx_tstamp_cycles;
5189         uint64_t ns;
5190
5191         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5192         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5193                 return -EINVAL;
5194
5195         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5196         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5197         *timestamp = rte_ns_to_timespec(ns);
5198
5199         return  0;
5200 }
5201
5202 static int
5203 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5204                                struct timespec *timestamp)
5205 {
5206         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5207         struct e1000_adapter *adapter =
5208                         (struct e1000_adapter *)dev->data->dev_private;
5209         uint32_t tsync_txctl;
5210         uint64_t tx_tstamp_cycles;
5211         uint64_t ns;
5212
5213         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5214         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5215                 return -EINVAL;
5216
5217         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5218         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5219         *timestamp = rte_ns_to_timespec(ns);
5220
5221         return  0;
5222 }
5223
5224 static int
5225 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5226 {
5227         int count = 0;
5228         int g_ind = 0;
5229         const struct reg_info *reg_group;
5230
5231         while ((reg_group = igb_regs[g_ind++]))
5232                 count += igb_reg_group_count(reg_group);
5233
5234         return count;
5235 }
5236
5237 static int
5238 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5239 {
5240         int count = 0;
5241         int g_ind = 0;
5242         const struct reg_info *reg_group;
5243
5244         while ((reg_group = igbvf_regs[g_ind++]))
5245                 count += igb_reg_group_count(reg_group);
5246
5247         return count;
5248 }
5249
5250 static int
5251 eth_igb_get_regs(struct rte_eth_dev *dev,
5252         struct rte_dev_reg_info *regs)
5253 {
5254         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255         uint32_t *data = regs->data;
5256         int g_ind = 0;
5257         int count = 0;
5258         const struct reg_info *reg_group;
5259
5260         if (data == NULL) {
5261                 regs->length = eth_igb_get_reg_length(dev);
5262                 regs->width = sizeof(uint32_t);
5263                 return 0;
5264         }
5265
5266         /* Support only full register dump */
5267         if ((regs->length == 0) ||
5268             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5269                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5270                         hw->device_id;
5271                 while ((reg_group = igb_regs[g_ind++]))
5272                         count += igb_read_regs_group(dev, &data[count],
5273                                                         reg_group);
5274                 return 0;
5275         }
5276
5277         return -ENOTSUP;
5278 }
5279
5280 static int
5281 igbvf_get_regs(struct rte_eth_dev *dev,
5282         struct rte_dev_reg_info *regs)
5283 {
5284         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5285         uint32_t *data = regs->data;
5286         int g_ind = 0;
5287         int count = 0;
5288         const struct reg_info *reg_group;
5289
5290         if (data == NULL) {
5291                 regs->length = igbvf_get_reg_length(dev);
5292                 regs->width = sizeof(uint32_t);
5293                 return 0;
5294         }
5295
5296         /* Support only full register dump */
5297         if ((regs->length == 0) ||
5298             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5299                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5300                         hw->device_id;
5301                 while ((reg_group = igbvf_regs[g_ind++]))
5302                         count += igb_read_regs_group(dev, &data[count],
5303                                                         reg_group);
5304                 return 0;
5305         }
5306
5307         return -ENOTSUP;
5308 }
5309
5310 static int
5311 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5312 {
5313         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5314
5315         /* Return unit is byte count */
5316         return hw->nvm.word_size * 2;
5317 }
5318
5319 static int
5320 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5321         struct rte_dev_eeprom_info *in_eeprom)
5322 {
5323         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5324         struct e1000_nvm_info *nvm = &hw->nvm;
5325         uint16_t *data = in_eeprom->data;
5326         int first, length;
5327
5328         first = in_eeprom->offset >> 1;
5329         length = in_eeprom->length >> 1;
5330         if ((first >= hw->nvm.word_size) ||
5331             ((first + length) >= hw->nvm.word_size))
5332                 return -EINVAL;
5333
5334         in_eeprom->magic = hw->vendor_id |
5335                 ((uint32_t)hw->device_id << 16);
5336
5337         if ((nvm->ops.read) == NULL)
5338                 return -ENOTSUP;
5339
5340         return nvm->ops.read(hw, first, length, data);
5341 }
5342
5343 static int
5344 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5345         struct rte_dev_eeprom_info *in_eeprom)
5346 {
5347         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5348         struct e1000_nvm_info *nvm = &hw->nvm;
5349         uint16_t *data = in_eeprom->data;
5350         int first, length;
5351
5352         first = in_eeprom->offset >> 1;
5353         length = in_eeprom->length >> 1;
5354         if ((first >= hw->nvm.word_size) ||
5355             ((first + length) >= hw->nvm.word_size))
5356                 return -EINVAL;
5357
5358         in_eeprom->magic = (uint32_t)hw->vendor_id |
5359                 ((uint32_t)hw->device_id << 16);
5360
5361         if ((nvm->ops.write) == NULL)
5362                 return -ENOTSUP;
5363         return nvm->ops.write(hw,  first, length, data);
5364 }
5365
5366 static int
5367 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5368 {
5369         struct e1000_hw *hw =
5370                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5371         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5372         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5373         uint32_t vec = E1000_MISC_VEC_ID;
5374
5375         if (rte_intr_allow_others(intr_handle))
5376                 vec = E1000_RX_VEC_START;
5377
5378         uint32_t mask = 1 << (queue_id + vec);
5379
5380         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5381         E1000_WRITE_FLUSH(hw);
5382
5383         return 0;
5384 }
5385
5386 static int
5387 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5388 {
5389         struct e1000_hw *hw =
5390                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5391         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5392         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5393         uint32_t vec = E1000_MISC_VEC_ID;
5394
5395         if (rte_intr_allow_others(intr_handle))
5396                 vec = E1000_RX_VEC_START;
5397
5398         uint32_t mask = 1 << (queue_id + vec);
5399         uint32_t regval;
5400
5401         regval = E1000_READ_REG(hw, E1000_EIMS);
5402         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5403         E1000_WRITE_FLUSH(hw);
5404
5405         rte_intr_enable(intr_handle);
5406
5407         return 0;
5408 }
5409
5410 static void
5411 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5412                    uint8_t index, uint8_t offset)
5413 {
5414         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5415
5416         /* clear bits */
5417         val &= ~((uint32_t)0xFF << offset);
5418
5419         /* write vector and valid bit */
5420         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5421
5422         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5423 }
5424
5425 static void
5426 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5427                            uint8_t queue, uint8_t msix_vector)
5428 {
5429         uint32_t tmp = 0;
5430
5431         if (hw->mac.type == e1000_82575) {
5432                 if (direction == 0)
5433                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5434                 else if (direction == 1)
5435                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5436                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5437         } else if (hw->mac.type == e1000_82576) {
5438                 if ((direction == 0) || (direction == 1))
5439                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5440                                            ((queue & 0x8) << 1) +
5441                                            8 * direction);
5442         } else if ((hw->mac.type == e1000_82580) ||
5443                         (hw->mac.type == e1000_i350) ||
5444                         (hw->mac.type == e1000_i354) ||
5445                         (hw->mac.type == e1000_i210) ||
5446                         (hw->mac.type == e1000_i211)) {
5447                 if ((direction == 0) || (direction == 1))
5448                         eth_igb_write_ivar(hw, msix_vector,
5449                                            queue >> 1,
5450                                            ((queue & 0x1) << 4) +
5451                                            8 * direction);
5452         }
5453 }
5454
5455 /* Sets up the hardware to generate MSI-X interrupts properly
5456  * @hw
5457  *  board private structure
5458  */
5459 static void
5460 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5461 {
5462         int queue_id;
5463         uint32_t tmpval, regval, intr_mask;
5464         struct e1000_hw *hw =
5465                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5466         uint32_t vec = E1000_MISC_VEC_ID;
5467         uint32_t base = E1000_MISC_VEC_ID;
5468         uint32_t misc_shift = 0;
5469         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5470         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5471
5472         /* won't configure msix register if no mapping is done
5473          * between intr vector and event fd
5474          */
5475         if (!rte_intr_dp_is_en(intr_handle))
5476                 return;
5477
5478         if (rte_intr_allow_others(intr_handle)) {
5479                 vec = base = E1000_RX_VEC_START;
5480                 misc_shift = 1;
5481         }
5482
5483         /* set interrupt vector for other causes */
5484         if (hw->mac.type == e1000_82575) {
5485                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5486                 /* enable MSI-X PBA support */
5487                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5488
5489                 /* Auto-Mask interrupts upon ICR read */
5490                 tmpval |= E1000_CTRL_EXT_EIAME;
5491                 tmpval |= E1000_CTRL_EXT_IRCA;
5492
5493                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5494
5495                 /* enable msix_other interrupt */
5496                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5497                 regval = E1000_READ_REG(hw, E1000_EIAC);
5498                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5499                 regval = E1000_READ_REG(hw, E1000_EIAM);
5500                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5501         } else if ((hw->mac.type == e1000_82576) ||
5502                         (hw->mac.type == e1000_82580) ||
5503                         (hw->mac.type == e1000_i350) ||
5504                         (hw->mac.type == e1000_i354) ||
5505                         (hw->mac.type == e1000_i210) ||
5506                         (hw->mac.type == e1000_i211)) {
5507                 /* turn on MSI-X capability first */
5508                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5509                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5510                                         E1000_GPIE_NSICR);
5511                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5512                         misc_shift;
5513                 regval = E1000_READ_REG(hw, E1000_EIAC);
5514                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5515
5516                 /* enable msix_other interrupt */
5517                 regval = E1000_READ_REG(hw, E1000_EIMS);
5518                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5519                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5520                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5521         }
5522
5523         /* use EIAM to auto-mask when MSI-X interrupt
5524          * is asserted, this saves a register write for every interrupt
5525          */
5526         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5527                 misc_shift;
5528         regval = E1000_READ_REG(hw, E1000_EIAM);
5529         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5530
5531         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5532                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5533                 intr_handle->intr_vec[queue_id] = vec;
5534                 if (vec < base + intr_handle->nb_efd - 1)
5535                         vec++;
5536         }
5537
5538         E1000_WRITE_FLUSH(hw);
5539 }
5540
5541 /* restore n-tuple filter */
5542 static inline void
5543 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5544 {
5545         struct e1000_filter_info *filter_info =
5546                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5547         struct e1000_5tuple_filter *p_5tuple;
5548         struct e1000_2tuple_filter *p_2tuple;
5549
5550         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5551                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5552         }
5553
5554         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5555                 igb_inject_2uple_filter(dev, p_2tuple);
5556         }
5557 }
5558
5559 /* restore SYN filter */
5560 static inline void
5561 igb_syn_filter_restore(struct rte_eth_dev *dev)
5562 {
5563         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         struct e1000_filter_info *filter_info =
5565                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5566         uint32_t synqf;
5567
5568         synqf = filter_info->syn_info;
5569
5570         if (synqf & E1000_SYN_FILTER_ENABLE) {
5571                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5572                 E1000_WRITE_FLUSH(hw);
5573         }
5574 }
5575
5576 /* restore ethernet type filter */
5577 static inline void
5578 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5579 {
5580         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581         struct e1000_filter_info *filter_info =
5582                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5583         int i;
5584
5585         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5586                 if (filter_info->ethertype_mask & (1 << i)) {
5587                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5588                                 filter_info->ethertype_filters[i].etqf);
5589                         E1000_WRITE_FLUSH(hw);
5590                 }
5591         }
5592 }
5593
5594 /* restore flex byte filter */
5595 static inline void
5596 igb_flex_filter_restore(struct rte_eth_dev *dev)
5597 {
5598         struct e1000_filter_info *filter_info =
5599                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5600         struct e1000_flex_filter *flex_filter;
5601
5602         TAILQ_FOREACH(flex_filter, &filter_info->flex_list, entries) {
5603                 igb_inject_flex_filter(dev, flex_filter);
5604         }
5605 }
5606
5607 /* restore rss filter */
5608 static inline void
5609 igb_rss_filter_restore(struct rte_eth_dev *dev)
5610 {
5611         struct e1000_filter_info *filter_info =
5612                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5613
5614         if (filter_info->rss_info.num)
5615                 igb_config_rss_filter(dev, &filter_info->rss_info, TRUE);
5616 }
5617
5618 /* restore all types filter */
5619 static int
5620 igb_filter_restore(struct rte_eth_dev *dev)
5621 {
5622         igb_ntuple_filter_restore(dev);
5623         igb_ethertype_filter_restore(dev);
5624         igb_syn_filter_restore(dev);
5625         igb_flex_filter_restore(dev);
5626         igb_rss_filter_restore(dev);
5627
5628         return 0;
5629 }
5630
5631 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5632 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5633 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5634 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5635 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5636 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");