drivers/net/e1000/igb_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <stdarg.h>
  39
  40 #include <rte_common.h>
  41 #include <rte_interrupts.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_log.h>
  44 #include <rte_debug.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memory.h>
  50 #include <rte_memzone.h>
  51 #include <rte_eal.h>
  52 #include <rte_atomic.h>
  53 #include <rte_malloc.h>
  54 #include <rte_dev.h>
  55
  56 #include "e1000_logs.h"
  57 #include "base/e1000_api.h"
  58 #include "e1000_ethdev.h"
  59 #include "igb_regs.h"
  60
  61 /*
  62  * Default values for port configuration
  63  */
  64 #define IGB_DEFAULT_RX_FREE_THRESH  32
  65
  66 #define IGB_DEFAULT_RX_PTHRESH      ((hw->mac.type == e1000_i354) ? 12 : 8)
  67 #define IGB_DEFAULT_RX_HTHRESH      8
  68 #define IGB_DEFAULT_RX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 4)
  69
  70 #define IGB_DEFAULT_TX_PTHRESH      ((hw->mac.type == e1000_i354) ? 20 : 8)
  71 #define IGB_DEFAULT_TX_HTHRESH      1
  72 #define IGB_DEFAULT_TX_WTHRESH      ((hw->mac.type == e1000_82576) ? 1 : 16)
  73
  74 #define IGB_HKEY_MAX_INDEX 10
  75
  76 /* Bit shift and mask */
  77 #define IGB_4_BIT_WIDTH  (CHAR_BIT / 2)
  78 #define IGB_4_BIT_MASK   RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)
  79 #define IGB_8_BIT_WIDTH  CHAR_BIT
  80 #define IGB_8_BIT_MASK   UINT8_MAX
  81
  82 /* Additional timesync values. */
  83 #define E1000_CYCLECOUNTER_MASK      0xffffffffffffffffULL
  84 #define E1000_ETQF_FILTER_1588       3
  85 #define IGB_82576_TSYNC_SHIFT        16
  86 #define E1000_INCPERIOD_82576        (1 << E1000_TIMINCA_16NS_SHIFT)
  87 #define E1000_INCVALUE_82576         (16 << IGB_82576_TSYNC_SHIFT)
  88 #define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
  89
  90 #define E1000_VTIVAR_MISC                0x01740
  91 #define E1000_VTIVAR_MISC_MASK           0xFF
  92 #define E1000_VTIVAR_VALID               0x80
  93 #define E1000_VTIVAR_MISC_MAILBOX        0
  94 #define E1000_VTIVAR_MISC_INTR_MASK      0x3
  95
  96 /* External VLAN Enable bit mask */
  97 #define E1000_CTRL_EXT_EXT_VLAN      (1 << 26)
  98
  99 /* External VLAN Ether Type bit mask and shift */
 100 #define E1000_VET_VET_EXT            0xFFFF0000
 101 #define E1000_VET_VET_EXT_SHIFT      16
 102
 103 static int  eth_igb_configure(struct rte_eth_dev *dev);
 104 static int  eth_igb_start(struct rte_eth_dev *dev);
 105 static void eth_igb_stop(struct rte_eth_dev *dev);
 106 static int  eth_igb_dev_set_link_up(struct rte_eth_dev *dev);
 107 static int  eth_igb_dev_set_link_down(struct rte_eth_dev *dev);
 108 static void eth_igb_close(struct rte_eth_dev *dev);
 109 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
 110 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
 111 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
 112 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
 113 static int  eth_igb_link_update(struct rte_eth_dev *dev,
 114                                 int wait_to_complete);
 115 static void eth_igb_stats_get(struct rte_eth_dev *dev,
 116                                 struct rte_eth_stats *rte_stats);
 117 static int eth_igb_xstats_get(struct rte_eth_dev *dev,
 118                               struct rte_eth_xstat *xstats, unsigned n);
 119 static int eth_igb_xstats_get_by_id(struct rte_eth_dev *dev,
 120                 const uint64_t *ids,
 121                 uint64_t *values, unsigned int n);
 122 static int eth_igb_xstats_get_names(struct rte_eth_dev *dev,
 123                                     struct rte_eth_xstat_name *xstats_names,
 124                                     unsigned int size);
 125 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
 126                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
 127                 unsigned int limit);
 128 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
 129 static void eth_igb_xstats_reset(struct rte_eth_dev *dev);
 130 static int eth_igb_fw_version_get(struct rte_eth_dev *dev,
 131                                    char *fw_version, size_t fw_size);
 132 static void eth_igb_infos_get(struct rte_eth_dev *dev,
 133                               struct rte_eth_dev_info *dev_info);
 134 static const uint32_t *eth_igb_supported_ptypes_get(struct rte_eth_dev *dev);
 135 static void eth_igbvf_infos_get(struct rte_eth_dev *dev,
 136                                 struct rte_eth_dev_info *dev_info);
 137 static int  eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,
 138                                 struct rte_eth_fc_conf *fc_conf);
 139 static int  eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
 140                                 struct rte_eth_fc_conf *fc_conf);
 141 static int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);
 142 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);
 143 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
 144 static int eth_igb_interrupt_action(struct rte_eth_dev *dev,
 145                                     struct rte_intr_handle *handle);
 146 static void eth_igb_interrupt_handler(void *param);
 147 static int  igb_hardware_init(struct e1000_hw *hw);
 148 static void igb_hw_control_acquire(struct e1000_hw *hw);
 149 static void igb_hw_control_release(struct e1000_hw *hw);
 150 static void igb_init_manageability(struct e1000_hw *hw);
 151 static void igb_release_manageability(struct e1000_hw *hw);
 152
 153 static int  eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154
 155 static int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
 156                 uint16_t vlan_id, int on);
 157 static int eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
 158                                  enum rte_vlan_type vlan_type,
 159                                  uint16_t tpid_id);
 160 static void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161
 162 static void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 163 static void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 164 static void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);
 165 static void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);
 166 static void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 167 static void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 168
 169 static int eth_igb_led_on(struct rte_eth_dev *dev);
 170 static int eth_igb_led_off(struct rte_eth_dev *dev);
 171
 172 static void igb_intr_disable(struct e1000_hw *hw);
 173 static int  igb_get_rx_buffer_size(struct e1000_hw *hw);
 174 static int eth_igb_rar_set(struct rte_eth_dev *dev,
 175                            struct ether_addr *mac_addr,
 176                            uint32_t index, uint32_t pool);
 177 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 178 static void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
 179                 struct ether_addr *addr);
 180
 181 static void igbvf_intr_disable(struct e1000_hw *hw);
 182 static int igbvf_dev_configure(struct rte_eth_dev *dev);
 183 static int igbvf_dev_start(struct rte_eth_dev *dev);
 184 static void igbvf_dev_stop(struct rte_eth_dev *dev);
 185 static void igbvf_dev_close(struct rte_eth_dev *dev);
 186 static void igbvf_promiscuous_enable(struct rte_eth_dev *dev);
 187 static void igbvf_promiscuous_disable(struct rte_eth_dev *dev);
 188 static void igbvf_allmulticast_enable(struct rte_eth_dev *dev);
 189 static void igbvf_allmulticast_disable(struct rte_eth_dev *dev);
 190 static int eth_igbvf_link_update(struct e1000_hw *hw);
 191 static void eth_igbvf_stats_get(struct rte_eth_dev *dev,
 192                                 struct rte_eth_stats *rte_stats);
 193 static int eth_igbvf_xstats_get(struct rte_eth_dev *dev,
 194                                 struct rte_eth_xstat *xstats, unsigned n);
 195 static int eth_igbvf_xstats_get_names(struct rte_eth_dev *dev,
 196                                       struct rte_eth_xstat_name *xstats_names,
 197                                       unsigned limit);
 198 static void eth_igbvf_stats_reset(struct rte_eth_dev *dev);
 199 static int igbvf_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);
 202 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 203 static void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,
 204                 struct ether_addr *addr);
 205 static int igbvf_get_reg_length(struct rte_eth_dev *dev);
 206 static int igbvf_get_regs(struct rte_eth_dev *dev,
 207                 struct rte_dev_reg_info *regs);
 208
 209 static int eth_igb_rss_reta_update(struct rte_eth_dev *dev,
 210                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 211                                    uint16_t reta_size);
 212 static int eth_igb_rss_reta_query(struct rte_eth_dev *dev,
 213                                   struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                   uint16_t reta_size);
 215
 216 static int eth_igb_syn_filter_set(struct rte_eth_dev *dev,
 217                         struct rte_eth_syn_filter *filter,
 218                         bool add);
 219 static int eth_igb_syn_filter_get(struct rte_eth_dev *dev,
 220                         struct rte_eth_syn_filter *filter);
 221 static int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
 222                         enum rte_filter_op filter_op,
 223                         void *arg);
 224 static int igb_add_2tuple_filter(struct rte_eth_dev *dev,
 225                         struct rte_eth_ntuple_filter *ntuple_filter);
 226 static int igb_remove_2tuple_filter(struct rte_eth_dev *dev,
 227                         struct rte_eth_ntuple_filter *ntuple_filter);
 228 static int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
 229                         struct rte_eth_flex_filter *filter,
 230                         bool add);
 231 static int eth_igb_get_flex_filter(struct rte_eth_dev *dev,
 232                         struct rte_eth_flex_filter *filter);
 233 static int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
 234                         enum rte_filter_op filter_op,
 235                         void *arg);
 236 static int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
 237                         struct rte_eth_ntuple_filter *ntuple_filter);
 238 static int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *ntuple_filter);
 240 static int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
 241                         struct rte_eth_ntuple_filter *filter,
 242                         bool add);
 243 static int igb_get_ntuple_filter(struct rte_eth_dev *dev,
 244                         struct rte_eth_ntuple_filter *filter);
 245 static int igb_ntuple_filter_handle(struct rte_eth_dev *dev,
 246                                 enum rte_filter_op filter_op,
 247                                 void *arg);
 248 static int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
 249                         struct rte_eth_ethertype_filter *filter,
 250                         bool add);
 251 static int igb_ethertype_filter_handle(struct rte_eth_dev *dev,
 252                                 enum rte_filter_op filter_op,
 253                                 void *arg);
 254 static int igb_get_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter);
 256 static int eth_igb_filter_ctrl(struct rte_eth_dev *dev,
 257                      enum rte_filter_type filter_type,
 258                      enum rte_filter_op filter_op,
 259                      void *arg);
 260 static int eth_igb_get_reg_length(struct rte_eth_dev *dev);
 261 static int eth_igb_get_regs(struct rte_eth_dev *dev,
 262                 struct rte_dev_reg_info *regs);
 263 static int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);
 264 static int eth_igb_get_eeprom(struct rte_eth_dev *dev,
 265                 struct rte_dev_eeprom_info *eeprom);
 266 static int eth_igb_set_eeprom(struct rte_eth_dev *dev,
 267                 struct rte_dev_eeprom_info *eeprom);
 268 static int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                     struct ether_addr *mc_addr_set,
 270                                     uint32_t nb_mc_addr);
 271 static int igb_timesync_enable(struct rte_eth_dev *dev);
 272 static int igb_timesync_disable(struct rte_eth_dev *dev);
 273 static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 274                                           struct timespec *timestamp,
 275                                           uint32_t flags);
 276 static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 277                                           struct timespec *timestamp);
 278 static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 279 static int igb_timesync_read_time(struct rte_eth_dev *dev,
 280                                   struct timespec *timestamp);
 281 static int igb_timesync_write_time(struct rte_eth_dev *dev,
 282                                    const struct timespec *timestamp);
 283 static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
 284                                         uint16_t queue_id);
 285 static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
 286                                          uint16_t queue_id);
 287 static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
 288                                        uint8_t queue, uint8_t msix_vector);
 289 static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
 290                                uint8_t index, uint8_t offset);
 291 static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
 292 static void eth_igbvf_interrupt_handler(void *param);
 293 static void igbvf_mbx_process(struct rte_eth_dev *dev);
 294 static int igb_filter_restore(struct rte_eth_dev *dev);
 295
 296 /*
 297  * Define VF Stats MACRO for Non "cleared on read" register
 298  */
 299 #define UPDATE_VF_STAT(reg, last, cur)            \
 300 {                                                 \
 301         u32 latest = E1000_READ_REG(hw, reg);     \
 302         cur += (latest - last) & UINT_MAX;        \
 303         last = latest;                            \
 304 }
 305
 306 #define IGB_FC_PAUSE_TIME 0x0680
 307 #define IGB_LINK_UPDATE_CHECK_TIMEOUT  90  /* 9s */
 308 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
 309
 310 #define IGBVF_PMD_NAME "rte_igbvf_pmd"     /* PMD name */
 311
 312 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
 313
 314 /*
 315  * The set of PCI devices this driver supports
 316  */
 317 static const struct rte_pci_id pci_id_igb_map[] = {
 318         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576) },
 319         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_FIBER) },
 320         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES) },
 321         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER) },
 322         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },
 323         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS) },
 324         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_NS_SERDES) },
 325         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_SERDES_QUAD) },
 326
 327         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_COPPER) },
 328         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575EB_FIBER_SERDES) },
 329         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82575GB_QUAD_COPPER) },
 330
 331         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER) },
 332         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_FIBER) },
 333         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SERDES) },
 334         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_SGMII) },
 335         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_COPPER_DUAL) },
 336         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82580_QUAD_FIBER) },
 337
 338         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_COPPER) },
 339         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_FIBER) },
 340         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SERDES) },
 341         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_SGMII) },
 342         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_DA4) },
 343         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER) },
 344         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_OEM1) },
 345         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_COPPER_IT) },
 346         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_FIBER) },
 347         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SERDES) },
 348         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I210_SGMII) },
 349         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I211_COPPER) },
 350         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
 351         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_SGMII) },
 352         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
 353         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SGMII) },
 354         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SERDES) },
 355         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_BACKPLANE) },
 356         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_DH89XXCC_SFP) },
 357         { .vendor_id = 0, /* sentinel */ },
 358 };
 359
 360 /*
 361  * The set of PCI devices this driver supports (for 82576&I350 VF)
 362  */
 363 static const struct rte_pci_id pci_id_igbvf_map[] = {
 364         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF) },
 365         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82576_VF_HV) },
 366         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF) },
 367         { RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_I350_VF_HV) },
 368         { .vendor_id = 0, /* sentinel */ },
 369 };
 370
 371 static const struct rte_eth_desc_lim rx_desc_lim = {
 372         .nb_max = E1000_MAX_RING_DESC,
 373         .nb_min = E1000_MIN_RING_DESC,
 374         .nb_align = IGB_RXD_ALIGN,
 375 };
 376
 377 static const struct rte_eth_desc_lim tx_desc_lim = {
 378         .nb_max = E1000_MAX_RING_DESC,
 379         .nb_min = E1000_MIN_RING_DESC,
 380         .nb_align = IGB_RXD_ALIGN,
 381         .nb_seg_max = IGB_TX_MAX_SEG,
 382         .nb_mtu_seg_max = IGB_TX_MAX_MTU_SEG,
 383 };
 384
 385 static const struct eth_dev_ops eth_igb_ops = {
 386         .dev_configure        = eth_igb_configure,
 387         .dev_start            = eth_igb_start,
 388         .dev_stop             = eth_igb_stop,
 389         .dev_set_link_up      = eth_igb_dev_set_link_up,
 390         .dev_set_link_down    = eth_igb_dev_set_link_down,
 391         .dev_close            = eth_igb_close,
 392         .promiscuous_enable   = eth_igb_promiscuous_enable,
 393         .promiscuous_disable  = eth_igb_promiscuous_disable,
 394         .allmulticast_enable  = eth_igb_allmulticast_enable,
 395         .allmulticast_disable = eth_igb_allmulticast_disable,
 396         .link_update          = eth_igb_link_update,
 397         .stats_get            = eth_igb_stats_get,
 398         .xstats_get           = eth_igb_xstats_get,
 399         .xstats_get_by_id     = eth_igb_xstats_get_by_id,
 400         .xstats_get_names_by_id = eth_igb_xstats_get_names_by_id,
 401         .xstats_get_names     = eth_igb_xstats_get_names,
 402         .stats_reset          = eth_igb_stats_reset,
 403         .xstats_reset         = eth_igb_xstats_reset,
 404         .fw_version_get       = eth_igb_fw_version_get,
 405         .dev_infos_get        = eth_igb_infos_get,
 406         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 407         .mtu_set              = eth_igb_mtu_set,
 408         .vlan_filter_set      = eth_igb_vlan_filter_set,
 409         .vlan_tpid_set        = eth_igb_vlan_tpid_set,
 410         .vlan_offload_set     = eth_igb_vlan_offload_set,
 411         .rx_queue_setup       = eth_igb_rx_queue_setup,
 412         .rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,
 413         .rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,
 414         .rx_queue_release     = eth_igb_rx_queue_release,
 415         .rx_queue_count       = eth_igb_rx_queue_count,
 416         .rx_descriptor_done   = eth_igb_rx_descriptor_done,
 417         .rx_descriptor_status = eth_igb_rx_descriptor_status,
 418         .tx_descriptor_status = eth_igb_tx_descriptor_status,
 419         .tx_queue_setup       = eth_igb_tx_queue_setup,
 420         .tx_queue_release     = eth_igb_tx_queue_release,
 421         .tx_done_cleanup      = eth_igb_tx_done_cleanup,
 422         .dev_led_on           = eth_igb_led_on,
 423         .dev_led_off          = eth_igb_led_off,
 424         .flow_ctrl_get        = eth_igb_flow_ctrl_get,
 425         .flow_ctrl_set        = eth_igb_flow_ctrl_set,
 426         .mac_addr_add         = eth_igb_rar_set,
 427         .mac_addr_remove      = eth_igb_rar_clear,
 428         .mac_addr_set         = eth_igb_default_mac_addr_set,
 429         .reta_update          = eth_igb_rss_reta_update,
 430         .reta_query           = eth_igb_rss_reta_query,
 431         .rss_hash_update      = eth_igb_rss_hash_update,
 432         .rss_hash_conf_get    = eth_igb_rss_hash_conf_get,
 433         .filter_ctrl          = eth_igb_filter_ctrl,
 434         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 435         .rxq_info_get         = igb_rxq_info_get,
 436         .txq_info_get         = igb_txq_info_get,
 437         .timesync_enable      = igb_timesync_enable,
 438         .timesync_disable     = igb_timesync_disable,
 439         .timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,
 440         .timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,
 441         .get_reg              = eth_igb_get_regs,
 442         .get_eeprom_length    = eth_igb_get_eeprom_length,
 443         .get_eeprom           = eth_igb_get_eeprom,
 444         .set_eeprom           = eth_igb_set_eeprom,
 445         .timesync_adjust_time = igb_timesync_adjust_time,
 446         .timesync_read_time   = igb_timesync_read_time,
 447         .timesync_write_time  = igb_timesync_write_time,
 448 };
 449
 450 /*
 451  * dev_ops for virtual function, bare necessities for basic vf
 452  * operation have been implemented
 453  */
 454 static const struct eth_dev_ops igbvf_eth_dev_ops = {
 455         .dev_configure        = igbvf_dev_configure,
 456         .dev_start            = igbvf_dev_start,
 457         .dev_stop             = igbvf_dev_stop,
 458         .dev_close            = igbvf_dev_close,
 459         .promiscuous_enable   = igbvf_promiscuous_enable,
 460         .promiscuous_disable  = igbvf_promiscuous_disable,
 461         .allmulticast_enable  = igbvf_allmulticast_enable,
 462         .allmulticast_disable = igbvf_allmulticast_disable,
 463         .link_update          = eth_igb_link_update,
 464         .stats_get            = eth_igbvf_stats_get,
 465         .xstats_get           = eth_igbvf_xstats_get,
 466         .xstats_get_names     = eth_igbvf_xstats_get_names,
 467         .stats_reset          = eth_igbvf_stats_reset,
 468         .xstats_reset         = eth_igbvf_stats_reset,
 469         .vlan_filter_set      = igbvf_vlan_filter_set,
 470         .dev_infos_get        = eth_igbvf_infos_get,
 471         .dev_supported_ptypes_get = eth_igb_supported_ptypes_get,
 472         .rx_queue_setup       = eth_igb_rx_queue_setup,
 473         .rx_queue_release     = eth_igb_rx_queue_release,
 474         .tx_queue_setup       = eth_igb_tx_queue_setup,
 475         .tx_queue_release     = eth_igb_tx_queue_release,
 476         .set_mc_addr_list     = eth_igb_set_mc_addr_list,
 477         .rxq_info_get         = igb_rxq_info_get,
 478         .txq_info_get         = igb_txq_info_get,
 479         .mac_addr_set         = igbvf_default_mac_addr_set,
 480         .get_reg              = igbvf_get_regs,
 481 };
 482
 483 /* store statistics names and its offset in stats structure */
 484 struct rte_igb_xstats_name_off {
 485         char name[RTE_ETH_XSTATS_NAME_SIZE];
 486         unsigned offset;
 487 };
 488
 489 static const struct rte_igb_xstats_name_off rte_igb_stats_strings[] = {
 490         {"rx_crc_errors", offsetof(struct e1000_hw_stats, crcerrs)},
 491         {"rx_align_errors", offsetof(struct e1000_hw_stats, algnerrc)},
 492         {"rx_symbol_errors", offsetof(struct e1000_hw_stats, symerrs)},
 493         {"rx_missed_packets", offsetof(struct e1000_hw_stats, mpc)},
 494         {"tx_single_collision_packets", offsetof(struct e1000_hw_stats, scc)},
 495         {"tx_multiple_collision_packets", offsetof(struct e1000_hw_stats, mcc)},
 496         {"tx_excessive_collision_packets", offsetof(struct e1000_hw_stats,
 497                 ecol)},
 498         {"tx_late_collisions", offsetof(struct e1000_hw_stats, latecol)},
 499         {"tx_total_collisions", offsetof(struct e1000_hw_stats, colc)},
 500         {"tx_deferred_packets", offsetof(struct e1000_hw_stats, dc)},
 501         {"tx_no_carrier_sense_packets", offsetof(struct e1000_hw_stats, tncrs)},
 502         {"rx_carrier_ext_errors", offsetof(struct e1000_hw_stats, cexterr)},
 503         {"rx_length_errors", offsetof(struct e1000_hw_stats, rlec)},
 504         {"rx_xon_packets", offsetof(struct e1000_hw_stats, xonrxc)},
 505         {"tx_xon_packets", offsetof(struct e1000_hw_stats, xontxc)},
 506         {"rx_xoff_packets", offsetof(struct e1000_hw_stats, xoffrxc)},
 507         {"tx_xoff_packets", offsetof(struct e1000_hw_stats, xofftxc)},
 508         {"rx_flow_control_unsupported_packets", offsetof(struct e1000_hw_stats,
 509                 fcruc)},
 510         {"rx_size_64_packets", offsetof(struct e1000_hw_stats, prc64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, prc127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, prc255)},
 513         {"rx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, prc511)},
 514         {"rx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 515                 prc1023)},
 516         {"rx_size_1024_to_max_packets", offsetof(struct e1000_hw_stats,
 517                 prc1522)},
 518         {"rx_broadcast_packets", offsetof(struct e1000_hw_stats, bprc)},
 519         {"rx_multicast_packets", offsetof(struct e1000_hw_stats, mprc)},
 520         {"rx_undersize_errors", offsetof(struct e1000_hw_stats, ruc)},
 521         {"rx_fragment_errors", offsetof(struct e1000_hw_stats, rfc)},
 522         {"rx_oversize_errors", offsetof(struct e1000_hw_stats, roc)},
 523         {"rx_jabber_errors", offsetof(struct e1000_hw_stats, rjc)},
 524         {"rx_management_packets", offsetof(struct e1000_hw_stats, mgprc)},
 525         {"rx_management_dropped", offsetof(struct e1000_hw_stats, mgpdc)},
 526         {"tx_management_packets", offsetof(struct e1000_hw_stats, mgptc)},
 527         {"rx_total_packets", offsetof(struct e1000_hw_stats, tpr)},
 528         {"tx_total_packets", offsetof(struct e1000_hw_stats, tpt)},
 529         {"rx_total_bytes", offsetof(struct e1000_hw_stats, tor)},
 530         {"tx_total_bytes", offsetof(struct e1000_hw_stats, tot)},
 531         {"tx_size_64_packets", offsetof(struct e1000_hw_stats, ptc64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct e1000_hw_stats, ptc127)},
 533         {"tx_size_128_to_255_packets", offsetof(struct e1000_hw_stats, ptc255)},
 534         {"tx_size_256_to_511_packets", offsetof(struct e1000_hw_stats, ptc511)},
 535         {"tx_size_512_to_1023_packets", offsetof(struct e1000_hw_stats,
 536                 ptc1023)},
 537         {"tx_size_1023_to_max_packets", offsetof(struct e1000_hw_stats,
 538                 ptc1522)},
 539         {"tx_multicast_packets", offsetof(struct e1000_hw_stats, mptc)},
 540         {"tx_broadcast_packets", offsetof(struct e1000_hw_stats, bptc)},
 541         {"tx_tso_packets", offsetof(struct e1000_hw_stats, tsctc)},
 542         {"tx_tso_errors", offsetof(struct e1000_hw_stats, tsctfc)},
 543         {"rx_sent_to_host_packets", offsetof(struct e1000_hw_stats, rpthc)},
 544         {"tx_sent_by_host_packets", offsetof(struct e1000_hw_stats, hgptc)},
 545         {"rx_code_violation_packets", offsetof(struct e1000_hw_stats, scvpc)},
 546
 547         {"interrupt_assert_count", offsetof(struct e1000_hw_stats, iac)},
 548 };
 549
 550 #define IGB_NB_XSTATS (sizeof(rte_igb_stats_strings) / \
 551                 sizeof(rte_igb_stats_strings[0]))
 552
 553 static const struct rte_igb_xstats_name_off rte_igbvf_stats_strings[] = {
 554         {"rx_multicast_packets", offsetof(struct e1000_vf_stats, mprc)},
 555         {"rx_good_loopback_packets", offsetof(struct e1000_vf_stats, gprlbc)},
 556         {"tx_good_loopback_packets", offsetof(struct e1000_vf_stats, gptlbc)},
 557         {"rx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gorlbc)},
 558         {"tx_good_loopback_bytes", offsetof(struct e1000_vf_stats, gotlbc)},
 559 };
 560
 561 #define IGBVF_NB_XSTATS (sizeof(rte_igbvf_stats_strings) / \
 562                 sizeof(rte_igbvf_stats_strings[0]))
 563
 564 /**
 565  * Atomically reads the link status information from global
 566  * structure rte_eth_dev.
 567  *
 568  * @param dev
 569  *   - Pointer to the structure rte_eth_dev to read from.
 570  *   - Pointer to the buffer to be saved with the link status.
 571  *
 572  * @return
 573  *   - On success, zero.
 574  *   - On failure, negative value.
 575  */
 576 static inline int
 577 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 578                                 struct rte_eth_link *link)
 579 {
 580         struct rte_eth_link *dst = link;
 581         struct rte_eth_link *src = &(dev->data->dev_link);
 582
 583         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 584                                         *(uint64_t *)src) == 0)
 585                 return -1;
 586
 587         return 0;
 588 }
 589
 590 /**
 591  * Atomically writes the link status information into global
 592  * structure rte_eth_dev.
 593  *
 594  * @param dev
 595  *   - Pointer to the structure rte_eth_dev to read from.
 596  *   - Pointer to the buffer to be saved with the link status.
 597  *
 598  * @return
 599  *   - On success, zero.
 600  *   - On failure, negative value.
 601  */
 602 static inline int
 603 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 604                                 struct rte_eth_link *link)
 605 {
 606         struct rte_eth_link *dst = &(dev->data->dev_link);
 607         struct rte_eth_link *src = link;
 608
 609         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 610                                         *(uint64_t *)src) == 0)
 611                 return -1;
 612
 613         return 0;
 614 }
 615
 616 static inline void
 617 igb_intr_enable(struct rte_eth_dev *dev)
 618 {
 619         struct e1000_interrupt *intr =
 620                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 621         struct e1000_hw *hw =
 622                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623
 624         E1000_WRITE_REG(hw, E1000_IMS, intr->mask);
 625         E1000_WRITE_FLUSH(hw);
 626 }
 627
 628 static void
 629 igb_intr_disable(struct e1000_hw *hw)
 630 {
 631         E1000_WRITE_REG(hw, E1000_IMC, ~0);
 632         E1000_WRITE_FLUSH(hw);
 633 }
 634
 635 static inline void
 636 igbvf_intr_enable(struct rte_eth_dev *dev)
 637 {
 638         struct e1000_hw *hw =
 639                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         /* only for mailbox */
 642         E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
 643         E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
 644         E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
 645         E1000_WRITE_FLUSH(hw);
 646 }
 647
 648 /* only for mailbox now. If RX/TX needed, should extend this function.  */
 649 static void
 650 igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
 651 {
 652         uint32_t tmp = 0;
 653
 654         /* mailbox */
 655         tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
 656         tmp |= E1000_VTIVAR_VALID;
 657         E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
 658 }
 659
 660 static void
 661 eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
 662 {
 663         struct e1000_hw *hw =
 664                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 665
 666         /* Configure VF other cause ivar */
 667         igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
 668 }
 669
 670 static inline int32_t
 671 igb_pf_reset_hw(struct e1000_hw *hw)
 672 {
 673         uint32_t ctrl_ext;
 674         int32_t status;
 675
 676         status = e1000_reset_hw(hw);
 677
 678         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 679         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 680         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 681         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 682         E1000_WRITE_FLUSH(hw);
 683
 684         return status;
 685 }
 686
 687 static void
 688 igb_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
 689 {
 690         struct e1000_hw *hw =
 691                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 692
 693
 694         hw->vendor_id = pci_dev->id.vendor_id;
 695         hw->device_id = pci_dev->id.device_id;
 696         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 697         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 698
 699         e1000_set_mac_type(hw);
 700
 701         /* need to check if it is a vf device below */
 702 }
 703
 704 static int
 705 igb_reset_swfw_lock(struct e1000_hw *hw)
 706 {
 707         int ret_val;
 708
 709         /*
 710          * Do mac ops initialization manually here, since we will need
 711          * some function pointers set by this call.
 712          */
 713         ret_val = e1000_init_mac_params(hw);
 714         if (ret_val)
 715                 return ret_val;
 716
 717         /*
 718          * SMBI lock should not fail in this early stage. If this is the case,
 719          * it is due to an improper exit of the application.
 720          * So force the release of the faulty lock.
 721          */
 722         if (e1000_get_hw_semaphore_generic(hw) < 0) {
 723                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
 724         }
 725         e1000_put_hw_semaphore_generic(hw);
 726
 727         if (hw->mac.ops.acquire_swfw_sync != NULL) {
 728                 uint16_t mask;
 729
 730                 /*
 731                  * Phy lock should not fail in this early stage. If this is the case,
 732                  * it is due to an improper exit of the application.
 733                  * So force the release of the faulty lock.
 734                  */
 735                 mask = E1000_SWFW_PHY0_SM << hw->bus.func;
 736                 if (hw->bus.func > E1000_FUNC_1)
 737                         mask <<= 2;
 738                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 739                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
 740                                     hw->bus.func);
 741                 }
 742                 hw->mac.ops.release_swfw_sync(hw, mask);
 743
 744                 /*
 745                  * This one is more tricky since it is common to all ports; but
 746                  * swfw_sync retries last long enough (1s) to be almost sure that if
 747                  * lock can not be taken it is due to an improper lock of the
 748                  * semaphore.
 749                  */
 750                 mask = E1000_SWFW_EEP_SM;
 751                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
 752                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 753                 }
 754                 hw->mac.ops.release_swfw_sync(hw, mask);
 755         }
 756
 757         return E1000_SUCCESS;
 758 }
 759
 760 /* Remove all ntuple filters of the device */
 761 static int igb_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 762 {
 763         struct e1000_filter_info *filter_info =
 764                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 765         struct e1000_5tuple_filter *p_5tuple;
 766         struct e1000_2tuple_filter *p_2tuple;
 767
 768         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 769                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 770                         p_5tuple, entries);
 771                         rte_free(p_5tuple);
 772         }
 773         filter_info->fivetuple_mask = 0;
 774         while ((p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list))) {
 775                 TAILQ_REMOVE(&filter_info->twotuple_list,
 776                         p_2tuple, entries);
 777                         rte_free(p_2tuple);
 778         }
 779         filter_info->twotuple_mask = 0;
 780
 781         return 0;
 782 }
 783
 784 static int
 785 eth_igb_dev_init(struct rte_eth_dev *eth_dev)
 786 {
 787         int error = 0;
 788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 789         struct e1000_hw *hw =
 790                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 791         struct e1000_vfta * shadow_vfta =
 792                 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 793         struct e1000_filter_info *filter_info =
 794                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 795         struct e1000_adapter *adapter =
 796                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 797
 798         uint32_t ctrl_ext;
 799
 800         eth_dev->dev_ops = &eth_igb_ops;
 801         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
 802         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
 803         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
 804
 805         /* for secondary processes, we don't initialise any further as primary
 806          * has already done this work. Only check we don't need a different
 807          * RX function */
 808         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 809                 if (eth_dev->data->scattered_rx)
 810                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
 811                 return 0;
 812         }
 813
 814         rte_eth_copy_pci_info(eth_dev, pci_dev);
 815         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 816
 817         hw->hw_addr= (void *)pci_dev->mem_resource[0].addr;
 818
 819         igb_identify_hardware(eth_dev, pci_dev);
 820         if (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {
 821                 error = -EIO;
 822                 goto err_late;
 823         }
 824
 825         e1000_get_bus_info(hw);
 826
 827         /* Reset any pending lock */
 828         if (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {
 829                 error = -EIO;
 830                 goto err_late;
 831         }
 832
 833         /* Finish initialization */
 834         if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
 835                 error = -EIO;
 836                 goto err_late;
 837         }
 838
 839         hw->mac.autoneg = 1;
 840         hw->phy.autoneg_wait_to_complete = 0;
 841         hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
 842
 843         /* Copper options */
 844         if (hw->phy.media_type == e1000_media_type_copper) {
 845                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
 846                 hw->phy.disable_polarity_correction = 0;
 847                 hw->phy.ms_type = e1000_ms_hw_default;
 848         }
 849
 850         /*
 851          * Start from a known state, this is important in reading the nvm
 852          * and mac from that.
 853          */
 854         igb_pf_reset_hw(hw);
 855
 856         /* Make sure we have a good EEPROM before we read from it */
 857         if (e1000_validate_nvm_checksum(hw) < 0) {
 858                 /*
 859                  * Some PCI-E parts fail the first check due to
 860                  * the link being in sleep state, call it again,
 861                  * if it fails a second time its a real issue.
 862                  */
 863                 if (e1000_validate_nvm_checksum(hw) < 0) {
 864                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
 865                         error = -EIO;
 866                         goto err_late;
 867                 }
 868         }
 869
 870         /* Read the permanent MAC address out of the EEPROM */
 871         if (e1000_read_mac_addr(hw) != 0) {
 872                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
 873                 error = -EIO;
 874                 goto err_late;
 875         }
 876
 877         /* Allocate memory for storing MAC addresses */
 878         eth_dev->data->mac_addrs = rte_zmalloc("e1000",
 879                 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
 880         if (eth_dev->data->mac_addrs == NULL) {
 881                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
 882                                                 "store MAC addresses",
 883                                 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
 884                 error = -ENOMEM;
 885                 goto err_late;
 886         }
 887
 888         /* Copy the permanent MAC address */
 889         ether_addr_copy((struct ether_addr *)hw->mac.addr, &eth_dev->data->mac_addrs[0]);
 890
 891         /* initialize the vfta */
 892         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 893
 894         /* Now initialize the hardware */
 895         if (igb_hardware_init(hw) != 0) {
 896                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
 897                 rte_free(eth_dev->data->mac_addrs);
 898                 eth_dev->data->mac_addrs = NULL;
 899                 error = -ENODEV;
 900                 goto err_late;
 901         }
 902         hw->mac.get_link_status = 1;
 903         adapter->stopped = 0;
 904
 905         /* Indicate SOL/IDER usage */
 906         if (e1000_check_reset_block(hw) < 0) {
 907                 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
 908                                         "SOL/IDER session");
 909         }
 910
 911         /* initialize PF if max_vfs not zero */
 912         igb_pf_host_init(eth_dev);
 913
 914         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 915         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 916         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
 917         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 918         E1000_WRITE_FLUSH(hw);
 919
 920         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
 921                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 922                      pci_dev->id.device_id);
 923
 924         rte_intr_callback_register(&pci_dev->intr_handle,
 925                                    eth_igb_interrupt_handler,
 926                                    (void *)eth_dev);
 927
 928         /* enable uio/vfio intr/eventfd mapping */
 929         rte_intr_enable(&pci_dev->intr_handle);
 930
 931         /* enable support intr */
 932         igb_intr_enable(eth_dev);
 933
 934         /* initialize filter info */
 935         memset(filter_info, 0,
 936                sizeof(struct e1000_filter_info));
 937
 938         TAILQ_INIT(&filter_info->flex_list);
 939         TAILQ_INIT(&filter_info->twotuple_list);
 940         TAILQ_INIT(&filter_info->fivetuple_list);
 941
 942         return 0;
 943
 944 err_late:
 945         igb_hw_control_release(hw);
 946
 947         return error;
 948 }
 949
 950 static int
 951 eth_igb_dev_uninit(struct rte_eth_dev *eth_dev)
 952 {
 953         struct rte_pci_device *pci_dev;
 954         struct rte_intr_handle *intr_handle;
 955         struct e1000_hw *hw;
 956         struct e1000_adapter *adapter =
 957                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
 958         struct e1000_filter_info *filter_info =
 959                 E1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 964                 return -EPERM;
 965
 966         hw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 967         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 968         intr_handle = &pci_dev->intr_handle;
 969
 970         if (adapter->stopped == 0)
 971                 eth_igb_close(eth_dev);
 972
 973         eth_dev->dev_ops = NULL;
 974         eth_dev->rx_pkt_burst = NULL;
 975         eth_dev->tx_pkt_burst = NULL;
 976
 977         /* Reset any pending lock */
 978         igb_reset_swfw_lock(hw);
 979
 980         rte_free(eth_dev->data->mac_addrs);
 981         eth_dev->data->mac_addrs = NULL;
 982
 983         /* uninitialize PF if max_vfs not zero */
 984         igb_pf_host_uninit(eth_dev);
 985
 986         /* disable uio intr before callback unregister */
 987         rte_intr_disable(intr_handle);
 988         rte_intr_callback_unregister(intr_handle,
 989                                      eth_igb_interrupt_handler, eth_dev);
 990
 991         /* clear the SYN filter info */
 992         filter_info->syn_info = 0;
 993
 994         /* clear the ethertype filters info */
 995         filter_info->ethertype_mask = 0;
 996         memset(filter_info->ethertype_filters, 0,
 997                 E1000_MAX_ETQF_FILTERS * sizeof(struct igb_ethertype_filter));
 998
 999         /* remove all ntuple filters of the device */
1000         igb_ntuple_filter_uninit(eth_dev);
1001
1002         return 0;
1003 }
1004
1005 /*
1006  * Virtual Function device init
1007  */
1008 static int
1009 eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
1010 {
1011         struct rte_pci_device *pci_dev;
1012         struct rte_intr_handle *intr_handle;
1013         struct e1000_adapter *adapter =
1014                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1015         struct e1000_hw *hw =
1016                 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1017         int diag;
1018         struct ether_addr *perm_addr = (struct ether_addr *)hw->mac.perm_addr;
1019
1020         PMD_INIT_FUNC_TRACE();
1021
1022         eth_dev->dev_ops = &igbvf_eth_dev_ops;
1023         eth_dev->rx_pkt_burst = &eth_igb_recv_pkts;
1024         eth_dev->tx_pkt_burst = &eth_igb_xmit_pkts;
1025         eth_dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1026
1027         /* for secondary processes, we don't initialise any further as primary
1028          * has already done this work. Only check we don't need a different
1029          * RX function */
1030         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1031                 if (eth_dev->data->scattered_rx)
1032                         eth_dev->rx_pkt_burst = &eth_igb_recv_scattered_pkts;
1033                 return 0;
1034         }
1035
1036         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1037         rte_eth_copy_pci_info(eth_dev, pci_dev);
1038         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1039
1040         hw->device_id = pci_dev->id.device_id;
1041         hw->vendor_id = pci_dev->id.vendor_id;
1042         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1043         adapter->stopped = 0;
1044
1045         /* Initialize the shared code (base driver) */
1046         diag = e1000_setup_init_funcs(hw, TRUE);
1047         if (diag != 0) {
1048                 PMD_INIT_LOG(ERR, "Shared code init failed for igbvf: %d",
1049                         diag);
1050                 return -EIO;
1051         }
1052
1053         /* init_mailbox_params */
1054         hw->mbx.ops.init_params(hw);
1055
1056         /* Disable the interrupts for VF */
1057         igbvf_intr_disable(hw);
1058
1059         diag = hw->mac.ops.reset_hw(hw);
1060
1061         /* Allocate memory for storing MAC addresses */
1062         eth_dev->data->mac_addrs = rte_zmalloc("igbvf", ETHER_ADDR_LEN *
1063                 hw->mac.rar_entry_count, 0);
1064         if (eth_dev->data->mac_addrs == NULL) {
1065                 PMD_INIT_LOG(ERR,
1066                         "Failed to allocate %d bytes needed to store MAC "
1067                         "addresses",
1068                         ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1069                 return -ENOMEM;
1070         }
1071
1072         /* Generate a random MAC address, if none was assigned by PF. */
1073         if (is_zero_ether_addr(perm_addr)) {
1074                 eth_random_addr(perm_addr->addr_bytes);
1075                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1076                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1077                              "%02x:%02x:%02x:%02x:%02x:%02x",
1078                              perm_addr->addr_bytes[0],
1079                              perm_addr->addr_bytes[1],
1080                              perm_addr->addr_bytes[2],
1081                              perm_addr->addr_bytes[3],
1082                              perm_addr->addr_bytes[4],
1083                              perm_addr->addr_bytes[5]);
1084         }
1085
1086         diag = e1000_rar_set(hw, perm_addr->addr_bytes, 0);
1087         if (diag) {
1088                 rte_free(eth_dev->data->mac_addrs);
1089                 eth_dev->data->mac_addrs = NULL;
1090                 return diag;
1091         }
1092         /* Copy the permanent MAC address */
1093         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1094                         &eth_dev->data->mac_addrs[0]);
1095
1096         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x "
1097                      "mac.type=%s",
1098                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1099                      pci_dev->id.device_id, "igb_mac_82576_vf");
1100
1101         intr_handle = &pci_dev->intr_handle;
1102         rte_intr_callback_register(intr_handle,
1103                                    eth_igbvf_interrupt_handler, eth_dev);
1104
1105         return 0;
1106 }
1107
1108 static int
1109 eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
1110 {
1111         struct e1000_adapter *adapter =
1112                 E1000_DEV_PRIVATE(eth_dev->data->dev_private);
1113         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1114
1115         PMD_INIT_FUNC_TRACE();
1116
1117         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1118                 return -EPERM;
1119
1120         if (adapter->stopped == 0)
1121                 igbvf_dev_close(eth_dev);
1122
1123         eth_dev->dev_ops = NULL;
1124         eth_dev->rx_pkt_burst = NULL;
1125         eth_dev->tx_pkt_burst = NULL;
1126
1127         rte_free(eth_dev->data->mac_addrs);
1128         eth_dev->data->mac_addrs = NULL;
1129
1130         /* disable uio intr before callback unregister */
1131         rte_intr_disable(&pci_dev->intr_handle);
1132         rte_intr_callback_unregister(&pci_dev->intr_handle,
1133                                      eth_igbvf_interrupt_handler,
1134                                      (void *)eth_dev);
1135
1136         return 0;
1137 }
1138
1139 static int eth_igb_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1140         struct rte_pci_device *pci_dev)
1141 {
1142         return rte_eth_dev_pci_generic_probe(pci_dev,
1143                 sizeof(struct e1000_adapter), eth_igb_dev_init);
1144 }
1145
1146 static int eth_igb_pci_remove(struct rte_pci_device *pci_dev)
1147 {
1148         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igb_dev_uninit);
1149 }
1150
1151 static struct rte_pci_driver rte_igb_pmd = {
1152         .id_table = pci_id_igb_map,
1153         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1154         .probe = eth_igb_pci_probe,
1155         .remove = eth_igb_pci_remove,
1156 };
1157
1158
1159 static int eth_igbvf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1160         struct rte_pci_device *pci_dev)
1161 {
1162         return rte_eth_dev_pci_generic_probe(pci_dev,
1163                 sizeof(struct e1000_adapter), eth_igbvf_dev_init);
1164 }
1165
1166 static int eth_igbvf_pci_remove(struct rte_pci_device *pci_dev)
1167 {
1168         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igbvf_dev_uninit);
1169 }
1170
1171 /*
1172  * virtual function driver struct
1173  */
1174 static struct rte_pci_driver rte_igbvf_pmd = {
1175         .id_table = pci_id_igbvf_map,
1176         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1177         .probe = eth_igbvf_pci_probe,
1178         .remove = eth_igbvf_pci_remove,
1179 };
1180
1181 static void
1182 igb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1183 {
1184         struct e1000_hw *hw =
1185                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186         /* RCTL: enable VLAN filter since VMDq always use VLAN filter */
1187         uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);
1188         rctl |= E1000_RCTL_VFE;
1189         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1190 }
1191
1192 static int
1193 igb_check_mq_mode(struct rte_eth_dev *dev)
1194 {
1195         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1196         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1197         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1198         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1199
1200         if ((rx_mq_mode & ETH_MQ_RX_DCB_FLAG) ||
1201             tx_mq_mode == ETH_MQ_TX_DCB ||
1202             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1203                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
1204                 return -EINVAL;
1205         }
1206         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1207                 /* Check multi-queue mode.
1208                  * To no break software we accept ETH_MQ_RX_NONE as this might
1209                  * be used to turn off VLAN filter.
1210                  */
1211
1212                 if (rx_mq_mode == ETH_MQ_RX_NONE ||
1213                     rx_mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1214                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1215                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1216                 } else {
1217                         /* Only support one queue on VFs.
1218                          * RSS together with SRIOV is not supported.
1219                          */
1220                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1221                                         " wrong mq_mode rx %d.",
1222                                         rx_mq_mode);
1223                         return -EINVAL;
1224                 }
1225                 /* TX mode is not used here, so mode might be ignored.*/
1226                 if (tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1227                         /* SRIOV only works in VMDq enable mode */
1228                         PMD_INIT_LOG(WARNING, "SRIOV is active,"
1229                                         " TX mode %d is not supported. "
1230                                         " Driver will behave as %d mode.",
1231                                         tx_mq_mode, ETH_MQ_TX_VMDQ_ONLY);
1232                 }
1233
1234                 /* check valid queue number */
1235                 if ((nb_rx_q > 1) || (nb_tx_q > 1)) {
1236                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1237                                         " only support one queue on VFs.");
1238                         return -EINVAL;
1239                 }
1240         } else {
1241                 /* To no break software that set invalid mode, only display
1242                  * warning if invalid mode is used.
1243                  */
1244                 if (rx_mq_mode != ETH_MQ_RX_NONE &&
1245                     rx_mq_mode != ETH_MQ_RX_VMDQ_ONLY &&
1246                     rx_mq_mode != ETH_MQ_RX_RSS) {
1247                         /* RSS together with VMDq not supported*/
1248                         PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
1249                                      rx_mq_mode);
1250                         return -EINVAL;
1251                 }
1252
1253                 if (tx_mq_mode != ETH_MQ_TX_NONE &&
1254                     tx_mq_mode != ETH_MQ_TX_VMDQ_ONLY) {
1255                         PMD_INIT_LOG(WARNING, "TX mode %d is not supported."
1256                                         " Due to txmode is meaningless in this"
1257                                         " driver, just ignore.",
1258                                         tx_mq_mode);
1259                 }
1260         }
1261         return 0;
1262 }
1263
1264 static int
1265 eth_igb_configure(struct rte_eth_dev *dev)
1266 {
1267         struct e1000_interrupt *intr =
1268                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1269         int ret;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         /* multipe queue mode checking */
1274         ret  = igb_check_mq_mode(dev);
1275         if (ret != 0) {
1276                 PMD_DRV_LOG(ERR, "igb_check_mq_mode fails with %d.",
1277                             ret);
1278                 return ret;
1279         }
1280
1281         intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1282         PMD_INIT_FUNC_TRACE();
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_igb_start(struct rte_eth_dev *dev)
1289 {
1290         struct e1000_hw *hw =
1291                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292         struct e1000_adapter *adapter =
1293                 E1000_DEV_PRIVATE(dev->data->dev_private);
1294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1295         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1296         int ret, mask;
1297         uint32_t intr_vector = 0;
1298         uint32_t ctrl_ext;
1299         uint32_t *speeds;
1300         int num_speeds;
1301         bool autoneg;
1302
1303         PMD_INIT_FUNC_TRACE();
1304
1305         /* disable uio/vfio intr/eventfd mapping */
1306         rte_intr_disable(intr_handle);
1307
1308         /* Power up the phy. Needed to make the link go Up */
1309         eth_igb_dev_set_link_up(dev);
1310
1311         /*
1312          * Packet Buffer Allocation (PBA)
1313          * Writing PBA sets the receive portion of the buffer
1314          * the remainder is used for the transmit buffer.
1315          */
1316         if (hw->mac.type == e1000_82575) {
1317                 uint32_t pba;
1318
1319                 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1320                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1321         }
1322
1323         /* Put the address into the Receive Address Array */
1324         e1000_rar_set(hw, hw->mac.addr, 0);
1325
1326         /* Initialize the hardware */
1327         if (igb_hardware_init(hw)) {
1328                 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
1329                 return -EIO;
1330         }
1331         adapter->stopped = 0;
1332
1333         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1334
1335         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1336         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1337         ctrl_ext |= E1000_CTRL_EXT_PFRSTD;
1338         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1339         E1000_WRITE_FLUSH(hw);
1340
1341         /* configure PF module if SRIOV enabled */
1342         igb_pf_host_configure(dev);
1343
1344         /* check and configure queue intr-vector mapping */
1345         if ((rte_intr_cap_multiple(intr_handle) ||
1346              !RTE_ETH_DEV_SRIOV(dev).active) &&
1347             dev->data->dev_conf.intr_conf.rxq != 0) {
1348                 intr_vector = dev->data->nb_rx_queues;
1349                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1350                         return -1;
1351         }
1352
1353         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1354                 intr_handle->intr_vec =
1355                         rte_zmalloc("intr_vec",
1356                                     dev->data->nb_rx_queues * sizeof(int), 0);
1357                 if (intr_handle->intr_vec == NULL) {
1358                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1359                                      " intr_vec", dev->data->nb_rx_queues);
1360                         return -ENOMEM;
1361                 }
1362         }
1363
1364         /* confiugre msix for rx interrupt */
1365         eth_igb_configure_msix_intr(dev);
1366
1367         /* Configure for OS presence */
1368         igb_init_manageability(hw);
1369
1370         eth_igb_tx_init(dev);
1371
1372         /* This can fail when allocating mbufs for descriptor rings */
1373         ret = eth_igb_rx_init(dev);
1374         if (ret) {
1375                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1376                 igb_dev_clear_queues(dev);
1377                 return ret;
1378         }
1379
1380         e1000_clear_hw_cntrs_base_generic(hw);
1381
1382         /*
1383          * VLAN Offload Settings
1384          */
1385         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1386                         ETH_VLAN_EXTEND_MASK;
1387         eth_igb_vlan_offload_set(dev, mask);
1388
1389         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1390                 /* Enable VLAN filter since VMDq always use VLAN filter */
1391                 igb_vmdq_vlan_hw_filter_enable(dev);
1392         }
1393
1394         if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
1395                 (hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||
1396                 (hw->mac.type == e1000_i211)) {
1397                 /* Configure EITR with the maximum possible value (0xFFFF) */
1398                 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
1399         }
1400
1401         /* Setup link speed and duplex */
1402         speeds = &dev->data->dev_conf.link_speeds;
1403         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
1404                 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
1405                 hw->mac.autoneg = 1;
1406         } else {
1407                 num_speeds = 0;
1408                 autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
1409
1410                 /* Reset */
1411                 hw->phy.autoneg_advertised = 0;
1412
1413                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1414                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1415                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
1416                         num_speeds = -1;
1417                         goto error_invalid_config;
1418                 }
1419                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1420                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1421                         num_speeds++;
1422                 }
1423                 if (*speeds & ETH_LINK_SPEED_10M) {
1424                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1425                         num_speeds++;
1426                 }
1427                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1428                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1429                         num_speeds++;
1430                 }
1431                 if (*speeds & ETH_LINK_SPEED_100M) {
1432                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1433                         num_speeds++;
1434                 }
1435                 if (*speeds & ETH_LINK_SPEED_1G) {
1436                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1437                         num_speeds++;
1438                 }
1439                 if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
1440                         goto error_invalid_config;
1441
1442                 /* Set/reset the mac.autoneg based on the link speed,
1443                  * fixed or not
1444                  */
1445                 if (!autoneg) {
1446                         hw->mac.autoneg = 0;
1447                         hw->mac.forced_speed_duplex =
1448                                         hw->phy.autoneg_advertised;
1449                 } else {
1450                         hw->mac.autoneg = 1;
1451                 }
1452         }
1453
1454         e1000_setup_link(hw);
1455
1456         if (rte_intr_allow_others(intr_handle)) {
1457                 /* check if lsc interrupt is enabled */
1458                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1459                         eth_igb_lsc_interrupt_setup(dev);
1460         } else {
1461                 rte_intr_callback_unregister(intr_handle,
1462                                              eth_igb_interrupt_handler,
1463                                              (void *)dev);
1464                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1465                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1466                                      " no intr multiplex");
1467         }
1468
1469         /* check if rxq interrupt is enabled */
1470         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1471             rte_intr_dp_is_en(intr_handle))
1472                 eth_igb_rxq_interrupt_setup(dev);
1473
1474         /* enable uio/vfio intr/eventfd mapping */
1475         rte_intr_enable(intr_handle);
1476
1477         /* resume enabled intr since hw reset */
1478         igb_intr_enable(dev);
1479
1480         /* restore all types filter */
1481         igb_filter_restore(dev);
1482
1483         PMD_INIT_LOG(DEBUG, "<<");
1484
1485         return 0;
1486
1487 error_invalid_config:
1488         PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1489                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1490         igb_dev_clear_queues(dev);
1491         return -EINVAL;
1492 }
1493
1494 /*********************************************************************
1495  *
1496  *  This routine disables all traffic on the adapter by issuing a
1497  *  global reset on the MAC.
1498  *
1499  **********************************************************************/
1500 static void
1501 eth_igb_stop(struct rte_eth_dev *dev)
1502 {
1503         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1504         struct e1000_filter_info *filter_info =
1505                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1507         struct rte_eth_link link;
1508         struct e1000_flex_filter *p_flex;
1509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1510
1511         igb_intr_disable(hw);
1512
1513         /* disable intr eventfd mapping */
1514         rte_intr_disable(intr_handle);
1515
1516         igb_pf_reset_hw(hw);
1517         E1000_WRITE_REG(hw, E1000_WUC, 0);
1518
1519         /* Set bit for Go Link disconnect */
1520         if (hw->mac.type >= e1000_82580) {
1521                 uint32_t phpm_reg;
1522
1523                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1524                 phpm_reg |= E1000_82580_PM_GO_LINKD;
1525                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1526         }
1527
1528         /* Power down the phy. Needed to make the link go Down */
1529         eth_igb_dev_set_link_down(dev);
1530
1531         igb_dev_clear_queues(dev);
1532
1533         /* clear the recorded link status */
1534         memset(&link, 0, sizeof(link));
1535         rte_igb_dev_atomic_write_link_status(dev, &link);
1536
1537         /* Remove all flex filters of the device */
1538         while ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {
1539                 TAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);
1540                 rte_free(p_flex);
1541         }
1542         filter_info->flex_mask = 0;
1543
1544         if (!rte_intr_allow_others(intr_handle))
1545                 /* resume to the default handler */
1546                 rte_intr_callback_register(intr_handle,
1547                                            eth_igb_interrupt_handler,
1548                                            (void *)dev);
1549
1550         /* Clean datapath event and queue/vec mapping */
1551         rte_intr_efd_disable(intr_handle);
1552         if (intr_handle->intr_vec != NULL) {
1553                 rte_free(intr_handle->intr_vec);
1554                 intr_handle->intr_vec = NULL;
1555         }
1556 }
1557
1558 static int
1559 eth_igb_dev_set_link_up(struct rte_eth_dev *dev)
1560 {
1561         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1562
1563         if (hw->phy.media_type == e1000_media_type_copper)
1564                 e1000_power_up_phy(hw);
1565         else
1566                 e1000_power_up_fiber_serdes_link(hw);
1567
1568         return 0;
1569 }
1570
1571 static int
1572 eth_igb_dev_set_link_down(struct rte_eth_dev *dev)
1573 {
1574         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1575
1576         if (hw->phy.media_type == e1000_media_type_copper)
1577                 e1000_power_down_phy(hw);
1578         else
1579                 e1000_shutdown_fiber_serdes_link(hw);
1580
1581         return 0;
1582 }
1583
1584 static void
1585 eth_igb_close(struct rte_eth_dev *dev)
1586 {
1587         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         struct e1000_adapter *adapter =
1589                 E1000_DEV_PRIVATE(dev->data->dev_private);
1590         struct rte_eth_link link;
1591         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1592         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1593
1594         eth_igb_stop(dev);
1595         adapter->stopped = 1;
1596
1597         e1000_phy_hw_reset(hw);
1598         igb_release_manageability(hw);
1599         igb_hw_control_release(hw);
1600
1601         /* Clear bit for Go Link disconnect */
1602         if (hw->mac.type >= e1000_82580) {
1603                 uint32_t phpm_reg;
1604
1605                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1606                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1607                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1608         }
1609
1610         igb_dev_free_queues(dev);
1611
1612         if (intr_handle->intr_vec) {
1613                 rte_free(intr_handle->intr_vec);
1614                 intr_handle->intr_vec = NULL;
1615         }
1616
1617         memset(&link, 0, sizeof(link));
1618         rte_igb_dev_atomic_write_link_status(dev, &link);
1619 }
1620
1621 static int
1622 igb_get_rx_buffer_size(struct e1000_hw *hw)
1623 {
1624         uint32_t rx_buf_size;
1625         if (hw->mac.type == e1000_82576) {
1626                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
1627         } else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {
1628                 /* PBS needs to be translated according to a lookup table */
1629                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
1630                 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
1631                 rx_buf_size = (rx_buf_size << 10);
1632         } else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
1633                 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;
1634         } else {
1635                 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
1636         }
1637
1638         return rx_buf_size;
1639 }
1640
1641 /*********************************************************************
1642  *
1643  *  Initialize the hardware
1644  *
1645  **********************************************************************/
1646 static int
1647 igb_hardware_init(struct e1000_hw *hw)
1648 {
1649         uint32_t rx_buf_size;
1650         int diag;
1651
1652         /* Let the firmware know the OS is in control */
1653         igb_hw_control_acquire(hw);
1654
1655         /*
1656          * These parameters control the automatic generation (Tx) and
1657          * response (Rx) to Ethernet PAUSE frames.
1658          * - High water mark should allow for at least two standard size (1518)
1659          *   frames to be received after sending an XOFF.
1660          * - Low water mark works best when it is very near the high water mark.
1661          *   This allows the receiver to restart by sending XON when it has
1662          *   drained a bit. Here we use an arbitrary value of 1500 which will
1663          *   restart after one full frame is pulled from the buffer. There
1664          *   could be several smaller frames in the buffer and if so they will
1665          *   not trigger the XON until their total number reduces the buffer
1666          *   by 1500.
1667          * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1668          */
1669         rx_buf_size = igb_get_rx_buffer_size(hw);
1670
1671         hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
1672         hw->fc.low_water = hw->fc.high_water - 1500;
1673         hw->fc.pause_time = IGB_FC_PAUSE_TIME;
1674         hw->fc.send_xon = 1;
1675
1676         /* Set Flow control, use the tunable location if sane */
1677         if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
1678                 hw->fc.requested_mode = igb_fc_setting;
1679         else
1680                 hw->fc.requested_mode = e1000_fc_none;
1681
1682         /* Issue a global reset */
1683         igb_pf_reset_hw(hw);
1684         E1000_WRITE_REG(hw, E1000_WUC, 0);
1685
1686         diag = e1000_init_hw(hw);
1687         if (diag < 0)
1688                 return diag;
1689
1690         E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);
1691         e1000_get_phy_info(hw);
1692         e1000_check_for_link(hw);
1693
1694         return 0;
1695 }
1696
1697 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
1698 static void
1699 igb_read_stats_registers(struct e1000_hw *hw, struct e1000_hw_stats *stats)
1700 {
1701         int pause_frames;
1702
1703         uint64_t old_gprc  = stats->gprc;
1704         uint64_t old_gptc  = stats->gptc;
1705         uint64_t old_tpr   = stats->tpr;
1706         uint64_t old_tpt   = stats->tpt;
1707         uint64_t old_rpthc = stats->rpthc;
1708         uint64_t old_hgptc = stats->hgptc;
1709
1710         if(hw->phy.media_type == e1000_media_type_copper ||
1711             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
1712                 stats->symerrs +=
1713                     E1000_READ_REG(hw,E1000_SYMERRS);
1714                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
1715         }
1716
1717         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
1718         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
1719         stats->scc += E1000_READ_REG(hw, E1000_SCC);
1720         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
1721
1722         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
1723         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
1724         stats->colc += E1000_READ_REG(hw, E1000_COLC);
1725         stats->dc += E1000_READ_REG(hw, E1000_DC);
1726         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
1727         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
1728         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
1729         /*
1730         ** For watchdog management we need to know if we have been
1731         ** paused during the last interval, so capture that here.
1732         */
1733         pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
1734         stats->xoffrxc += pause_frames;
1735         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
1736         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
1737         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
1738         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
1739         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
1740         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
1741         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
1742         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
1743         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
1744         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
1745         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
1746         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
1747
1748         /* For the 64-bit byte counters the low dword must be read first. */
1749         /* Both registers clear on the read of the high dword */
1750
1751         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1752         stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
1753         stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
1754         stats->gorc -= (stats->gprc - old_gprc) * ETHER_CRC_LEN;
1755         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
1756         stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
1757         stats->gotc -= (stats->gptc - old_gptc) * ETHER_CRC_LEN;
1758
1759         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
1760         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
1761         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
1762         stats->roc += E1000_READ_REG(hw, E1000_ROC);
1763         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
1764
1765         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
1766         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
1767
1768         stats->tor += E1000_READ_REG(hw, E1000_TORL);
1769         stats->tor += ((uint64_t)E1000_READ_REG(hw, E1000_TORH) << 32);
1770         stats->tor -= (stats->tpr - old_tpr) * ETHER_CRC_LEN;
1771         stats->tot += E1000_READ_REG(hw, E1000_TOTL);
1772         stats->tot += ((uint64_t)E1000_READ_REG(hw, E1000_TOTH) << 32);
1773         stats->tot -= (stats->tpt - old_tpt) * ETHER_CRC_LEN;
1774
1775         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
1776         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
1777         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
1778         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
1779         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
1780         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
1781         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
1782         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
1783
1784         /* Interrupt Counts */
1785
1786         stats->iac += E1000_READ_REG(hw, E1000_IAC);
1787         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
1788         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
1789         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
1790         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
1791         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
1792         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
1793         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
1794         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
1795
1796         /* Host to Card Statistics */
1797
1798         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
1799         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
1800         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
1801         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
1802         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
1803         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
1804         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
1805         stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
1806         stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
1807         stats->hgorc -= (stats->rpthc - old_rpthc) * ETHER_CRC_LEN;
1808         stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
1809         stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
1810         stats->hgotc -= (stats->hgptc - old_hgptc) * ETHER_CRC_LEN;
1811         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
1812         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
1813         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
1814
1815         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
1816         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
1817         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
1818         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
1819         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
1820         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
1821 }
1822
1823 static void
1824 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1825 {
1826         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct e1000_hw_stats *stats =
1828                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1829
1830         igb_read_stats_registers(hw, stats);
1831
1832         if (rte_stats == NULL)
1833                 return;
1834
1835         /* Rx Errors */
1836         rte_stats->imissed = stats->mpc;
1837         rte_stats->ierrors = stats->crcerrs +
1838                              stats->rlec + stats->ruc + stats->roc +
1839                              stats->rxerrc + stats->algnerrc + stats->cexterr;
1840
1841         /* Tx Errors */
1842         rte_stats->oerrors = stats->ecol + stats->latecol;
1843
1844         rte_stats->ipackets = stats->gprc;
1845         rte_stats->opackets = stats->gptc;
1846         rte_stats->ibytes   = stats->gorc;
1847         rte_stats->obytes   = stats->gotc;
1848 }
1849
1850 static void
1851 eth_igb_stats_reset(struct rte_eth_dev *dev)
1852 {
1853         struct e1000_hw_stats *hw_stats =
1854                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1855
1856         /* HW registers are cleared on read */
1857         eth_igb_stats_get(dev, NULL);
1858
1859         /* Reset software totals */
1860         memset(hw_stats, 0, sizeof(*hw_stats));
1861 }
1862
1863 static void
1864 eth_igb_xstats_reset(struct rte_eth_dev *dev)
1865 {
1866         struct e1000_hw_stats *stats =
1867                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1868
1869         /* HW registers are cleared on read */
1870         eth_igb_xstats_get(dev, NULL, IGB_NB_XSTATS);
1871
1872         /* Reset software totals */
1873         memset(stats, 0, sizeof(*stats));
1874 }
1875
1876 static int eth_igb_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1877         struct rte_eth_xstat_name *xstats_names,
1878         __rte_unused unsigned int size)
1879 {
1880         unsigned i;
1881
1882         if (xstats_names == NULL)
1883                 return IGB_NB_XSTATS;
1884
1885         /* Note: limit checked in rte_eth_xstats_names() */
1886
1887         for (i = 0; i < IGB_NB_XSTATS; i++) {
1888                 snprintf(xstats_names[i].name, sizeof(xstats_names[i].name),
1889                          "%s", rte_igb_stats_strings[i].name);
1890         }
1891
1892         return IGB_NB_XSTATS;
1893 }
1894
1895 static int eth_igb_xstats_get_names_by_id(struct rte_eth_dev *dev,
1896                 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
1897                 unsigned int limit)
1898 {
1899         unsigned int i;
1900
1901         if (!ids) {
1902                 if (xstats_names == NULL)
1903                         return IGB_NB_XSTATS;
1904
1905                 for (i = 0; i < IGB_NB_XSTATS; i++)
1906                         snprintf(xstats_names[i].name,
1907                                         sizeof(xstats_names[i].name),
1908                                         "%s", rte_igb_stats_strings[i].name);
1909
1910                 return IGB_NB_XSTATS;
1911
1912         } else {
1913                 struct rte_eth_xstat_name xstats_names_copy[IGB_NB_XSTATS];
1914
1915                 eth_igb_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
1916                                 IGB_NB_XSTATS);
1917
1918                 for (i = 0; i < limit; i++) {
1919                         if (ids[i] >= IGB_NB_XSTATS) {
1920                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1921                                 return -1;
1922                         }
1923                         strcpy(xstats_names[i].name,
1924                                         xstats_names_copy[ids[i]].name);
1925                 }
1926                 return limit;
1927         }
1928 }
1929
1930 static int
1931 eth_igb_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1932                    unsigned n)
1933 {
1934         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         struct e1000_hw_stats *hw_stats =
1936                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937         unsigned i;
1938
1939         if (n < IGB_NB_XSTATS)
1940                 return IGB_NB_XSTATS;
1941
1942         igb_read_stats_registers(hw, hw_stats);
1943
1944         /* If this is a reset xstats is NULL, and we have cleared the
1945          * registers by reading them.
1946          */
1947         if (!xstats)
1948                 return 0;
1949
1950         /* Extended stats */
1951         for (i = 0; i < IGB_NB_XSTATS; i++) {
1952                 xstats[i].id = i;
1953                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1954                         rte_igb_stats_strings[i].offset);
1955         }
1956
1957         return IGB_NB_XSTATS;
1958 }
1959
1960 static int
1961 eth_igb_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1962                 uint64_t *values, unsigned int n)
1963 {
1964         unsigned int i;
1965
1966         if (!ids) {
1967                 struct e1000_hw *hw =
1968                         E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969                 struct e1000_hw_stats *hw_stats =
1970                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1971
1972                 if (n < IGB_NB_XSTATS)
1973                         return IGB_NB_XSTATS;
1974
1975                 igb_read_stats_registers(hw, hw_stats);
1976
1977                 /* If this is a reset xstats is NULL, and we have cleared the
1978                  * registers by reading them.
1979                  */
1980                 if (!values)
1981                         return 0;
1982
1983                 /* Extended stats */
1984                 for (i = 0; i < IGB_NB_XSTATS; i++)
1985                         values[i] = *(uint64_t *)(((char *)hw_stats) +
1986                                         rte_igb_stats_strings[i].offset);
1987
1988                 return IGB_NB_XSTATS;
1989
1990         } else {
1991                 uint64_t values_copy[IGB_NB_XSTATS];
1992
1993                 eth_igb_xstats_get_by_id(dev, NULL, values_copy,
1994                                 IGB_NB_XSTATS);
1995
1996                 for (i = 0; i < n; i++) {
1997                         if (ids[i] >= IGB_NB_XSTATS) {
1998                                 PMD_INIT_LOG(ERR, "id value isn't valid");
1999                                 return -1;
2000                         }
2001                         values[i] = values_copy[ids[i]];
2002                 }
2003                 return n;
2004         }
2005 }
2006
2007 static void
2008 igbvf_read_stats_registers(struct e1000_hw *hw, struct e1000_vf_stats *hw_stats)
2009 {
2010         /* Good Rx packets, include VF loopback */
2011         UPDATE_VF_STAT(E1000_VFGPRC,
2012             hw_stats->last_gprc, hw_stats->gprc);
2013
2014         /* Good Rx octets, include VF loopback */
2015         UPDATE_VF_STAT(E1000_VFGORC,
2016             hw_stats->last_gorc, hw_stats->gorc);
2017
2018         /* Good Tx packets, include VF loopback */
2019         UPDATE_VF_STAT(E1000_VFGPTC,
2020             hw_stats->last_gptc, hw_stats->gptc);
2021
2022         /* Good Tx octets, include VF loopback */
2023         UPDATE_VF_STAT(E1000_VFGOTC,
2024             hw_stats->last_gotc, hw_stats->gotc);
2025
2026         /* Rx Multicst packets */
2027         UPDATE_VF_STAT(E1000_VFMPRC,
2028             hw_stats->last_mprc, hw_stats->mprc);
2029
2030         /* Good Rx loopback packets */
2031         UPDATE_VF_STAT(E1000_VFGPRLBC,
2032             hw_stats->last_gprlbc, hw_stats->gprlbc);
2033
2034         /* Good Rx loopback octets */
2035         UPDATE_VF_STAT(E1000_VFGORLBC,
2036             hw_stats->last_gorlbc, hw_stats->gorlbc);
2037
2038         /* Good Tx loopback packets */
2039         UPDATE_VF_STAT(E1000_VFGPTLBC,
2040             hw_stats->last_gptlbc, hw_stats->gptlbc);
2041
2042         /* Good Tx loopback octets */
2043         UPDATE_VF_STAT(E1000_VFGOTLBC,
2044             hw_stats->last_gotlbc, hw_stats->gotlbc);
2045 }
2046
2047 static int eth_igbvf_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2048                                      struct rte_eth_xstat_name *xstats_names,
2049                                      __rte_unused unsigned limit)
2050 {
2051         unsigned i;
2052
2053         if (xstats_names != NULL)
2054                 for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2055                         snprintf(xstats_names[i].name,
2056                                 sizeof(xstats_names[i].name), "%s",
2057                                 rte_igbvf_stats_strings[i].name);
2058                 }
2059         return IGBVF_NB_XSTATS;
2060 }
2061
2062 static int
2063 eth_igbvf_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2064                      unsigned n)
2065 {
2066         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2068                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2069         unsigned i;
2070
2071         if (n < IGBVF_NB_XSTATS)
2072                 return IGBVF_NB_XSTATS;
2073
2074         igbvf_read_stats_registers(hw, hw_stats);
2075
2076         if (!xstats)
2077                 return 0;
2078
2079         for (i = 0; i < IGBVF_NB_XSTATS; i++) {
2080                 xstats[i].id = i;
2081                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2082                         rte_igbvf_stats_strings[i].offset);
2083         }
2084
2085         return IGBVF_NB_XSTATS;
2086 }
2087
2088 static void
2089 eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
2090 {
2091         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats *)
2093                           E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2094
2095         igbvf_read_stats_registers(hw, hw_stats);
2096
2097         if (rte_stats == NULL)
2098                 return;
2099
2100         rte_stats->ipackets = hw_stats->gprc;
2101         rte_stats->ibytes = hw_stats->gorc;
2102         rte_stats->opackets = hw_stats->gptc;
2103         rte_stats->obytes = hw_stats->gotc;
2104 }
2105
2106 static void
2107 eth_igbvf_stats_reset(struct rte_eth_dev *dev)
2108 {
2109         struct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)
2110                         E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2111
2112         /* Sync HW register to the last stats */
2113         eth_igbvf_stats_get(dev, NULL);
2114
2115         /* reset HW current stats*/
2116         memset(&hw_stats->gprc, 0, sizeof(*hw_stats) -
2117                offsetof(struct e1000_vf_stats, gprc));
2118 }
2119
2120 static int
2121 eth_igb_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
2122                        size_t fw_size)
2123 {
2124         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct e1000_fw_version fw;
2126         int ret;
2127
2128         e1000_get_fw_version(hw, &fw);
2129
2130         switch (hw->mac.type) {
2131         case e1000_i210:
2132         case e1000_i211:
2133                 if (!(e1000_get_flash_presence_i210(hw))) {
2134                         ret = snprintf(fw_version, fw_size,
2135                                  "%2d.%2d-%d",
2136                                  fw.invm_major, fw.invm_minor,
2137                                  fw.invm_img_type);
2138                         break;
2139                 }
2140                 /* fall through */
2141         default:
2142                 /* if option rom is valid, display its version too */
2143                 if (fw.or_valid) {
2144                         ret = snprintf(fw_version, fw_size,
2145                                  "%d.%d, 0x%08x, %d.%d.%d",
2146                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2147                                  fw.or_major, fw.or_build, fw.or_patch);
2148                 /* no option rom */
2149                 } else {
2150                         if (fw.etrack_id != 0X0000) {
2151                                 ret = snprintf(fw_version, fw_size,
2152                                          "%d.%d, 0x%08x",
2153                                          fw.eep_major, fw.eep_minor,
2154                                          fw.etrack_id);
2155                         } else {
2156                                 ret = snprintf(fw_version, fw_size,
2157                                          "%d.%d.%d",
2158                                          fw.eep_major, fw.eep_minor,
2159                                          fw.eep_build);
2160                         }
2161                 }
2162                 break;
2163         }
2164
2165         ret += 1; /* add the size of '\0' */
2166         if (fw_size < (u32)ret)
2167                 return ret;
2168         else
2169                 return 0;
2170 }
2171
2172 static void
2173 eth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2174 {
2175         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176
2177         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2179         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2180         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2181         dev_info->rx_offload_capa =
2182                 DEV_RX_OFFLOAD_VLAN_STRIP |
2183                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2184                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2185                 DEV_RX_OFFLOAD_TCP_CKSUM;
2186         dev_info->tx_offload_capa =
2187                 DEV_TX_OFFLOAD_VLAN_INSERT |
2188                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2189                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2190                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2191                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2192                 DEV_TX_OFFLOAD_TCP_TSO;
2193
2194         switch (hw->mac.type) {
2195         case e1000_82575:
2196                 dev_info->max_rx_queues = 4;
2197                 dev_info->max_tx_queues = 4;
2198                 dev_info->max_vmdq_pools = 0;
2199                 break;
2200
2201         case e1000_82576:
2202                 dev_info->max_rx_queues = 16;
2203                 dev_info->max_tx_queues = 16;
2204                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2205                 dev_info->vmdq_queue_num = 16;
2206                 break;
2207
2208         case e1000_82580:
2209                 dev_info->max_rx_queues = 8;
2210                 dev_info->max_tx_queues = 8;
2211                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2212                 dev_info->vmdq_queue_num = 8;
2213                 break;
2214
2215         case e1000_i350:
2216                 dev_info->max_rx_queues = 8;
2217                 dev_info->max_tx_queues = 8;
2218                 dev_info->max_vmdq_pools = ETH_8_POOLS;
2219                 dev_info->vmdq_queue_num = 8;
2220                 break;
2221
2222         case e1000_i354:
2223                 dev_info->max_rx_queues = 8;
2224                 dev_info->max_tx_queues = 8;
2225                 break;
2226
2227         case e1000_i210:
2228                 dev_info->max_rx_queues = 4;
2229                 dev_info->max_tx_queues = 4;
2230                 dev_info->max_vmdq_pools = 0;
2231                 break;
2232
2233         case e1000_i211:
2234                 dev_info->max_rx_queues = 2;
2235                 dev_info->max_tx_queues = 2;
2236                 dev_info->max_vmdq_pools = 0;
2237                 break;
2238
2239         default:
2240                 /* Should not happen */
2241                 break;
2242         }
2243         dev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);
2244         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2245         dev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;
2246
2247         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2248                 .rx_thresh = {
2249                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2250                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2251                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2252                 },
2253                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2254                 .rx_drop_en = 0,
2255         };
2256
2257         dev_info->default_txconf = (struct rte_eth_txconf) {
2258                 .tx_thresh = {
2259                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2260                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2261                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2262                 },
2263                 .txq_flags = 0,
2264         };
2265
2266         dev_info->rx_desc_lim = rx_desc_lim;
2267         dev_info->tx_desc_lim = tx_desc_lim;
2268
2269         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
2270                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
2271                         ETH_LINK_SPEED_1G;
2272 }
2273
2274 static const uint32_t *
2275 eth_igb_supported_ptypes_get(struct rte_eth_dev *dev)
2276 {
2277         static const uint32_t ptypes[] = {
2278                 /* refers to igb_rxd_pkt_info_to_pkt_type() */
2279                 RTE_PTYPE_L2_ETHER,
2280                 RTE_PTYPE_L3_IPV4,
2281                 RTE_PTYPE_L3_IPV4_EXT,
2282                 RTE_PTYPE_L3_IPV6,
2283                 RTE_PTYPE_L3_IPV6_EXT,
2284                 RTE_PTYPE_L4_TCP,
2285                 RTE_PTYPE_L4_UDP,
2286                 RTE_PTYPE_L4_SCTP,
2287                 RTE_PTYPE_TUNNEL_IP,
2288                 RTE_PTYPE_INNER_L3_IPV6,
2289                 RTE_PTYPE_INNER_L3_IPV6_EXT,
2290                 RTE_PTYPE_INNER_L4_TCP,
2291                 RTE_PTYPE_INNER_L4_UDP,
2292                 RTE_PTYPE_UNKNOWN
2293         };
2294
2295         if (dev->rx_pkt_burst == eth_igb_recv_pkts ||
2296             dev->rx_pkt_burst == eth_igb_recv_scattered_pkts)
2297                 return ptypes;
2298         return NULL;
2299 }
2300
2301 static void
2302 eth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2303 {
2304         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2305
2306         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2307         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
2308         dev_info->max_rx_pktlen  = 0x3FFF; /* See RLPML register. */
2309         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
2310         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2311                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2312                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2313                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2314         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2315                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2316                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2317                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2318                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2319                                 DEV_TX_OFFLOAD_TCP_TSO;
2320         switch (hw->mac.type) {
2321         case e1000_vfadapt:
2322                 dev_info->max_rx_queues = 2;
2323                 dev_info->max_tx_queues = 2;
2324                 break;
2325         case e1000_vfadapt_i350:
2326                 dev_info->max_rx_queues = 1;
2327                 dev_info->max_tx_queues = 1;
2328                 break;
2329         default:
2330                 /* Should not happen */
2331                 break;
2332         }
2333
2334         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2335                 .rx_thresh = {
2336                         .pthresh = IGB_DEFAULT_RX_PTHRESH,
2337                         .hthresh = IGB_DEFAULT_RX_HTHRESH,
2338                         .wthresh = IGB_DEFAULT_RX_WTHRESH,
2339                 },
2340                 .rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,
2341                 .rx_drop_en = 0,
2342         };
2343
2344         dev_info->default_txconf = (struct rte_eth_txconf) {
2345                 .tx_thresh = {
2346                         .pthresh = IGB_DEFAULT_TX_PTHRESH,
2347                         .hthresh = IGB_DEFAULT_TX_HTHRESH,
2348                         .wthresh = IGB_DEFAULT_TX_WTHRESH,
2349                 },
2350                 .txq_flags = 0,
2351         };
2352
2353         dev_info->rx_desc_lim = rx_desc_lim;
2354         dev_info->tx_desc_lim = tx_desc_lim;
2355 }
2356
2357 /* return 0 means link status changed, -1 means not changed */
2358 static int
2359 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2360 {
2361         struct e1000_hw *hw =
2362                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct rte_eth_link link, old;
2364         int link_check, count;
2365
2366         link_check = 0;
2367         hw->mac.get_link_status = 1;
2368
2369         /* possible wait-to-complete in up to 9 seconds */
2370         for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
2371                 /* Read the real link status */
2372                 switch (hw->phy.media_type) {
2373                 case e1000_media_type_copper:
2374                         /* Do the work to read phy */
2375                         e1000_check_for_link(hw);
2376                         link_check = !hw->mac.get_link_status;
2377                         break;
2378
2379                 case e1000_media_type_fiber:
2380                         e1000_check_for_link(hw);
2381                         link_check = (E1000_READ_REG(hw, E1000_STATUS) &
2382                                       E1000_STATUS_LU);
2383                         break;
2384
2385                 case e1000_media_type_internal_serdes:
2386                         e1000_check_for_link(hw);
2387                         link_check = hw->mac.serdes_has_link;
2388                         break;
2389
2390                 /* VF device is type_unknown */
2391                 case e1000_media_type_unknown:
2392                         eth_igbvf_link_update(hw);
2393                         link_check = !hw->mac.get_link_status;
2394                         break;
2395
2396                 default:
2397                         break;
2398                 }
2399                 if (link_check || wait_to_complete == 0)
2400                         break;
2401                 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
2402         }
2403         memset(&link, 0, sizeof(link));
2404         rte_igb_dev_atomic_read_link_status(dev, &link);
2405         old = link;
2406
2407         /* Now we check if a transition has happened */
2408         if (link_check) {
2409                 uint16_t duplex, speed;
2410                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
2411                 link.link_duplex = (duplex == FULL_DUPLEX) ?
2412                                 ETH_LINK_FULL_DUPLEX :
2413                                 ETH_LINK_HALF_DUPLEX;
2414                 link.link_speed = speed;
2415                 link.link_status = ETH_LINK_UP;
2416                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2417                                 ETH_LINK_SPEED_FIXED);
2418         } else if (!link_check) {
2419                 link.link_speed = 0;
2420                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2421                 link.link_status = ETH_LINK_DOWN;
2422                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
2423         }
2424         rte_igb_dev_atomic_write_link_status(dev, &link);
2425
2426         /* not changed */
2427         if (old.link_status == link.link_status)
2428                 return -1;
2429
2430         /* changed */
2431         return 0;
2432 }
2433
2434 /*
2435  * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
2436  * For ASF and Pass Through versions of f/w this means
2437  * that the driver is loaded.
2438  */
2439 static void
2440 igb_hw_control_acquire(struct e1000_hw *hw)
2441 {
2442         uint32_t ctrl_ext;
2443
2444         /* Let firmware know the driver has taken over */
2445         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2446         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2447 }
2448
2449 /*
2450  * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
2451  * For ASF and Pass Through versions of f/w this means that the
2452  * driver is no longer loaded.
2453  */
2454 static void
2455 igb_hw_control_release(struct e1000_hw *hw)
2456 {
2457         uint32_t ctrl_ext;
2458
2459         /* Let firmware taken over control of h/w */
2460         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2461         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
2462                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2463 }
2464
2465 /*
2466  * Bit of a misnomer, what this really means is
2467  * to enable OS management of the system... aka
2468  * to disable special hardware management features.
2469  */
2470 static void
2471 igb_init_manageability(struct e1000_hw *hw)
2472 {
2473         if (e1000_enable_mng_pass_thru(hw)) {
2474                 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
2475                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2476
2477                 /* disable hardware interception of ARP */
2478                 manc &= ~(E1000_MANC_ARP_EN);
2479
2480                 /* enable receiving management packets to the host */
2481                 manc |= E1000_MANC_EN_MNG2HOST;
2482                 manc2h |= 1 << 5;  /* Mng Port 623 */
2483                 manc2h |= 1 << 6;  /* Mng Port 664 */
2484                 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
2485                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2486         }
2487 }
2488
2489 static void
2490 igb_release_manageability(struct e1000_hw *hw)
2491 {
2492         if (e1000_enable_mng_pass_thru(hw)) {
2493                 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
2494
2495                 manc |= E1000_MANC_ARP_EN;
2496                 manc &= ~E1000_MANC_EN_MNG2HOST;
2497
2498                 E1000_WRITE_REG(hw, E1000_MANC, manc);
2499         }
2500 }
2501
2502 static void
2503 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
2504 {
2505         struct e1000_hw *hw =
2506                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2507         uint32_t rctl;
2508
2509         rctl = E1000_READ_REG(hw, E1000_RCTL);
2510         rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2511         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2512 }
2513
2514 static void
2515 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
2516 {
2517         struct e1000_hw *hw =
2518                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2519         uint32_t rctl;
2520
2521         rctl = E1000_READ_REG(hw, E1000_RCTL);
2522         rctl &= (~E1000_RCTL_UPE);
2523         if (dev->data->all_multicast == 1)
2524                 rctl |= E1000_RCTL_MPE;
2525         else
2526                 rctl &= (~E1000_RCTL_MPE);
2527         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2528 }
2529
2530 static void
2531 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
2532 {
2533         struct e1000_hw *hw =
2534                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535         uint32_t rctl;
2536
2537         rctl = E1000_READ_REG(hw, E1000_RCTL);
2538         rctl |= E1000_RCTL_MPE;
2539         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2540 }
2541
2542 static void
2543 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
2544 {
2545         struct e1000_hw *hw =
2546                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2547         uint32_t rctl;
2548
2549         if (dev->data->promiscuous == 1)
2550                 return; /* must remain in all_multicast mode */
2551         rctl = E1000_READ_REG(hw, E1000_RCTL);
2552         rctl &= (~E1000_RCTL_MPE);
2553         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2554 }
2555
2556 static int
2557 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2558 {
2559         struct e1000_hw *hw =
2560                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2561         struct e1000_vfta * shadow_vfta =
2562                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2563         uint32_t vfta;
2564         uint32_t vid_idx;
2565         uint32_t vid_bit;
2566
2567         vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
2568                               E1000_VFTA_ENTRY_MASK);
2569         vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
2570         vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
2571         if (on)
2572                 vfta |= vid_bit;
2573         else
2574                 vfta &= ~vid_bit;
2575         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
2576
2577         /* update local VFTA copy */
2578         shadow_vfta->vfta[vid_idx] = vfta;
2579
2580         return 0;
2581 }
2582
2583 static int
2584 eth_igb_vlan_tpid_set(struct rte_eth_dev *dev,
2585                       enum rte_vlan_type vlan_type,
2586                       uint16_t tpid)
2587 {
2588         struct e1000_hw *hw =
2589                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590         uint32_t reg, qinq;
2591
2592         qinq = E1000_READ_REG(hw, E1000_CTRL_EXT);
2593         qinq &= E1000_CTRL_EXT_EXT_VLAN;
2594
2595         /* only outer TPID of double VLAN can be configured*/
2596         if (qinq && vlan_type == ETH_VLAN_TYPE_OUTER) {
2597                 reg = E1000_READ_REG(hw, E1000_VET);
2598                 reg = (reg & (~E1000_VET_VET_EXT)) |
2599                         ((uint32_t)tpid << E1000_VET_VET_EXT_SHIFT);
2600                 E1000_WRITE_REG(hw, E1000_VET, reg);
2601
2602                 return 0;
2603         }
2604
2605         /* all other TPID values are read-only*/
2606         PMD_DRV_LOG(ERR, "Not supported");
2607
2608         return -ENOTSUP;
2609 }
2610
2611 static void
2612 igb_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2613 {
2614         struct e1000_hw *hw =
2615                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         uint32_t reg;
2617
2618         /* Filter Table Disable */
2619         reg = E1000_READ_REG(hw, E1000_RCTL);
2620         reg &= ~E1000_RCTL_CFIEN;
2621         reg &= ~E1000_RCTL_VFE;
2622         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2623 }
2624
2625 static void
2626 igb_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2627 {
2628         struct e1000_hw *hw =
2629                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630         struct e1000_vfta * shadow_vfta =
2631                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2632         uint32_t reg;
2633         int i;
2634
2635         /* Filter Table Enable, CFI not used for packet acceptance */
2636         reg = E1000_READ_REG(hw, E1000_RCTL);
2637         reg &= ~E1000_RCTL_CFIEN;
2638         reg |= E1000_RCTL_VFE;
2639         E1000_WRITE_REG(hw, E1000_RCTL, reg);
2640
2641         /* restore VFTA table */
2642         for (i = 0; i < IGB_VFTA_SIZE; i++)
2643                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
2644 }
2645
2646 static void
2647 igb_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2648 {
2649         struct e1000_hw *hw =
2650                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651         uint32_t reg;
2652
2653         /* VLAN Mode Disable */
2654         reg = E1000_READ_REG(hw, E1000_CTRL);
2655         reg &= ~E1000_CTRL_VME;
2656         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2657 }
2658
2659 static void
2660 igb_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2661 {
2662         struct e1000_hw *hw =
2663                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2664         uint32_t reg;
2665
2666         /* VLAN Mode Enable */
2667         reg = E1000_READ_REG(hw, E1000_CTRL);
2668         reg |= E1000_CTRL_VME;
2669         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2670 }
2671
2672 static void
2673 igb_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2674 {
2675         struct e1000_hw *hw =
2676                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677         uint32_t reg;
2678
2679         /* CTRL_EXT: Extended VLAN */
2680         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2681         reg &= ~E1000_CTRL_EXT_EXTEND_VLAN;
2682         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2683
2684         /* Update maximum packet length */
2685         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2686                 E1000_WRITE_REG(hw, E1000_RLPML,
2687                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2688                                                 VLAN_TAG_SIZE);
2689 }
2690
2691 static void
2692 igb_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2693 {
2694         struct e1000_hw *hw =
2695                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2696         uint32_t reg;
2697
2698         /* CTRL_EXT: Extended VLAN */
2699         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2700         reg |= E1000_CTRL_EXT_EXTEND_VLAN;
2701         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2702
2703         /* Update maximum packet length */
2704         if (dev->data->dev_conf.rxmode.jumbo_frame == 1)
2705                 E1000_WRITE_REG(hw, E1000_RLPML,
2706                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2707                                                 2 * VLAN_TAG_SIZE);
2708 }
2709
2710 static void
2711 eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2712 {
2713         if(mask & ETH_VLAN_STRIP_MASK){
2714                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2715                         igb_vlan_hw_strip_enable(dev);
2716                 else
2717                         igb_vlan_hw_strip_disable(dev);
2718         }
2719
2720         if(mask & ETH_VLAN_FILTER_MASK){
2721                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2722                         igb_vlan_hw_filter_enable(dev);
2723                 else
2724                         igb_vlan_hw_filter_disable(dev);
2725         }
2726
2727         if(mask & ETH_VLAN_EXTEND_MASK){
2728                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2729                         igb_vlan_hw_extend_enable(dev);
2730                 else
2731                         igb_vlan_hw_extend_disable(dev);
2732         }
2733 }
2734
2735
2736 /**
2737  * It enables the interrupt mask and then enable the interrupt.
2738  *
2739  * @param dev
2740  *  Pointer to struct rte_eth_dev.
2741  *
2742  * @return
2743  *  - On success, zero.
2744  *  - On failure, a negative value.
2745  */
2746 static int
2747 eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)
2748 {
2749         struct e1000_interrupt *intr =
2750                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2751
2752         intr->mask |= E1000_ICR_LSC;
2753
2754         return 0;
2755 }
2756
2757 /* It clears the interrupt causes and enables the interrupt.
2758  * It will be called once only during nic initialized.
2759  *
2760  * @param dev
2761  *  Pointer to struct rte_eth_dev.
2762  *
2763  * @return
2764  *  - On success, zero.
2765  *  - On failure, a negative value.
2766  */
2767 static int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)
2768 {
2769         uint32_t mask, regval;
2770         struct e1000_hw *hw =
2771                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2772         struct rte_eth_dev_info dev_info;
2773
2774         memset(&dev_info, 0, sizeof(dev_info));
2775         eth_igb_infos_get(dev, &dev_info);
2776
2777         mask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);
2778         regval = E1000_READ_REG(hw, E1000_EIMS);
2779         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
2780
2781         return 0;
2782 }
2783
2784 /*
2785  * It reads ICR and gets interrupt causes, check it and set a bit flag
2786  * to update link status.
2787  *
2788  * @param dev
2789  *  Pointer to struct rte_eth_dev.
2790  *
2791  * @return
2792  *  - On success, zero.
2793  *  - On failure, a negative value.
2794  */
2795 static int
2796 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
2797 {
2798         uint32_t icr;
2799         struct e1000_hw *hw =
2800                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2801         struct e1000_interrupt *intr =
2802                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2803
2804         igb_intr_disable(hw);
2805
2806         /* read-on-clear nic registers here */
2807         icr = E1000_READ_REG(hw, E1000_ICR);
2808
2809         intr->flags = 0;
2810         if (icr & E1000_ICR_LSC) {
2811                 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
2812         }
2813
2814         if (icr & E1000_ICR_VMMB)
2815                 intr->flags |= E1000_FLAG_MAILBOX;
2816
2817         return 0;
2818 }
2819
2820 /*
2821  * It executes link_update after knowing an interrupt is prsent.
2822  *
2823  * @param dev
2824  *  Pointer to struct rte_eth_dev.
2825  *
2826  * @return
2827  *  - On success, zero.
2828  *  - On failure, a negative value.
2829  */
2830 static int
2831 eth_igb_interrupt_action(struct rte_eth_dev *dev,
2832                          struct rte_intr_handle *intr_handle)
2833 {
2834         struct e1000_hw *hw =
2835                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836         struct e1000_interrupt *intr =
2837                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2838         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2839         uint32_t tctl, rctl;
2840         struct rte_eth_link link;
2841         int ret;
2842
2843         if (intr->flags & E1000_FLAG_MAILBOX) {
2844                 igb_pf_mbx_process(dev);
2845                 intr->flags &= ~E1000_FLAG_MAILBOX;
2846         }
2847
2848         igb_intr_enable(dev);
2849         rte_intr_enable(intr_handle);
2850
2851         if (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {
2852                 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
2853
2854                 /* set get_link_status to check register later */
2855                 hw->mac.get_link_status = 1;
2856                 ret = eth_igb_link_update(dev, 0);
2857
2858                 /* check if link has changed */
2859                 if (ret < 0)
2860                         return 0;
2861
2862                 memset(&link, 0, sizeof(link));
2863                 rte_igb_dev_atomic_read_link_status(dev, &link);
2864                 if (link.link_status) {
2865                         PMD_INIT_LOG(INFO,
2866                                      " Port %d: Link Up - speed %u Mbps - %s",
2867                                      dev->data->port_id,
2868                                      (unsigned)link.link_speed,
2869                                      link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2870                                      "full-duplex" : "half-duplex");
2871                 } else {
2872                         PMD_INIT_LOG(INFO, " Port %d: Link Down",
2873                                      dev->data->port_id);
2874                 }
2875
2876                 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2877                              pci_dev->addr.domain,
2878                              pci_dev->addr.bus,
2879                              pci_dev->addr.devid,
2880                              pci_dev->addr.function);
2881                 tctl = E1000_READ_REG(hw, E1000_TCTL);
2882                 rctl = E1000_READ_REG(hw, E1000_RCTL);
2883                 if (link.link_status) {
2884                         /* enable Tx/Rx */
2885                         tctl |= E1000_TCTL_EN;
2886                         rctl |= E1000_RCTL_EN;
2887                 } else {
2888                         /* disable Tx/Rx */
2889                         tctl &= ~E1000_TCTL_EN;
2890                         rctl &= ~E1000_RCTL_EN;
2891                 }
2892                 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2893                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2894                 E1000_WRITE_FLUSH(hw);
2895                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2896         }
2897
2898         return 0;
2899 }
2900
2901 /**
2902  * Interrupt handler which shall be registered at first.
2903  *
2904  * @param handle
2905  *  Pointer to interrupt handle.
2906  * @param param
2907  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2908  *
2909  * @return
2910  *  void
2911  */
2912 static void
2913 eth_igb_interrupt_handler(void *param)
2914 {
2915         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2916
2917         eth_igb_interrupt_get_status(dev);
2918         eth_igb_interrupt_action(dev, dev->intr_handle);
2919 }
2920
2921 static int
2922 eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
2923 {
2924         uint32_t eicr;
2925         struct e1000_hw *hw =
2926                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927         struct e1000_interrupt *intr =
2928                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2929
2930         igbvf_intr_disable(hw);
2931
2932         /* read-on-clear nic registers here */
2933         eicr = E1000_READ_REG(hw, E1000_EICR);
2934         intr->flags = 0;
2935
2936         if (eicr == E1000_VTIVAR_MISC_MAILBOX)
2937                 intr->flags |= E1000_FLAG_MAILBOX;
2938
2939         return 0;
2940 }
2941
2942 void igbvf_mbx_process(struct rte_eth_dev *dev)
2943 {
2944         struct e1000_hw *hw =
2945                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2946         struct e1000_mbx_info *mbx = &hw->mbx;
2947         u32 in_msg = 0;
2948
2949         if (mbx->ops.read(hw, &in_msg, 1, 0))
2950                 return;
2951
2952         /* PF reset VF event */
2953         if (in_msg == E1000_PF_CONTROL_MSG)
2954                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
2955 }
2956
2957 static int
2958 eth_igbvf_interrupt_action(struct rte_eth_dev *dev, struct rte_intr_handle *intr_handle)
2959 {
2960         struct e1000_interrupt *intr =
2961                 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2962
2963         if (intr->flags & E1000_FLAG_MAILBOX) {
2964                 igbvf_mbx_process(dev);
2965                 intr->flags &= ~E1000_FLAG_MAILBOX;
2966         }
2967
2968         igbvf_intr_enable(dev);
2969         rte_intr_enable(intr_handle);
2970
2971         return 0;
2972 }
2973
2974 static void
2975 eth_igbvf_interrupt_handler(void *param)
2976 {
2977         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2978
2979         eth_igbvf_interrupt_get_status(dev);
2980         eth_igbvf_interrupt_action(dev, dev->intr_handle);
2981 }
2982
2983 static int
2984 eth_igb_led_on(struct rte_eth_dev *dev)
2985 {
2986         struct e1000_hw *hw;
2987
2988         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2989         return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2990 }
2991
2992 static int
2993 eth_igb_led_off(struct rte_eth_dev *dev)
2994 {
2995         struct e1000_hw *hw;
2996
2997         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2998         return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
2999 }
3000
3001 static int
3002 eth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3003 {
3004         struct e1000_hw *hw;
3005         uint32_t ctrl;
3006         int tx_pause;
3007         int rx_pause;
3008
3009         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010         fc_conf->pause_time = hw->fc.pause_time;
3011         fc_conf->high_water = hw->fc.high_water;
3012         fc_conf->low_water = hw->fc.low_water;
3013         fc_conf->send_xon = hw->fc.send_xon;
3014         fc_conf->autoneg = hw->mac.autoneg;
3015
3016         /*
3017          * Return rx_pause and tx_pause status according to actual setting of
3018          * the TFCE and RFCE bits in the CTRL register.
3019          */
3020         ctrl = E1000_READ_REG(hw, E1000_CTRL);
3021         if (ctrl & E1000_CTRL_TFCE)
3022                 tx_pause = 1;
3023         else
3024                 tx_pause = 0;
3025
3026         if (ctrl & E1000_CTRL_RFCE)
3027                 rx_pause = 1;
3028         else
3029                 rx_pause = 0;
3030
3031         if (rx_pause && tx_pause)
3032                 fc_conf->mode = RTE_FC_FULL;
3033         else if (rx_pause)
3034                 fc_conf->mode = RTE_FC_RX_PAUSE;
3035         else if (tx_pause)
3036                 fc_conf->mode = RTE_FC_TX_PAUSE;
3037         else
3038                 fc_conf->mode = RTE_FC_NONE;
3039
3040         return 0;
3041 }
3042
3043 static int
3044 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3045 {
3046         struct e1000_hw *hw;
3047         int err;
3048         enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
3049                 e1000_fc_none,
3050                 e1000_fc_rx_pause,
3051                 e1000_fc_tx_pause,
3052                 e1000_fc_full
3053         };
3054         uint32_t rx_buf_size;
3055         uint32_t max_high_water;
3056         uint32_t rctl;
3057
3058         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059         if (fc_conf->autoneg != hw->mac.autoneg)
3060                 return -ENOTSUP;
3061         rx_buf_size = igb_get_rx_buffer_size(hw);
3062         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3063
3064         /* At least reserve one Ethernet frame for watermark */
3065         max_high_water = rx_buf_size - ETHER_MAX_LEN;
3066         if ((fc_conf->high_water > max_high_water) ||
3067             (fc_conf->high_water < fc_conf->low_water)) {
3068                 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
3069                 PMD_INIT_LOG(ERR, "high water must <=  0x%x", max_high_water);
3070                 return -EINVAL;
3071         }
3072
3073         hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
3074         hw->fc.pause_time     = fc_conf->pause_time;
3075         hw->fc.high_water     = fc_conf->high_water;
3076         hw->fc.low_water      = fc_conf->low_water;
3077         hw->fc.send_xon       = fc_conf->send_xon;
3078
3079         err = e1000_setup_link_generic(hw);
3080         if (err == E1000_SUCCESS) {
3081
3082                 /* check if we want to forward MAC frames - driver doesn't have native
3083                  * capability to do that, so we'll write the registers ourselves */
3084
3085                 rctl = E1000_READ_REG(hw, E1000_RCTL);
3086
3087                 /* set or clear MFLCN.PMCF bit depending on configuration */
3088                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3089                         rctl |= E1000_RCTL_PMCF;
3090                 else
3091                         rctl &= ~E1000_RCTL_PMCF;
3092
3093                 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
3094                 E1000_WRITE_FLUSH(hw);
3095
3096                 return 0;
3097         }
3098
3099         PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
3100         return -EIO;
3101 }
3102
3103 #define E1000_RAH_POOLSEL_SHIFT      (18)
3104 static int
3105 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3106                 uint32_t index, uint32_t pool)
3107 {
3108         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109         uint32_t rah;
3110
3111         e1000_rar_set(hw, mac_addr->addr_bytes, index);
3112         rah = E1000_READ_REG(hw, E1000_RAH(index));
3113         rah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));
3114         E1000_WRITE_REG(hw, E1000_RAH(index), rah);
3115         return 0;
3116 }
3117
3118 static void
3119 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
3120 {
3121         uint8_t addr[ETHER_ADDR_LEN];
3122         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123
3124         memset(addr, 0, sizeof(addr));
3125
3126         e1000_rar_set(hw, addr, index);
3127 }
3128
3129 static void
3130 eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,
3131                                 struct ether_addr *addr)
3132 {
3133         eth_igb_rar_clear(dev, 0);
3134
3135         eth_igb_rar_set(dev, (void *)addr, 0, 0);
3136 }
3137 /*
3138  * Virtual Function operations
3139  */
3140 static void
3141 igbvf_intr_disable(struct e1000_hw *hw)
3142 {
3143         PMD_INIT_FUNC_TRACE();
3144
3145         /* Clear interrupt mask to stop from interrupts being generated */
3146         E1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);
3147
3148         E1000_WRITE_FLUSH(hw);
3149 }
3150
3151 static void
3152 igbvf_stop_adapter(struct rte_eth_dev *dev)
3153 {
3154         u32 reg_val;
3155         u16 i;
3156         struct rte_eth_dev_info dev_info;
3157         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158
3159         memset(&dev_info, 0, sizeof(dev_info));
3160         eth_igbvf_infos_get(dev, &dev_info);
3161
3162         /* Clear interrupt mask to stop from interrupts being generated */
3163         igbvf_intr_disable(hw);
3164
3165         /* Clear any pending interrupts, flush previous writes */
3166         E1000_READ_REG(hw, E1000_EICR);
3167
3168         /* Disable the transmit unit.  Each queue must be disabled. */
3169         for (i = 0; i < dev_info.max_tx_queues; i++)
3170                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);
3171
3172         /* Disable the receive unit by stopping each queue */
3173         for (i = 0; i < dev_info.max_rx_queues; i++) {
3174                 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));
3175                 reg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;
3176                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);
3177                 while (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)
3178                         ;
3179         }
3180
3181         /* flush all queues disables */
3182         E1000_WRITE_FLUSH(hw);
3183         msec_delay(2);
3184 }
3185
3186 static int eth_igbvf_link_update(struct e1000_hw *hw)
3187 {
3188         struct e1000_mbx_info *mbx = &hw->mbx;
3189         struct e1000_mac_info *mac = &hw->mac;
3190         int ret_val = E1000_SUCCESS;
3191
3192         PMD_INIT_LOG(DEBUG, "e1000_check_for_link_vf");
3193
3194         /*
3195          * We only want to run this if there has been a rst asserted.
3196          * in this case that could mean a link change, device reset,
3197          * or a virtual function reset
3198          */
3199
3200         /* If we were hit with a reset or timeout drop the link */
3201         if (!e1000_check_for_rst(hw, 0) || !mbx->timeout)
3202                 mac->get_link_status = TRUE;
3203
3204         if (!mac->get_link_status)
3205                 goto out;
3206
3207         /* if link status is down no point in checking to see if pf is up */
3208         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))
3209                 goto out;
3210
3211         /* if we passed all the tests above then the link is up and we no
3212          * longer need to check for link */
3213         mac->get_link_status = FALSE;
3214
3215 out:
3216         return ret_val;
3217 }
3218
3219
3220 static int
3221 igbvf_dev_configure(struct rte_eth_dev *dev)
3222 {
3223         struct rte_eth_conf* conf = &dev->data->dev_conf;
3224
3225         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3226                      dev->data->port_id);
3227
3228         /*
3229          * VF has no ability to enable/disable HW CRC
3230          * Keep the persistent behavior the same as Host PF
3231          */
3232 #ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC
3233         if (!conf->rxmode.hw_strip_crc) {
3234                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3235                 conf->rxmode.hw_strip_crc = 1;
3236         }
3237 #else
3238         if (conf->rxmode.hw_strip_crc) {
3239                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3240                 conf->rxmode.hw_strip_crc = 0;
3241         }
3242 #endif
3243
3244         return 0;
3245 }
3246
3247 static int
3248 igbvf_dev_start(struct rte_eth_dev *dev)
3249 {
3250         struct e1000_hw *hw =
3251                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252         struct e1000_adapter *adapter =
3253                 E1000_DEV_PRIVATE(dev->data->dev_private);
3254         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3255         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3256         int ret;
3257         uint32_t intr_vector = 0;
3258
3259         PMD_INIT_FUNC_TRACE();
3260
3261         hw->mac.ops.reset_hw(hw);
3262         adapter->stopped = 0;
3263
3264         /* Set all vfta */
3265         igbvf_set_vfta_all(dev,1);
3266
3267         eth_igbvf_tx_init(dev);
3268
3269         /* This can fail when allocating mbufs for descriptor rings */
3270         ret = eth_igbvf_rx_init(dev);
3271         if (ret) {
3272                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
3273                 igb_dev_clear_queues(dev);
3274                 return ret;
3275         }
3276
3277         /* check and configure queue intr-vector mapping */
3278         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3279                 intr_vector = dev->data->nb_rx_queues;
3280                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
3281                 if (ret)
3282                         return ret;
3283         }
3284
3285         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3286                 intr_handle->intr_vec =
3287                         rte_zmalloc("intr_vec",
3288                                     dev->data->nb_rx_queues * sizeof(int), 0);
3289                 if (!intr_handle->intr_vec) {
3290                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3291                                      " intr_vec", dev->data->nb_rx_queues);
3292                         return -ENOMEM;
3293                 }
3294         }
3295
3296         eth_igbvf_configure_msix_intr(dev);
3297
3298         /* enable uio/vfio intr/eventfd mapping */
3299         rte_intr_enable(intr_handle);
3300
3301         /* resume enabled intr since hw reset */
3302         igbvf_intr_enable(dev);
3303
3304         return 0;
3305 }
3306
3307 static void
3308 igbvf_dev_stop(struct rte_eth_dev *dev)
3309 {
3310         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3311         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3312
3313         PMD_INIT_FUNC_TRACE();
3314
3315         igbvf_stop_adapter(dev);
3316
3317         /*
3318           * Clear what we set, but we still keep shadow_vfta to
3319           * restore after device starts
3320           */
3321         igbvf_set_vfta_all(dev,0);
3322
3323         igb_dev_clear_queues(dev);
3324
3325         /* disable intr eventfd mapping */
3326         rte_intr_disable(intr_handle);
3327
3328         /* Clean datapath event and queue/vec mapping */
3329         rte_intr_efd_disable(intr_handle);
3330         if (intr_handle->intr_vec) {
3331                 rte_free(intr_handle->intr_vec);
3332                 intr_handle->intr_vec = NULL;
3333         }
3334 }
3335
3336 static void
3337 igbvf_dev_close(struct rte_eth_dev *dev)
3338 {
3339         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         struct e1000_adapter *adapter =
3341                 E1000_DEV_PRIVATE(dev->data->dev_private);
3342         struct ether_addr addr;
3343
3344         PMD_INIT_FUNC_TRACE();
3345
3346         e1000_reset_hw(hw);
3347
3348         igbvf_dev_stop(dev);
3349         adapter->stopped = 1;
3350         igb_dev_free_queues(dev);
3351
3352         /**
3353          * reprogram the RAR with a zero mac address,
3354          * to ensure that the VF traffic goes to the PF
3355          * after stop, close and detach of the VF.
3356          **/
3357
3358         memset(&addr, 0, sizeof(addr));
3359         igbvf_default_mac_addr_set(dev, &addr);
3360 }
3361
3362 static void
3363 igbvf_promiscuous_enable(struct rte_eth_dev *dev)
3364 {
3365         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366
3367         /* Set both unicast and multicast promisc */
3368         e1000_promisc_set_vf(hw, e1000_promisc_enabled);
3369 }
3370
3371 static void
3372 igbvf_promiscuous_disable(struct rte_eth_dev *dev)
3373 {
3374         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375
3376         /* If in allmulticast mode leave multicast promisc */
3377         if (dev->data->all_multicast == 1)
3378                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3379         else
3380                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3381 }
3382
3383 static void
3384 igbvf_allmulticast_enable(struct rte_eth_dev *dev)
3385 {
3386         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387
3388         /* In promiscuous mode multicast promisc already set */
3389         if (dev->data->promiscuous == 0)
3390                 e1000_promisc_set_vf(hw, e1000_promisc_multicast);
3391 }
3392
3393 static void
3394 igbvf_allmulticast_disable(struct rte_eth_dev *dev)
3395 {
3396         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397
3398         /* In promiscuous mode leave multicast promisc enabled */
3399         if (dev->data->promiscuous == 0)
3400                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
3401 }
3402
3403 static int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)
3404 {
3405         struct e1000_mbx_info *mbx = &hw->mbx;
3406         uint32_t msgbuf[2];
3407         s32 err;
3408
3409         /* After set vlan, vlan strip will also be enabled in igb driver*/
3410         msgbuf[0] = E1000_VF_SET_VLAN;
3411         msgbuf[1] = vid;
3412         /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */
3413         if (on)
3414                 msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
3415
3416         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
3417         if (err)
3418                 goto mbx_err;
3419
3420         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
3421         if (err)
3422                 goto mbx_err;
3423
3424         msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
3425         if (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK))
3426                 err = -EINVAL;
3427
3428 mbx_err:
3429         return err;
3430 }
3431
3432 static void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3433 {
3434         struct e1000_hw *hw =
3435                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436         struct e1000_vfta * shadow_vfta =
3437                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3438         int i = 0, j = 0, vfta = 0, mask = 1;
3439
3440         for (i = 0; i < IGB_VFTA_SIZE; i++){
3441                 vfta = shadow_vfta->vfta[i];
3442                 if(vfta){
3443                         mask = 1;
3444                         for (j = 0; j < 32; j++){
3445                                 if(vfta & mask)
3446                                         igbvf_set_vfta(hw,
3447                                                 (uint16_t)((i<<5)+j), on);
3448                                 mask<<=1;
3449                         }
3450                 }
3451         }
3452
3453 }
3454
3455 static int
3456 igbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3457 {
3458         struct e1000_hw *hw =
3459                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3460         struct e1000_vfta * shadow_vfta =
3461                 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3462         uint32_t vid_idx = 0;
3463         uint32_t vid_bit = 0;
3464         int ret = 0;
3465
3466         PMD_INIT_FUNC_TRACE();
3467
3468         /*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/
3469         ret = igbvf_set_vfta(hw, vlan_id, !!on);
3470         if(ret){
3471                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3472                 return ret;
3473         }
3474         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3475         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3476
3477         /*Save what we set and retore it after device reset*/
3478         if (on)
3479                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3480         else
3481                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3482
3483         return 0;
3484 }
3485
3486 static void
3487 igbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
3488 {
3489         struct e1000_hw *hw =
3490                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3491
3492         /* index is not used by rar_set() */
3493         hw->mac.ops.rar_set(hw, (void *)addr, 0);
3494 }
3495
3496
3497 static int
3498 eth_igb_rss_reta_update(struct rte_eth_dev *dev,
3499                         struct rte_eth_rss_reta_entry64 *reta_conf,
3500                         uint16_t reta_size)
3501 {
3502         uint8_t i, j, mask;
3503         uint32_t reta, r;
3504         uint16_t idx, shift;
3505         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3506
3507         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3508                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3509                         "(%d) doesn't match the number hardware can supported "
3510                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3511                 return -EINVAL;
3512         }
3513
3514         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3515                 idx = i / RTE_RETA_GROUP_SIZE;
3516                 shift = i % RTE_RETA_GROUP_SIZE;
3517                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3518                                                 IGB_4_BIT_MASK);
3519                 if (!mask)
3520                         continue;
3521                 if (mask == IGB_4_BIT_MASK)
3522                         r = 0;
3523                 else
3524                         r = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3525                 for (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {
3526                         if (mask & (0x1 << j))
3527                                 reta |= reta_conf[idx].reta[shift + j] <<
3528                                                         (CHAR_BIT * j);
3529                         else
3530                                 reta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));
3531                 }
3532                 E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);
3533         }
3534
3535         return 0;
3536 }
3537
3538 static int
3539 eth_igb_rss_reta_query(struct rte_eth_dev *dev,
3540                        struct rte_eth_rss_reta_entry64 *reta_conf,
3541                        uint16_t reta_size)
3542 {
3543         uint8_t i, j, mask;
3544         uint32_t reta;
3545         uint16_t idx, shift;
3546         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547
3548         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3549                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3550                         "(%d) doesn't match the number hardware can supported "
3551                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3552                 return -EINVAL;
3553         }
3554
3555         for (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {
3556                 idx = i / RTE_RETA_GROUP_SIZE;
3557                 shift = i % RTE_RETA_GROUP_SIZE;
3558                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3559                                                 IGB_4_BIT_MASK);
3560                 if (!mask)
3561                         continue;
3562                 reta = E1000_READ_REG(hw, E1000_RETA(i >> 2));
3563                 for (j = 0; j < IGB_4_BIT_WIDTH; j++) {
3564                         if (mask & (0x1 << j))
3565                                 reta_conf[idx].reta[shift + j] =
3566                                         ((reta >> (CHAR_BIT * j)) &
3567                                                 IGB_8_BIT_MASK);
3568                 }
3569         }
3570
3571         return 0;
3572 }
3573
3574 #define MAC_TYPE_FILTER_SUP(type)    do {\
3575         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3576                 (type) != e1000_82576 && (type) != e1000_i210 &&\
3577                 (type) != e1000_i211)\
3578                 return -ENOTSUP;\
3579 } while (0)
3580
3581 static int
3582 eth_igb_syn_filter_set(struct rte_eth_dev *dev,
3583                         struct rte_eth_syn_filter *filter,
3584                         bool add)
3585 {
3586         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3587         struct e1000_filter_info *filter_info =
3588                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3589         uint32_t synqf, rfctl;
3590
3591         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3592                 return -EINVAL;
3593
3594         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3595
3596         if (add) {
3597                 if (synqf & E1000_SYN_FILTER_ENABLE)
3598                         return -EINVAL;
3599
3600                 synqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &
3601                         E1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);
3602
3603                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3604                 if (filter->hig_pri)
3605                         rfctl |= E1000_RFCTL_SYNQFP;
3606                 else
3607                         rfctl &= ~E1000_RFCTL_SYNQFP;
3608
3609                 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
3610         } else {
3611                 if (!(synqf & E1000_SYN_FILTER_ENABLE))
3612                         return -ENOENT;
3613                 synqf = 0;
3614         }
3615
3616         filter_info->syn_info = synqf;
3617         E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
3618         E1000_WRITE_FLUSH(hw);
3619         return 0;
3620 }
3621
3622 static int
3623 eth_igb_syn_filter_get(struct rte_eth_dev *dev,
3624                         struct rte_eth_syn_filter *filter)
3625 {
3626         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         uint32_t synqf, rfctl;
3628
3629         synqf = E1000_READ_REG(hw, E1000_SYNQF(0));
3630         if (synqf & E1000_SYN_FILTER_ENABLE) {
3631                 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
3632                 filter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;
3633                 filter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>
3634                                 E1000_SYN_FILTER_QUEUE_SHIFT);
3635                 return 0;
3636         }
3637
3638         return -ENOENT;
3639 }
3640
3641 static int
3642 eth_igb_syn_filter_handle(struct rte_eth_dev *dev,
3643                         enum rte_filter_op filter_op,
3644                         void *arg)
3645 {
3646         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647         int ret;
3648
3649         MAC_TYPE_FILTER_SUP(hw->mac.type);
3650
3651         if (filter_op == RTE_ETH_FILTER_NOP)
3652                 return 0;
3653
3654         if (arg == NULL) {
3655                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3656                             filter_op);
3657                 return -EINVAL;
3658         }
3659
3660         switch (filter_op) {
3661         case RTE_ETH_FILTER_ADD:
3662                 ret = eth_igb_syn_filter_set(dev,
3663                                 (struct rte_eth_syn_filter *)arg,
3664                                 TRUE);
3665                 break;
3666         case RTE_ETH_FILTER_DELETE:
3667                 ret = eth_igb_syn_filter_set(dev,
3668                                 (struct rte_eth_syn_filter *)arg,
3669                                 FALSE);
3670                 break;
3671         case RTE_ETH_FILTER_GET:
3672                 ret = eth_igb_syn_filter_get(dev,
3673                                 (struct rte_eth_syn_filter *)arg);
3674                 break;
3675         default:
3676                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
3677                 ret = -EINVAL;
3678                 break;
3679         }
3680
3681         return ret;
3682 }
3683
3684 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3685         if ((type) != e1000_82580 && (type) != e1000_i350 &&\
3686                 (type) != e1000_i210 && (type) != e1000_i211)\
3687                 return -ENOSYS; \
3688 } while (0)
3689
3690 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/
3691 static inline int
3692 ntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,
3693                         struct e1000_2tuple_filter_info *filter_info)
3694 {
3695         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM)
3696                 return -EINVAL;
3697         if (filter->priority > E1000_2TUPLE_MAX_PRI)
3698                 return -EINVAL;  /* filter index is out of range. */
3699         if (filter->tcp_flags > TCP_FLAG_ALL)
3700                 return -EINVAL;  /* flags is invalid. */
3701
3702         switch (filter->dst_port_mask) {
3703         case UINT16_MAX:
3704                 filter_info->dst_port_mask = 0;
3705                 filter_info->dst_port = filter->dst_port;
3706                 break;
3707         case 0:
3708                 filter_info->dst_port_mask = 1;
3709                 break;
3710         default:
3711                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3712                 return -EINVAL;
3713         }
3714
3715         switch (filter->proto_mask) {
3716         case UINT8_MAX:
3717                 filter_info->proto_mask = 0;
3718                 filter_info->proto = filter->proto;
3719                 break;
3720         case 0:
3721                 filter_info->proto_mask = 1;
3722                 break;
3723         default:
3724                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3725                 return -EINVAL;
3726         }
3727
3728         filter_info->priority = (uint8_t)filter->priority;
3729         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
3730                 filter_info->tcp_flags = filter->tcp_flags;
3731         else
3732                 filter_info->tcp_flags = 0;
3733
3734         return 0;
3735 }
3736
3737 static inline struct e1000_2tuple_filter *
3738 igb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,
3739                         struct e1000_2tuple_filter_info *key)
3740 {
3741         struct e1000_2tuple_filter *it;
3742
3743         TAILQ_FOREACH(it, filter_list, entries) {
3744                 if (memcmp(key, &it->filter_info,
3745                         sizeof(struct e1000_2tuple_filter_info)) == 0) {
3746                         return it;
3747                 }
3748         }
3749         return NULL;
3750 }
3751
3752 /* inject a igb 2tuple filter to HW */
3753 static inline void
3754 igb_inject_2uple_filter(struct rte_eth_dev *dev,
3755                            struct e1000_2tuple_filter *filter)
3756 {
3757         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758         uint32_t ttqf = E1000_TTQF_DISABLE_MASK;
3759         uint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;
3760         int i;
3761
3762         i = filter->index;
3763         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
3764         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
3765                 imir |= E1000_IMIR_PORT_BP;
3766         else
3767                 imir &= ~E1000_IMIR_PORT_BP;
3768
3769         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
3770
3771         ttqf |= E1000_TTQF_QUEUE_ENABLE;
3772         ttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);
3773         ttqf |= (uint32_t)(filter->filter_info.proto &
3774                                                 E1000_TTQF_PROTOCOL_MASK);
3775         if (filter->filter_info.proto_mask == 0)
3776                 ttqf &= ~E1000_TTQF_MASK_ENABLE;
3777
3778         /* tcp flags bits setting. */
3779         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
3780                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
3781                         imir_ext |= E1000_IMIREXT_CTRL_URG;
3782                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
3783                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
3784                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
3785                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
3786                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
3787                         imir_ext |= E1000_IMIREXT_CTRL_RST;
3788                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
3789                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
3790                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
3791                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
3792         } else {
3793                 imir_ext |= E1000_IMIREXT_CTRL_BP;
3794         }
3795         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
3796         E1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);
3797         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
3798 }
3799
3800 /*
3801  * igb_add_2tuple_filter - add a 2tuple filter
3802  *
3803  * @param
3804  * dev: Pointer to struct rte_eth_dev.
3805  * ntuple_filter: ponter to the filter that will be added.
3806  *
3807  * @return
3808  *    - On success, zero.
3809  *    - On failure, a negative value.
3810  */
3811 static int
3812 igb_add_2tuple_filter(struct rte_eth_dev *dev,
3813                         struct rte_eth_ntuple_filter *ntuple_filter)
3814 {
3815         struct e1000_filter_info *filter_info =
3816                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3817         struct e1000_2tuple_filter *filter;
3818         int i, ret;
3819
3820         filter = rte_zmalloc("e1000_2tuple_filter",
3821                         sizeof(struct e1000_2tuple_filter), 0);
3822         if (filter == NULL)
3823                 return -ENOMEM;
3824
3825         ret = ntuple_filter_to_2tuple(ntuple_filter,
3826                                       &filter->filter_info);
3827         if (ret < 0) {
3828                 rte_free(filter);
3829                 return ret;
3830         }
3831         if (igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3832                                          &filter->filter_info) != NULL) {
3833                 PMD_DRV_LOG(ERR, "filter exists.");
3834                 rte_free(filter);
3835                 return -EEXIST;
3836         }
3837         filter->queue = ntuple_filter->queue;
3838
3839         /*
3840          * look for an unused 2tuple filter index,
3841          * and insert the filter to list.
3842          */
3843         for (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {
3844                 if (!(filter_info->twotuple_mask & (1 << i))) {
3845                         filter_info->twotuple_mask |= 1 << i;
3846                         filter->index = i;
3847                         TAILQ_INSERT_TAIL(&filter_info->twotuple_list,
3848                                           filter,
3849                                           entries);
3850                         break;
3851                 }
3852         }
3853         if (i >= E1000_MAX_TTQF_FILTERS) {
3854                 PMD_DRV_LOG(ERR, "2tuple filters are full.");
3855                 rte_free(filter);
3856                 return -ENOSYS;
3857         }
3858
3859         igb_inject_2uple_filter(dev, filter);
3860         return 0;
3861 }
3862
3863 /*
3864  * igb_remove_2tuple_filter - remove a 2tuple filter
3865  *
3866  * @param
3867  * dev: Pointer to struct rte_eth_dev.
3868  * ntuple_filter: ponter to the filter that will be removed.
3869  *
3870  * @return
3871  *    - On success, zero.
3872  *    - On failure, a negative value.
3873  */
3874 static int
3875 igb_remove_2tuple_filter(struct rte_eth_dev *dev,
3876                         struct rte_eth_ntuple_filter *ntuple_filter)
3877 {
3878         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct e1000_filter_info *filter_info =
3880                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3881         struct e1000_2tuple_filter_info filter_2tuple;
3882         struct e1000_2tuple_filter *filter;
3883         int ret;
3884
3885         memset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));
3886         ret = ntuple_filter_to_2tuple(ntuple_filter,
3887                                       &filter_2tuple);
3888         if (ret < 0)
3889                 return ret;
3890
3891         filter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,
3892                                          &filter_2tuple);
3893         if (filter == NULL) {
3894                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3895                 return -ENOENT;
3896         }
3897
3898         filter_info->twotuple_mask &= ~(1 << filter->index);
3899         TAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);
3900         rte_free(filter);
3901
3902         E1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);
3903         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
3904         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
3905         return 0;
3906 }
3907
3908 static inline struct e1000_flex_filter *
3909 eth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,
3910                         struct e1000_flex_filter_info *key)
3911 {
3912         struct e1000_flex_filter *it;
3913
3914         TAILQ_FOREACH(it, filter_list, entries) {
3915                 if (memcmp(key, &it->filter_info,
3916                         sizeof(struct e1000_flex_filter_info)) == 0)
3917                         return it;
3918         }
3919
3920         return NULL;
3921 }
3922
3923 static int
3924 eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,
3925                         struct rte_eth_flex_filter *filter,
3926                         bool add)
3927 {
3928         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         struct e1000_filter_info *filter_info =
3930                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3931         struct e1000_flex_filter *flex_filter, *it;
3932         uint32_t wufc, queueing, mask;
3933         uint32_t reg_off;
3934         uint8_t shift, i, j = 0;
3935
3936         flex_filter = rte_zmalloc("e1000_flex_filter",
3937                         sizeof(struct e1000_flex_filter), 0);
3938         if (flex_filter == NULL)
3939                 return -ENOMEM;
3940
3941         flex_filter->filter_info.len = filter->len;
3942         flex_filter->filter_info.priority = filter->priority;
3943         memcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);
3944         for (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {
3945                 mask = 0;
3946                 /* reverse bits in flex filter's mask*/
3947                 for (shift = 0; shift < CHAR_BIT; shift++) {
3948                         if (filter->mask[i] & (0x01 << shift))
3949                                 mask |= (0x80 >> shift);
3950                 }
3951                 flex_filter->filter_info.mask[i] = mask;
3952         }
3953
3954         wufc = E1000_READ_REG(hw, E1000_WUFC);
3955
3956         if (add) {
3957                 if (eth_igb_flex_filter_lookup(&filter_info->flex_list,
3958                                 &flex_filter->filter_info) != NULL) {
3959                         PMD_DRV_LOG(ERR, "filter exists.");
3960                         rte_free(flex_filter);
3961                         return -EEXIST;
3962                 }
3963                 flex_filter->queue = filter->queue;
3964                 /*
3965                  * look for an unused flex filter index
3966                  * and insert the filter into the list.
3967                  */
3968                 for (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {
3969                         if (!(filter_info->flex_mask & (1 << i))) {
3970                                 filter_info->flex_mask |= 1 << i;
3971                                 flex_filter->index = i;
3972                                 TAILQ_INSERT_TAIL(&filter_info->flex_list,
3973                                         flex_filter,
3974                                         entries);
3975                                 break;
3976                         }
3977                 }
3978                 if (i >= E1000_MAX_FLEX_FILTERS) {
3979                         PMD_DRV_LOG(ERR, "flex filters are full.");
3980                         rte_free(flex_filter);
3981                         return -ENOSYS;
3982                 }
3983
3984                 if (flex_filter->index < E1000_MAX_FHFT)
3985                         reg_off = E1000_FHFT(flex_filter->index);
3986                 else
3987                         reg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);
3988
3989                 E1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |
3990                                 (E1000_WUFC_FLX0 << flex_filter->index));
3991                 queueing = filter->len |
3992                         (filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |
3993                         (filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);
3994                 E1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,
3995                                 queueing);
3996                 for (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {
3997                         E1000_WRITE_REG(hw, reg_off,
3998                                         flex_filter->filter_info.dwords[j]);
3999                         reg_off += sizeof(uint32_t);
4000                         E1000_WRITE_REG(hw, reg_off,
4001                                         flex_filter->filter_info.dwords[++j]);
4002                         reg_off += sizeof(uint32_t);
4003                         E1000_WRITE_REG(hw, reg_off,
4004                                 (uint32_t)flex_filter->filter_info.mask[i]);
4005                         reg_off += sizeof(uint32_t) * 2;
4006                         ++j;
4007                 }
4008         } else {
4009                 it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4010                                 &flex_filter->filter_info);
4011                 if (it == NULL) {
4012                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4013                         rte_free(flex_filter);
4014                         return -ENOENT;
4015                 }
4016
4017                 if (it->index < E1000_MAX_FHFT)
4018                         reg_off = E1000_FHFT(it->index);
4019                 else
4020                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4021
4022                 for (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)
4023                         E1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);
4024                 E1000_WRITE_REG(hw, E1000_WUFC, wufc &
4025                         (~(E1000_WUFC_FLX0 << it->index)));
4026
4027                 filter_info->flex_mask &= ~(1 << it->index);
4028                 TAILQ_REMOVE(&filter_info->flex_list, it, entries);
4029                 rte_free(it);
4030                 rte_free(flex_filter);
4031         }
4032
4033         return 0;
4034 }
4035
4036 static int
4037 eth_igb_get_flex_filter(struct rte_eth_dev *dev,
4038                         struct rte_eth_flex_filter *filter)
4039 {
4040         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         struct e1000_filter_info *filter_info =
4042                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4043         struct e1000_flex_filter flex_filter, *it;
4044         uint32_t wufc, queueing, wufc_en = 0;
4045
4046         memset(&flex_filter, 0, sizeof(struct e1000_flex_filter));
4047         flex_filter.filter_info.len = filter->len;
4048         flex_filter.filter_info.priority = filter->priority;
4049         memcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);
4050         memcpy(flex_filter.filter_info.mask, filter->mask,
4051                         RTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));
4052
4053         it = eth_igb_flex_filter_lookup(&filter_info->flex_list,
4054                                 &flex_filter.filter_info);
4055         if (it == NULL) {
4056                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4057                 return -ENOENT;
4058         }
4059
4060         wufc = E1000_READ_REG(hw, E1000_WUFC);
4061         wufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);
4062
4063         if ((wufc & wufc_en) == wufc_en) {
4064                 uint32_t reg_off = 0;
4065                 if (it->index < E1000_MAX_FHFT)
4066                         reg_off = E1000_FHFT(it->index);
4067                 else
4068                         reg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);
4069
4070                 queueing = E1000_READ_REG(hw,
4071                                 reg_off + E1000_FHFT_QUEUEING_OFFSET);
4072                 filter->len = queueing & E1000_FHFT_QUEUEING_LEN;
4073                 filter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>
4074                         E1000_FHFT_QUEUEING_PRIO_SHIFT;
4075                 filter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>
4076                         E1000_FHFT_QUEUEING_QUEUE_SHIFT;
4077                 return 0;
4078         }
4079         return -ENOENT;
4080 }
4081
4082 static int
4083 eth_igb_flex_filter_handle(struct rte_eth_dev *dev,
4084                         enum rte_filter_op filter_op,
4085                         void *arg)
4086 {
4087         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4088         struct rte_eth_flex_filter *filter;
4089         int ret = 0;
4090
4091         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4092
4093         if (filter_op == RTE_ETH_FILTER_NOP)
4094                 return ret;
4095
4096         if (arg == NULL) {
4097                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4098                             filter_op);
4099                 return -EINVAL;
4100         }
4101
4102         filter = (struct rte_eth_flex_filter *)arg;
4103         if (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN
4104             || filter->len % sizeof(uint64_t) != 0) {
4105                 PMD_DRV_LOG(ERR, "filter's length is out of range");
4106                 return -EINVAL;
4107         }
4108         if (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {
4109                 PMD_DRV_LOG(ERR, "filter's priority is out of range");
4110                 return -EINVAL;
4111         }
4112
4113         switch (filter_op) {
4114         case RTE_ETH_FILTER_ADD:
4115                 ret = eth_igb_add_del_flex_filter(dev, filter, TRUE);
4116                 break;
4117         case RTE_ETH_FILTER_DELETE:
4118                 ret = eth_igb_add_del_flex_filter(dev, filter, FALSE);
4119                 break;
4120         case RTE_ETH_FILTER_GET:
4121                 ret = eth_igb_get_flex_filter(dev, filter);
4122                 break;
4123         default:
4124                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
4125                 ret = -EINVAL;
4126                 break;
4127         }
4128
4129         return ret;
4130 }
4131
4132 /* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/
4133 static inline int
4134 ntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,
4135                         struct e1000_5tuple_filter_info *filter_info)
4136 {
4137         if (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)
4138                 return -EINVAL;
4139         if (filter->priority > E1000_2TUPLE_MAX_PRI)
4140                 return -EINVAL;  /* filter index is out of range. */
4141         if (filter->tcp_flags > TCP_FLAG_ALL)
4142                 return -EINVAL;  /* flags is invalid. */
4143
4144         switch (filter->dst_ip_mask) {
4145         case UINT32_MAX:
4146                 filter_info->dst_ip_mask = 0;
4147                 filter_info->dst_ip = filter->dst_ip;
4148                 break;
4149         case 0:
4150                 filter_info->dst_ip_mask = 1;
4151                 break;
4152         default:
4153                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4154                 return -EINVAL;
4155         }
4156
4157         switch (filter->src_ip_mask) {
4158         case UINT32_MAX:
4159                 filter_info->src_ip_mask = 0;
4160                 filter_info->src_ip = filter->src_ip;
4161                 break;
4162         case 0:
4163                 filter_info->src_ip_mask = 1;
4164                 break;
4165         default:
4166                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4167                 return -EINVAL;
4168         }
4169
4170         switch (filter->dst_port_mask) {
4171         case UINT16_MAX:
4172                 filter_info->dst_port_mask = 0;
4173                 filter_info->dst_port = filter->dst_port;
4174                 break;
4175         case 0:
4176                 filter_info->dst_port_mask = 1;
4177                 break;
4178         default:
4179                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4180                 return -EINVAL;
4181         }
4182
4183         switch (filter->src_port_mask) {
4184         case UINT16_MAX:
4185                 filter_info->src_port_mask = 0;
4186                 filter_info->src_port = filter->src_port;
4187                 break;
4188         case 0:
4189                 filter_info->src_port_mask = 1;
4190                 break;
4191         default:
4192                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4193                 return -EINVAL;
4194         }
4195
4196         switch (filter->proto_mask) {
4197         case UINT8_MAX:
4198                 filter_info->proto_mask = 0;
4199                 filter_info->proto = filter->proto;
4200                 break;
4201         case 0:
4202                 filter_info->proto_mask = 1;
4203                 break;
4204         default:
4205                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4206                 return -EINVAL;
4207         }
4208
4209         filter_info->priority = (uint8_t)filter->priority;
4210         if (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)
4211                 filter_info->tcp_flags = filter->tcp_flags;
4212         else
4213                 filter_info->tcp_flags = 0;
4214
4215         return 0;
4216 }
4217
4218 static inline struct e1000_5tuple_filter *
4219 igb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,
4220                         struct e1000_5tuple_filter_info *key)
4221 {
4222         struct e1000_5tuple_filter *it;
4223
4224         TAILQ_FOREACH(it, filter_list, entries) {
4225                 if (memcmp(key, &it->filter_info,
4226                         sizeof(struct e1000_5tuple_filter_info)) == 0) {
4227                         return it;
4228                 }
4229         }
4230         return NULL;
4231 }
4232
4233 /* inject a igb 5-tuple filter to HW */
4234 static inline void
4235 igb_inject_5tuple_filter_82576(struct rte_eth_dev *dev,
4236                            struct e1000_5tuple_filter *filter)
4237 {
4238         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4239         uint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;
4240         uint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;
4241         uint8_t i;
4242
4243         i = filter->index;
4244         ftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;
4245         if (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */
4246                 ftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;
4247         if (filter->filter_info.dst_ip_mask == 0)
4248                 ftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;
4249         if (filter->filter_info.src_port_mask == 0)
4250                 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
4251         if (filter->filter_info.proto_mask == 0)
4252                 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
4253         ftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &
4254                 E1000_FTQF_QUEUE_MASK;
4255         ftqf |= E1000_FTQF_QUEUE_ENABLE;
4256         E1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);
4257         E1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);
4258         E1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);
4259
4260         spqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;
4261         E1000_WRITE_REG(hw, E1000_SPQF(i), spqf);
4262
4263         imir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);
4264         if (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */
4265                 imir |= E1000_IMIR_PORT_BP;
4266         else
4267                 imir &= ~E1000_IMIR_PORT_BP;
4268         imir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;
4269
4270         /* tcp flags bits setting. */
4271         if (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {
4272                 if (filter->filter_info.tcp_flags & TCP_URG_FLAG)
4273                         imir_ext |= E1000_IMIREXT_CTRL_URG;
4274                 if (filter->filter_info.tcp_flags & TCP_ACK_FLAG)
4275                         imir_ext |= E1000_IMIREXT_CTRL_ACK;
4276                 if (filter->filter_info.tcp_flags & TCP_PSH_FLAG)
4277                         imir_ext |= E1000_IMIREXT_CTRL_PSH;
4278                 if (filter->filter_info.tcp_flags & TCP_RST_FLAG)
4279                         imir_ext |= E1000_IMIREXT_CTRL_RST;
4280                 if (filter->filter_info.tcp_flags & TCP_SYN_FLAG)
4281                         imir_ext |= E1000_IMIREXT_CTRL_SYN;
4282                 if (filter->filter_info.tcp_flags & TCP_FIN_FLAG)
4283                         imir_ext |= E1000_IMIREXT_CTRL_FIN;
4284         } else {
4285                 imir_ext |= E1000_IMIREXT_CTRL_BP;
4286         }
4287         E1000_WRITE_REG(hw, E1000_IMIR(i), imir);
4288         E1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);
4289 }
4290
4291 /*
4292  * igb_add_5tuple_filter_82576 - add a 5tuple filter
4293  *
4294  * @param
4295  * dev: Pointer to struct rte_eth_dev.
4296  * ntuple_filter: ponter to the filter that will be added.
4297  *
4298  * @return
4299  *    - On success, zero.
4300  *    - On failure, a negative value.
4301  */
4302 static int
4303 igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,
4304                         struct rte_eth_ntuple_filter *ntuple_filter)
4305 {
4306         struct e1000_filter_info *filter_info =
4307                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4308         struct e1000_5tuple_filter *filter;
4309         uint8_t i;
4310         int ret;
4311
4312         filter = rte_zmalloc("e1000_5tuple_filter",
4313                         sizeof(struct e1000_5tuple_filter), 0);
4314         if (filter == NULL)
4315                 return -ENOMEM;
4316
4317         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4318                                             &filter->filter_info);
4319         if (ret < 0) {
4320                 rte_free(filter);
4321                 return ret;
4322         }
4323
4324         if (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4325                                          &filter->filter_info) != NULL) {
4326                 PMD_DRV_LOG(ERR, "filter exists.");
4327                 rte_free(filter);
4328                 return -EEXIST;
4329         }
4330         filter->queue = ntuple_filter->queue;
4331
4332         /*
4333          * look for an unused 5tuple filter index,
4334          * and insert the filter to list.
4335          */
4336         for (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {
4337                 if (!(filter_info->fivetuple_mask & (1 << i))) {
4338                         filter_info->fivetuple_mask |= 1 << i;
4339                         filter->index = i;
4340                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4341                                           filter,
4342                                           entries);
4343                         break;
4344                 }
4345         }
4346         if (i >= E1000_MAX_FTQF_FILTERS) {
4347                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4348                 rte_free(filter);
4349                 return -ENOSYS;
4350         }
4351
4352         igb_inject_5tuple_filter_82576(dev, filter);
4353         return 0;
4354 }
4355
4356 /*
4357  * igb_remove_5tuple_filter_82576 - remove a 5tuple filter
4358  *
4359  * @param
4360  * dev: Pointer to struct rte_eth_dev.
4361  * ntuple_filter: ponter to the filter that will be removed.
4362  *
4363  * @return
4364  *    - On success, zero.
4365  *    - On failure, a negative value.
4366  */
4367 static int
4368 igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,
4369                                 struct rte_eth_ntuple_filter *ntuple_filter)
4370 {
4371         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4372         struct e1000_filter_info *filter_info =
4373                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4374         struct e1000_5tuple_filter_info filter_5tuple;
4375         struct e1000_5tuple_filter *filter;
4376         int ret;
4377
4378         memset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));
4379         ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4380                                             &filter_5tuple);
4381         if (ret < 0)
4382                 return ret;
4383
4384         filter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,
4385                                          &filter_5tuple);
4386         if (filter == NULL) {
4387                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4388                 return -ENOENT;
4389         }
4390
4391         filter_info->fivetuple_mask &= ~(1 << filter->index);
4392         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4393         rte_free(filter);
4394
4395         E1000_WRITE_REG(hw, E1000_FTQF(filter->index),
4396                         E1000_FTQF_VF_BP | E1000_FTQF_MASK);
4397         E1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);
4398         E1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);
4399         E1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);
4400         E1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);
4401         E1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);
4402         return 0;
4403 }
4404
4405 static int
4406 eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4407 {
4408         uint32_t rctl;
4409         struct e1000_hw *hw;
4410         struct rte_eth_dev_info dev_info;
4411         uint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +
4412                                      VLAN_TAG_SIZE);
4413
4414         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415
4416 #ifdef RTE_LIBRTE_82571_SUPPORT
4417         /* XXX: not bigger than max_rx_pktlen */
4418         if (hw->mac.type == e1000_82571)
4419                 return -ENOTSUP;
4420 #endif
4421         eth_igb_infos_get(dev, &dev_info);
4422
4423         /* check that mtu is within the allowed range */
4424         if ((mtu < ETHER_MIN_MTU) ||
4425             (frame_size > dev_info.max_rx_pktlen))
4426                 return -EINVAL;
4427
4428         /* refuse mtu that requires the support of scattered packets when this
4429          * feature has not been enabled before. */
4430         if (!dev->data->scattered_rx &&
4431             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
4432                 return -EINVAL;
4433
4434         rctl = E1000_READ_REG(hw, E1000_RCTL);
4435
4436         /* switch to jumbo mode if needed */
4437         if (frame_size > ETHER_MAX_LEN) {
4438                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4439                 rctl |= E1000_RCTL_LPE;
4440         } else {
4441                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4442                 rctl &= ~E1000_RCTL_LPE;
4443         }
4444         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
4445
4446         /* update max frame size */
4447         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4448
4449         E1000_WRITE_REG(hw, E1000_RLPML,
4450                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
4451
4452         return 0;
4453 }
4454
4455 /*
4456  * igb_add_del_ntuple_filter - add or delete a ntuple filter
4457  *
4458  * @param
4459  * dev: Pointer to struct rte_eth_dev.
4460  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4461  * add: if true, add filter, if false, remove filter
4462  *
4463  * @return
4464  *    - On success, zero.
4465  *    - On failure, a negative value.
4466  */
4467 static int
4468 igb_add_del_ntuple_filter(struct rte_eth_dev *dev,
4469                         struct rte_eth_ntuple_filter *ntuple_filter,
4470                         bool add)
4471 {
4472         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         int ret;
4474
4475         switch (ntuple_filter->flags) {
4476         case RTE_5TUPLE_FLAGS:
4477         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4478                 if (hw->mac.type != e1000_82576)
4479                         return -ENOTSUP;
4480                 if (add)
4481                         ret = igb_add_5tuple_filter_82576(dev,
4482                                                           ntuple_filter);
4483                 else
4484                         ret = igb_remove_5tuple_filter_82576(dev,
4485                                                              ntuple_filter);
4486                 break;
4487         case RTE_2TUPLE_FLAGS:
4488         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4489                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350 &&
4490                         hw->mac.type != e1000_i210 &&
4491                         hw->mac.type != e1000_i211)
4492                         return -ENOTSUP;
4493                 if (add)
4494                         ret = igb_add_2tuple_filter(dev, ntuple_filter);
4495                 else
4496                         ret = igb_remove_2tuple_filter(dev, ntuple_filter);
4497                 break;
4498         default:
4499                 ret = -EINVAL;
4500                 break;
4501         }
4502
4503         return ret;
4504 }
4505
4506 /*
4507  * igb_get_ntuple_filter - get a ntuple filter
4508  *
4509  * @param
4510  * dev: Pointer to struct rte_eth_dev.
4511  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4512  *
4513  * @return
4514  *    - On success, zero.
4515  *    - On failure, a negative value.
4516  */
4517 static int
4518 igb_get_ntuple_filter(struct rte_eth_dev *dev,
4519                         struct rte_eth_ntuple_filter *ntuple_filter)
4520 {
4521         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4522         struct e1000_filter_info *filter_info =
4523                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4524         struct e1000_5tuple_filter_info filter_5tuple;
4525         struct e1000_2tuple_filter_info filter_2tuple;
4526         struct e1000_5tuple_filter *p_5tuple_filter;
4527         struct e1000_2tuple_filter *p_2tuple_filter;
4528         int ret;
4529
4530         switch (ntuple_filter->flags) {
4531         case RTE_5TUPLE_FLAGS:
4532         case (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4533                 if (hw->mac.type != e1000_82576)
4534                         return -ENOTSUP;
4535                 memset(&filter_5tuple,
4536                         0,
4537                         sizeof(struct e1000_5tuple_filter_info));
4538                 ret = ntuple_filter_to_5tuple_82576(ntuple_filter,
4539                                                     &filter_5tuple);
4540                 if (ret < 0)
4541                         return ret;
4542                 p_5tuple_filter = igb_5tuple_filter_lookup_82576(
4543                                         &filter_info->fivetuple_list,
4544                                         &filter_5tuple);
4545                 if (p_5tuple_filter == NULL) {
4546                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4547                         return -ENOENT;
4548                 }
4549                 ntuple_filter->queue = p_5tuple_filter->queue;
4550                 break;
4551         case RTE_2TUPLE_FLAGS:
4552         case (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):
4553                 if (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)
4554                         return -ENOTSUP;
4555                 memset(&filter_2tuple,
4556                         0,
4557                         sizeof(struct e1000_2tuple_filter_info));
4558                 ret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);
4559                 if (ret < 0)
4560                         return ret;
4561                 p_2tuple_filter = igb_2tuple_filter_lookup(
4562                                         &filter_info->twotuple_list,
4563                                         &filter_2tuple);
4564                 if (p_2tuple_filter == NULL) {
4565                         PMD_DRV_LOG(ERR, "filter doesn't exist.");
4566                         return -ENOENT;
4567                 }
4568                 ntuple_filter->queue = p_2tuple_filter->queue;
4569                 break;
4570         default:
4571                 ret = -EINVAL;
4572                 break;
4573         }
4574
4575         return 0;
4576 }
4577
4578 /*
4579  * igb_ntuple_filter_handle - Handle operations for ntuple filter.
4580  * @dev: pointer to rte_eth_dev structure
4581  * @filter_op:operation will be taken.
4582  * @arg: a pointer to specific structure corresponding to the filter_op
4583  */
4584 static int
4585 igb_ntuple_filter_handle(struct rte_eth_dev *dev,
4586                                 enum rte_filter_op filter_op,
4587                                 void *arg)
4588 {
4589         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4590         int ret;
4591
4592         MAC_TYPE_FILTER_SUP(hw->mac.type);
4593
4594         if (filter_op == RTE_ETH_FILTER_NOP)
4595                 return 0;
4596
4597         if (arg == NULL) {
4598                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4599                             filter_op);
4600                 return -EINVAL;
4601         }
4602
4603         switch (filter_op) {
4604         case RTE_ETH_FILTER_ADD:
4605                 ret = igb_add_del_ntuple_filter(dev,
4606                         (struct rte_eth_ntuple_filter *)arg,
4607                         TRUE);
4608                 break;
4609         case RTE_ETH_FILTER_DELETE:
4610                 ret = igb_add_del_ntuple_filter(dev,
4611                         (struct rte_eth_ntuple_filter *)arg,
4612                         FALSE);
4613                 break;
4614         case RTE_ETH_FILTER_GET:
4615                 ret = igb_get_ntuple_filter(dev,
4616                         (struct rte_eth_ntuple_filter *)arg);
4617                 break;
4618         default:
4619                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4620                 ret = -EINVAL;
4621                 break;
4622         }
4623         return ret;
4624 }
4625
4626 static inline int
4627 igb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,
4628                         uint16_t ethertype)
4629 {
4630         int i;
4631
4632         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4633                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
4634                     (filter_info->ethertype_mask & (1 << i)))
4635                         return i;
4636         }
4637         return -1;
4638 }
4639
4640 static inline int
4641 igb_ethertype_filter_insert(struct e1000_filter_info *filter_info,
4642                         uint16_t ethertype, uint32_t etqf)
4643 {
4644         int i;
4645
4646         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
4647                 if (!(filter_info->ethertype_mask & (1 << i))) {
4648                         filter_info->ethertype_mask |= 1 << i;
4649                         filter_info->ethertype_filters[i].ethertype = ethertype;
4650                         filter_info->ethertype_filters[i].etqf = etqf;
4651                         return i;
4652                 }
4653         }
4654         return -1;
4655 }
4656
4657 static int
4658 igb_ethertype_filter_remove(struct e1000_filter_info *filter_info,
4659                         uint8_t idx)
4660 {
4661         if (idx >= E1000_MAX_ETQF_FILTERS)
4662                 return -1;
4663         filter_info->ethertype_mask &= ~(1 << idx);
4664         filter_info->ethertype_filters[idx].ethertype = 0;
4665         filter_info->ethertype_filters[idx].etqf = 0;
4666         return idx;
4667 }
4668
4669
4670 int
4671 igb_add_del_ethertype_filter(struct rte_eth_dev *dev,
4672                         struct rte_eth_ethertype_filter *filter,
4673                         bool add)
4674 {
4675         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4676         struct e1000_filter_info *filter_info =
4677                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4678         uint32_t etqf = 0;
4679         int ret;
4680
4681         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4682                 filter->ether_type == ETHER_TYPE_IPv6) {
4683                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4684                         " ethertype filter.", filter->ether_type);
4685                 return -EINVAL;
4686         }
4687
4688         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4689                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4690                 return -EINVAL;
4691         }
4692         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4693                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4694                 return -EINVAL;
4695         }
4696
4697         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4698         if (ret >= 0 && add) {
4699                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4700                             filter->ether_type);
4701                 return -EEXIST;
4702         }
4703         if (ret < 0 && !add) {
4704                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4705                             filter->ether_type);
4706                 return -ENOENT;
4707         }
4708
4709         if (add) {
4710                 etqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;
4711                 etqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);
4712                 etqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;
4713                 ret = igb_ethertype_filter_insert(filter_info,
4714                                 filter->ether_type, etqf);
4715                 if (ret < 0) {
4716                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4717                         return -ENOSYS;
4718                 }
4719         } else {
4720                 ret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);
4721                 if (ret < 0)
4722                         return -ENOSYS;
4723         }
4724         E1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);
4725         E1000_WRITE_FLUSH(hw);
4726
4727         return 0;
4728 }
4729
4730 static int
4731 igb_get_ethertype_filter(struct rte_eth_dev *dev,
4732                         struct rte_eth_ethertype_filter *filter)
4733 {
4734         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         struct e1000_filter_info *filter_info =
4736                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4737         uint32_t etqf;
4738         int ret;
4739
4740         ret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);
4741         if (ret < 0) {
4742                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4743                             filter->ether_type);
4744                 return -ENOENT;
4745         }
4746
4747         etqf = E1000_READ_REG(hw, E1000_ETQF(ret));
4748         if (etqf & E1000_ETQF_FILTER_ENABLE) {
4749                 filter->ether_type = etqf & E1000_ETQF_ETHERTYPE;
4750                 filter->flags = 0;
4751                 filter->queue = (etqf & E1000_ETQF_QUEUE) >>
4752                                 E1000_ETQF_QUEUE_SHIFT;
4753                 return 0;
4754         }
4755
4756         return -ENOENT;
4757 }
4758
4759 /*
4760  * igb_ethertype_filter_handle - Handle operations for ethertype filter.
4761  * @dev: pointer to rte_eth_dev structure
4762  * @filter_op:operation will be taken.
4763  * @arg: a pointer to specific structure corresponding to the filter_op
4764  */
4765 static int
4766 igb_ethertype_filter_handle(struct rte_eth_dev *dev,
4767                                 enum rte_filter_op filter_op,
4768                                 void *arg)
4769 {
4770         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4771         int ret;
4772
4773         MAC_TYPE_FILTER_SUP(hw->mac.type);
4774
4775         if (filter_op == RTE_ETH_FILTER_NOP)
4776                 return 0;
4777
4778         if (arg == NULL) {
4779                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4780                             filter_op);
4781                 return -EINVAL;
4782         }
4783
4784         switch (filter_op) {
4785         case RTE_ETH_FILTER_ADD:
4786                 ret = igb_add_del_ethertype_filter(dev,
4787                         (struct rte_eth_ethertype_filter *)arg,
4788                         TRUE);
4789                 break;
4790         case RTE_ETH_FILTER_DELETE:
4791                 ret = igb_add_del_ethertype_filter(dev,
4792                         (struct rte_eth_ethertype_filter *)arg,
4793                         FALSE);
4794                 break;
4795         case RTE_ETH_FILTER_GET:
4796                 ret = igb_get_ethertype_filter(dev,
4797                         (struct rte_eth_ethertype_filter *)arg);
4798                 break;
4799         default:
4800                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4801                 ret = -EINVAL;
4802                 break;
4803         }
4804         return ret;
4805 }
4806
4807 static int
4808 eth_igb_filter_ctrl(struct rte_eth_dev *dev,
4809                      enum rte_filter_type filter_type,
4810                      enum rte_filter_op filter_op,
4811                      void *arg)
4812 {
4813         int ret = -EINVAL;
4814
4815         switch (filter_type) {
4816         case RTE_ETH_FILTER_NTUPLE:
4817                 ret = igb_ntuple_filter_handle(dev, filter_op, arg);
4818                 break;
4819         case RTE_ETH_FILTER_ETHERTYPE:
4820                 ret = igb_ethertype_filter_handle(dev, filter_op, arg);
4821                 break;
4822         case RTE_ETH_FILTER_SYN:
4823                 ret = eth_igb_syn_filter_handle(dev, filter_op, arg);
4824                 break;
4825         case RTE_ETH_FILTER_FLEXIBLE:
4826                 ret = eth_igb_flex_filter_handle(dev, filter_op, arg);
4827                 break;
4828         default:
4829                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4830                                                         filter_type);
4831                 break;
4832         }
4833
4834         return ret;
4835 }
4836
4837 static int
4838 eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
4839                          struct ether_addr *mc_addr_set,
4840                          uint32_t nb_mc_addr)
4841 {
4842         struct e1000_hw *hw;
4843
4844         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
4846         return 0;
4847 }
4848
4849 static uint64_t
4850 igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
4851 {
4852         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         uint64_t systime_cycles;
4854
4855         switch (hw->mac.type) {
4856         case e1000_i210:
4857         case e1000_i211:
4858                 /*
4859                  * Need to read System Time Residue Register to be able
4860                  * to read the other two registers.
4861                  */
4862                 E1000_READ_REG(hw, E1000_SYSTIMR);
4863                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
4864                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4865                 systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4866                                 * NSEC_PER_SEC;
4867                 break;
4868         case e1000_82580:
4869         case e1000_i350:
4870         case e1000_i354:
4871                 /*
4872                  * Need to read System Time Residue Register to be able
4873                  * to read the other two registers.
4874                  */
4875                 E1000_READ_REG(hw, E1000_SYSTIMR);
4876                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4877                 /* Only the 8 LSB are valid. */
4878                 systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
4879                                 & 0xff) << 32;
4880                 break;
4881         default:
4882                 systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
4883                 systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
4884                                 << 32;
4885                 break;
4886         }
4887
4888         return systime_cycles;
4889 }
4890
4891 static uint64_t
4892 igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4893 {
4894         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4895         uint64_t rx_tstamp_cycles;
4896
4897         switch (hw->mac.type) {
4898         case e1000_i210:
4899         case e1000_i211:
4900                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4901                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4902                 rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4903                                 * NSEC_PER_SEC;
4904                 break;
4905         case e1000_82580:
4906         case e1000_i350:
4907         case e1000_i354:
4908                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4909                 /* Only the 8 LSB are valid. */
4910                 rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
4911                                 & 0xff) << 32;
4912                 break;
4913         default:
4914                 rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
4915                 rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
4916                                 << 32;
4917                 break;
4918         }
4919
4920         return rx_tstamp_cycles;
4921 }
4922
4923 static uint64_t
4924 igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4925 {
4926         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4927         uint64_t tx_tstamp_cycles;
4928
4929         switch (hw->mac.type) {
4930         case e1000_i210:
4931         case e1000_i211:
4932                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
4933                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4934                 tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4935                                 * NSEC_PER_SEC;
4936                 break;
4937         case e1000_82580:
4938         case e1000_i350:
4939         case e1000_i354:
4940                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4941                 /* Only the 8 LSB are valid. */
4942                 tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
4943                                 & 0xff) << 32;
4944                 break;
4945         default:
4946                 tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
4947                 tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
4948                                 << 32;
4949                 break;
4950         }
4951
4952         return tx_tstamp_cycles;
4953 }
4954
4955 static void
4956 igb_start_timecounters(struct rte_eth_dev *dev)
4957 {
4958         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4959         struct e1000_adapter *adapter =
4960                 (struct e1000_adapter *)dev->data->dev_private;
4961         uint32_t incval = 1;
4962         uint32_t shift = 0;
4963         uint64_t mask = E1000_CYCLECOUNTER_MASK;
4964
4965         switch (hw->mac.type) {
4966         case e1000_82580:
4967         case e1000_i350:
4968         case e1000_i354:
4969                 /* 32 LSB bits + 8 MSB bits = 40 bits */
4970                 mask = (1ULL << 40) - 1;
4971                 /* fall-through */
4972         case e1000_i210:
4973         case e1000_i211:
4974                 /*
4975                  * Start incrementing the register
4976                  * used to timestamp PTP packets.
4977                  */
4978                 E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
4979                 break;
4980         case e1000_82576:
4981                 incval = E1000_INCVALUE_82576;
4982                 shift = IGB_82576_TSYNC_SHIFT;
4983                 E1000_WRITE_REG(hw, E1000_TIMINCA,
4984                                 E1000_INCPERIOD_82576 | incval);
4985                 break;
4986         default:
4987                 /* Not supported */
4988                 return;
4989         }
4990
4991         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4992         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4993         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4994
4995         adapter->systime_tc.cc_mask = mask;
4996         adapter->systime_tc.cc_shift = shift;
4997         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4998
4999         adapter->rx_tstamp_tc.cc_mask = mask;
5000         adapter->rx_tstamp_tc.cc_shift = shift;
5001         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5002
5003         adapter->tx_tstamp_tc.cc_mask = mask;
5004         adapter->tx_tstamp_tc.cc_shift = shift;
5005         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5006 }
5007
5008 static int
5009 igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5010 {
5011         struct e1000_adapter *adapter =
5012                         (struct e1000_adapter *)dev->data->dev_private;
5013
5014         adapter->systime_tc.nsec += delta;
5015         adapter->rx_tstamp_tc.nsec += delta;
5016         adapter->tx_tstamp_tc.nsec += delta;
5017
5018         return 0;
5019 }
5020
5021 static int
5022 igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5023 {
5024         uint64_t ns;
5025         struct e1000_adapter *adapter =
5026                         (struct e1000_adapter *)dev->data->dev_private;
5027
5028         ns = rte_timespec_to_ns(ts);
5029
5030         /* Set the timecounters to a new value. */
5031         adapter->systime_tc.nsec = ns;
5032         adapter->rx_tstamp_tc.nsec = ns;
5033         adapter->tx_tstamp_tc.nsec = ns;
5034
5035         return 0;
5036 }
5037
5038 static int
5039 igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5040 {
5041         uint64_t ns, systime_cycles;
5042         struct e1000_adapter *adapter =
5043                         (struct e1000_adapter *)dev->data->dev_private;
5044
5045         systime_cycles = igb_read_systime_cyclecounter(dev);
5046         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5047         *ts = rte_ns_to_timespec(ns);
5048
5049         return 0;
5050 }
5051
5052 static int
5053 igb_timesync_enable(struct rte_eth_dev *dev)
5054 {
5055         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056         uint32_t tsync_ctl;
5057         uint32_t tsauxc;
5058
5059         /* Stop the timesync system time. */
5060         E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
5061         /* Reset the timesync system time value. */
5062         switch (hw->mac.type) {
5063         case e1000_82580:
5064         case e1000_i350:
5065         case e1000_i354:
5066         case e1000_i210:
5067         case e1000_i211:
5068                 E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
5069                 /* fall-through */
5070         case e1000_82576:
5071                 E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
5072                 E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
5073                 break;
5074         default:
5075                 /* Not supported. */
5076                 return -ENOTSUP;
5077         }
5078
5079         /* Enable system time for it isn't on by default. */
5080         tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
5081         tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
5082         E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
5083
5084         igb_start_timecounters(dev);
5085
5086         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5087         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
5088                         (ETHER_TYPE_1588 |
5089                          E1000_ETQF_FILTER_ENABLE |
5090                          E1000_ETQF_1588));
5091
5092         /* Enable timestamping of received PTP packets. */
5093         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5094         tsync_ctl |= E1000_TSYNCRXCTL_ENABLED;
5095         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5096
5097         /* Enable Timestamping of transmitted PTP packets. */
5098         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5099         tsync_ctl |= E1000_TSYNCTXCTL_ENABLED;
5100         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5101
5102         return 0;
5103 }
5104
5105 static int
5106 igb_timesync_disable(struct rte_eth_dev *dev)
5107 {
5108         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint32_t tsync_ctl;
5110
5111         /* Disable timestamping of transmitted PTP packets. */
5112         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5113         tsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;
5114         E1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);
5115
5116         /* Disable timestamping of received PTP packets. */
5117         tsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5118         tsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;
5119         E1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);
5120
5121         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5122         E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);
5123
5124         /* Stop incrementating the System Time registers. */
5125         E1000_WRITE_REG(hw, E1000_TIMINCA, 0);
5126
5127         return 0;
5128 }
5129
5130 static int
5131 igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5132                                struct timespec *timestamp,
5133                                uint32_t flags __rte_unused)
5134 {
5135         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136         struct e1000_adapter *adapter =
5137                         (struct e1000_adapter *)dev->data->dev_private;
5138         uint32_t tsync_rxctl;
5139         uint64_t rx_tstamp_cycles;
5140         uint64_t ns;
5141
5142         tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
5143         if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
5144                 return -EINVAL;
5145
5146         rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
5147         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5148         *timestamp = rte_ns_to_timespec(ns);
5149
5150         return  0;
5151 }
5152
5153 static int
5154 igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5155                                struct timespec *timestamp)
5156 {
5157         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5158         struct e1000_adapter *adapter =
5159                         (struct e1000_adapter *)dev->data->dev_private;
5160         uint32_t tsync_txctl;
5161         uint64_t tx_tstamp_cycles;
5162         uint64_t ns;
5163
5164         tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
5165         if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
5166                 return -EINVAL;
5167
5168         tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
5169         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5170         *timestamp = rte_ns_to_timespec(ns);
5171
5172         return  0;
5173 }
5174
5175 static int
5176 eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5177 {
5178         int count = 0;
5179         int g_ind = 0;
5180         const struct reg_info *reg_group;
5181
5182         while ((reg_group = igb_regs[g_ind++]))
5183                 count += igb_reg_group_count(reg_group);
5184
5185         return count;
5186 }
5187
5188 static int
5189 igbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5190 {
5191         int count = 0;
5192         int g_ind = 0;
5193         const struct reg_info *reg_group;
5194
5195         while ((reg_group = igbvf_regs[g_ind++]))
5196                 count += igb_reg_group_count(reg_group);
5197
5198         return count;
5199 }
5200
5201 static int
5202 eth_igb_get_regs(struct rte_eth_dev *dev,
5203         struct rte_dev_reg_info *regs)
5204 {
5205         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5206         uint32_t *data = regs->data;
5207         int g_ind = 0;
5208         int count = 0;
5209         const struct reg_info *reg_group;
5210
5211         if (data == NULL) {
5212                 regs->length = eth_igb_get_reg_length(dev);
5213                 regs->width = sizeof(uint32_t);
5214                 return 0;
5215         }
5216
5217         /* Support only full register dump */
5218         if ((regs->length == 0) ||
5219             (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {
5220                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5221                         hw->device_id;
5222                 while ((reg_group = igb_regs[g_ind++]))
5223                         count += igb_read_regs_group(dev, &data[count],
5224                                                         reg_group);
5225                 return 0;
5226         }
5227
5228         return -ENOTSUP;
5229 }
5230
5231 static int
5232 igbvf_get_regs(struct rte_eth_dev *dev,
5233         struct rte_dev_reg_info *regs)
5234 {
5235         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236         uint32_t *data = regs->data;
5237         int g_ind = 0;
5238         int count = 0;
5239         const struct reg_info *reg_group;
5240
5241         if (data == NULL) {
5242                 regs->length = igbvf_get_reg_length(dev);
5243                 regs->width = sizeof(uint32_t);
5244                 return 0;
5245         }
5246
5247         /* Support only full register dump */
5248         if ((regs->length == 0) ||
5249             (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {
5250                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5251                         hw->device_id;
5252                 while ((reg_group = igbvf_regs[g_ind++]))
5253                         count += igb_read_regs_group(dev, &data[count],
5254                                                         reg_group);
5255                 return 0;
5256         }
5257
5258         return -ENOTSUP;
5259 }
5260
5261 static int
5262 eth_igb_get_eeprom_length(struct rte_eth_dev *dev)
5263 {
5264         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265
5266         /* Return unit is byte count */
5267         return hw->nvm.word_size * 2;
5268 }
5269
5270 static int
5271 eth_igb_get_eeprom(struct rte_eth_dev *dev,
5272         struct rte_dev_eeprom_info *in_eeprom)
5273 {
5274         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5275         struct e1000_nvm_info *nvm = &hw->nvm;
5276         uint16_t *data = in_eeprom->data;
5277         int first, length;
5278
5279         first = in_eeprom->offset >> 1;
5280         length = in_eeprom->length >> 1;
5281         if ((first >= hw->nvm.word_size) ||
5282             ((first + length) >= hw->nvm.word_size))
5283                 return -EINVAL;
5284
5285         in_eeprom->magic = hw->vendor_id |
5286                 ((uint32_t)hw->device_id << 16);
5287
5288         if ((nvm->ops.read) == NULL)
5289                 return -ENOTSUP;
5290
5291         return nvm->ops.read(hw, first, length, data);
5292 }
5293
5294 static int
5295 eth_igb_set_eeprom(struct rte_eth_dev *dev,
5296         struct rte_dev_eeprom_info *in_eeprom)
5297 {
5298         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299         struct e1000_nvm_info *nvm = &hw->nvm;
5300         uint16_t *data = in_eeprom->data;
5301         int first, length;
5302
5303         first = in_eeprom->offset >> 1;
5304         length = in_eeprom->length >> 1;
5305         if ((first >= hw->nvm.word_size) ||
5306             ((first + length) >= hw->nvm.word_size))
5307                 return -EINVAL;
5308
5309         in_eeprom->magic = (uint32_t)hw->vendor_id |
5310                 ((uint32_t)hw->device_id << 16);
5311
5312         if ((nvm->ops.write) == NULL)
5313                 return -ENOTSUP;
5314         return nvm->ops.write(hw,  first, length, data);
5315 }
5316
5317 static int
5318 eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5319 {
5320         struct e1000_hw *hw =
5321                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5322         uint32_t mask = 1 << queue_id;
5323
5324         E1000_WRITE_REG(hw, E1000_EIMC, mask);
5325         E1000_WRITE_FLUSH(hw);
5326
5327         return 0;
5328 }
5329
5330 static int
5331 eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5332 {
5333         struct e1000_hw *hw =
5334                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5336         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5337         uint32_t mask = 1 << queue_id;
5338         uint32_t regval;
5339
5340         regval = E1000_READ_REG(hw, E1000_EIMS);
5341         E1000_WRITE_REG(hw, E1000_EIMS, regval | mask);
5342         E1000_WRITE_FLUSH(hw);
5343
5344         rte_intr_enable(intr_handle);
5345
5346         return 0;
5347 }
5348
5349 static void
5350 eth_igb_write_ivar(struct e1000_hw *hw, uint8_t  msix_vector,
5351                    uint8_t index, uint8_t offset)
5352 {
5353         uint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
5354
5355         /* clear bits */
5356         val &= ~((uint32_t)0xFF << offset);
5357
5358         /* write vector and valid bit */
5359         val |= (msix_vector | E1000_IVAR_VALID) << offset;
5360
5361         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);
5362 }
5363
5364 static void
5365 eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
5366                            uint8_t queue, uint8_t msix_vector)
5367 {
5368         uint32_t tmp = 0;
5369
5370         if (hw->mac.type == e1000_82575) {
5371                 if (direction == 0)
5372                         tmp = E1000_EICR_RX_QUEUE0 << queue;
5373                 else if (direction == 1)
5374                         tmp = E1000_EICR_TX_QUEUE0 << queue;
5375                 E1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);
5376         } else if (hw->mac.type == e1000_82576) {
5377                 if ((direction == 0) || (direction == 1))
5378                         eth_igb_write_ivar(hw, msix_vector, queue & 0x7,
5379                                            ((queue & 0x8) << 1) +
5380                                            8 * direction);
5381         } else if ((hw->mac.type == e1000_82580) ||
5382                         (hw->mac.type == e1000_i350) ||
5383                         (hw->mac.type == e1000_i354) ||
5384                         (hw->mac.type == e1000_i210) ||
5385                         (hw->mac.type == e1000_i211)) {
5386                 if ((direction == 0) || (direction == 1))
5387                         eth_igb_write_ivar(hw, msix_vector,
5388                                            queue >> 1,
5389                                            ((queue & 0x1) << 4) +
5390                                            8 * direction);
5391         }
5392 }
5393
5394 /* Sets up the hardware to generate MSI-X interrupts properly
5395  * @hw
5396  *  board private structure
5397  */
5398 static void
5399 eth_igb_configure_msix_intr(struct rte_eth_dev *dev)
5400 {
5401         int queue_id;
5402         uint32_t tmpval, regval, intr_mask;
5403         struct e1000_hw *hw =
5404                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         uint32_t vec = E1000_MISC_VEC_ID;
5406         uint32_t base = E1000_MISC_VEC_ID;
5407         uint32_t misc_shift = 0;
5408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5410
5411         /* won't configure msix register if no mapping is done
5412          * between intr vector and event fd
5413          */
5414         if (!rte_intr_dp_is_en(intr_handle))
5415                 return;
5416
5417         if (rte_intr_allow_others(intr_handle)) {
5418                 vec = base = E1000_RX_VEC_START;
5419                 misc_shift = 1;
5420         }
5421
5422         /* set interrupt vector for other causes */
5423         if (hw->mac.type == e1000_82575) {
5424                 tmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);
5425                 /* enable MSI-X PBA support */
5426                 tmpval |= E1000_CTRL_EXT_PBA_CLR;
5427
5428                 /* Auto-Mask interrupts upon ICR read */
5429                 tmpval |= E1000_CTRL_EXT_EIAME;
5430                 tmpval |= E1000_CTRL_EXT_IRCA;
5431
5432                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);
5433
5434                 /* enable msix_other interrupt */
5435                 E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);
5436                 regval = E1000_READ_REG(hw, E1000_EIAC);
5437                 E1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);
5438                 regval = E1000_READ_REG(hw, E1000_EIAM);
5439                 E1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);
5440         } else if ((hw->mac.type == e1000_82576) ||
5441                         (hw->mac.type == e1000_82580) ||
5442                         (hw->mac.type == e1000_i350) ||
5443                         (hw->mac.type == e1000_i354) ||
5444                         (hw->mac.type == e1000_i210) ||
5445                         (hw->mac.type == e1000_i211)) {
5446                 /* turn on MSI-X capability first */
5447                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |
5448                                         E1000_GPIE_PBA | E1000_GPIE_EIAME |
5449                                         E1000_GPIE_NSICR);
5450                 intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5451                         misc_shift;
5452                 regval = E1000_READ_REG(hw, E1000_EIAC);
5453                 E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);
5454
5455                 /* enable msix_other interrupt */
5456                 regval = E1000_READ_REG(hw, E1000_EIMS);
5457                 E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);
5458                 tmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;
5459                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);
5460         }
5461
5462         /* use EIAM to auto-mask when MSI-X interrupt
5463          * is asserted, this saves a register write for every interrupt
5464          */
5465         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
5466                 misc_shift;
5467         regval = E1000_READ_REG(hw, E1000_EIAM);
5468         E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);
5469
5470         for (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {
5471                 eth_igb_assign_msix_vector(hw, 0, queue_id, vec);
5472                 intr_handle->intr_vec[queue_id] = vec;
5473                 if (vec < base + intr_handle->nb_efd - 1)
5474                         vec++;
5475         }
5476
5477         E1000_WRITE_FLUSH(hw);
5478 }
5479
5480 /* restore n-tuple filter */
5481 static inline void
5482 igb_ntuple_filter_restore(struct rte_eth_dev *dev)
5483 {
5484         struct e1000_filter_info *filter_info =
5485                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5486         struct e1000_5tuple_filter *p_5tuple;
5487         struct e1000_2tuple_filter *p_2tuple;
5488
5489         TAILQ_FOREACH(p_5tuple, &filter_info->fivetuple_list, entries) {
5490                 igb_inject_5tuple_filter_82576(dev, p_5tuple);
5491         }
5492
5493         TAILQ_FOREACH(p_2tuple, &filter_info->twotuple_list, entries) {
5494                 igb_inject_2uple_filter(dev, p_2tuple);
5495         }
5496 }
5497
5498 /* restore SYN filter */
5499 static inline void
5500 igb_syn_filter_restore(struct rte_eth_dev *dev)
5501 {
5502         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503         struct e1000_filter_info *filter_info =
5504                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5505         uint32_t synqf;
5506
5507         synqf = filter_info->syn_info;
5508
5509         if (synqf & E1000_SYN_FILTER_ENABLE) {
5510                 E1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);
5511                 E1000_WRITE_FLUSH(hw);
5512         }
5513 }
5514
5515 /* restore ethernet type filter */
5516 static inline void
5517 igb_ethertype_filter_restore(struct rte_eth_dev *dev)
5518 {
5519         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5520         struct e1000_filter_info *filter_info =
5521                 E1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5522         int i;
5523
5524         for (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {
5525                 if (filter_info->ethertype_mask & (1 << i)) {
5526                         E1000_WRITE_REG(hw, E1000_ETQF(i),
5527                                 filter_info->ethertype_filters[i].etqf);
5528                         E1000_WRITE_FLUSH(hw);
5529                 }
5530         }
5531 }
5532
5533 /* restore all types filter */
5534 static int
5535 igb_filter_restore(struct rte_eth_dev *dev)
5536 {
5537         igb_ntuple_filter_restore(dev);
5538         igb_ethertype_filter_restore(dev);
5539         igb_syn_filter_restore(dev);
5540
5541         return 0;
5542 }
5543
5544 RTE_PMD_REGISTER_PCI(net_e1000_igb, rte_igb_pmd);
5545 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb, pci_id_igb_map);
5546 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb, "* igb_uio | uio_pci_generic | vfio-pci");
5547 RTE_PMD_REGISTER_PCI(net_e1000_igb_vf, rte_igbvf_pmd);
5548 RTE_PMD_REGISTER_PCI_TABLE(net_e1000_igb_vf, pci_id_igbvf_map);
5549 RTE_PMD_REGISTER_KMOD_DEP(net_e1000_igb_vf, "* igb_uio | vfio-pci");