drivers/net/e1000/igb_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35
  36 #include <stdio.h>
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <errno.h>
  40 #include <stdint.h>
  41 #include <stdarg.h>
  42 #include <inttypes.h>
  43
  44 #include <rte_interrupts.h>
  45 #include <rte_byteorder.h>
  46 #include <rte_common.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_memory.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_memzone.h>
  53 #include <rte_launch.h>
  54 #include <rte_eal.h>
  55 #include <rte_per_lcore.h>
  56 #include <rte_lcore.h>
  57 #include <rte_atomic.h>
  58 #include <rte_branch_prediction.h>
  59 #include <rte_mempool.h>
  60 #include <rte_malloc.h>
  61 #include <rte_mbuf.h>
  62 #include <rte_ether.h>
  63 #include <rte_ethdev.h>
  64 #include <rte_prefetch.h>
  65 #include <rte_udp.h>
  66 #include <rte_tcp.h>
  67 #include <rte_sctp.h>
  68 #include <rte_net.h>
  69 #include <rte_string_fns.h>
  70
  71 #include "e1000_logs.h"
  72 #include "base/e1000_api.h"
  73 #include "e1000_ethdev.h"
  74
  75 #ifdef RTE_LIBRTE_IEEE1588
  76 #define IGB_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  77 #else
  78 #define IGB_TX_IEEE1588_TMST 0
  79 #endif
  80 /* Bit Mask to indicate what bits required for building TX context */
  81 #define IGB_TX_OFFLOAD_MASK (                    \
  82                 PKT_TX_VLAN_PKT |                \
  83                 PKT_TX_IP_CKSUM |                \
  84                 PKT_TX_L4_MASK |                 \
  85                 PKT_TX_TCP_SEG |                 \
  86                 IGB_TX_IEEE1588_TMST)
  87
  88 #define IGB_TX_OFFLOAD_NOTSUP_MASK \
  89                 (PKT_TX_OFFLOAD_MASK ^ IGB_TX_OFFLOAD_MASK)
  90
  91 /**
  92  * Structure associated with each descriptor of the RX ring of a RX queue.
  93  */
  94 struct igb_rx_entry {
  95         struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
  96 };
  97
  98 /**
  99  * Structure associated with each descriptor of the TX ring of a TX queue.
 100  */
 101 struct igb_tx_entry {
 102         struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
 103         uint16_t next_id; /**< Index of next descriptor in ring. */
 104         uint16_t last_id; /**< Index of last scattered descriptor. */
 105 };
 106
 107 /**
 108  * Structure associated with each RX queue.
 109  */
 110 struct igb_rx_queue {
 111         struct rte_mempool  *mb_pool;   /**< mbuf pool to populate RX ring. */
 112         volatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
 113         uint64_t            rx_ring_phys_addr; /**< RX ring DMA address. */
 114         volatile uint32_t   *rdt_reg_addr; /**< RDT register address. */
 115         volatile uint32_t   *rdh_reg_addr; /**< RDH register address. */
 116         struct igb_rx_entry *sw_ring;   /**< address of RX software ring. */
 117         struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
 118         struct rte_mbuf *pkt_last_seg;  /**< Last segment of current packet. */
 119         uint16_t            nb_rx_desc; /**< number of RX descriptors. */
 120         uint16_t            rx_tail;    /**< current value of RDT register. */
 121         uint16_t            nb_rx_hold; /**< number of held free RX desc. */
 122         uint16_t            rx_free_thresh; /**< max free RX desc to hold. */
 123         uint16_t            queue_id;   /**< RX queue index. */
 124         uint16_t            reg_idx;    /**< RX queue register index. */
 125         uint8_t             port_id;    /**< Device port identifier. */
 126         uint8_t             pthresh;    /**< Prefetch threshold register. */
 127         uint8_t             hthresh;    /**< Host threshold register. */
 128         uint8_t             wthresh;    /**< Write-back threshold register. */
 129         uint8_t             crc_len;    /**< 0 if CRC stripped, 4 otherwise. */
 130         uint8_t             drop_en;  /**< If not 0, set SRRCTL.Drop_En. */
 131 };
 132
 133 /**
 134  * Hardware context number
 135  */
 136 enum igb_advctx_num {
 137         IGB_CTX_0    = 0, /**< CTX0    */
 138         IGB_CTX_1    = 1, /**< CTX1    */
 139         IGB_CTX_NUM  = 2, /**< CTX_NUM */
 140 };
 141
 142 /** Offload features */
 143 union igb_tx_offload {
 144         uint64_t data;
 145         struct {
 146                 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
 147                 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
 148                 uint64_t vlan_tci:16;  /**< VLAN Tag Control Identifier(CPU order). */
 149                 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
 150                 uint64_t tso_segsz:16; /**< TCP TSO segment size. */
 151
 152                 /* uint64_t unused:8; */
 153         };
 154 };
 155
 156 /*
 157  * Compare mask for igb_tx_offload.data,
 158  * should be in sync with igb_tx_offload layout.
 159  * */
 160 #define TX_MACIP_LEN_CMP_MASK   0x000000000000FFFFULL /**< L2L3 header mask. */
 161 #define TX_VLAN_CMP_MASK                0x00000000FFFF0000ULL /**< Vlan mask. */
 162 #define TX_TCP_LEN_CMP_MASK             0x000000FF00000000ULL /**< TCP header mask. */
 163 #define TX_TSO_MSS_CMP_MASK             0x00FFFF0000000000ULL /**< TSO segsz mask. */
 164 /** Mac + IP + TCP + Mss mask. */
 165 #define TX_TSO_CMP_MASK \
 166         (TX_MACIP_LEN_CMP_MASK | TX_TCP_LEN_CMP_MASK | TX_TSO_MSS_CMP_MASK)
 167
 168 /**
 169  * Strucutre to check if new context need be built
 170  */
 171 struct igb_advctx_info {
 172         uint64_t flags;           /**< ol_flags related to context build. */
 173         /** tx offload: vlan, tso, l2-l3-l4 lengths. */
 174         union igb_tx_offload tx_offload;
 175         /** compare mask for tx offload. */
 176         union igb_tx_offload tx_offload_mask;
 177 };
 178
 179 /**
 180  * Structure associated with each TX queue.
 181  */
 182 struct igb_tx_queue {
 183         volatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */
 184         uint64_t               tx_ring_phys_addr; /**< TX ring DMA address. */
 185         struct igb_tx_entry    *sw_ring; /**< virtual address of SW ring. */
 186         volatile uint32_t      *tdt_reg_addr; /**< Address of TDT register. */
 187         uint32_t               txd_type;      /**< Device-specific TXD type */
 188         uint16_t               nb_tx_desc;    /**< number of TX descriptors. */
 189         uint16_t               tx_tail; /**< Current value of TDT register. */
 190         uint16_t               tx_head;
 191         /**< Index of first used TX descriptor. */
 192         uint16_t               queue_id; /**< TX queue index. */
 193         uint16_t               reg_idx;  /**< TX queue register index. */
 194         uint8_t                port_id;  /**< Device port identifier. */
 195         uint8_t                pthresh;  /**< Prefetch threshold register. */
 196         uint8_t                hthresh;  /**< Host threshold register. */
 197         uint8_t                wthresh;  /**< Write-back threshold register. */
 198         uint32_t               ctx_curr;
 199         /**< Current used hardware descriptor. */
 200         uint32_t               ctx_start;
 201         /**< Start context position for transmit queue. */
 202         struct igb_advctx_info ctx_cache[IGB_CTX_NUM];
 203         /**< Hardware context history.*/
 204 };
 205
 206 #if 1
 207 #define RTE_PMD_USE_PREFETCH
 208 #endif
 209
 210 #ifdef RTE_PMD_USE_PREFETCH
 211 #define rte_igb_prefetch(p)     rte_prefetch0(p)
 212 #else
 213 #define rte_igb_prefetch(p)     do {} while(0)
 214 #endif
 215
 216 #ifdef RTE_PMD_PACKET_PREFETCH
 217 #define rte_packet_prefetch(p) rte_prefetch1(p)
 218 #else
 219 #define rte_packet_prefetch(p)  do {} while(0)
 220 #endif
 221
 222 /*
 223  * Macro for VMDq feature for 1 GbE NIC.
 224  */
 225 #define E1000_VMOLR_SIZE                        (8)
 226 #define IGB_TSO_MAX_HDRLEN                      (512)
 227 #define IGB_TSO_MAX_MSS                         (9216)
 228
 229 /*********************************************************************
 230  *
 231  *  TX function
 232  *
 233  **********************************************************************/
 234
 235 /*
 236  *There're some limitations in hardware for TCP segmentation offload. We
 237  *should check whether the parameters are valid.
 238  */
 239 static inline uint64_t
 240 check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)
 241 {
 242         if (!(ol_req & PKT_TX_TCP_SEG))
 243                 return ol_req;
 244         if ((ol_para.tso_segsz > IGB_TSO_MAX_MSS) || (ol_para.l2_len +
 245                         ol_para.l3_len + ol_para.l4_len > IGB_TSO_MAX_HDRLEN)) {
 246                 ol_req &= ~PKT_TX_TCP_SEG;
 247                 ol_req |= PKT_TX_TCP_CKSUM;
 248         }
 249         return ol_req;
 250 }
 251
 252 /*
 253  * Advanced context descriptor are almost same between igb/ixgbe
 254  * This is a separate function, looking for optimization opportunity here
 255  * Rework required to go with the pre-defined values.
 256  */
 257
 258 static inline void
 259 igbe_set_xmit_ctx(struct igb_tx_queue* txq,
 260                 volatile struct e1000_adv_tx_context_desc *ctx_txd,
 261                 uint64_t ol_flags, union igb_tx_offload tx_offload)
 262 {
 263         uint32_t type_tucmd_mlhl;
 264         uint32_t mss_l4len_idx;
 265         uint32_t ctx_idx, ctx_curr;
 266         uint32_t vlan_macip_lens;
 267         union igb_tx_offload tx_offload_mask;
 268
 269         ctx_curr = txq->ctx_curr;
 270         ctx_idx = ctx_curr + txq->ctx_start;
 271
 272         tx_offload_mask.data = 0;
 273         type_tucmd_mlhl = 0;
 274
 275         /* Specify which HW CTX to upload. */
 276         mss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);
 277
 278         if (ol_flags & PKT_TX_VLAN_PKT)
 279                 tx_offload_mask.data |= TX_VLAN_CMP_MASK;
 280
 281         /* check if TCP segmentation required for this packet */
 282         if (ol_flags & PKT_TX_TCP_SEG) {
 283                 /* implies IP cksum in IPv4 */
 284                 if (ol_flags & PKT_TX_IP_CKSUM)
 285                         type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4 |
 286                                 E1000_ADVTXD_TUCMD_L4T_TCP |
 287                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 288                 else
 289                         type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV6 |
 290                                 E1000_ADVTXD_TUCMD_L4T_TCP |
 291                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 292
 293                 tx_offload_mask.data |= TX_TSO_CMP_MASK;
 294                 mss_l4len_idx |= tx_offload.tso_segsz << E1000_ADVTXD_MSS_SHIFT;
 295                 mss_l4len_idx |= tx_offload.l4_len << E1000_ADVTXD_L4LEN_SHIFT;
 296         } else { /* no TSO, check if hardware checksum is needed */
 297                 if (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))
 298                         tx_offload_mask.data |= TX_MACIP_LEN_CMP_MASK;
 299
 300                 if (ol_flags & PKT_TX_IP_CKSUM)
 301                         type_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;
 302
 303                 switch (ol_flags & PKT_TX_L4_MASK) {
 304                 case PKT_TX_UDP_CKSUM:
 305                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |
 306                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 307                         mss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 308                         break;
 309                 case PKT_TX_TCP_CKSUM:
 310                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |
 311                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 312                         mss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 313                         break;
 314                 case PKT_TX_SCTP_CKSUM:
 315                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |
 316                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 317                         mss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;
 318                         break;
 319                 default:
 320                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |
 321                                 E1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;
 322                         break;
 323                 }
 324         }
 325
 326         txq->ctx_cache[ctx_curr].flags = ol_flags;
 327         txq->ctx_cache[ctx_curr].tx_offload.data =
 328                 tx_offload_mask.data & tx_offload.data;
 329         txq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;
 330
 331         ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
 332         vlan_macip_lens = (uint32_t)tx_offload.data;
 333         ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
 334         ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
 335         ctx_txd->seqnum_seed = 0;
 336 }
 337
 338 /*
 339  * Check which hardware context can be used. Use the existing match
 340  * or create a new context descriptor.
 341  */
 342 static inline uint32_t
 343 what_advctx_update(struct igb_tx_queue *txq, uint64_t flags,
 344                 union igb_tx_offload tx_offload)
 345 {
 346         /* If match with the current context */
 347         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 348                 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
 349                 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
 350                         return txq->ctx_curr;
 351         }
 352
 353         /* If match with the second context */
 354         txq->ctx_curr ^= 1;
 355         if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
 356                 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
 357                 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
 358                         return txq->ctx_curr;
 359         }
 360
 361         /* Mismatch, use the previous context */
 362         return IGB_CTX_NUM;
 363 }
 364
 365 static inline uint32_t
 366 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
 367 {
 368         static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};
 369         static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};
 370         uint32_t tmp;
 371
 372         tmp  = l4_olinfo[(ol_flags & PKT_TX_L4_MASK)  != PKT_TX_L4_NO_CKSUM];
 373         tmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];
 374         tmp |= l4_olinfo[(ol_flags & PKT_TX_TCP_SEG) != 0];
 375         return tmp;
 376 }
 377
 378 static inline uint32_t
 379 tx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)
 380 {
 381         uint32_t cmdtype;
 382         static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};
 383         static uint32_t tso_cmd[2] = {0, E1000_ADVTXD_DCMD_TSE};
 384         cmdtype = vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];
 385         cmdtype |= tso_cmd[(ol_flags & PKT_TX_TCP_SEG) != 0];
 386         return cmdtype;
 387 }
 388
 389 uint16_t
 390 eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 391                uint16_t nb_pkts)
 392 {
 393         struct igb_tx_queue *txq;
 394         struct igb_tx_entry *sw_ring;
 395         struct igb_tx_entry *txe, *txn;
 396         volatile union e1000_adv_tx_desc *txr;
 397         volatile union e1000_adv_tx_desc *txd;
 398         struct rte_mbuf     *tx_pkt;
 399         struct rte_mbuf     *m_seg;
 400         uint64_t buf_dma_addr;
 401         uint32_t olinfo_status;
 402         uint32_t cmd_type_len;
 403         uint32_t pkt_len;
 404         uint16_t slen;
 405         uint64_t ol_flags;
 406         uint16_t tx_end;
 407         uint16_t tx_id;
 408         uint16_t tx_last;
 409         uint16_t nb_tx;
 410         uint64_t tx_ol_req;
 411         uint32_t new_ctx = 0;
 412         uint32_t ctx = 0;
 413         union igb_tx_offload tx_offload = {0};
 414
 415         txq = tx_queue;
 416         sw_ring = txq->sw_ring;
 417         txr     = txq->tx_ring;
 418         tx_id   = txq->tx_tail;
 419         txe = &sw_ring[tx_id];
 420
 421         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
 422                 tx_pkt = *tx_pkts++;
 423                 pkt_len = tx_pkt->pkt_len;
 424
 425                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
 426
 427                 /*
 428                  * The number of descriptors that must be allocated for a
 429                  * packet is the number of segments of that packet, plus 1
 430                  * Context Descriptor for the VLAN Tag Identifier, if any.
 431                  * Determine the last TX descriptor to allocate in the TX ring
 432                  * for the packet, starting from the current position (tx_id)
 433                  * in the ring.
 434                  */
 435                 tx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);
 436
 437                 ol_flags = tx_pkt->ol_flags;
 438                 tx_ol_req = ol_flags & IGB_TX_OFFLOAD_MASK;
 439
 440                 /* If a Context Descriptor need be built . */
 441                 if (tx_ol_req) {
 442                         tx_offload.l2_len = tx_pkt->l2_len;
 443                         tx_offload.l3_len = tx_pkt->l3_len;
 444                         tx_offload.l4_len = tx_pkt->l4_len;
 445                         tx_offload.vlan_tci = tx_pkt->vlan_tci;
 446                         tx_offload.tso_segsz = tx_pkt->tso_segsz;
 447                         tx_ol_req = check_tso_para(tx_ol_req, tx_offload);
 448
 449                         ctx = what_advctx_update(txq, tx_ol_req, tx_offload);
 450                         /* Only allocate context descriptor if required*/
 451                         new_ctx = (ctx == IGB_CTX_NUM);
 452                         ctx = txq->ctx_curr + txq->ctx_start;
 453                         tx_last = (uint16_t) (tx_last + new_ctx);
 454                 }
 455                 if (tx_last >= txq->nb_tx_desc)
 456                         tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
 457
 458                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
 459                            " tx_first=%u tx_last=%u",
 460                            (unsigned) txq->port_id,
 461                            (unsigned) txq->queue_id,
 462                            (unsigned) pkt_len,
 463                            (unsigned) tx_id,
 464                            (unsigned) tx_last);
 465
 466                 /*
 467                  * Check if there are enough free descriptors in the TX ring
 468                  * to transmit the next packet.
 469                  * This operation is based on the two following rules:
 470                  *
 471                  *   1- Only check that the last needed TX descriptor can be
 472                  *      allocated (by construction, if that descriptor is free,
 473                  *      all intermediate ones are also free).
 474                  *
 475                  *      For this purpose, the index of the last TX descriptor
 476                  *      used for a packet (the "last descriptor" of a packet)
 477                  *      is recorded in the TX entries (the last one included)
 478                  *      that are associated with all TX descriptors allocated
 479                  *      for that packet.
 480                  *
 481                  *   2- Avoid to allocate the last free TX descriptor of the
 482                  *      ring, in order to never set the TDT register with the
 483                  *      same value stored in parallel by the NIC in the TDH
 484                  *      register, which makes the TX engine of the NIC enter
 485                  *      in a deadlock situation.
 486                  *
 487                  *      By extension, avoid to allocate a free descriptor that
 488                  *      belongs to the last set of free descriptors allocated
 489                  *      to the same packet previously transmitted.
 490                  */
 491
 492                 /*
 493                  * The "last descriptor" of the previously sent packet, if any,
 494                  * which used the last descriptor to allocate.
 495                  */
 496                 tx_end = sw_ring[tx_last].last_id;
 497
 498                 /*
 499                  * The next descriptor following that "last descriptor" in the
 500                  * ring.
 501                  */
 502                 tx_end = sw_ring[tx_end].next_id;
 503
 504                 /*
 505                  * The "last descriptor" associated with that next descriptor.
 506                  */
 507                 tx_end = sw_ring[tx_end].last_id;
 508
 509                 /*
 510                  * Check that this descriptor is free.
 511                  */
 512                 if (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {
 513                         if (nb_tx == 0)
 514                                 return 0;
 515                         goto end_of_tx;
 516                 }
 517
 518                 /*
 519                  * Set common flags of all TX Data Descriptors.
 520                  *
 521                  * The following bits must be set in all Data Descriptors:
 522                  *   - E1000_ADVTXD_DTYP_DATA
 523                  *   - E1000_ADVTXD_DCMD_DEXT
 524                  *
 525                  * The following bits must be set in the first Data Descriptor
 526                  * and are ignored in the other ones:
 527                  *   - E1000_ADVTXD_DCMD_IFCS
 528                  *   - E1000_ADVTXD_MAC_1588
 529                  *   - E1000_ADVTXD_DCMD_VLE
 530                  *
 531                  * The following bits must only be set in the last Data
 532                  * Descriptor:
 533                  *   - E1000_TXD_CMD_EOP
 534                  *
 535                  * The following bits can be set in any Data Descriptor, but
 536                  * are only set in the last Data Descriptor:
 537                  *   - E1000_TXD_CMD_RS
 538                  */
 539                 cmd_type_len = txq->txd_type |
 540                         E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
 541                 if (tx_ol_req & PKT_TX_TCP_SEG)
 542                         pkt_len -= (tx_pkt->l2_len + tx_pkt->l3_len + tx_pkt->l4_len);
 543                 olinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);
 544 #if defined(RTE_LIBRTE_IEEE1588)
 545                 if (ol_flags & PKT_TX_IEEE1588_TMST)
 546                         cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
 547 #endif
 548                 if (tx_ol_req) {
 549                         /* Setup TX Advanced context descriptor if required */
 550                         if (new_ctx) {
 551                                 volatile struct e1000_adv_tx_context_desc *
 552                                     ctx_txd;
 553
 554                                 ctx_txd = (volatile struct
 555                                     e1000_adv_tx_context_desc *)
 556                                     &txr[tx_id];
 557
 558                                 txn = &sw_ring[txe->next_id];
 559                                 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
 560
 561                                 if (txe->mbuf != NULL) {
 562                                         rte_pktmbuf_free_seg(txe->mbuf);
 563                                         txe->mbuf = NULL;
 564                                 }
 565
 566                                 igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);
 567
 568                                 txe->last_id = tx_last;
 569                                 tx_id = txe->next_id;
 570                                 txe = txn;
 571                         }
 572
 573                         /* Setup the TX Advanced Data Descriptor */
 574                         cmd_type_len  |= tx_desc_vlan_flags_to_cmdtype(tx_ol_req);
 575                         olinfo_status |= tx_desc_cksum_flags_to_olinfo(tx_ol_req);
 576                         olinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);
 577                 }
 578
 579                 m_seg = tx_pkt;
 580                 do {
 581                         txn = &sw_ring[txe->next_id];
 582                         txd = &txr[tx_id];
 583
 584                         if (txe->mbuf != NULL)
 585                                 rte_pktmbuf_free_seg(txe->mbuf);
 586                         txe->mbuf = m_seg;
 587
 588                         /*
 589                          * Set up transmit descriptor.
 590                          */
 591                         slen = (uint16_t) m_seg->data_len;
 592                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
 593                         txd->read.buffer_addr =
 594                                 rte_cpu_to_le_64(buf_dma_addr);
 595                         txd->read.cmd_type_len =
 596                                 rte_cpu_to_le_32(cmd_type_len | slen);
 597                         txd->read.olinfo_status =
 598                                 rte_cpu_to_le_32(olinfo_status);
 599                         txe->last_id = tx_last;
 600                         tx_id = txe->next_id;
 601                         txe = txn;
 602                         m_seg = m_seg->next;
 603                 } while (m_seg != NULL);
 604
 605                 /*
 606                  * The last packet data descriptor needs End Of Packet (EOP)
 607                  * and Report Status (RS).
 608                  */
 609                 txd->read.cmd_type_len |=
 610                         rte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
 611         }
 612  end_of_tx:
 613         rte_wmb();
 614
 615         /*
 616          * Set the Transmit Descriptor Tail (TDT).
 617          */
 618         E1000_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
 619         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
 620                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
 621                    (unsigned) tx_id, (unsigned) nb_tx);
 622         txq->tx_tail = tx_id;
 623
 624         return nb_tx;
 625 }
 626
 627 /*********************************************************************
 628  *
 629  *  TX prep functions
 630  *
 631  **********************************************************************/
 632 uint16_t
 633 eth_igb_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
 634                 uint16_t nb_pkts)
 635 {
 636         int i, ret;
 637         struct rte_mbuf *m;
 638
 639         for (i = 0; i < nb_pkts; i++) {
 640                 m = tx_pkts[i];
 641
 642                 /* Check some limitations for TSO in hardware */
 643                 if (m->ol_flags & PKT_TX_TCP_SEG)
 644                         if ((m->tso_segsz > IGB_TSO_MAX_MSS) ||
 645                                         (m->l2_len + m->l3_len + m->l4_len >
 646                                         IGB_TSO_MAX_HDRLEN)) {
 647                                 rte_errno = -EINVAL;
 648                                 return i;
 649                         }
 650
 651                 if (m->ol_flags & IGB_TX_OFFLOAD_NOTSUP_MASK) {
 652                         rte_errno = -ENOTSUP;
 653                         return i;
 654                 }
 655
 656 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
 657                 ret = rte_validate_tx_offload(m);
 658                 if (ret != 0) {
 659                         rte_errno = ret;
 660                         return i;
 661                 }
 662 #endif
 663                 ret = rte_net_intel_cksum_prepare(m);
 664                 if (ret != 0) {
 665                         rte_errno = ret;
 666                         return i;
 667                 }
 668         }
 669
 670         return i;
 671 }
 672
 673 /*********************************************************************
 674  *
 675  *  RX functions
 676  *
 677  **********************************************************************/
 678 #define IGB_PACKET_TYPE_IPV4              0X01
 679 #define IGB_PACKET_TYPE_IPV4_TCP          0X11
 680 #define IGB_PACKET_TYPE_IPV4_UDP          0X21
 681 #define IGB_PACKET_TYPE_IPV4_SCTP         0X41
 682 #define IGB_PACKET_TYPE_IPV4_EXT          0X03
 683 #define IGB_PACKET_TYPE_IPV4_EXT_SCTP     0X43
 684 #define IGB_PACKET_TYPE_IPV6              0X04
 685 #define IGB_PACKET_TYPE_IPV6_TCP          0X14
 686 #define IGB_PACKET_TYPE_IPV6_UDP          0X24
 687 #define IGB_PACKET_TYPE_IPV6_EXT          0X0C
 688 #define IGB_PACKET_TYPE_IPV6_EXT_TCP      0X1C
 689 #define IGB_PACKET_TYPE_IPV6_EXT_UDP      0X2C
 690 #define IGB_PACKET_TYPE_IPV4_IPV6         0X05
 691 #define IGB_PACKET_TYPE_IPV4_IPV6_TCP     0X15
 692 #define IGB_PACKET_TYPE_IPV4_IPV6_UDP     0X25
 693 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT     0X0D
 694 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
 695 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
 696 #define IGB_PACKET_TYPE_MAX               0X80
 697 #define IGB_PACKET_TYPE_MASK              0X7F
 698 #define IGB_PACKET_TYPE_SHIFT             0X04
 699 static inline uint32_t
 700 igb_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
 701 {
 702         static const uint32_t
 703                 ptype_table[IGB_PACKET_TYPE_MAX] __rte_cache_aligned = {
 704                 [IGB_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
 705                         RTE_PTYPE_L3_IPV4,
 706                 [IGB_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
 707                         RTE_PTYPE_L3_IPV4_EXT,
 708                 [IGB_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
 709                         RTE_PTYPE_L3_IPV6,
 710                 [IGB_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
 711                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 712                         RTE_PTYPE_INNER_L3_IPV6,
 713                 [IGB_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
 714                         RTE_PTYPE_L3_IPV6_EXT,
 715                 [IGB_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
 716                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 717                         RTE_PTYPE_INNER_L3_IPV6_EXT,
 718                 [IGB_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
 719                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 720                 [IGB_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
 721                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 722                 [IGB_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
 723                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 724                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
 725                 [IGB_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
 726                         RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
 727                 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
 728                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 729                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
 730                 [IGB_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
 731                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 732                 [IGB_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
 733                         RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 734                 [IGB_PACKET_TYPE_IPV4_IPV6_UDP] =  RTE_PTYPE_L2_ETHER |
 735                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 736                         RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
 737                 [IGB_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
 738                         RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
 739                 [IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
 740                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
 741                         RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
 742                 [IGB_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
 743                         RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
 744                 [IGB_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
 745                         RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
 746         };
 747         if (unlikely(pkt_info & E1000_RXDADV_PKTTYPE_ETQF))
 748                 return RTE_PTYPE_UNKNOWN;
 749
 750         pkt_info = (pkt_info >> IGB_PACKET_TYPE_SHIFT) & IGB_PACKET_TYPE_MASK;
 751
 752         return ptype_table[pkt_info];
 753 }
 754
 755 static inline uint64_t
 756 rx_desc_hlen_type_rss_to_pkt_flags(struct igb_rx_queue *rxq, uint32_t hl_tp_rs)
 757 {
 758         uint64_t pkt_flags = ((hl_tp_rs & 0x0F) == 0) ?  0 : PKT_RX_RSS_HASH;
 759
 760 #if defined(RTE_LIBRTE_IEEE1588)
 761         static uint32_t ip_pkt_etqf_map[8] = {
 762                 0, 0, 0, PKT_RX_IEEE1588_PTP,
 763                 0, 0, 0, 0,
 764         };
 765
 766         struct rte_eth_dev dev = rte_eth_devices[rxq->port_id];
 767         struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev.data->dev_private);
 768
 769         /* EtherType is in bits 8:10 in Packet Type, and not in the default 0:2 */
 770         if (hw->mac.type == e1000_i210)
 771                 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 12) & 0x07];
 772         else
 773                 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07];
 774 #else
 775         RTE_SET_USED(rxq);
 776 #endif
 777
 778         return pkt_flags;
 779 }
 780
 781 static inline uint64_t
 782 rx_desc_status_to_pkt_flags(uint32_t rx_status)
 783 {
 784         uint64_t pkt_flags;
 785
 786         /* Check if VLAN present */
 787         pkt_flags = ((rx_status & E1000_RXD_STAT_VP) ?
 788                 PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED : 0);
 789
 790 #if defined(RTE_LIBRTE_IEEE1588)
 791         if (rx_status & E1000_RXD_STAT_TMST)
 792                 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
 793 #endif
 794         return pkt_flags;
 795 }
 796
 797 static inline uint64_t
 798 rx_desc_error_to_pkt_flags(uint32_t rx_status)
 799 {
 800         /*
 801          * Bit 30: IPE, IPv4 checksum error
 802          * Bit 29: L4I, L4I integrity error
 803          */
 804
 805         static uint64_t error_to_pkt_flags_map[4] = {
 806                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD,
 807                 PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD,
 808                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD,
 809                 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
 810         };
 811         return error_to_pkt_flags_map[(rx_status >>
 812                 E1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];
 813 }
 814
 815 uint16_t
 816 eth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 817                uint16_t nb_pkts)
 818 {
 819         struct igb_rx_queue *rxq;
 820         volatile union e1000_adv_rx_desc *rx_ring;
 821         volatile union e1000_adv_rx_desc *rxdp;
 822         struct igb_rx_entry *sw_ring;
 823         struct igb_rx_entry *rxe;
 824         struct rte_mbuf *rxm;
 825         struct rte_mbuf *nmb;
 826         union e1000_adv_rx_desc rxd;
 827         uint64_t dma_addr;
 828         uint32_t staterr;
 829         uint32_t hlen_type_rss;
 830         uint16_t pkt_len;
 831         uint16_t rx_id;
 832         uint16_t nb_rx;
 833         uint16_t nb_hold;
 834         uint64_t pkt_flags;
 835
 836         nb_rx = 0;
 837         nb_hold = 0;
 838         rxq = rx_queue;
 839         rx_id = rxq->rx_tail;
 840         rx_ring = rxq->rx_ring;
 841         sw_ring = rxq->sw_ring;
 842         while (nb_rx < nb_pkts) {
 843                 /*
 844                  * The order of operations here is important as the DD status
 845                  * bit must not be read after any other descriptor fields.
 846                  * rx_ring and rxdp are pointing to volatile data so the order
 847                  * of accesses cannot be reordered by the compiler. If they were
 848                  * not volatile, they could be reordered which could lead to
 849                  * using invalid descriptor fields when read from rxd.
 850                  */
 851                 rxdp = &rx_ring[rx_id];
 852                 staterr = rxdp->wb.upper.status_error;
 853                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
 854                         break;
 855                 rxd = *rxdp;
 856
 857                 /*
 858                  * End of packet.
 859                  *
 860                  * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is
 861                  * likely to be invalid and to be dropped by the various
 862                  * validation checks performed by the network stack.
 863                  *
 864                  * Allocate a new mbuf to replenish the RX ring descriptor.
 865                  * If the allocation fails:
 866                  *    - arrange for that RX descriptor to be the first one
 867                  *      being parsed the next time the receive function is
 868                  *      invoked [on the same queue].
 869                  *
 870                  *    - Stop parsing the RX ring and return immediately.
 871                  *
 872                  * This policy do not drop the packet received in the RX
 873                  * descriptor for which the allocation of a new mbuf failed.
 874                  * Thus, it allows that packet to be later retrieved if
 875                  * mbuf have been freed in the mean time.
 876                  * As a side effect, holding RX descriptors instead of
 877                  * systematically giving them back to the NIC may lead to
 878                  * RX ring exhaustion situations.
 879                  * However, the NIC can gracefully prevent such situations
 880                  * to happen by sending specific "back-pressure" flow control
 881                  * frames to its peer(s).
 882                  */
 883                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
 884                            "staterr=0x%x pkt_len=%u",
 885                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 886                            (unsigned) rx_id, (unsigned) staterr,
 887                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
 888
 889                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
 890                 if (nmb == NULL) {
 891                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 892                                    "queue_id=%u", (unsigned) rxq->port_id,
 893                                    (unsigned) rxq->queue_id);
 894                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 895                         break;
 896                 }
 897
 898                 nb_hold++;
 899                 rxe = &sw_ring[rx_id];
 900                 rx_id++;
 901                 if (rx_id == rxq->nb_rx_desc)
 902                         rx_id = 0;
 903
 904                 /* Prefetch next mbuf while processing current one. */
 905                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
 906
 907                 /*
 908                  * When next RX descriptor is on a cache-line boundary,
 909                  * prefetch the next 4 RX descriptors and the next 8 pointers
 910                  * to mbufs.
 911                  */
 912                 if ((rx_id & 0x3) == 0) {
 913                         rte_igb_prefetch(&rx_ring[rx_id]);
 914                         rte_igb_prefetch(&sw_ring[rx_id]);
 915                 }
 916
 917                 rxm = rxe->mbuf;
 918                 rxe->mbuf = nmb;
 919                 dma_addr =
 920                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 921                 rxdp->read.hdr_addr = 0;
 922                 rxdp->read.pkt_addr = dma_addr;
 923
 924                 /*
 925                  * Initialize the returned mbuf.
 926                  * 1) setup generic mbuf fields:
 927                  *    - number of segments,
 928                  *    - next segment,
 929                  *    - packet length,
 930                  *    - RX port identifier.
 931                  * 2) integrate hardware offload data, if any:
 932                  *    - RSS flag & hash,
 933                  *    - IP checksum flag,
 934                  *    - VLAN TCI, if any,
 935                  *    - error flags.
 936                  */
 937                 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
 938                                       rxq->crc_len);
 939                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 940                 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
 941                 rxm->nb_segs = 1;
 942                 rxm->next = NULL;
 943                 rxm->pkt_len = pkt_len;
 944                 rxm->data_len = pkt_len;
 945                 rxm->port = rxq->port_id;
 946
 947                 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
 948                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
 949                 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
 950                 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
 951
 952                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
 953                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
 954                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
 955                 rxm->ol_flags = pkt_flags;
 956                 rxm->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.lower.
 957                                                 lo_dword.hs_rss.pkt_info);
 958
 959                 /*
 960                  * Store the mbuf address into the next entry of the array
 961                  * of returned packets.
 962                  */
 963                 rx_pkts[nb_rx++] = rxm;
 964         }
 965         rxq->rx_tail = rx_id;
 966
 967         /*
 968          * If the number of free RX descriptors is greater than the RX free
 969          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 970          * register.
 971          * Update the RDT with the value of the last processed RX descriptor
 972          * minus 1, to guarantee that the RDT register is never equal to the
 973          * RDH register, which creates a "full" ring situtation from the
 974          * hardware point of view...
 975          */
 976         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
 977         if (nb_hold > rxq->rx_free_thresh) {
 978                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
 979                            "nb_hold=%u nb_rx=%u",
 980                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
 981                            (unsigned) rx_id, (unsigned) nb_hold,
 982                            (unsigned) nb_rx);
 983                 rx_id = (uint16_t) ((rx_id == 0) ?
 984                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
 985                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
 986                 nb_hold = 0;
 987         }
 988         rxq->nb_rx_hold = nb_hold;
 989         return nb_rx;
 990 }
 991
 992 uint16_t
 993 eth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 994                          uint16_t nb_pkts)
 995 {
 996         struct igb_rx_queue *rxq;
 997         volatile union e1000_adv_rx_desc *rx_ring;
 998         volatile union e1000_adv_rx_desc *rxdp;
 999         struct igb_rx_entry *sw_ring;
1000         struct igb_rx_entry *rxe;
1001         struct rte_mbuf *first_seg;
1002         struct rte_mbuf *last_seg;
1003         struct rte_mbuf *rxm;
1004         struct rte_mbuf *nmb;
1005         union e1000_adv_rx_desc rxd;
1006         uint64_t dma; /* Physical address of mbuf data buffer */
1007         uint32_t staterr;
1008         uint32_t hlen_type_rss;
1009         uint16_t rx_id;
1010         uint16_t nb_rx;
1011         uint16_t nb_hold;
1012         uint16_t data_len;
1013         uint64_t pkt_flags;
1014
1015         nb_rx = 0;
1016         nb_hold = 0;
1017         rxq = rx_queue;
1018         rx_id = rxq->rx_tail;
1019         rx_ring = rxq->rx_ring;
1020         sw_ring = rxq->sw_ring;
1021
1022         /*
1023          * Retrieve RX context of current packet, if any.
1024          */
1025         first_seg = rxq->pkt_first_seg;
1026         last_seg = rxq->pkt_last_seg;
1027
1028         while (nb_rx < nb_pkts) {
1029         next_desc:
1030                 /*
1031                  * The order of operations here is important as the DD status
1032                  * bit must not be read after any other descriptor fields.
1033                  * rx_ring and rxdp are pointing to volatile data so the order
1034                  * of accesses cannot be reordered by the compiler. If they were
1035                  * not volatile, they could be reordered which could lead to
1036                  * using invalid descriptor fields when read from rxd.
1037                  */
1038                 rxdp = &rx_ring[rx_id];
1039                 staterr = rxdp->wb.upper.status_error;
1040                 if (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))
1041                         break;
1042                 rxd = *rxdp;
1043
1044                 /*
1045                  * Descriptor done.
1046                  *
1047                  * Allocate a new mbuf to replenish the RX ring descriptor.
1048                  * If the allocation fails:
1049                  *    - arrange for that RX descriptor to be the first one
1050                  *      being parsed the next time the receive function is
1051                  *      invoked [on the same queue].
1052                  *
1053                  *    - Stop parsing the RX ring and return immediately.
1054                  *
1055                  * This policy does not drop the packet received in the RX
1056                  * descriptor for which the allocation of a new mbuf failed.
1057                  * Thus, it allows that packet to be later retrieved if
1058                  * mbuf have been freed in the mean time.
1059                  * As a side effect, holding RX descriptors instead of
1060                  * systematically giving them back to the NIC may lead to
1061                  * RX ring exhaustion situations.
1062                  * However, the NIC can gracefully prevent such situations
1063                  * to happen by sending specific "back-pressure" flow control
1064                  * frames to its peer(s).
1065                  */
1066                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1067                            "staterr=0x%x data_len=%u",
1068                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1069                            (unsigned) rx_id, (unsigned) staterr,
1070                            (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1071
1072                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1073                 if (nmb == NULL) {
1074                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1075                                    "queue_id=%u", (unsigned) rxq->port_id,
1076                                    (unsigned) rxq->queue_id);
1077                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1078                         break;
1079                 }
1080
1081                 nb_hold++;
1082                 rxe = &sw_ring[rx_id];
1083                 rx_id++;
1084                 if (rx_id == rxq->nb_rx_desc)
1085                         rx_id = 0;
1086
1087                 /* Prefetch next mbuf while processing current one. */
1088                 rte_igb_prefetch(sw_ring[rx_id].mbuf);
1089
1090                 /*
1091                  * When next RX descriptor is on a cache-line boundary,
1092                  * prefetch the next 4 RX descriptors and the next 8 pointers
1093                  * to mbufs.
1094                  */
1095                 if ((rx_id & 0x3) == 0) {
1096                         rte_igb_prefetch(&rx_ring[rx_id]);
1097                         rte_igb_prefetch(&sw_ring[rx_id]);
1098                 }
1099
1100                 /*
1101                  * Update RX descriptor with the physical address of the new
1102                  * data buffer of the new allocated mbuf.
1103                  */
1104                 rxm = rxe->mbuf;
1105                 rxe->mbuf = nmb;
1106                 dma = rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
1107                 rxdp->read.pkt_addr = dma;
1108                 rxdp->read.hdr_addr = 0;
1109
1110                 /*
1111                  * Set data length & data buffer address of mbuf.
1112                  */
1113                 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1114                 rxm->data_len = data_len;
1115                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1116
1117                 /*
1118                  * If this is the first buffer of the received packet,
1119                  * set the pointer to the first mbuf of the packet and
1120                  * initialize its context.
1121                  * Otherwise, update the total length and the number of segments
1122                  * of the current scattered packet, and update the pointer to
1123                  * the last mbuf of the current packet.
1124                  */
1125                 if (first_seg == NULL) {
1126                         first_seg = rxm;
1127                         first_seg->pkt_len = data_len;
1128                         first_seg->nb_segs = 1;
1129                 } else {
1130                         first_seg->pkt_len += data_len;
1131                         first_seg->nb_segs++;
1132                         last_seg->next = rxm;
1133                 }
1134
1135                 /*
1136                  * If this is not the last buffer of the received packet,
1137                  * update the pointer to the last mbuf of the current scattered
1138                  * packet and continue to parse the RX ring.
1139                  */
1140                 if (! (staterr & E1000_RXD_STAT_EOP)) {
1141                         last_seg = rxm;
1142                         goto next_desc;
1143                 }
1144
1145                 /*
1146                  * This is the last buffer of the received packet.
1147                  * If the CRC is not stripped by the hardware:
1148                  *   - Subtract the CRC length from the total packet length.
1149                  *   - If the last buffer only contains the whole CRC or a part
1150                  *     of it, free the mbuf associated to the last buffer.
1151                  *     If part of the CRC is also contained in the previous
1152                  *     mbuf, subtract the length of that CRC part from the
1153                  *     data length of the previous mbuf.
1154                  */
1155                 rxm->next = NULL;
1156                 if (unlikely(rxq->crc_len > 0)) {
1157                         first_seg->pkt_len -= ETHER_CRC_LEN;
1158                         if (data_len <= ETHER_CRC_LEN) {
1159                                 rte_pktmbuf_free_seg(rxm);
1160                                 first_seg->nb_segs--;
1161                                 last_seg->data_len = (uint16_t)
1162                                         (last_seg->data_len -
1163                                          (ETHER_CRC_LEN - data_len));
1164                                 last_seg->next = NULL;
1165                         } else
1166                                 rxm->data_len =
1167                                         (uint16_t) (data_len - ETHER_CRC_LEN);
1168                 }
1169
1170                 /*
1171                  * Initialize the first mbuf of the returned packet:
1172                  *    - RX port identifier,
1173                  *    - hardware offload data, if any:
1174                  *      - RSS flag & hash,
1175                  *      - IP checksum flag,
1176                  *      - VLAN TCI, if any,
1177                  *      - error flags.
1178                  */
1179                 first_seg->port = rxq->port_id;
1180                 first_seg->hash.rss = rxd.wb.lower.hi_dword.rss;
1181
1182                 /*
1183                  * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1184                  * set in the pkt_flags field.
1185                  */
1186                 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1187                 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1188                 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(rxq, hlen_type_rss);
1189                 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1190                 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1191                 first_seg->ol_flags = pkt_flags;
1192                 first_seg->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.
1193                                         lower.lo_dword.hs_rss.pkt_info);
1194
1195                 /* Prefetch data of first segment, if configured to do so. */
1196                 rte_packet_prefetch((char *)first_seg->buf_addr +
1197                         first_seg->data_off);
1198
1199                 /*
1200                  * Store the mbuf address into the next entry of the array
1201                  * of returned packets.
1202                  */
1203                 rx_pkts[nb_rx++] = first_seg;
1204
1205                 /*
1206                  * Setup receipt context for a new packet.
1207                  */
1208                 first_seg = NULL;
1209         }
1210
1211         /*
1212          * Record index of the next RX descriptor to probe.
1213          */
1214         rxq->rx_tail = rx_id;
1215
1216         /*
1217          * Save receive context.
1218          */
1219         rxq->pkt_first_seg = first_seg;
1220         rxq->pkt_last_seg = last_seg;
1221
1222         /*
1223          * If the number of free RX descriptors is greater than the RX free
1224          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1225          * register.
1226          * Update the RDT with the value of the last processed RX descriptor
1227          * minus 1, to guarantee that the RDT register is never equal to the
1228          * RDH register, which creates a "full" ring situtation from the
1229          * hardware point of view...
1230          */
1231         nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1232         if (nb_hold > rxq->rx_free_thresh) {
1233                 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1234                            "nb_hold=%u nb_rx=%u",
1235                            (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1236                            (unsigned) rx_id, (unsigned) nb_hold,
1237                            (unsigned) nb_rx);
1238                 rx_id = (uint16_t) ((rx_id == 0) ?
1239                                      (rxq->nb_rx_desc - 1) : (rx_id - 1));
1240                 E1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1241                 nb_hold = 0;
1242         }
1243         rxq->nb_rx_hold = nb_hold;
1244         return nb_rx;
1245 }
1246
1247 /*
1248  * Maximum number of Ring Descriptors.
1249  *
1250  * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring
1251  * desscriptors should meet the following condition:
1252  *      (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1253  */
1254
1255 static void
1256 igb_tx_queue_release_mbufs(struct igb_tx_queue *txq)
1257 {
1258         unsigned i;
1259
1260         if (txq->sw_ring != NULL) {
1261                 for (i = 0; i < txq->nb_tx_desc; i++) {
1262                         if (txq->sw_ring[i].mbuf != NULL) {
1263                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1264                                 txq->sw_ring[i].mbuf = NULL;
1265                         }
1266                 }
1267         }
1268 }
1269
1270 static void
1271 igb_tx_queue_release(struct igb_tx_queue *txq)
1272 {
1273         if (txq != NULL) {
1274                 igb_tx_queue_release_mbufs(txq);
1275                 rte_free(txq->sw_ring);
1276                 rte_free(txq);
1277         }
1278 }
1279
1280 void
1281 eth_igb_tx_queue_release(void *txq)
1282 {
1283         igb_tx_queue_release(txq);
1284 }
1285
1286 static void
1287 igb_reset_tx_queue_stat(struct igb_tx_queue *txq)
1288 {
1289         txq->tx_head = 0;
1290         txq->tx_tail = 0;
1291         txq->ctx_curr = 0;
1292         memset((void*)&txq->ctx_cache, 0,
1293                 IGB_CTX_NUM * sizeof(struct igb_advctx_info));
1294 }
1295
1296 static void
1297 igb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)
1298 {
1299         static const union e1000_adv_tx_desc zeroed_desc = {{0}};
1300         struct igb_tx_entry *txe = txq->sw_ring;
1301         uint16_t i, prev;
1302         struct e1000_hw *hw;
1303
1304         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1305         /* Zero out HW ring memory */
1306         for (i = 0; i < txq->nb_tx_desc; i++) {
1307                 txq->tx_ring[i] = zeroed_desc;
1308         }
1309
1310         /* Initialize ring entries */
1311         prev = (uint16_t)(txq->nb_tx_desc - 1);
1312         for (i = 0; i < txq->nb_tx_desc; i++) {
1313                 volatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);
1314
1315                 txd->wb.status = E1000_TXD_STAT_DD;
1316                 txe[i].mbuf = NULL;
1317                 txe[i].last_id = i;
1318                 txe[prev].next_id = i;
1319                 prev = i;
1320         }
1321
1322         txq->txd_type = E1000_ADVTXD_DTYP_DATA;
1323         /* 82575 specific, each tx queue will use 2 hw contexts */
1324         if (hw->mac.type == e1000_82575)
1325                 txq->ctx_start = txq->queue_id * IGB_CTX_NUM;
1326
1327         igb_reset_tx_queue_stat(txq);
1328 }
1329
1330 int
1331 eth_igb_tx_queue_setup(struct rte_eth_dev *dev,
1332                          uint16_t queue_idx,
1333                          uint16_t nb_desc,
1334                          unsigned int socket_id,
1335                          const struct rte_eth_txconf *tx_conf)
1336 {
1337         const struct rte_memzone *tz;
1338         struct igb_tx_queue *txq;
1339         struct e1000_hw     *hw;
1340         uint32_t size;
1341
1342         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1343
1344         /*
1345          * Validate number of transmit descriptors.
1346          * It must not exceed hardware maximum, and must be multiple
1347          * of E1000_ALIGN.
1348          */
1349         if (nb_desc % IGB_TXD_ALIGN != 0 ||
1350                         (nb_desc > E1000_MAX_RING_DESC) ||
1351                         (nb_desc < E1000_MIN_RING_DESC)) {
1352                 return -EINVAL;
1353         }
1354
1355         /*
1356          * The tx_free_thresh and tx_rs_thresh values are not used in the 1G
1357          * driver.
1358          */
1359         if (tx_conf->tx_free_thresh != 0)
1360                 PMD_INIT_LOG(INFO, "The tx_free_thresh parameter is not "
1361                              "used for the 1G driver.");
1362         if (tx_conf->tx_rs_thresh != 0)
1363                 PMD_INIT_LOG(INFO, "The tx_rs_thresh parameter is not "
1364                              "used for the 1G driver.");
1365         if (tx_conf->tx_thresh.wthresh == 0 && hw->mac.type != e1000_82576)
1366                 PMD_INIT_LOG(INFO, "To improve 1G driver performance, "
1367                              "consider setting the TX WTHRESH value to 4, 8, "
1368                              "or 16.");
1369
1370         /* Free memory prior to re-allocation if needed */
1371         if (dev->data->tx_queues[queue_idx] != NULL) {
1372                 igb_tx_queue_release(dev->data->tx_queues[queue_idx]);
1373                 dev->data->tx_queues[queue_idx] = NULL;
1374         }
1375
1376         /* First allocate the tx queue data structure */
1377         txq = rte_zmalloc("ethdev TX queue", sizeof(struct igb_tx_queue),
1378                                                         RTE_CACHE_LINE_SIZE);
1379         if (txq == NULL)
1380                 return -ENOMEM;
1381
1382         /*
1383          * Allocate TX ring hardware descriptors. A memzone large enough to
1384          * handle the maximum ring size is allocated in order to allow for
1385          * resizing in later calls to the queue setup function.
1386          */
1387         size = sizeof(union e1000_adv_tx_desc) * E1000_MAX_RING_DESC;
1388         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, size,
1389                                       E1000_ALIGN, socket_id);
1390         if (tz == NULL) {
1391                 igb_tx_queue_release(txq);
1392                 return -ENOMEM;
1393         }
1394
1395         txq->nb_tx_desc = nb_desc;
1396         txq->pthresh = tx_conf->tx_thresh.pthresh;
1397         txq->hthresh = tx_conf->tx_thresh.hthresh;
1398         txq->wthresh = tx_conf->tx_thresh.wthresh;
1399         if (txq->wthresh > 0 && hw->mac.type == e1000_82576)
1400                 txq->wthresh = 1;
1401         txq->queue_id = queue_idx;
1402         txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1403                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1404         txq->port_id = dev->data->port_id;
1405
1406         txq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));
1407         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1408
1409         txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;
1410         /* Allocate software ring */
1411         txq->sw_ring = rte_zmalloc("txq->sw_ring",
1412                                    sizeof(struct igb_tx_entry) * nb_desc,
1413                                    RTE_CACHE_LINE_SIZE);
1414         if (txq->sw_ring == NULL) {
1415                 igb_tx_queue_release(txq);
1416                 return -ENOMEM;
1417         }
1418         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1419                      txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1420
1421         igb_reset_tx_queue(txq, dev);
1422         dev->tx_pkt_burst = eth_igb_xmit_pkts;
1423         dev->tx_pkt_prepare = &eth_igb_prep_pkts;
1424         dev->data->tx_queues[queue_idx] = txq;
1425
1426         return 0;
1427 }
1428
1429 static void
1430 igb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)
1431 {
1432         unsigned i;
1433
1434         if (rxq->sw_ring != NULL) {
1435                 for (i = 0; i < rxq->nb_rx_desc; i++) {
1436                         if (rxq->sw_ring[i].mbuf != NULL) {
1437                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1438                                 rxq->sw_ring[i].mbuf = NULL;
1439                         }
1440                 }
1441         }
1442 }
1443
1444 static void
1445 igb_rx_queue_release(struct igb_rx_queue *rxq)
1446 {
1447         if (rxq != NULL) {
1448                 igb_rx_queue_release_mbufs(rxq);
1449                 rte_free(rxq->sw_ring);
1450                 rte_free(rxq);
1451         }
1452 }
1453
1454 void
1455 eth_igb_rx_queue_release(void *rxq)
1456 {
1457         igb_rx_queue_release(rxq);
1458 }
1459
1460 static void
1461 igb_reset_rx_queue(struct igb_rx_queue *rxq)
1462 {
1463         static const union e1000_adv_rx_desc zeroed_desc = {{0}};
1464         unsigned i;
1465
1466         /* Zero out HW ring memory */
1467         for (i = 0; i < rxq->nb_rx_desc; i++) {
1468                 rxq->rx_ring[i] = zeroed_desc;
1469         }
1470
1471         rxq->rx_tail = 0;
1472         rxq->pkt_first_seg = NULL;
1473         rxq->pkt_last_seg = NULL;
1474 }
1475
1476 int
1477 eth_igb_rx_queue_setup(struct rte_eth_dev *dev,
1478                          uint16_t queue_idx,
1479                          uint16_t nb_desc,
1480                          unsigned int socket_id,
1481                          const struct rte_eth_rxconf *rx_conf,
1482                          struct rte_mempool *mp)
1483 {
1484         const struct rte_memzone *rz;
1485         struct igb_rx_queue *rxq;
1486         struct e1000_hw     *hw;
1487         unsigned int size;
1488
1489         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490
1491         /*
1492          * Validate number of receive descriptors.
1493          * It must not exceed hardware maximum, and must be multiple
1494          * of E1000_ALIGN.
1495          */
1496         if (nb_desc % IGB_RXD_ALIGN != 0 ||
1497                         (nb_desc > E1000_MAX_RING_DESC) ||
1498                         (nb_desc < E1000_MIN_RING_DESC)) {
1499                 return -EINVAL;
1500         }
1501
1502         /* Free memory prior to re-allocation if needed */
1503         if (dev->data->rx_queues[queue_idx] != NULL) {
1504                 igb_rx_queue_release(dev->data->rx_queues[queue_idx]);
1505                 dev->data->rx_queues[queue_idx] = NULL;
1506         }
1507
1508         /* First allocate the RX queue data structure. */
1509         rxq = rte_zmalloc("ethdev RX queue", sizeof(struct igb_rx_queue),
1510                           RTE_CACHE_LINE_SIZE);
1511         if (rxq == NULL)
1512                 return -ENOMEM;
1513         rxq->mb_pool = mp;
1514         rxq->nb_rx_desc = nb_desc;
1515         rxq->pthresh = rx_conf->rx_thresh.pthresh;
1516         rxq->hthresh = rx_conf->rx_thresh.hthresh;
1517         rxq->wthresh = rx_conf->rx_thresh.wthresh;
1518         if (rxq->wthresh > 0 &&
1519             (hw->mac.type == e1000_82576 || hw->mac.type == e1000_vfadapt_i350))
1520                 rxq->wthresh = 1;
1521         rxq->drop_en = rx_conf->rx_drop_en;
1522         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1523         rxq->queue_id = queue_idx;
1524         rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1525                 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1526         rxq->port_id = dev->data->port_id;
1527         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
1528                                   ETHER_CRC_LEN);
1529
1530         /*
1531          *  Allocate RX ring hardware descriptors. A memzone large enough to
1532          *  handle the maximum ring size is allocated in order to allow for
1533          *  resizing in later calls to the queue setup function.
1534          */
1535         size = sizeof(union e1000_adv_rx_desc) * E1000_MAX_RING_DESC;
1536         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size,
1537                                       E1000_ALIGN, socket_id);
1538         if (rz == NULL) {
1539                 igb_rx_queue_release(rxq);
1540                 return -ENOMEM;
1541         }
1542         rxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));
1543         rxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));
1544         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1545         rxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;
1546
1547         /* Allocate software ring. */
1548         rxq->sw_ring = rte_zmalloc("rxq->sw_ring",
1549                                    sizeof(struct igb_rx_entry) * nb_desc,
1550                                    RTE_CACHE_LINE_SIZE);
1551         if (rxq->sw_ring == NULL) {
1552                 igb_rx_queue_release(rxq);
1553                 return -ENOMEM;
1554         }
1555         PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1556                      rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
1557
1558         dev->data->rx_queues[queue_idx] = rxq;
1559         igb_reset_rx_queue(rxq);
1560
1561         return 0;
1562 }
1563
1564 uint32_t
1565 eth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1566 {
1567 #define IGB_RXQ_SCAN_INTERVAL 4
1568         volatile union e1000_adv_rx_desc *rxdp;
1569         struct igb_rx_queue *rxq;
1570         uint32_t desc = 0;
1571
1572         rxq = dev->data->rx_queues[rx_queue_id];
1573         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1574
1575         while ((desc < rxq->nb_rx_desc) &&
1576                 (rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {
1577                 desc += IGB_RXQ_SCAN_INTERVAL;
1578                 rxdp += IGB_RXQ_SCAN_INTERVAL;
1579                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1580                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1581                                 desc - rxq->nb_rx_desc]);
1582         }
1583
1584         return desc;
1585 }
1586
1587 int
1588 eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)
1589 {
1590         volatile union e1000_adv_rx_desc *rxdp;
1591         struct igb_rx_queue *rxq = rx_queue;
1592         uint32_t desc;
1593
1594         if (unlikely(offset >= rxq->nb_rx_desc))
1595                 return 0;
1596         desc = rxq->rx_tail + offset;
1597         if (desc >= rxq->nb_rx_desc)
1598                 desc -= rxq->nb_rx_desc;
1599
1600         rxdp = &rxq->rx_ring[desc];
1601         return !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);
1602 }
1603
1604 void
1605 igb_dev_clear_queues(struct rte_eth_dev *dev)
1606 {
1607         uint16_t i;
1608         struct igb_tx_queue *txq;
1609         struct igb_rx_queue *rxq;
1610
1611         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1612                 txq = dev->data->tx_queues[i];
1613                 if (txq != NULL) {
1614                         igb_tx_queue_release_mbufs(txq);
1615                         igb_reset_tx_queue(txq, dev);
1616                 }
1617         }
1618
1619         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1620                 rxq = dev->data->rx_queues[i];
1621                 if (rxq != NULL) {
1622                         igb_rx_queue_release_mbufs(rxq);
1623                         igb_reset_rx_queue(rxq);
1624                 }
1625         }
1626 }
1627
1628 void
1629 igb_dev_free_queues(struct rte_eth_dev *dev)
1630 {
1631         uint16_t i;
1632
1633         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1634                 eth_igb_rx_queue_release(dev->data->rx_queues[i]);
1635                 dev->data->rx_queues[i] = NULL;
1636         }
1637         dev->data->nb_rx_queues = 0;
1638
1639         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1640                 eth_igb_tx_queue_release(dev->data->tx_queues[i]);
1641                 dev->data->tx_queues[i] = NULL;
1642         }
1643         dev->data->nb_tx_queues = 0;
1644 }
1645
1646 /**
1647  * Receive Side Scaling (RSS).
1648  * See section 7.1.1.7 in the following document:
1649  *     "Intel 82576 GbE Controller Datasheet" - Revision 2.45 October 2009
1650  *
1651  * Principles:
1652  * The source and destination IP addresses of the IP header and the source and
1653  * destination ports of TCP/UDP headers, if any, of received packets are hashed
1654  * against a configurable random key to compute a 32-bit RSS hash result.
1655  * The seven (7) LSBs of the 32-bit hash result are used as an index into a
1656  * 128-entry redirection table (RETA).  Each entry of the RETA provides a 3-bit
1657  * RSS output index which is used as the RX queue index where to store the
1658  * received packets.
1659  * The following output is supplied in the RX write-back descriptor:
1660  *     - 32-bit result of the Microsoft RSS hash function,
1661  *     - 4-bit RSS type field.
1662  */
1663
1664 /*
1665  * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.
1666  * Used as the default key.
1667  */
1668 static uint8_t rss_intel_key[40] = {
1669         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1670         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1671         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1672         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1673         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1674 };
1675
1676 static void
1677 igb_rss_disable(struct rte_eth_dev *dev)
1678 {
1679         struct e1000_hw *hw;
1680         uint32_t mrqc;
1681
1682         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1684         mrqc &= ~E1000_MRQC_ENABLE_MASK;
1685         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1686 }
1687
1688 static void
1689 igb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)
1690 {
1691         uint8_t  *hash_key;
1692         uint32_t rss_key;
1693         uint32_t mrqc;
1694         uint64_t rss_hf;
1695         uint16_t i;
1696
1697         hash_key = rss_conf->rss_key;
1698         if (hash_key != NULL) {
1699                 /* Fill in RSS hash key */
1700                 for (i = 0; i < 10; i++) {
1701                         rss_key  = hash_key[(i * 4)];
1702                         rss_key |= hash_key[(i * 4) + 1] << 8;
1703                         rss_key |= hash_key[(i * 4) + 2] << 16;
1704                         rss_key |= hash_key[(i * 4) + 3] << 24;
1705                         E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);
1706                 }
1707         }
1708
1709         /* Set configured hashing protocols in MRQC register */
1710         rss_hf = rss_conf->rss_hf;
1711         mrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */
1712         if (rss_hf & ETH_RSS_IPV4)
1713                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4;
1714         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1715                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;
1716         if (rss_hf & ETH_RSS_IPV6)
1717                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6;
1718         if (rss_hf & ETH_RSS_IPV6_EX)
1719                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;
1720         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1721                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;
1722         if (rss_hf & ETH_RSS_IPV6_TCP_EX)
1723                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
1724         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1725                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
1726         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1727                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
1728         if (rss_hf & ETH_RSS_IPV6_UDP_EX)
1729                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;
1730         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1731 }
1732
1733 int
1734 eth_igb_rss_hash_update(struct rte_eth_dev *dev,
1735                         struct rte_eth_rss_conf *rss_conf)
1736 {
1737         struct e1000_hw *hw;
1738         uint32_t mrqc;
1739         uint64_t rss_hf;
1740
1741         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1742
1743         /*
1744          * Before changing anything, first check that the update RSS operation
1745          * does not attempt to disable RSS, if RSS was enabled at
1746          * initialization time, or does not attempt to enable RSS, if RSS was
1747          * disabled at initialization time.
1748          */
1749         rss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;
1750         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1751         if (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */
1752                 if (rss_hf != 0) /* Enable RSS */
1753                         return -(EINVAL);
1754                 return 0; /* Nothing to do */
1755         }
1756         /* RSS enabled */
1757         if (rss_hf == 0) /* Disable RSS */
1758                 return -(EINVAL);
1759         igb_hw_rss_hash_set(hw, rss_conf);
1760         return 0;
1761 }
1762
1763 int eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,
1764                               struct rte_eth_rss_conf *rss_conf)
1765 {
1766         struct e1000_hw *hw;
1767         uint8_t *hash_key;
1768         uint32_t rss_key;
1769         uint32_t mrqc;
1770         uint64_t rss_hf;
1771         uint16_t i;
1772
1773         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1774         hash_key = rss_conf->rss_key;
1775         if (hash_key != NULL) {
1776                 /* Return RSS hash key */
1777                 for (i = 0; i < 10; i++) {
1778                         rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);
1779                         hash_key[(i * 4)] = rss_key & 0x000000FF;
1780                         hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
1781                         hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
1782                         hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
1783                 }
1784         }
1785
1786         /* Get RSS functions configured in MRQC register */
1787         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1788         if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */
1789                 rss_conf->rss_hf = 0;
1790                 return 0;
1791         }
1792         rss_hf = 0;
1793         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4)
1794                 rss_hf |= ETH_RSS_IPV4;
1795         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)
1796                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1797         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6)
1798                 rss_hf |= ETH_RSS_IPV6;
1799         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)
1800                 rss_hf |= ETH_RSS_IPV6_EX;
1801         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)
1802                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1803         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)
1804                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
1805         if (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)
1806                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1807         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)
1808                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1809         if (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)
1810                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
1811         rss_conf->rss_hf = rss_hf;
1812         return 0;
1813 }
1814
1815 static void
1816 igb_rss_configure(struct rte_eth_dev *dev)
1817 {
1818         struct rte_eth_rss_conf rss_conf;
1819         struct e1000_hw *hw;
1820         uint32_t shift;
1821         uint16_t i;
1822
1823         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824
1825         /* Fill in redirection table. */
1826         shift = (hw->mac.type == e1000_82575) ? 6 : 0;
1827         for (i = 0; i < 128; i++) {
1828                 union e1000_reta {
1829                         uint32_t dword;
1830                         uint8_t  bytes[4];
1831                 } reta;
1832                 uint8_t q_idx;
1833
1834                 q_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?
1835                                    i % dev->data->nb_rx_queues : 0);
1836                 reta.bytes[i & 3] = (uint8_t) (q_idx << shift);
1837                 if ((i & 3) == 3)
1838                         E1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);
1839         }
1840
1841         /*
1842          * Configure the RSS key and the RSS protocols used to compute
1843          * the RSS hash of input packets.
1844          */
1845         rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
1846         if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {
1847                 igb_rss_disable(dev);
1848                 return;
1849         }
1850         if (rss_conf.rss_key == NULL)
1851                 rss_conf.rss_key = rss_intel_key; /* Default hash key */
1852         igb_hw_rss_hash_set(hw, &rss_conf);
1853 }
1854
1855 /*
1856  * Check if the mac type support VMDq or not.
1857  * Return 1 if it supports, otherwise, return 0.
1858  */
1859 static int
1860 igb_is_vmdq_supported(const struct rte_eth_dev *dev)
1861 {
1862         const struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863
1864         switch (hw->mac.type) {
1865         case e1000_82576:
1866         case e1000_82580:
1867         case e1000_i350:
1868                 return 1;
1869         case e1000_82540:
1870         case e1000_82541:
1871         case e1000_82542:
1872         case e1000_82543:
1873         case e1000_82544:
1874         case e1000_82545:
1875         case e1000_82546:
1876         case e1000_82547:
1877         case e1000_82571:
1878         case e1000_82572:
1879         case e1000_82573:
1880         case e1000_82574:
1881         case e1000_82583:
1882         case e1000_i210:
1883         case e1000_i211:
1884         default:
1885                 PMD_INIT_LOG(ERR, "Cannot support VMDq feature");
1886                 return 0;
1887         }
1888 }
1889
1890 static int
1891 igb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
1892 {
1893         struct rte_eth_vmdq_rx_conf *cfg;
1894         struct e1000_hw *hw;
1895         uint32_t mrqc, vt_ctl, vmolr, rctl;
1896         int i;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1902
1903         /* Check if mac type can support VMDq, return value of 0 means NOT support */
1904         if (igb_is_vmdq_supported(dev) == 0)
1905                 return -1;
1906
1907         igb_rss_disable(dev);
1908
1909         /* RCTL: eanble VLAN filter */
1910         rctl = E1000_READ_REG(hw, E1000_RCTL);
1911         rctl |= E1000_RCTL_VFE;
1912         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1913
1914         /* MRQC: enable vmdq */
1915         mrqc = E1000_READ_REG(hw, E1000_MRQC);
1916         mrqc |= E1000_MRQC_ENABLE_VMDQ;
1917         E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
1918
1919         /* VTCTL:  pool selection according to VLAN tag */
1920         vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1921         if (cfg->enable_default_pool)
1922                 vt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1923         vt_ctl |= E1000_VT_CTL_IGNORE_MAC;
1924         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1925
1926         for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1927                 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1928                 vmolr &= ~(E1000_VMOLR_AUPE | E1000_VMOLR_ROMPE |
1929                         E1000_VMOLR_ROPE | E1000_VMOLR_BAM |
1930                         E1000_VMOLR_MPME);
1931
1932                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
1933                         vmolr |= E1000_VMOLR_AUPE;
1934                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
1935                         vmolr |= E1000_VMOLR_ROMPE;
1936                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
1937                         vmolr |= E1000_VMOLR_ROPE;
1938                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
1939                         vmolr |= E1000_VMOLR_BAM;
1940                 if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
1941                         vmolr |= E1000_VMOLR_MPME;
1942
1943                 E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1944         }
1945
1946         /*
1947          * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1
1948          * Both 82576 and 82580 support it
1949          */
1950         if (hw->mac.type != e1000_i350) {
1951                 for (i = 0; i < E1000_VMOLR_SIZE; i++) {
1952                         vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));
1953                         vmolr |= E1000_VMOLR_STRVLAN;
1954                         E1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);
1955                 }
1956         }
1957
1958         /* VFTA - enable all vlan filters */
1959         for (i = 0; i < IGB_VFTA_SIZE; i++)
1960                 E1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);
1961
1962         /* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */
1963         if (hw->mac.type != e1000_82580)
1964                 E1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);
1965
1966         /*
1967          * RAH/RAL - allow pools to read specific mac addresses
1968          * In this case, all pools should be able to read from mac addr 0
1969          */
1970         E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));
1971         E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);
1972
1973         /* VLVF: set up filters for vlan tags as configured */
1974         for (i = 0; i < cfg->nb_pool_maps; i++) {
1975                 /* set vlan id in VF register and set the valid bit */
1976                 E1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \
1977                         (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \
1978                         ((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \
1979                         E1000_VLVF_POOLSEL_MASK)));
1980         }
1981
1982         E1000_WRITE_FLUSH(hw);
1983
1984         return 0;
1985 }
1986
1987
1988 /*********************************************************************
1989  *
1990  *  Enable receive unit.
1991  *
1992  **********************************************************************/
1993
1994 static int
1995 igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
1996 {
1997         struct igb_rx_entry *rxe = rxq->sw_ring;
1998         uint64_t dma_addr;
1999         unsigned i;
2000
2001         /* Initialize software ring entries. */
2002         for (i = 0; i < rxq->nb_rx_desc; i++) {
2003                 volatile union e1000_adv_rx_desc *rxd;
2004                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
2005
2006                 if (mbuf == NULL) {
2007                         PMD_INIT_LOG(ERR, "RX mbuf alloc failed "
2008                                      "queue_id=%hu", rxq->queue_id);
2009                         return -ENOMEM;
2010                 }
2011                 dma_addr =
2012                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2013                 rxd = &rxq->rx_ring[i];
2014                 rxd->read.hdr_addr = 0;
2015                 rxd->read.pkt_addr = dma_addr;
2016                 rxe[i].mbuf = mbuf;
2017         }
2018
2019         return 0;
2020 }
2021
2022 #define E1000_MRQC_DEF_Q_SHIFT               (3)
2023 static int
2024 igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
2025 {
2026         struct e1000_hw *hw =
2027                 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t mrqc;
2029
2030         if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
2031                 /*
2032                  * SRIOV active scheme
2033                  * FIXME if support RSS together with VMDq & SRIOV
2034                  */
2035                 mrqc = E1000_MRQC_ENABLE_VMDQ;
2036                 /* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
2037                 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
2038                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2039         } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
2040                 /*
2041                  * SRIOV inactive scheme
2042                  */
2043                 switch (dev->data->dev_conf.rxmode.mq_mode) {
2044                         case ETH_MQ_RX_RSS:
2045                                 igb_rss_configure(dev);
2046                                 break;
2047                         case ETH_MQ_RX_VMDQ_ONLY:
2048                                 /*Configure general VMDQ only RX parameters*/
2049                                 igb_vmdq_rx_hw_configure(dev);
2050                                 break;
2051                         case ETH_MQ_RX_NONE:
2052                                 /* if mq_mode is none, disable rss mode.*/
2053                         default:
2054                                 igb_rss_disable(dev);
2055                                 break;
2056                 }
2057         }
2058
2059         return 0;
2060 }
2061
2062 int
2063 eth_igb_rx_init(struct rte_eth_dev *dev)
2064 {
2065         struct e1000_hw     *hw;
2066         struct igb_rx_queue *rxq;
2067         uint32_t rctl;
2068         uint32_t rxcsum;
2069         uint32_t srrctl;
2070         uint16_t buf_size;
2071         uint16_t rctl_bsize;
2072         uint16_t i;
2073         int ret;
2074
2075         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076         srrctl = 0;
2077
2078         /*
2079          * Make sure receives are disabled while setting
2080          * up the descriptor ring.
2081          */
2082         rctl = E1000_READ_REG(hw, E1000_RCTL);
2083         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2084
2085         /*
2086          * Configure support of jumbo frames, if any.
2087          */
2088         if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
2089                 rctl |= E1000_RCTL_LPE;
2090
2091                 /*
2092                  * Set maximum packet length by default, and might be updated
2093                  * together with enabling/disabling dual VLAN.
2094                  */
2095                 E1000_WRITE_REG(hw, E1000_RLPML,
2096                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2097                                                 VLAN_TAG_SIZE);
2098         } else
2099                 rctl &= ~E1000_RCTL_LPE;
2100
2101         /* Configure and enable each RX queue. */
2102         rctl_bsize = 0;
2103         dev->rx_pkt_burst = eth_igb_recv_pkts;
2104         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2105                 uint64_t bus_addr;
2106                 uint32_t rxdctl;
2107
2108                 rxq = dev->data->rx_queues[i];
2109
2110                 /* Allocate buffers for descriptor rings and set up queue */
2111                 ret = igb_alloc_rx_queue_mbufs(rxq);
2112                 if (ret)
2113                         return ret;
2114
2115                 /*
2116                  * Reset crc_len in case it was changed after queue setup by a
2117                  *  call to configure
2118                  */
2119                 rxq->crc_len =
2120                         (uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?
2121                                                         0 : ETHER_CRC_LEN);
2122
2123                 bus_addr = rxq->rx_ring_phys_addr;
2124                 E1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),
2125                                 rxq->nb_rx_desc *
2126                                 sizeof(union e1000_adv_rx_desc));
2127                 E1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),
2128                                 (uint32_t)(bus_addr >> 32));
2129                 E1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);
2130
2131                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2132
2133                 /*
2134                  * Configure RX buffer size.
2135                  */
2136                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2137                         RTE_PKTMBUF_HEADROOM);
2138                 if (buf_size >= 1024) {
2139                         /*
2140                          * Configure the BSIZEPACKET field of the SRRCTL
2141                          * register of the queue.
2142                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2143                          * If this field is equal to 0b, then RCTL.BSIZE
2144                          * determines the RX packet buffer size.
2145                          */
2146                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2147                                    E1000_SRRCTL_BSIZEPKT_MASK);
2148                         buf_size = (uint16_t) ((srrctl &
2149                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2150                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2151
2152                         /* It adds dual VLAN length for supporting dual VLAN */
2153                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2154                                                 2 * VLAN_TAG_SIZE) > buf_size){
2155                                 if (!dev->data->scattered_rx)
2156                                         PMD_INIT_LOG(DEBUG,
2157                                                      "forcing scatter mode");
2158                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2159                                 dev->data->scattered_rx = 1;
2160                         }
2161                 } else {
2162                         /*
2163                          * Use BSIZE field of the device RCTL register.
2164                          */
2165                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2166                                 rctl_bsize = buf_size;
2167                         if (!dev->data->scattered_rx)
2168                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2169                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2170                         dev->data->scattered_rx = 1;
2171                 }
2172
2173                 /* Set if packets are dropped when no descriptors available */
2174                 if (rxq->drop_en)
2175                         srrctl |= E1000_SRRCTL_DROP_EN;
2176
2177                 E1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);
2178
2179                 /* Enable this RX queue. */
2180                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));
2181                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2182                 rxdctl &= 0xFFF00000;
2183                 rxdctl |= (rxq->pthresh & 0x1F);
2184                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2185                 rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2186                 E1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);
2187         }
2188
2189         if (dev->data->dev_conf.rxmode.enable_scatter) {
2190                 if (!dev->data->scattered_rx)
2191                         PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2192                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2193                 dev->data->scattered_rx = 1;
2194         }
2195
2196         /*
2197          * Setup BSIZE field of RCTL register, if needed.
2198          * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL
2199          * register, since the code above configures the SRRCTL register of
2200          * the RX queue in such a case.
2201          * All configurable sizes are:
2202          * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);
2203          *  8192: rctl |= (E1000_RCTL_SZ_8192  | E1000_RCTL_BSEX);
2204          *  4096: rctl |= (E1000_RCTL_SZ_4096  | E1000_RCTL_BSEX);
2205          *  2048: rctl |= E1000_RCTL_SZ_2048;
2206          *  1024: rctl |= E1000_RCTL_SZ_1024;
2207          *   512: rctl |= E1000_RCTL_SZ_512;
2208          *   256: rctl |= E1000_RCTL_SZ_256;
2209          */
2210         if (rctl_bsize > 0) {
2211                 if (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */
2212                         rctl |= E1000_RCTL_SZ_512;
2213                 else /* 256 <= buf_size < 512 - use 256 */
2214                         rctl |= E1000_RCTL_SZ_256;
2215         }
2216
2217         /*
2218          * Configure RSS if device configured with multiple RX queues.
2219          */
2220         igb_dev_mq_rx_configure(dev);
2221
2222         /* Update the rctl since igb_dev_mq_rx_configure may change its value */
2223         rctl |= E1000_READ_REG(hw, E1000_RCTL);
2224
2225         /*
2226          * Setup the Checksum Register.
2227          * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.
2228          */
2229         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2230         rxcsum |= E1000_RXCSUM_PCSD;
2231
2232         /* Enable both L3/L4 rx checksum offload */
2233         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
2234                 rxcsum |= (E1000_RXCSUM_IPOFL  | E1000_RXCSUM_TUOFL);
2235         else
2236                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2237         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2238
2239         /* Setup the Receive Control Register. */
2240         if (dev->data->dev_conf.rxmode.hw_strip_crc) {
2241                 rctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */
2242
2243                 /* set STRCRC bit in all queues */
2244                 if (hw->mac.type == e1000_i350 ||
2245                     hw->mac.type == e1000_i210 ||
2246                     hw->mac.type == e1000_i211 ||
2247                     hw->mac.type == e1000_i354) {
2248                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2249                                 rxq = dev->data->rx_queues[i];
2250                                 uint32_t dvmolr = E1000_READ_REG(hw,
2251                                         E1000_DVMOLR(rxq->reg_idx));
2252                                 dvmolr |= E1000_DVMOLR_STRCRC;
2253                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2254                         }
2255                 }
2256         } else {
2257                 rctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */
2258
2259                 /* clear STRCRC bit in all queues */
2260                 if (hw->mac.type == e1000_i350 ||
2261                     hw->mac.type == e1000_i210 ||
2262                     hw->mac.type == e1000_i211 ||
2263                     hw->mac.type == e1000_i354) {
2264                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2265                                 rxq = dev->data->rx_queues[i];
2266                                 uint32_t dvmolr = E1000_READ_REG(hw,
2267                                         E1000_DVMOLR(rxq->reg_idx));
2268                                 dvmolr &= ~E1000_DVMOLR_STRCRC;
2269                                 E1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);
2270                         }
2271                 }
2272         }
2273
2274         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2275         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2276                 E1000_RCTL_RDMTS_HALF |
2277                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2278
2279         /* Make sure VLAN Filters are off. */
2280         if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)
2281                 rctl &= ~E1000_RCTL_VFE;
2282         /* Don't store bad packets. */
2283         rctl &= ~E1000_RCTL_SBP;
2284
2285         /* Enable Receives. */
2286         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2287
2288         /*
2289          * Setup the HW Rx Head and Tail Descriptor Pointers.
2290          * This needs to be done after enable.
2291          */
2292         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2293                 rxq = dev->data->rx_queues[i];
2294                 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);
2295                 E1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
2296         }
2297
2298         return 0;
2299 }
2300
2301 /*********************************************************************
2302  *
2303  *  Enable transmit unit.
2304  *
2305  **********************************************************************/
2306 void
2307 eth_igb_tx_init(struct rte_eth_dev *dev)
2308 {
2309         struct e1000_hw     *hw;
2310         struct igb_tx_queue *txq;
2311         uint32_t tctl;
2312         uint32_t txdctl;
2313         uint16_t i;
2314
2315         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316
2317         /* Setup the Base and Length of the Tx Descriptor Rings. */
2318         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2319                 uint64_t bus_addr;
2320                 txq = dev->data->tx_queues[i];
2321                 bus_addr = txq->tx_ring_phys_addr;
2322
2323                 E1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),
2324                                 txq->nb_tx_desc *
2325                                 sizeof(union e1000_adv_tx_desc));
2326                 E1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),
2327                                 (uint32_t)(bus_addr >> 32));
2328                 E1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);
2329
2330                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2331                 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);
2332                 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);
2333
2334                 /* Setup Transmit threshold registers. */
2335                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));
2336                 txdctl |= txq->pthresh & 0x1F;
2337                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2338                 txdctl |= ((txq->wthresh & 0x1F) << 16);
2339                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2340                 E1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);
2341         }
2342
2343         /* Program the Transmit Control Register. */
2344         tctl = E1000_READ_REG(hw, E1000_TCTL);
2345         tctl &= ~E1000_TCTL_CT;
2346         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2347                  (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
2348
2349         e1000_config_collision_dist(hw);
2350
2351         /* This write will effectively turn on the transmit unit. */
2352         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
2353 }
2354
2355 /*********************************************************************
2356  *
2357  *  Enable VF receive unit.
2358  *
2359  **********************************************************************/
2360 int
2361 eth_igbvf_rx_init(struct rte_eth_dev *dev)
2362 {
2363         struct e1000_hw     *hw;
2364         struct igb_rx_queue *rxq;
2365         uint32_t srrctl;
2366         uint16_t buf_size;
2367         uint16_t rctl_bsize;
2368         uint16_t i;
2369         int ret;
2370
2371         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372
2373         /* setup MTU */
2374         e1000_rlpml_set_vf(hw,
2375                 (uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len +
2376                 VLAN_TAG_SIZE));
2377
2378         /* Configure and enable each RX queue. */
2379         rctl_bsize = 0;
2380         dev->rx_pkt_burst = eth_igb_recv_pkts;
2381         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2382                 uint64_t bus_addr;
2383                 uint32_t rxdctl;
2384
2385                 rxq = dev->data->rx_queues[i];
2386
2387                 /* Allocate buffers for descriptor rings and set up queue */
2388                 ret = igb_alloc_rx_queue_mbufs(rxq);
2389                 if (ret)
2390                         return ret;
2391
2392                 bus_addr = rxq->rx_ring_phys_addr;
2393                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2394                                 rxq->nb_rx_desc *
2395                                 sizeof(union e1000_adv_rx_desc));
2396                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2397                                 (uint32_t)(bus_addr >> 32));
2398                 E1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);
2399
2400                 srrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2401
2402                 /*
2403                  * Configure RX buffer size.
2404                  */
2405                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
2406                         RTE_PKTMBUF_HEADROOM);
2407                 if (buf_size >= 1024) {
2408                         /*
2409                          * Configure the BSIZEPACKET field of the SRRCTL
2410                          * register of the queue.
2411                          * Value is in 1 KB resolution, from 1 KB to 127 KB.
2412                          * If this field is equal to 0b, then RCTL.BSIZE
2413                          * determines the RX packet buffer size.
2414                          */
2415                         srrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &
2416                                    E1000_SRRCTL_BSIZEPKT_MASK);
2417                         buf_size = (uint16_t) ((srrctl &
2418                                                 E1000_SRRCTL_BSIZEPKT_MASK) <<
2419                                                E1000_SRRCTL_BSIZEPKT_SHIFT);
2420
2421                         /* It adds dual VLAN length for supporting dual VLAN */
2422                         if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
2423                                                 2 * VLAN_TAG_SIZE) > buf_size){
2424                                 if (!dev->data->scattered_rx)
2425                                         PMD_INIT_LOG(DEBUG,
2426                                                      "forcing scatter mode");
2427                                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2428                                 dev->data->scattered_rx = 1;
2429                         }
2430                 } else {
2431                         /*
2432                          * Use BSIZE field of the device RCTL register.
2433                          */
2434                         if ((rctl_bsize == 0) || (rctl_bsize > buf_size))
2435                                 rctl_bsize = buf_size;
2436                         if (!dev->data->scattered_rx)
2437                                 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2438                         dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2439                         dev->data->scattered_rx = 1;
2440                 }
2441
2442                 /* Set if packets are dropped when no descriptors available */
2443                 if (rxq->drop_en)
2444                         srrctl |= E1000_SRRCTL_DROP_EN;
2445
2446                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2447
2448                 /* Enable this RX queue. */
2449                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2450                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2451                 rxdctl &= 0xFFF00000;
2452                 rxdctl |= (rxq->pthresh & 0x1F);
2453                 rxdctl |= ((rxq->hthresh & 0x1F) << 8);
2454                 if (hw->mac.type == e1000_vfadapt) {
2455                         /*
2456                          * Workaround of 82576 VF Erratum
2457                          * force set WTHRESH to 1
2458                          * to avoid Write-Back not triggered sometimes
2459                          */
2460                         rxdctl |= 0x10000;
2461                         PMD_INIT_LOG(DEBUG, "Force set RX WTHRESH to 1 !");
2462                 }
2463                 else
2464                         rxdctl |= ((rxq->wthresh & 0x1F) << 16);
2465                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2466         }
2467
2468         if (dev->data->dev_conf.rxmode.enable_scatter) {
2469                 if (!dev->data->scattered_rx)
2470                         PMD_INIT_LOG(DEBUG, "forcing scatter mode");
2471                 dev->rx_pkt_burst = eth_igb_recv_scattered_pkts;
2472                 dev->data->scattered_rx = 1;
2473         }
2474
2475         /*
2476          * Setup the HW Rx Head and Tail Descriptor Pointers.
2477          * This needs to be done after enable.
2478          */
2479         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2480                 rxq = dev->data->rx_queues[i];
2481                 E1000_WRITE_REG(hw, E1000_RDH(i), 0);
2482                 E1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);
2483         }
2484
2485         return 0;
2486 }
2487
2488 /*********************************************************************
2489  *
2490  *  Enable VF transmit unit.
2491  *
2492  **********************************************************************/
2493 void
2494 eth_igbvf_tx_init(struct rte_eth_dev *dev)
2495 {
2496         struct e1000_hw     *hw;
2497         struct igb_tx_queue *txq;
2498         uint32_t txdctl;
2499         uint16_t i;
2500
2501         hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502
2503         /* Setup the Base and Length of the Tx Descriptor Rings. */
2504         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2505                 uint64_t bus_addr;
2506
2507                 txq = dev->data->tx_queues[i];
2508                 bus_addr = txq->tx_ring_phys_addr;
2509                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
2510                                 txq->nb_tx_desc *
2511                                 sizeof(union e1000_adv_tx_desc));
2512                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
2513                                 (uint32_t)(bus_addr >> 32));
2514                 E1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);
2515
2516                 /* Setup the HW Tx Head and Tail descriptor pointers. */
2517                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
2518                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
2519
2520                 /* Setup Transmit threshold registers. */
2521                 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));
2522                 txdctl |= txq->pthresh & 0x1F;
2523                 txdctl |= ((txq->hthresh & 0x1F) << 8);
2524                 if (hw->mac.type == e1000_82576) {
2525                         /*
2526                          * Workaround of 82576 VF Erratum
2527                          * force set WTHRESH to 1
2528                          * to avoid Write-Back not triggered sometimes
2529                          */
2530                         txdctl |= 0x10000;
2531                         PMD_INIT_LOG(DEBUG, "Force set TX WTHRESH to 1 !");
2532                 }
2533                 else
2534                         txdctl |= ((txq->wthresh & 0x1F) << 16);
2535                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2536                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
2537         }
2538
2539 }
2540
2541 void
2542 igb_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2543         struct rte_eth_rxq_info *qinfo)
2544 {
2545         struct igb_rx_queue *rxq;
2546
2547         rxq = dev->data->rx_queues[queue_id];
2548
2549         qinfo->mp = rxq->mb_pool;
2550         qinfo->scattered_rx = dev->data->scattered_rx;
2551         qinfo->nb_desc = rxq->nb_rx_desc;
2552
2553         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2554         qinfo->conf.rx_drop_en = rxq->drop_en;
2555 }
2556
2557 void
2558 igb_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2559         struct rte_eth_txq_info *qinfo)
2560 {
2561         struct igb_tx_queue *txq;
2562
2563         txq = dev->data->tx_queues[queue_id];
2564
2565         qinfo->nb_desc = txq->nb_tx_desc;
2566
2567         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2568         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2569         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2570 }