drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 static const struct ena_stats ena_stats_global_strings[] = {
 118         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 119         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 120         ENA_STAT_GLOBAL_ENTRY(io_resume),
 121         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 122         ENA_STAT_GLOBAL_ENTRY(interface_up),
 123         ENA_STAT_GLOBAL_ENTRY(interface_down),
 124         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 125 };
 126
 127 static const struct ena_stats ena_stats_tx_strings[] = {
 128         ENA_STAT_TX_ENTRY(cnt),
 129         ENA_STAT_TX_ENTRY(bytes),
 130         ENA_STAT_TX_ENTRY(queue_stop),
 131         ENA_STAT_TX_ENTRY(queue_wakeup),
 132         ENA_STAT_TX_ENTRY(dma_mapping_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 138         ENA_STAT_TX_ENTRY(missing_tx_comp),
 139         ENA_STAT_TX_ENTRY(bad_req_id),
 140 };
 141
 142 static const struct ena_stats ena_stats_rx_strings[] = {
 143         ENA_STAT_RX_ENTRY(cnt),
 144         ENA_STAT_RX_ENTRY(bytes),
 145         ENA_STAT_RX_ENTRY(refil_partial),
 146         ENA_STAT_RX_ENTRY(bad_csum),
 147         ENA_STAT_RX_ENTRY(page_alloc_fail),
 148         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 149         ENA_STAT_RX_ENTRY(dma_mapping_err),
 150         ENA_STAT_RX_ENTRY(bad_desc_num),
 151         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 152 };
 153
 154 static const struct ena_stats ena_stats_ena_com_strings[] = {
 155         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 157         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 158         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 159         ENA_STAT_ENA_COM_ENTRY(no_completion),
 160 };
 161
 162 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 163 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 164 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 166
 167 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 168                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 169                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 170                         DEV_TX_OFFLOAD_TCP_TSO)
 171 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 172                        PKT_TX_IP_CKSUM |\
 173                        PKT_TX_TCP_SEG)
 174
 175 /** Vendor ID used by Amazon devices */
 176 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 177 /** Amazon devices */
 178 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 179 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 180
 181 #define ENA_TX_OFFLOAD_MASK     (\
 182         PKT_TX_L4_MASK |         \
 183         PKT_TX_IP_CKSUM |        \
 184         PKT_TX_TCP_SEG)
 185
 186 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 187         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 188
 189 int ena_logtype_init;
 190 int ena_logtype_driver;
 191
 192 static const struct rte_pci_id pci_id_ena_map[] = {
 193         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 194         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 195         { .device_id = 0 },
 196 };
 197
 198 static int ena_device_init(struct ena_com_dev *ena_dev,
 199                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 200 static int ena_dev_configure(struct rte_eth_dev *dev);
 201 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 202                                   uint16_t nb_pkts);
 203 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 204                 uint16_t nb_pkts);
 205 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 206                               uint16_t nb_desc, unsigned int socket_id,
 207                               const struct rte_eth_txconf *tx_conf);
 208 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 209                               uint16_t nb_desc, unsigned int socket_id,
 210                               const struct rte_eth_rxconf *rx_conf,
 211                               struct rte_mempool *mp);
 212 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 213                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 214 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 215 static void ena_init_rings(struct ena_adapter *adapter);
 216 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 217 static int ena_start(struct rte_eth_dev *dev);
 218 static void ena_close(struct rte_eth_dev *dev);
 219 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 220 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 221 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 222 static void ena_rx_queue_release(void *queue);
 223 static void ena_tx_queue_release(void *queue);
 224 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 225 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 226 static int ena_link_update(struct rte_eth_dev *dev,
 227                            int wait_to_complete);
 228 static int ena_queue_restart(struct ena_ring *ring);
 229 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 230                                  enum ena_ring_type ring_type);
 231 static void ena_stats_restart(struct rte_eth_dev *dev);
 232 static void ena_infos_get(struct rte_eth_dev *dev,
 233                           struct rte_eth_dev_info *dev_info);
 234 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 235                                struct rte_eth_rss_reta_entry64 *reta_conf,
 236                                uint16_t reta_size);
 237 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 238                               struct rte_eth_rss_reta_entry64 *reta_conf,
 239                               uint16_t reta_size);
 240 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 241 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
 242                                               uint64_t offloads);
 243
 244 static const struct eth_dev_ops ena_dev_ops = {
 245         .dev_configure        = ena_dev_configure,
 246         .dev_infos_get        = ena_infos_get,
 247         .rx_queue_setup       = ena_rx_queue_setup,
 248         .tx_queue_setup       = ena_tx_queue_setup,
 249         .dev_start            = ena_start,
 250         .link_update          = ena_link_update,
 251         .stats_get            = ena_stats_get,
 252         .mtu_set              = ena_mtu_set,
 253         .rx_queue_release     = ena_rx_queue_release,
 254         .tx_queue_release     = ena_tx_queue_release,
 255         .dev_close            = ena_close,
 256         .reta_update          = ena_rss_reta_update,
 257         .reta_query           = ena_rss_reta_query,
 258 };
 259
 260 #define NUMA_NO_NODE    SOCKET_ID_ANY
 261
 262 static inline int ena_cpu_to_node(int cpu)
 263 {
 264         struct rte_config *config = rte_eal_get_configuration();
 265
 266         if (likely(cpu < RTE_MAX_MEMZONE))
 267                 return config->mem_config->memzone[cpu].socket_id;
 268
 269         return NUMA_NO_NODE;
 270 }
 271
 272 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 273                                        struct ena_com_rx_ctx *ena_rx_ctx)
 274 {
 275         uint64_t ol_flags = 0;
 276
 277         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 278                 ol_flags |= PKT_TX_TCP_CKSUM;
 279         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 280                 ol_flags |= PKT_TX_UDP_CKSUM;
 281
 282         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 283                 ol_flags |= PKT_TX_IPV4;
 284         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 285                 ol_flags |= PKT_TX_IPV6;
 286
 287         if (unlikely(ena_rx_ctx->l4_csum_err))
 288                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 289         if (unlikely(ena_rx_ctx->l3_csum_err))
 290                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 291
 292         mbuf->ol_flags = ol_flags;
 293 }
 294
 295 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 296                                        struct ena_com_tx_ctx *ena_tx_ctx,
 297                                        uint64_t queue_offloads)
 298 {
 299         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 300
 301         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 302             (queue_offloads & QUEUE_OFFLOADS)) {
 303                 /* check if TSO is required */
 304                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 305                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 306                         ena_tx_ctx->tso_enable = true;
 307
 308                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 309                 }
 310
 311                 /* check if L3 checksum is needed */
 312                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 313                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 314                         ena_tx_ctx->l3_csum_enable = true;
 315
 316                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 317                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 318                 } else {
 319                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 320
 321                         /* set don't fragment (DF) flag */
 322                         if (mbuf->packet_type &
 323                                 (RTE_PTYPE_L4_NONFRAG
 324                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 325                                 ena_tx_ctx->df = true;
 326                 }
 327
 328                 /* check if L4 checksum is needed */
 329                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 331                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 332                         ena_tx_ctx->l4_csum_enable = true;
 333                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 334                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 335                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 336                         ena_tx_ctx->l4_csum_enable = true;
 337                 } else {
 338                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 339                         ena_tx_ctx->l4_csum_enable = false;
 340                 }
 341
 342                 ena_meta->mss = mbuf->tso_segsz;
 343                 ena_meta->l3_hdr_len = mbuf->l3_len;
 344                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 345                 /* this param needed only for TSO */
 346                 ena_meta->l3_outer_hdr_len = 0;
 347                 ena_meta->l3_outer_hdr_offset = 0;
 348
 349                 ena_tx_ctx->meta_valid = true;
 350         } else {
 351                 ena_tx_ctx->meta_valid = false;
 352         }
 353 }
 354
 355 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 356 {
 357         struct ena_admin_host_info *host_info;
 358         int rc;
 359
 360         /* Allocate only the host info */
 361         rc = ena_com_allocate_host_info(ena_dev);
 362         if (rc) {
 363                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 364                 return;
 365         }
 366
 367         host_info = ena_dev->host_attr.host_info;
 368
 369         host_info->os_type = ENA_ADMIN_OS_DPDK;
 370         host_info->kernel_ver = RTE_VERSION;
 371         snprintf((char *)host_info->kernel_ver_str,
 372                  sizeof(host_info->kernel_ver_str),
 373                  "%s", rte_version());
 374         host_info->os_dist = RTE_VERSION;
 375         snprintf((char *)host_info->os_dist_str,
 376                  sizeof(host_info->os_dist_str),
 377                  "%s", rte_version());
 378         host_info->driver_version =
 379                 (DRV_MODULE_VER_MAJOR) |
 380                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 381                 (DRV_MODULE_VER_SUBMINOR <<
 382                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 383
 384         rc = ena_com_set_host_attributes(ena_dev);
 385         if (rc) {
 386                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 387                 if (rc != -EPERM)
 388                         goto err;
 389         }
 390
 391         return;
 392
 393 err:
 394         ena_com_delete_host_info(ena_dev);
 395 }
 396
 397 static int
 398 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 399 {
 400         if (sset != ETH_SS_STATS)
 401                 return -EOPNOTSUPP;
 402
 403          /* Workaround for clang:
 404          * touch internal structures to prevent
 405          * compiler error
 406          */
 407         ENA_TOUCH(ena_stats_global_strings);
 408         ENA_TOUCH(ena_stats_tx_strings);
 409         ENA_TOUCH(ena_stats_rx_strings);
 410         ENA_TOUCH(ena_stats_ena_com_strings);
 411
 412         return  dev->data->nb_tx_queues *
 413                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 414                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 415 }
 416
 417 static void ena_config_debug_area(struct ena_adapter *adapter)
 418 {
 419         u32 debug_area_size;
 420         int rc, ss_count;
 421
 422         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 423         if (ss_count <= 0) {
 424                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 425                 return;
 426         }
 427
 428         /* allocate 32 bytes for each string and 64bit for the value */
 429         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 430
 431         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 432         if (rc) {
 433                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 434                 return;
 435         }
 436
 437         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 438         if (rc) {
 439                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 440                 if (rc != -EPERM)
 441                         goto err;
 442         }
 443
 444         return;
 445 err:
 446         ena_com_delete_debug_area(&adapter->ena_dev);
 447 }
 448
 449 static void ena_close(struct rte_eth_dev *dev)
 450 {
 451         struct ena_adapter *adapter =
 452                 (struct ena_adapter *)(dev->data->dev_private);
 453
 454         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 455
 456         ena_rx_queue_release_all(dev);
 457         ena_tx_queue_release_all(dev);
 458 }
 459
 460 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 461                                struct rte_eth_rss_reta_entry64 *reta_conf,
 462                                uint16_t reta_size)
 463 {
 464         struct ena_adapter *adapter =
 465                 (struct ena_adapter *)(dev->data->dev_private);
 466         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 467         int ret, i;
 468         u16 entry_value;
 469         int conf_idx;
 470         int idx;
 471
 472         if ((reta_size == 0) || (reta_conf == NULL))
 473                 return -EINVAL;
 474
 475         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 476                 RTE_LOG(WARNING, PMD,
 477                         "indirection table %d is bigger than supported (%d)\n",
 478                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 479                 ret = -EINVAL;
 480                 goto err;
 481         }
 482
 483         for (i = 0 ; i < reta_size ; i++) {
 484                 /* each reta_conf is for 64 entries.
 485                  * to support 128 we use 2 conf of 64
 486                  */
 487                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 488                 idx = i % RTE_RETA_GROUP_SIZE;
 489                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 490                         entry_value =
 491                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 492                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 493                                                                 i,
 494                                                                 entry_value);
 495                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 496                                 RTE_LOG(ERR, PMD,
 497                                         "Cannot fill indirect table\n");
 498                                 ret = -ENOTSUP;
 499                                 goto err;
 500                         }
 501                 }
 502         }
 503
 504         ret = ena_com_indirect_table_set(ena_dev);
 505         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 506                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 507                 ret = -ENOTSUP;
 508                 goto err;
 509         }
 510
 511         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 512                 __func__, reta_size, adapter->rte_dev->data->port_id);
 513 err:
 514         return ret;
 515 }
 516
 517 /* Query redirection table. */
 518 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 519                               struct rte_eth_rss_reta_entry64 *reta_conf,
 520                               uint16_t reta_size)
 521 {
 522         struct ena_adapter *adapter =
 523                 (struct ena_adapter *)(dev->data->dev_private);
 524         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 525         int ret;
 526         int i;
 527         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 528         int reta_conf_idx;
 529         int reta_idx;
 530
 531         if (reta_size == 0 || reta_conf == NULL ||
 532             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 533                 return -EINVAL;
 534
 535         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 536         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 537                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 538                 ret = -ENOTSUP;
 539                 goto err;
 540         }
 541
 542         for (i = 0 ; i < reta_size ; i++) {
 543                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 544                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 545                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 546                         reta_conf[reta_conf_idx].reta[reta_idx] =
 547                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 548         }
 549 err:
 550         return ret;
 551 }
 552
 553 static int ena_rss_init_default(struct ena_adapter *adapter)
 554 {
 555         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 556         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 557         int rc, i;
 558         u32 val;
 559
 560         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 561         if (unlikely(rc)) {
 562                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 563                 goto err_rss_init;
 564         }
 565
 566         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 567                 val = i % nb_rx_queues;
 568                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 569                                                        ENA_IO_RXQ_IDX(val));
 570                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 571                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 572                         goto err_fill_indir;
 573                 }
 574         }
 575
 576         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 577                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 578         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 579                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 580                 goto err_fill_indir;
 581         }
 582
 583         rc = ena_com_set_default_hash_ctrl(ena_dev);
 584         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 585                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 586                 goto err_fill_indir;
 587         }
 588
 589         rc = ena_com_indirect_table_set(ena_dev);
 590         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 591                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 592                 goto err_fill_indir;
 593         }
 594         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 595                 adapter->rte_dev->data->port_id);
 596
 597         return 0;
 598
 599 err_fill_indir:
 600         ena_com_rss_destroy(ena_dev);
 601 err_rss_init:
 602
 603         return rc;
 604 }
 605
 606 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 607 {
 608         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 609         int nb_queues = dev->data->nb_rx_queues;
 610         int i;
 611
 612         for (i = 0; i < nb_queues; i++)
 613                 ena_rx_queue_release(queues[i]);
 614 }
 615
 616 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 617 {
 618         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 619         int nb_queues = dev->data->nb_tx_queues;
 620         int i;
 621
 622         for (i = 0; i < nb_queues; i++)
 623                 ena_tx_queue_release(queues[i]);
 624 }
 625
 626 static void ena_rx_queue_release(void *queue)
 627 {
 628         struct ena_ring *ring = (struct ena_ring *)queue;
 629         struct ena_adapter *adapter = ring->adapter;
 630         int ena_qid;
 631
 632         ena_assert_msg(ring->configured,
 633                        "API violation - releasing not configured queue");
 634         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 635                        "API violation");
 636
 637         /* Destroy HW queue */
 638         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 639         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 640
 641         /* Free all bufs */
 642         ena_rx_queue_release_bufs(ring);
 643
 644         /* Free ring resources */
 645         if (ring->rx_buffer_info)
 646                 rte_free(ring->rx_buffer_info);
 647         ring->rx_buffer_info = NULL;
 648
 649         ring->configured = 0;
 650
 651         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 652                 ring->port_id, ring->id);
 653 }
 654
 655 static void ena_tx_queue_release(void *queue)
 656 {
 657         struct ena_ring *ring = (struct ena_ring *)queue;
 658         struct ena_adapter *adapter = ring->adapter;
 659         int ena_qid;
 660
 661         ena_assert_msg(ring->configured,
 662                        "API violation. Releasing not configured queue");
 663         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 664                        "API violation");
 665
 666         /* Destroy HW queue */
 667         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 668         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 669
 670         /* Free all bufs */
 671         ena_tx_queue_release_bufs(ring);
 672
 673         /* Free ring resources */
 674         if (ring->tx_buffer_info)
 675                 rte_free(ring->tx_buffer_info);
 676
 677         if (ring->empty_tx_reqs)
 678                 rte_free(ring->empty_tx_reqs);
 679
 680         ring->empty_tx_reqs = NULL;
 681         ring->tx_buffer_info = NULL;
 682
 683         ring->configured = 0;
 684
 685         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 686                 ring->port_id, ring->id);
 687 }
 688
 689 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 690 {
 691         unsigned int ring_mask = ring->ring_size - 1;
 692
 693         while (ring->next_to_clean != ring->next_to_use) {
 694                 struct rte_mbuf *m =
 695                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 696
 697                 if (m)
 698                         rte_mbuf_raw_free(m);
 699
 700                 ring->next_to_clean++;
 701         }
 702 }
 703
 704 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 705 {
 706         unsigned int i;
 707
 708         for (i = 0; i < ring->ring_size; ++i) {
 709                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 710
 711                 if (tx_buf->mbuf)
 712                         rte_pktmbuf_free(tx_buf->mbuf);
 713
 714                 ring->next_to_clean++;
 715         }
 716 }
 717
 718 static int ena_link_update(struct rte_eth_dev *dev,
 719                            __rte_unused int wait_to_complete)
 720 {
 721         struct rte_eth_link *link = &dev->data->dev_link;
 722
 723         link->link_status = 1;
 724         link->link_speed = ETH_SPEED_NUM_10G;
 725         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 726
 727         return 0;
 728 }
 729
 730 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 731                                  enum ena_ring_type ring_type)
 732 {
 733         struct ena_adapter *adapter =
 734                 (struct ena_adapter *)(dev->data->dev_private);
 735         struct ena_ring *queues = NULL;
 736         int i = 0;
 737         int rc = 0;
 738
 739         queues = (ring_type == ENA_RING_TYPE_RX) ?
 740                 adapter->rx_ring : adapter->tx_ring;
 741
 742         for (i = 0; i < adapter->num_queues; i++) {
 743                 if (queues[i].configured) {
 744                         if (ring_type == ENA_RING_TYPE_RX) {
 745                                 ena_assert_msg(
 746                                         dev->data->rx_queues[i] == &queues[i],
 747                                         "Inconsistent state of rx queues\n");
 748                         } else {
 749                                 ena_assert_msg(
 750                                         dev->data->tx_queues[i] == &queues[i],
 751                                         "Inconsistent state of tx queues\n");
 752                         }
 753
 754                         rc = ena_queue_restart(&queues[i]);
 755
 756                         if (rc) {
 757                                 PMD_INIT_LOG(ERR,
 758                                              "failed to restart queue %d type(%d)",
 759                                              i, ring_type);
 760                                 return -1;
 761                         }
 762                 }
 763         }
 764
 765         return 0;
 766 }
 767
 768 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 769 {
 770         uint32_t max_frame_len = adapter->max_mtu;
 771
 772         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 773                 max_frame_len =
 774                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 775
 776         return max_frame_len;
 777 }
 778
 779 static int ena_check_valid_conf(struct ena_adapter *adapter)
 780 {
 781         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 782
 783         if (max_frame_len > adapter->max_mtu) {
 784                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 785                 return -1;
 786         }
 787
 788         return 0;
 789 }
 790
 791 static int
 792 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 793                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 794 {
 795         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 796
 797         queue_size = RTE_MIN(queue_size,
 798                              get_feat_ctx->max_queues.max_cq_depth);
 799         queue_size = RTE_MIN(queue_size,
 800                              get_feat_ctx->max_queues.max_sq_depth);
 801
 802         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 803                 queue_size = RTE_MIN(queue_size,
 804                                      get_feat_ctx->max_queues.max_llq_depth);
 805
 806         /* Round down to power of 2 */
 807         if (!rte_is_power_of_2(queue_size))
 808                 queue_size = rte_align32pow2(queue_size >> 1);
 809
 810         if (queue_size == 0) {
 811                 PMD_INIT_LOG(ERR, "Invalid queue size");
 812                 return -EFAULT;
 813         }
 814
 815         return queue_size;
 816 }
 817
 818 static void ena_stats_restart(struct rte_eth_dev *dev)
 819 {
 820         struct ena_adapter *adapter =
 821                 (struct ena_adapter *)(dev->data->dev_private);
 822
 823         rte_atomic64_init(&adapter->drv_stats->ierrors);
 824         rte_atomic64_init(&adapter->drv_stats->oerrors);
 825         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 826 }
 827
 828 static int ena_stats_get(struct rte_eth_dev *dev,
 829                           struct rte_eth_stats *stats)
 830 {
 831         struct ena_admin_basic_stats ena_stats;
 832         struct ena_adapter *adapter =
 833                 (struct ena_adapter *)(dev->data->dev_private);
 834         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 835         int rc;
 836
 837         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 838                 return -ENOTSUP;
 839
 840         memset(&ena_stats, 0, sizeof(ena_stats));
 841         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 842         if (unlikely(rc)) {
 843                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 844                 return rc;
 845         }
 846
 847         /* Set of basic statistics from ENA */
 848         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 849                                           ena_stats.rx_pkts_low);
 850         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 851                                           ena_stats.tx_pkts_low);
 852         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 853                                         ena_stats.rx_bytes_low);
 854         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 855                                         ena_stats.tx_bytes_low);
 856         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 857                                          ena_stats.rx_drops_low);
 858
 859         /* Driver related stats */
 860         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 861         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 862         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 863         return 0;
 864 }
 865
 866 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 867 {
 868         struct ena_adapter *adapter;
 869         struct ena_com_dev *ena_dev;
 870         int rc = 0;
 871
 872         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 873         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 874         adapter = (struct ena_adapter *)(dev->data->dev_private);
 875
 876         ena_dev = &adapter->ena_dev;
 877         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 878
 879         if (mtu > ena_get_mtu_conf(adapter)) {
 880                 RTE_LOG(ERR, PMD,
 881                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 882                         mtu, ena_get_mtu_conf(adapter));
 883                 rc = -EINVAL;
 884                 goto err;
 885         }
 886
 887         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 888         if (rc)
 889                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 890         else
 891                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 892
 893 err:
 894         return rc;
 895 }
 896
 897 static int ena_start(struct rte_eth_dev *dev)
 898 {
 899         struct ena_adapter *adapter =
 900                 (struct ena_adapter *)(dev->data->dev_private);
 901         int rc = 0;
 902
 903         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 904               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 905                 PMD_INIT_LOG(ERR, "API violation");
 906                 return -1;
 907         }
 908
 909         rc = ena_check_valid_conf(adapter);
 910         if (rc)
 911                 return rc;
 912
 913         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 914         if (rc)
 915                 return rc;
 916
 917         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 918         if (rc)
 919                 return rc;
 920
 921         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 922             ETH_MQ_RX_RSS_FLAG) {
 923                 rc = ena_rss_init_default(adapter);
 924                 if (rc)
 925                         return rc;
 926         }
 927
 928         ena_stats_restart(dev);
 929
 930         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 931
 932         return 0;
 933 }
 934
 935 static int ena_queue_restart(struct ena_ring *ring)
 936 {
 937         int rc, bufs_num;
 938
 939         ena_assert_msg(ring->configured == 1,
 940                        "Trying to restart unconfigured queue\n");
 941
 942         ring->next_to_clean = 0;
 943         ring->next_to_use = 0;
 944
 945         if (ring->type == ENA_RING_TYPE_TX)
 946                 return 0;
 947
 948         bufs_num = ring->ring_size - 1;
 949         rc = ena_populate_rx_queue(ring, bufs_num);
 950         if (rc != bufs_num) {
 951                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 952                 return (-1);
 953         }
 954
 955         return 0;
 956 }
 957
 958 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 959                               uint16_t queue_idx,
 960                               uint16_t nb_desc,
 961                               __rte_unused unsigned int socket_id,
 962                               const struct rte_eth_txconf *tx_conf)
 963 {
 964         struct ena_com_create_io_ctx ctx =
 965                 /* policy set to _HOST just to satisfy icc compiler */
 966                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 967                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 968         struct ena_ring *txq = NULL;
 969         struct ena_adapter *adapter =
 970                 (struct ena_adapter *)(dev->data->dev_private);
 971         unsigned int i;
 972         int ena_qid;
 973         int rc;
 974         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 975
 976         txq = &adapter->tx_ring[queue_idx];
 977
 978         if (txq->configured) {
 979                 RTE_LOG(CRIT, PMD,
 980                         "API violation. Queue %d is already configured\n",
 981                         queue_idx);
 982                 return -1;
 983         }
 984
 985         if (!rte_is_power_of_2(nb_desc)) {
 986                 RTE_LOG(ERR, PMD,
 987                         "Unsupported size of RX queue: %d is not a power of 2.",
 988                         nb_desc);
 989                 return -EINVAL;
 990         }
 991
 992         if (nb_desc > adapter->tx_ring_size) {
 993                 RTE_LOG(ERR, PMD,
 994                         "Unsupported size of TX queue (max size: %d)\n",
 995                         adapter->tx_ring_size);
 996                 return -EINVAL;
 997         }
 998
 999         if (tx_conf->txq_flags == ETH_TXQ_FLAGS_IGNORE &&
1000             !ena_are_tx_queue_offloads_allowed(adapter, tx_conf->offloads)) {
1001                 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1002                 return -EINVAL;
1003         }
1004
1005         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1006
1007         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1008         ctx.qid = ena_qid;
1009         ctx.msix_vector = -1; /* admin interrupts not used */
1010         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1011         ctx.queue_size = adapter->tx_ring_size;
1012         ctx.numa_node = ena_cpu_to_node(queue_idx);
1013
1014         rc = ena_com_create_io_queue(ena_dev, &ctx);
1015         if (rc) {
1016                 RTE_LOG(ERR, PMD,
1017                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1018                         queue_idx, ena_qid, rc);
1019         }
1020         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1021         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1022
1023         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1024                                      &txq->ena_com_io_sq,
1025                                      &txq->ena_com_io_cq);
1026         if (rc) {
1027                 RTE_LOG(ERR, PMD,
1028                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1029                         queue_idx, rc);
1030                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1031                 goto err;
1032         }
1033
1034         txq->port_id = dev->data->port_id;
1035         txq->next_to_clean = 0;
1036         txq->next_to_use = 0;
1037         txq->ring_size = nb_desc;
1038
1039         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1040                                           sizeof(struct ena_tx_buffer) *
1041                                           txq->ring_size,
1042                                           RTE_CACHE_LINE_SIZE);
1043         if (!txq->tx_buffer_info) {
1044                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1045                 return -ENOMEM;
1046         }
1047
1048         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1049                                          sizeof(u16) * txq->ring_size,
1050                                          RTE_CACHE_LINE_SIZE);
1051         if (!txq->empty_tx_reqs) {
1052                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1053                 rte_free(txq->tx_buffer_info);
1054                 return -ENOMEM;
1055         }
1056         for (i = 0; i < txq->ring_size; i++)
1057                 txq->empty_tx_reqs[i] = i;
1058
1059         txq->offloads = tx_conf->offloads;
1060
1061         /* Store pointer to this queue in upper layer */
1062         txq->configured = 1;
1063         dev->data->tx_queues[queue_idx] = txq;
1064 err:
1065         return rc;
1066 }
1067
1068 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1069                               uint16_t queue_idx,
1070                               uint16_t nb_desc,
1071                               __rte_unused unsigned int socket_id,
1072                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1073                               struct rte_mempool *mp)
1074 {
1075         struct ena_com_create_io_ctx ctx =
1076                 /* policy set to _HOST just to satisfy icc compiler */
1077                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1078                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1079         struct ena_adapter *adapter =
1080                 (struct ena_adapter *)(dev->data->dev_private);
1081         struct ena_ring *rxq = NULL;
1082         uint16_t ena_qid = 0;
1083         int rc = 0;
1084         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1085
1086         rxq = &adapter->rx_ring[queue_idx];
1087         if (rxq->configured) {
1088                 RTE_LOG(CRIT, PMD,
1089                         "API violation. Queue %d is already configured\n",
1090                         queue_idx);
1091                 return -1;
1092         }
1093
1094         if (!rte_is_power_of_2(nb_desc)) {
1095                 RTE_LOG(ERR, PMD,
1096                         "Unsupported size of TX queue: %d is not a power of 2.",
1097                         nb_desc);
1098                 return -EINVAL;
1099         }
1100
1101         if (nb_desc > adapter->rx_ring_size) {
1102                 RTE_LOG(ERR, PMD,
1103                         "Unsupported size of RX queue (max size: %d)\n",
1104                         adapter->rx_ring_size);
1105                 return -EINVAL;
1106         }
1107
1108         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1109
1110         ctx.qid = ena_qid;
1111         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1112         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1113         ctx.msix_vector = -1; /* admin interrupts not used */
1114         ctx.queue_size = adapter->rx_ring_size;
1115         ctx.numa_node = ena_cpu_to_node(queue_idx);
1116
1117         rc = ena_com_create_io_queue(ena_dev, &ctx);
1118         if (rc)
1119                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1120                         queue_idx, rc);
1121
1122         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1123         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1124
1125         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1126                                      &rxq->ena_com_io_sq,
1127                                      &rxq->ena_com_io_cq);
1128         if (rc) {
1129                 RTE_LOG(ERR, PMD,
1130                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1131                         queue_idx, rc);
1132                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1133         }
1134
1135         rxq->port_id = dev->data->port_id;
1136         rxq->next_to_clean = 0;
1137         rxq->next_to_use = 0;
1138         rxq->ring_size = nb_desc;
1139         rxq->mb_pool = mp;
1140
1141         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1142                                           sizeof(struct rte_mbuf *) * nb_desc,
1143                                           RTE_CACHE_LINE_SIZE);
1144         if (!rxq->rx_buffer_info) {
1145                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1146                 return -ENOMEM;
1147         }
1148
1149         /* Store pointer to this queue in upper layer */
1150         rxq->configured = 1;
1151         dev->data->rx_queues[queue_idx] = rxq;
1152
1153         return rc;
1154 }
1155
1156 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1157 {
1158         unsigned int i;
1159         int rc;
1160         uint16_t ring_size = rxq->ring_size;
1161         uint16_t ring_mask = ring_size - 1;
1162         uint16_t next_to_use = rxq->next_to_use;
1163         uint16_t in_use;
1164         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1165
1166         if (unlikely(!count))
1167                 return 0;
1168
1169         in_use = rxq->next_to_use - rxq->next_to_clean;
1170         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1171
1172         count = RTE_MIN(count,
1173                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1174
1175         /* get resources for incoming packets */
1176         rc = rte_mempool_get_bulk(rxq->mb_pool,
1177                                   (void **)(&mbufs[next_to_use & ring_mask]),
1178                                   count);
1179         if (unlikely(rc < 0)) {
1180                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1181                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1182                 return 0;
1183         }
1184
1185         for (i = 0; i < count; i++) {
1186                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1187                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1188                 struct ena_com_buf ebuf;
1189
1190                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1191                 /* prepare physical address for DMA transaction */
1192                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1193                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1194                 /* pass resource to device */
1195                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1196                                                 &ebuf, next_to_use_masked);
1197                 if (unlikely(rc)) {
1198                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1199                                              count - i);
1200                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1201                         break;
1202                 }
1203                 next_to_use++;
1204         }
1205
1206         /* When we submitted free recources to device... */
1207         if (i > 0) {
1208                 /* ...let HW know that it can fill buffers with data */
1209                 rte_wmb();
1210                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1211
1212                 rxq->next_to_use = next_to_use;
1213         }
1214
1215         return i;
1216 }
1217
1218 static int ena_device_init(struct ena_com_dev *ena_dev,
1219                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1220 {
1221         int rc;
1222         bool readless_supported;
1223
1224         /* Initialize mmio registers */
1225         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1226         if (rc) {
1227                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1228                 return rc;
1229         }
1230
1231         /* The PCIe configuration space revision id indicate if mmio reg
1232          * read is disabled.
1233          */
1234         readless_supported =
1235                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1236                                & ENA_MMIO_DISABLE_REG_READ);
1237         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1238
1239         /* reset device */
1240         rc = ena_com_dev_reset(ena_dev);
1241         if (rc) {
1242                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1243                 goto err_mmio_read_less;
1244         }
1245
1246         /* check FW version */
1247         rc = ena_com_validate_version(ena_dev);
1248         if (rc) {
1249                 RTE_LOG(ERR, PMD, "device version is too low\n");
1250                 goto err_mmio_read_less;
1251         }
1252
1253         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1254
1255         /* ENA device administration layer init */
1256         rc = ena_com_admin_init(ena_dev, NULL, true);
1257         if (rc) {
1258                 RTE_LOG(ERR, PMD,
1259                         "cannot initialize ena admin queue with device\n");
1260                 goto err_mmio_read_less;
1261         }
1262
1263         /* To enable the msix interrupts the driver needs to know the number
1264          * of queues. So the driver uses polling mode to retrieve this
1265          * information.
1266          */
1267         ena_com_set_admin_polling_mode(ena_dev, true);
1268
1269         ena_config_host_info(ena_dev);
1270
1271         /* Get Device Attributes and features */
1272         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1273         if (rc) {
1274                 RTE_LOG(ERR, PMD,
1275                         "cannot get attribute for ena device rc= %d\n", rc);
1276                 goto err_admin_init;
1277         }
1278
1279         return 0;
1280
1281 err_admin_init:
1282         ena_com_admin_destroy(ena_dev);
1283
1284 err_mmio_read_less:
1285         ena_com_mmio_reg_read_request_destroy(ena_dev);
1286
1287         return rc;
1288 }
1289
1290 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1291 {
1292         struct rte_pci_device *pci_dev;
1293         struct ena_adapter *adapter =
1294                 (struct ena_adapter *)(eth_dev->data->dev_private);
1295         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1296         struct ena_com_dev_get_features_ctx get_feat_ctx;
1297         int queue_size, rc;
1298
1299         static int adapters_found;
1300
1301         memset(adapter, 0, sizeof(struct ena_adapter));
1302         ena_dev = &adapter->ena_dev;
1303
1304         eth_dev->dev_ops = &ena_dev_ops;
1305         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1306         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1307         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1308         adapter->rte_eth_dev_data = eth_dev->data;
1309         adapter->rte_dev = eth_dev;
1310
1311         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1312                 return 0;
1313
1314         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315         adapter->pdev = pci_dev;
1316
1317         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1318                      pci_dev->addr.domain,
1319                      pci_dev->addr.bus,
1320                      pci_dev->addr.devid,
1321                      pci_dev->addr.function);
1322
1323         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1324         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1325
1326         /* Present ENA_MEM_BAR indicates available LLQ mode.
1327          * Use corresponding policy
1328          */
1329         if (adapter->dev_mem_base)
1330                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1331         else if (adapter->regs)
1332                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1333         else
1334                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1335                              ENA_REGS_BAR);
1336
1337         ena_dev->reg_bar = adapter->regs;
1338         ena_dev->dmadev = adapter->pdev;
1339
1340         adapter->id_number = adapters_found;
1341
1342         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1343                  adapter->id_number);
1344
1345         /* device specific initialization routine */
1346         rc = ena_device_init(ena_dev, &get_feat_ctx);
1347         if (rc) {
1348                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1349                 return -1;
1350         }
1351
1352         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1353                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1354                         PMD_INIT_LOG(ERR,
1355                                      "Trying to use LLQ but llq_num is 0.\n"
1356                                      "Fall back into regular queues.");
1357                         ena_dev->tx_mem_queue_type =
1358                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1359                         adapter->num_queues =
1360                                 get_feat_ctx.max_queues.max_sq_num;
1361                 } else {
1362                         adapter->num_queues =
1363                                 get_feat_ctx.max_queues.max_llq_num;
1364                 }
1365         } else {
1366                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1367         }
1368
1369         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1370         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1371                 return -EFAULT;
1372
1373         adapter->tx_ring_size = queue_size;
1374         adapter->rx_ring_size = queue_size;
1375
1376         /* prepare ring structures */
1377         ena_init_rings(adapter);
1378
1379         ena_config_debug_area(adapter);
1380
1381         /* Set max MTU for this device */
1382         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1383
1384         /* set device support for TSO */
1385         adapter->tso4_supported = get_feat_ctx.offload.tx &
1386                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1387
1388         /* Copy MAC address and point DPDK to it */
1389         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1390         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1391                         (struct ether_addr *)adapter->mac_addr);
1392
1393         adapter->drv_stats = rte_zmalloc("adapter stats",
1394                                          sizeof(*adapter->drv_stats),
1395                                          RTE_CACHE_LINE_SIZE);
1396         if (!adapter->drv_stats) {
1397                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1398                 return -ENOMEM;
1399         }
1400
1401         adapters_found++;
1402         adapter->state = ENA_ADAPTER_STATE_INIT;
1403
1404         return 0;
1405 }
1406
1407 static int ena_dev_configure(struct rte_eth_dev *dev)
1408 {
1409         struct ena_adapter *adapter =
1410                 (struct ena_adapter *)(dev->data->dev_private);
1411         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
1412
1413         if ((tx_offloads & adapter->tx_supported_offloads) != tx_offloads) {
1414                 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported "
1415                     "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1416                     tx_offloads, adapter->tx_supported_offloads);
1417                 return -ENOTSUP;
1418         }
1419
1420         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1421               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1422                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1423                              adapter->state);
1424                 return -1;
1425         }
1426
1427         switch (adapter->state) {
1428         case ENA_ADAPTER_STATE_INIT:
1429         case ENA_ADAPTER_STATE_STOPPED:
1430                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1431                 break;
1432         case ENA_ADAPTER_STATE_CONFIG:
1433                 RTE_LOG(WARNING, PMD,
1434                         "Ivalid driver state while trying to configure device\n");
1435                 break;
1436         default:
1437                 break;
1438         }
1439
1440         adapter->tx_selected_offloads = tx_offloads;
1441         return 0;
1442 }
1443
1444 static void ena_init_rings(struct ena_adapter *adapter)
1445 {
1446         int i;
1447
1448         for (i = 0; i < adapter->num_queues; i++) {
1449                 struct ena_ring *ring = &adapter->tx_ring[i];
1450
1451                 ring->configured = 0;
1452                 ring->type = ENA_RING_TYPE_TX;
1453                 ring->adapter = adapter;
1454                 ring->id = i;
1455                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1456                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1457         }
1458
1459         for (i = 0; i < adapter->num_queues; i++) {
1460                 struct ena_ring *ring = &adapter->rx_ring[i];
1461
1462                 ring->configured = 0;
1463                 ring->type = ENA_RING_TYPE_RX;
1464                 ring->adapter = adapter;
1465                 ring->id = i;
1466         }
1467 }
1468
1469 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
1470                                               uint64_t offloads)
1471 {
1472         uint64_t port_offloads = adapter->tx_selected_offloads;
1473
1474         /* Check if port supports all requested offloads.
1475          * True if all offloads selected for queue are set for port.
1476          */
1477         if ((offloads & port_offloads) != offloads)
1478                 return false;
1479         return true;
1480 }
1481
1482 static void ena_infos_get(struct rte_eth_dev *dev,
1483                           struct rte_eth_dev_info *dev_info)
1484 {
1485         struct ena_adapter *adapter;
1486         struct ena_com_dev *ena_dev;
1487         struct ena_com_dev_get_features_ctx feat;
1488         uint64_t rx_feat = 0, tx_feat = 0;
1489         int rc = 0;
1490
1491         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1492         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1493         adapter = (struct ena_adapter *)(dev->data->dev_private);
1494
1495         ena_dev = &adapter->ena_dev;
1496         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1497
1498         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1499
1500         dev_info->speed_capa =
1501                         ETH_LINK_SPEED_1G   |
1502                         ETH_LINK_SPEED_2_5G |
1503                         ETH_LINK_SPEED_5G   |
1504                         ETH_LINK_SPEED_10G  |
1505                         ETH_LINK_SPEED_25G  |
1506                         ETH_LINK_SPEED_40G  |
1507                         ETH_LINK_SPEED_50G  |
1508                         ETH_LINK_SPEED_100G;
1509
1510         /* Get supported features from HW */
1511         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1512         if (unlikely(rc)) {
1513                 RTE_LOG(ERR, PMD,
1514                         "Cannot get attribute for ena device rc= %d\n", rc);
1515                 return;
1516         }
1517
1518         /* Set Tx & Rx features available for device */
1519         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1520                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1521
1522         if (feat.offload.tx &
1523             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1524                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1525                         DEV_TX_OFFLOAD_UDP_CKSUM |
1526                         DEV_TX_OFFLOAD_TCP_CKSUM;
1527
1528         if (feat.offload.rx_supported &
1529             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1530                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1531                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1532                         DEV_RX_OFFLOAD_TCP_CKSUM;
1533
1534         /* Inform framework about available features */
1535         dev_info->rx_offload_capa = rx_feat;
1536         dev_info->tx_offload_capa = tx_feat;
1537         dev_info->tx_queue_offload_capa = tx_feat;
1538
1539         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1540         dev_info->max_rx_pktlen  = adapter->max_mtu;
1541         dev_info->max_mac_addrs = 1;
1542
1543         dev_info->max_rx_queues = adapter->num_queues;
1544         dev_info->max_tx_queues = adapter->num_queues;
1545         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1546
1547         adapter->tx_supported_offloads = tx_feat;
1548 }
1549
1550 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1551                                   uint16_t nb_pkts)
1552 {
1553         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1554         unsigned int ring_size = rx_ring->ring_size;
1555         unsigned int ring_mask = ring_size - 1;
1556         uint16_t next_to_clean = rx_ring->next_to_clean;
1557         uint16_t desc_in_use = 0;
1558         unsigned int recv_idx = 0;
1559         struct rte_mbuf *mbuf = NULL;
1560         struct rte_mbuf *mbuf_head = NULL;
1561         struct rte_mbuf *mbuf_prev = NULL;
1562         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1563         unsigned int completed;
1564
1565         struct ena_com_rx_ctx ena_rx_ctx;
1566         int rc = 0;
1567
1568         /* Check adapter state */
1569         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1570                 RTE_LOG(ALERT, PMD,
1571                         "Trying to receive pkts while device is NOT running\n");
1572                 return 0;
1573         }
1574
1575         desc_in_use = rx_ring->next_to_use - next_to_clean;
1576         if (unlikely(nb_pkts > desc_in_use))
1577                 nb_pkts = desc_in_use;
1578
1579         for (completed = 0; completed < nb_pkts; completed++) {
1580                 int segments = 0;
1581
1582                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1583                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1584                 ena_rx_ctx.descs = 0;
1585                 /* receive packet context */
1586                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1587                                     rx_ring->ena_com_io_sq,
1588                                     &ena_rx_ctx);
1589                 if (unlikely(rc)) {
1590                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1591                         return 0;
1592                 }
1593
1594                 if (unlikely(ena_rx_ctx.descs == 0))
1595                         break;
1596
1597                 while (segments < ena_rx_ctx.descs) {
1598                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1599                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1600                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1601                         mbuf->refcnt = 1;
1602                         mbuf->next = NULL;
1603                         if (segments == 0) {
1604                                 mbuf->nb_segs = ena_rx_ctx.descs;
1605                                 mbuf->port = rx_ring->port_id;
1606                                 mbuf->pkt_len = 0;
1607                                 mbuf_head = mbuf;
1608                         } else {
1609                                 /* for multi-segment pkts create mbuf chain */
1610                                 mbuf_prev->next = mbuf;
1611                         }
1612                         mbuf_head->pkt_len += mbuf->data_len;
1613
1614                         mbuf_prev = mbuf;
1615                         segments++;
1616                         next_to_clean++;
1617                 }
1618
1619                 /* fill mbuf attributes if any */
1620                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1621                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1622
1623                 /* pass to DPDK application head mbuf */
1624                 rx_pkts[recv_idx] = mbuf_head;
1625                 recv_idx++;
1626         }
1627
1628         rx_ring->next_to_clean = next_to_clean;
1629
1630         desc_in_use = desc_in_use - completed + 1;
1631         /* Burst refill to save doorbells, memory barriers, const interval */
1632         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1633                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1634
1635         return recv_idx;
1636 }
1637
1638 static uint16_t
1639 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1640                 uint16_t nb_pkts)
1641 {
1642         int32_t ret;
1643         uint32_t i;
1644         struct rte_mbuf *m;
1645         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1646         struct ipv4_hdr *ip_hdr;
1647         uint64_t ol_flags;
1648         uint16_t frag_field;
1649
1650         for (i = 0; i != nb_pkts; i++) {
1651                 m = tx_pkts[i];
1652                 ol_flags = m->ol_flags;
1653
1654                 if (!(ol_flags & PKT_TX_IPV4))
1655                         continue;
1656
1657                 /* If there was not L2 header length specified, assume it is
1658                  * length of the ethernet header.
1659                  */
1660                 if (unlikely(m->l2_len == 0))
1661                         m->l2_len = sizeof(struct ether_hdr);
1662
1663                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1664                                                  m->l2_len);
1665                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1666
1667                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1668                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1669
1670                         /* If IPv4 header has DF flag enabled and TSO support is
1671                          * disabled, partial chcecksum should not be calculated.
1672                          */
1673                         if (!tx_ring->adapter->tso4_supported)
1674                                 continue;
1675                 }
1676
1677                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1678                                 (ol_flags & PKT_TX_L4_MASK) ==
1679                                 PKT_TX_SCTP_CKSUM) {
1680                         rte_errno = -ENOTSUP;
1681                         return i;
1682                 }
1683
1684 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1685                 ret = rte_validate_tx_offload(m);
1686                 if (ret != 0) {
1687                         rte_errno = ret;
1688                         return i;
1689                 }
1690 #endif
1691
1692                 /* In case we are supposed to TSO and have DF not set (DF=0)
1693                  * hardware must be provided with partial checksum, otherwise
1694                  * it will take care of necessary calculations.
1695                  */
1696
1697                 ret = rte_net_intel_cksum_flags_prepare(m,
1698                         ol_flags & ~PKT_TX_TCP_SEG);
1699                 if (ret != 0) {
1700                         rte_errno = ret;
1701                         return i;
1702                 }
1703         }
1704
1705         return i;
1706 }
1707
1708 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1709                                   uint16_t nb_pkts)
1710 {
1711         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1712         uint16_t next_to_use = tx_ring->next_to_use;
1713         uint16_t next_to_clean = tx_ring->next_to_clean;
1714         struct rte_mbuf *mbuf;
1715         unsigned int ring_size = tx_ring->ring_size;
1716         unsigned int ring_mask = ring_size - 1;
1717         struct ena_com_tx_ctx ena_tx_ctx;
1718         struct ena_tx_buffer *tx_info;
1719         struct ena_com_buf *ebuf;
1720         uint16_t rc, req_id, total_tx_descs = 0;
1721         uint16_t sent_idx = 0, empty_tx_reqs;
1722         int nb_hw_desc;
1723
1724         /* Check adapter state */
1725         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1726                 RTE_LOG(ALERT, PMD,
1727                         "Trying to xmit pkts while device is NOT running\n");
1728                 return 0;
1729         }
1730
1731         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1732         if (nb_pkts > empty_tx_reqs)
1733                 nb_pkts = empty_tx_reqs;
1734
1735         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1736                 mbuf = tx_pkts[sent_idx];
1737
1738                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1739                 tx_info = &tx_ring->tx_buffer_info[req_id];
1740                 tx_info->mbuf = mbuf;
1741                 tx_info->num_of_bufs = 0;
1742                 ebuf = tx_info->bufs;
1743
1744                 /* Prepare TX context */
1745                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1746                 memset(&ena_tx_ctx.ena_meta, 0x0,
1747                        sizeof(struct ena_com_tx_meta));
1748                 ena_tx_ctx.ena_bufs = ebuf;
1749                 ena_tx_ctx.req_id = req_id;
1750                 if (tx_ring->tx_mem_queue_type ==
1751                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1752                         /* prepare the push buffer with
1753                          * virtual address of the data
1754                          */
1755                         ena_tx_ctx.header_len =
1756                                 RTE_MIN(mbuf->data_len,
1757                                         tx_ring->tx_max_header_size);
1758                         ena_tx_ctx.push_header =
1759                                 (void *)((char *)mbuf->buf_addr +
1760                                          mbuf->data_off);
1761                 } /* there's no else as we take advantage of memset zeroing */
1762
1763                 /* Set TX offloads flags, if applicable */
1764                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1765
1766                 if (unlikely(mbuf->ol_flags &
1767                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1768                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1769
1770                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1771
1772                 /* Process first segment taking into
1773                  * consideration pushed header
1774                  */
1775                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1776                         ebuf->paddr = mbuf->buf_iova +
1777                                       mbuf->data_off +
1778                                       ena_tx_ctx.header_len;
1779                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1780                         ebuf++;
1781                         tx_info->num_of_bufs++;
1782                 }
1783
1784                 while ((mbuf = mbuf->next) != NULL) {
1785                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1786                         ebuf->len = mbuf->data_len;
1787                         ebuf++;
1788                         tx_info->num_of_bufs++;
1789                 }
1790
1791                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1792
1793                 /* Write data to device */
1794                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1795                                         &ena_tx_ctx, &nb_hw_desc);
1796                 if (unlikely(rc))
1797                         break;
1798
1799                 tx_info->tx_descs = nb_hw_desc;
1800
1801                 next_to_use++;
1802         }
1803
1804         /* If there are ready packets to be xmitted... */
1805         if (sent_idx > 0) {
1806                 /* ...let HW do its best :-) */
1807                 rte_wmb();
1808                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1809
1810                 tx_ring->next_to_use = next_to_use;
1811         }
1812
1813         /* Clear complete packets  */
1814         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1815                 /* Get Tx info & store how many descs were processed  */
1816                 tx_info = &tx_ring->tx_buffer_info[req_id];
1817                 total_tx_descs += tx_info->tx_descs;
1818
1819                 /* Free whole mbuf chain  */
1820                 mbuf = tx_info->mbuf;
1821                 rte_pktmbuf_free(mbuf);
1822                 tx_info->mbuf = NULL;
1823
1824                 /* Put back descriptor to the ring for reuse */
1825                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1826                 next_to_clean++;
1827
1828                 /* If too many descs to clean, leave it for another run */
1829                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1830                         break;
1831         }
1832
1833         if (total_tx_descs > 0) {
1834                 /* acknowledge completion of sent packets */
1835                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1836                 tx_ring->next_to_clean = next_to_clean;
1837         }
1838
1839         return sent_idx;
1840 }
1841
1842 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1843         struct rte_pci_device *pci_dev)
1844 {
1845         return rte_eth_dev_pci_generic_probe(pci_dev,
1846                 sizeof(struct ena_adapter), eth_ena_dev_init);
1847 }
1848
1849 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1850 {
1851         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1852 }
1853
1854 static struct rte_pci_driver rte_ena_pmd = {
1855         .id_table = pci_id_ena_map,
1856         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1857         .probe = eth_ena_pci_probe,
1858         .remove = eth_ena_pci_remove,
1859 };
1860
1861 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1862 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1863 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1864
1865 RTE_INIT(ena_init_log);
1866 static void
1867 ena_init_log(void)
1868 {
1869         ena_logtype_init = rte_log_register("pmd.ena.init");
1870         if (ena_logtype_init >= 0)
1871                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1872         ena_logtype_driver = rte_log_register("pmd.ena.driver");
1873         if (ena_logtype_driver >= 0)
1874                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1875 }