drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_ether.h>
   8 #include <rte_ethdev_driver.h>
   9 #include <rte_ethdev_pci.h>
  10 #include <rte_tcp.h>
  11 #include <rte_atomic.h>
  12 #include <rte_dev.h>
  13 #include <rte_errno.h>
  14 #include <rte_version.h>
  15 #include <rte_net.h>
  16 #include <rte_kvargs.h>
  17
  18 #include "ena_ethdev.h"
  19 #include "ena_logs.h"
  20 #include "ena_platform.h"
  21 #include "ena_com.h"
  22 #include "ena_eth_com.h"
  23
  24 #include <ena_common_defs.h>
  25 #include <ena_regs_defs.h>
  26 #include <ena_admin_defs.h>
  27 #include <ena_eth_io_defs.h>
  28
  29 #define DRV_MODULE_VER_MAJOR    2
  30 #define DRV_MODULE_VER_MINOR    1
  31 #define DRV_MODULE_VER_SUBMINOR 0
  32
  33 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  34 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  35 /*reverse version of ENA_IO_RXQ_IDX*/
  36 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  37
  38 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  39 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  40
  41 #define GET_L4_HDR_LEN(mbuf)                                    \
  42         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  43                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  44
  45 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  46 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  47 #define ENA_HASH_KEY_SIZE       40
  48 #define ETH_GSTRING_LEN 32
  49
  50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  51
  52 #define ENA_MIN_RING_DESC       128
  53
  54 enum ethtool_stringset {
  55         ETH_SS_TEST             = 0,
  56         ETH_SS_STATS,
  57 };
  58
  59 struct ena_stats {
  60         char name[ETH_GSTRING_LEN];
  61         int stat_offset;
  62 };
  63
  64 #define ENA_STAT_ENTRY(stat, stat_type) { \
  65         .name = #stat, \
  66         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  67 }
  68
  69 #define ENA_STAT_RX_ENTRY(stat) \
  70         ENA_STAT_ENTRY(stat, rx)
  71
  72 #define ENA_STAT_TX_ENTRY(stat) \
  73         ENA_STAT_ENTRY(stat, tx)
  74
  75 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  76         ENA_STAT_ENTRY(stat, dev)
  77
  78 /* Device arguments */
  79 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  80
  81 /*
  82  * Each rte_memzone should have unique name.
  83  * To satisfy it, count number of allocation and add it to name.
  84  */
  85 rte_atomic32_t ena_alloc_cnt;
  86
  87 static const struct ena_stats ena_stats_global_strings[] = {
  88         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  89         ENA_STAT_GLOBAL_ENTRY(dev_start),
  90         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  91         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  92 };
  93
  94 static const struct ena_stats ena_stats_tx_strings[] = {
  95         ENA_STAT_TX_ENTRY(cnt),
  96         ENA_STAT_TX_ENTRY(bytes),
  97         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  98         ENA_STAT_TX_ENTRY(linearize),
  99         ENA_STAT_TX_ENTRY(linearize_failed),
 100         ENA_STAT_TX_ENTRY(tx_poll),
 101         ENA_STAT_TX_ENTRY(doorbells),
 102         ENA_STAT_TX_ENTRY(bad_req_id),
 103         ENA_STAT_TX_ENTRY(available_desc),
 104 };
 105
 106 static const struct ena_stats ena_stats_rx_strings[] = {
 107         ENA_STAT_RX_ENTRY(cnt),
 108         ENA_STAT_RX_ENTRY(bytes),
 109         ENA_STAT_RX_ENTRY(refill_partial),
 110         ENA_STAT_RX_ENTRY(bad_csum),
 111         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 112         ENA_STAT_RX_ENTRY(bad_desc_num),
 113         ENA_STAT_RX_ENTRY(bad_req_id),
 114 };
 115
 116 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 117 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 118 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 119
 120 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 121                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 122                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 123                         DEV_TX_OFFLOAD_TCP_TSO)
 124 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 125                        PKT_TX_IP_CKSUM |\
 126                        PKT_TX_TCP_SEG)
 127
 128 /** Vendor ID used by Amazon devices */
 129 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 130 /** Amazon devices */
 131 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 132 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 133
 134 #define ENA_TX_OFFLOAD_MASK     (\
 135         PKT_TX_L4_MASK |         \
 136         PKT_TX_IPV6 |            \
 137         PKT_TX_IPV4 |            \
 138         PKT_TX_IP_CKSUM |        \
 139         PKT_TX_TCP_SEG)
 140
 141 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 142         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 143
 144 int ena_logtype_init;
 145 int ena_logtype_driver;
 146
 147 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
 148 int ena_logtype_rx;
 149 #endif
 150 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
 151 int ena_logtype_tx;
 152 #endif
 153 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
 154 int ena_logtype_tx_free;
 155 #endif
 156 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
 157 int ena_logtype_com;
 158 #endif
 159
 160 static const struct rte_pci_id pci_id_ena_map[] = {
 161         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 162         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 163         { .device_id = 0 },
 164 };
 165
 166 static struct ena_aenq_handlers aenq_handlers;
 167
 168 static int ena_device_init(struct ena_com_dev *ena_dev,
 169                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 170                            bool *wd_state);
 171 static int ena_dev_configure(struct rte_eth_dev *dev);
 172 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 173         struct ena_tx_buffer *tx_info,
 174         struct rte_mbuf *mbuf,
 175         void **push_header,
 176         uint16_t *header_len);
 177 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 178 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 179 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 180                                   uint16_t nb_pkts);
 181 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 182                 uint16_t nb_pkts);
 183 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 184                               uint16_t nb_desc, unsigned int socket_id,
 185                               const struct rte_eth_txconf *tx_conf);
 186 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 187                               uint16_t nb_desc, unsigned int socket_id,
 188                               const struct rte_eth_rxconf *rx_conf,
 189                               struct rte_mempool *mp);
 190 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 191 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 192                                     struct ena_com_rx_buf_info *ena_bufs,
 193                                     uint32_t descs,
 194                                     uint16_t *next_to_clean,
 195                                     uint8_t offset);
 196 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 197                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 198 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 199                                   struct rte_mbuf *mbuf, uint16_t id);
 200 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 201 static void ena_init_rings(struct ena_adapter *adapter,
 202                            bool disable_meta_caching);
 203 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204 static int ena_start(struct rte_eth_dev *dev);
 205 static void ena_stop(struct rte_eth_dev *dev);
 206 static void ena_close(struct rte_eth_dev *dev);
 207 static int ena_dev_reset(struct rte_eth_dev *dev);
 208 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 209 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 210 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 211 static void ena_rx_queue_release(void *queue);
 212 static void ena_tx_queue_release(void *queue);
 213 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 214 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 215 static int ena_link_update(struct rte_eth_dev *dev,
 216                            int wait_to_complete);
 217 static int ena_create_io_queue(struct ena_ring *ring);
 218 static void ena_queue_stop(struct ena_ring *ring);
 219 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 220                               enum ena_ring_type ring_type);
 221 static int ena_queue_start(struct ena_ring *ring);
 222 static int ena_queue_start_all(struct rte_eth_dev *dev,
 223                                enum ena_ring_type ring_type);
 224 static void ena_stats_restart(struct rte_eth_dev *dev);
 225 static int ena_infos_get(struct rte_eth_dev *dev,
 226                          struct rte_eth_dev_info *dev_info);
 227 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 228                                struct rte_eth_rss_reta_entry64 *reta_conf,
 229                                uint16_t reta_size);
 230 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 231                               struct rte_eth_rss_reta_entry64 *reta_conf,
 232                               uint16_t reta_size);
 233 static void ena_interrupt_handler_rte(void *cb_arg);
 234 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 235 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 236 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 237 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 238                                 struct rte_eth_xstat_name *xstats_names,
 239                                 unsigned int n);
 240 static int ena_xstats_get(struct rte_eth_dev *dev,
 241                           struct rte_eth_xstat *stats,
 242                           unsigned int n);
 243 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 244                                 const uint64_t *ids,
 245                                 uint64_t *values,
 246                                 unsigned int n);
 247 static int ena_process_bool_devarg(const char *key,
 248                                    const char *value,
 249                                    void *opaque);
 250 static int ena_parse_devargs(struct ena_adapter *adapter,
 251                              struct rte_devargs *devargs);
 252
 253 static const struct eth_dev_ops ena_dev_ops = {
 254         .dev_configure        = ena_dev_configure,
 255         .dev_infos_get        = ena_infos_get,
 256         .rx_queue_setup       = ena_rx_queue_setup,
 257         .tx_queue_setup       = ena_tx_queue_setup,
 258         .dev_start            = ena_start,
 259         .dev_stop             = ena_stop,
 260         .link_update          = ena_link_update,
 261         .stats_get            = ena_stats_get,
 262         .xstats_get_names     = ena_xstats_get_names,
 263         .xstats_get           = ena_xstats_get,
 264         .xstats_get_by_id     = ena_xstats_get_by_id,
 265         .mtu_set              = ena_mtu_set,
 266         .rx_queue_release     = ena_rx_queue_release,
 267         .tx_queue_release     = ena_tx_queue_release,
 268         .dev_close            = ena_close,
 269         .dev_reset            = ena_dev_reset,
 270         .reta_update          = ena_rss_reta_update,
 271         .reta_query           = ena_rss_reta_query,
 272 };
 273
 274 void ena_rss_key_fill(void *key, size_t size)
 275 {
 276         static bool key_generated;
 277         static uint8_t default_key[ENA_HASH_KEY_SIZE];
 278         size_t i;
 279
 280         RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
 281
 282         if (!key_generated) {
 283                 for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
 284                         default_key[i] = rte_rand() & 0xff;
 285                 key_generated = true;
 286         }
 287
 288         rte_memcpy(key, default_key, size);
 289 }
 290
 291 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 292                                        struct ena_com_rx_ctx *ena_rx_ctx)
 293 {
 294         uint64_t ol_flags = 0;
 295         uint32_t packet_type = 0;
 296
 297         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 298                 packet_type |= RTE_PTYPE_L4_TCP;
 299         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 300                 packet_type |= RTE_PTYPE_L4_UDP;
 301
 302         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 303                 packet_type |= RTE_PTYPE_L3_IPV4;
 304         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 305                 packet_type |= RTE_PTYPE_L3_IPV6;
 306
 307         if (!ena_rx_ctx->l4_csum_checked)
 308                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 309         else
 310                 if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
 311                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 312                 else
 313                         ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 314
 315         if (unlikely(ena_rx_ctx->l3_csum_err))
 316                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 317
 318         mbuf->ol_flags = ol_flags;
 319         mbuf->packet_type = packet_type;
 320 }
 321
 322 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 323                                        struct ena_com_tx_ctx *ena_tx_ctx,
 324                                        uint64_t queue_offloads,
 325                                        bool disable_meta_caching)
 326 {
 327         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 328
 329         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 330             (queue_offloads & QUEUE_OFFLOADS)) {
 331                 /* check if TSO is required */
 332                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 333                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 334                         ena_tx_ctx->tso_enable = true;
 335
 336                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 337                 }
 338
 339                 /* check if L3 checksum is needed */
 340                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 341                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 342                         ena_tx_ctx->l3_csum_enable = true;
 343
 344                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 345                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 346                 } else {
 347                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 348
 349                         /* set don't fragment (DF) flag */
 350                         if (mbuf->packet_type &
 351                                 (RTE_PTYPE_L4_NONFRAG
 352                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 353                                 ena_tx_ctx->df = true;
 354                 }
 355
 356                 /* check if L4 checksum is needed */
 357                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 358                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 359                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 360                         ena_tx_ctx->l4_csum_enable = true;
 361                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 362                                 PKT_TX_UDP_CKSUM) &&
 363                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 365                         ena_tx_ctx->l4_csum_enable = true;
 366                 } else {
 367                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 368                         ena_tx_ctx->l4_csum_enable = false;
 369                 }
 370
 371                 ena_meta->mss = mbuf->tso_segsz;
 372                 ena_meta->l3_hdr_len = mbuf->l3_len;
 373                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 374
 375                 ena_tx_ctx->meta_valid = true;
 376         } else if (disable_meta_caching) {
 377                 memset(ena_meta, 0, sizeof(*ena_meta));
 378                 ena_tx_ctx->meta_valid = true;
 379         } else {
 380                 ena_tx_ctx->meta_valid = false;
 381         }
 382 }
 383
 384 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 385 {
 386         if (likely(req_id < rx_ring->ring_size))
 387                 return 0;
 388
 389         PMD_DRV_LOG(ERR, "Invalid rx req_id: %hu\n", req_id);
 390
 391         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 392         rx_ring->adapter->trigger_reset = true;
 393         ++rx_ring->rx_stats.bad_req_id;
 394
 395         return -EFAULT;
 396 }
 397
 398 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 399 {
 400         struct ena_tx_buffer *tx_info = NULL;
 401
 402         if (likely(req_id < tx_ring->ring_size)) {
 403                 tx_info = &tx_ring->tx_buffer_info[req_id];
 404                 if (likely(tx_info->mbuf))
 405                         return 0;
 406         }
 407
 408         if (tx_info)
 409                 PMD_DRV_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 410         else
 411                 PMD_DRV_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 412
 413         /* Trigger device reset */
 414         ++tx_ring->tx_stats.bad_req_id;
 415         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 416         tx_ring->adapter->trigger_reset = true;
 417         return -EFAULT;
 418 }
 419
 420 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 421 {
 422         struct ena_admin_host_info *host_info;
 423         int rc;
 424
 425         /* Allocate only the host info */
 426         rc = ena_com_allocate_host_info(ena_dev);
 427         if (rc) {
 428                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 429                 return;
 430         }
 431
 432         host_info = ena_dev->host_attr.host_info;
 433
 434         host_info->os_type = ENA_ADMIN_OS_DPDK;
 435         host_info->kernel_ver = RTE_VERSION;
 436         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 437                 sizeof(host_info->kernel_ver_str));
 438         host_info->os_dist = RTE_VERSION;
 439         strlcpy((char *)host_info->os_dist_str, rte_version(),
 440                 sizeof(host_info->os_dist_str));
 441         host_info->driver_version =
 442                 (DRV_MODULE_VER_MAJOR) |
 443                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 444                 (DRV_MODULE_VER_SUBMINOR <<
 445                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 446         host_info->num_cpus = rte_lcore_count();
 447
 448         host_info->driver_supported_features =
 449                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
 450
 451         rc = ena_com_set_host_attributes(ena_dev);
 452         if (rc) {
 453                 if (rc == -ENA_COM_UNSUPPORTED)
 454                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 455                 else
 456                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 457
 458                 goto err;
 459         }
 460
 461         return;
 462
 463 err:
 464         ena_com_delete_host_info(ena_dev);
 465 }
 466
 467 /* This function calculates the number of xstats based on the current config */
 468 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev)
 469 {
 470         return ENA_STATS_ARRAY_GLOBAL +
 471                 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 472                 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 473 }
 474
 475 static void ena_config_debug_area(struct ena_adapter *adapter)
 476 {
 477         u32 debug_area_size;
 478         int rc, ss_count;
 479
 480         ss_count = ena_xstats_calc_num(adapter->rte_dev);
 481
 482         /* allocate 32 bytes for each string and 64bit for the value */
 483         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 484
 485         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 486         if (rc) {
 487                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 488                 return;
 489         }
 490
 491         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 492         if (rc) {
 493                 if (rc == -ENA_COM_UNSUPPORTED)
 494                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 495                 else
 496                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 497
 498                 goto err;
 499         }
 500
 501         return;
 502 err:
 503         ena_com_delete_debug_area(&adapter->ena_dev);
 504 }
 505
 506 static void ena_close(struct rte_eth_dev *dev)
 507 {
 508         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 509         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 510         struct ena_adapter *adapter = dev->data->dev_private;
 511
 512         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 513                 ena_stop(dev);
 514         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 515
 516         ena_rx_queue_release_all(dev);
 517         ena_tx_queue_release_all(dev);
 518
 519         rte_free(adapter->drv_stats);
 520         adapter->drv_stats = NULL;
 521
 522         rte_intr_disable(intr_handle);
 523         rte_intr_callback_unregister(intr_handle,
 524                                      ena_interrupt_handler_rte,
 525                                      adapter);
 526
 527         /*
 528          * MAC is not allocated dynamically. Setting NULL should prevent from
 529          * release of the resource in the rte_eth_dev_release_port().
 530          */
 531         dev->data->mac_addrs = NULL;
 532 }
 533
 534 static int
 535 ena_dev_reset(struct rte_eth_dev *dev)
 536 {
 537         int rc = 0;
 538
 539         ena_destroy_device(dev);
 540         rc = eth_ena_dev_init(dev);
 541         if (rc)
 542                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 543
 544         return rc;
 545 }
 546
 547 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 548                                struct rte_eth_rss_reta_entry64 *reta_conf,
 549                                uint16_t reta_size)
 550 {
 551         struct ena_adapter *adapter = dev->data->dev_private;
 552         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 553         int rc, i;
 554         u16 entry_value;
 555         int conf_idx;
 556         int idx;
 557
 558         if ((reta_size == 0) || (reta_conf == NULL))
 559                 return -EINVAL;
 560
 561         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 562                 PMD_DRV_LOG(WARNING,
 563                         "indirection table %d is bigger than supported (%d)\n",
 564                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 565                 return -EINVAL;
 566         }
 567
 568         for (i = 0 ; i < reta_size ; i++) {
 569                 /* each reta_conf is for 64 entries.
 570                  * to support 128 we use 2 conf of 64
 571                  */
 572                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 573                 idx = i % RTE_RETA_GROUP_SIZE;
 574                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 575                         entry_value =
 576                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 577
 578                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 579                                                                i,
 580                                                                entry_value);
 581                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 582                                 PMD_DRV_LOG(ERR,
 583                                         "Cannot fill indirect table\n");
 584                                 return rc;
 585                         }
 586                 }
 587         }
 588
 589         rc = ena_com_indirect_table_set(ena_dev);
 590         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 591                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 592                 return rc;
 593         }
 594
 595         PMD_DRV_LOG(DEBUG, "%s(): RSS configured %d entries  for port %d\n",
 596                 __func__, reta_size, adapter->rte_dev->data->port_id);
 597
 598         return 0;
 599 }
 600
 601 /* Query redirection table. */
 602 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 603                               struct rte_eth_rss_reta_entry64 *reta_conf,
 604                               uint16_t reta_size)
 605 {
 606         struct ena_adapter *adapter = dev->data->dev_private;
 607         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 608         int rc;
 609         int i;
 610         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 611         int reta_conf_idx;
 612         int reta_idx;
 613
 614         if (reta_size == 0 || reta_conf == NULL ||
 615             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 616                 return -EINVAL;
 617
 618         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 619         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 620                 PMD_DRV_LOG(ERR, "cannot get indirect table\n");
 621                 return -ENOTSUP;
 622         }
 623
 624         for (i = 0 ; i < reta_size ; i++) {
 625                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 626                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 627                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 628                         reta_conf[reta_conf_idx].reta[reta_idx] =
 629                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int ena_rss_init_default(struct ena_adapter *adapter)
 636 {
 637         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 638         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 639         int rc, i;
 640         u32 val;
 641
 642         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 643         if (unlikely(rc)) {
 644                 PMD_DRV_LOG(ERR, "Cannot init indirect table\n");
 645                 goto err_rss_init;
 646         }
 647
 648         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 649                 val = i % nb_rx_queues;
 650                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 651                                                        ENA_IO_RXQ_IDX(val));
 652                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 653                         PMD_DRV_LOG(ERR, "Cannot fill indirect table\n");
 654                         goto err_fill_indir;
 655                 }
 656         }
 657
 658         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 659                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 660         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 661                 PMD_DRV_LOG(INFO, "Cannot fill hash function\n");
 662                 goto err_fill_indir;
 663         }
 664
 665         rc = ena_com_set_default_hash_ctrl(ena_dev);
 666         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 667                 PMD_DRV_LOG(INFO, "Cannot fill hash control\n");
 668                 goto err_fill_indir;
 669         }
 670
 671         rc = ena_com_indirect_table_set(ena_dev);
 672         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 673                 PMD_DRV_LOG(ERR, "Cannot flush the indirect table\n");
 674                 goto err_fill_indir;
 675         }
 676         PMD_DRV_LOG(DEBUG, "RSS configured for port %d\n",
 677                 adapter->rte_dev->data->port_id);
 678
 679         return 0;
 680
 681 err_fill_indir:
 682         ena_com_rss_destroy(ena_dev);
 683 err_rss_init:
 684
 685         return rc;
 686 }
 687
 688 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 689 {
 690         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 691         int nb_queues = dev->data->nb_rx_queues;
 692         int i;
 693
 694         for (i = 0; i < nb_queues; i++)
 695                 ena_rx_queue_release(queues[i]);
 696 }
 697
 698 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 699 {
 700         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 701         int nb_queues = dev->data->nb_tx_queues;
 702         int i;
 703
 704         for (i = 0; i < nb_queues; i++)
 705                 ena_tx_queue_release(queues[i]);
 706 }
 707
 708 static void ena_rx_queue_release(void *queue)
 709 {
 710         struct ena_ring *ring = (struct ena_ring *)queue;
 711
 712         /* Free ring resources */
 713         if (ring->rx_buffer_info)
 714                 rte_free(ring->rx_buffer_info);
 715         ring->rx_buffer_info = NULL;
 716
 717         if (ring->rx_refill_buffer)
 718                 rte_free(ring->rx_refill_buffer);
 719         ring->rx_refill_buffer = NULL;
 720
 721         if (ring->empty_rx_reqs)
 722                 rte_free(ring->empty_rx_reqs);
 723         ring->empty_rx_reqs = NULL;
 724
 725         ring->configured = 0;
 726
 727         PMD_DRV_LOG(NOTICE, "RX Queue %d:%d released\n",
 728                 ring->port_id, ring->id);
 729 }
 730
 731 static void ena_tx_queue_release(void *queue)
 732 {
 733         struct ena_ring *ring = (struct ena_ring *)queue;
 734
 735         /* Free ring resources */
 736         if (ring->push_buf_intermediate_buf)
 737                 rte_free(ring->push_buf_intermediate_buf);
 738
 739         if (ring->tx_buffer_info)
 740                 rte_free(ring->tx_buffer_info);
 741
 742         if (ring->empty_tx_reqs)
 743                 rte_free(ring->empty_tx_reqs);
 744
 745         ring->empty_tx_reqs = NULL;
 746         ring->tx_buffer_info = NULL;
 747         ring->push_buf_intermediate_buf = NULL;
 748
 749         ring->configured = 0;
 750
 751         PMD_DRV_LOG(NOTICE, "TX Queue %d:%d released\n",
 752                 ring->port_id, ring->id);
 753 }
 754
 755 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 756 {
 757         unsigned int i;
 758
 759         for (i = 0; i < ring->ring_size; ++i) {
 760                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 761                 if (rx_info->mbuf) {
 762                         rte_mbuf_raw_free(rx_info->mbuf);
 763                         rx_info->mbuf = NULL;
 764                 }
 765         }
 766 }
 767
 768 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 769 {
 770         unsigned int i;
 771
 772         for (i = 0; i < ring->ring_size; ++i) {
 773                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 774
 775                 if (tx_buf->mbuf)
 776                         rte_pktmbuf_free(tx_buf->mbuf);
 777         }
 778 }
 779
 780 static int ena_link_update(struct rte_eth_dev *dev,
 781                            __rte_unused int wait_to_complete)
 782 {
 783         struct rte_eth_link *link = &dev->data->dev_link;
 784         struct ena_adapter *adapter = dev->data->dev_private;
 785
 786         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 787         link->link_speed = ETH_SPEED_NUM_NONE;
 788         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 789
 790         return 0;
 791 }
 792
 793 static int ena_queue_start_all(struct rte_eth_dev *dev,
 794                                enum ena_ring_type ring_type)
 795 {
 796         struct ena_adapter *adapter = dev->data->dev_private;
 797         struct ena_ring *queues = NULL;
 798         int nb_queues;
 799         int i = 0;
 800         int rc = 0;
 801
 802         if (ring_type == ENA_RING_TYPE_RX) {
 803                 queues = adapter->rx_ring;
 804                 nb_queues = dev->data->nb_rx_queues;
 805         } else {
 806                 queues = adapter->tx_ring;
 807                 nb_queues = dev->data->nb_tx_queues;
 808         }
 809         for (i = 0; i < nb_queues; i++) {
 810                 if (queues[i].configured) {
 811                         if (ring_type == ENA_RING_TYPE_RX) {
 812                                 ena_assert_msg(
 813                                         dev->data->rx_queues[i] == &queues[i],
 814                                         "Inconsistent state of rx queues\n");
 815                         } else {
 816                                 ena_assert_msg(
 817                                         dev->data->tx_queues[i] == &queues[i],
 818                                         "Inconsistent state of tx queues\n");
 819                         }
 820
 821                         rc = ena_queue_start(&queues[i]);
 822
 823                         if (rc) {
 824                                 PMD_INIT_LOG(ERR,
 825                                              "failed to start queue %d type(%d)",
 826                                              i, ring_type);
 827                                 goto err;
 828                         }
 829                 }
 830         }
 831
 832         return 0;
 833
 834 err:
 835         while (i--)
 836                 if (queues[i].configured)
 837                         ena_queue_stop(&queues[i]);
 838
 839         return rc;
 840 }
 841
 842 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 843 {
 844         uint32_t max_frame_len = adapter->max_mtu;
 845
 846         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 847             DEV_RX_OFFLOAD_JUMBO_FRAME)
 848                 max_frame_len =
 849                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 850
 851         return max_frame_len;
 852 }
 853
 854 static int ena_check_valid_conf(struct ena_adapter *adapter)
 855 {
 856         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 857
 858         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 859                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 860                                   "max mtu: %d, min mtu: %d",
 861                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 862                 return ENA_COM_UNSUPPORTED;
 863         }
 864
 865         return 0;
 866 }
 867
 868 static int
 869 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 870                        bool use_large_llq_hdr)
 871 {
 872         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 873         struct ena_com_dev *ena_dev = ctx->ena_dev;
 874         uint32_t max_tx_queue_size;
 875         uint32_t max_rx_queue_size;
 876
 877         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 878                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 879                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 880                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 881                         max_queue_ext->max_rx_sq_depth);
 882                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 883
 884                 if (ena_dev->tx_mem_queue_type ==
 885                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 886                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 887                                 llq->max_llq_depth);
 888                 } else {
 889                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 890                                 max_queue_ext->max_tx_sq_depth);
 891                 }
 892
 893                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 894                         max_queue_ext->max_per_packet_rx_descs);
 895                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 896                         max_queue_ext->max_per_packet_tx_descs);
 897         } else {
 898                 struct ena_admin_queue_feature_desc *max_queues =
 899                         &ctx->get_feat_ctx->max_queues;
 900                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 901                         max_queues->max_sq_depth);
 902                 max_tx_queue_size = max_queues->max_cq_depth;
 903
 904                 if (ena_dev->tx_mem_queue_type ==
 905                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 906                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 907                                 llq->max_llq_depth);
 908                 } else {
 909                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 910                                 max_queues->max_sq_depth);
 911                 }
 912
 913                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 914                         max_queues->max_packet_rx_descs);
 915                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 916                         max_queues->max_packet_tx_descs);
 917         }
 918
 919         /* Round down to the nearest power of 2 */
 920         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 921         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 922
 923         if (use_large_llq_hdr) {
 924                 if ((llq->entry_size_ctrl_supported &
 925                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 926                     (ena_dev->tx_mem_queue_type ==
 927                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 928                         max_tx_queue_size /= 2;
 929                         PMD_INIT_LOG(INFO,
 930                                 "Forcing large headers and decreasing maximum TX queue size to %d\n",
 931                                 max_tx_queue_size);
 932                 } else {
 933                         PMD_INIT_LOG(ERR,
 934                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 935                 }
 936         }
 937
 938         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 939                 PMD_INIT_LOG(ERR, "Invalid queue size");
 940                 return -EFAULT;
 941         }
 942
 943         ctx->max_tx_queue_size = max_tx_queue_size;
 944         ctx->max_rx_queue_size = max_rx_queue_size;
 945
 946         return 0;
 947 }
 948
 949 static void ena_stats_restart(struct rte_eth_dev *dev)
 950 {
 951         struct ena_adapter *adapter = dev->data->dev_private;
 952
 953         rte_atomic64_init(&adapter->drv_stats->ierrors);
 954         rte_atomic64_init(&adapter->drv_stats->oerrors);
 955         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 956         adapter->drv_stats->rx_drops = 0;
 957 }
 958
 959 static int ena_stats_get(struct rte_eth_dev *dev,
 960                           struct rte_eth_stats *stats)
 961 {
 962         struct ena_admin_basic_stats ena_stats;
 963         struct ena_adapter *adapter = dev->data->dev_private;
 964         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 965         int rc;
 966         int i;
 967         int max_rings_stats;
 968
 969         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 970                 return -ENOTSUP;
 971
 972         memset(&ena_stats, 0, sizeof(ena_stats));
 973         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 974         if (unlikely(rc)) {
 975                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 976                 return rc;
 977         }
 978
 979         /* Set of basic statistics from ENA */
 980         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 981                                           ena_stats.rx_pkts_low);
 982         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 983                                           ena_stats.tx_pkts_low);
 984         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 985                                         ena_stats.rx_bytes_low);
 986         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 987                                         ena_stats.tx_bytes_low);
 988
 989         /* Driver related stats */
 990         stats->imissed = adapter->drv_stats->rx_drops;
 991         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 992         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 993         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 994
 995         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 996                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 997         for (i = 0; i < max_rings_stats; ++i) {
 998                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 999
1000                 stats->q_ibytes[i] = rx_stats->bytes;
1001                 stats->q_ipackets[i] = rx_stats->cnt;
1002                 stats->q_errors[i] = rx_stats->bad_desc_num +
1003                         rx_stats->bad_req_id;
1004         }
1005
1006         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1007                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1008         for (i = 0; i < max_rings_stats; ++i) {
1009                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1010
1011                 stats->q_obytes[i] = tx_stats->bytes;
1012                 stats->q_opackets[i] = tx_stats->cnt;
1013         }
1014
1015         return 0;
1016 }
1017
1018 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1019 {
1020         struct ena_adapter *adapter;
1021         struct ena_com_dev *ena_dev;
1022         int rc = 0;
1023
1024         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1025         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1026         adapter = dev->data->dev_private;
1027
1028         ena_dev = &adapter->ena_dev;
1029         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1030
1031         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1032                 PMD_DRV_LOG(ERR,
1033                         "Invalid MTU setting. new_mtu: %d "
1034                         "max mtu: %d min mtu: %d\n",
1035                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1036                 return -EINVAL;
1037         }
1038
1039         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1040         if (rc)
1041                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
1042         else
1043                 PMD_DRV_LOG(NOTICE, "Set MTU: %d\n", mtu);
1044
1045         return rc;
1046 }
1047
1048 static int ena_start(struct rte_eth_dev *dev)
1049 {
1050         struct ena_adapter *adapter = dev->data->dev_private;
1051         uint64_t ticks;
1052         int rc = 0;
1053
1054         rc = ena_check_valid_conf(adapter);
1055         if (rc)
1056                 return rc;
1057
1058         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1059         if (rc)
1060                 return rc;
1061
1062         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1063         if (rc)
1064                 goto err_start_tx;
1065
1066         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1067             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1068                 rc = ena_rss_init_default(adapter);
1069                 if (rc)
1070                         goto err_rss_init;
1071         }
1072
1073         ena_stats_restart(dev);
1074
1075         adapter->timestamp_wd = rte_get_timer_cycles();
1076         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1077
1078         ticks = rte_get_timer_hz();
1079         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1080                         ena_timer_wd_callback, adapter);
1081
1082         ++adapter->dev_stats.dev_start;
1083         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1084
1085         return 0;
1086
1087 err_rss_init:
1088         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1089 err_start_tx:
1090         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1091         return rc;
1092 }
1093
1094 static void ena_stop(struct rte_eth_dev *dev)
1095 {
1096         struct ena_adapter *adapter = dev->data->dev_private;
1097         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1098         int rc;
1099
1100         rte_timer_stop_sync(&adapter->timer_wd);
1101         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1102         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1103
1104         if (adapter->trigger_reset) {
1105                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1106                 if (rc)
1107                         PMD_DRV_LOG(ERR, "Device reset failed rc=%d\n", rc);
1108         }
1109
1110         ++adapter->dev_stats.dev_stop;
1111         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1112 }
1113
1114 static int ena_create_io_queue(struct ena_ring *ring)
1115 {
1116         struct ena_adapter *adapter;
1117         struct ena_com_dev *ena_dev;
1118         struct ena_com_create_io_ctx ctx =
1119                 /* policy set to _HOST just to satisfy icc compiler */
1120                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1121                   0, 0, 0, 0, 0 };
1122         uint16_t ena_qid;
1123         unsigned int i;
1124         int rc;
1125
1126         adapter = ring->adapter;
1127         ena_dev = &adapter->ena_dev;
1128
1129         if (ring->type == ENA_RING_TYPE_TX) {
1130                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1131                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1132                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1133                 for (i = 0; i < ring->ring_size; i++)
1134                         ring->empty_tx_reqs[i] = i;
1135         } else {
1136                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1137                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1138                 for (i = 0; i < ring->ring_size; i++)
1139                         ring->empty_rx_reqs[i] = i;
1140         }
1141         ctx.queue_size = ring->ring_size;
1142         ctx.qid = ena_qid;
1143         ctx.msix_vector = -1; /* interrupts not used */
1144         ctx.numa_node = ring->numa_socket_id;
1145
1146         rc = ena_com_create_io_queue(ena_dev, &ctx);
1147         if (rc) {
1148                 PMD_DRV_LOG(ERR,
1149                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1150                         ring->id, ena_qid, rc);
1151                 return rc;
1152         }
1153
1154         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1155                                      &ring->ena_com_io_sq,
1156                                      &ring->ena_com_io_cq);
1157         if (rc) {
1158                 PMD_DRV_LOG(ERR,
1159                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1160                         ring->id, rc);
1161                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1162                 return rc;
1163         }
1164
1165         if (ring->type == ENA_RING_TYPE_TX)
1166                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1167
1168         return 0;
1169 }
1170
1171 static void ena_queue_stop(struct ena_ring *ring)
1172 {
1173         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1174
1175         if (ring->type == ENA_RING_TYPE_RX) {
1176                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1177                 ena_rx_queue_release_bufs(ring);
1178         } else {
1179                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1180                 ena_tx_queue_release_bufs(ring);
1181         }
1182 }
1183
1184 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1185                               enum ena_ring_type ring_type)
1186 {
1187         struct ena_adapter *adapter = dev->data->dev_private;
1188         struct ena_ring *queues = NULL;
1189         uint16_t nb_queues, i;
1190
1191         if (ring_type == ENA_RING_TYPE_RX) {
1192                 queues = adapter->rx_ring;
1193                 nb_queues = dev->data->nb_rx_queues;
1194         } else {
1195                 queues = adapter->tx_ring;
1196                 nb_queues = dev->data->nb_tx_queues;
1197         }
1198
1199         for (i = 0; i < nb_queues; ++i)
1200                 if (queues[i].configured)
1201                         ena_queue_stop(&queues[i]);
1202 }
1203
1204 static int ena_queue_start(struct ena_ring *ring)
1205 {
1206         int rc, bufs_num;
1207
1208         ena_assert_msg(ring->configured == 1,
1209                        "Trying to start unconfigured queue\n");
1210
1211         rc = ena_create_io_queue(ring);
1212         if (rc) {
1213                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1214                 return rc;
1215         }
1216
1217         ring->next_to_clean = 0;
1218         ring->next_to_use = 0;
1219
1220         if (ring->type == ENA_RING_TYPE_TX) {
1221                 ring->tx_stats.available_desc =
1222                         ena_com_free_q_entries(ring->ena_com_io_sq);
1223                 return 0;
1224         }
1225
1226         bufs_num = ring->ring_size - 1;
1227         rc = ena_populate_rx_queue(ring, bufs_num);
1228         if (rc != bufs_num) {
1229                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1230                                          ENA_IO_RXQ_IDX(ring->id));
1231                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1232                 return ENA_COM_FAULT;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1239                               uint16_t queue_idx,
1240                               uint16_t nb_desc,
1241                               unsigned int socket_id,
1242                               const struct rte_eth_txconf *tx_conf)
1243 {
1244         struct ena_ring *txq = NULL;
1245         struct ena_adapter *adapter = dev->data->dev_private;
1246         unsigned int i;
1247
1248         txq = &adapter->tx_ring[queue_idx];
1249
1250         if (txq->configured) {
1251                 PMD_DRV_LOG(CRIT,
1252                         "API violation. Queue %d is already configured\n",
1253                         queue_idx);
1254                 return ENA_COM_FAULT;
1255         }
1256
1257         if (!rte_is_power_of_2(nb_desc)) {
1258                 PMD_DRV_LOG(ERR,
1259                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1260                         nb_desc);
1261                 return -EINVAL;
1262         }
1263
1264         if (nb_desc > adapter->max_tx_ring_size) {
1265                 PMD_DRV_LOG(ERR,
1266                         "Unsupported size of TX queue (max size: %d)\n",
1267                         adapter->max_tx_ring_size);
1268                 return -EINVAL;
1269         }
1270
1271         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1272                 nb_desc = adapter->max_tx_ring_size;
1273
1274         txq->port_id = dev->data->port_id;
1275         txq->next_to_clean = 0;
1276         txq->next_to_use = 0;
1277         txq->ring_size = nb_desc;
1278         txq->size_mask = nb_desc - 1;
1279         txq->numa_socket_id = socket_id;
1280
1281         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1282                                           sizeof(struct ena_tx_buffer) *
1283                                           txq->ring_size,
1284                                           RTE_CACHE_LINE_SIZE);
1285         if (!txq->tx_buffer_info) {
1286                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx buffer info\n");
1287                 return -ENOMEM;
1288         }
1289
1290         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1291                                          sizeof(u16) * txq->ring_size,
1292                                          RTE_CACHE_LINE_SIZE);
1293         if (!txq->empty_tx_reqs) {
1294                 PMD_DRV_LOG(ERR, "failed to alloc mem for tx reqs\n");
1295                 rte_free(txq->tx_buffer_info);
1296                 return -ENOMEM;
1297         }
1298
1299         txq->push_buf_intermediate_buf =
1300                 rte_zmalloc("txq->push_buf_intermediate_buf",
1301                             txq->tx_max_header_size,
1302                             RTE_CACHE_LINE_SIZE);
1303         if (!txq->push_buf_intermediate_buf) {
1304                 PMD_DRV_LOG(ERR, "failed to alloc push buff for LLQ\n");
1305                 rte_free(txq->tx_buffer_info);
1306                 rte_free(txq->empty_tx_reqs);
1307                 return -ENOMEM;
1308         }
1309
1310         for (i = 0; i < txq->ring_size; i++)
1311                 txq->empty_tx_reqs[i] = i;
1312
1313         if (tx_conf != NULL) {
1314                 txq->offloads =
1315                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1316         }
1317         /* Store pointer to this queue in upper layer */
1318         txq->configured = 1;
1319         dev->data->tx_queues[queue_idx] = txq;
1320
1321         return 0;
1322 }
1323
1324 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1325                               uint16_t queue_idx,
1326                               uint16_t nb_desc,
1327                               unsigned int socket_id,
1328                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1329                               struct rte_mempool *mp)
1330 {
1331         struct ena_adapter *adapter = dev->data->dev_private;
1332         struct ena_ring *rxq = NULL;
1333         size_t buffer_size;
1334         int i;
1335
1336         rxq = &adapter->rx_ring[queue_idx];
1337         if (rxq->configured) {
1338                 PMD_DRV_LOG(CRIT,
1339                         "API violation. Queue %d is already configured\n",
1340                         queue_idx);
1341                 return ENA_COM_FAULT;
1342         }
1343
1344         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1345                 nb_desc = adapter->max_rx_ring_size;
1346
1347         if (!rte_is_power_of_2(nb_desc)) {
1348                 PMD_DRV_LOG(ERR,
1349                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1350                         nb_desc);
1351                 return -EINVAL;
1352         }
1353
1354         if (nb_desc > adapter->max_rx_ring_size) {
1355                 PMD_DRV_LOG(ERR,
1356                         "Unsupported size of RX queue (max size: %d)\n",
1357                         adapter->max_rx_ring_size);
1358                 return -EINVAL;
1359         }
1360
1361         /* ENA isn't supporting buffers smaller than 1400 bytes */
1362         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1363         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1364                 PMD_DRV_LOG(ERR,
1365                         "Unsupported size of RX buffer: %zu (min size: %d)\n",
1366                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1367                 return -EINVAL;
1368         }
1369
1370         rxq->port_id = dev->data->port_id;
1371         rxq->next_to_clean = 0;
1372         rxq->next_to_use = 0;
1373         rxq->ring_size = nb_desc;
1374         rxq->size_mask = nb_desc - 1;
1375         rxq->numa_socket_id = socket_id;
1376         rxq->mb_pool = mp;
1377
1378         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1379                 sizeof(struct ena_rx_buffer) * nb_desc,
1380                 RTE_CACHE_LINE_SIZE);
1381         if (!rxq->rx_buffer_info) {
1382                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx buffer info\n");
1383                 return -ENOMEM;
1384         }
1385
1386         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1387                                             sizeof(struct rte_mbuf *) * nb_desc,
1388                                             RTE_CACHE_LINE_SIZE);
1389
1390         if (!rxq->rx_refill_buffer) {
1391                 PMD_DRV_LOG(ERR, "failed to alloc mem for rx refill buffer\n");
1392                 rte_free(rxq->rx_buffer_info);
1393                 rxq->rx_buffer_info = NULL;
1394                 return -ENOMEM;
1395         }
1396
1397         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1398                                          sizeof(uint16_t) * nb_desc,
1399                                          RTE_CACHE_LINE_SIZE);
1400         if (!rxq->empty_rx_reqs) {
1401                 PMD_DRV_LOG(ERR, "failed to alloc mem for empty rx reqs\n");
1402                 rte_free(rxq->rx_buffer_info);
1403                 rxq->rx_buffer_info = NULL;
1404                 rte_free(rxq->rx_refill_buffer);
1405                 rxq->rx_refill_buffer = NULL;
1406                 return -ENOMEM;
1407         }
1408
1409         for (i = 0; i < nb_desc; i++)
1410                 rxq->empty_rx_reqs[i] = i;
1411
1412         /* Store pointer to this queue in upper layer */
1413         rxq->configured = 1;
1414         dev->data->rx_queues[queue_idx] = rxq;
1415
1416         return 0;
1417 }
1418
1419 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1420                                   struct rte_mbuf *mbuf, uint16_t id)
1421 {
1422         struct ena_com_buf ebuf;
1423         int rc;
1424
1425         /* prepare physical address for DMA transaction */
1426         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1427         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1428
1429         /* pass resource to device */
1430         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1431         if (unlikely(rc != 0))
1432                 PMD_DRV_LOG(WARNING, "failed adding rx desc\n");
1433
1434         return rc;
1435 }
1436
1437 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1438 {
1439         unsigned int i;
1440         int rc;
1441         uint16_t next_to_use = rxq->next_to_use;
1442         uint16_t in_use, req_id;
1443         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1444
1445         if (unlikely(!count))
1446                 return 0;
1447
1448         in_use = rxq->ring_size - 1 -
1449                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1450         ena_assert_msg(((in_use + count) < rxq->ring_size),
1451                 "bad ring state\n");
1452
1453         /* get resources for incoming packets */
1454         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1455         if (unlikely(rc < 0)) {
1456                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1457                 ++rxq->rx_stats.mbuf_alloc_fail;
1458                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1459                 return 0;
1460         }
1461
1462         for (i = 0; i < count; i++) {
1463                 struct rte_mbuf *mbuf = mbufs[i];
1464                 struct ena_rx_buffer *rx_info;
1465
1466                 if (likely((i + 4) < count))
1467                         rte_prefetch0(mbufs[i + 4]);
1468
1469                 req_id = rxq->empty_rx_reqs[next_to_use];
1470                 rc = validate_rx_req_id(rxq, req_id);
1471                 if (unlikely(rc))
1472                         break;
1473
1474                 rx_info = &rxq->rx_buffer_info[req_id];
1475
1476                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1477                 if (unlikely(rc != 0))
1478                         break;
1479
1480                 rx_info->mbuf = mbuf;
1481                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1482         }
1483
1484         if (unlikely(i < count)) {
1485                 PMD_DRV_LOG(WARNING, "refilled rx qid %d with only %d "
1486                         "buffers (from %d)\n", rxq->id, i, count);
1487                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1488                                      count - i);
1489                 ++rxq->rx_stats.refill_partial;
1490         }
1491
1492         /* When we submitted free recources to device... */
1493         if (likely(i > 0)) {
1494                 /* ...let HW know that it can fill buffers with data. */
1495                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1496
1497                 rxq->next_to_use = next_to_use;
1498         }
1499
1500         return i;
1501 }
1502
1503 static int ena_device_init(struct ena_com_dev *ena_dev,
1504                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1505                            bool *wd_state)
1506 {
1507         uint32_t aenq_groups;
1508         int rc;
1509         bool readless_supported;
1510
1511         /* Initialize mmio registers */
1512         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1513         if (rc) {
1514                 PMD_DRV_LOG(ERR, "failed to init mmio read less\n");
1515                 return rc;
1516         }
1517
1518         /* The PCIe configuration space revision id indicate if mmio reg
1519          * read is disabled.
1520          */
1521         readless_supported =
1522                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1523                                & ENA_MMIO_DISABLE_REG_READ);
1524         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1525
1526         /* reset device */
1527         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1528         if (rc) {
1529                 PMD_DRV_LOG(ERR, "cannot reset device\n");
1530                 goto err_mmio_read_less;
1531         }
1532
1533         /* check FW version */
1534         rc = ena_com_validate_version(ena_dev);
1535         if (rc) {
1536                 PMD_DRV_LOG(ERR, "device version is too low\n");
1537                 goto err_mmio_read_less;
1538         }
1539
1540         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1541
1542         /* ENA device administration layer init */
1543         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1544         if (rc) {
1545                 PMD_DRV_LOG(ERR,
1546                         "cannot initialize ena admin queue with device\n");
1547                 goto err_mmio_read_less;
1548         }
1549
1550         /* To enable the msix interrupts the driver needs to know the number
1551          * of queues. So the driver uses polling mode to retrieve this
1552          * information.
1553          */
1554         ena_com_set_admin_polling_mode(ena_dev, true);
1555
1556         ena_config_host_info(ena_dev);
1557
1558         /* Get Device Attributes and features */
1559         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1560         if (rc) {
1561                 PMD_DRV_LOG(ERR,
1562                         "cannot get attribute for ena device rc= %d\n", rc);
1563                 goto err_admin_init;
1564         }
1565
1566         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1567                       BIT(ENA_ADMIN_NOTIFICATION) |
1568                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1569                       BIT(ENA_ADMIN_FATAL_ERROR) |
1570                       BIT(ENA_ADMIN_WARNING);
1571
1572         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1573         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1574         if (rc) {
1575                 PMD_DRV_LOG(ERR, "Cannot configure aenq groups rc: %d\n", rc);
1576                 goto err_admin_init;
1577         }
1578
1579         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1580
1581         return 0;
1582
1583 err_admin_init:
1584         ena_com_admin_destroy(ena_dev);
1585
1586 err_mmio_read_less:
1587         ena_com_mmio_reg_read_request_destroy(ena_dev);
1588
1589         return rc;
1590 }
1591
1592 static void ena_interrupt_handler_rte(void *cb_arg)
1593 {
1594         struct ena_adapter *adapter = cb_arg;
1595         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1596
1597         ena_com_admin_q_comp_intr_handler(ena_dev);
1598         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1599                 ena_com_aenq_intr_handler(ena_dev, adapter);
1600 }
1601
1602 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1603 {
1604         if (!adapter->wd_state)
1605                 return;
1606
1607         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1608                 return;
1609
1610         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1611             adapter->keep_alive_timeout)) {
1612                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1613                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1614                 adapter->trigger_reset = true;
1615                 ++adapter->dev_stats.wd_expired;
1616         }
1617 }
1618
1619 /* Check if admin queue is enabled */
1620 static void check_for_admin_com_state(struct ena_adapter *adapter)
1621 {
1622         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1623                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state!\n");
1624                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1625                 adapter->trigger_reset = true;
1626         }
1627 }
1628
1629 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1630                                   void *arg)
1631 {
1632         struct ena_adapter *adapter = arg;
1633         struct rte_eth_dev *dev = adapter->rte_dev;
1634
1635         check_for_missing_keep_alive(adapter);
1636         check_for_admin_com_state(adapter);
1637
1638         if (unlikely(adapter->trigger_reset)) {
1639                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1640                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1641                         NULL);
1642         }
1643 }
1644
1645 static inline void
1646 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1647                                struct ena_admin_feature_llq_desc *llq,
1648                                bool use_large_llq_hdr)
1649 {
1650         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1651         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1652         llq_config->llq_num_decs_before_header =
1653                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1654
1655         if (use_large_llq_hdr &&
1656             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1657                 llq_config->llq_ring_entry_size =
1658                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1659                 llq_config->llq_ring_entry_size_value = 256;
1660         } else {
1661                 llq_config->llq_ring_entry_size =
1662                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1663                 llq_config->llq_ring_entry_size_value = 128;
1664         }
1665 }
1666
1667 static int
1668 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1669                                 struct ena_com_dev *ena_dev,
1670                                 struct ena_admin_feature_llq_desc *llq,
1671                                 struct ena_llq_configurations *llq_default_configurations)
1672 {
1673         int rc;
1674         u32 llq_feature_mask;
1675
1676         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1677         if (!(ena_dev->supported_features & llq_feature_mask)) {
1678                 PMD_DRV_LOG(INFO,
1679                         "LLQ is not supported. Fallback to host mode policy.\n");
1680                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1681                 return 0;
1682         }
1683
1684         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1685         if (unlikely(rc)) {
1686                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1687                         "Fallback to host mode policy.");
1688                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1689                 return 0;
1690         }
1691
1692         /* Nothing to config, exit */
1693         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1694                 return 0;
1695
1696         if (!adapter->dev_mem_base) {
1697                 PMD_DRV_LOG(ERR, "Unable to access LLQ bar resource. "
1698                         "Fallback to host mode policy.\n.");
1699                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1700                 return 0;
1701         }
1702
1703         ena_dev->mem_bar = adapter->dev_mem_base;
1704
1705         return 0;
1706 }
1707
1708 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1709         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1710 {
1711         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1712
1713         /* Regular queues capabilities */
1714         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1715                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1716                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1717                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1718                                     max_queue_ext->max_rx_cq_num);
1719                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1720                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1721         } else {
1722                 struct ena_admin_queue_feature_desc *max_queues =
1723                         &get_feat_ctx->max_queues;
1724                 io_tx_sq_num = max_queues->max_sq_num;
1725                 io_tx_cq_num = max_queues->max_cq_num;
1726                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1727         }
1728
1729         /* In case of LLQ use the llq number in the get feature cmd */
1730         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1731                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1732
1733         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1734         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1735         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1736
1737         if (unlikely(max_num_io_queues == 0)) {
1738                 PMD_DRV_LOG(ERR, "Number of IO queues should not be 0\n");
1739                 return -EFAULT;
1740         }
1741
1742         return max_num_io_queues;
1743 }
1744
1745 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1746 {
1747         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1748         struct rte_pci_device *pci_dev;
1749         struct rte_intr_handle *intr_handle;
1750         struct ena_adapter *adapter = eth_dev->data->dev_private;
1751         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1752         struct ena_com_dev_get_features_ctx get_feat_ctx;
1753         struct ena_llq_configurations llq_config;
1754         const char *queue_type_str;
1755         uint32_t max_num_io_queues;
1756         int rc;
1757         static int adapters_found;
1758         bool disable_meta_caching;
1759         bool wd_state;
1760
1761         eth_dev->dev_ops = &ena_dev_ops;
1762         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1763         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1764         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1765
1766         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1767                 return 0;
1768
1769         memset(adapter, 0, sizeof(struct ena_adapter));
1770         ena_dev = &adapter->ena_dev;
1771
1772         adapter->rte_eth_dev_data = eth_dev->data;
1773         adapter->rte_dev = eth_dev;
1774
1775         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1776         adapter->pdev = pci_dev;
1777
1778         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1779                      pci_dev->addr.domain,
1780                      pci_dev->addr.bus,
1781                      pci_dev->addr.devid,
1782                      pci_dev->addr.function);
1783
1784         intr_handle = &pci_dev->intr_handle;
1785
1786         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1787         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1788
1789         if (!adapter->regs) {
1790                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1791                              ENA_REGS_BAR);
1792                 return -ENXIO;
1793         }
1794
1795         ena_dev->reg_bar = adapter->regs;
1796         ena_dev->dmadev = adapter->pdev;
1797
1798         adapter->id_number = adapters_found;
1799
1800         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1801                  adapter->id_number);
1802
1803         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1804         if (rc != 0) {
1805                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1806                 goto err;
1807         }
1808
1809         /* device specific initialization routine */
1810         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1811         if (rc) {
1812                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1813                 goto err;
1814         }
1815         adapter->wd_state = wd_state;
1816
1817         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1818                 adapter->use_large_llq_hdr);
1819         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1820                                              &get_feat_ctx.llq, &llq_config);
1821         if (unlikely(rc)) {
1822                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1823                 return rc;
1824         }
1825
1826         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1827                 queue_type_str = "Regular";
1828         else
1829                 queue_type_str = "Low latency";
1830         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1831
1832         calc_queue_ctx.ena_dev = ena_dev;
1833         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1834
1835         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1836         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1837                 adapter->use_large_llq_hdr);
1838         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1839                 rc = -EFAULT;
1840                 goto err_device_destroy;
1841         }
1842
1843         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1844         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1845         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1846         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1847         adapter->max_num_io_queues = max_num_io_queues;
1848
1849         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1850                 disable_meta_caching =
1851                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1852                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1853         } else {
1854                 disable_meta_caching = false;
1855         }
1856
1857         /* prepare ring structures */
1858         ena_init_rings(adapter, disable_meta_caching);
1859
1860         ena_config_debug_area(adapter);
1861
1862         /* Set max MTU for this device */
1863         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1864
1865         /* set device support for offloads */
1866         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1867                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1868         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1869                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1870         adapter->offloads.rx_csum_supported =
1871                 (get_feat_ctx.offload.rx_supported &
1872                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1873
1874         /* Copy MAC address and point DPDK to it */
1875         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1876         rte_ether_addr_copy((struct rte_ether_addr *)
1877                         get_feat_ctx.dev_attr.mac_addr,
1878                         (struct rte_ether_addr *)adapter->mac_addr);
1879
1880         /*
1881          * Pass the information to the rte_eth_dev_close() that it should also
1882          * release the private port resources.
1883          */
1884         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1885
1886         adapter->drv_stats = rte_zmalloc("adapter stats",
1887                                          sizeof(*adapter->drv_stats),
1888                                          RTE_CACHE_LINE_SIZE);
1889         if (!adapter->drv_stats) {
1890                 PMD_DRV_LOG(ERR, "failed to alloc mem for adapter stats\n");
1891                 rc = -ENOMEM;
1892                 goto err_delete_debug_area;
1893         }
1894
1895         rte_intr_callback_register(intr_handle,
1896                                    ena_interrupt_handler_rte,
1897                                    adapter);
1898         rte_intr_enable(intr_handle);
1899         ena_com_set_admin_polling_mode(ena_dev, false);
1900         ena_com_admin_aenq_enable(ena_dev);
1901
1902         if (adapters_found == 0)
1903                 rte_timer_subsystem_init();
1904         rte_timer_init(&adapter->timer_wd);
1905
1906         adapters_found++;
1907         adapter->state = ENA_ADAPTER_STATE_INIT;
1908
1909         return 0;
1910
1911 err_delete_debug_area:
1912         ena_com_delete_debug_area(ena_dev);
1913
1914 err_device_destroy:
1915         ena_com_delete_host_info(ena_dev);
1916         ena_com_admin_destroy(ena_dev);
1917
1918 err:
1919         return rc;
1920 }
1921
1922 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1923 {
1924         struct ena_adapter *adapter = eth_dev->data->dev_private;
1925         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1926
1927         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1928                 return;
1929
1930         ena_com_set_admin_running_state(ena_dev, false);
1931
1932         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1933                 ena_close(eth_dev);
1934
1935         ena_com_delete_debug_area(ena_dev);
1936         ena_com_delete_host_info(ena_dev);
1937
1938         ena_com_abort_admin_commands(ena_dev);
1939         ena_com_wait_for_abort_completion(ena_dev);
1940         ena_com_admin_destroy(ena_dev);
1941         ena_com_mmio_reg_read_request_destroy(ena_dev);
1942
1943         adapter->state = ENA_ADAPTER_STATE_FREE;
1944 }
1945
1946 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1947 {
1948         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1949                 return 0;
1950
1951         ena_destroy_device(eth_dev);
1952
1953         eth_dev->dev_ops = NULL;
1954         eth_dev->rx_pkt_burst = NULL;
1955         eth_dev->tx_pkt_burst = NULL;
1956         eth_dev->tx_pkt_prepare = NULL;
1957
1958         return 0;
1959 }
1960
1961 static int ena_dev_configure(struct rte_eth_dev *dev)
1962 {
1963         struct ena_adapter *adapter = dev->data->dev_private;
1964
1965         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1966
1967         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1968         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1969         return 0;
1970 }
1971
1972 static void ena_init_rings(struct ena_adapter *adapter,
1973                            bool disable_meta_caching)
1974 {
1975         size_t i;
1976
1977         for (i = 0; i < adapter->max_num_io_queues; i++) {
1978                 struct ena_ring *ring = &adapter->tx_ring[i];
1979
1980                 ring->configured = 0;
1981                 ring->type = ENA_RING_TYPE_TX;
1982                 ring->adapter = adapter;
1983                 ring->id = i;
1984                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1985                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1986                 ring->sgl_size = adapter->max_tx_sgl_size;
1987                 ring->disable_meta_caching = disable_meta_caching;
1988         }
1989
1990         for (i = 0; i < adapter->max_num_io_queues; i++) {
1991                 struct ena_ring *ring = &adapter->rx_ring[i];
1992
1993                 ring->configured = 0;
1994                 ring->type = ENA_RING_TYPE_RX;
1995                 ring->adapter = adapter;
1996                 ring->id = i;
1997                 ring->sgl_size = adapter->max_rx_sgl_size;
1998         }
1999 }
2000
2001 static int ena_infos_get(struct rte_eth_dev *dev,
2002                           struct rte_eth_dev_info *dev_info)
2003 {
2004         struct ena_adapter *adapter;
2005         struct ena_com_dev *ena_dev;
2006         uint64_t rx_feat = 0, tx_feat = 0;
2007
2008         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
2009         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
2010         adapter = dev->data->dev_private;
2011
2012         ena_dev = &adapter->ena_dev;
2013         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
2014
2015         dev_info->speed_capa =
2016                         ETH_LINK_SPEED_1G   |
2017                         ETH_LINK_SPEED_2_5G |
2018                         ETH_LINK_SPEED_5G   |
2019                         ETH_LINK_SPEED_10G  |
2020                         ETH_LINK_SPEED_25G  |
2021                         ETH_LINK_SPEED_40G  |
2022                         ETH_LINK_SPEED_50G  |
2023                         ETH_LINK_SPEED_100G;
2024
2025         /* Set Tx & Rx features available for device */
2026         if (adapter->offloads.tso4_supported)
2027                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
2028
2029         if (adapter->offloads.tx_csum_supported)
2030                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2031                         DEV_TX_OFFLOAD_UDP_CKSUM |
2032                         DEV_TX_OFFLOAD_TCP_CKSUM;
2033
2034         if (adapter->offloads.rx_csum_supported)
2035                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2036                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2037                         DEV_RX_OFFLOAD_TCP_CKSUM;
2038
2039         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2040
2041         /* Inform framework about available features */
2042         dev_info->rx_offload_capa = rx_feat;
2043         dev_info->rx_queue_offload_capa = rx_feat;
2044         dev_info->tx_offload_capa = tx_feat;
2045         dev_info->tx_queue_offload_capa = tx_feat;
2046
2047         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2048                                            ETH_RSS_UDP;
2049
2050         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2051         dev_info->max_rx_pktlen  = adapter->max_mtu;
2052         dev_info->max_mac_addrs = 1;
2053
2054         dev_info->max_rx_queues = adapter->max_num_io_queues;
2055         dev_info->max_tx_queues = adapter->max_num_io_queues;
2056         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2057
2058         adapter->tx_supported_offloads = tx_feat;
2059         adapter->rx_supported_offloads = rx_feat;
2060
2061         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
2062         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2063         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2064                                         adapter->max_rx_sgl_size);
2065         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2066                                         adapter->max_rx_sgl_size);
2067
2068         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
2069         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2070         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2071                                         adapter->max_tx_sgl_size);
2072         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2073                                         adapter->max_tx_sgl_size);
2074
2075         return 0;
2076 }
2077
2078 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
2079 {
2080         mbuf->data_len = len;
2081         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2082         mbuf->refcnt = 1;
2083         mbuf->next = NULL;
2084 }
2085
2086 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
2087                                     struct ena_com_rx_buf_info *ena_bufs,
2088                                     uint32_t descs,
2089                                     uint16_t *next_to_clean,
2090                                     uint8_t offset)
2091 {
2092         struct rte_mbuf *mbuf;
2093         struct rte_mbuf *mbuf_head;
2094         struct ena_rx_buffer *rx_info;
2095         int rc;
2096         uint16_t ntc, len, req_id, buf = 0;
2097
2098         if (unlikely(descs == 0))
2099                 return NULL;
2100
2101         ntc = *next_to_clean;
2102
2103         len = ena_bufs[buf].len;
2104         req_id = ena_bufs[buf].req_id;
2105         if (unlikely(validate_rx_req_id(rx_ring, req_id)))
2106                 return NULL;
2107
2108         rx_info = &rx_ring->rx_buffer_info[req_id];
2109
2110         mbuf = rx_info->mbuf;
2111         RTE_ASSERT(mbuf != NULL);
2112
2113         ena_init_rx_mbuf(mbuf, len);
2114
2115         /* Fill the mbuf head with the data specific for 1st segment. */
2116         mbuf_head = mbuf;
2117         mbuf_head->nb_segs = descs;
2118         mbuf_head->port = rx_ring->port_id;
2119         mbuf_head->pkt_len = len;
2120         mbuf_head->data_off += offset;
2121
2122         rx_info->mbuf = NULL;
2123         rx_ring->empty_rx_reqs[ntc] = req_id;
2124         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2125
2126         while (--descs) {
2127                 ++buf;
2128                 len = ena_bufs[buf].len;
2129                 req_id = ena_bufs[buf].req_id;
2130                 if (unlikely(validate_rx_req_id(rx_ring, req_id))) {
2131                         rte_mbuf_raw_free(mbuf_head);
2132                         return NULL;
2133                 }
2134
2135                 rx_info = &rx_ring->rx_buffer_info[req_id];
2136                 RTE_ASSERT(rx_info->mbuf != NULL);
2137
2138                 if (unlikely(len == 0)) {
2139                         /*
2140                          * Some devices can pass descriptor with the length 0.
2141                          * To avoid confusion, the PMD is simply putting the
2142                          * descriptor back, as it was never used. We'll avoid
2143                          * mbuf allocation that way.
2144                          */
2145                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2146                                 rx_info->mbuf, req_id);
2147                         if (unlikely(rc != 0)) {
2148                                 /* Free the mbuf in case of an error. */
2149                                 rte_mbuf_raw_free(rx_info->mbuf);
2150                         } else {
2151                                 /*
2152                                  * If there was no error, just exit the loop as
2153                                  * 0 length descriptor is always the last one.
2154                                  */
2155                                 break;
2156                         }
2157                 } else {
2158                         /* Create an mbuf chain. */
2159                         mbuf->next = rx_info->mbuf;
2160                         mbuf = mbuf->next;
2161
2162                         ena_init_rx_mbuf(mbuf, len);
2163                         mbuf_head->pkt_len += len;
2164                 }
2165
2166                 /*
2167                  * Mark the descriptor as depleted and perform necessary
2168                  * cleanup.
2169                  * This code will execute in two cases:
2170                  *  1. Descriptor len was greater than 0 - normal situation.
2171                  *  2. Descriptor len was 0 and we failed to add the descriptor
2172                  *     to the device. In that situation, we should try to add
2173                  *     the mbuf again in the populate routine and mark the
2174                  *     descriptor as used up by the device.
2175                  */
2176                 rx_info->mbuf = NULL;
2177                 rx_ring->empty_rx_reqs[ntc] = req_id;
2178                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2179         }
2180
2181         *next_to_clean = ntc;
2182
2183         return mbuf_head;
2184 }
2185
2186 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2187                                   uint16_t nb_pkts)
2188 {
2189         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2190         unsigned int free_queue_entries;
2191         unsigned int refill_threshold;
2192         uint16_t next_to_clean = rx_ring->next_to_clean;
2193         uint16_t descs_in_use;
2194         struct rte_mbuf *mbuf;
2195         uint16_t completed;
2196         struct ena_com_rx_ctx ena_rx_ctx;
2197         int i, rc = 0;
2198
2199         /* Check adapter state */
2200         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2201                 PMD_DRV_LOG(ALERT,
2202                         "Trying to receive pkts while device is NOT running\n");
2203                 return 0;
2204         }
2205
2206         descs_in_use = rx_ring->ring_size -
2207                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2208         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2209
2210         for (completed = 0; completed < nb_pkts; completed++) {
2211                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2212                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2213                 ena_rx_ctx.descs = 0;
2214                 ena_rx_ctx.pkt_offset = 0;
2215                 /* receive packet context */
2216                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2217                                     rx_ring->ena_com_io_sq,
2218                                     &ena_rx_ctx);
2219                 if (unlikely(rc)) {
2220                         PMD_DRV_LOG(ERR, "ena_com_rx_pkt error %d\n", rc);
2221                         rx_ring->adapter->reset_reason =
2222                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2223                         rx_ring->adapter->trigger_reset = true;
2224                         ++rx_ring->rx_stats.bad_desc_num;
2225                         return 0;
2226                 }
2227
2228                 mbuf = ena_rx_mbuf(rx_ring,
2229                         ena_rx_ctx.ena_bufs,
2230                         ena_rx_ctx.descs,
2231                         &next_to_clean,
2232                         ena_rx_ctx.pkt_offset);
2233                 if (unlikely(mbuf == NULL)) {
2234                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2235                                 rx_ring->empty_rx_reqs[next_to_clean] =
2236                                         rx_ring->ena_bufs[i].req_id;
2237                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2238                                         next_to_clean, rx_ring->size_mask);
2239                         }
2240                         break;
2241                 }
2242
2243                 /* fill mbuf attributes if any */
2244                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx);
2245
2246                 if (unlikely(mbuf->ol_flags &
2247                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2248                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2249                         ++rx_ring->rx_stats.bad_csum;
2250                 }
2251
2252                 mbuf->hash.rss = ena_rx_ctx.hash;
2253
2254                 rx_pkts[completed] = mbuf;
2255                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2256         }
2257
2258         rx_ring->rx_stats.cnt += completed;
2259         rx_ring->next_to_clean = next_to_clean;
2260
2261         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2262         refill_threshold =
2263                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2264                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2265
2266         /* Burst refill to save doorbells, memory barriers, const interval */
2267         if (free_queue_entries > refill_threshold) {
2268                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2269                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2270         }
2271
2272         return completed;
2273 }
2274
2275 static uint16_t
2276 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2277                 uint16_t nb_pkts)
2278 {
2279         int32_t ret;
2280         uint32_t i;
2281         struct rte_mbuf *m;
2282         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2283         struct rte_ipv4_hdr *ip_hdr;
2284         uint64_t ol_flags;
2285         uint16_t frag_field;
2286
2287         for (i = 0; i != nb_pkts; i++) {
2288                 m = tx_pkts[i];
2289                 ol_flags = m->ol_flags;
2290
2291                 if (!(ol_flags & PKT_TX_IPV4))
2292                         continue;
2293
2294                 /* If there was not L2 header length specified, assume it is
2295                  * length of the ethernet header.
2296                  */
2297                 if (unlikely(m->l2_len == 0))
2298                         m->l2_len = sizeof(struct rte_ether_hdr);
2299
2300                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2301                                                  m->l2_len);
2302                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2303
2304                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2305                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2306
2307                         /* If IPv4 header has DF flag enabled and TSO support is
2308                          * disabled, partial chcecksum should not be calculated.
2309                          */
2310                         if (!tx_ring->adapter->offloads.tso4_supported)
2311                                 continue;
2312                 }
2313
2314                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2315                                 (ol_flags & PKT_TX_L4_MASK) ==
2316                                 PKT_TX_SCTP_CKSUM) {
2317                         rte_errno = ENOTSUP;
2318                         return i;
2319                 }
2320
2321 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2322                 ret = rte_validate_tx_offload(m);
2323                 if (ret != 0) {
2324                         rte_errno = -ret;
2325                         return i;
2326                 }
2327 #endif
2328
2329                 /* In case we are supposed to TSO and have DF not set (DF=0)
2330                  * hardware must be provided with partial checksum, otherwise
2331                  * it will take care of necessary calculations.
2332                  */
2333
2334                 ret = rte_net_intel_cksum_flags_prepare(m,
2335                         ol_flags & ~PKT_TX_TCP_SEG);
2336                 if (ret != 0) {
2337                         rte_errno = -ret;
2338                         return i;
2339                 }
2340         }
2341
2342         return i;
2343 }
2344
2345 static void ena_update_hints(struct ena_adapter *adapter,
2346                              struct ena_admin_ena_hw_hints *hints)
2347 {
2348         if (hints->admin_completion_tx_timeout)
2349                 adapter->ena_dev.admin_queue.completion_timeout =
2350                         hints->admin_completion_tx_timeout * 1000;
2351
2352         if (hints->mmio_read_timeout)
2353                 /* convert to usec */
2354                 adapter->ena_dev.mmio_read.reg_read_to =
2355                         hints->mmio_read_timeout * 1000;
2356
2357         if (hints->driver_watchdog_timeout) {
2358                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2359                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2360                 else
2361                         // Convert msecs to ticks
2362                         adapter->keep_alive_timeout =
2363                                 (hints->driver_watchdog_timeout *
2364                                 rte_get_timer_hz()) / 1000;
2365         }
2366 }
2367
2368 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2369                                         struct rte_mbuf *mbuf)
2370 {
2371         struct ena_com_dev *ena_dev;
2372         int num_segments, header_len, rc;
2373
2374         ena_dev = &tx_ring->adapter->ena_dev;
2375         num_segments = mbuf->nb_segs;
2376         header_len = mbuf->data_len;
2377
2378         if (likely(num_segments < tx_ring->sgl_size))
2379                 return 0;
2380
2381         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2382             (num_segments == tx_ring->sgl_size) &&
2383             (header_len < tx_ring->tx_max_header_size))
2384                 return 0;
2385
2386         ++tx_ring->tx_stats.linearize;
2387         rc = rte_pktmbuf_linearize(mbuf);
2388         if (unlikely(rc)) {
2389                 PMD_DRV_LOG(WARNING, "Mbuf linearize failed\n");
2390                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2391                 ++tx_ring->tx_stats.linearize_failed;
2392                 return rc;
2393         }
2394
2395         return rc;
2396 }
2397
2398 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2399         struct ena_tx_buffer *tx_info,
2400         struct rte_mbuf *mbuf,
2401         void **push_header,
2402         uint16_t *header_len)
2403 {
2404         struct ena_com_buf *ena_buf;
2405         uint16_t delta, seg_len, push_len;
2406
2407         delta = 0;
2408         seg_len = mbuf->data_len;
2409
2410         tx_info->mbuf = mbuf;
2411         ena_buf = tx_info->bufs;
2412
2413         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2414                 /*
2415                  * Tx header might be (and will be in most cases) smaller than
2416                  * tx_max_header_size. But it's not an issue to send more data
2417                  * to the device, than actually needed if the mbuf size is
2418                  * greater than tx_max_header_size.
2419                  */
2420                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2421                 *header_len = push_len;
2422
2423                 if (likely(push_len <= seg_len)) {
2424                         /* If the push header is in the single segment, then
2425                          * just point it to the 1st mbuf data.
2426                          */
2427                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2428                 } else {
2429                         /* If the push header lays in the several segments, copy
2430                          * it to the intermediate buffer.
2431                          */
2432                         rte_pktmbuf_read(mbuf, 0, push_len,
2433                                 tx_ring->push_buf_intermediate_buf);
2434                         *push_header = tx_ring->push_buf_intermediate_buf;
2435                         delta = push_len - seg_len;
2436                 }
2437         } else {
2438                 *push_header = NULL;
2439                 *header_len = 0;
2440                 push_len = 0;
2441         }
2442
2443         /* Process first segment taking into consideration pushed header */
2444         if (seg_len > push_len) {
2445                 ena_buf->paddr = mbuf->buf_iova +
2446                                 mbuf->data_off +
2447                                 push_len;
2448                 ena_buf->len = seg_len - push_len;
2449                 ena_buf++;
2450                 tx_info->num_of_bufs++;
2451         }
2452
2453         while ((mbuf = mbuf->next) != NULL) {
2454                 seg_len = mbuf->data_len;
2455
2456                 /* Skip mbufs if whole data is pushed as a header */
2457                 if (unlikely(delta > seg_len)) {
2458                         delta -= seg_len;
2459                         continue;
2460                 }
2461
2462                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2463                 ena_buf->len = seg_len - delta;
2464                 ena_buf++;
2465                 tx_info->num_of_bufs++;
2466
2467                 delta = 0;
2468         }
2469 }
2470
2471 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2472 {
2473         struct ena_tx_buffer *tx_info;
2474         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2475         uint16_t next_to_use;
2476         uint16_t header_len;
2477         uint16_t req_id;
2478         void *push_header;
2479         int nb_hw_desc;
2480         int rc;
2481
2482         rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2483         if (unlikely(rc))
2484                 return rc;
2485
2486         next_to_use = tx_ring->next_to_use;
2487
2488         req_id = tx_ring->empty_tx_reqs[next_to_use];
2489         tx_info = &tx_ring->tx_buffer_info[req_id];
2490         tx_info->num_of_bufs = 0;
2491
2492         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2493
2494         ena_tx_ctx.ena_bufs = tx_info->bufs;
2495         ena_tx_ctx.push_header = push_header;
2496         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2497         ena_tx_ctx.req_id = req_id;
2498         ena_tx_ctx.header_len = header_len;
2499
2500         /* Set Tx offloads flags, if applicable */
2501         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2502                 tx_ring->disable_meta_caching);
2503
2504         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2505                         &ena_tx_ctx))) {
2506                 PMD_DRV_LOG(DEBUG,
2507                         "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2508                         tx_ring->id);
2509                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2510         }
2511
2512         /* prepare the packet's descriptors to dma engine */
2513         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2514                 &nb_hw_desc);
2515         if (unlikely(rc)) {
2516                 ++tx_ring->tx_stats.prepare_ctx_err;
2517                 return rc;
2518         }
2519
2520         tx_info->tx_descs = nb_hw_desc;
2521
2522         tx_ring->tx_stats.cnt++;
2523         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2524
2525         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2526                 tx_ring->size_mask);
2527
2528         return 0;
2529 }
2530
2531 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2532 {
2533         unsigned int cleanup_budget;
2534         unsigned int total_tx_descs = 0;
2535         uint16_t next_to_clean = tx_ring->next_to_clean;
2536
2537         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2538                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2539
2540         while (likely(total_tx_descs < cleanup_budget)) {
2541                 struct rte_mbuf *mbuf;
2542                 struct ena_tx_buffer *tx_info;
2543                 uint16_t req_id;
2544
2545                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2546                         break;
2547
2548                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2549                         break;
2550
2551                 /* Get Tx info & store how many descs were processed  */
2552                 tx_info = &tx_ring->tx_buffer_info[req_id];
2553
2554                 mbuf = tx_info->mbuf;
2555                 rte_pktmbuf_free(mbuf);
2556
2557                 tx_info->mbuf = NULL;
2558                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2559
2560                 total_tx_descs += tx_info->tx_descs;
2561
2562                 /* Put back descriptor to the ring for reuse */
2563                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2564                         tx_ring->size_mask);
2565         }
2566
2567         if (likely(total_tx_descs > 0)) {
2568                 /* acknowledge completion of sent packets */
2569                 tx_ring->next_to_clean = next_to_clean;
2570                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2571                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2572         }
2573 }
2574
2575 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2576                                   uint16_t nb_pkts)
2577 {
2578         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2579         uint16_t sent_idx = 0;
2580
2581         /* Check adapter state */
2582         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2583                 PMD_DRV_LOG(ALERT,
2584                         "Trying to xmit pkts while device is NOT running\n");
2585                 return 0;
2586         }
2587
2588         nb_pkts = RTE_MIN(ena_com_free_q_entries(tx_ring->ena_com_io_sq),
2589                 nb_pkts);
2590
2591         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2592                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2593                         break;
2594
2595                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2596                         tx_ring->size_mask)]);
2597         }
2598
2599         tx_ring->tx_stats.available_desc =
2600                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2601
2602         /* If there are ready packets to be xmitted... */
2603         if (sent_idx > 0) {
2604                 /* ...let HW do its best :-) */
2605                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2606                 tx_ring->tx_stats.doorbells++;
2607         }
2608
2609         ena_tx_cleanup(tx_ring);
2610
2611         tx_ring->tx_stats.available_desc =
2612                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2613         tx_ring->tx_stats.tx_poll++;
2614
2615         return sent_idx;
2616 }
2617
2618 /**
2619  * DPDK callback to retrieve names of extended device statistics
2620  *
2621  * @param dev
2622  *   Pointer to Ethernet device structure.
2623  * @param[out] xstats_names
2624  *   Buffer to insert names into.
2625  * @param n
2626  *   Number of names.
2627  *
2628  * @return
2629  *   Number of xstats names.
2630  */
2631 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2632                                 struct rte_eth_xstat_name *xstats_names,
2633                                 unsigned int n)
2634 {
2635         unsigned int xstats_count = ena_xstats_calc_num(dev);
2636         unsigned int stat, i, count = 0;
2637
2638         if (n < xstats_count || !xstats_names)
2639                 return xstats_count;
2640
2641         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2642                 strcpy(xstats_names[count].name,
2643                         ena_stats_global_strings[stat].name);
2644
2645         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2646                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2647                         snprintf(xstats_names[count].name,
2648                                 sizeof(xstats_names[count].name),
2649                                 "rx_q%d_%s", i,
2650                                 ena_stats_rx_strings[stat].name);
2651
2652         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2653                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2654                         snprintf(xstats_names[count].name,
2655                                 sizeof(xstats_names[count].name),
2656                                 "tx_q%d_%s", i,
2657                                 ena_stats_tx_strings[stat].name);
2658
2659         return xstats_count;
2660 }
2661
2662 /**
2663  * DPDK callback to get extended device statistics.
2664  *
2665  * @param dev
2666  *   Pointer to Ethernet device structure.
2667  * @param[out] stats
2668  *   Stats table output buffer.
2669  * @param n
2670  *   The size of the stats table.
2671  *
2672  * @return
2673  *   Number of xstats on success, negative on failure.
2674  */
2675 static int ena_xstats_get(struct rte_eth_dev *dev,
2676                           struct rte_eth_xstat *xstats,
2677                           unsigned int n)
2678 {
2679         struct ena_adapter *adapter = dev->data->dev_private;
2680         unsigned int xstats_count = ena_xstats_calc_num(dev);
2681         unsigned int stat, i, count = 0;
2682         int stat_offset;
2683         void *stats_begin;
2684
2685         if (n < xstats_count)
2686                 return xstats_count;
2687
2688         if (!xstats)
2689                 return 0;
2690
2691         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2692                 stat_offset = ena_stats_rx_strings[stat].stat_offset;
2693                 stats_begin = &adapter->dev_stats;
2694
2695                 xstats[count].id = count;
2696                 xstats[count].value = *((uint64_t *)
2697                         ((char *)stats_begin + stat_offset));
2698         }
2699
2700         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2701                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2702                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2703                         stats_begin = &adapter->rx_ring[i].rx_stats;
2704
2705                         xstats[count].id = count;
2706                         xstats[count].value = *((uint64_t *)
2707                                 ((char *)stats_begin + stat_offset));
2708                 }
2709         }
2710
2711         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2712                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2713                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2714                         stats_begin = &adapter->tx_ring[i].rx_stats;
2715
2716                         xstats[count].id = count;
2717                         xstats[count].value = *((uint64_t *)
2718                                 ((char *)stats_begin + stat_offset));
2719                 }
2720         }
2721
2722         return count;
2723 }
2724
2725 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2726                                 const uint64_t *ids,
2727                                 uint64_t *values,
2728                                 unsigned int n)
2729 {
2730         struct ena_adapter *adapter = dev->data->dev_private;
2731         uint64_t id;
2732         uint64_t rx_entries, tx_entries;
2733         unsigned int i;
2734         int qid;
2735         int valid = 0;
2736         for (i = 0; i < n; ++i) {
2737                 id = ids[i];
2738                 /* Check if id belongs to global statistics */
2739                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2740                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2741                         ++valid;
2742                         continue;
2743                 }
2744
2745                 /* Check if id belongs to rx queue statistics */
2746                 id -= ENA_STATS_ARRAY_GLOBAL;
2747                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2748                 if (id < rx_entries) {
2749                         qid = id % dev->data->nb_rx_queues;
2750                         id /= dev->data->nb_rx_queues;
2751                         values[i] = *((uint64_t *)
2752                                 &adapter->rx_ring[qid].rx_stats + id);
2753                         ++valid;
2754                         continue;
2755                 }
2756                                 /* Check if id belongs to rx queue statistics */
2757                 id -= rx_entries;
2758                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2759                 if (id < tx_entries) {
2760                         qid = id % dev->data->nb_tx_queues;
2761                         id /= dev->data->nb_tx_queues;
2762                         values[i] = *((uint64_t *)
2763                                 &adapter->tx_ring[qid].tx_stats + id);
2764                         ++valid;
2765                         continue;
2766                 }
2767         }
2768
2769         return valid;
2770 }
2771
2772 static int ena_process_bool_devarg(const char *key,
2773                                    const char *value,
2774                                    void *opaque)
2775 {
2776         struct ena_adapter *adapter = opaque;
2777         bool bool_value;
2778
2779         /* Parse the value. */
2780         if (strcmp(value, "1") == 0) {
2781                 bool_value = true;
2782         } else if (strcmp(value, "0") == 0) {
2783                 bool_value = false;
2784         } else {
2785                 PMD_INIT_LOG(ERR,
2786                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2787                         value, key);
2788                 return -EINVAL;
2789         }
2790
2791         /* Now, assign it to the proper adapter field. */
2792         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR))
2793                 adapter->use_large_llq_hdr = bool_value;
2794
2795         return 0;
2796 }
2797
2798 static int ena_parse_devargs(struct ena_adapter *adapter,
2799                              struct rte_devargs *devargs)
2800 {
2801         static const char * const allowed_args[] = {
2802                 ENA_DEVARG_LARGE_LLQ_HDR,
2803         };
2804         struct rte_kvargs *kvlist;
2805         int rc;
2806
2807         if (devargs == NULL)
2808                 return 0;
2809
2810         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2811         if (kvlist == NULL) {
2812                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2813                         devargs->args);
2814                 return -EINVAL;
2815         }
2816
2817         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2818                 ena_process_bool_devarg, adapter);
2819
2820         rte_kvargs_free(kvlist);
2821
2822         return rc;
2823 }
2824
2825 /*********************************************************************
2826  *  PMD configuration
2827  *********************************************************************/
2828 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2829         struct rte_pci_device *pci_dev)
2830 {
2831         return rte_eth_dev_pci_generic_probe(pci_dev,
2832                 sizeof(struct ena_adapter), eth_ena_dev_init);
2833 }
2834
2835 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2836 {
2837         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2838 }
2839
2840 static struct rte_pci_driver rte_ena_pmd = {
2841         .id_table = pci_id_ena_map,
2842         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2843                      RTE_PCI_DRV_WC_ACTIVATE,
2844         .probe = eth_ena_pci_probe,
2845         .remove = eth_ena_pci_remove,
2846 };
2847
2848 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2849 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2850 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2851 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2852
2853 RTE_INIT(ena_init_log)
2854 {
2855         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2856         if (ena_logtype_init >= 0)
2857                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2858         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2859         if (ena_logtype_driver >= 0)
2860                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2861
2862 #ifdef RTE_LIBRTE_ENA_DEBUG_RX
2863         ena_logtype_rx = rte_log_register("pmd.net.ena.rx");
2864         if (ena_logtype_rx >= 0)
2865                 rte_log_set_level(ena_logtype_rx, RTE_LOG_NOTICE);
2866 #endif
2867
2868 #ifdef RTE_LIBRTE_ENA_DEBUG_TX
2869         ena_logtype_tx = rte_log_register("pmd.net.ena.tx");
2870         if (ena_logtype_tx >= 0)
2871                 rte_log_set_level(ena_logtype_tx, RTE_LOG_NOTICE);
2872 #endif
2873
2874 #ifdef RTE_LIBRTE_ENA_DEBUG_TX_FREE
2875         ena_logtype_tx_free = rte_log_register("pmd.net.ena.tx_free");
2876         if (ena_logtype_tx_free >= 0)
2877                 rte_log_set_level(ena_logtype_tx_free, RTE_LOG_NOTICE);
2878 #endif
2879
2880 #ifdef RTE_LIBRTE_ENA_COM_DEBUG
2881         ena_logtype_com = rte_log_register("pmd.net.ena.com");
2882         if (ena_logtype_com >= 0)
2883                 rte_log_set_level(ena_logtype_com, RTE_LOG_NOTICE);
2884 #endif
2885 }
2886
2887 /******************************************************************************
2888  ******************************** AENQ Handlers *******************************
2889  *****************************************************************************/
2890 static void ena_update_on_link_change(void *adapter_data,
2891                                       struct ena_admin_aenq_entry *aenq_e)
2892 {
2893         struct rte_eth_dev *eth_dev;
2894         struct ena_adapter *adapter;
2895         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2896         uint32_t status;
2897
2898         adapter = adapter_data;
2899         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2900         eth_dev = adapter->rte_dev;
2901
2902         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2903         adapter->link_status = status;
2904
2905         ena_link_update(eth_dev, 0);
2906         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2907 }
2908
2909 static void ena_notification(void *data,
2910                              struct ena_admin_aenq_entry *aenq_e)
2911 {
2912         struct ena_adapter *adapter = data;
2913         struct ena_admin_ena_hw_hints *hints;
2914
2915         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2916                 PMD_DRV_LOG(WARNING, "Invalid group(%x) expected %x\n",
2917                         aenq_e->aenq_common_desc.group,
2918                         ENA_ADMIN_NOTIFICATION);
2919
2920         switch (aenq_e->aenq_common_desc.syndrom) {
2921         case ENA_ADMIN_UPDATE_HINTS:
2922                 hints = (struct ena_admin_ena_hw_hints *)
2923                         (&aenq_e->inline_data_w4);
2924                 ena_update_hints(adapter, hints);
2925                 break;
2926         default:
2927                 PMD_DRV_LOG(ERR, "Invalid aenq notification link state %d\n",
2928                         aenq_e->aenq_common_desc.syndrom);
2929         }
2930 }
2931
2932 static void ena_keep_alive(void *adapter_data,
2933                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2934 {
2935         struct ena_adapter *adapter = adapter_data;
2936         struct ena_admin_aenq_keep_alive_desc *desc;
2937         uint64_t rx_drops;
2938         uint64_t tx_drops;
2939
2940         adapter->timestamp_wd = rte_get_timer_cycles();
2941
2942         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2943         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2944         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2945
2946         adapter->drv_stats->rx_drops = rx_drops;
2947         adapter->dev_stats.tx_drops = tx_drops;
2948 }
2949
2950 /**
2951  * This handler will called for unknown event group or unimplemented handlers
2952  **/
2953 static void unimplemented_aenq_handler(__rte_unused void *data,
2954                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2955 {
2956         PMD_DRV_LOG(ERR, "Unknown event was received or event with "
2957                           "unimplemented handler\n");
2958 }
2959
2960 static struct ena_aenq_handlers aenq_handlers = {
2961         .handlers = {
2962                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2963                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2964                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2965         },
2966         .unimplemented_handler = unimplemented_aenq_handler
2967 };