drivers/net/ena/ena_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
   3  * All rights reserved.
   4  */
   5
   6 #include <rte_string_fns.h>
   7 #include <rte_errno.h>
   8 #include <rte_version.h>
   9 #include <rte_net.h>
  10 #include <rte_kvargs.h>
  11
  12 #include "ena_ethdev.h"
  13 #include "ena_logs.h"
  14 #include "ena_platform.h"
  15 #include "ena_com.h"
  16 #include "ena_eth_com.h"
  17
  18 #include <ena_common_defs.h>
  19 #include <ena_regs_defs.h>
  20 #include <ena_admin_defs.h>
  21 #include <ena_eth_io_defs.h>
  22
  23 #define DRV_MODULE_VER_MAJOR    2
  24 #define DRV_MODULE_VER_MINOR    4
  25 #define DRV_MODULE_VER_SUBMINOR 0
  26
  27 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  28
  29 #define GET_L4_HDR_LEN(mbuf)                                    \
  30         ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *,   \
  31                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  32
  33 #define ETH_GSTRING_LEN 32
  34
  35 #define ARRAY_SIZE(x) RTE_DIM(x)
  36
  37 #define ENA_MIN_RING_DESC       128
  38
  39 #define ENA_PTYPE_HAS_HASH      (RTE_PTYPE_L4_TCP | RTE_PTYPE_L4_UDP)
  40
  41 enum ethtool_stringset {
  42         ETH_SS_TEST             = 0,
  43         ETH_SS_STATS,
  44 };
  45
  46 struct ena_stats {
  47         char name[ETH_GSTRING_LEN];
  48         int stat_offset;
  49 };
  50
  51 #define ENA_STAT_ENTRY(stat, stat_type) { \
  52         .name = #stat, \
  53         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
  54 }
  55
  56 #define ENA_STAT_RX_ENTRY(stat) \
  57         ENA_STAT_ENTRY(stat, rx)
  58
  59 #define ENA_STAT_TX_ENTRY(stat) \
  60         ENA_STAT_ENTRY(stat, tx)
  61
  62 #define ENA_STAT_ENI_ENTRY(stat) \
  63         ENA_STAT_ENTRY(stat, eni)
  64
  65 #define ENA_STAT_GLOBAL_ENTRY(stat) \
  66         ENA_STAT_ENTRY(stat, dev)
  67
  68 /* Device arguments */
  69 #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
  70
  71 /*
  72  * Each rte_memzone should have unique name.
  73  * To satisfy it, count number of allocation and add it to name.
  74  */
  75 rte_atomic64_t ena_alloc_cnt;
  76
  77 static const struct ena_stats ena_stats_global_strings[] = {
  78         ENA_STAT_GLOBAL_ENTRY(wd_expired),
  79         ENA_STAT_GLOBAL_ENTRY(dev_start),
  80         ENA_STAT_GLOBAL_ENTRY(dev_stop),
  81         ENA_STAT_GLOBAL_ENTRY(tx_drops),
  82 };
  83
  84 static const struct ena_stats ena_stats_eni_strings[] = {
  85         ENA_STAT_ENI_ENTRY(bw_in_allowance_exceeded),
  86         ENA_STAT_ENI_ENTRY(bw_out_allowance_exceeded),
  87         ENA_STAT_ENI_ENTRY(pps_allowance_exceeded),
  88         ENA_STAT_ENI_ENTRY(conntrack_allowance_exceeded),
  89         ENA_STAT_ENI_ENTRY(linklocal_allowance_exceeded),
  90 };
  91
  92 static const struct ena_stats ena_stats_tx_strings[] = {
  93         ENA_STAT_TX_ENTRY(cnt),
  94         ENA_STAT_TX_ENTRY(bytes),
  95         ENA_STAT_TX_ENTRY(prepare_ctx_err),
  96         ENA_STAT_TX_ENTRY(linearize),
  97         ENA_STAT_TX_ENTRY(linearize_failed),
  98         ENA_STAT_TX_ENTRY(tx_poll),
  99         ENA_STAT_TX_ENTRY(doorbells),
 100         ENA_STAT_TX_ENTRY(bad_req_id),
 101         ENA_STAT_TX_ENTRY(available_desc),
 102 };
 103
 104 static const struct ena_stats ena_stats_rx_strings[] = {
 105         ENA_STAT_RX_ENTRY(cnt),
 106         ENA_STAT_RX_ENTRY(bytes),
 107         ENA_STAT_RX_ENTRY(refill_partial),
 108         ENA_STAT_RX_ENTRY(bad_csum),
 109         ENA_STAT_RX_ENTRY(mbuf_alloc_fail),
 110         ENA_STAT_RX_ENTRY(bad_desc_num),
 111         ENA_STAT_RX_ENTRY(bad_req_id),
 112 };
 113
 114 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 115 #define ENA_STATS_ARRAY_ENI     ARRAY_SIZE(ena_stats_eni_strings)
 116 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 117 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 118
 119 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 120                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 121                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 122                         DEV_TX_OFFLOAD_TCP_TSO)
 123 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 124                        PKT_TX_IP_CKSUM |\
 125                        PKT_TX_TCP_SEG)
 126
 127 /** Vendor ID used by Amazon devices */
 128 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 129 /** Amazon devices */
 130 #define PCI_DEVICE_ID_ENA_VF            0xEC20
 131 #define PCI_DEVICE_ID_ENA_VF_RSERV0     0xEC21
 132
 133 #define ENA_TX_OFFLOAD_MASK     (\
 134         PKT_TX_L4_MASK |         \
 135         PKT_TX_IPV6 |            \
 136         PKT_TX_IPV4 |            \
 137         PKT_TX_IP_CKSUM |        \
 138         PKT_TX_TCP_SEG)
 139
 140 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 141         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 142
 143 static const struct rte_pci_id pci_id_ena_map[] = {
 144         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 145         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF_RSERV0) },
 146         { .device_id = 0 },
 147 };
 148
 149 static struct ena_aenq_handlers aenq_handlers;
 150
 151 static int ena_device_init(struct ena_com_dev *ena_dev,
 152                            struct rte_pci_device *pdev,
 153                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 154                            bool *wd_state);
 155 static int ena_dev_configure(struct rte_eth_dev *dev);
 156 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
 157         struct ena_tx_buffer *tx_info,
 158         struct rte_mbuf *mbuf,
 159         void **push_header,
 160         uint16_t *header_len);
 161 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf);
 162 static void ena_tx_cleanup(struct ena_ring *tx_ring);
 163 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 164                                   uint16_t nb_pkts);
 165 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 166                 uint16_t nb_pkts);
 167 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 168                               uint16_t nb_desc, unsigned int socket_id,
 169                               const struct rte_eth_txconf *tx_conf);
 170 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 171                               uint16_t nb_desc, unsigned int socket_id,
 172                               const struct rte_eth_rxconf *rx_conf,
 173                               struct rte_mempool *mp);
 174 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len);
 175 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
 176                                     struct ena_com_rx_buf_info *ena_bufs,
 177                                     uint32_t descs,
 178                                     uint16_t *next_to_clean,
 179                                     uint8_t offset);
 180 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 181                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 182 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
 183                                   struct rte_mbuf *mbuf, uint16_t id);
 184 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 185 static void ena_init_rings(struct ena_adapter *adapter,
 186                            bool disable_meta_caching);
 187 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188 static int ena_start(struct rte_eth_dev *dev);
 189 static int ena_stop(struct rte_eth_dev *dev);
 190 static int ena_close(struct rte_eth_dev *dev);
 191 static int ena_dev_reset(struct rte_eth_dev *dev);
 192 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 193 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 194 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 195 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 196 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
 197 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 198 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 199 static int ena_link_update(struct rte_eth_dev *dev,
 200                            int wait_to_complete);
 201 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring);
 202 static void ena_queue_stop(struct ena_ring *ring);
 203 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 204                               enum ena_ring_type ring_type);
 205 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring);
 206 static int ena_queue_start_all(struct rte_eth_dev *dev,
 207                                enum ena_ring_type ring_type);
 208 static void ena_stats_restart(struct rte_eth_dev *dev);
 209 static int ena_infos_get(struct rte_eth_dev *dev,
 210                          struct rte_eth_dev_info *dev_info);
 211 static void ena_interrupt_handler_rte(void *cb_arg);
 212 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 213 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 214 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 215 static int ena_xstats_get_names(struct rte_eth_dev *dev,
 216                                 struct rte_eth_xstat_name *xstats_names,
 217                                 unsigned int n);
 218 static int ena_xstats_get(struct rte_eth_dev *dev,
 219                           struct rte_eth_xstat *stats,
 220                           unsigned int n);
 221 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
 222                                 const uint64_t *ids,
 223                                 uint64_t *values,
 224                                 unsigned int n);
 225 static int ena_process_bool_devarg(const char *key,
 226                                    const char *value,
 227                                    void *opaque);
 228 static int ena_parse_devargs(struct ena_adapter *adapter,
 229                              struct rte_devargs *devargs);
 230 static int ena_copy_eni_stats(struct ena_adapter *adapter);
 231 static int ena_setup_rx_intr(struct rte_eth_dev *dev);
 232 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
 233                                     uint16_t queue_id);
 234 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
 235                                      uint16_t queue_id);
 236
 237 static const struct eth_dev_ops ena_dev_ops = {
 238         .dev_configure        = ena_dev_configure,
 239         .dev_infos_get        = ena_infos_get,
 240         .rx_queue_setup       = ena_rx_queue_setup,
 241         .tx_queue_setup       = ena_tx_queue_setup,
 242         .dev_start            = ena_start,
 243         .dev_stop             = ena_stop,
 244         .link_update          = ena_link_update,
 245         .stats_get            = ena_stats_get,
 246         .xstats_get_names     = ena_xstats_get_names,
 247         .xstats_get           = ena_xstats_get,
 248         .xstats_get_by_id     = ena_xstats_get_by_id,
 249         .mtu_set              = ena_mtu_set,
 250         .rx_queue_release     = ena_rx_queue_release,
 251         .tx_queue_release     = ena_tx_queue_release,
 252         .dev_close            = ena_close,
 253         .dev_reset            = ena_dev_reset,
 254         .reta_update          = ena_rss_reta_update,
 255         .reta_query           = ena_rss_reta_query,
 256         .rx_queue_intr_enable = ena_rx_queue_intr_enable,
 257         .rx_queue_intr_disable = ena_rx_queue_intr_disable,
 258         .rss_hash_update      = ena_rss_hash_update,
 259         .rss_hash_conf_get    = ena_rss_hash_conf_get,
 260 };
 261
 262 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 263                                        struct ena_com_rx_ctx *ena_rx_ctx,
 264                                        bool fill_hash)
 265 {
 266         uint64_t ol_flags = 0;
 267         uint32_t packet_type = 0;
 268
 269         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 270                 packet_type |= RTE_PTYPE_L4_TCP;
 271         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 272                 packet_type |= RTE_PTYPE_L4_UDP;
 273
 274         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 275                 packet_type |= RTE_PTYPE_L3_IPV4;
 276                 if (unlikely(ena_rx_ctx->l3_csum_err))
 277                         ol_flags |= PKT_RX_IP_CKSUM_BAD;
 278                 else
 279                         ol_flags |= PKT_RX_IP_CKSUM_GOOD;
 280         } else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 281                 packet_type |= RTE_PTYPE_L3_IPV6;
 282         }
 283
 284         if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 285                 ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 286         else
 287                 if (unlikely(ena_rx_ctx->l4_csum_err))
 288                         ol_flags |= PKT_RX_L4_CKSUM_BAD;
 289                 else
 290                         ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 291
 292         if (fill_hash &&
 293             likely((packet_type & ENA_PTYPE_HAS_HASH) && !ena_rx_ctx->frag)) {
 294                 ol_flags |= PKT_RX_RSS_HASH;
 295                 mbuf->hash.rss = ena_rx_ctx->hash;
 296         }
 297
 298         mbuf->ol_flags = ol_flags;
 299         mbuf->packet_type = packet_type;
 300 }
 301
 302 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 303                                        struct ena_com_tx_ctx *ena_tx_ctx,
 304                                        uint64_t queue_offloads,
 305                                        bool disable_meta_caching)
 306 {
 307         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 308
 309         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 310             (queue_offloads & QUEUE_OFFLOADS)) {
 311                 /* check if TSO is required */
 312                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 313                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 314                         ena_tx_ctx->tso_enable = true;
 315
 316                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 317                 }
 318
 319                 /* check if L3 checksum is needed */
 320                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 321                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 322                         ena_tx_ctx->l3_csum_enable = true;
 323
 324                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 325                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 326                 } else {
 327                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 328
 329                         /* set don't fragment (DF) flag */
 330                         if (mbuf->packet_type &
 331                                 (RTE_PTYPE_L4_NONFRAG
 332                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 333                                 ena_tx_ctx->df = true;
 334                 }
 335
 336                 /* check if L4 checksum is needed */
 337                 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 339                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 340                         ena_tx_ctx->l4_csum_enable = true;
 341                 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) ==
 342                                 PKT_TX_UDP_CKSUM) &&
 343                                 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 344                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 345                         ena_tx_ctx->l4_csum_enable = true;
 346                 } else {
 347                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 348                         ena_tx_ctx->l4_csum_enable = false;
 349                 }
 350
 351                 ena_meta->mss = mbuf->tso_segsz;
 352                 ena_meta->l3_hdr_len = mbuf->l3_len;
 353                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 354
 355                 ena_tx_ctx->meta_valid = true;
 356         } else if (disable_meta_caching) {
 357                 memset(ena_meta, 0, sizeof(*ena_meta));
 358                 ena_tx_ctx->meta_valid = true;
 359         } else {
 360                 ena_tx_ctx->meta_valid = false;
 361         }
 362 }
 363
 364 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 365 {
 366         struct ena_tx_buffer *tx_info = NULL;
 367
 368         if (likely(req_id < tx_ring->ring_size)) {
 369                 tx_info = &tx_ring->tx_buffer_info[req_id];
 370                 if (likely(tx_info->mbuf))
 371                         return 0;
 372         }
 373
 374         if (tx_info)
 375                 PMD_TX_LOG(ERR, "tx_info doesn't have valid mbuf\n");
 376         else
 377                 PMD_TX_LOG(ERR, "Invalid req_id: %hu\n", req_id);
 378
 379         /* Trigger device reset */
 380         ++tx_ring->tx_stats.bad_req_id;
 381         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 382         tx_ring->adapter->trigger_reset = true;
 383         return -EFAULT;
 384 }
 385
 386 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 387 {
 388         struct ena_admin_host_info *host_info;
 389         int rc;
 390
 391         /* Allocate only the host info */
 392         rc = ena_com_allocate_host_info(ena_dev);
 393         if (rc) {
 394                 PMD_DRV_LOG(ERR, "Cannot allocate host info\n");
 395                 return;
 396         }
 397
 398         host_info = ena_dev->host_attr.host_info;
 399
 400         host_info->os_type = ENA_ADMIN_OS_DPDK;
 401         host_info->kernel_ver = RTE_VERSION;
 402         strlcpy((char *)host_info->kernel_ver_str, rte_version(),
 403                 sizeof(host_info->kernel_ver_str));
 404         host_info->os_dist = RTE_VERSION;
 405         strlcpy((char *)host_info->os_dist_str, rte_version(),
 406                 sizeof(host_info->os_dist_str));
 407         host_info->driver_version =
 408                 (DRV_MODULE_VER_MAJOR) |
 409                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 410                 (DRV_MODULE_VER_SUBMINOR <<
 411                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 412         host_info->num_cpus = rte_lcore_count();
 413
 414         host_info->driver_supported_features =
 415                 ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK |
 416                 ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
 417
 418         rc = ena_com_set_host_attributes(ena_dev);
 419         if (rc) {
 420                 if (rc == -ENA_COM_UNSUPPORTED)
 421                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 422                 else
 423                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 424
 425                 goto err;
 426         }
 427
 428         return;
 429
 430 err:
 431         ena_com_delete_host_info(ena_dev);
 432 }
 433
 434 /* This function calculates the number of xstats based on the current config */
 435 static unsigned int ena_xstats_calc_num(struct rte_eth_dev_data *data)
 436 {
 437         return ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENI +
 438                 (data->nb_tx_queues * ENA_STATS_ARRAY_TX) +
 439                 (data->nb_rx_queues * ENA_STATS_ARRAY_RX);
 440 }
 441
 442 static void ena_config_debug_area(struct ena_adapter *adapter)
 443 {
 444         u32 debug_area_size;
 445         int rc, ss_count;
 446
 447         ss_count = ena_xstats_calc_num(adapter->edev_data);
 448
 449         /* allocate 32 bytes for each string and 64bit for the value */
 450         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 451
 452         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 453         if (rc) {
 454                 PMD_DRV_LOG(ERR, "Cannot allocate debug area\n");
 455                 return;
 456         }
 457
 458         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 459         if (rc) {
 460                 if (rc == -ENA_COM_UNSUPPORTED)
 461                         PMD_DRV_LOG(WARNING, "Cannot set host attributes\n");
 462                 else
 463                         PMD_DRV_LOG(ERR, "Cannot set host attributes\n");
 464
 465                 goto err;
 466         }
 467
 468         return;
 469 err:
 470         ena_com_delete_debug_area(&adapter->ena_dev);
 471 }
 472
 473 static int ena_close(struct rte_eth_dev *dev)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 476         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 477         struct ena_adapter *adapter = dev->data->dev_private;
 478         int ret = 0;
 479
 480         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 481                 return 0;
 482
 483         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 484                 ret = ena_stop(dev);
 485         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 486
 487         ena_rx_queue_release_all(dev);
 488         ena_tx_queue_release_all(dev);
 489
 490         rte_free(adapter->drv_stats);
 491         adapter->drv_stats = NULL;
 492
 493         rte_intr_disable(intr_handle);
 494         rte_intr_callback_unregister(intr_handle,
 495                                      ena_interrupt_handler_rte,
 496                                      dev);
 497
 498         /*
 499          * MAC is not allocated dynamically. Setting NULL should prevent from
 500          * release of the resource in the rte_eth_dev_release_port().
 501          */
 502         dev->data->mac_addrs = NULL;
 503
 504         return ret;
 505 }
 506
 507 static int
 508 ena_dev_reset(struct rte_eth_dev *dev)
 509 {
 510         int rc = 0;
 511
 512         /* Cannot release memory in secondary process */
 513         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 514                 PMD_DRV_LOG(WARNING, "dev_reset not supported in secondary.\n");
 515                 return -EPERM;
 516         }
 517
 518         ena_destroy_device(dev);
 519         rc = eth_ena_dev_init(dev);
 520         if (rc)
 521                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 522
 523         return rc;
 524 }
 525
 526 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 527 {
 528         int nb_queues = dev->data->nb_rx_queues;
 529         int i;
 530
 531         for (i = 0; i < nb_queues; i++)
 532                 ena_rx_queue_release(dev, i);
 533 }
 534
 535 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 536 {
 537         int nb_queues = dev->data->nb_tx_queues;
 538         int i;
 539
 540         for (i = 0; i < nb_queues; i++)
 541                 ena_tx_queue_release(dev, i);
 542 }
 543
 544 static void ena_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 545 {
 546         struct ena_ring *ring = dev->data->rx_queues[qid];
 547
 548         /* Free ring resources */
 549         if (ring->rx_buffer_info)
 550                 rte_free(ring->rx_buffer_info);
 551         ring->rx_buffer_info = NULL;
 552
 553         if (ring->rx_refill_buffer)
 554                 rte_free(ring->rx_refill_buffer);
 555         ring->rx_refill_buffer = NULL;
 556
 557         if (ring->empty_rx_reqs)
 558                 rte_free(ring->empty_rx_reqs);
 559         ring->empty_rx_reqs = NULL;
 560
 561         ring->configured = 0;
 562
 563         PMD_DRV_LOG(NOTICE, "Rx queue %d:%d released\n",
 564                 ring->port_id, ring->id);
 565 }
 566
 567 static void ena_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
 568 {
 569         struct ena_ring *ring = dev->data->tx_queues[qid];
 570
 571         /* Free ring resources */
 572         if (ring->push_buf_intermediate_buf)
 573                 rte_free(ring->push_buf_intermediate_buf);
 574
 575         if (ring->tx_buffer_info)
 576                 rte_free(ring->tx_buffer_info);
 577
 578         if (ring->empty_tx_reqs)
 579                 rte_free(ring->empty_tx_reqs);
 580
 581         ring->empty_tx_reqs = NULL;
 582         ring->tx_buffer_info = NULL;
 583         ring->push_buf_intermediate_buf = NULL;
 584
 585         ring->configured = 0;
 586
 587         PMD_DRV_LOG(NOTICE, "Tx queue %d:%d released\n",
 588                 ring->port_id, ring->id);
 589 }
 590
 591 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 592 {
 593         unsigned int i;
 594
 595         for (i = 0; i < ring->ring_size; ++i) {
 596                 struct ena_rx_buffer *rx_info = &ring->rx_buffer_info[i];
 597                 if (rx_info->mbuf) {
 598                         rte_mbuf_raw_free(rx_info->mbuf);
 599                         rx_info->mbuf = NULL;
 600                 }
 601         }
 602 }
 603
 604 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 605 {
 606         unsigned int i;
 607
 608         for (i = 0; i < ring->ring_size; ++i) {
 609                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 610
 611                 if (tx_buf->mbuf) {
 612                         rte_pktmbuf_free(tx_buf->mbuf);
 613                         tx_buf->mbuf = NULL;
 614                 }
 615         }
 616 }
 617
 618 static int ena_link_update(struct rte_eth_dev *dev,
 619                            __rte_unused int wait_to_complete)
 620 {
 621         struct rte_eth_link *link = &dev->data->dev_link;
 622         struct ena_adapter *adapter = dev->data->dev_private;
 623
 624         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 625         link->link_speed = ETH_SPEED_NUM_NONE;
 626         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 627
 628         return 0;
 629 }
 630
 631 static int ena_queue_start_all(struct rte_eth_dev *dev,
 632                                enum ena_ring_type ring_type)
 633 {
 634         struct ena_adapter *adapter = dev->data->dev_private;
 635         struct ena_ring *queues = NULL;
 636         int nb_queues;
 637         int i = 0;
 638         int rc = 0;
 639
 640         if (ring_type == ENA_RING_TYPE_RX) {
 641                 queues = adapter->rx_ring;
 642                 nb_queues = dev->data->nb_rx_queues;
 643         } else {
 644                 queues = adapter->tx_ring;
 645                 nb_queues = dev->data->nb_tx_queues;
 646         }
 647         for (i = 0; i < nb_queues; i++) {
 648                 if (queues[i].configured) {
 649                         if (ring_type == ENA_RING_TYPE_RX) {
 650                                 ena_assert_msg(
 651                                         dev->data->rx_queues[i] == &queues[i],
 652                                         "Inconsistent state of Rx queues\n");
 653                         } else {
 654                                 ena_assert_msg(
 655                                         dev->data->tx_queues[i] == &queues[i],
 656                                         "Inconsistent state of Tx queues\n");
 657                         }
 658
 659                         rc = ena_queue_start(dev, &queues[i]);
 660
 661                         if (rc) {
 662                                 PMD_INIT_LOG(ERR,
 663                                         "Failed to start queue[%d] of type(%d)\n",
 664                                         i, ring_type);
 665                                 goto err;
 666                         }
 667                 }
 668         }
 669
 670         return 0;
 671
 672 err:
 673         while (i--)
 674                 if (queues[i].configured)
 675                         ena_queue_stop(&queues[i]);
 676
 677         return rc;
 678 }
 679
 680 static int ena_check_valid_conf(struct ena_adapter *adapter)
 681 {
 682         uint32_t mtu = adapter->edev_data->mtu;
 683
 684         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 685                 PMD_INIT_LOG(ERR,
 686                         "Unsupported MTU of %d. Max MTU: %d, min MTU: %d\n",
 687                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 688                 return ENA_COM_UNSUPPORTED;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static int
 695 ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,
 696                        bool use_large_llq_hdr)
 697 {
 698         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 699         struct ena_com_dev *ena_dev = ctx->ena_dev;
 700         uint32_t max_tx_queue_size;
 701         uint32_t max_rx_queue_size;
 702
 703         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 704                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 705                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 706                 max_rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 707                         max_queue_ext->max_rx_sq_depth);
 708                 max_tx_queue_size = max_queue_ext->max_tx_cq_depth;
 709
 710                 if (ena_dev->tx_mem_queue_type ==
 711                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 712                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 713                                 llq->max_llq_depth);
 714                 } else {
 715                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 716                                 max_queue_ext->max_tx_sq_depth);
 717                 }
 718
 719                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 720                         max_queue_ext->max_per_packet_rx_descs);
 721                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 722                         max_queue_ext->max_per_packet_tx_descs);
 723         } else {
 724                 struct ena_admin_queue_feature_desc *max_queues =
 725                         &ctx->get_feat_ctx->max_queues;
 726                 max_rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 727                         max_queues->max_sq_depth);
 728                 max_tx_queue_size = max_queues->max_cq_depth;
 729
 730                 if (ena_dev->tx_mem_queue_type ==
 731                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 732                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 733                                 llq->max_llq_depth);
 734                 } else {
 735                         max_tx_queue_size = RTE_MIN(max_tx_queue_size,
 736                                 max_queues->max_sq_depth);
 737                 }
 738
 739                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 740                         max_queues->max_packet_rx_descs);
 741                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 742                         max_queues->max_packet_tx_descs);
 743         }
 744
 745         /* Round down to the nearest power of 2 */
 746         max_rx_queue_size = rte_align32prevpow2(max_rx_queue_size);
 747         max_tx_queue_size = rte_align32prevpow2(max_tx_queue_size);
 748
 749         if (use_large_llq_hdr) {
 750                 if ((llq->entry_size_ctrl_supported &
 751                      ENA_ADMIN_LIST_ENTRY_SIZE_256B) &&
 752                     (ena_dev->tx_mem_queue_type ==
 753                      ENA_ADMIN_PLACEMENT_POLICY_DEV)) {
 754                         max_tx_queue_size /= 2;
 755                         PMD_INIT_LOG(INFO,
 756                                 "Forcing large headers and decreasing maximum Tx queue size to %d\n",
 757                                 max_tx_queue_size);
 758                 } else {
 759                         PMD_INIT_LOG(ERR,
 760                                 "Forcing large headers failed: LLQ is disabled or device does not support large headers\n");
 761                 }
 762         }
 763
 764         if (unlikely(max_rx_queue_size == 0 || max_tx_queue_size == 0)) {
 765                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 766                 return -EFAULT;
 767         }
 768
 769         ctx->max_tx_queue_size = max_tx_queue_size;
 770         ctx->max_rx_queue_size = max_rx_queue_size;
 771
 772         return 0;
 773 }
 774
 775 static void ena_stats_restart(struct rte_eth_dev *dev)
 776 {
 777         struct ena_adapter *adapter = dev->data->dev_private;
 778
 779         rte_atomic64_init(&adapter->drv_stats->ierrors);
 780         rte_atomic64_init(&adapter->drv_stats->oerrors);
 781         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 782         adapter->drv_stats->rx_drops = 0;
 783 }
 784
 785 static int ena_stats_get(struct rte_eth_dev *dev,
 786                           struct rte_eth_stats *stats)
 787 {
 788         struct ena_admin_basic_stats ena_stats;
 789         struct ena_adapter *adapter = dev->data->dev_private;
 790         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 791         int rc;
 792         int i;
 793         int max_rings_stats;
 794
 795         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 796                 return -ENOTSUP;
 797
 798         memset(&ena_stats, 0, sizeof(ena_stats));
 799
 800         rte_spinlock_lock(&adapter->admin_lock);
 801         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 802         rte_spinlock_unlock(&adapter->admin_lock);
 803         if (unlikely(rc)) {
 804                 PMD_DRV_LOG(ERR, "Could not retrieve statistics from ENA\n");
 805                 return rc;
 806         }
 807
 808         /* Set of basic statistics from ENA */
 809         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 810                                           ena_stats.rx_pkts_low);
 811         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 812                                           ena_stats.tx_pkts_low);
 813         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 814                                         ena_stats.rx_bytes_low);
 815         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 816                                         ena_stats.tx_bytes_low);
 817
 818         /* Driver related stats */
 819         stats->imissed = adapter->drv_stats->rx_drops;
 820         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 821         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 822         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 823
 824         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
 825                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 826         for (i = 0; i < max_rings_stats; ++i) {
 827                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
 828
 829                 stats->q_ibytes[i] = rx_stats->bytes;
 830                 stats->q_ipackets[i] = rx_stats->cnt;
 831                 stats->q_errors[i] = rx_stats->bad_desc_num +
 832                         rx_stats->bad_req_id;
 833         }
 834
 835         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
 836                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
 837         for (i = 0; i < max_rings_stats; ++i) {
 838                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
 839
 840                 stats->q_obytes[i] = tx_stats->bytes;
 841                 stats->q_opackets[i] = tx_stats->cnt;
 842         }
 843
 844         return 0;
 845 }
 846
 847 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 848 {
 849         struct ena_adapter *adapter;
 850         struct ena_com_dev *ena_dev;
 851         int rc = 0;
 852
 853         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
 854         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
 855         adapter = dev->data->dev_private;
 856
 857         ena_dev = &adapter->ena_dev;
 858         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
 859
 860         if (mtu > adapter->max_mtu || mtu < ENA_MIN_MTU) {
 861                 PMD_DRV_LOG(ERR,
 862                         "Invalid MTU setting. New MTU: %d, max MTU: %d, min MTU: %d\n",
 863                         mtu, adapter->max_mtu, ENA_MIN_MTU);
 864                 return -EINVAL;
 865         }
 866
 867         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 868         if (rc)
 869                 PMD_DRV_LOG(ERR, "Could not set MTU: %d\n", mtu);
 870         else
 871                 PMD_DRV_LOG(NOTICE, "MTU set to: %d\n", mtu);
 872
 873         return rc;
 874 }
 875
 876 static int ena_start(struct rte_eth_dev *dev)
 877 {
 878         struct ena_adapter *adapter = dev->data->dev_private;
 879         uint64_t ticks;
 880         int rc = 0;
 881
 882         /* Cannot allocate memory in secondary process */
 883         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 884                 PMD_DRV_LOG(WARNING, "dev_start not supported in secondary.\n");
 885                 return -EPERM;
 886         }
 887
 888         rc = ena_check_valid_conf(adapter);
 889         if (rc)
 890                 return rc;
 891
 892         rc = ena_setup_rx_intr(dev);
 893         if (rc)
 894                 return rc;
 895
 896         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
 897         if (rc)
 898                 return rc;
 899
 900         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
 901         if (rc)
 902                 goto err_start_tx;
 903
 904         if (adapter->edev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 905                 rc = ena_rss_configure(adapter);
 906                 if (rc)
 907                         goto err_rss_init;
 908         }
 909
 910         ena_stats_restart(dev);
 911
 912         adapter->timestamp_wd = rte_get_timer_cycles();
 913         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
 914
 915         ticks = rte_get_timer_hz();
 916         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
 917                         ena_timer_wd_callback, dev);
 918
 919         ++adapter->dev_stats.dev_start;
 920         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 921
 922         return 0;
 923
 924 err_rss_init:
 925         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 926 err_start_tx:
 927         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 928         return rc;
 929 }
 930
 931 static int ena_stop(struct rte_eth_dev *dev)
 932 {
 933         struct ena_adapter *adapter = dev->data->dev_private;
 934         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 936         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 937         int rc;
 938
 939         /* Cannot free memory in secondary process */
 940         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 941                 PMD_DRV_LOG(WARNING, "dev_stop not supported in secondary.\n");
 942                 return -EPERM;
 943         }
 944
 945         rte_timer_stop_sync(&adapter->timer_wd);
 946         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
 947         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
 948
 949         if (adapter->trigger_reset) {
 950                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 951                 if (rc)
 952                         PMD_DRV_LOG(ERR, "Device reset failed, rc: %d\n", rc);
 953         }
 954
 955         rte_intr_disable(intr_handle);
 956
 957         rte_intr_efd_disable(intr_handle);
 958         if (intr_handle->intr_vec != NULL) {
 959                 rte_free(intr_handle->intr_vec);
 960                 intr_handle->intr_vec = NULL;
 961         }
 962
 963         rte_intr_enable(intr_handle);
 964
 965         ++adapter->dev_stats.dev_stop;
 966         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 967         dev->data->dev_started = 0;
 968
 969         return 0;
 970 }
 971
 972 static int ena_create_io_queue(struct rte_eth_dev *dev, struct ena_ring *ring)
 973 {
 974         struct ena_adapter *adapter = ring->adapter;
 975         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 976         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 977         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 978         struct ena_com_create_io_ctx ctx =
 979                 /* policy set to _HOST just to satisfy icc compiler */
 980                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 981                   0, 0, 0, 0, 0 };
 982         uint16_t ena_qid;
 983         unsigned int i;
 984         int rc;
 985
 986         ctx.msix_vector = -1;
 987         if (ring->type == ENA_RING_TYPE_TX) {
 988                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
 989                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 990                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 991                 for (i = 0; i < ring->ring_size; i++)
 992                         ring->empty_tx_reqs[i] = i;
 993         } else {
 994                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
 995                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
 996                 if (rte_intr_dp_is_en(intr_handle))
 997                         ctx.msix_vector = intr_handle->intr_vec[ring->id];
 998                 for (i = 0; i < ring->ring_size; i++)
 999                         ring->empty_rx_reqs[i] = i;
1000         }
1001         ctx.queue_size = ring->ring_size;
1002         ctx.qid = ena_qid;
1003         ctx.numa_node = ring->numa_socket_id;
1004
1005         rc = ena_com_create_io_queue(ena_dev, &ctx);
1006         if (rc) {
1007                 PMD_DRV_LOG(ERR,
1008                         "Failed to create IO queue[%d] (qid:%d), rc: %d\n",
1009                         ring->id, ena_qid, rc);
1010                 return rc;
1011         }
1012
1013         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1014                                      &ring->ena_com_io_sq,
1015                                      &ring->ena_com_io_cq);
1016         if (rc) {
1017                 PMD_DRV_LOG(ERR,
1018                         "Failed to get IO queue[%d] handlers, rc: %d\n",
1019                         ring->id, rc);
1020                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1021                 return rc;
1022         }
1023
1024         if (ring->type == ENA_RING_TYPE_TX)
1025                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1026
1027         /* Start with Rx interrupts being masked. */
1028         if (ring->type == ENA_RING_TYPE_RX && rte_intr_dp_is_en(intr_handle))
1029                 ena_rx_queue_intr_disable(dev, ring->id);
1030
1031         return 0;
1032 }
1033
1034 static void ena_queue_stop(struct ena_ring *ring)
1035 {
1036         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1037
1038         if (ring->type == ENA_RING_TYPE_RX) {
1039                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1040                 ena_rx_queue_release_bufs(ring);
1041         } else {
1042                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1043                 ena_tx_queue_release_bufs(ring);
1044         }
1045 }
1046
1047 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1048                               enum ena_ring_type ring_type)
1049 {
1050         struct ena_adapter *adapter = dev->data->dev_private;
1051         struct ena_ring *queues = NULL;
1052         uint16_t nb_queues, i;
1053
1054         if (ring_type == ENA_RING_TYPE_RX) {
1055                 queues = adapter->rx_ring;
1056                 nb_queues = dev->data->nb_rx_queues;
1057         } else {
1058                 queues = adapter->tx_ring;
1059                 nb_queues = dev->data->nb_tx_queues;
1060         }
1061
1062         for (i = 0; i < nb_queues; ++i)
1063                 if (queues[i].configured)
1064                         ena_queue_stop(&queues[i]);
1065 }
1066
1067 static int ena_queue_start(struct rte_eth_dev *dev, struct ena_ring *ring)
1068 {
1069         int rc, bufs_num;
1070
1071         ena_assert_msg(ring->configured == 1,
1072                        "Trying to start unconfigured queue\n");
1073
1074         rc = ena_create_io_queue(dev, ring);
1075         if (rc) {
1076                 PMD_INIT_LOG(ERR, "Failed to create IO queue\n");
1077                 return rc;
1078         }
1079
1080         ring->next_to_clean = 0;
1081         ring->next_to_use = 0;
1082
1083         if (ring->type == ENA_RING_TYPE_TX) {
1084                 ring->tx_stats.available_desc =
1085                         ena_com_free_q_entries(ring->ena_com_io_sq);
1086                 return 0;
1087         }
1088
1089         bufs_num = ring->ring_size - 1;
1090         rc = ena_populate_rx_queue(ring, bufs_num);
1091         if (rc != bufs_num) {
1092                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1093                                          ENA_IO_RXQ_IDX(ring->id));
1094                 PMD_INIT_LOG(ERR, "Failed to populate Rx ring\n");
1095                 return ENA_COM_FAULT;
1096         }
1097         /* Flush per-core RX buffers pools cache as they can be used on other
1098          * cores as well.
1099          */
1100         rte_mempool_cache_flush(NULL, ring->mb_pool);
1101
1102         return 0;
1103 }
1104
1105 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1106                               uint16_t queue_idx,
1107                               uint16_t nb_desc,
1108                               unsigned int socket_id,
1109                               const struct rte_eth_txconf *tx_conf)
1110 {
1111         struct ena_ring *txq = NULL;
1112         struct ena_adapter *adapter = dev->data->dev_private;
1113         unsigned int i;
1114
1115         txq = &adapter->tx_ring[queue_idx];
1116
1117         if (txq->configured) {
1118                 PMD_DRV_LOG(CRIT,
1119                         "API violation. Queue[%d] is already configured\n",
1120                         queue_idx);
1121                 return ENA_COM_FAULT;
1122         }
1123
1124         if (!rte_is_power_of_2(nb_desc)) {
1125                 PMD_DRV_LOG(ERR,
1126                         "Unsupported size of Tx queue: %d is not a power of 2.\n",
1127                         nb_desc);
1128                 return -EINVAL;
1129         }
1130
1131         if (nb_desc > adapter->max_tx_ring_size) {
1132                 PMD_DRV_LOG(ERR,
1133                         "Unsupported size of Tx queue (max size: %d)\n",
1134                         adapter->max_tx_ring_size);
1135                 return -EINVAL;
1136         }
1137
1138         txq->port_id = dev->data->port_id;
1139         txq->next_to_clean = 0;
1140         txq->next_to_use = 0;
1141         txq->ring_size = nb_desc;
1142         txq->size_mask = nb_desc - 1;
1143         txq->numa_socket_id = socket_id;
1144         txq->pkts_without_db = false;
1145
1146         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1147                                           sizeof(struct ena_tx_buffer) *
1148                                           txq->ring_size,
1149                                           RTE_CACHE_LINE_SIZE);
1150         if (!txq->tx_buffer_info) {
1151                 PMD_DRV_LOG(ERR,
1152                         "Failed to allocate memory for Tx buffer info\n");
1153                 return -ENOMEM;
1154         }
1155
1156         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1157                                          sizeof(u16) * txq->ring_size,
1158                                          RTE_CACHE_LINE_SIZE);
1159         if (!txq->empty_tx_reqs) {
1160                 PMD_DRV_LOG(ERR,
1161                         "Failed to allocate memory for empty Tx requests\n");
1162                 rte_free(txq->tx_buffer_info);
1163                 return -ENOMEM;
1164         }
1165
1166         txq->push_buf_intermediate_buf =
1167                 rte_zmalloc("txq->push_buf_intermediate_buf",
1168                             txq->tx_max_header_size,
1169                             RTE_CACHE_LINE_SIZE);
1170         if (!txq->push_buf_intermediate_buf) {
1171                 PMD_DRV_LOG(ERR, "Failed to alloc push buffer for LLQ\n");
1172                 rte_free(txq->tx_buffer_info);
1173                 rte_free(txq->empty_tx_reqs);
1174                 return -ENOMEM;
1175         }
1176
1177         for (i = 0; i < txq->ring_size; i++)
1178                 txq->empty_tx_reqs[i] = i;
1179
1180         if (tx_conf != NULL) {
1181                 txq->offloads =
1182                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1183         }
1184         /* Store pointer to this queue in upper layer */
1185         txq->configured = 1;
1186         dev->data->tx_queues[queue_idx] = txq;
1187
1188         return 0;
1189 }
1190
1191 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1192                               uint16_t queue_idx,
1193                               uint16_t nb_desc,
1194                               unsigned int socket_id,
1195                               const struct rte_eth_rxconf *rx_conf,
1196                               struct rte_mempool *mp)
1197 {
1198         struct ena_adapter *adapter = dev->data->dev_private;
1199         struct ena_ring *rxq = NULL;
1200         size_t buffer_size;
1201         int i;
1202
1203         rxq = &adapter->rx_ring[queue_idx];
1204         if (rxq->configured) {
1205                 PMD_DRV_LOG(CRIT,
1206                         "API violation. Queue[%d] is already configured\n",
1207                         queue_idx);
1208                 return ENA_COM_FAULT;
1209         }
1210
1211         if (!rte_is_power_of_2(nb_desc)) {
1212                 PMD_DRV_LOG(ERR,
1213                         "Unsupported size of Rx queue: %d is not a power of 2.\n",
1214                         nb_desc);
1215                 return -EINVAL;
1216         }
1217
1218         if (nb_desc > adapter->max_rx_ring_size) {
1219                 PMD_DRV_LOG(ERR,
1220                         "Unsupported size of Rx queue (max size: %d)\n",
1221                         adapter->max_rx_ring_size);
1222                 return -EINVAL;
1223         }
1224
1225         /* ENA isn't supporting buffers smaller than 1400 bytes */
1226         buffer_size = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
1227         if (buffer_size < ENA_RX_BUF_MIN_SIZE) {
1228                 PMD_DRV_LOG(ERR,
1229                         "Unsupported size of Rx buffer: %zu (min size: %d)\n",
1230                         buffer_size, ENA_RX_BUF_MIN_SIZE);
1231                 return -EINVAL;
1232         }
1233
1234         rxq->port_id = dev->data->port_id;
1235         rxq->next_to_clean = 0;
1236         rxq->next_to_use = 0;
1237         rxq->ring_size = nb_desc;
1238         rxq->size_mask = nb_desc - 1;
1239         rxq->numa_socket_id = socket_id;
1240         rxq->mb_pool = mp;
1241
1242         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1243                 sizeof(struct ena_rx_buffer) * nb_desc,
1244                 RTE_CACHE_LINE_SIZE);
1245         if (!rxq->rx_buffer_info) {
1246                 PMD_DRV_LOG(ERR,
1247                         "Failed to allocate memory for Rx buffer info\n");
1248                 return -ENOMEM;
1249         }
1250
1251         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1252                                             sizeof(struct rte_mbuf *) * nb_desc,
1253                                             RTE_CACHE_LINE_SIZE);
1254
1255         if (!rxq->rx_refill_buffer) {
1256                 PMD_DRV_LOG(ERR,
1257                         "Failed to allocate memory for Rx refill buffer\n");
1258                 rte_free(rxq->rx_buffer_info);
1259                 rxq->rx_buffer_info = NULL;
1260                 return -ENOMEM;
1261         }
1262
1263         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1264                                          sizeof(uint16_t) * nb_desc,
1265                                          RTE_CACHE_LINE_SIZE);
1266         if (!rxq->empty_rx_reqs) {
1267                 PMD_DRV_LOG(ERR,
1268                         "Failed to allocate memory for empty Rx requests\n");
1269                 rte_free(rxq->rx_buffer_info);
1270                 rxq->rx_buffer_info = NULL;
1271                 rte_free(rxq->rx_refill_buffer);
1272                 rxq->rx_refill_buffer = NULL;
1273                 return -ENOMEM;
1274         }
1275
1276         for (i = 0; i < nb_desc; i++)
1277                 rxq->empty_rx_reqs[i] = i;
1278
1279         rxq->offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1280
1281         /* Store pointer to this queue in upper layer */
1282         rxq->configured = 1;
1283         dev->data->rx_queues[queue_idx] = rxq;
1284
1285         return 0;
1286 }
1287
1288 static int ena_add_single_rx_desc(struct ena_com_io_sq *io_sq,
1289                                   struct rte_mbuf *mbuf, uint16_t id)
1290 {
1291         struct ena_com_buf ebuf;
1292         int rc;
1293
1294         /* prepare physical address for DMA transaction */
1295         ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1296         ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1297
1298         /* pass resource to device */
1299         rc = ena_com_add_single_rx_desc(io_sq, &ebuf, id);
1300         if (unlikely(rc != 0))
1301                 PMD_RX_LOG(WARNING, "Failed adding Rx desc\n");
1302
1303         return rc;
1304 }
1305
1306 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1307 {
1308         unsigned int i;
1309         int rc;
1310         uint16_t next_to_use = rxq->next_to_use;
1311         uint16_t req_id;
1312 #ifdef RTE_ETHDEV_DEBUG_RX
1313         uint16_t in_use;
1314 #endif
1315         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1316
1317         if (unlikely(!count))
1318                 return 0;
1319
1320 #ifdef RTE_ETHDEV_DEBUG_RX
1321         in_use = rxq->ring_size - 1 -
1322                 ena_com_free_q_entries(rxq->ena_com_io_sq);
1323         if (unlikely((in_use + count) >= rxq->ring_size))
1324                 PMD_RX_LOG(ERR, "Bad Rx ring state\n");
1325 #endif
1326
1327         /* get resources for incoming packets */
1328         rc = rte_pktmbuf_alloc_bulk(rxq->mb_pool, mbufs, count);
1329         if (unlikely(rc < 0)) {
1330                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1331                 ++rxq->rx_stats.mbuf_alloc_fail;
1332                 PMD_RX_LOG(DEBUG, "There are not enough free buffers\n");
1333                 return 0;
1334         }
1335
1336         for (i = 0; i < count; i++) {
1337                 struct rte_mbuf *mbuf = mbufs[i];
1338                 struct ena_rx_buffer *rx_info;
1339
1340                 if (likely((i + 4) < count))
1341                         rte_prefetch0(mbufs[i + 4]);
1342
1343                 req_id = rxq->empty_rx_reqs[next_to_use];
1344                 rx_info = &rxq->rx_buffer_info[req_id];
1345
1346                 rc = ena_add_single_rx_desc(rxq->ena_com_io_sq, mbuf, req_id);
1347                 if (unlikely(rc != 0))
1348                         break;
1349
1350                 rx_info->mbuf = mbuf;
1351                 next_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);
1352         }
1353
1354         if (unlikely(i < count)) {
1355                 PMD_RX_LOG(WARNING,
1356                         "Refilled Rx queue[%d] with only %d/%d buffers\n",
1357                         rxq->id, i, count);
1358                 rte_pktmbuf_free_bulk(&mbufs[i], count - i);
1359                 ++rxq->rx_stats.refill_partial;
1360         }
1361
1362         /* When we submitted free recources to device... */
1363         if (likely(i > 0)) {
1364                 /* ...let HW know that it can fill buffers with data. */
1365                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1366
1367                 rxq->next_to_use = next_to_use;
1368         }
1369
1370         return i;
1371 }
1372
1373 static int ena_device_init(struct ena_com_dev *ena_dev,
1374                            struct rte_pci_device *pdev,
1375                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1376                            bool *wd_state)
1377 {
1378         uint32_t aenq_groups;
1379         int rc;
1380         bool readless_supported;
1381
1382         /* Initialize mmio registers */
1383         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1384         if (rc) {
1385                 PMD_DRV_LOG(ERR, "Failed to init MMIO read less\n");
1386                 return rc;
1387         }
1388
1389         /* The PCIe configuration space revision id indicate if mmio reg
1390          * read is disabled.
1391          */
1392         readless_supported = !(pdev->id.class_id & ENA_MMIO_DISABLE_REG_READ);
1393         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1394
1395         /* reset device */
1396         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1397         if (rc) {
1398                 PMD_DRV_LOG(ERR, "Cannot reset device\n");
1399                 goto err_mmio_read_less;
1400         }
1401
1402         /* check FW version */
1403         rc = ena_com_validate_version(ena_dev);
1404         if (rc) {
1405                 PMD_DRV_LOG(ERR, "Device version is too low\n");
1406                 goto err_mmio_read_less;
1407         }
1408
1409         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1410
1411         /* ENA device administration layer init */
1412         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1413         if (rc) {
1414                 PMD_DRV_LOG(ERR,
1415                         "Cannot initialize ENA admin queue\n");
1416                 goto err_mmio_read_less;
1417         }
1418
1419         /* To enable the msix interrupts the driver needs to know the number
1420          * of queues. So the driver uses polling mode to retrieve this
1421          * information.
1422          */
1423         ena_com_set_admin_polling_mode(ena_dev, true);
1424
1425         ena_config_host_info(ena_dev);
1426
1427         /* Get Device Attributes and features */
1428         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1429         if (rc) {
1430                 PMD_DRV_LOG(ERR,
1431                         "Cannot get attribute for ENA device, rc: %d\n", rc);
1432                 goto err_admin_init;
1433         }
1434
1435         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1436                       BIT(ENA_ADMIN_NOTIFICATION) |
1437                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1438                       BIT(ENA_ADMIN_FATAL_ERROR) |
1439                       BIT(ENA_ADMIN_WARNING);
1440
1441         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1442         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1443         if (rc) {
1444                 PMD_DRV_LOG(ERR, "Cannot configure AENQ groups, rc: %d\n", rc);
1445                 goto err_admin_init;
1446         }
1447
1448         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1449
1450         return 0;
1451
1452 err_admin_init:
1453         ena_com_admin_destroy(ena_dev);
1454
1455 err_mmio_read_less:
1456         ena_com_mmio_reg_read_request_destroy(ena_dev);
1457
1458         return rc;
1459 }
1460
1461 static void ena_interrupt_handler_rte(void *cb_arg)
1462 {
1463         struct rte_eth_dev *dev = cb_arg;
1464         struct ena_adapter *adapter = dev->data->dev_private;
1465         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1466
1467         ena_com_admin_q_comp_intr_handler(ena_dev);
1468         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1469                 ena_com_aenq_intr_handler(ena_dev, dev);
1470 }
1471
1472 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1473 {
1474         if (!adapter->wd_state)
1475                 return;
1476
1477         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1478                 return;
1479
1480         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1481             adapter->keep_alive_timeout)) {
1482                 PMD_DRV_LOG(ERR, "Keep alive timeout\n");
1483                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1484                 adapter->trigger_reset = true;
1485                 ++adapter->dev_stats.wd_expired;
1486         }
1487 }
1488
1489 /* Check if admin queue is enabled */
1490 static void check_for_admin_com_state(struct ena_adapter *adapter)
1491 {
1492         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1493                 PMD_DRV_LOG(ERR, "ENA admin queue is not in running state\n");
1494                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1495                 adapter->trigger_reset = true;
1496         }
1497 }
1498
1499 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1500                                   void *arg)
1501 {
1502         struct rte_eth_dev *dev = arg;
1503         struct ena_adapter *adapter = dev->data->dev_private;
1504
1505         check_for_missing_keep_alive(adapter);
1506         check_for_admin_com_state(adapter);
1507
1508         if (unlikely(adapter->trigger_reset)) {
1509                 PMD_DRV_LOG(ERR, "Trigger reset is on\n");
1510                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1511                         NULL);
1512         }
1513 }
1514
1515 static inline void
1516 set_default_llq_configurations(struct ena_llq_configurations *llq_config,
1517                                struct ena_admin_feature_llq_desc *llq,
1518                                bool use_large_llq_hdr)
1519 {
1520         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1521         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1522         llq_config->llq_num_decs_before_header =
1523                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1524
1525         if (use_large_llq_hdr &&
1526             (llq->entry_size_ctrl_supported & ENA_ADMIN_LIST_ENTRY_SIZE_256B)) {
1527                 llq_config->llq_ring_entry_size =
1528                         ENA_ADMIN_LIST_ENTRY_SIZE_256B;
1529                 llq_config->llq_ring_entry_size_value = 256;
1530         } else {
1531                 llq_config->llq_ring_entry_size =
1532                         ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1533                 llq_config->llq_ring_entry_size_value = 128;
1534         }
1535 }
1536
1537 static int
1538 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1539                                 struct ena_com_dev *ena_dev,
1540                                 struct ena_admin_feature_llq_desc *llq,
1541                                 struct ena_llq_configurations *llq_default_configurations)
1542 {
1543         int rc;
1544         u32 llq_feature_mask;
1545
1546         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1547         if (!(ena_dev->supported_features & llq_feature_mask)) {
1548                 PMD_DRV_LOG(INFO,
1549                         "LLQ is not supported. Fallback to host mode policy.\n");
1550                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1551                 return 0;
1552         }
1553
1554         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1555         if (unlikely(rc)) {
1556                 PMD_INIT_LOG(WARNING,
1557                         "Failed to config dev mode. Fallback to host mode policy.\n");
1558                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1559                 return 0;
1560         }
1561
1562         /* Nothing to config, exit */
1563         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1564                 return 0;
1565
1566         if (!adapter->dev_mem_base) {
1567                 PMD_DRV_LOG(ERR,
1568                         "Unable to access LLQ BAR resource. Fallback to host mode policy.\n");
1569                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1570                 return 0;
1571         }
1572
1573         ena_dev->mem_bar = adapter->dev_mem_base;
1574
1575         return 0;
1576 }
1577
1578 static uint32_t ena_calc_max_io_queue_num(struct ena_com_dev *ena_dev,
1579         struct ena_com_dev_get_features_ctx *get_feat_ctx)
1580 {
1581         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, max_num_io_queues;
1582
1583         /* Regular queues capabilities */
1584         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1585                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1586                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1587                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1588                                     max_queue_ext->max_rx_cq_num);
1589                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1590                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1591         } else {
1592                 struct ena_admin_queue_feature_desc *max_queues =
1593                         &get_feat_ctx->max_queues;
1594                 io_tx_sq_num = max_queues->max_sq_num;
1595                 io_tx_cq_num = max_queues->max_cq_num;
1596                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1597         }
1598
1599         /* In case of LLQ use the llq number in the get feature cmd */
1600         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1601                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1602
1603         max_num_io_queues = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num);
1604         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_sq_num);
1605         max_num_io_queues = RTE_MIN(max_num_io_queues, io_tx_cq_num);
1606
1607         if (unlikely(max_num_io_queues == 0)) {
1608                 PMD_DRV_LOG(ERR, "Number of IO queues cannot not be 0\n");
1609                 return -EFAULT;
1610         }
1611
1612         return max_num_io_queues;
1613 }
1614
1615 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1616 {
1617         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1618         struct rte_pci_device *pci_dev;
1619         struct rte_intr_handle *intr_handle;
1620         struct ena_adapter *adapter = eth_dev->data->dev_private;
1621         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1622         struct ena_com_dev_get_features_ctx get_feat_ctx;
1623         struct ena_llq_configurations llq_config;
1624         const char *queue_type_str;
1625         uint32_t max_num_io_queues;
1626         int rc;
1627         static int adapters_found;
1628         bool disable_meta_caching;
1629         bool wd_state = false;
1630
1631         eth_dev->dev_ops = &ena_dev_ops;
1632         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1633         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1634         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1635
1636         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1637                 return 0;
1638
1639         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1640
1641         memset(adapter, 0, sizeof(struct ena_adapter));
1642         ena_dev = &adapter->ena_dev;
1643
1644         adapter->edev_data = eth_dev->data;
1645
1646         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1647
1648         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1649                      pci_dev->addr.domain,
1650                      pci_dev->addr.bus,
1651                      pci_dev->addr.devid,
1652                      pci_dev->addr.function);
1653
1654         intr_handle = &pci_dev->intr_handle;
1655
1656         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1657         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1658
1659         if (!adapter->regs) {
1660                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1661                              ENA_REGS_BAR);
1662                 return -ENXIO;
1663         }
1664
1665         ena_dev->reg_bar = adapter->regs;
1666         /* This is a dummy pointer for ena_com functions. */
1667         ena_dev->dmadev = adapter;
1668
1669         adapter->id_number = adapters_found;
1670
1671         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1672                  adapter->id_number);
1673
1674         rc = ena_parse_devargs(adapter, pci_dev->device.devargs);
1675         if (rc != 0) {
1676                 PMD_INIT_LOG(CRIT, "Failed to parse devargs\n");
1677                 goto err;
1678         }
1679
1680         /* device specific initialization routine */
1681         rc = ena_device_init(ena_dev, pci_dev, &get_feat_ctx, &wd_state);
1682         if (rc) {
1683                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1684                 goto err;
1685         }
1686         adapter->wd_state = wd_state;
1687
1688         set_default_llq_configurations(&llq_config, &get_feat_ctx.llq,
1689                 adapter->use_large_llq_hdr);
1690         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1691                                              &get_feat_ctx.llq, &llq_config);
1692         if (unlikely(rc)) {
1693                 PMD_INIT_LOG(CRIT, "Failed to set placement policy\n");
1694                 return rc;
1695         }
1696
1697         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1698                 queue_type_str = "Regular";
1699         else
1700                 queue_type_str = "Low latency";
1701         PMD_DRV_LOG(INFO, "Placement policy: %s\n", queue_type_str);
1702
1703         calc_queue_ctx.ena_dev = ena_dev;
1704         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1705
1706         max_num_io_queues = ena_calc_max_io_queue_num(ena_dev, &get_feat_ctx);
1707         rc = ena_calc_io_queue_size(&calc_queue_ctx,
1708                 adapter->use_large_llq_hdr);
1709         if (unlikely((rc != 0) || (max_num_io_queues == 0))) {
1710                 rc = -EFAULT;
1711                 goto err_device_destroy;
1712         }
1713
1714         adapter->max_tx_ring_size = calc_queue_ctx.max_tx_queue_size;
1715         adapter->max_rx_ring_size = calc_queue_ctx.max_rx_queue_size;
1716         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1717         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1718         adapter->max_num_io_queues = max_num_io_queues;
1719
1720         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1721                 disable_meta_caching =
1722                         !!(get_feat_ctx.llq.accel_mode.u.get.supported_flags &
1723                         BIT(ENA_ADMIN_DISABLE_META_CACHING));
1724         } else {
1725                 disable_meta_caching = false;
1726         }
1727
1728         /* prepare ring structures */
1729         ena_init_rings(adapter, disable_meta_caching);
1730
1731         ena_config_debug_area(adapter);
1732
1733         /* Set max MTU for this device */
1734         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1735
1736         /* set device support for offloads */
1737         adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx &
1738                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0;
1739         adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx &
1740                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0;
1741         adapter->offloads.rx_csum_supported =
1742                 (get_feat_ctx.offload.rx_supported &
1743                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0;
1744         adapter->offloads.rss_hash_supported =
1745                 (get_feat_ctx.offload.rx_supported &
1746                 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) != 0;
1747
1748         /* Copy MAC address and point DPDK to it */
1749         eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr;
1750         rte_ether_addr_copy((struct rte_ether_addr *)
1751                         get_feat_ctx.dev_attr.mac_addr,
1752                         (struct rte_ether_addr *)adapter->mac_addr);
1753
1754         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
1755         if (unlikely(rc != 0)) {
1756                 PMD_DRV_LOG(ERR, "Failed to initialize RSS in ENA device\n");
1757                 goto err_delete_debug_area;
1758         }
1759
1760         adapter->drv_stats = rte_zmalloc("adapter stats",
1761                                          sizeof(*adapter->drv_stats),
1762                                          RTE_CACHE_LINE_SIZE);
1763         if (!adapter->drv_stats) {
1764                 PMD_DRV_LOG(ERR,
1765                         "Failed to allocate memory for adapter statistics\n");
1766                 rc = -ENOMEM;
1767                 goto err_rss_destroy;
1768         }
1769
1770         rte_spinlock_init(&adapter->admin_lock);
1771
1772         rte_intr_callback_register(intr_handle,
1773                                    ena_interrupt_handler_rte,
1774                                    eth_dev);
1775         rte_intr_enable(intr_handle);
1776         ena_com_set_admin_polling_mode(ena_dev, false);
1777         ena_com_admin_aenq_enable(ena_dev);
1778
1779         if (adapters_found == 0)
1780                 rte_timer_subsystem_init();
1781         rte_timer_init(&adapter->timer_wd);
1782
1783         adapters_found++;
1784         adapter->state = ENA_ADAPTER_STATE_INIT;
1785
1786         return 0;
1787
1788 err_rss_destroy:
1789         ena_com_rss_destroy(ena_dev);
1790 err_delete_debug_area:
1791         ena_com_delete_debug_area(ena_dev);
1792
1793 err_device_destroy:
1794         ena_com_delete_host_info(ena_dev);
1795         ena_com_admin_destroy(ena_dev);
1796
1797 err:
1798         return rc;
1799 }
1800
1801 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1802 {
1803         struct ena_adapter *adapter = eth_dev->data->dev_private;
1804         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1805
1806         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1807                 return;
1808
1809         ena_com_set_admin_running_state(ena_dev, false);
1810
1811         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1812                 ena_close(eth_dev);
1813
1814         ena_com_rss_destroy(ena_dev);
1815
1816         ena_com_delete_debug_area(ena_dev);
1817         ena_com_delete_host_info(ena_dev);
1818
1819         ena_com_abort_admin_commands(ena_dev);
1820         ena_com_wait_for_abort_completion(ena_dev);
1821         ena_com_admin_destroy(ena_dev);
1822         ena_com_mmio_reg_read_request_destroy(ena_dev);
1823
1824         adapter->state = ENA_ADAPTER_STATE_FREE;
1825 }
1826
1827 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1828 {
1829         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1830                 return 0;
1831
1832         ena_destroy_device(eth_dev);
1833
1834         return 0;
1835 }
1836
1837 static int ena_dev_configure(struct rte_eth_dev *dev)
1838 {
1839         struct ena_adapter *adapter = dev->data->dev_private;
1840
1841         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1842
1843         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1844                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1845         dev->data->dev_conf.txmode.offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
1846
1847         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1848         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1849         return 0;
1850 }
1851
1852 static void ena_init_rings(struct ena_adapter *adapter,
1853                            bool disable_meta_caching)
1854 {
1855         size_t i;
1856
1857         for (i = 0; i < adapter->max_num_io_queues; i++) {
1858                 struct ena_ring *ring = &adapter->tx_ring[i];
1859
1860                 ring->configured = 0;
1861                 ring->type = ENA_RING_TYPE_TX;
1862                 ring->adapter = adapter;
1863                 ring->id = i;
1864                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1865                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1866                 ring->sgl_size = adapter->max_tx_sgl_size;
1867                 ring->disable_meta_caching = disable_meta_caching;
1868         }
1869
1870         for (i = 0; i < adapter->max_num_io_queues; i++) {
1871                 struct ena_ring *ring = &adapter->rx_ring[i];
1872
1873                 ring->configured = 0;
1874                 ring->type = ENA_RING_TYPE_RX;
1875                 ring->adapter = adapter;
1876                 ring->id = i;
1877                 ring->sgl_size = adapter->max_rx_sgl_size;
1878         }
1879 }
1880
1881 static int ena_infos_get(struct rte_eth_dev *dev,
1882                           struct rte_eth_dev_info *dev_info)
1883 {
1884         struct ena_adapter *adapter;
1885         struct ena_com_dev *ena_dev;
1886         uint64_t rx_feat = 0, tx_feat = 0;
1887
1888         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1889         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1890         adapter = dev->data->dev_private;
1891
1892         ena_dev = &adapter->ena_dev;
1893         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1894
1895         dev_info->speed_capa =
1896                         ETH_LINK_SPEED_1G   |
1897                         ETH_LINK_SPEED_2_5G |
1898                         ETH_LINK_SPEED_5G   |
1899                         ETH_LINK_SPEED_10G  |
1900                         ETH_LINK_SPEED_25G  |
1901                         ETH_LINK_SPEED_40G  |
1902                         ETH_LINK_SPEED_50G  |
1903                         ETH_LINK_SPEED_100G;
1904
1905         /* Set Tx & Rx features available for device */
1906         if (adapter->offloads.tso4_supported)
1907                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1908
1909         if (adapter->offloads.tx_csum_supported)
1910                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1911                         DEV_TX_OFFLOAD_UDP_CKSUM |
1912                         DEV_TX_OFFLOAD_TCP_CKSUM;
1913
1914         if (adapter->offloads.rx_csum_supported)
1915                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1916                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1917                         DEV_RX_OFFLOAD_TCP_CKSUM;
1918
1919         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1920         tx_feat |= DEV_TX_OFFLOAD_MULTI_SEGS;
1921
1922         /* Inform framework about available features */
1923         dev_info->rx_offload_capa = rx_feat;
1924         if (adapter->offloads.rss_hash_supported)
1925                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_RSS_HASH;
1926         dev_info->rx_queue_offload_capa = rx_feat;
1927         dev_info->tx_offload_capa = tx_feat;
1928         dev_info->tx_queue_offload_capa = tx_feat;
1929
1930         dev_info->flow_type_rss_offloads = ENA_ALL_RSS_HF;
1931         dev_info->hash_key_size = ENA_HASH_KEY_SIZE;
1932
1933         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1934         dev_info->max_rx_pktlen  = adapter->max_mtu + RTE_ETHER_HDR_LEN +
1935                 RTE_ETHER_CRC_LEN;
1936         dev_info->min_mtu = ENA_MIN_MTU;
1937         dev_info->max_mtu = adapter->max_mtu;
1938         dev_info->max_mac_addrs = 1;
1939
1940         dev_info->max_rx_queues = adapter->max_num_io_queues;
1941         dev_info->max_tx_queues = adapter->max_num_io_queues;
1942         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1943
1944         adapter->tx_supported_offloads = tx_feat;
1945         adapter->rx_supported_offloads = rx_feat;
1946
1947         dev_info->rx_desc_lim.nb_max = adapter->max_rx_ring_size;
1948         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1949         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1950                                         adapter->max_rx_sgl_size);
1951         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1952                                         adapter->max_rx_sgl_size);
1953
1954         dev_info->tx_desc_lim.nb_max = adapter->max_tx_ring_size;
1955         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1956         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1957                                         adapter->max_tx_sgl_size);
1958         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1959                                         adapter->max_tx_sgl_size);
1960
1961         dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE;
1962         dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE;
1963
1964         return 0;
1965 }
1966
1967 static inline void ena_init_rx_mbuf(struct rte_mbuf *mbuf, uint16_t len)
1968 {
1969         mbuf->data_len = len;
1970         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1971         mbuf->refcnt = 1;
1972         mbuf->next = NULL;
1973 }
1974
1975 static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,
1976                                     struct ena_com_rx_buf_info *ena_bufs,
1977                                     uint32_t descs,
1978                                     uint16_t *next_to_clean,
1979                                     uint8_t offset)
1980 {
1981         struct rte_mbuf *mbuf;
1982         struct rte_mbuf *mbuf_head;
1983         struct ena_rx_buffer *rx_info;
1984         int rc;
1985         uint16_t ntc, len, req_id, buf = 0;
1986
1987         if (unlikely(descs == 0))
1988                 return NULL;
1989
1990         ntc = *next_to_clean;
1991
1992         len = ena_bufs[buf].len;
1993         req_id = ena_bufs[buf].req_id;
1994
1995         rx_info = &rx_ring->rx_buffer_info[req_id];
1996
1997         mbuf = rx_info->mbuf;
1998         RTE_ASSERT(mbuf != NULL);
1999
2000         ena_init_rx_mbuf(mbuf, len);
2001
2002         /* Fill the mbuf head with the data specific for 1st segment. */
2003         mbuf_head = mbuf;
2004         mbuf_head->nb_segs = descs;
2005         mbuf_head->port = rx_ring->port_id;
2006         mbuf_head->pkt_len = len;
2007         mbuf_head->data_off += offset;
2008
2009         rx_info->mbuf = NULL;
2010         rx_ring->empty_rx_reqs[ntc] = req_id;
2011         ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2012
2013         while (--descs) {
2014                 ++buf;
2015                 len = ena_bufs[buf].len;
2016                 req_id = ena_bufs[buf].req_id;
2017
2018                 rx_info = &rx_ring->rx_buffer_info[req_id];
2019                 RTE_ASSERT(rx_info->mbuf != NULL);
2020
2021                 if (unlikely(len == 0)) {
2022                         /*
2023                          * Some devices can pass descriptor with the length 0.
2024                          * To avoid confusion, the PMD is simply putting the
2025                          * descriptor back, as it was never used. We'll avoid
2026                          * mbuf allocation that way.
2027                          */
2028                         rc = ena_add_single_rx_desc(rx_ring->ena_com_io_sq,
2029                                 rx_info->mbuf, req_id);
2030                         if (unlikely(rc != 0)) {
2031                                 /* Free the mbuf in case of an error. */
2032                                 rte_mbuf_raw_free(rx_info->mbuf);
2033                         } else {
2034                                 /*
2035                                  * If there was no error, just exit the loop as
2036                                  * 0 length descriptor is always the last one.
2037                                  */
2038                                 break;
2039                         }
2040                 } else {
2041                         /* Create an mbuf chain. */
2042                         mbuf->next = rx_info->mbuf;
2043                         mbuf = mbuf->next;
2044
2045                         ena_init_rx_mbuf(mbuf, len);
2046                         mbuf_head->pkt_len += len;
2047                 }
2048
2049                 /*
2050                  * Mark the descriptor as depleted and perform necessary
2051                  * cleanup.
2052                  * This code will execute in two cases:
2053                  *  1. Descriptor len was greater than 0 - normal situation.
2054                  *  2. Descriptor len was 0 and we failed to add the descriptor
2055                  *     to the device. In that situation, we should try to add
2056                  *     the mbuf again in the populate routine and mark the
2057                  *     descriptor as used up by the device.
2058                  */
2059                 rx_info->mbuf = NULL;
2060                 rx_ring->empty_rx_reqs[ntc] = req_id;
2061                 ntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);
2062         }
2063
2064         *next_to_clean = ntc;
2065
2066         return mbuf_head;
2067 }
2068
2069 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2070                                   uint16_t nb_pkts)
2071 {
2072         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2073         unsigned int free_queue_entries;
2074         unsigned int refill_threshold;
2075         uint16_t next_to_clean = rx_ring->next_to_clean;
2076         uint16_t descs_in_use;
2077         struct rte_mbuf *mbuf;
2078         uint16_t completed;
2079         struct ena_com_rx_ctx ena_rx_ctx;
2080         int i, rc = 0;
2081         bool fill_hash;
2082
2083 #ifdef RTE_ETHDEV_DEBUG_RX
2084         /* Check adapter state */
2085         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2086                 PMD_RX_LOG(ALERT,
2087                         "Trying to receive pkts while device is NOT running\n");
2088                 return 0;
2089         }
2090 #endif
2091
2092         fill_hash = rx_ring->offloads & DEV_RX_OFFLOAD_RSS_HASH;
2093
2094         descs_in_use = rx_ring->ring_size -
2095                 ena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;
2096         nb_pkts = RTE_MIN(descs_in_use, nb_pkts);
2097
2098         for (completed = 0; completed < nb_pkts; completed++) {
2099                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2100                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2101                 ena_rx_ctx.descs = 0;
2102                 ena_rx_ctx.pkt_offset = 0;
2103                 /* receive packet context */
2104                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2105                                     rx_ring->ena_com_io_sq,
2106                                     &ena_rx_ctx);
2107                 if (unlikely(rc)) {
2108                         PMD_RX_LOG(ERR,
2109                                 "Failed to get the packet from the device, rc: %d\n",
2110                                 rc);
2111                         if (rc == ENA_COM_NO_SPACE) {
2112                                 ++rx_ring->rx_stats.bad_desc_num;
2113                                 rx_ring->adapter->reset_reason =
2114                                         ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2115                         } else {
2116                                 ++rx_ring->rx_stats.bad_req_id;
2117                                 rx_ring->adapter->reset_reason =
2118                                         ENA_REGS_RESET_INV_RX_REQ_ID;
2119                         }
2120                         rx_ring->adapter->trigger_reset = true;
2121                         return 0;
2122                 }
2123
2124                 mbuf = ena_rx_mbuf(rx_ring,
2125                         ena_rx_ctx.ena_bufs,
2126                         ena_rx_ctx.descs,
2127                         &next_to_clean,
2128                         ena_rx_ctx.pkt_offset);
2129                 if (unlikely(mbuf == NULL)) {
2130                         for (i = 0; i < ena_rx_ctx.descs; ++i) {
2131                                 rx_ring->empty_rx_reqs[next_to_clean] =
2132                                         rx_ring->ena_bufs[i].req_id;
2133                                 next_to_clean = ENA_IDX_NEXT_MASKED(
2134                                         next_to_clean, rx_ring->size_mask);
2135                         }
2136                         break;
2137                 }
2138
2139                 /* fill mbuf attributes if any */
2140                 ena_rx_mbuf_prepare(mbuf, &ena_rx_ctx, fill_hash);
2141
2142                 if (unlikely(mbuf->ol_flags &
2143                                 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) {
2144                         rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors);
2145                         ++rx_ring->rx_stats.bad_csum;
2146                 }
2147
2148                 rx_pkts[completed] = mbuf;
2149                 rx_ring->rx_stats.bytes += mbuf->pkt_len;
2150         }
2151
2152         rx_ring->rx_stats.cnt += completed;
2153         rx_ring->next_to_clean = next_to_clean;
2154
2155         free_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);
2156         refill_threshold =
2157                 RTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2158                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2159
2160         /* Burst refill to save doorbells, memory barriers, const interval */
2161         if (free_queue_entries > refill_threshold) {
2162                 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
2163                 ena_populate_rx_queue(rx_ring, free_queue_entries);
2164         }
2165
2166         return completed;
2167 }
2168
2169 static uint16_t
2170 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2171                 uint16_t nb_pkts)
2172 {
2173         int32_t ret;
2174         uint32_t i;
2175         struct rte_mbuf *m;
2176         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2177         struct rte_ipv4_hdr *ip_hdr;
2178         uint64_t ol_flags;
2179         uint16_t frag_field;
2180
2181         for (i = 0; i != nb_pkts; i++) {
2182                 m = tx_pkts[i];
2183                 ol_flags = m->ol_flags;
2184
2185                 if (!(ol_flags & PKT_TX_IPV4))
2186                         continue;
2187
2188                 /* If there was not L2 header length specified, assume it is
2189                  * length of the ethernet header.
2190                  */
2191                 if (unlikely(m->l2_len == 0))
2192                         m->l2_len = sizeof(struct rte_ether_hdr);
2193
2194                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
2195                                                  m->l2_len);
2196                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2197
2198                 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) {
2199                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2200
2201                         /* If IPv4 header has DF flag enabled and TSO support is
2202                          * disabled, partial chcecksum should not be calculated.
2203                          */
2204                         if (!tx_ring->adapter->offloads.tso4_supported)
2205                                 continue;
2206                 }
2207
2208                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2209                                 (ol_flags & PKT_TX_L4_MASK) ==
2210                                 PKT_TX_SCTP_CKSUM) {
2211                         rte_errno = ENOTSUP;
2212                         return i;
2213                 }
2214
2215 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2216                 ret = rte_validate_tx_offload(m);
2217                 if (ret != 0) {
2218                         rte_errno = -ret;
2219                         return i;
2220                 }
2221 #endif
2222
2223                 /* In case we are supposed to TSO and have DF not set (DF=0)
2224                  * hardware must be provided with partial checksum, otherwise
2225                  * it will take care of necessary calculations.
2226                  */
2227
2228                 ret = rte_net_intel_cksum_flags_prepare(m,
2229                         ol_flags & ~PKT_TX_TCP_SEG);
2230                 if (ret != 0) {
2231                         rte_errno = -ret;
2232                         return i;
2233                 }
2234         }
2235
2236         return i;
2237 }
2238
2239 static void ena_update_hints(struct ena_adapter *adapter,
2240                              struct ena_admin_ena_hw_hints *hints)
2241 {
2242         if (hints->admin_completion_tx_timeout)
2243                 adapter->ena_dev.admin_queue.completion_timeout =
2244                         hints->admin_completion_tx_timeout * 1000;
2245
2246         if (hints->mmio_read_timeout)
2247                 /* convert to usec */
2248                 adapter->ena_dev.mmio_read.reg_read_to =
2249                         hints->mmio_read_timeout * 1000;
2250
2251         if (hints->driver_watchdog_timeout) {
2252                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2253                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2254                 else
2255                         // Convert msecs to ticks
2256                         adapter->keep_alive_timeout =
2257                                 (hints->driver_watchdog_timeout *
2258                                 rte_get_timer_hz()) / 1000;
2259         }
2260 }
2261
2262 static int ena_check_space_and_linearize_mbuf(struct ena_ring *tx_ring,
2263                                               struct rte_mbuf *mbuf)
2264 {
2265         struct ena_com_dev *ena_dev;
2266         int num_segments, header_len, rc;
2267
2268         ena_dev = &tx_ring->adapter->ena_dev;
2269         num_segments = mbuf->nb_segs;
2270         header_len = mbuf->data_len;
2271
2272         if (likely(num_segments < tx_ring->sgl_size))
2273                 goto checkspace;
2274
2275         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2276             (num_segments == tx_ring->sgl_size) &&
2277             (header_len < tx_ring->tx_max_header_size))
2278                 goto checkspace;
2279
2280         /* Checking for space for 2 additional metadata descriptors due to
2281          * possible header split and metadata descriptor. Linearization will
2282          * be needed so we reduce the segments number from num_segments to 1
2283          */
2284         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 3)) {
2285                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2286                 return ENA_COM_NO_MEM;
2287         }
2288         ++tx_ring->tx_stats.linearize;
2289         rc = rte_pktmbuf_linearize(mbuf);
2290         if (unlikely(rc)) {
2291                 PMD_TX_LOG(WARNING, "Mbuf linearize failed\n");
2292                 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2293                 ++tx_ring->tx_stats.linearize_failed;
2294                 return rc;
2295         }
2296
2297         return 0;
2298
2299 checkspace:
2300         /* Checking for space for 2 additional metadata descriptors due to
2301          * possible header split and metadata descriptor
2302          */
2303         if (!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq,
2304                                           num_segments + 2)) {
2305                 PMD_TX_LOG(DEBUG, "Not enough space in the Tx queue\n");
2306                 return ENA_COM_NO_MEM;
2307         }
2308
2309         return 0;
2310 }
2311
2312 static void ena_tx_map_mbuf(struct ena_ring *tx_ring,
2313         struct ena_tx_buffer *tx_info,
2314         struct rte_mbuf *mbuf,
2315         void **push_header,
2316         uint16_t *header_len)
2317 {
2318         struct ena_com_buf *ena_buf;
2319         uint16_t delta, seg_len, push_len;
2320
2321         delta = 0;
2322         seg_len = mbuf->data_len;
2323
2324         tx_info->mbuf = mbuf;
2325         ena_buf = tx_info->bufs;
2326
2327         if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2328                 /*
2329                  * Tx header might be (and will be in most cases) smaller than
2330                  * tx_max_header_size. But it's not an issue to send more data
2331                  * to the device, than actually needed if the mbuf size is
2332                  * greater than tx_max_header_size.
2333                  */
2334                 push_len = RTE_MIN(mbuf->pkt_len, tx_ring->tx_max_header_size);
2335                 *header_len = push_len;
2336
2337                 if (likely(push_len <= seg_len)) {
2338                         /* If the push header is in the single segment, then
2339                          * just point it to the 1st mbuf data.
2340                          */
2341                         *push_header = rte_pktmbuf_mtod(mbuf, uint8_t *);
2342                 } else {
2343                         /* If the push header lays in the several segments, copy
2344                          * it to the intermediate buffer.
2345                          */
2346                         rte_pktmbuf_read(mbuf, 0, push_len,
2347                                 tx_ring->push_buf_intermediate_buf);
2348                         *push_header = tx_ring->push_buf_intermediate_buf;
2349                         delta = push_len - seg_len;
2350                 }
2351         } else {
2352                 *push_header = NULL;
2353                 *header_len = 0;
2354                 push_len = 0;
2355         }
2356
2357         /* Process first segment taking into consideration pushed header */
2358         if (seg_len > push_len) {
2359                 ena_buf->paddr = mbuf->buf_iova +
2360                                 mbuf->data_off +
2361                                 push_len;
2362                 ena_buf->len = seg_len - push_len;
2363                 ena_buf++;
2364                 tx_info->num_of_bufs++;
2365         }
2366
2367         while ((mbuf = mbuf->next) != NULL) {
2368                 seg_len = mbuf->data_len;
2369
2370                 /* Skip mbufs if whole data is pushed as a header */
2371                 if (unlikely(delta > seg_len)) {
2372                         delta -= seg_len;
2373                         continue;
2374                 }
2375
2376                 ena_buf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2377                 ena_buf->len = seg_len - delta;
2378                 ena_buf++;
2379                 tx_info->num_of_bufs++;
2380
2381                 delta = 0;
2382         }
2383 }
2384
2385 static int ena_xmit_mbuf(struct ena_ring *tx_ring, struct rte_mbuf *mbuf)
2386 {
2387         struct ena_tx_buffer *tx_info;
2388         struct ena_com_tx_ctx ena_tx_ctx = { { 0 } };
2389         uint16_t next_to_use;
2390         uint16_t header_len;
2391         uint16_t req_id;
2392         void *push_header;
2393         int nb_hw_desc;
2394         int rc;
2395
2396         rc = ena_check_space_and_linearize_mbuf(tx_ring, mbuf);
2397         if (unlikely(rc))
2398                 return rc;
2399
2400         next_to_use = tx_ring->next_to_use;
2401
2402         req_id = tx_ring->empty_tx_reqs[next_to_use];
2403         tx_info = &tx_ring->tx_buffer_info[req_id];
2404         tx_info->num_of_bufs = 0;
2405
2406         ena_tx_map_mbuf(tx_ring, tx_info, mbuf, &push_header, &header_len);
2407
2408         ena_tx_ctx.ena_bufs = tx_info->bufs;
2409         ena_tx_ctx.push_header = push_header;
2410         ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2411         ena_tx_ctx.req_id = req_id;
2412         ena_tx_ctx.header_len = header_len;
2413
2414         /* Set Tx offloads flags, if applicable */
2415         ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,
2416                 tx_ring->disable_meta_caching);
2417
2418         if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2419                         &ena_tx_ctx))) {
2420                 PMD_TX_LOG(DEBUG,
2421                         "LLQ Tx max burst size of queue %d achieved, writing doorbell to send burst\n",
2422                         tx_ring->id);
2423                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2424                 tx_ring->tx_stats.doorbells++;
2425                 tx_ring->pkts_without_db = false;
2426         }
2427
2428         /* prepare the packet's descriptors to dma engine */
2429         rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
2430                 &nb_hw_desc);
2431         if (unlikely(rc)) {
2432                 PMD_DRV_LOG(ERR, "Failed to prepare Tx buffers, rc: %d\n", rc);
2433                 ++tx_ring->tx_stats.prepare_ctx_err;
2434                 tx_ring->adapter->reset_reason =
2435                     ENA_REGS_RESET_DRIVER_INVALID_STATE;
2436                 tx_ring->adapter->trigger_reset = true;
2437                 return rc;
2438         }
2439
2440         tx_info->tx_descs = nb_hw_desc;
2441
2442         tx_ring->tx_stats.cnt++;
2443         tx_ring->tx_stats.bytes += mbuf->pkt_len;
2444
2445         tx_ring->next_to_use = ENA_IDX_NEXT_MASKED(next_to_use,
2446                 tx_ring->size_mask);
2447
2448         return 0;
2449 }
2450
2451 static void ena_tx_cleanup(struct ena_ring *tx_ring)
2452 {
2453         unsigned int cleanup_budget;
2454         unsigned int total_tx_descs = 0;
2455         uint16_t next_to_clean = tx_ring->next_to_clean;
2456
2457         cleanup_budget = RTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,
2458                 (unsigned int)ENA_REFILL_THRESH_PACKET);
2459
2460         while (likely(total_tx_descs < cleanup_budget)) {
2461                 struct rte_mbuf *mbuf;
2462                 struct ena_tx_buffer *tx_info;
2463                 uint16_t req_id;
2464
2465                 if (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) != 0)
2466                         break;
2467
2468                 if (unlikely(validate_tx_req_id(tx_ring, req_id) != 0))
2469                         break;
2470
2471                 /* Get Tx info & store how many descs were processed  */
2472                 tx_info = &tx_ring->tx_buffer_info[req_id];
2473
2474                 mbuf = tx_info->mbuf;
2475                 rte_pktmbuf_free(mbuf);
2476
2477                 tx_info->mbuf = NULL;
2478                 tx_ring->empty_tx_reqs[next_to_clean] = req_id;
2479
2480                 total_tx_descs += tx_info->tx_descs;
2481
2482                 /* Put back descriptor to the ring for reuse */
2483                 next_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,
2484                         tx_ring->size_mask);
2485         }
2486
2487         if (likely(total_tx_descs > 0)) {
2488                 /* acknowledge completion of sent packets */
2489                 tx_ring->next_to_clean = next_to_clean;
2490                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2491                 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
2492         }
2493 }
2494
2495 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2496                                   uint16_t nb_pkts)
2497 {
2498         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2499         uint16_t sent_idx = 0;
2500
2501 #ifdef RTE_ETHDEV_DEBUG_TX
2502         /* Check adapter state */
2503         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2504                 PMD_TX_LOG(ALERT,
2505                         "Trying to xmit pkts while device is NOT running\n");
2506                 return 0;
2507         }
2508 #endif
2509
2510         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2511                 if (ena_xmit_mbuf(tx_ring, tx_pkts[sent_idx]))
2512                         break;
2513                 tx_ring->pkts_without_db = true;
2514                 rte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(sent_idx, 4,
2515                         tx_ring->size_mask)]);
2516         }
2517
2518         tx_ring->tx_stats.available_desc =
2519                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2520
2521         /* If there are ready packets to be xmitted... */
2522         if (likely(tx_ring->pkts_without_db)) {
2523                 /* ...let HW do its best :-) */
2524                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2525                 tx_ring->tx_stats.doorbells++;
2526                 tx_ring->pkts_without_db = false;
2527         }
2528
2529         ena_tx_cleanup(tx_ring);
2530
2531         tx_ring->tx_stats.available_desc =
2532                 ena_com_free_q_entries(tx_ring->ena_com_io_sq);
2533         tx_ring->tx_stats.tx_poll++;
2534
2535         return sent_idx;
2536 }
2537
2538 int ena_copy_eni_stats(struct ena_adapter *adapter)
2539 {
2540         struct ena_admin_eni_stats admin_eni_stats;
2541         int rc;
2542
2543         rte_spinlock_lock(&adapter->admin_lock);
2544         rc = ena_com_get_eni_stats(&adapter->ena_dev, &admin_eni_stats);
2545         rte_spinlock_unlock(&adapter->admin_lock);
2546         if (rc != 0) {
2547                 if (rc == ENA_COM_UNSUPPORTED) {
2548                         PMD_DRV_LOG(DEBUG,
2549                                 "Retrieving ENI metrics is not supported\n");
2550                 } else {
2551                         PMD_DRV_LOG(WARNING,
2552                                 "Failed to get ENI metrics, rc: %d\n", rc);
2553                 }
2554                 return rc;
2555         }
2556
2557         rte_memcpy(&adapter->eni_stats, &admin_eni_stats,
2558                 sizeof(struct ena_stats_eni));
2559
2560         return 0;
2561 }
2562
2563 /**
2564  * DPDK callback to retrieve names of extended device statistics
2565  *
2566  * @param dev
2567  *   Pointer to Ethernet device structure.
2568  * @param[out] xstats_names
2569  *   Buffer to insert names into.
2570  * @param n
2571  *   Number of names.
2572  *
2573  * @return
2574  *   Number of xstats names.
2575  */
2576 static int ena_xstats_get_names(struct rte_eth_dev *dev,
2577                                 struct rte_eth_xstat_name *xstats_names,
2578                                 unsigned int n)
2579 {
2580         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2581         unsigned int stat, i, count = 0;
2582
2583         if (n < xstats_count || !xstats_names)
2584                 return xstats_count;
2585
2586         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++)
2587                 strcpy(xstats_names[count].name,
2588                         ena_stats_global_strings[stat].name);
2589
2590         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++)
2591                 strcpy(xstats_names[count].name,
2592                         ena_stats_eni_strings[stat].name);
2593
2594         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++)
2595                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++)
2596                         snprintf(xstats_names[count].name,
2597                                 sizeof(xstats_names[count].name),
2598                                 "rx_q%d_%s", i,
2599                                 ena_stats_rx_strings[stat].name);
2600
2601         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++)
2602                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++)
2603                         snprintf(xstats_names[count].name,
2604                                 sizeof(xstats_names[count].name),
2605                                 "tx_q%d_%s", i,
2606                                 ena_stats_tx_strings[stat].name);
2607
2608         return xstats_count;
2609 }
2610
2611 /**
2612  * DPDK callback to get extended device statistics.
2613  *
2614  * @param dev
2615  *   Pointer to Ethernet device structure.
2616  * @param[out] stats
2617  *   Stats table output buffer.
2618  * @param n
2619  *   The size of the stats table.
2620  *
2621  * @return
2622  *   Number of xstats on success, negative on failure.
2623  */
2624 static int ena_xstats_get(struct rte_eth_dev *dev,
2625                           struct rte_eth_xstat *xstats,
2626                           unsigned int n)
2627 {
2628         struct ena_adapter *adapter = dev->data->dev_private;
2629         unsigned int xstats_count = ena_xstats_calc_num(dev->data);
2630         unsigned int stat, i, count = 0;
2631         int stat_offset;
2632         void *stats_begin;
2633
2634         if (n < xstats_count)
2635                 return xstats_count;
2636
2637         if (!xstats)
2638                 return 0;
2639
2640         for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
2641                 stat_offset = ena_stats_global_strings[stat].stat_offset;
2642                 stats_begin = &adapter->dev_stats;
2643
2644                 xstats[count].id = count;
2645                 xstats[count].value = *((uint64_t *)
2646                         ((char *)stats_begin + stat_offset));
2647         }
2648
2649         /* Even if the function below fails, we should copy previous (or initial
2650          * values) to keep structure of rte_eth_xstat consistent.
2651          */
2652         ena_copy_eni_stats(adapter);
2653         for (stat = 0; stat < ENA_STATS_ARRAY_ENI; stat++, count++) {
2654                 stat_offset = ena_stats_eni_strings[stat].stat_offset;
2655                 stats_begin = &adapter->eni_stats;
2656
2657                 xstats[count].id = count;
2658                 xstats[count].value = *((uint64_t *)
2659                     ((char *)stats_begin + stat_offset));
2660         }
2661
2662         for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) {
2663                 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) {
2664                         stat_offset = ena_stats_rx_strings[stat].stat_offset;
2665                         stats_begin = &adapter->rx_ring[i].rx_stats;
2666
2667                         xstats[count].id = count;
2668                         xstats[count].value = *((uint64_t *)
2669                                 ((char *)stats_begin + stat_offset));
2670                 }
2671         }
2672
2673         for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) {
2674                 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) {
2675                         stat_offset = ena_stats_tx_strings[stat].stat_offset;
2676                         stats_begin = &adapter->tx_ring[i].rx_stats;
2677
2678                         xstats[count].id = count;
2679                         xstats[count].value = *((uint64_t *)
2680                                 ((char *)stats_begin + stat_offset));
2681                 }
2682         }
2683
2684         return count;
2685 }
2686
2687 static int ena_xstats_get_by_id(struct rte_eth_dev *dev,
2688                                 const uint64_t *ids,
2689                                 uint64_t *values,
2690                                 unsigned int n)
2691 {
2692         struct ena_adapter *adapter = dev->data->dev_private;
2693         uint64_t id;
2694         uint64_t rx_entries, tx_entries;
2695         unsigned int i;
2696         int qid;
2697         int valid = 0;
2698         bool was_eni_copied = false;
2699
2700         for (i = 0; i < n; ++i) {
2701                 id = ids[i];
2702                 /* Check if id belongs to global statistics */
2703                 if (id < ENA_STATS_ARRAY_GLOBAL) {
2704                         values[i] = *((uint64_t *)&adapter->dev_stats + id);
2705                         ++valid;
2706                         continue;
2707                 }
2708
2709                 /* Check if id belongs to ENI statistics */
2710                 id -= ENA_STATS_ARRAY_GLOBAL;
2711                 if (id < ENA_STATS_ARRAY_ENI) {
2712                         /* Avoid reading ENI stats multiple times in a single
2713                          * function call, as it requires communication with the
2714                          * admin queue.
2715                          */
2716                         if (!was_eni_copied) {
2717                                 was_eni_copied = true;
2718                                 ena_copy_eni_stats(adapter);
2719                         }
2720                         values[i] = *((uint64_t *)&adapter->eni_stats + id);
2721                         ++valid;
2722                         continue;
2723                 }
2724
2725                 /* Check if id belongs to rx queue statistics */
2726                 id -= ENA_STATS_ARRAY_ENI;
2727                 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues;
2728                 if (id < rx_entries) {
2729                         qid = id % dev->data->nb_rx_queues;
2730                         id /= dev->data->nb_rx_queues;
2731                         values[i] = *((uint64_t *)
2732                                 &adapter->rx_ring[qid].rx_stats + id);
2733                         ++valid;
2734                         continue;
2735                 }
2736                                 /* Check if id belongs to rx queue statistics */
2737                 id -= rx_entries;
2738                 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues;
2739                 if (id < tx_entries) {
2740                         qid = id % dev->data->nb_tx_queues;
2741                         id /= dev->data->nb_tx_queues;
2742                         values[i] = *((uint64_t *)
2743                                 &adapter->tx_ring[qid].tx_stats + id);
2744                         ++valid;
2745                         continue;
2746                 }
2747         }
2748
2749         return valid;
2750 }
2751
2752 static int ena_process_bool_devarg(const char *key,
2753                                    const char *value,
2754                                    void *opaque)
2755 {
2756         struct ena_adapter *adapter = opaque;
2757         bool bool_value;
2758
2759         /* Parse the value. */
2760         if (strcmp(value, "1") == 0) {
2761                 bool_value = true;
2762         } else if (strcmp(value, "0") == 0) {
2763                 bool_value = false;
2764         } else {
2765                 PMD_INIT_LOG(ERR,
2766                         "Invalid value: '%s' for key '%s'. Accepted: '0' or '1'\n",
2767                         value, key);
2768                 return -EINVAL;
2769         }
2770
2771         /* Now, assign it to the proper adapter field. */
2772         if (strcmp(key, ENA_DEVARG_LARGE_LLQ_HDR) == 0)
2773                 adapter->use_large_llq_hdr = bool_value;
2774
2775         return 0;
2776 }
2777
2778 static int ena_parse_devargs(struct ena_adapter *adapter,
2779                              struct rte_devargs *devargs)
2780 {
2781         static const char * const allowed_args[] = {
2782                 ENA_DEVARG_LARGE_LLQ_HDR,
2783                 NULL,
2784         };
2785         struct rte_kvargs *kvlist;
2786         int rc;
2787
2788         if (devargs == NULL)
2789                 return 0;
2790
2791         kvlist = rte_kvargs_parse(devargs->args, allowed_args);
2792         if (kvlist == NULL) {
2793                 PMD_INIT_LOG(ERR, "Invalid device arguments: %s\n",
2794                         devargs->args);
2795                 return -EINVAL;
2796         }
2797
2798         rc = rte_kvargs_process(kvlist, ENA_DEVARG_LARGE_LLQ_HDR,
2799                 ena_process_bool_devarg, adapter);
2800
2801         rte_kvargs_free(kvlist);
2802
2803         return rc;
2804 }
2805
2806 static int ena_setup_rx_intr(struct rte_eth_dev *dev)
2807 {
2808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2809         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2810         int rc;
2811         uint16_t vectors_nb, i;
2812         bool rx_intr_requested = dev->data->dev_conf.intr_conf.rxq;
2813
2814         if (!rx_intr_requested)
2815                 return 0;
2816
2817         if (!rte_intr_cap_multiple(intr_handle)) {
2818                 PMD_DRV_LOG(ERR,
2819                         "Rx interrupt requested, but it isn't supported by the PCI driver\n");
2820                 return -ENOTSUP;
2821         }
2822
2823         /* Disable interrupt mapping before the configuration starts. */
2824         rte_intr_disable(intr_handle);
2825
2826         /* Verify if there are enough vectors available. */
2827         vectors_nb = dev->data->nb_rx_queues;
2828         if (vectors_nb > RTE_MAX_RXTX_INTR_VEC_ID) {
2829                 PMD_DRV_LOG(ERR,
2830                         "Too many Rx interrupts requested, maximum number: %d\n",
2831                         RTE_MAX_RXTX_INTR_VEC_ID);
2832                 rc = -ENOTSUP;
2833                 goto enable_intr;
2834         }
2835
2836         intr_handle->intr_vec = rte_zmalloc("intr_vec",
2837                 dev->data->nb_rx_queues * sizeof(*intr_handle->intr_vec), 0);
2838         if (intr_handle->intr_vec == NULL) {
2839                 PMD_DRV_LOG(ERR,
2840                         "Failed to allocate interrupt vector for %d queues\n",
2841                         dev->data->nb_rx_queues);
2842                 rc = -ENOMEM;
2843                 goto enable_intr;
2844         }
2845
2846         rc = rte_intr_efd_enable(intr_handle, vectors_nb);
2847         if (rc != 0)
2848                 goto free_intr_vec;
2849
2850         if (!rte_intr_allow_others(intr_handle)) {
2851                 PMD_DRV_LOG(ERR,
2852                         "Not enough interrupts available to use both ENA Admin and Rx interrupts\n");
2853                 goto disable_intr_efd;
2854         }
2855
2856         for (i = 0; i < vectors_nb; ++i)
2857                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + i;
2858
2859         rte_intr_enable(intr_handle);
2860         return 0;
2861
2862 disable_intr_efd:
2863         rte_intr_efd_disable(intr_handle);
2864 free_intr_vec:
2865         rte_free(intr_handle->intr_vec);
2866         intr_handle->intr_vec = NULL;
2867 enable_intr:
2868         rte_intr_enable(intr_handle);
2869         return rc;
2870 }
2871
2872 static void ena_rx_queue_intr_set(struct rte_eth_dev *dev,
2873                                  uint16_t queue_id,
2874                                  bool unmask)
2875 {
2876         struct ena_adapter *adapter = dev->data->dev_private;
2877         struct ena_ring *rxq = &adapter->rx_ring[queue_id];
2878         struct ena_eth_io_intr_reg intr_reg;
2879
2880         ena_com_update_intr_reg(&intr_reg, 0, 0, unmask);
2881         ena_com_unmask_intr(rxq->ena_com_io_cq, &intr_reg);
2882 }
2883
2884 static int ena_rx_queue_intr_enable(struct rte_eth_dev *dev,
2885                                     uint16_t queue_id)
2886 {
2887         ena_rx_queue_intr_set(dev, queue_id, true);
2888
2889         return 0;
2890 }
2891
2892 static int ena_rx_queue_intr_disable(struct rte_eth_dev *dev,
2893                                      uint16_t queue_id)
2894 {
2895         ena_rx_queue_intr_set(dev, queue_id, false);
2896
2897         return 0;
2898 }
2899
2900 /*********************************************************************
2901  *  PMD configuration
2902  *********************************************************************/
2903 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2904         struct rte_pci_device *pci_dev)
2905 {
2906         return rte_eth_dev_pci_generic_probe(pci_dev,
2907                 sizeof(struct ena_adapter), eth_ena_dev_init);
2908 }
2909
2910 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2911 {
2912         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2913 }
2914
2915 static struct rte_pci_driver rte_ena_pmd = {
2916         .id_table = pci_id_ena_map,
2917         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2918                      RTE_PCI_DRV_WC_ACTIVATE,
2919         .probe = eth_ena_pci_probe,
2920         .remove = eth_ena_pci_remove,
2921 };
2922
2923 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2924 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2925 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2926 RTE_PMD_REGISTER_PARAM_STRING(net_ena, ENA_DEVARG_LARGE_LLQ_HDR "=<0|1>");
2927 RTE_LOG_REGISTER_SUFFIX(ena_logtype_init, init, NOTICE);
2928 RTE_LOG_REGISTER_SUFFIX(ena_logtype_driver, driver, NOTICE);
2929 #ifdef RTE_ETHDEV_DEBUG_RX
2930 RTE_LOG_REGISTER_SUFFIX(ena_logtype_rx, rx, DEBUG);
2931 #endif
2932 #ifdef RTE_ETHDEV_DEBUG_TX
2933 RTE_LOG_REGISTER_SUFFIX(ena_logtype_tx, tx, DEBUG);
2934 #endif
2935 RTE_LOG_REGISTER_SUFFIX(ena_logtype_com, com, WARNING);
2936
2937 /******************************************************************************
2938  ******************************** AENQ Handlers *******************************
2939  *****************************************************************************/
2940 static void ena_update_on_link_change(void *adapter_data,
2941                                       struct ena_admin_aenq_entry *aenq_e)
2942 {
2943         struct rte_eth_dev *eth_dev = adapter_data;
2944         struct ena_adapter *adapter = eth_dev->data->dev_private;
2945         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2946         uint32_t status;
2947
2948         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2949
2950         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2951         adapter->link_status = status;
2952
2953         ena_link_update(eth_dev, 0);
2954         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2955 }
2956
2957 static void ena_notification(void *adapter_data,
2958                              struct ena_admin_aenq_entry *aenq_e)
2959 {
2960         struct rte_eth_dev *eth_dev = adapter_data;
2961         struct ena_adapter *adapter = eth_dev->data->dev_private;
2962         struct ena_admin_ena_hw_hints *hints;
2963
2964         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2965                 PMD_DRV_LOG(WARNING, "Invalid AENQ group: %x. Expected: %x\n",
2966                         aenq_e->aenq_common_desc.group,
2967                         ENA_ADMIN_NOTIFICATION);
2968
2969         switch (aenq_e->aenq_common_desc.syndrome) {
2970         case ENA_ADMIN_UPDATE_HINTS:
2971                 hints = (struct ena_admin_ena_hw_hints *)
2972                         (&aenq_e->inline_data_w4);
2973                 ena_update_hints(adapter, hints);
2974                 break;
2975         default:
2976                 PMD_DRV_LOG(ERR, "Invalid AENQ notification link state: %d\n",
2977                         aenq_e->aenq_common_desc.syndrome);
2978         }
2979 }
2980
2981 static void ena_keep_alive(void *adapter_data,
2982                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2983 {
2984         struct rte_eth_dev *eth_dev = adapter_data;
2985         struct ena_adapter *adapter = eth_dev->data->dev_private;
2986         struct ena_admin_aenq_keep_alive_desc *desc;
2987         uint64_t rx_drops;
2988         uint64_t tx_drops;
2989
2990         adapter->timestamp_wd = rte_get_timer_cycles();
2991
2992         desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e;
2993         rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low;
2994         tx_drops = ((uint64_t)desc->tx_drops_high << 32) | desc->tx_drops_low;
2995
2996         adapter->drv_stats->rx_drops = rx_drops;
2997         adapter->dev_stats.tx_drops = tx_drops;
2998 }
2999
3000 /**
3001  * This handler will called for unknown event group or unimplemented handlers
3002  **/
3003 static void unimplemented_aenq_handler(__rte_unused void *data,
3004                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
3005 {
3006         PMD_DRV_LOG(ERR,
3007                 "Unknown event was received or event with unimplemented handler\n");
3008 }
3009
3010 static struct ena_aenq_handlers aenq_handlers = {
3011         .handlers = {
3012                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3013                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3014                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
3015         },
3016         .unimplemented_handler = unimplemented_aenq_handler
3017 };