drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev.h>
  36 #include <rte_tcp.h>
  37 #include <rte_atomic.h>
  38 #include <rte_dev.h>
  39 #include <rte_errno.h>
  40 #include <rte_version.h>
  41 #include <rte_eal_memconfig.h>
  42
  43 #include "ena_ethdev.h"
  44 #include "ena_logs.h"
  45 #include "ena_platform.h"
  46 #include "ena_com.h"
  47 #include "ena_eth_com.h"
  48
  49 #include <ena_common_defs.h>
  50 #include <ena_regs_defs.h>
  51 #include <ena_admin_defs.h>
  52 #include <ena_eth_io_defs.h>
  53
  54 #define DRV_MODULE_VER_MAJOR    1
  55 #define DRV_MODULE_VER_MINOR    0
  56 #define DRV_MODULE_VER_SUBMINOR 0
  57
  58 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  59 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  60 /*reverse version of ENA_IO_RXQ_IDX*/
  61 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  62
  63 /* While processing submitted and completed descriptors (rx and tx path
  64  * respectively) in a loop it is desired to:
  65  *  - perform batch submissions while populating sumbissmion queue
  66  *  - avoid blocking transmission of other packets during cleanup phase
  67  * Hence the utilization ratio of 1/8 of a queue size.
  68  */
  69 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  70
  71 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  72 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  73
  74 #define GET_L4_HDR_LEN(mbuf)                                    \
  75         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  76                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  77
  78 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  79 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  80 #define ENA_HASH_KEY_SIZE       40
  81 #define ENA_ETH_SS_STATS        0xFF
  82 #define ETH_GSTRING_LEN 32
  83
  84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  85
  86 enum ethtool_stringset {
  87         ETH_SS_TEST             = 0,
  88         ETH_SS_STATS,
  89 };
  90
  91 struct ena_stats {
  92         char name[ETH_GSTRING_LEN];
  93         int stat_offset;
  94 };
  95
  96 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  97         .name = #stat, \
  98         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
  99 }
 100
 101 #define ENA_STAT_ENTRY(stat, stat_type) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 104 }
 105
 106 #define ENA_STAT_RX_ENTRY(stat) \
 107         ENA_STAT_ENTRY(stat, rx)
 108
 109 #define ENA_STAT_TX_ENTRY(stat) \
 110         ENA_STAT_ENTRY(stat, tx)
 111
 112 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 113         ENA_STAT_ENTRY(stat, dev)
 114
 115 static const struct ena_stats ena_stats_global_strings[] = {
 116         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 117         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 118         ENA_STAT_GLOBAL_ENTRY(io_resume),
 119         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 120         ENA_STAT_GLOBAL_ENTRY(interface_up),
 121         ENA_STAT_GLOBAL_ENTRY(interface_down),
 122         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 123 };
 124
 125 static const struct ena_stats ena_stats_tx_strings[] = {
 126         ENA_STAT_TX_ENTRY(cnt),
 127         ENA_STAT_TX_ENTRY(bytes),
 128         ENA_STAT_TX_ENTRY(queue_stop),
 129         ENA_STAT_TX_ENTRY(queue_wakeup),
 130         ENA_STAT_TX_ENTRY(dma_mapping_err),
 131         ENA_STAT_TX_ENTRY(linearize),
 132         ENA_STAT_TX_ENTRY(linearize_failed),
 133         ENA_STAT_TX_ENTRY(tx_poll),
 134         ENA_STAT_TX_ENTRY(doorbells),
 135         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 136         ENA_STAT_TX_ENTRY(missing_tx_comp),
 137         ENA_STAT_TX_ENTRY(bad_req_id),
 138 };
 139
 140 static const struct ena_stats ena_stats_rx_strings[] = {
 141         ENA_STAT_RX_ENTRY(cnt),
 142         ENA_STAT_RX_ENTRY(bytes),
 143         ENA_STAT_RX_ENTRY(refil_partial),
 144         ENA_STAT_RX_ENTRY(bad_csum),
 145         ENA_STAT_RX_ENTRY(page_alloc_fail),
 146         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 147         ENA_STAT_RX_ENTRY(dma_mapping_err),
 148         ENA_STAT_RX_ENTRY(bad_desc_num),
 149         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 150 };
 151
 152 static const struct ena_stats ena_stats_ena_com_strings[] = {
 153         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 154         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 155         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 157         ENA_STAT_ENA_COM_ENTRY(no_completion),
 158 };
 159
 160 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 161 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 162 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 163 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 164
 165 /** Vendor ID used by Amazon devices */
 166 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 167 /** Amazon devices */
 168 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 169 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 170
 171 static struct rte_pci_id pci_id_ena_map[] = {
 172 #define RTE_PCI_DEV_ID_DECL_ENA(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 173         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF)
 174         RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF)
 175         {.device_id = 0},
 176 };
 177
 178 static int ena_device_init(struct ena_com_dev *ena_dev,
 179                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 180 static int ena_dev_configure(struct rte_eth_dev *dev);
 181 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 182                                   uint16_t nb_pkts);
 183 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 184                               uint16_t nb_desc, unsigned int socket_id,
 185                               const struct rte_eth_txconf *tx_conf);
 186 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 187                               uint16_t nb_desc, unsigned int socket_id,
 188                               const struct rte_eth_rxconf *rx_conf,
 189                               struct rte_mempool *mp);
 190 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 191                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 192 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 193 static void ena_init_rings(struct ena_adapter *adapter);
 194 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 195 static int ena_start(struct rte_eth_dev *dev);
 196 static void ena_close(struct rte_eth_dev *dev);
 197 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 198 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 199 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 200 static void ena_rx_queue_release(void *queue);
 201 static void ena_tx_queue_release(void *queue);
 202 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 203 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 204 static int ena_link_update(struct rte_eth_dev *dev,
 205                            __rte_unused int wait_to_complete);
 206 static int ena_queue_restart(struct ena_ring *ring);
 207 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 208                                  enum ena_ring_type ring_type);
 209 static void ena_stats_restart(struct rte_eth_dev *dev);
 210 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
 211                           struct rte_eth_dev_info *dev_info);
 212 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 213                                struct rte_eth_rss_reta_entry64 *reta_conf,
 214                                uint16_t reta_size);
 215 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 216                               struct rte_eth_rss_reta_entry64 *reta_conf,
 217                               uint16_t reta_size);
 218 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 219
 220 static struct eth_dev_ops ena_dev_ops = {
 221         .dev_configure        = ena_dev_configure,
 222         .dev_infos_get        = ena_infos_get,
 223         .rx_queue_setup       = ena_rx_queue_setup,
 224         .tx_queue_setup       = ena_tx_queue_setup,
 225         .dev_start            = ena_start,
 226         .link_update          = ena_link_update,
 227         .stats_get            = ena_stats_get,
 228         .mtu_set              = ena_mtu_set,
 229         .rx_queue_release     = ena_rx_queue_release,
 230         .tx_queue_release     = ena_tx_queue_release,
 231         .dev_close            = ena_close,
 232         .reta_update          = ena_rss_reta_update,
 233         .reta_query           = ena_rss_reta_query,
 234 };
 235
 236 #define NUMA_NO_NODE    SOCKET_ID_ANY
 237
 238 static inline int ena_cpu_to_node(int cpu)
 239 {
 240         struct rte_config *config = rte_eal_get_configuration();
 241
 242         if (likely(cpu < RTE_MAX_MEMZONE))
 243                 return config->mem_config->memzone[cpu].socket_id;
 244
 245         return NUMA_NO_NODE;
 246 }
 247
 248 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 249                                        struct ena_com_rx_ctx *ena_rx_ctx)
 250 {
 251         uint64_t ol_flags = 0;
 252
 253         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 254                 ol_flags |= PKT_TX_TCP_CKSUM;
 255         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 256                 ol_flags |= PKT_TX_UDP_CKSUM;
 257
 258         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 259                 ol_flags |= PKT_TX_IPV4;
 260         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 261                 ol_flags |= PKT_TX_IPV6;
 262
 263         if (unlikely(ena_rx_ctx->l4_csum_err))
 264                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 265         if (unlikely(ena_rx_ctx->l3_csum_err))
 266                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 267
 268         mbuf->ol_flags = ol_flags;
 269 }
 270
 271 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 272                                        struct ena_com_tx_ctx *ena_tx_ctx)
 273 {
 274         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 275
 276         if (mbuf->ol_flags &
 277             (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
 278                 /* check if TSO is required */
 279                 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
 280                         ena_tx_ctx->tso_enable = true;
 281
 282                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 283                 }
 284
 285                 /* check if L3 checksum is needed */
 286                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
 287                         ena_tx_ctx->l3_csum_enable = true;
 288
 289                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 290                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 291                 } else {
 292                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 293
 294                         /* set don't fragment (DF) flag */
 295                         if (mbuf->packet_type &
 296                                 (RTE_PTYPE_L4_NONFRAG
 297                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 298                                 ena_tx_ctx->df = true;
 299                 }
 300
 301                 /* check if L4 checksum is needed */
 302                 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
 303                 case PKT_TX_TCP_CKSUM:
 304                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 305                         ena_tx_ctx->l4_csum_enable = true;
 306                         break;
 307                 case PKT_TX_UDP_CKSUM:
 308                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 309                         ena_tx_ctx->l4_csum_enable = true;
 310                         break;
 311                 default:
 312                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 313                         ena_tx_ctx->l4_csum_enable = false;
 314                         break;
 315                 }
 316
 317                 ena_meta->mss = mbuf->tso_segsz;
 318                 ena_meta->l3_hdr_len = mbuf->l3_len;
 319                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 320                 /* this param needed only for TSO */
 321                 ena_meta->l3_outer_hdr_len = 0;
 322                 ena_meta->l3_outer_hdr_offset = 0;
 323
 324                 ena_tx_ctx->meta_valid = true;
 325         } else {
 326                 ena_tx_ctx->meta_valid = false;
 327         }
 328 }
 329
 330 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 331 {
 332         struct ena_admin_host_info *host_info;
 333         int rc;
 334
 335         /* Allocate only the host info */
 336         rc = ena_com_allocate_host_info(ena_dev);
 337         if (rc) {
 338                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 339                 return;
 340         }
 341
 342         host_info = ena_dev->host_attr.host_info;
 343
 344         host_info->os_type = ENA_ADMIN_OS_DPDK;
 345         host_info->kernel_ver = RTE_VERSION;
 346         strncpy((char *)host_info->kernel_ver_str, rte_version(),
 347                 strlen(rte_version()));
 348         host_info->os_dist = RTE_VERSION;
 349         strncpy((char *)host_info->os_dist_str, rte_version(),
 350                 strlen(rte_version()));
 351         host_info->driver_version =
 352                 (DRV_MODULE_VER_MAJOR) |
 353                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 354                 (DRV_MODULE_VER_SUBMINOR <<
 355                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 356
 357         rc = ena_com_set_host_attributes(ena_dev);
 358         if (rc) {
 359                 if (rc == -EPERM)
 360                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 361                 else
 362                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 363
 364                 goto err;
 365         }
 366
 367         return;
 368
 369 err:
 370         ena_com_delete_host_info(ena_dev);
 371 }
 372
 373 static int
 374 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 375 {
 376         if (sset != ETH_SS_STATS)
 377                 return -EOPNOTSUPP;
 378
 379          /* Workaround for clang:
 380          * touch internal structures to prevent
 381          * compiler error
 382          */
 383         ENA_TOUCH(ena_stats_global_strings);
 384         ENA_TOUCH(ena_stats_tx_strings);
 385         ENA_TOUCH(ena_stats_rx_strings);
 386         ENA_TOUCH(ena_stats_ena_com_strings);
 387
 388         return  dev->data->nb_tx_queues *
 389                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 390                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 391 }
 392
 393 static void ena_config_debug_area(struct ena_adapter *adapter)
 394 {
 395         u32 debug_area_size;
 396         int rc, ss_count;
 397
 398         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 399         if (ss_count <= 0) {
 400                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 401                 return;
 402         }
 403
 404         /* allocate 32 bytes for each string and 64bit for the value */
 405         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 406
 407         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 408         if (rc) {
 409                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 410                 return;
 411         }
 412
 413         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 414         if (rc) {
 415                 if (rc == -EPERM)
 416                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 417                 else
 418                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 419                 goto err;
 420         }
 421
 422         return;
 423 err:
 424         ena_com_delete_debug_area(&adapter->ena_dev);
 425 }
 426
 427 static void ena_close(struct rte_eth_dev *dev)
 428 {
 429         struct ena_adapter *adapter =
 430                 (struct ena_adapter *)(dev->data->dev_private);
 431
 432         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 433
 434         ena_rx_queue_release_all(dev);
 435         ena_tx_queue_release_all(dev);
 436 }
 437
 438 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 439                                struct rte_eth_rss_reta_entry64 *reta_conf,
 440                                uint16_t reta_size)
 441 {
 442         struct ena_adapter *adapter =
 443                 (struct ena_adapter *)(dev->data->dev_private);
 444         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 445         int ret, i;
 446         u16 entry_value;
 447         int conf_idx;
 448         int idx;
 449
 450         if ((reta_size == 0) || (reta_conf == NULL))
 451                 return -EINVAL;
 452
 453         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 454                 RTE_LOG(WARNING, PMD,
 455                         "indirection table %d is bigger than supported (%d)\n",
 456                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 457                 ret = -EINVAL;
 458                 goto err;
 459         }
 460
 461         for (i = 0 ; i < reta_size ; i++) {
 462                 /* each reta_conf is for 64 entries.
 463                  * to support 128 we use 2 conf of 64
 464                  */
 465                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 466                 idx = i % RTE_RETA_GROUP_SIZE;
 467                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 468                         entry_value =
 469                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 470                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 471                                                                 i,
 472                                                                 entry_value);
 473                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 474                                 RTE_LOG(ERR, PMD,
 475                                         "Cannot fill indirect table\n");
 476                                 ret = -ENOTSUP;
 477                                 goto err;
 478                         }
 479                 }
 480         }
 481
 482         ret = ena_com_indirect_table_set(ena_dev);
 483         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 484                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 485                 ret = -ENOTSUP;
 486                 goto err;
 487         }
 488
 489         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 490                 __func__, reta_size, adapter->rte_dev->data->port_id);
 491 err:
 492         return ret;
 493 }
 494
 495 /* Query redirection table. */
 496 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 497                               struct rte_eth_rss_reta_entry64 *reta_conf,
 498                               uint16_t reta_size)
 499 {
 500         struct ena_adapter *adapter =
 501                 (struct ena_adapter *)(dev->data->dev_private);
 502         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 503         int ret;
 504         int i;
 505         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 506         int reta_conf_idx;
 507         int reta_idx;
 508
 509         if (reta_size == 0 || reta_conf == NULL ||
 510             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 511                 return -EINVAL;
 512
 513         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 514         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 515                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 516                 ret = -ENOTSUP;
 517                 goto err;
 518         }
 519
 520         for (i = 0 ; i < reta_size ; i++) {
 521                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 522                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 523                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 524                         reta_conf[reta_conf_idx].reta[reta_idx] =
 525                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 526         }
 527 err:
 528         return ret;
 529 }
 530
 531 static int ena_rss_init_default(struct ena_adapter *adapter)
 532 {
 533         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 534         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 535         int rc, i;
 536         u32 val;
 537
 538         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 539         if (unlikely(rc)) {
 540                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 541                 goto err_rss_init;
 542         }
 543
 544         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 545                 val = i % nb_rx_queues;
 546                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 547                                                        ENA_IO_RXQ_IDX(val));
 548                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 549                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 550                         goto err_fill_indir;
 551                 }
 552         }
 553
 554         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 555                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 556         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 557                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 558                 goto err_fill_indir;
 559         }
 560
 561         rc = ena_com_set_default_hash_ctrl(ena_dev);
 562         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 563                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 564                 goto err_fill_indir;
 565         }
 566
 567         rc = ena_com_indirect_table_set(ena_dev);
 568         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 569                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 570                 goto err_fill_indir;
 571         }
 572         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 573                 adapter->rte_dev->data->port_id);
 574
 575         return 0;
 576
 577 err_fill_indir:
 578         ena_com_rss_destroy(ena_dev);
 579 err_rss_init:
 580
 581         return rc;
 582 }
 583
 584 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 585 {
 586         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 587         int nb_queues = dev->data->nb_rx_queues;
 588         int i;
 589
 590         for (i = 0; i < nb_queues; i++)
 591                 ena_rx_queue_release(queues[i]);
 592 }
 593
 594 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 595 {
 596         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 597         int nb_queues = dev->data->nb_tx_queues;
 598         int i;
 599
 600         for (i = 0; i < nb_queues; i++)
 601                 ena_tx_queue_release(queues[i]);
 602 }
 603
 604 static void ena_rx_queue_release(void *queue)
 605 {
 606         struct ena_ring *ring = (struct ena_ring *)queue;
 607         struct ena_adapter *adapter = ring->adapter;
 608         int ena_qid;
 609
 610         ena_assert_msg(ring->configured,
 611                        "API violation - releasing not configured queue");
 612         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 613                        "API violation");
 614
 615         /* Destroy HW queue */
 616         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 617         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 618
 619         /* Free all bufs */
 620         ena_rx_queue_release_bufs(ring);
 621
 622         /* Free ring resources */
 623         if (ring->rx_buffer_info)
 624                 rte_free(ring->rx_buffer_info);
 625         ring->rx_buffer_info = NULL;
 626
 627         ring->configured = 0;
 628
 629         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 630                 ring->port_id, ring->id);
 631 }
 632
 633 static void ena_tx_queue_release(void *queue)
 634 {
 635         struct ena_ring *ring = (struct ena_ring *)queue;
 636         struct ena_adapter *adapter = ring->adapter;
 637         int ena_qid;
 638
 639         ena_assert_msg(ring->configured,
 640                        "API violation. Releasing not configured queue");
 641         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 642                        "API violation");
 643
 644         /* Destroy HW queue */
 645         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 646         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 647
 648         /* Free all bufs */
 649         ena_tx_queue_release_bufs(ring);
 650
 651         /* Free ring resources */
 652         if (ring->tx_buffer_info)
 653                 rte_free(ring->tx_buffer_info);
 654
 655         if (ring->empty_tx_reqs)
 656                 rte_free(ring->empty_tx_reqs);
 657
 658         ring->empty_tx_reqs = NULL;
 659         ring->tx_buffer_info = NULL;
 660
 661         ring->configured = 0;
 662
 663         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 664                 ring->port_id, ring->id);
 665 }
 666
 667 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 668 {
 669         unsigned int ring_mask = ring->ring_size - 1;
 670
 671         while (ring->next_to_clean != ring->next_to_use) {
 672                 struct rte_mbuf *m =
 673                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 674
 675                 if (m)
 676                         __rte_mbuf_raw_free(m);
 677
 678                 ring->next_to_clean =
 679                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 680         }
 681 }
 682
 683 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 684 {
 685         unsigned int ring_mask = ring->ring_size - 1;
 686
 687         while (ring->next_to_clean != ring->next_to_use) {
 688                 struct ena_tx_buffer *tx_buf =
 689                         &ring->tx_buffer_info[ring->next_to_clean & ring_mask];
 690
 691                 if (tx_buf->mbuf)
 692                         rte_pktmbuf_free(tx_buf->mbuf);
 693
 694                 ring->next_to_clean =
 695                         ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
 696         }
 697 }
 698
 699 static int ena_link_update(struct rte_eth_dev *dev,
 700                            __rte_unused int wait_to_complete)
 701 {
 702         struct rte_eth_link *link = &dev->data->dev_link;
 703
 704         link->link_status = 1;
 705         link->link_speed = ETH_SPEED_NUM_10G;
 706         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 707
 708         return 0;
 709 }
 710
 711 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 712                                  enum ena_ring_type ring_type)
 713 {
 714         struct ena_adapter *adapter =
 715                 (struct ena_adapter *)(dev->data->dev_private);
 716         struct ena_ring *queues = NULL;
 717         int i = 0;
 718         int rc = 0;
 719
 720         queues = (ring_type == ENA_RING_TYPE_RX) ?
 721                 adapter->rx_ring : adapter->tx_ring;
 722
 723         for (i = 0; i < adapter->num_queues; i++) {
 724                 if (queues[i].configured) {
 725                         if (ring_type == ENA_RING_TYPE_RX) {
 726                                 ena_assert_msg(
 727                                         dev->data->rx_queues[i] == &queues[i],
 728                                         "Inconsistent state of rx queues\n");
 729                         } else {
 730                                 ena_assert_msg(
 731                                         dev->data->tx_queues[i] == &queues[i],
 732                                         "Inconsistent state of tx queues\n");
 733                         }
 734
 735                         rc = ena_queue_restart(&queues[i]);
 736
 737                         if (rc) {
 738                                 PMD_INIT_LOG(ERR,
 739                                              "failed to restart queue %d type(%d)\n",
 740                                              i, ring_type);
 741                                 return -1;
 742                         }
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 750 {
 751         uint32_t max_frame_len = adapter->max_mtu;
 752
 753         if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
 754                 max_frame_len =
 755                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 756
 757         return max_frame_len;
 758 }
 759
 760 static int ena_check_valid_conf(struct ena_adapter *adapter)
 761 {
 762         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 763
 764         if (max_frame_len > adapter->max_mtu) {
 765                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
 766                 return -1;
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int
 773 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 774                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 775 {
 776         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 777
 778         queue_size = RTE_MIN(queue_size,
 779                              get_feat_ctx->max_queues.max_cq_depth);
 780         queue_size = RTE_MIN(queue_size,
 781                              get_feat_ctx->max_queues.max_sq_depth);
 782
 783         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 784                 queue_size = RTE_MIN(queue_size,
 785                                      get_feat_ctx->max_queues.max_llq_depth);
 786
 787         /* Round down to power of 2 */
 788         if (!rte_is_power_of_2(queue_size))
 789                 queue_size = rte_align32pow2(queue_size >> 1);
 790
 791         if (queue_size == 0) {
 792                 PMD_INIT_LOG(ERR, "Invalid queue size\n");
 793                 return -EFAULT;
 794         }
 795
 796         return queue_size;
 797 }
 798
 799 static void ena_stats_restart(struct rte_eth_dev *dev)
 800 {
 801         struct ena_adapter *adapter =
 802                 (struct ena_adapter *)(dev->data->dev_private);
 803
 804         rte_atomic64_init(&adapter->drv_stats->ierrors);
 805         rte_atomic64_init(&adapter->drv_stats->oerrors);
 806         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 807 }
 808
 809 static void ena_stats_get(struct rte_eth_dev *dev,
 810                           struct rte_eth_stats *stats)
 811 {
 812         struct ena_admin_basic_stats ena_stats;
 813         struct ena_adapter *adapter =
 814                 (struct ena_adapter *)(dev->data->dev_private);
 815         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 816         int rc;
 817
 818         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 819                 return;
 820
 821         memset(&ena_stats, 0, sizeof(ena_stats));
 822         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 823         if (unlikely(rc)) {
 824                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 825                 return;
 826         }
 827
 828         /* Set of basic statistics from ENA */
 829         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 830                                           ena_stats.rx_pkts_low);
 831         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 832                                           ena_stats.tx_pkts_low);
 833         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 834                                         ena_stats.rx_bytes_low);
 835         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 836                                         ena_stats.tx_bytes_low);
 837         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 838                                          ena_stats.rx_drops_low);
 839
 840         /* Driver related stats */
 841         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 842         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 843         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 844 }
 845
 846 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 847 {
 848         struct ena_adapter *adapter;
 849         struct ena_com_dev *ena_dev;
 850         int rc = 0;
 851
 852         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 853         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 854         adapter = (struct ena_adapter *)(dev->data->dev_private);
 855
 856         ena_dev = &adapter->ena_dev;
 857         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 858
 859         if (mtu > ena_get_mtu_conf(adapter)) {
 860                 RTE_LOG(ERR, PMD,
 861                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 862                         mtu, ena_get_mtu_conf(adapter));
 863                 rc = -EINVAL;
 864                 goto err;
 865         }
 866
 867         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 868         if (rc)
 869                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 870         else
 871                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 872
 873 err:
 874         return rc;
 875 }
 876
 877 static int ena_start(struct rte_eth_dev *dev)
 878 {
 879         struct ena_adapter *adapter =
 880                 (struct ena_adapter *)(dev->data->dev_private);
 881         int rc = 0;
 882
 883         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 884               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 885                 PMD_INIT_LOG(ERR, "API violation");
 886                 return -1;
 887         }
 888
 889         rc = ena_check_valid_conf(adapter);
 890         if (rc)
 891                 return rc;
 892
 893         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 894         if (rc)
 895                 return rc;
 896
 897         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 898         if (rc)
 899                 return rc;
 900
 901         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 902             ETH_MQ_RX_RSS_FLAG) {
 903                 rc = ena_rss_init_default(adapter);
 904                 if (rc)
 905                         return rc;
 906         }
 907
 908         ena_stats_restart(dev);
 909
 910         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 911
 912         return 0;
 913 }
 914
 915 static int ena_queue_restart(struct ena_ring *ring)
 916 {
 917         int rc;
 918
 919         ena_assert_msg(ring->configured == 1,
 920                        "Trying to restart unconfigured queue\n");
 921
 922         ring->next_to_clean = 0;
 923         ring->next_to_use = 0;
 924
 925         if (ring->type == ENA_RING_TYPE_TX)
 926                 return 0;
 927
 928         rc = ena_populate_rx_queue(ring, ring->ring_size - 1);
 929         if ((unsigned int)rc != ring->ring_size - 1) {
 930                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !\n");
 931                 return (-1);
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 938                               uint16_t queue_idx,
 939                               uint16_t nb_desc,
 940                               __rte_unused unsigned int socket_id,
 941                               __rte_unused const struct rte_eth_txconf *tx_conf)
 942 {
 943         struct ena_com_create_io_ctx ctx =
 944                 /* policy set to _HOST just to satisfy icc compiler */
 945                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 946                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 947         struct ena_ring *txq = NULL;
 948         struct ena_adapter *adapter =
 949                 (struct ena_adapter *)(dev->data->dev_private);
 950         unsigned int i;
 951         int ena_qid;
 952         int rc;
 953         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 954
 955         txq = &adapter->tx_ring[queue_idx];
 956
 957         if (txq->configured) {
 958                 RTE_LOG(CRIT, PMD,
 959                         "API violation. Queue %d is already configured\n",
 960                         queue_idx);
 961                 return -1;
 962         }
 963
 964         if (nb_desc > adapter->tx_ring_size) {
 965                 RTE_LOG(ERR, PMD,
 966                         "Unsupported size of TX queue (max size: %d)\n",
 967                         adapter->tx_ring_size);
 968                 return -EINVAL;
 969         }
 970
 971         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
 972
 973         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
 974         ctx.qid = ena_qid;
 975         ctx.msix_vector = -1; /* admin interrupts not used */
 976         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
 977         ctx.queue_size = adapter->tx_ring_size;
 978         ctx.numa_node = ena_cpu_to_node(queue_idx);
 979
 980         rc = ena_com_create_io_queue(ena_dev, &ctx);
 981         if (rc) {
 982                 RTE_LOG(ERR, PMD,
 983                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
 984                         queue_idx, ena_qid, rc);
 985         }
 986         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
 987         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
 988
 989         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
 990                                      &txq->ena_com_io_sq,
 991                                      &txq->ena_com_io_cq);
 992         if (rc) {
 993                 RTE_LOG(ERR, PMD,
 994                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
 995                         queue_idx, rc);
 996                 ena_com_destroy_io_queue(ena_dev, ena_qid);
 997                 goto err;
 998         }
 999
1000         txq->port_id = dev->data->port_id;
1001         txq->next_to_clean = 0;
1002         txq->next_to_use = 0;
1003         txq->ring_size = nb_desc;
1004
1005         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1006                                           sizeof(struct ena_tx_buffer) *
1007                                           txq->ring_size,
1008                                           RTE_CACHE_LINE_SIZE);
1009         if (!txq->tx_buffer_info) {
1010                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1011                 return -ENOMEM;
1012         }
1013
1014         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1015                                          sizeof(u16) * txq->ring_size,
1016                                          RTE_CACHE_LINE_SIZE);
1017         if (!txq->empty_tx_reqs) {
1018                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1019                 rte_free(txq->tx_buffer_info);
1020                 return -ENOMEM;
1021         }
1022         for (i = 0; i < txq->ring_size; i++)
1023                 txq->empty_tx_reqs[i] = i;
1024
1025         /* Store pointer to this queue in upper layer */
1026         txq->configured = 1;
1027         dev->data->tx_queues[queue_idx] = txq;
1028 err:
1029         return rc;
1030 }
1031
1032 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1033                               uint16_t queue_idx,
1034                               uint16_t nb_desc,
1035                               __rte_unused unsigned int socket_id,
1036                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1037                               struct rte_mempool *mp)
1038 {
1039         struct ena_com_create_io_ctx ctx =
1040                 /* policy set to _HOST just to satisfy icc compiler */
1041                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1042                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1043         struct ena_adapter *adapter =
1044                 (struct ena_adapter *)(dev->data->dev_private);
1045         struct ena_ring *rxq = NULL;
1046         uint16_t ena_qid = 0;
1047         int rc = 0;
1048         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1049
1050         rxq = &adapter->rx_ring[queue_idx];
1051         if (rxq->configured) {
1052                 RTE_LOG(CRIT, PMD,
1053                         "API violation. Queue %d is already configured\n",
1054                         queue_idx);
1055                 return -1;
1056         }
1057
1058         if (nb_desc > adapter->rx_ring_size) {
1059                 RTE_LOG(ERR, PMD,
1060                         "Unsupported size of RX queue (max size: %d)\n",
1061                         adapter->rx_ring_size);
1062                 return -EINVAL;
1063         }
1064
1065         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1066
1067         ctx.qid = ena_qid;
1068         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1069         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1070         ctx.msix_vector = -1; /* admin interrupts not used */
1071         ctx.queue_size = adapter->rx_ring_size;
1072         ctx.numa_node = ena_cpu_to_node(queue_idx);
1073
1074         rc = ena_com_create_io_queue(ena_dev, &ctx);
1075         if (rc)
1076                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1077                         queue_idx, rc);
1078
1079         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1080         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1081
1082         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1083                                      &rxq->ena_com_io_sq,
1084                                      &rxq->ena_com_io_cq);
1085         if (rc) {
1086                 RTE_LOG(ERR, PMD,
1087                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1088                         queue_idx, rc);
1089                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1090         }
1091
1092         rxq->port_id = dev->data->port_id;
1093         rxq->next_to_clean = 0;
1094         rxq->next_to_use = 0;
1095         rxq->ring_size = nb_desc;
1096         rxq->mb_pool = mp;
1097
1098         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1099                                           sizeof(struct rte_mbuf *) * nb_desc,
1100                                           RTE_CACHE_LINE_SIZE);
1101         if (!rxq->rx_buffer_info) {
1102                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1103                 return -ENOMEM;
1104         }
1105
1106         /* Store pointer to this queue in upper layer */
1107         rxq->configured = 1;
1108         dev->data->rx_queues[queue_idx] = rxq;
1109
1110         return rc;
1111 }
1112
1113 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1114 {
1115         unsigned int i;
1116         int rc;
1117         unsigned int ring_size = rxq->ring_size;
1118         unsigned int ring_mask = ring_size - 1;
1119         int next_to_use = rxq->next_to_use & ring_mask;
1120         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1121
1122         if (unlikely(!count))
1123                 return 0;
1124
1125         ena_assert_msg((((ENA_CIRC_COUNT(rxq->next_to_use, rxq->next_to_clean,
1126                                          rxq->ring_size)) +
1127                          count) < rxq->ring_size), "bad ring state");
1128
1129         count = RTE_MIN(count, ring_size - next_to_use);
1130
1131         /* get resources for incoming packets */
1132         rc = rte_mempool_get_bulk(rxq->mb_pool,
1133                                   (void **)(&mbufs[next_to_use]), count);
1134         if (unlikely(rc < 0)) {
1135                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1136                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1137                 return 0;
1138         }
1139
1140         for (i = 0; i < count; i++) {
1141                 struct rte_mbuf *mbuf = mbufs[next_to_use];
1142                 struct ena_com_buf ebuf;
1143
1144                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1145                 /* prepare physical address for DMA transaction */
1146                 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1147                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1148                 /* pass resource to device */
1149                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1150                                                 &ebuf, next_to_use);
1151                 if (unlikely(rc)) {
1152                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1153                         break;
1154                 }
1155                 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, ring_size);
1156         }
1157
1158         /* When we submitted free recources to device... */
1159         if (i > 0) {
1160                 /* ...let HW know that it can fill buffers with data */
1161                 rte_wmb();
1162                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1163
1164                 rxq->next_to_use = next_to_use;
1165         }
1166
1167         return i;
1168 }
1169
1170 static int ena_device_init(struct ena_com_dev *ena_dev,
1171                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1172 {
1173         int rc;
1174         bool readless_supported;
1175
1176         /* Initialize mmio registers */
1177         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1178         if (rc) {
1179                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1180                 return rc;
1181         }
1182
1183         /* The PCIe configuration space revision id indicate if mmio reg
1184          * read is disabled.
1185          */
1186         readless_supported =
1187                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1188                                & ENA_MMIO_DISABLE_REG_READ);
1189         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1190
1191         /* reset device */
1192         rc = ena_com_dev_reset(ena_dev);
1193         if (rc) {
1194                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1195                 goto err_mmio_read_less;
1196         }
1197
1198         /* check FW version */
1199         rc = ena_com_validate_version(ena_dev);
1200         if (rc) {
1201                 RTE_LOG(ERR, PMD, "device version is too low\n");
1202                 goto err_mmio_read_less;
1203         }
1204
1205         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1206
1207         /* ENA device administration layer init */
1208         rc = ena_com_admin_init(ena_dev, NULL, true);
1209         if (rc) {
1210                 RTE_LOG(ERR, PMD,
1211                         "cannot initialize ena admin queue with device\n");
1212                 goto err_mmio_read_less;
1213         }
1214
1215         ena_config_host_info(ena_dev);
1216
1217         /* To enable the msix interrupts the driver needs to know the number
1218          * of queues. So the driver uses polling mode to retrieve this
1219          * information.
1220          */
1221         ena_com_set_admin_polling_mode(ena_dev, true);
1222
1223         /* Get Device Attributes and features */
1224         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1225         if (rc) {
1226                 RTE_LOG(ERR, PMD,
1227                         "cannot get attribute for ena device rc= %d\n", rc);
1228                 goto err_admin_init;
1229         }
1230
1231         return 0;
1232
1233 err_admin_init:
1234         ena_com_admin_destroy(ena_dev);
1235
1236 err_mmio_read_less:
1237         ena_com_mmio_reg_read_request_destroy(ena_dev);
1238
1239         return rc;
1240 }
1241
1242 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1243 {
1244         struct rte_pci_device *pci_dev;
1245         struct ena_adapter *adapter =
1246                 (struct ena_adapter *)(eth_dev->data->dev_private);
1247         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1248         struct ena_com_dev_get_features_ctx get_feat_ctx;
1249         int queue_size, rc;
1250
1251         static int adapters_found;
1252
1253         memset(adapter, 0, sizeof(struct ena_adapter));
1254         ena_dev = &adapter->ena_dev;
1255
1256         eth_dev->dev_ops = &ena_dev_ops;
1257         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1258         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1259         adapter->rte_eth_dev_data = eth_dev->data;
1260         adapter->rte_dev = eth_dev;
1261
1262         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1263                 return 0;
1264
1265         pci_dev = eth_dev->pci_dev;
1266         adapter->pdev = pci_dev;
1267
1268         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1269                      pci_dev->addr.domain,
1270                      pci_dev->addr.bus,
1271                      pci_dev->addr.devid,
1272                      pci_dev->addr.function);
1273
1274         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1275         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1276
1277         /* Present ENA_MEM_BAR indicates available LLQ mode.
1278          * Use corresponding policy
1279          */
1280         if (adapter->dev_mem_base)
1281                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1282         else if (adapter->regs)
1283                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1284         else
1285                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1286                              ENA_REGS_BAR);
1287
1288         ena_dev->reg_bar = adapter->regs;
1289         ena_dev->dmadev = adapter->pdev;
1290
1291         adapter->id_number = adapters_found;
1292
1293         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1294                  adapter->id_number);
1295
1296         /* device specific initialization routine */
1297         rc = ena_device_init(ena_dev, &get_feat_ctx);
1298         if (rc) {
1299                 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1300                 return -1;
1301         }
1302
1303         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1304                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1305                         PMD_INIT_LOG(ERR,
1306                                      "Trying to use LLQ but llq_num is 0.\n"
1307                                      "Fall back into regular queues.\n");
1308                         ena_dev->tx_mem_queue_type =
1309                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1310                         adapter->num_queues =
1311                                 get_feat_ctx.max_queues.max_sq_num;
1312                 } else {
1313                         adapter->num_queues =
1314                                 get_feat_ctx.max_queues.max_llq_num;
1315                 }
1316         } else {
1317                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1318         }
1319
1320         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1321         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1322                 return -EFAULT;
1323
1324         adapter->tx_ring_size = queue_size;
1325         adapter->rx_ring_size = queue_size;
1326
1327         /* prepare ring structures */
1328         ena_init_rings(adapter);
1329
1330         ena_config_debug_area(adapter);
1331
1332         /* Set max MTU for this device */
1333         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1334
1335         /* Copy MAC address and point DPDK to it */
1336         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1337         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1338                         (struct ether_addr *)adapter->mac_addr);
1339
1340         adapter->drv_stats = rte_zmalloc("adapter stats",
1341                                          sizeof(*adapter->drv_stats),
1342                                          RTE_CACHE_LINE_SIZE);
1343         if (!adapter->drv_stats) {
1344                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1345                 return -ENOMEM;
1346         }
1347
1348         adapters_found++;
1349         adapter->state = ENA_ADAPTER_STATE_INIT;
1350
1351         return 0;
1352 }
1353
1354 static int ena_dev_configure(struct rte_eth_dev *dev)
1355 {
1356         struct ena_adapter *adapter =
1357                 (struct ena_adapter *)(dev->data->dev_private);
1358
1359         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1360               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1361                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1362                              adapter->state);
1363                 return -1;
1364         }
1365
1366         switch (adapter->state) {
1367         case ENA_ADAPTER_STATE_INIT:
1368         case ENA_ADAPTER_STATE_STOPPED:
1369                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1370                 break;
1371         case ENA_ADAPTER_STATE_CONFIG:
1372                 RTE_LOG(WARNING, PMD,
1373                         "Ivalid driver state while trying to configure device\n");
1374                 break;
1375         default:
1376                 break;
1377         }
1378
1379         return 0;
1380 }
1381
1382 static void ena_init_rings(struct ena_adapter *adapter)
1383 {
1384         int i;
1385
1386         for (i = 0; i < adapter->num_queues; i++) {
1387                 struct ena_ring *ring = &adapter->tx_ring[i];
1388
1389                 ring->configured = 0;
1390                 ring->type = ENA_RING_TYPE_TX;
1391                 ring->adapter = adapter;
1392                 ring->id = i;
1393                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1394                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1395         }
1396
1397         for (i = 0; i < adapter->num_queues; i++) {
1398                 struct ena_ring *ring = &adapter->rx_ring[i];
1399
1400                 ring->configured = 0;
1401                 ring->type = ENA_RING_TYPE_RX;
1402                 ring->adapter = adapter;
1403                 ring->id = i;
1404         }
1405 }
1406
1407 static void ena_infos_get(struct rte_eth_dev *dev,
1408                           struct rte_eth_dev_info *dev_info)
1409 {
1410         struct ena_adapter *adapter;
1411         struct ena_com_dev *ena_dev;
1412         struct ena_com_dev_get_features_ctx feat;
1413         uint32_t rx_feat = 0, tx_feat = 0;
1414         int rc = 0;
1415
1416         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1417         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1418         adapter = (struct ena_adapter *)(dev->data->dev_private);
1419
1420         ena_dev = &adapter->ena_dev;
1421         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1422
1423         dev_info->speed_capa =
1424                         ETH_LINK_SPEED_1G   |
1425                         ETH_LINK_SPEED_2_5G |
1426                         ETH_LINK_SPEED_5G   |
1427                         ETH_LINK_SPEED_10G  |
1428                         ETH_LINK_SPEED_25G  |
1429                         ETH_LINK_SPEED_40G  |
1430                         ETH_LINK_SPEED_50G  |
1431                         ETH_LINK_SPEED_100G;
1432
1433         /* Get supported features from HW */
1434         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1435         if (unlikely(rc)) {
1436                 RTE_LOG(ERR, PMD,
1437                         "Cannot get attribute for ena device rc= %d\n", rc);
1438                 return;
1439         }
1440
1441         /* Set Tx & Rx features available for device */
1442         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1443                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1444
1445         if (feat.offload.tx &
1446             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1447                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1448                         DEV_TX_OFFLOAD_UDP_CKSUM |
1449                         DEV_TX_OFFLOAD_TCP_CKSUM;
1450
1451         if (feat.offload.tx &
1452             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1453                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1454                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1455                         DEV_RX_OFFLOAD_TCP_CKSUM;
1456
1457         /* Inform framework about available features */
1458         dev_info->rx_offload_capa = rx_feat;
1459         dev_info->tx_offload_capa = tx_feat;
1460
1461         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1462         dev_info->max_rx_pktlen  = adapter->max_mtu;
1463         dev_info->max_mac_addrs = 1;
1464
1465         dev_info->max_rx_queues = adapter->num_queues;
1466         dev_info->max_tx_queues = adapter->num_queues;
1467         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1468 }
1469
1470 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1471                                   uint16_t nb_pkts)
1472 {
1473         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1474         unsigned int ring_size = rx_ring->ring_size;
1475         unsigned int ring_mask = ring_size - 1;
1476         uint16_t next_to_clean = rx_ring->next_to_clean;
1477         int desc_in_use = 0;
1478         unsigned int recv_idx = 0;
1479         struct rte_mbuf *mbuf = NULL;
1480         struct rte_mbuf *mbuf_head = NULL;
1481         struct rte_mbuf *mbuf_prev = NULL;
1482         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1483         unsigned int completed;
1484
1485         struct ena_com_rx_ctx ena_rx_ctx;
1486         int rc = 0;
1487
1488         /* Check adapter state */
1489         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1490                 RTE_LOG(ALERT, PMD,
1491                         "Trying to receive pkts while device is NOT running\n");
1492                 return 0;
1493         }
1494
1495         desc_in_use = ENA_CIRC_COUNT(rx_ring->next_to_use,
1496                                      next_to_clean, ring_size);
1497         if (unlikely(nb_pkts > desc_in_use))
1498                 nb_pkts = desc_in_use;
1499
1500         for (completed = 0; completed < nb_pkts; completed++) {
1501                 int segments = 0;
1502
1503                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1504                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1505                 ena_rx_ctx.descs = 0;
1506                 /* receive packet context */
1507                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1508                                     rx_ring->ena_com_io_sq,
1509                                     &ena_rx_ctx);
1510                 if (unlikely(rc)) {
1511                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1512                         return 0;
1513                 }
1514
1515                 if (unlikely(ena_rx_ctx.descs == 0))
1516                         break;
1517
1518                 while (segments < ena_rx_ctx.descs) {
1519                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1520                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1521                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1522                         mbuf->refcnt = 1;
1523                         mbuf->next = NULL;
1524                         if (segments == 0) {
1525                                 mbuf->nb_segs = ena_rx_ctx.descs;
1526                                 mbuf->port = rx_ring->port_id;
1527                                 mbuf->pkt_len = 0;
1528                                 mbuf_head = mbuf;
1529                         } else {
1530                                 /* for multi-segment pkts create mbuf chain */
1531                                 mbuf_prev->next = mbuf;
1532                         }
1533                         mbuf_head->pkt_len += mbuf->data_len;
1534
1535                         mbuf_prev = mbuf;
1536                         segments++;
1537                         next_to_clean =
1538                                 ENA_RX_RING_IDX_NEXT(next_to_clean, ring_size);
1539                 }
1540
1541                 /* fill mbuf attributes if any */
1542                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1543                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1544
1545                 /* pass to DPDK application head mbuf */
1546                 rx_pkts[recv_idx] = mbuf_head;
1547                 recv_idx++;
1548         }
1549
1550         /* Burst refill to save doorbells, memory barriers, const interval */
1551         if (ring_size - desc_in_use - 1 > ENA_RING_DESCS_RATIO(ring_size))
1552                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use - 1);
1553
1554         rx_ring->next_to_clean = next_to_clean & ring_mask;
1555
1556         return recv_idx;
1557 }
1558
1559 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1560                                   uint16_t nb_pkts)
1561 {
1562         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1563         unsigned int next_to_use = tx_ring->next_to_use;
1564         struct rte_mbuf *mbuf;
1565         unsigned int ring_size = tx_ring->ring_size;
1566         unsigned int ring_mask = ring_size - 1;
1567         struct ena_com_tx_ctx ena_tx_ctx;
1568         struct ena_tx_buffer *tx_info;
1569         struct ena_com_buf *ebuf;
1570         uint16_t rc, req_id, total_tx_descs = 0;
1571         uint16_t sent_idx = 0;
1572         int nb_hw_desc;
1573
1574         /* Check adapter state */
1575         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1576                 RTE_LOG(ALERT, PMD,
1577                         "Trying to xmit pkts while device is NOT running\n");
1578                 return 0;
1579         }
1580
1581         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1582                 mbuf = tx_pkts[sent_idx];
1583
1584                 req_id = tx_ring->empty_tx_reqs[next_to_use];
1585                 tx_info = &tx_ring->tx_buffer_info[req_id];
1586                 tx_info->mbuf = mbuf;
1587                 tx_info->num_of_bufs = 0;
1588                 ebuf = tx_info->bufs;
1589
1590                 /* Prepare TX context */
1591                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1592                 memset(&ena_tx_ctx.ena_meta, 0x0,
1593                        sizeof(struct ena_com_tx_meta));
1594                 ena_tx_ctx.ena_bufs = ebuf;
1595                 ena_tx_ctx.req_id = req_id;
1596                 if (tx_ring->tx_mem_queue_type ==
1597                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1598                         /* prepare the push buffer with
1599                          * virtual address of the data
1600                          */
1601                         ena_tx_ctx.header_len =
1602                                 RTE_MIN(mbuf->data_len,
1603                                         tx_ring->tx_max_header_size);
1604                         ena_tx_ctx.push_header =
1605                                 (void *)((char *)mbuf->buf_addr +
1606                                          mbuf->data_off);
1607                 } /* there's no else as we take advantage of memset zeroing */
1608
1609                 /* Set TX offloads flags, if applicable */
1610                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1611
1612                 if (unlikely(mbuf->ol_flags &
1613                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1614                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1615
1616                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1617
1618                 /* Process first segment taking into
1619                  * consideration pushed header
1620                  */
1621                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1622                         ebuf->paddr = mbuf->buf_physaddr +
1623                                       mbuf->data_off +
1624                                       ena_tx_ctx.header_len;
1625                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1626                         ebuf++;
1627                         tx_info->num_of_bufs++;
1628                 }
1629
1630                 while ((mbuf = mbuf->next) != NULL) {
1631                         ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1632                         ebuf->len = mbuf->data_len;
1633                         ebuf++;
1634                         tx_info->num_of_bufs++;
1635                 }
1636
1637                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1638
1639                 /* Write data to device */
1640                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1641                                         &ena_tx_ctx, &nb_hw_desc);
1642                 if (unlikely(rc))
1643                         break;
1644
1645                 tx_info->tx_descs = nb_hw_desc;
1646
1647                 next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, ring_size);
1648         }
1649
1650         /* If there are ready packets to be xmitted... */
1651         if (sent_idx > 0) {
1652                 /* ...let HW do its best :-) */
1653                 rte_wmb();
1654                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1655
1656                 tx_ring->next_to_use = next_to_use;
1657         }
1658
1659         /* Clear complete packets  */
1660         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1661                 /* Get Tx info & store how many descs were processed  */
1662                 tx_info = &tx_ring->tx_buffer_info[req_id];
1663                 total_tx_descs += tx_info->tx_descs;
1664
1665                 /* Free whole mbuf chain  */
1666                 mbuf = tx_info->mbuf;
1667                 rte_pktmbuf_free(mbuf);
1668
1669                 /* Put back descriptor to the ring for reuse */
1670                 tx_ring->empty_tx_reqs[tx_ring->next_to_clean] = req_id;
1671                 tx_ring->next_to_clean =
1672                         ENA_TX_RING_IDX_NEXT(tx_ring->next_to_clean,
1673                                              tx_ring->ring_size);
1674
1675                 /* If too many descs to clean, leave it for another run */
1676                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1677                         break;
1678         }
1679
1680         if (total_tx_descs > 0) {
1681                 /* acknowledge completion of sent packets */
1682                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1683         }
1684
1685         return sent_idx;
1686 }
1687
1688 static struct eth_driver rte_ena_pmd = {
1689         {
1690                 .name = "rte_ena_pmd",
1691                 .id_table = pci_id_ena_map,
1692                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1693         },
1694         .eth_dev_init = eth_ena_dev_init,
1695         .dev_private_size = sizeof(struct ena_adapter),
1696 };
1697
1698 static int
1699 rte_ena_pmd_init(const char *name __rte_unused,
1700                  const char *params __rte_unused)
1701 {
1702         rte_eth_driver_register(&rte_ena_pmd);
1703         return 0;
1704 };
1705
1706 struct rte_driver ena_pmd_drv = {
1707         .type = PMD_PDEV,
1708         .init = rte_ena_pmd_init,
1709 };
1710
1711 PMD_REGISTER_DRIVER(ena_pmd_drv, ena);
1712 DRIVER_REGISTER_PCI_TABLE(ena, pci_id_ena_map);