drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IP_CKSUM |        \
 193         PKT_TX_TCP_SEG)
 194
 195 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 196         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 197
 198 int ena_logtype_init;
 199 int ena_logtype_driver;
 200
 201 static const struct rte_pci_id pci_id_ena_map[] = {
 202         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 203         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 204         { .device_id = 0 },
 205 };
 206
 207 static struct ena_aenq_handlers aenq_handlers;
 208
 209 static int ena_device_init(struct ena_com_dev *ena_dev,
 210                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 211                            bool *wd_state);
 212 static int ena_dev_configure(struct rte_eth_dev *dev);
 213 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 214                                   uint16_t nb_pkts);
 215 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                 uint16_t nb_pkts);
 217 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 218                               uint16_t nb_desc, unsigned int socket_id,
 219                               const struct rte_eth_txconf *tx_conf);
 220 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 221                               uint16_t nb_desc, unsigned int socket_id,
 222                               const struct rte_eth_rxconf *rx_conf,
 223                               struct rte_mempool *mp);
 224 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 225                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 226 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 227 static void ena_init_rings(struct ena_adapter *adapter);
 228 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 229 static int ena_start(struct rte_eth_dev *dev);
 230 static void ena_stop(struct rte_eth_dev *dev);
 231 static void ena_close(struct rte_eth_dev *dev);
 232 static int ena_dev_reset(struct rte_eth_dev *dev);
 233 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 234 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 235 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 236 static void ena_rx_queue_release(void *queue);
 237 static void ena_tx_queue_release(void *queue);
 238 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 239 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 240 static int ena_link_update(struct rte_eth_dev *dev,
 241                            int wait_to_complete);
 242 static int ena_queue_restart(struct ena_ring *ring);
 243 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 244                                  enum ena_ring_type ring_type);
 245 static void ena_stats_restart(struct rte_eth_dev *dev);
 246 static void ena_infos_get(struct rte_eth_dev *dev,
 247                           struct rte_eth_dev_info *dev_info);
 248 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 249                                struct rte_eth_rss_reta_entry64 *reta_conf,
 250                                uint16_t reta_size);
 251 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 252                               struct rte_eth_rss_reta_entry64 *reta_conf,
 253                               uint16_t reta_size);
 254 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 255 static void ena_interrupt_handler_rte(void *cb_arg);
 256 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 257
 258 static const struct eth_dev_ops ena_dev_ops = {
 259         .dev_configure        = ena_dev_configure,
 260         .dev_infos_get        = ena_infos_get,
 261         .rx_queue_setup       = ena_rx_queue_setup,
 262         .tx_queue_setup       = ena_tx_queue_setup,
 263         .dev_start            = ena_start,
 264         .dev_stop             = ena_stop,
 265         .link_update          = ena_link_update,
 266         .stats_get            = ena_stats_get,
 267         .mtu_set              = ena_mtu_set,
 268         .rx_queue_release     = ena_rx_queue_release,
 269         .tx_queue_release     = ena_tx_queue_release,
 270         .dev_close            = ena_close,
 271         .dev_reset            = ena_dev_reset,
 272         .reta_update          = ena_rss_reta_update,
 273         .reta_query           = ena_rss_reta_query,
 274 };
 275
 276 #define NUMA_NO_NODE    SOCKET_ID_ANY
 277
 278 static inline int ena_cpu_to_node(int cpu)
 279 {
 280         struct rte_config *config = rte_eal_get_configuration();
 281         struct rte_fbarray *arr = &config->mem_config->memzones;
 282         const struct rte_memzone *mz;
 283
 284         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 285                 return NUMA_NO_NODE;
 286
 287         mz = rte_fbarray_get(arr, cpu);
 288
 289         return mz->socket_id;
 290 }
 291
 292 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 293                                        struct ena_com_rx_ctx *ena_rx_ctx)
 294 {
 295         uint64_t ol_flags = 0;
 296         uint32_t packet_type = 0;
 297
 298         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 299                 packet_type |= RTE_PTYPE_L4_TCP;
 300         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 301                 packet_type |= RTE_PTYPE_L4_UDP;
 302
 303         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 304                 packet_type |= RTE_PTYPE_L3_IPV4;
 305         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 306                 packet_type |= RTE_PTYPE_L3_IPV6;
 307
 308         if (unlikely(ena_rx_ctx->l4_csum_err))
 309                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 310         if (unlikely(ena_rx_ctx->l3_csum_err))
 311                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 312
 313         mbuf->ol_flags = ol_flags;
 314         mbuf->packet_type = packet_type;
 315 }
 316
 317 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 318                                        struct ena_com_tx_ctx *ena_tx_ctx,
 319                                        uint64_t queue_offloads)
 320 {
 321         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 322
 323         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 324             (queue_offloads & QUEUE_OFFLOADS)) {
 325                 /* check if TSO is required */
 326                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 327                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 328                         ena_tx_ctx->tso_enable = true;
 329
 330                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 331                 }
 332
 333                 /* check if L3 checksum is needed */
 334                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 335                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 336                         ena_tx_ctx->l3_csum_enable = true;
 337
 338                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 339                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 340                 } else {
 341                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 342
 343                         /* set don't fragment (DF) flag */
 344                         if (mbuf->packet_type &
 345                                 (RTE_PTYPE_L4_NONFRAG
 346                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 347                                 ena_tx_ctx->df = true;
 348                 }
 349
 350                 /* check if L4 checksum is needed */
 351                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 352                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 356                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else {
 360                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 361                         ena_tx_ctx->l4_csum_enable = false;
 362                 }
 363
 364                 ena_meta->mss = mbuf->tso_segsz;
 365                 ena_meta->l3_hdr_len = mbuf->l3_len;
 366                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 367
 368                 ena_tx_ctx->meta_valid = true;
 369         } else {
 370                 ena_tx_ctx->meta_valid = false;
 371         }
 372 }
 373
 374 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 375 {
 376         if (likely(req_id < rx_ring->ring_size))
 377                 return 0;
 378
 379         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 380
 381         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 382         rx_ring->adapter->trigger_reset = true;
 383
 384         return -EFAULT;
 385 }
 386
 387 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 388 {
 389         struct ena_admin_host_info *host_info;
 390         int rc;
 391
 392         /* Allocate only the host info */
 393         rc = ena_com_allocate_host_info(ena_dev);
 394         if (rc) {
 395                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 396                 return;
 397         }
 398
 399         host_info = ena_dev->host_attr.host_info;
 400
 401         host_info->os_type = ENA_ADMIN_OS_DPDK;
 402         host_info->kernel_ver = RTE_VERSION;
 403         snprintf((char *)host_info->kernel_ver_str,
 404                  sizeof(host_info->kernel_ver_str),
 405                  "%s", rte_version());
 406         host_info->os_dist = RTE_VERSION;
 407         snprintf((char *)host_info->os_dist_str,
 408                  sizeof(host_info->os_dist_str),
 409                  "%s", rte_version());
 410         host_info->driver_version =
 411                 (DRV_MODULE_VER_MAJOR) |
 412                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 413                 (DRV_MODULE_VER_SUBMINOR <<
 414                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 415
 416         rc = ena_com_set_host_attributes(ena_dev);
 417         if (rc) {
 418                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 419                 if (rc != -ENA_COM_UNSUPPORTED)
 420                         goto err;
 421         }
 422
 423         return;
 424
 425 err:
 426         ena_com_delete_host_info(ena_dev);
 427 }
 428
 429 static int
 430 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 431 {
 432         if (sset != ETH_SS_STATS)
 433                 return -EOPNOTSUPP;
 434
 435          /* Workaround for clang:
 436          * touch internal structures to prevent
 437          * compiler error
 438          */
 439         ENA_TOUCH(ena_stats_global_strings);
 440         ENA_TOUCH(ena_stats_tx_strings);
 441         ENA_TOUCH(ena_stats_rx_strings);
 442         ENA_TOUCH(ena_stats_ena_com_strings);
 443
 444         return  dev->data->nb_tx_queues *
 445                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 446                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 447 }
 448
 449 static void ena_config_debug_area(struct ena_adapter *adapter)
 450 {
 451         u32 debug_area_size;
 452         int rc, ss_count;
 453
 454         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 455         if (ss_count <= 0) {
 456                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 457                 return;
 458         }
 459
 460         /* allocate 32 bytes for each string and 64bit for the value */
 461         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 462
 463         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 464         if (rc) {
 465                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 466                 return;
 467         }
 468
 469         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 470         if (rc) {
 471                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 472                 if (rc != -ENA_COM_UNSUPPORTED)
 473                         goto err;
 474         }
 475
 476         return;
 477 err:
 478         ena_com_delete_debug_area(&adapter->ena_dev);
 479 }
 480
 481 static void ena_close(struct rte_eth_dev *dev)
 482 {
 483         struct ena_adapter *adapter =
 484                 (struct ena_adapter *)(dev->data->dev_private);
 485
 486         ena_stop(dev);
 487         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 488
 489         ena_rx_queue_release_all(dev);
 490         ena_tx_queue_release_all(dev);
 491 }
 492
 493 static int
 494 ena_dev_reset(struct rte_eth_dev *dev)
 495 {
 496         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 497         struct rte_eth_dev *eth_dev;
 498         struct rte_pci_device *pci_dev;
 499         struct rte_intr_handle *intr_handle;
 500         struct ena_com_dev *ena_dev;
 501         struct ena_com_dev_get_features_ctx get_feat_ctx;
 502         struct ena_adapter *adapter;
 503         int nb_queues;
 504         int rc, i;
 505         bool wd_state;
 506
 507         adapter = (struct ena_adapter *)(dev->data->dev_private);
 508         ena_dev = &adapter->ena_dev;
 509         eth_dev = adapter->rte_dev;
 510         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 511         intr_handle = &pci_dev->intr_handle;
 512         nb_queues = eth_dev->data->nb_rx_queues;
 513
 514         ena_com_set_admin_running_state(ena_dev, false);
 515
 516         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 517
 518         for (i = 0; i < nb_queues; i++)
 519                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 520
 521         ena_rx_queue_release_all(eth_dev);
 522         ena_tx_queue_release_all(eth_dev);
 523
 524         rte_intr_disable(intr_handle);
 525
 526         ena_com_abort_admin_commands(ena_dev);
 527         ena_com_wait_for_abort_completion(ena_dev);
 528         ena_com_admin_destroy(ena_dev);
 529         ena_com_mmio_reg_read_request_destroy(ena_dev);
 530
 531         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 532         if (rc) {
 533                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 534                 return rc;
 535         }
 536         adapter->wd_state = wd_state;
 537
 538         rte_intr_enable(intr_handle);
 539         ena_com_set_admin_polling_mode(ena_dev, false);
 540         ena_com_admin_aenq_enable(ena_dev);
 541
 542         for (i = 0; i < nb_queues; ++i)
 543                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 544                         mb_pool_rx[i]);
 545
 546         for (i = 0; i < nb_queues; ++i)
 547                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 548
 549         adapter->trigger_reset = false;
 550
 551         return 0;
 552 }
 553
 554 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 555                                struct rte_eth_rss_reta_entry64 *reta_conf,
 556                                uint16_t reta_size)
 557 {
 558         struct ena_adapter *adapter =
 559                 (struct ena_adapter *)(dev->data->dev_private);
 560         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 561         int ret, i;
 562         u16 entry_value;
 563         int conf_idx;
 564         int idx;
 565
 566         if ((reta_size == 0) || (reta_conf == NULL))
 567                 return -EINVAL;
 568
 569         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 570                 RTE_LOG(WARNING, PMD,
 571                         "indirection table %d is bigger than supported (%d)\n",
 572                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 573                 ret = -EINVAL;
 574                 goto err;
 575         }
 576
 577         for (i = 0 ; i < reta_size ; i++) {
 578                 /* each reta_conf is for 64 entries.
 579                  * to support 128 we use 2 conf of 64
 580                  */
 581                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 582                 idx = i % RTE_RETA_GROUP_SIZE;
 583                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 584                         entry_value =
 585                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 586                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 587                                                                 i,
 588                                                                 entry_value);
 589                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 590                                 RTE_LOG(ERR, PMD,
 591                                         "Cannot fill indirect table\n");
 592                                 ret = -ENOTSUP;
 593                                 goto err;
 594                         }
 595                 }
 596         }
 597
 598         ret = ena_com_indirect_table_set(ena_dev);
 599         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 600                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 601                 ret = -ENOTSUP;
 602                 goto err;
 603         }
 604
 605         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 606                 __func__, reta_size, adapter->rte_dev->data->port_id);
 607 err:
 608         return ret;
 609 }
 610
 611 /* Query redirection table. */
 612 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 613                               struct rte_eth_rss_reta_entry64 *reta_conf,
 614                               uint16_t reta_size)
 615 {
 616         struct ena_adapter *adapter =
 617                 (struct ena_adapter *)(dev->data->dev_private);
 618         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 619         int ret;
 620         int i;
 621         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 622         int reta_conf_idx;
 623         int reta_idx;
 624
 625         if (reta_size == 0 || reta_conf == NULL ||
 626             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 627                 return -EINVAL;
 628
 629         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 630         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 631                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 632                 ret = -ENOTSUP;
 633                 goto err;
 634         }
 635
 636         for (i = 0 ; i < reta_size ; i++) {
 637                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 638                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 639                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 640                         reta_conf[reta_conf_idx].reta[reta_idx] =
 641                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 642         }
 643 err:
 644         return ret;
 645 }
 646
 647 static int ena_rss_init_default(struct ena_adapter *adapter)
 648 {
 649         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 650         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 651         int rc, i;
 652         u32 val;
 653
 654         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 655         if (unlikely(rc)) {
 656                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 657                 goto err_rss_init;
 658         }
 659
 660         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 661                 val = i % nb_rx_queues;
 662                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 663                                                        ENA_IO_RXQ_IDX(val));
 664                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 665                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 666                         goto err_fill_indir;
 667                 }
 668         }
 669
 670         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 671                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 672         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 673                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 674                 goto err_fill_indir;
 675         }
 676
 677         rc = ena_com_set_default_hash_ctrl(ena_dev);
 678         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 679                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 680                 goto err_fill_indir;
 681         }
 682
 683         rc = ena_com_indirect_table_set(ena_dev);
 684         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 685                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 686                 goto err_fill_indir;
 687         }
 688         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 689                 adapter->rte_dev->data->port_id);
 690
 691         return 0;
 692
 693 err_fill_indir:
 694         ena_com_rss_destroy(ena_dev);
 695 err_rss_init:
 696
 697         return rc;
 698 }
 699
 700 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 701 {
 702         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 703         int nb_queues = dev->data->nb_rx_queues;
 704         int i;
 705
 706         for (i = 0; i < nb_queues; i++)
 707                 ena_rx_queue_release(queues[i]);
 708 }
 709
 710 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 711 {
 712         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 713         int nb_queues = dev->data->nb_tx_queues;
 714         int i;
 715
 716         for (i = 0; i < nb_queues; i++)
 717                 ena_tx_queue_release(queues[i]);
 718 }
 719
 720 static void ena_rx_queue_release(void *queue)
 721 {
 722         struct ena_ring *ring = (struct ena_ring *)queue;
 723         struct ena_adapter *adapter = ring->adapter;
 724         int ena_qid;
 725
 726         ena_assert_msg(ring->configured,
 727                        "API violation - releasing not configured queue");
 728         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 729                        "API violation");
 730
 731         /* Destroy HW queue */
 732         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 733         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 734
 735         /* Free all bufs */
 736         ena_rx_queue_release_bufs(ring);
 737
 738         /* Free ring resources */
 739         if (ring->rx_buffer_info)
 740                 rte_free(ring->rx_buffer_info);
 741         ring->rx_buffer_info = NULL;
 742
 743         if (ring->empty_rx_reqs)
 744                 rte_free(ring->empty_rx_reqs);
 745         ring->empty_rx_reqs = NULL;
 746
 747         ring->configured = 0;
 748
 749         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 750                 ring->port_id, ring->id);
 751 }
 752
 753 static void ena_tx_queue_release(void *queue)
 754 {
 755         struct ena_ring *ring = (struct ena_ring *)queue;
 756         struct ena_adapter *adapter = ring->adapter;
 757         int ena_qid;
 758
 759         ena_assert_msg(ring->configured,
 760                        "API violation. Releasing not configured queue");
 761         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 762                        "API violation");
 763
 764         /* Destroy HW queue */
 765         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 766         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 767
 768         /* Free all bufs */
 769         ena_tx_queue_release_bufs(ring);
 770
 771         /* Free ring resources */
 772         if (ring->tx_buffer_info)
 773                 rte_free(ring->tx_buffer_info);
 774
 775         if (ring->empty_tx_reqs)
 776                 rte_free(ring->empty_tx_reqs);
 777
 778         ring->empty_tx_reqs = NULL;
 779         ring->tx_buffer_info = NULL;
 780
 781         ring->configured = 0;
 782
 783         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 784                 ring->port_id, ring->id);
 785 }
 786
 787 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 788 {
 789         unsigned int ring_mask = ring->ring_size - 1;
 790
 791         while (ring->next_to_clean != ring->next_to_use) {
 792                 struct rte_mbuf *m =
 793                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 794
 795                 if (m)
 796                         rte_mbuf_raw_free(m);
 797
 798                 ring->next_to_clean++;
 799         }
 800 }
 801
 802 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 803 {
 804         unsigned int i;
 805
 806         for (i = 0; i < ring->ring_size; ++i) {
 807                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 808
 809                 if (tx_buf->mbuf)
 810                         rte_pktmbuf_free(tx_buf->mbuf);
 811
 812                 ring->next_to_clean++;
 813         }
 814 }
 815
 816 static int ena_link_update(struct rte_eth_dev *dev,
 817                            __rte_unused int wait_to_complete)
 818 {
 819         struct rte_eth_link *link = &dev->data->dev_link;
 820         struct ena_adapter *adapter;
 821
 822         adapter = (struct ena_adapter *)(dev->data->dev_private);
 823
 824         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 825         link->link_speed = ETH_SPEED_NUM_10G;
 826         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 827
 828         return 0;
 829 }
 830
 831 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 832                                  enum ena_ring_type ring_type)
 833 {
 834         struct ena_adapter *adapter =
 835                 (struct ena_adapter *)(dev->data->dev_private);
 836         struct ena_ring *queues = NULL;
 837         int nb_queues;
 838         int i = 0;
 839         int rc = 0;
 840
 841         if (ring_type == ENA_RING_TYPE_RX) {
 842                 queues = adapter->rx_ring;
 843                 nb_queues = dev->data->nb_rx_queues;
 844         } else {
 845                 queues = adapter->tx_ring;
 846                 nb_queues = dev->data->nb_tx_queues;
 847         }
 848         for (i = 0; i < nb_queues; i++) {
 849                 if (queues[i].configured) {
 850                         if (ring_type == ENA_RING_TYPE_RX) {
 851                                 ena_assert_msg(
 852                                         dev->data->rx_queues[i] == &queues[i],
 853                                         "Inconsistent state of rx queues\n");
 854                         } else {
 855                                 ena_assert_msg(
 856                                         dev->data->tx_queues[i] == &queues[i],
 857                                         "Inconsistent state of tx queues\n");
 858                         }
 859
 860                         rc = ena_queue_restart(&queues[i]);
 861
 862                         if (rc) {
 863                                 PMD_INIT_LOG(ERR,
 864                                              "failed to restart queue %d type(%d)",
 865                                              i, ring_type);
 866                                 return -1;
 867                         }
 868                 }
 869         }
 870
 871         return 0;
 872 }
 873
 874 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 875 {
 876         uint32_t max_frame_len = adapter->max_mtu;
 877
 878         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 879             DEV_RX_OFFLOAD_JUMBO_FRAME)
 880                 max_frame_len =
 881                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 882
 883         return max_frame_len;
 884 }
 885
 886 static int ena_check_valid_conf(struct ena_adapter *adapter)
 887 {
 888         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 889
 890         if (max_frame_len > adapter->max_mtu) {
 891                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 892                 return -1;
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int
 899 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 900                     u16 *max_tx_sgl_size,
 901                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 902 {
 903         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 904
 905         queue_size = RTE_MIN(queue_size,
 906                              get_feat_ctx->max_queues.max_cq_depth);
 907         queue_size = RTE_MIN(queue_size,
 908                              get_feat_ctx->max_queues.max_sq_depth);
 909
 910         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 911                 queue_size = RTE_MIN(queue_size,
 912                                      get_feat_ctx->max_queues.max_llq_depth);
 913
 914         /* Round down to power of 2 */
 915         if (!rte_is_power_of_2(queue_size))
 916                 queue_size = rte_align32pow2(queue_size >> 1);
 917
 918         if (queue_size == 0) {
 919                 PMD_INIT_LOG(ERR, "Invalid queue size");
 920                 return -EFAULT;
 921         }
 922
 923         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 924                 get_feat_ctx->max_queues.max_packet_tx_descs);
 925
 926         return queue_size;
 927 }
 928
 929 static void ena_stats_restart(struct rte_eth_dev *dev)
 930 {
 931         struct ena_adapter *adapter =
 932                 (struct ena_adapter *)(dev->data->dev_private);
 933
 934         rte_atomic64_init(&adapter->drv_stats->ierrors);
 935         rte_atomic64_init(&adapter->drv_stats->oerrors);
 936         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 937 }
 938
 939 static int ena_stats_get(struct rte_eth_dev *dev,
 940                           struct rte_eth_stats *stats)
 941 {
 942         struct ena_admin_basic_stats ena_stats;
 943         struct ena_adapter *adapter =
 944                 (struct ena_adapter *)(dev->data->dev_private);
 945         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 946         int rc;
 947
 948         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 949                 return -ENOTSUP;
 950
 951         memset(&ena_stats, 0, sizeof(ena_stats));
 952         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 953         if (unlikely(rc)) {
 954                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 955                 return rc;
 956         }
 957
 958         /* Set of basic statistics from ENA */
 959         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 960                                           ena_stats.rx_pkts_low);
 961         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 962                                           ena_stats.tx_pkts_low);
 963         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 964                                         ena_stats.rx_bytes_low);
 965         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 966                                         ena_stats.tx_bytes_low);
 967         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 968                                          ena_stats.rx_drops_low);
 969
 970         /* Driver related stats */
 971         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 972         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 973         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 974         return 0;
 975 }
 976
 977 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 978 {
 979         struct ena_adapter *adapter;
 980         struct ena_com_dev *ena_dev;
 981         int rc = 0;
 982
 983         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 984         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 985         adapter = (struct ena_adapter *)(dev->data->dev_private);
 986
 987         ena_dev = &adapter->ena_dev;
 988         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 989
 990         if (mtu > ena_get_mtu_conf(adapter)) {
 991                 RTE_LOG(ERR, PMD,
 992                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 993                         mtu, ena_get_mtu_conf(adapter));
 994                 rc = -EINVAL;
 995                 goto err;
 996         }
 997
 998         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 999         if (rc)
1000                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1001         else
1002                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1003
1004 err:
1005         return rc;
1006 }
1007
1008 static int ena_start(struct rte_eth_dev *dev)
1009 {
1010         struct ena_adapter *adapter =
1011                 (struct ena_adapter *)(dev->data->dev_private);
1012         uint64_t ticks;
1013         int rc = 0;
1014
1015         rc = ena_check_valid_conf(adapter);
1016         if (rc)
1017                 return rc;
1018
1019         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1020         if (rc)
1021                 return rc;
1022
1023         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1024         if (rc)
1025                 return rc;
1026
1027         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1028             ETH_MQ_RX_RSS_FLAG) {
1029                 rc = ena_rss_init_default(adapter);
1030                 if (rc)
1031                         return rc;
1032         }
1033
1034         ena_stats_restart(dev);
1035
1036         adapter->timestamp_wd = rte_get_timer_cycles();
1037         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1038
1039         ticks = rte_get_timer_hz();
1040         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1041                         ena_timer_wd_callback, adapter);
1042
1043         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1044
1045         return 0;
1046 }
1047
1048 static void ena_stop(struct rte_eth_dev *dev)
1049 {
1050         struct ena_adapter *adapter =
1051                 (struct ena_adapter *)(dev->data->dev_private);
1052
1053         rte_timer_stop_sync(&adapter->timer_wd);
1054
1055         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1056 }
1057
1058 static int ena_queue_restart(struct ena_ring *ring)
1059 {
1060         int rc, bufs_num;
1061
1062         ena_assert_msg(ring->configured == 1,
1063                        "Trying to restart unconfigured queue\n");
1064
1065         ring->next_to_clean = 0;
1066         ring->next_to_use = 0;
1067
1068         if (ring->type == ENA_RING_TYPE_TX)
1069                 return 0;
1070
1071         bufs_num = ring->ring_size - 1;
1072         rc = ena_populate_rx_queue(ring, bufs_num);
1073         if (rc != bufs_num) {
1074                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1075                 return (-1);
1076         }
1077
1078         return 0;
1079 }
1080
1081 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1082                               uint16_t queue_idx,
1083                               uint16_t nb_desc,
1084                               __rte_unused unsigned int socket_id,
1085                               const struct rte_eth_txconf *tx_conf)
1086 {
1087         struct ena_com_create_io_ctx ctx =
1088                 /* policy set to _HOST just to satisfy icc compiler */
1089                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1090                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1091         struct ena_ring *txq = NULL;
1092         struct ena_adapter *adapter =
1093                 (struct ena_adapter *)(dev->data->dev_private);
1094         unsigned int i;
1095         int ena_qid;
1096         int rc;
1097         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1098
1099         txq = &adapter->tx_ring[queue_idx];
1100
1101         if (txq->configured) {
1102                 RTE_LOG(CRIT, PMD,
1103                         "API violation. Queue %d is already configured\n",
1104                         queue_idx);
1105                 return -1;
1106         }
1107
1108         if (!rte_is_power_of_2(nb_desc)) {
1109                 RTE_LOG(ERR, PMD,
1110                         "Unsupported size of RX queue: %d is not a power of 2.",
1111                         nb_desc);
1112                 return -EINVAL;
1113         }
1114
1115         if (nb_desc > adapter->tx_ring_size) {
1116                 RTE_LOG(ERR, PMD,
1117                         "Unsupported size of TX queue (max size: %d)\n",
1118                         adapter->tx_ring_size);
1119                 return -EINVAL;
1120         }
1121
1122         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1123
1124         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1125         ctx.qid = ena_qid;
1126         ctx.msix_vector = -1; /* admin interrupts not used */
1127         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1128         ctx.queue_size = adapter->tx_ring_size;
1129         ctx.numa_node = ena_cpu_to_node(queue_idx);
1130
1131         rc = ena_com_create_io_queue(ena_dev, &ctx);
1132         if (rc) {
1133                 RTE_LOG(ERR, PMD,
1134                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1135                         queue_idx, ena_qid, rc);
1136         }
1137         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1138         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1139
1140         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1141                                      &txq->ena_com_io_sq,
1142                                      &txq->ena_com_io_cq);
1143         if (rc) {
1144                 RTE_LOG(ERR, PMD,
1145                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1146                         queue_idx, rc);
1147                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1148                 goto err;
1149         }
1150
1151         txq->port_id = dev->data->port_id;
1152         txq->next_to_clean = 0;
1153         txq->next_to_use = 0;
1154         txq->ring_size = nb_desc;
1155
1156         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1157                                           sizeof(struct ena_tx_buffer) *
1158                                           txq->ring_size,
1159                                           RTE_CACHE_LINE_SIZE);
1160         if (!txq->tx_buffer_info) {
1161                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1162                 return -ENOMEM;
1163         }
1164
1165         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1166                                          sizeof(u16) * txq->ring_size,
1167                                          RTE_CACHE_LINE_SIZE);
1168         if (!txq->empty_tx_reqs) {
1169                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1170                 rte_free(txq->tx_buffer_info);
1171                 return -ENOMEM;
1172         }
1173         for (i = 0; i < txq->ring_size; i++)
1174                 txq->empty_tx_reqs[i] = i;
1175
1176         if (tx_conf != NULL) {
1177                 txq->offloads =
1178                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1179         }
1180
1181         /* Store pointer to this queue in upper layer */
1182         txq->configured = 1;
1183         dev->data->tx_queues[queue_idx] = txq;
1184 err:
1185         return rc;
1186 }
1187
1188 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1189                               uint16_t queue_idx,
1190                               uint16_t nb_desc,
1191                               __rte_unused unsigned int socket_id,
1192                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1193                               struct rte_mempool *mp)
1194 {
1195         struct ena_com_create_io_ctx ctx =
1196                 /* policy set to _HOST just to satisfy icc compiler */
1197                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1198                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1199         struct ena_adapter *adapter =
1200                 (struct ena_adapter *)(dev->data->dev_private);
1201         struct ena_ring *rxq = NULL;
1202         uint16_t ena_qid = 0;
1203         int i, rc = 0;
1204         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1205
1206         rxq = &adapter->rx_ring[queue_idx];
1207         if (rxq->configured) {
1208                 RTE_LOG(CRIT, PMD,
1209                         "API violation. Queue %d is already configured\n",
1210                         queue_idx);
1211                 return -1;
1212         }
1213
1214         if (!rte_is_power_of_2(nb_desc)) {
1215                 RTE_LOG(ERR, PMD,
1216                         "Unsupported size of TX queue: %d is not a power of 2.",
1217                         nb_desc);
1218                 return -EINVAL;
1219         }
1220
1221         if (nb_desc > adapter->rx_ring_size) {
1222                 RTE_LOG(ERR, PMD,
1223                         "Unsupported size of RX queue (max size: %d)\n",
1224                         adapter->rx_ring_size);
1225                 return -EINVAL;
1226         }
1227
1228         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1229
1230         ctx.qid = ena_qid;
1231         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1232         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1233         ctx.msix_vector = -1; /* admin interrupts not used */
1234         ctx.queue_size = adapter->rx_ring_size;
1235         ctx.numa_node = ena_cpu_to_node(queue_idx);
1236
1237         rc = ena_com_create_io_queue(ena_dev, &ctx);
1238         if (rc)
1239                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1240                         queue_idx, rc);
1241
1242         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1243         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1244
1245         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1246                                      &rxq->ena_com_io_sq,
1247                                      &rxq->ena_com_io_cq);
1248         if (rc) {
1249                 RTE_LOG(ERR, PMD,
1250                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1251                         queue_idx, rc);
1252                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1253         }
1254
1255         rxq->port_id = dev->data->port_id;
1256         rxq->next_to_clean = 0;
1257         rxq->next_to_use = 0;
1258         rxq->ring_size = nb_desc;
1259         rxq->mb_pool = mp;
1260
1261         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1262                                           sizeof(struct rte_mbuf *) * nb_desc,
1263                                           RTE_CACHE_LINE_SIZE);
1264         if (!rxq->rx_buffer_info) {
1265                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1266                 return -ENOMEM;
1267         }
1268
1269         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1270                                          sizeof(uint16_t) * nb_desc,
1271                                          RTE_CACHE_LINE_SIZE);
1272         if (!rxq->empty_rx_reqs) {
1273                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1274                 rte_free(rxq->rx_buffer_info);
1275                 rxq->rx_buffer_info = NULL;
1276                 return -ENOMEM;
1277         }
1278
1279         for (i = 0; i < nb_desc; i++)
1280                 rxq->empty_tx_reqs[i] = i;
1281
1282         /* Store pointer to this queue in upper layer */
1283         rxq->configured = 1;
1284         dev->data->rx_queues[queue_idx] = rxq;
1285
1286         return rc;
1287 }
1288
1289 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1290 {
1291         unsigned int i;
1292         int rc;
1293         uint16_t ring_size = rxq->ring_size;
1294         uint16_t ring_mask = ring_size - 1;
1295         uint16_t next_to_use = rxq->next_to_use;
1296         uint16_t in_use, req_id;
1297         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1298
1299         if (unlikely(!count))
1300                 return 0;
1301
1302         in_use = rxq->next_to_use - rxq->next_to_clean;
1303         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1304
1305         count = RTE_MIN(count,
1306                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1307
1308         /* get resources for incoming packets */
1309         rc = rte_mempool_get_bulk(rxq->mb_pool,
1310                                   (void **)(&mbufs[next_to_use & ring_mask]),
1311                                   count);
1312         if (unlikely(rc < 0)) {
1313                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1314                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1315                 return 0;
1316         }
1317
1318         for (i = 0; i < count; i++) {
1319                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1320                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1321                 struct ena_com_buf ebuf;
1322
1323                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1324
1325                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1326                 /* prepare physical address for DMA transaction */
1327                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1328                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1329                 /* pass resource to device */
1330                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1331                                                 &ebuf, req_id);
1332                 if (unlikely(rc)) {
1333                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1334                                              count - i);
1335                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1336                         break;
1337                 }
1338                 next_to_use++;
1339         }
1340
1341         /* When we submitted free recources to device... */
1342         if (i > 0) {
1343                 /* ...let HW know that it can fill buffers with data */
1344                 rte_wmb();
1345                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1346
1347                 rxq->next_to_use = next_to_use;
1348         }
1349
1350         return i;
1351 }
1352
1353 static int ena_device_init(struct ena_com_dev *ena_dev,
1354                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1355                            bool *wd_state)
1356 {
1357         uint32_t aenq_groups;
1358         int rc;
1359         bool readless_supported;
1360
1361         /* Initialize mmio registers */
1362         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1363         if (rc) {
1364                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1365                 return rc;
1366         }
1367
1368         /* The PCIe configuration space revision id indicate if mmio reg
1369          * read is disabled.
1370          */
1371         readless_supported =
1372                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1373                                & ENA_MMIO_DISABLE_REG_READ);
1374         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1375
1376         /* reset device */
1377         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1378         if (rc) {
1379                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1380                 goto err_mmio_read_less;
1381         }
1382
1383         /* check FW version */
1384         rc = ena_com_validate_version(ena_dev);
1385         if (rc) {
1386                 RTE_LOG(ERR, PMD, "device version is too low\n");
1387                 goto err_mmio_read_less;
1388         }
1389
1390         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1391
1392         /* ENA device administration layer init */
1393         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1394         if (rc) {
1395                 RTE_LOG(ERR, PMD,
1396                         "cannot initialize ena admin queue with device\n");
1397                 goto err_mmio_read_less;
1398         }
1399
1400         /* To enable the msix interrupts the driver needs to know the number
1401          * of queues. So the driver uses polling mode to retrieve this
1402          * information.
1403          */
1404         ena_com_set_admin_polling_mode(ena_dev, true);
1405
1406         ena_config_host_info(ena_dev);
1407
1408         /* Get Device Attributes and features */
1409         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1410         if (rc) {
1411                 RTE_LOG(ERR, PMD,
1412                         "cannot get attribute for ena device rc= %d\n", rc);
1413                 goto err_admin_init;
1414         }
1415
1416         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1417                       BIT(ENA_ADMIN_NOTIFICATION) |
1418                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1419                       BIT(ENA_ADMIN_FATAL_ERROR) |
1420                       BIT(ENA_ADMIN_WARNING);
1421
1422         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1423         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1424         if (rc) {
1425                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1426                 goto err_admin_init;
1427         }
1428
1429         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1430
1431         return 0;
1432
1433 err_admin_init:
1434         ena_com_admin_destroy(ena_dev);
1435
1436 err_mmio_read_less:
1437         ena_com_mmio_reg_read_request_destroy(ena_dev);
1438
1439         return rc;
1440 }
1441
1442 static void ena_interrupt_handler_rte(void *cb_arg)
1443 {
1444         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1445         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1446
1447         ena_com_admin_q_comp_intr_handler(ena_dev);
1448         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1449                 ena_com_aenq_intr_handler(ena_dev, adapter);
1450 }
1451
1452 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1453 {
1454         if (!adapter->wd_state)
1455                 return;
1456
1457         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1458                 return;
1459
1460         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1461             adapter->keep_alive_timeout)) {
1462                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1463                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1464                 adapter->trigger_reset = true;
1465         }
1466 }
1467
1468 /* Check if admin queue is enabled */
1469 static void check_for_admin_com_state(struct ena_adapter *adapter)
1470 {
1471         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1472                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1473                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1474                 adapter->trigger_reset = true;
1475         }
1476 }
1477
1478 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1479                                   void *arg)
1480 {
1481         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1482         struct rte_eth_dev *dev = adapter->rte_dev;
1483
1484         check_for_missing_keep_alive(adapter);
1485         check_for_admin_com_state(adapter);
1486
1487         if (unlikely(adapter->trigger_reset)) {
1488                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1489                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1490                         NULL);
1491         }
1492 }
1493
1494 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1495                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1496 {
1497         int io_sq_num, io_cq_num, io_queue_num;
1498
1499         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1500         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1501
1502         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1503
1504         if (unlikely(io_queue_num == 0)) {
1505                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1506                 return -EFAULT;
1507         }
1508
1509         return io_queue_num;
1510 }
1511
1512 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1513 {
1514         struct rte_pci_device *pci_dev;
1515         struct rte_intr_handle *intr_handle;
1516         struct ena_adapter *adapter =
1517                 (struct ena_adapter *)(eth_dev->data->dev_private);
1518         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1519         struct ena_com_dev_get_features_ctx get_feat_ctx;
1520         int queue_size, rc;
1521         u16 tx_sgl_size = 0;
1522
1523         static int adapters_found;
1524         bool wd_state;
1525
1526         memset(adapter, 0, sizeof(struct ena_adapter));
1527         ena_dev = &adapter->ena_dev;
1528
1529         eth_dev->dev_ops = &ena_dev_ops;
1530         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1531         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1532         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1533         adapter->rte_eth_dev_data = eth_dev->data;
1534         adapter->rte_dev = eth_dev;
1535
1536         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1537                 return 0;
1538
1539         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1540         adapter->pdev = pci_dev;
1541
1542         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1543                      pci_dev->addr.domain,
1544                      pci_dev->addr.bus,
1545                      pci_dev->addr.devid,
1546                      pci_dev->addr.function);
1547
1548         intr_handle = &pci_dev->intr_handle;
1549
1550         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1551         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1552
1553         if (!adapter->regs) {
1554                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1555                              ENA_REGS_BAR);
1556                 return -ENXIO;
1557         }
1558
1559         ena_dev->reg_bar = adapter->regs;
1560         ena_dev->dmadev = adapter->pdev;
1561
1562         adapter->id_number = adapters_found;
1563
1564         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1565                  adapter->id_number);
1566
1567         /* device specific initialization routine */
1568         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1569         if (rc) {
1570                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1571                 return -1;
1572         }
1573         adapter->wd_state = wd_state;
1574
1575         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1576         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1577                                                     &get_feat_ctx);
1578
1579         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1580         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1581                 return -EFAULT;
1582
1583         adapter->tx_ring_size = queue_size;
1584         adapter->rx_ring_size = queue_size;
1585
1586         adapter->max_tx_sgl_size = tx_sgl_size;
1587
1588         /* prepare ring structures */
1589         ena_init_rings(adapter);
1590
1591         ena_config_debug_area(adapter);
1592
1593         /* Set max MTU for this device */
1594         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1595
1596         /* set device support for TSO */
1597         adapter->tso4_supported = get_feat_ctx.offload.tx &
1598                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1599
1600         /* Copy MAC address and point DPDK to it */
1601         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1602         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1603                         (struct ether_addr *)adapter->mac_addr);
1604
1605         adapter->drv_stats = rte_zmalloc("adapter stats",
1606                                          sizeof(*adapter->drv_stats),
1607                                          RTE_CACHE_LINE_SIZE);
1608         if (!adapter->drv_stats) {
1609                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1610                 return -ENOMEM;
1611         }
1612
1613         rte_intr_callback_register(intr_handle,
1614                                    ena_interrupt_handler_rte,
1615                                    adapter);
1616         rte_intr_enable(intr_handle);
1617         ena_com_set_admin_polling_mode(ena_dev, false);
1618         ena_com_admin_aenq_enable(ena_dev);
1619
1620         if (adapters_found == 0)
1621                 rte_timer_subsystem_init();
1622         rte_timer_init(&adapter->timer_wd);
1623
1624         adapters_found++;
1625         adapter->state = ENA_ADAPTER_STATE_INIT;
1626
1627         return 0;
1628 }
1629
1630 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1631 {
1632         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1633         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1634         struct ena_adapter *adapter =
1635                 (struct ena_adapter *)(eth_dev->data->dev_private);
1636
1637         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1638                 return -EPERM;
1639
1640         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1641                 ena_close(eth_dev);
1642
1643         eth_dev->dev_ops = NULL;
1644         eth_dev->rx_pkt_burst = NULL;
1645         eth_dev->tx_pkt_burst = NULL;
1646         eth_dev->tx_pkt_prepare = NULL;
1647
1648         rte_free(adapter->drv_stats);
1649         adapter->drv_stats = NULL;
1650
1651         rte_intr_disable(intr_handle);
1652         rte_intr_callback_unregister(intr_handle,
1653                                      ena_interrupt_handler_rte,
1654                                      adapter);
1655
1656         adapter->state = ENA_ADAPTER_STATE_FREE;
1657
1658         return 0;
1659 }
1660
1661 static int ena_dev_configure(struct rte_eth_dev *dev)
1662 {
1663         struct ena_adapter *adapter =
1664                 (struct ena_adapter *)(dev->data->dev_private);
1665
1666         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1667
1668         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1669         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1670         return 0;
1671 }
1672
1673 static void ena_init_rings(struct ena_adapter *adapter)
1674 {
1675         int i;
1676
1677         for (i = 0; i < adapter->num_queues; i++) {
1678                 struct ena_ring *ring = &adapter->tx_ring[i];
1679
1680                 ring->configured = 0;
1681                 ring->type = ENA_RING_TYPE_TX;
1682                 ring->adapter = adapter;
1683                 ring->id = i;
1684                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1685                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1686                 ring->sgl_size = adapter->max_tx_sgl_size;
1687         }
1688
1689         for (i = 0; i < adapter->num_queues; i++) {
1690                 struct ena_ring *ring = &adapter->rx_ring[i];
1691
1692                 ring->configured = 0;
1693                 ring->type = ENA_RING_TYPE_RX;
1694                 ring->adapter = adapter;
1695                 ring->id = i;
1696         }
1697 }
1698
1699 static void ena_infos_get(struct rte_eth_dev *dev,
1700                           struct rte_eth_dev_info *dev_info)
1701 {
1702         struct ena_adapter *adapter;
1703         struct ena_com_dev *ena_dev;
1704         struct ena_com_dev_get_features_ctx feat;
1705         uint64_t rx_feat = 0, tx_feat = 0;
1706         int rc = 0;
1707
1708         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1709         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1710         adapter = (struct ena_adapter *)(dev->data->dev_private);
1711
1712         ena_dev = &adapter->ena_dev;
1713         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1714
1715         dev_info->speed_capa =
1716                         ETH_LINK_SPEED_1G   |
1717                         ETH_LINK_SPEED_2_5G |
1718                         ETH_LINK_SPEED_5G   |
1719                         ETH_LINK_SPEED_10G  |
1720                         ETH_LINK_SPEED_25G  |
1721                         ETH_LINK_SPEED_40G  |
1722                         ETH_LINK_SPEED_50G  |
1723                         ETH_LINK_SPEED_100G;
1724
1725         /* Get supported features from HW */
1726         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1727         if (unlikely(rc)) {
1728                 RTE_LOG(ERR, PMD,
1729                         "Cannot get attribute for ena device rc= %d\n", rc);
1730                 return;
1731         }
1732
1733         /* Set Tx & Rx features available for device */
1734         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1735                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1736
1737         if (feat.offload.tx &
1738             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1739                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1740                         DEV_TX_OFFLOAD_UDP_CKSUM |
1741                         DEV_TX_OFFLOAD_TCP_CKSUM;
1742
1743         if (feat.offload.rx_supported &
1744             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1745                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1746                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1747                         DEV_RX_OFFLOAD_TCP_CKSUM;
1748
1749         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1750
1751         /* Inform framework about available features */
1752         dev_info->rx_offload_capa = rx_feat;
1753         dev_info->rx_queue_offload_capa = rx_feat;
1754         dev_info->tx_offload_capa = tx_feat;
1755         dev_info->tx_queue_offload_capa = tx_feat;
1756
1757         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1758         dev_info->max_rx_pktlen  = adapter->max_mtu;
1759         dev_info->max_mac_addrs = 1;
1760
1761         dev_info->max_rx_queues = adapter->num_queues;
1762         dev_info->max_tx_queues = adapter->num_queues;
1763         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1764
1765         adapter->tx_supported_offloads = tx_feat;
1766         adapter->rx_supported_offloads = rx_feat;
1767
1768         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1769         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1770
1771         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1772         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1773         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1774                                         feat.max_queues.max_packet_tx_descs);
1775         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1776                                         feat.max_queues.max_packet_tx_descs);
1777 }
1778
1779 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1780                                   uint16_t nb_pkts)
1781 {
1782         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1783         unsigned int ring_size = rx_ring->ring_size;
1784         unsigned int ring_mask = ring_size - 1;
1785         uint16_t next_to_clean = rx_ring->next_to_clean;
1786         uint16_t desc_in_use = 0;
1787         uint16_t req_id;
1788         unsigned int recv_idx = 0;
1789         struct rte_mbuf *mbuf = NULL;
1790         struct rte_mbuf *mbuf_head = NULL;
1791         struct rte_mbuf *mbuf_prev = NULL;
1792         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1793         unsigned int completed;
1794
1795         struct ena_com_rx_ctx ena_rx_ctx;
1796         int rc = 0;
1797
1798         /* Check adapter state */
1799         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1800                 RTE_LOG(ALERT, PMD,
1801                         "Trying to receive pkts while device is NOT running\n");
1802                 return 0;
1803         }
1804
1805         desc_in_use = rx_ring->next_to_use - next_to_clean;
1806         if (unlikely(nb_pkts > desc_in_use))
1807                 nb_pkts = desc_in_use;
1808
1809         for (completed = 0; completed < nb_pkts; completed++) {
1810                 int segments = 0;
1811
1812                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1813                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1814                 ena_rx_ctx.descs = 0;
1815                 /* receive packet context */
1816                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1817                                     rx_ring->ena_com_io_sq,
1818                                     &ena_rx_ctx);
1819                 if (unlikely(rc)) {
1820                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1821                         return 0;
1822                 }
1823
1824                 if (unlikely(ena_rx_ctx.descs == 0))
1825                         break;
1826
1827                 while (segments < ena_rx_ctx.descs) {
1828                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1829                         rc = validate_rx_req_id(rx_ring, req_id);
1830                         if (unlikely(rc))
1831                                 break;
1832
1833                         mbuf = rx_buff_info[req_id];
1834                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1835                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1836                         mbuf->refcnt = 1;
1837                         mbuf->next = NULL;
1838                         if (segments == 0) {
1839                                 mbuf->nb_segs = ena_rx_ctx.descs;
1840                                 mbuf->port = rx_ring->port_id;
1841                                 mbuf->pkt_len = 0;
1842                                 mbuf_head = mbuf;
1843                         } else {
1844                                 /* for multi-segment pkts create mbuf chain */
1845                                 mbuf_prev->next = mbuf;
1846                         }
1847                         mbuf_head->pkt_len += mbuf->data_len;
1848
1849                         mbuf_prev = mbuf;
1850                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1851                                 req_id;
1852                         segments++;
1853                         next_to_clean++;
1854                 }
1855
1856                 /* fill mbuf attributes if any */
1857                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1858                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1859
1860                 /* pass to DPDK application head mbuf */
1861                 rx_pkts[recv_idx] = mbuf_head;
1862                 recv_idx++;
1863         }
1864
1865         rx_ring->next_to_clean = next_to_clean;
1866
1867         desc_in_use = desc_in_use - completed + 1;
1868         /* Burst refill to save doorbells, memory barriers, const interval */
1869         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1870                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1871
1872         return recv_idx;
1873 }
1874
1875 static uint16_t
1876 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1877                 uint16_t nb_pkts)
1878 {
1879         int32_t ret;
1880         uint32_t i;
1881         struct rte_mbuf *m;
1882         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1883         struct ipv4_hdr *ip_hdr;
1884         uint64_t ol_flags;
1885         uint16_t frag_field;
1886
1887         for (i = 0; i != nb_pkts; i++) {
1888                 m = tx_pkts[i];
1889                 ol_flags = m->ol_flags;
1890
1891                 if (!(ol_flags & PKT_TX_IPV4))
1892                         continue;
1893
1894                 /* If there was not L2 header length specified, assume it is
1895                  * length of the ethernet header.
1896                  */
1897                 if (unlikely(m->l2_len == 0))
1898                         m->l2_len = sizeof(struct ether_hdr);
1899
1900                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1901                                                  m->l2_len);
1902                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1903
1904                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1905                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1906
1907                         /* If IPv4 header has DF flag enabled and TSO support is
1908                          * disabled, partial chcecksum should not be calculated.
1909                          */
1910                         if (!tx_ring->adapter->tso4_supported)
1911                                 continue;
1912                 }
1913
1914                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1915                                 (ol_flags & PKT_TX_L4_MASK) ==
1916                                 PKT_TX_SCTP_CKSUM) {
1917                         rte_errno = -ENOTSUP;
1918                         return i;
1919                 }
1920
1921 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1922                 ret = rte_validate_tx_offload(m);
1923                 if (ret != 0) {
1924                         rte_errno = ret;
1925                         return i;
1926                 }
1927 #endif
1928
1929                 /* In case we are supposed to TSO and have DF not set (DF=0)
1930                  * hardware must be provided with partial checksum, otherwise
1931                  * it will take care of necessary calculations.
1932                  */
1933
1934                 ret = rte_net_intel_cksum_flags_prepare(m,
1935                         ol_flags & ~PKT_TX_TCP_SEG);
1936                 if (ret != 0) {
1937                         rte_errno = ret;
1938                         return i;
1939                 }
1940         }
1941
1942         return i;
1943 }
1944
1945 static void ena_update_hints(struct ena_adapter *adapter,
1946                              struct ena_admin_ena_hw_hints *hints)
1947 {
1948         if (hints->admin_completion_tx_timeout)
1949                 adapter->ena_dev.admin_queue.completion_timeout =
1950                         hints->admin_completion_tx_timeout * 1000;
1951
1952         if (hints->mmio_read_timeout)
1953                 /* convert to usec */
1954                 adapter->ena_dev.mmio_read.reg_read_to =
1955                         hints->mmio_read_timeout * 1000;
1956
1957         if (hints->driver_watchdog_timeout) {
1958                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1959                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1960                 else
1961                         // Convert msecs to ticks
1962                         adapter->keep_alive_timeout =
1963                                 (hints->driver_watchdog_timeout *
1964                                 rte_get_timer_hz()) / 1000;
1965         }
1966 }
1967
1968 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
1969                                         struct rte_mbuf *mbuf)
1970 {
1971         int num_segments, rc;
1972
1973         num_segments = mbuf->nb_segs;
1974
1975         if (likely(num_segments < tx_ring->sgl_size))
1976                 return 0;
1977
1978         rc = rte_pktmbuf_linearize(mbuf);
1979         if (unlikely(rc))
1980                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
1981
1982         return rc;
1983 }
1984
1985 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1986                                   uint16_t nb_pkts)
1987 {
1988         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1989         uint16_t next_to_use = tx_ring->next_to_use;
1990         uint16_t next_to_clean = tx_ring->next_to_clean;
1991         struct rte_mbuf *mbuf;
1992         unsigned int ring_size = tx_ring->ring_size;
1993         unsigned int ring_mask = ring_size - 1;
1994         struct ena_com_tx_ctx ena_tx_ctx;
1995         struct ena_tx_buffer *tx_info;
1996         struct ena_com_buf *ebuf;
1997         uint16_t rc, req_id, total_tx_descs = 0;
1998         uint16_t sent_idx = 0, empty_tx_reqs;
1999         int nb_hw_desc;
2000
2001         /* Check adapter state */
2002         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2003                 RTE_LOG(ALERT, PMD,
2004                         "Trying to xmit pkts while device is NOT running\n");
2005                 return 0;
2006         }
2007
2008         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2009         if (nb_pkts > empty_tx_reqs)
2010                 nb_pkts = empty_tx_reqs;
2011
2012         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2013                 mbuf = tx_pkts[sent_idx];
2014
2015                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2016                 if (unlikely(rc))
2017                         break;
2018
2019                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2020                 tx_info = &tx_ring->tx_buffer_info[req_id];
2021                 tx_info->mbuf = mbuf;
2022                 tx_info->num_of_bufs = 0;
2023                 ebuf = tx_info->bufs;
2024
2025                 /* Prepare TX context */
2026                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2027                 memset(&ena_tx_ctx.ena_meta, 0x0,
2028                        sizeof(struct ena_com_tx_meta));
2029                 ena_tx_ctx.ena_bufs = ebuf;
2030                 ena_tx_ctx.req_id = req_id;
2031                 if (tx_ring->tx_mem_queue_type ==
2032                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2033                         /* prepare the push buffer with
2034                          * virtual address of the data
2035                          */
2036                         ena_tx_ctx.header_len =
2037                                 RTE_MIN(mbuf->data_len,
2038                                         tx_ring->tx_max_header_size);
2039                         ena_tx_ctx.push_header =
2040                                 (void *)((char *)mbuf->buf_addr +
2041                                          mbuf->data_off);
2042                 } /* there's no else as we take advantage of memset zeroing */
2043
2044                 /* Set TX offloads flags, if applicable */
2045                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2046
2047                 if (unlikely(mbuf->ol_flags &
2048                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2049                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2050
2051                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2052
2053                 /* Process first segment taking into
2054                  * consideration pushed header
2055                  */
2056                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2057                         ebuf->paddr = mbuf->buf_iova +
2058                                       mbuf->data_off +
2059                                       ena_tx_ctx.header_len;
2060                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2061                         ebuf++;
2062                         tx_info->num_of_bufs++;
2063                 }
2064
2065                 while ((mbuf = mbuf->next) != NULL) {
2066                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2067                         ebuf->len = mbuf->data_len;
2068                         ebuf++;
2069                         tx_info->num_of_bufs++;
2070                 }
2071
2072                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2073
2074                 /* Write data to device */
2075                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2076                                         &ena_tx_ctx, &nb_hw_desc);
2077                 if (unlikely(rc))
2078                         break;
2079
2080                 tx_info->tx_descs = nb_hw_desc;
2081
2082                 next_to_use++;
2083         }
2084
2085         /* If there are ready packets to be xmitted... */
2086         if (sent_idx > 0) {
2087                 /* ...let HW do its best :-) */
2088                 rte_wmb();
2089                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2090
2091                 tx_ring->next_to_use = next_to_use;
2092         }
2093
2094         /* Clear complete packets  */
2095         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2096                 /* Get Tx info & store how many descs were processed  */
2097                 tx_info = &tx_ring->tx_buffer_info[req_id];
2098                 total_tx_descs += tx_info->tx_descs;
2099
2100                 /* Free whole mbuf chain  */
2101                 mbuf = tx_info->mbuf;
2102                 rte_pktmbuf_free(mbuf);
2103                 tx_info->mbuf = NULL;
2104
2105                 /* Put back descriptor to the ring for reuse */
2106                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2107                 next_to_clean++;
2108
2109                 /* If too many descs to clean, leave it for another run */
2110                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2111                         break;
2112         }
2113
2114         if (total_tx_descs > 0) {
2115                 /* acknowledge completion of sent packets */
2116                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2117                 tx_ring->next_to_clean = next_to_clean;
2118         }
2119
2120         return sent_idx;
2121 }
2122
2123 /*********************************************************************
2124  *  PMD configuration
2125  *********************************************************************/
2126 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2127         struct rte_pci_device *pci_dev)
2128 {
2129         return rte_eth_dev_pci_generic_probe(pci_dev,
2130                 sizeof(struct ena_adapter), eth_ena_dev_init);
2131 }
2132
2133 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2134 {
2135         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2136 }
2137
2138 static struct rte_pci_driver rte_ena_pmd = {
2139         .id_table = pci_id_ena_map,
2140         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2141         .probe = eth_ena_pci_probe,
2142         .remove = eth_ena_pci_remove,
2143 };
2144
2145 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2146 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2147 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2148
2149 RTE_INIT(ena_init_log);
2150 static void
2151 ena_init_log(void)
2152 {
2153         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2154         if (ena_logtype_init >= 0)
2155                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2156         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2157         if (ena_logtype_driver >= 0)
2158                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2159 }
2160
2161 /******************************************************************************
2162  ******************************** AENQ Handlers *******************************
2163  *****************************************************************************/
2164 static void ena_update_on_link_change(void *adapter_data,
2165                                       struct ena_admin_aenq_entry *aenq_e)
2166 {
2167         struct rte_eth_dev *eth_dev;
2168         struct ena_adapter *adapter;
2169         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2170         uint32_t status;
2171
2172         adapter = (struct ena_adapter *)adapter_data;
2173         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2174         eth_dev = adapter->rte_dev;
2175
2176         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2177         adapter->link_status = status;
2178
2179         ena_link_update(eth_dev, 0);
2180         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2181 }
2182
2183 static void ena_notification(void *data,
2184                              struct ena_admin_aenq_entry *aenq_e)
2185 {
2186         struct ena_adapter *adapter = (struct ena_adapter *)data;
2187         struct ena_admin_ena_hw_hints *hints;
2188
2189         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2190                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2191                         aenq_e->aenq_common_desc.group,
2192                         ENA_ADMIN_NOTIFICATION);
2193
2194         switch (aenq_e->aenq_common_desc.syndrom) {
2195         case ENA_ADMIN_UPDATE_HINTS:
2196                 hints = (struct ena_admin_ena_hw_hints *)
2197                         (&aenq_e->inline_data_w4);
2198                 ena_update_hints(adapter, hints);
2199                 break;
2200         default:
2201                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2202                         aenq_e->aenq_common_desc.syndrom);
2203         }
2204 }
2205
2206 static void ena_keep_alive(void *adapter_data,
2207                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2208 {
2209         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2210
2211         adapter->timestamp_wd = rte_get_timer_cycles();
2212 }
2213
2214 /**
2215  * This handler will called for unknown event group or unimplemented handlers
2216  **/
2217 static void unimplemented_aenq_handler(__rte_unused void *data,
2218                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2219 {
2220         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2221                           "unimplemented handler\n");
2222 }
2223
2224 static struct ena_aenq_handlers aenq_handlers = {
2225         .handlers = {
2226                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2227                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2228                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2229         },
2230         .unimplemented_handler = unimplemented_aenq_handler
2231 };