drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IP_CKSUM |        \
 193         PKT_TX_TCP_SEG)
 194
 195 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 196         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 197
 198 int ena_logtype_init;
 199 int ena_logtype_driver;
 200
 201 static const struct rte_pci_id pci_id_ena_map[] = {
 202         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 203         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 204         { .device_id = 0 },
 205 };
 206
 207 static struct ena_aenq_handlers aenq_handlers;
 208
 209 static int ena_device_init(struct ena_com_dev *ena_dev,
 210                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 211                            bool *wd_state);
 212 static int ena_dev_configure(struct rte_eth_dev *dev);
 213 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 214                                   uint16_t nb_pkts);
 215 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                 uint16_t nb_pkts);
 217 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 218                               uint16_t nb_desc, unsigned int socket_id,
 219                               const struct rte_eth_txconf *tx_conf);
 220 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 221                               uint16_t nb_desc, unsigned int socket_id,
 222                               const struct rte_eth_rxconf *rx_conf,
 223                               struct rte_mempool *mp);
 224 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 225                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 226 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 227 static void ena_init_rings(struct ena_adapter *adapter);
 228 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 229 static int ena_start(struct rte_eth_dev *dev);
 230 static void ena_stop(struct rte_eth_dev *dev);
 231 static void ena_close(struct rte_eth_dev *dev);
 232 static int ena_dev_reset(struct rte_eth_dev *dev);
 233 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 234 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 235 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 236 static void ena_rx_queue_release(void *queue);
 237 static void ena_tx_queue_release(void *queue);
 238 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 239 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 240 static int ena_link_update(struct rte_eth_dev *dev,
 241                            int wait_to_complete);
 242 static int ena_queue_restart(struct ena_ring *ring);
 243 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 244                                  enum ena_ring_type ring_type);
 245 static void ena_stats_restart(struct rte_eth_dev *dev);
 246 static void ena_infos_get(struct rte_eth_dev *dev,
 247                           struct rte_eth_dev_info *dev_info);
 248 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 249                                struct rte_eth_rss_reta_entry64 *reta_conf,
 250                                uint16_t reta_size);
 251 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 252                               struct rte_eth_rss_reta_entry64 *reta_conf,
 253                               uint16_t reta_size);
 254 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 255 static void ena_interrupt_handler_rte(void *cb_arg);
 256 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 257
 258 static const struct eth_dev_ops ena_dev_ops = {
 259         .dev_configure        = ena_dev_configure,
 260         .dev_infos_get        = ena_infos_get,
 261         .rx_queue_setup       = ena_rx_queue_setup,
 262         .tx_queue_setup       = ena_tx_queue_setup,
 263         .dev_start            = ena_start,
 264         .dev_stop             = ena_stop,
 265         .link_update          = ena_link_update,
 266         .stats_get            = ena_stats_get,
 267         .mtu_set              = ena_mtu_set,
 268         .rx_queue_release     = ena_rx_queue_release,
 269         .tx_queue_release     = ena_tx_queue_release,
 270         .dev_close            = ena_close,
 271         .dev_reset            = ena_dev_reset,
 272         .reta_update          = ena_rss_reta_update,
 273         .reta_query           = ena_rss_reta_query,
 274 };
 275
 276 #define NUMA_NO_NODE    SOCKET_ID_ANY
 277
 278 static inline int ena_cpu_to_node(int cpu)
 279 {
 280         struct rte_config *config = rte_eal_get_configuration();
 281         struct rte_fbarray *arr = &config->mem_config->memzones;
 282         const struct rte_memzone *mz;
 283
 284         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 285                 return NUMA_NO_NODE;
 286
 287         mz = rte_fbarray_get(arr, cpu);
 288
 289         return mz->socket_id;
 290 }
 291
 292 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 293                                        struct ena_com_rx_ctx *ena_rx_ctx)
 294 {
 295         uint64_t ol_flags = 0;
 296         uint32_t packet_type = 0;
 297
 298         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 299                 packet_type |= RTE_PTYPE_L4_TCP;
 300         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 301                 packet_type |= RTE_PTYPE_L4_UDP;
 302
 303         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 304                 packet_type |= RTE_PTYPE_L3_IPV4;
 305         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 306                 packet_type |= RTE_PTYPE_L3_IPV6;
 307
 308         if (unlikely(ena_rx_ctx->l4_csum_err))
 309                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 310         if (unlikely(ena_rx_ctx->l3_csum_err))
 311                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 312
 313         mbuf->ol_flags = ol_flags;
 314         mbuf->packet_type = packet_type;
 315 }
 316
 317 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 318                                        struct ena_com_tx_ctx *ena_tx_ctx,
 319                                        uint64_t queue_offloads)
 320 {
 321         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 322
 323         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 324             (queue_offloads & QUEUE_OFFLOADS)) {
 325                 /* check if TSO is required */
 326                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 327                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 328                         ena_tx_ctx->tso_enable = true;
 329
 330                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 331                 }
 332
 333                 /* check if L3 checksum is needed */
 334                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 335                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 336                         ena_tx_ctx->l3_csum_enable = true;
 337
 338                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 339                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 340                 } else {
 341                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 342
 343                         /* set don't fragment (DF) flag */
 344                         if (mbuf->packet_type &
 345                                 (RTE_PTYPE_L4_NONFRAG
 346                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 347                                 ena_tx_ctx->df = true;
 348                 }
 349
 350                 /* check if L4 checksum is needed */
 351                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 352                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 353                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 354                         ena_tx_ctx->l4_csum_enable = true;
 355                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 356                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else {
 360                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 361                         ena_tx_ctx->l4_csum_enable = false;
 362                 }
 363
 364                 ena_meta->mss = mbuf->tso_segsz;
 365                 ena_meta->l3_hdr_len = mbuf->l3_len;
 366                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 367
 368                 ena_tx_ctx->meta_valid = true;
 369         } else {
 370                 ena_tx_ctx->meta_valid = false;
 371         }
 372 }
 373
 374 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 375 {
 376         if (likely(req_id < rx_ring->ring_size))
 377                 return 0;
 378
 379         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 380
 381         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 382         rx_ring->adapter->trigger_reset = true;
 383
 384         return -EFAULT;
 385 }
 386
 387 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 388 {
 389         struct ena_tx_buffer *tx_info = NULL;
 390
 391         if (likely(req_id < tx_ring->ring_size)) {
 392                 tx_info = &tx_ring->tx_buffer_info[req_id];
 393                 if (likely(tx_info->mbuf))
 394                         return 0;
 395         }
 396
 397         if (tx_info)
 398                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 399         else
 400                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 401
 402         /* Trigger device reset */
 403         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 404         tx_ring->adapter->trigger_reset = true;
 405         return -EFAULT;
 406 }
 407
 408 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 409 {
 410         struct ena_admin_host_info *host_info;
 411         int rc;
 412
 413         /* Allocate only the host info */
 414         rc = ena_com_allocate_host_info(ena_dev);
 415         if (rc) {
 416                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 417                 return;
 418         }
 419
 420         host_info = ena_dev->host_attr.host_info;
 421
 422         host_info->os_type = ENA_ADMIN_OS_DPDK;
 423         host_info->kernel_ver = RTE_VERSION;
 424         snprintf((char *)host_info->kernel_ver_str,
 425                  sizeof(host_info->kernel_ver_str),
 426                  "%s", rte_version());
 427         host_info->os_dist = RTE_VERSION;
 428         snprintf((char *)host_info->os_dist_str,
 429                  sizeof(host_info->os_dist_str),
 430                  "%s", rte_version());
 431         host_info->driver_version =
 432                 (DRV_MODULE_VER_MAJOR) |
 433                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 434                 (DRV_MODULE_VER_SUBMINOR <<
 435                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 436
 437         rc = ena_com_set_host_attributes(ena_dev);
 438         if (rc) {
 439                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 440                 if (rc != -ENA_COM_UNSUPPORTED)
 441                         goto err;
 442         }
 443
 444         return;
 445
 446 err:
 447         ena_com_delete_host_info(ena_dev);
 448 }
 449
 450 static int
 451 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 452 {
 453         if (sset != ETH_SS_STATS)
 454                 return -EOPNOTSUPP;
 455
 456          /* Workaround for clang:
 457          * touch internal structures to prevent
 458          * compiler error
 459          */
 460         ENA_TOUCH(ena_stats_global_strings);
 461         ENA_TOUCH(ena_stats_tx_strings);
 462         ENA_TOUCH(ena_stats_rx_strings);
 463         ENA_TOUCH(ena_stats_ena_com_strings);
 464
 465         return  dev->data->nb_tx_queues *
 466                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 467                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 468 }
 469
 470 static void ena_config_debug_area(struct ena_adapter *adapter)
 471 {
 472         u32 debug_area_size;
 473         int rc, ss_count;
 474
 475         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 476         if (ss_count <= 0) {
 477                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 478                 return;
 479         }
 480
 481         /* allocate 32 bytes for each string and 64bit for the value */
 482         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 483
 484         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 485         if (rc) {
 486                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 487                 return;
 488         }
 489
 490         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 491         if (rc) {
 492                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 493                 if (rc != -ENA_COM_UNSUPPORTED)
 494                         goto err;
 495         }
 496
 497         return;
 498 err:
 499         ena_com_delete_debug_area(&adapter->ena_dev);
 500 }
 501
 502 static void ena_close(struct rte_eth_dev *dev)
 503 {
 504         struct ena_adapter *adapter =
 505                 (struct ena_adapter *)(dev->data->dev_private);
 506
 507         ena_stop(dev);
 508         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 509
 510         ena_rx_queue_release_all(dev);
 511         ena_tx_queue_release_all(dev);
 512 }
 513
 514 static int
 515 ena_dev_reset(struct rte_eth_dev *dev)
 516 {
 517         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 518         struct rte_eth_dev *eth_dev;
 519         struct rte_pci_device *pci_dev;
 520         struct rte_intr_handle *intr_handle;
 521         struct ena_com_dev *ena_dev;
 522         struct ena_com_dev_get_features_ctx get_feat_ctx;
 523         struct ena_adapter *adapter;
 524         int nb_queues;
 525         int rc, i;
 526         bool wd_state;
 527
 528         adapter = (struct ena_adapter *)(dev->data->dev_private);
 529         ena_dev = &adapter->ena_dev;
 530         eth_dev = adapter->rte_dev;
 531         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 532         intr_handle = &pci_dev->intr_handle;
 533         nb_queues = eth_dev->data->nb_rx_queues;
 534
 535         ena_com_set_admin_running_state(ena_dev, false);
 536
 537         ena_com_dev_reset(ena_dev, adapter->reset_reason);
 538
 539         for (i = 0; i < nb_queues; i++)
 540                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 541
 542         ena_rx_queue_release_all(eth_dev);
 543         ena_tx_queue_release_all(eth_dev);
 544
 545         rte_intr_disable(intr_handle);
 546
 547         ena_com_abort_admin_commands(ena_dev);
 548         ena_com_wait_for_abort_completion(ena_dev);
 549         ena_com_admin_destroy(ena_dev);
 550         ena_com_mmio_reg_read_request_destroy(ena_dev);
 551
 552         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 553         if (rc) {
 554                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 555                 return rc;
 556         }
 557         adapter->wd_state = wd_state;
 558
 559         rte_intr_enable(intr_handle);
 560         ena_com_set_admin_polling_mode(ena_dev, false);
 561         ena_com_admin_aenq_enable(ena_dev);
 562
 563         for (i = 0; i < nb_queues; ++i)
 564                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 565                         mb_pool_rx[i]);
 566
 567         for (i = 0; i < nb_queues; ++i)
 568                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 569
 570         adapter->trigger_reset = false;
 571
 572         return 0;
 573 }
 574
 575 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 576                                struct rte_eth_rss_reta_entry64 *reta_conf,
 577                                uint16_t reta_size)
 578 {
 579         struct ena_adapter *adapter =
 580                 (struct ena_adapter *)(dev->data->dev_private);
 581         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 582         int ret, i;
 583         u16 entry_value;
 584         int conf_idx;
 585         int idx;
 586
 587         if ((reta_size == 0) || (reta_conf == NULL))
 588                 return -EINVAL;
 589
 590         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 591                 RTE_LOG(WARNING, PMD,
 592                         "indirection table %d is bigger than supported (%d)\n",
 593                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 594                 ret = -EINVAL;
 595                 goto err;
 596         }
 597
 598         for (i = 0 ; i < reta_size ; i++) {
 599                 /* each reta_conf is for 64 entries.
 600                  * to support 128 we use 2 conf of 64
 601                  */
 602                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 603                 idx = i % RTE_RETA_GROUP_SIZE;
 604                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 605                         entry_value =
 606                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 607                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 608                                                                 i,
 609                                                                 entry_value);
 610                         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 611                                 RTE_LOG(ERR, PMD,
 612                                         "Cannot fill indirect table\n");
 613                                 ret = -ENOTSUP;
 614                                 goto err;
 615                         }
 616                 }
 617         }
 618
 619         ret = ena_com_indirect_table_set(ena_dev);
 620         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 621                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 622                 ret = -ENOTSUP;
 623                 goto err;
 624         }
 625
 626         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 627                 __func__, reta_size, adapter->rte_dev->data->port_id);
 628 err:
 629         return ret;
 630 }
 631
 632 /* Query redirection table. */
 633 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 634                               struct rte_eth_rss_reta_entry64 *reta_conf,
 635                               uint16_t reta_size)
 636 {
 637         struct ena_adapter *adapter =
 638                 (struct ena_adapter *)(dev->data->dev_private);
 639         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 640         int ret;
 641         int i;
 642         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 643         int reta_conf_idx;
 644         int reta_idx;
 645
 646         if (reta_size == 0 || reta_conf == NULL ||
 647             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 648                 return -EINVAL;
 649
 650         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 651         if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
 652                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 653                 ret = -ENOTSUP;
 654                 goto err;
 655         }
 656
 657         for (i = 0 ; i < reta_size ; i++) {
 658                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 659                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 660                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 661                         reta_conf[reta_conf_idx].reta[reta_idx] =
 662                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 663         }
 664 err:
 665         return ret;
 666 }
 667
 668 static int ena_rss_init_default(struct ena_adapter *adapter)
 669 {
 670         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 671         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 672         int rc, i;
 673         u32 val;
 674
 675         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 676         if (unlikely(rc)) {
 677                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 678                 goto err_rss_init;
 679         }
 680
 681         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 682                 val = i % nb_rx_queues;
 683                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 684                                                        ENA_IO_RXQ_IDX(val));
 685                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 686                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 687                         goto err_fill_indir;
 688                 }
 689         }
 690
 691         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 692                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 693         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 694                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 695                 goto err_fill_indir;
 696         }
 697
 698         rc = ena_com_set_default_hash_ctrl(ena_dev);
 699         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 700                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 701                 goto err_fill_indir;
 702         }
 703
 704         rc = ena_com_indirect_table_set(ena_dev);
 705         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 706                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 707                 goto err_fill_indir;
 708         }
 709         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 710                 adapter->rte_dev->data->port_id);
 711
 712         return 0;
 713
 714 err_fill_indir:
 715         ena_com_rss_destroy(ena_dev);
 716 err_rss_init:
 717
 718         return rc;
 719 }
 720
 721 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 722 {
 723         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 724         int nb_queues = dev->data->nb_rx_queues;
 725         int i;
 726
 727         for (i = 0; i < nb_queues; i++)
 728                 ena_rx_queue_release(queues[i]);
 729 }
 730
 731 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 732 {
 733         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 734         int nb_queues = dev->data->nb_tx_queues;
 735         int i;
 736
 737         for (i = 0; i < nb_queues; i++)
 738                 ena_tx_queue_release(queues[i]);
 739 }
 740
 741 static void ena_rx_queue_release(void *queue)
 742 {
 743         struct ena_ring *ring = (struct ena_ring *)queue;
 744         struct ena_adapter *adapter = ring->adapter;
 745         int ena_qid;
 746
 747         ena_assert_msg(ring->configured,
 748                        "API violation - releasing not configured queue");
 749         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 750                        "API violation");
 751
 752         /* Destroy HW queue */
 753         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 754         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 755
 756         /* Free all bufs */
 757         ena_rx_queue_release_bufs(ring);
 758
 759         /* Free ring resources */
 760         if (ring->rx_buffer_info)
 761                 rte_free(ring->rx_buffer_info);
 762         ring->rx_buffer_info = NULL;
 763
 764         if (ring->empty_rx_reqs)
 765                 rte_free(ring->empty_rx_reqs);
 766         ring->empty_rx_reqs = NULL;
 767
 768         ring->configured = 0;
 769
 770         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 771                 ring->port_id, ring->id);
 772 }
 773
 774 static void ena_tx_queue_release(void *queue)
 775 {
 776         struct ena_ring *ring = (struct ena_ring *)queue;
 777         struct ena_adapter *adapter = ring->adapter;
 778         int ena_qid;
 779
 780         ena_assert_msg(ring->configured,
 781                        "API violation. Releasing not configured queue");
 782         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 783                        "API violation");
 784
 785         /* Destroy HW queue */
 786         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 787         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 788
 789         /* Free all bufs */
 790         ena_tx_queue_release_bufs(ring);
 791
 792         /* Free ring resources */
 793         if (ring->tx_buffer_info)
 794                 rte_free(ring->tx_buffer_info);
 795
 796         if (ring->empty_tx_reqs)
 797                 rte_free(ring->empty_tx_reqs);
 798
 799         ring->empty_tx_reqs = NULL;
 800         ring->tx_buffer_info = NULL;
 801
 802         ring->configured = 0;
 803
 804         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 805                 ring->port_id, ring->id);
 806 }
 807
 808 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 809 {
 810         unsigned int ring_mask = ring->ring_size - 1;
 811
 812         while (ring->next_to_clean != ring->next_to_use) {
 813                 struct rte_mbuf *m =
 814                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 815
 816                 if (m)
 817                         rte_mbuf_raw_free(m);
 818
 819                 ring->next_to_clean++;
 820         }
 821 }
 822
 823 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 824 {
 825         unsigned int i;
 826
 827         for (i = 0; i < ring->ring_size; ++i) {
 828                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 829
 830                 if (tx_buf->mbuf)
 831                         rte_pktmbuf_free(tx_buf->mbuf);
 832
 833                 ring->next_to_clean++;
 834         }
 835 }
 836
 837 static int ena_link_update(struct rte_eth_dev *dev,
 838                            __rte_unused int wait_to_complete)
 839 {
 840         struct rte_eth_link *link = &dev->data->dev_link;
 841         struct ena_adapter *adapter;
 842
 843         adapter = (struct ena_adapter *)(dev->data->dev_private);
 844
 845         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 846         link->link_speed = ETH_SPEED_NUM_10G;
 847         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 848
 849         return 0;
 850 }
 851
 852 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 853                                  enum ena_ring_type ring_type)
 854 {
 855         struct ena_adapter *adapter =
 856                 (struct ena_adapter *)(dev->data->dev_private);
 857         struct ena_ring *queues = NULL;
 858         int nb_queues;
 859         int i = 0;
 860         int rc = 0;
 861
 862         if (ring_type == ENA_RING_TYPE_RX) {
 863                 queues = adapter->rx_ring;
 864                 nb_queues = dev->data->nb_rx_queues;
 865         } else {
 866                 queues = adapter->tx_ring;
 867                 nb_queues = dev->data->nb_tx_queues;
 868         }
 869         for (i = 0; i < nb_queues; i++) {
 870                 if (queues[i].configured) {
 871                         if (ring_type == ENA_RING_TYPE_RX) {
 872                                 ena_assert_msg(
 873                                         dev->data->rx_queues[i] == &queues[i],
 874                                         "Inconsistent state of rx queues\n");
 875                         } else {
 876                                 ena_assert_msg(
 877                                         dev->data->tx_queues[i] == &queues[i],
 878                                         "Inconsistent state of tx queues\n");
 879                         }
 880
 881                         rc = ena_queue_restart(&queues[i]);
 882
 883                         if (rc) {
 884                                 PMD_INIT_LOG(ERR,
 885                                              "failed to restart queue %d type(%d)",
 886                                              i, ring_type);
 887                                 return -1;
 888                         }
 889                 }
 890         }
 891
 892         return 0;
 893 }
 894
 895 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 896 {
 897         uint32_t max_frame_len = adapter->max_mtu;
 898
 899         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 900             DEV_RX_OFFLOAD_JUMBO_FRAME)
 901                 max_frame_len =
 902                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 903
 904         return max_frame_len;
 905 }
 906
 907 static int ena_check_valid_conf(struct ena_adapter *adapter)
 908 {
 909         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 910
 911         if (max_frame_len > adapter->max_mtu) {
 912                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 913                 return -1;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static int
 920 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 921                     u16 *max_tx_sgl_size,
 922                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 923 {
 924         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 925
 926         queue_size = RTE_MIN(queue_size,
 927                              get_feat_ctx->max_queues.max_cq_depth);
 928         queue_size = RTE_MIN(queue_size,
 929                              get_feat_ctx->max_queues.max_sq_depth);
 930
 931         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 932                 queue_size = RTE_MIN(queue_size,
 933                                      get_feat_ctx->max_queues.max_llq_depth);
 934
 935         /* Round down to power of 2 */
 936         if (!rte_is_power_of_2(queue_size))
 937                 queue_size = rte_align32pow2(queue_size >> 1);
 938
 939         if (unlikely(queue_size == 0)) {
 940                 PMD_INIT_LOG(ERR, "Invalid queue size");
 941                 return -EFAULT;
 942         }
 943
 944         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 945                 get_feat_ctx->max_queues.max_packet_tx_descs);
 946
 947         return queue_size;
 948 }
 949
 950 static void ena_stats_restart(struct rte_eth_dev *dev)
 951 {
 952         struct ena_adapter *adapter =
 953                 (struct ena_adapter *)(dev->data->dev_private);
 954
 955         rte_atomic64_init(&adapter->drv_stats->ierrors);
 956         rte_atomic64_init(&adapter->drv_stats->oerrors);
 957         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 958 }
 959
 960 static int ena_stats_get(struct rte_eth_dev *dev,
 961                           struct rte_eth_stats *stats)
 962 {
 963         struct ena_admin_basic_stats ena_stats;
 964         struct ena_adapter *adapter =
 965                 (struct ena_adapter *)(dev->data->dev_private);
 966         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 967         int rc;
 968
 969         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 970                 return -ENOTSUP;
 971
 972         memset(&ena_stats, 0, sizeof(ena_stats));
 973         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 974         if (unlikely(rc)) {
 975                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 976                 return rc;
 977         }
 978
 979         /* Set of basic statistics from ENA */
 980         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 981                                           ena_stats.rx_pkts_low);
 982         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 983                                           ena_stats.tx_pkts_low);
 984         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 985                                         ena_stats.rx_bytes_low);
 986         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 987                                         ena_stats.tx_bytes_low);
 988         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 989                                          ena_stats.rx_drops_low);
 990
 991         /* Driver related stats */
 992         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 993         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 994         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 995         return 0;
 996 }
 997
 998 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 999 {
1000         struct ena_adapter *adapter;
1001         struct ena_com_dev *ena_dev;
1002         int rc = 0;
1003
1004         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1005         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1006         adapter = (struct ena_adapter *)(dev->data->dev_private);
1007
1008         ena_dev = &adapter->ena_dev;
1009         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1010
1011         if (mtu > ena_get_mtu_conf(adapter)) {
1012                 RTE_LOG(ERR, PMD,
1013                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
1014                         mtu, ena_get_mtu_conf(adapter));
1015                 rc = -EINVAL;
1016                 goto err;
1017         }
1018
1019         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1020         if (rc)
1021                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1022         else
1023                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1024
1025 err:
1026         return rc;
1027 }
1028
1029 static int ena_start(struct rte_eth_dev *dev)
1030 {
1031         struct ena_adapter *adapter =
1032                 (struct ena_adapter *)(dev->data->dev_private);
1033         uint64_t ticks;
1034         int rc = 0;
1035
1036         rc = ena_check_valid_conf(adapter);
1037         if (rc)
1038                 return rc;
1039
1040         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1041         if (rc)
1042                 return rc;
1043
1044         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1045         if (rc)
1046                 return rc;
1047
1048         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1049             ETH_MQ_RX_RSS_FLAG) {
1050                 rc = ena_rss_init_default(adapter);
1051                 if (rc)
1052                         return rc;
1053         }
1054
1055         ena_stats_restart(dev);
1056
1057         adapter->timestamp_wd = rte_get_timer_cycles();
1058         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1059
1060         ticks = rte_get_timer_hz();
1061         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1062                         ena_timer_wd_callback, adapter);
1063
1064         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1065
1066         return 0;
1067 }
1068
1069 static void ena_stop(struct rte_eth_dev *dev)
1070 {
1071         struct ena_adapter *adapter =
1072                 (struct ena_adapter *)(dev->data->dev_private);
1073
1074         rte_timer_stop_sync(&adapter->timer_wd);
1075
1076         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1077 }
1078
1079 static int ena_queue_restart(struct ena_ring *ring)
1080 {
1081         int rc, bufs_num;
1082
1083         ena_assert_msg(ring->configured == 1,
1084                        "Trying to restart unconfigured queue\n");
1085
1086         ring->next_to_clean = 0;
1087         ring->next_to_use = 0;
1088
1089         if (ring->type == ENA_RING_TYPE_TX)
1090                 return 0;
1091
1092         bufs_num = ring->ring_size - 1;
1093         rc = ena_populate_rx_queue(ring, bufs_num);
1094         if (rc != bufs_num) {
1095                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1096                 return (-1);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1103                               uint16_t queue_idx,
1104                               uint16_t nb_desc,
1105                               __rte_unused unsigned int socket_id,
1106                               const struct rte_eth_txconf *tx_conf)
1107 {
1108         struct ena_com_create_io_ctx ctx =
1109                 /* policy set to _HOST just to satisfy icc compiler */
1110                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1111                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
1112         struct ena_ring *txq = NULL;
1113         struct ena_adapter *adapter =
1114                 (struct ena_adapter *)(dev->data->dev_private);
1115         unsigned int i;
1116         int ena_qid;
1117         int rc;
1118         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1119
1120         txq = &adapter->tx_ring[queue_idx];
1121
1122         if (txq->configured) {
1123                 RTE_LOG(CRIT, PMD,
1124                         "API violation. Queue %d is already configured\n",
1125                         queue_idx);
1126                 return -1;
1127         }
1128
1129         if (!rte_is_power_of_2(nb_desc)) {
1130                 RTE_LOG(ERR, PMD,
1131                         "Unsupported size of RX queue: %d is not a power of 2.",
1132                         nb_desc);
1133                 return -EINVAL;
1134         }
1135
1136         if (nb_desc > adapter->tx_ring_size) {
1137                 RTE_LOG(ERR, PMD,
1138                         "Unsupported size of TX queue (max size: %d)\n",
1139                         adapter->tx_ring_size);
1140                 return -EINVAL;
1141         }
1142
1143         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1144
1145         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1146         ctx.qid = ena_qid;
1147         ctx.msix_vector = -1; /* admin interrupts not used */
1148         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1149         ctx.queue_size = adapter->tx_ring_size;
1150         ctx.numa_node = ena_cpu_to_node(queue_idx);
1151
1152         rc = ena_com_create_io_queue(ena_dev, &ctx);
1153         if (rc) {
1154                 RTE_LOG(ERR, PMD,
1155                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1156                         queue_idx, ena_qid, rc);
1157         }
1158         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1159         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1160
1161         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1162                                      &txq->ena_com_io_sq,
1163                                      &txq->ena_com_io_cq);
1164         if (rc) {
1165                 RTE_LOG(ERR, PMD,
1166                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1167                         queue_idx, rc);
1168                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1169                 goto err;
1170         }
1171
1172         txq->port_id = dev->data->port_id;
1173         txq->next_to_clean = 0;
1174         txq->next_to_use = 0;
1175         txq->ring_size = nb_desc;
1176
1177         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1178                                           sizeof(struct ena_tx_buffer) *
1179                                           txq->ring_size,
1180                                           RTE_CACHE_LINE_SIZE);
1181         if (!txq->tx_buffer_info) {
1182                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1183                 return -ENOMEM;
1184         }
1185
1186         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1187                                          sizeof(u16) * txq->ring_size,
1188                                          RTE_CACHE_LINE_SIZE);
1189         if (!txq->empty_tx_reqs) {
1190                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1191                 rte_free(txq->tx_buffer_info);
1192                 return -ENOMEM;
1193         }
1194         for (i = 0; i < txq->ring_size; i++)
1195                 txq->empty_tx_reqs[i] = i;
1196
1197         if (tx_conf != NULL) {
1198                 txq->offloads =
1199                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1200         }
1201
1202         /* Store pointer to this queue in upper layer */
1203         txq->configured = 1;
1204         dev->data->tx_queues[queue_idx] = txq;
1205 err:
1206         return rc;
1207 }
1208
1209 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1210                               uint16_t queue_idx,
1211                               uint16_t nb_desc,
1212                               __rte_unused unsigned int socket_id,
1213                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1214                               struct rte_mempool *mp)
1215 {
1216         struct ena_com_create_io_ctx ctx =
1217                 /* policy set to _HOST just to satisfy icc compiler */
1218                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1219                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1220         struct ena_adapter *adapter =
1221                 (struct ena_adapter *)(dev->data->dev_private);
1222         struct ena_ring *rxq = NULL;
1223         uint16_t ena_qid = 0;
1224         int i, rc = 0;
1225         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1226
1227         rxq = &adapter->rx_ring[queue_idx];
1228         if (rxq->configured) {
1229                 RTE_LOG(CRIT, PMD,
1230                         "API violation. Queue %d is already configured\n",
1231                         queue_idx);
1232                 return -1;
1233         }
1234
1235         if (!rte_is_power_of_2(nb_desc)) {
1236                 RTE_LOG(ERR, PMD,
1237                         "Unsupported size of TX queue: %d is not a power of 2.",
1238                         nb_desc);
1239                 return -EINVAL;
1240         }
1241
1242         if (nb_desc > adapter->rx_ring_size) {
1243                 RTE_LOG(ERR, PMD,
1244                         "Unsupported size of RX queue (max size: %d)\n",
1245                         adapter->rx_ring_size);
1246                 return -EINVAL;
1247         }
1248
1249         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1250
1251         ctx.qid = ena_qid;
1252         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1253         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1254         ctx.msix_vector = -1; /* admin interrupts not used */
1255         ctx.queue_size = adapter->rx_ring_size;
1256         ctx.numa_node = ena_cpu_to_node(queue_idx);
1257
1258         rc = ena_com_create_io_queue(ena_dev, &ctx);
1259         if (rc)
1260                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1261                         queue_idx, rc);
1262
1263         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1264         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1265
1266         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1267                                      &rxq->ena_com_io_sq,
1268                                      &rxq->ena_com_io_cq);
1269         if (rc) {
1270                 RTE_LOG(ERR, PMD,
1271                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1272                         queue_idx, rc);
1273                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1274         }
1275
1276         rxq->port_id = dev->data->port_id;
1277         rxq->next_to_clean = 0;
1278         rxq->next_to_use = 0;
1279         rxq->ring_size = nb_desc;
1280         rxq->mb_pool = mp;
1281
1282         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1283                                           sizeof(struct rte_mbuf *) * nb_desc,
1284                                           RTE_CACHE_LINE_SIZE);
1285         if (!rxq->rx_buffer_info) {
1286                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1287                 return -ENOMEM;
1288         }
1289
1290         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1291                                          sizeof(uint16_t) * nb_desc,
1292                                          RTE_CACHE_LINE_SIZE);
1293         if (!rxq->empty_rx_reqs) {
1294                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1295                 rte_free(rxq->rx_buffer_info);
1296                 rxq->rx_buffer_info = NULL;
1297                 return -ENOMEM;
1298         }
1299
1300         for (i = 0; i < nb_desc; i++)
1301                 rxq->empty_tx_reqs[i] = i;
1302
1303         /* Store pointer to this queue in upper layer */
1304         rxq->configured = 1;
1305         dev->data->rx_queues[queue_idx] = rxq;
1306
1307         return rc;
1308 }
1309
1310 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1311 {
1312         unsigned int i;
1313         int rc;
1314         uint16_t ring_size = rxq->ring_size;
1315         uint16_t ring_mask = ring_size - 1;
1316         uint16_t next_to_use = rxq->next_to_use;
1317         uint16_t in_use, req_id;
1318         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1319
1320         if (unlikely(!count))
1321                 return 0;
1322
1323         in_use = rxq->next_to_use - rxq->next_to_clean;
1324         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1325
1326         count = RTE_MIN(count,
1327                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1328
1329         /* get resources for incoming packets */
1330         rc = rte_mempool_get_bulk(rxq->mb_pool,
1331                                   (void **)(&mbufs[next_to_use & ring_mask]),
1332                                   count);
1333         if (unlikely(rc < 0)) {
1334                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1335                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1336                 return 0;
1337         }
1338
1339         for (i = 0; i < count; i++) {
1340                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1341                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1342                 struct ena_com_buf ebuf;
1343
1344                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1345
1346                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1347                 /* prepare physical address for DMA transaction */
1348                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1349                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1350                 /* pass resource to device */
1351                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1352                                                 &ebuf, req_id);
1353                 if (unlikely(rc)) {
1354                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1355                                              count - i);
1356                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1357                         break;
1358                 }
1359                 next_to_use++;
1360         }
1361
1362         /* When we submitted free recources to device... */
1363         if (likely(i > 0)) {
1364                 /* ...let HW know that it can fill buffers with data */
1365                 rte_wmb();
1366                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1367
1368                 rxq->next_to_use = next_to_use;
1369         }
1370
1371         return i;
1372 }
1373
1374 static int ena_device_init(struct ena_com_dev *ena_dev,
1375                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1376                            bool *wd_state)
1377 {
1378         uint32_t aenq_groups;
1379         int rc;
1380         bool readless_supported;
1381
1382         /* Initialize mmio registers */
1383         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1384         if (rc) {
1385                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1386                 return rc;
1387         }
1388
1389         /* The PCIe configuration space revision id indicate if mmio reg
1390          * read is disabled.
1391          */
1392         readless_supported =
1393                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1394                                & ENA_MMIO_DISABLE_REG_READ);
1395         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1396
1397         /* reset device */
1398         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1399         if (rc) {
1400                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1401                 goto err_mmio_read_less;
1402         }
1403
1404         /* check FW version */
1405         rc = ena_com_validate_version(ena_dev);
1406         if (rc) {
1407                 RTE_LOG(ERR, PMD, "device version is too low\n");
1408                 goto err_mmio_read_less;
1409         }
1410
1411         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1412
1413         /* ENA device administration layer init */
1414         rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
1415         if (rc) {
1416                 RTE_LOG(ERR, PMD,
1417                         "cannot initialize ena admin queue with device\n");
1418                 goto err_mmio_read_less;
1419         }
1420
1421         /* To enable the msix interrupts the driver needs to know the number
1422          * of queues. So the driver uses polling mode to retrieve this
1423          * information.
1424          */
1425         ena_com_set_admin_polling_mode(ena_dev, true);
1426
1427         ena_config_host_info(ena_dev);
1428
1429         /* Get Device Attributes and features */
1430         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1431         if (rc) {
1432                 RTE_LOG(ERR, PMD,
1433                         "cannot get attribute for ena device rc= %d\n", rc);
1434                 goto err_admin_init;
1435         }
1436
1437         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1438                       BIT(ENA_ADMIN_NOTIFICATION) |
1439                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1440                       BIT(ENA_ADMIN_FATAL_ERROR) |
1441                       BIT(ENA_ADMIN_WARNING);
1442
1443         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1444         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1445         if (rc) {
1446                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1447                 goto err_admin_init;
1448         }
1449
1450         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1451
1452         return 0;
1453
1454 err_admin_init:
1455         ena_com_admin_destroy(ena_dev);
1456
1457 err_mmio_read_less:
1458         ena_com_mmio_reg_read_request_destroy(ena_dev);
1459
1460         return rc;
1461 }
1462
1463 static void ena_interrupt_handler_rte(void *cb_arg)
1464 {
1465         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1466         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1467
1468         ena_com_admin_q_comp_intr_handler(ena_dev);
1469         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1470                 ena_com_aenq_intr_handler(ena_dev, adapter);
1471 }
1472
1473 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1474 {
1475         if (!adapter->wd_state)
1476                 return;
1477
1478         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1479                 return;
1480
1481         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1482             adapter->keep_alive_timeout)) {
1483                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1484                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1485                 adapter->trigger_reset = true;
1486         }
1487 }
1488
1489 /* Check if admin queue is enabled */
1490 static void check_for_admin_com_state(struct ena_adapter *adapter)
1491 {
1492         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1493                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1494                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1495                 adapter->trigger_reset = true;
1496         }
1497 }
1498
1499 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1500                                   void *arg)
1501 {
1502         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1503         struct rte_eth_dev *dev = adapter->rte_dev;
1504
1505         check_for_missing_keep_alive(adapter);
1506         check_for_admin_com_state(adapter);
1507
1508         if (unlikely(adapter->trigger_reset)) {
1509                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1510                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1511                         NULL);
1512         }
1513 }
1514
1515 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1516                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1517 {
1518         int io_sq_num, io_cq_num, io_queue_num;
1519
1520         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1521         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1522
1523         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1524
1525         if (unlikely(io_queue_num == 0)) {
1526                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1527                 return -EFAULT;
1528         }
1529
1530         return io_queue_num;
1531 }
1532
1533 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1534 {
1535         struct rte_pci_device *pci_dev;
1536         struct rte_intr_handle *intr_handle;
1537         struct ena_adapter *adapter =
1538                 (struct ena_adapter *)(eth_dev->data->dev_private);
1539         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1540         struct ena_com_dev_get_features_ctx get_feat_ctx;
1541         int queue_size, rc;
1542         u16 tx_sgl_size = 0;
1543
1544         static int adapters_found;
1545         bool wd_state;
1546
1547         memset(adapter, 0, sizeof(struct ena_adapter));
1548         ena_dev = &adapter->ena_dev;
1549
1550         eth_dev->dev_ops = &ena_dev_ops;
1551         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1552         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1553         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1554         adapter->rte_eth_dev_data = eth_dev->data;
1555         adapter->rte_dev = eth_dev;
1556
1557         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1558                 return 0;
1559
1560         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1561         adapter->pdev = pci_dev;
1562
1563         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1564                      pci_dev->addr.domain,
1565                      pci_dev->addr.bus,
1566                      pci_dev->addr.devid,
1567                      pci_dev->addr.function);
1568
1569         intr_handle = &pci_dev->intr_handle;
1570
1571         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1572         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1573
1574         if (!adapter->regs) {
1575                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1576                              ENA_REGS_BAR);
1577                 return -ENXIO;
1578         }
1579
1580         ena_dev->reg_bar = adapter->regs;
1581         ena_dev->dmadev = adapter->pdev;
1582
1583         adapter->id_number = adapters_found;
1584
1585         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1586                  adapter->id_number);
1587
1588         /* device specific initialization routine */
1589         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1590         if (rc) {
1591                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1592                 return -1;
1593         }
1594         adapter->wd_state = wd_state;
1595
1596         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1597         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1598                                                     &get_feat_ctx);
1599
1600         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1601         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1602                 return -EFAULT;
1603
1604         adapter->tx_ring_size = queue_size;
1605         adapter->rx_ring_size = queue_size;
1606
1607         adapter->max_tx_sgl_size = tx_sgl_size;
1608
1609         /* prepare ring structures */
1610         ena_init_rings(adapter);
1611
1612         ena_config_debug_area(adapter);
1613
1614         /* Set max MTU for this device */
1615         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1616
1617         /* set device support for TSO */
1618         adapter->tso4_supported = get_feat_ctx.offload.tx &
1619                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1620
1621         /* Copy MAC address and point DPDK to it */
1622         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1623         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1624                         (struct ether_addr *)adapter->mac_addr);
1625
1626         adapter->drv_stats = rte_zmalloc("adapter stats",
1627                                          sizeof(*adapter->drv_stats),
1628                                          RTE_CACHE_LINE_SIZE);
1629         if (!adapter->drv_stats) {
1630                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1631                 return -ENOMEM;
1632         }
1633
1634         rte_intr_callback_register(intr_handle,
1635                                    ena_interrupt_handler_rte,
1636                                    adapter);
1637         rte_intr_enable(intr_handle);
1638         ena_com_set_admin_polling_mode(ena_dev, false);
1639         ena_com_admin_aenq_enable(ena_dev);
1640
1641         if (adapters_found == 0)
1642                 rte_timer_subsystem_init();
1643         rte_timer_init(&adapter->timer_wd);
1644
1645         adapters_found++;
1646         adapter->state = ENA_ADAPTER_STATE_INIT;
1647
1648         return 0;
1649 }
1650
1651 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1652 {
1653         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1654         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1655         struct ena_adapter *adapter =
1656                 (struct ena_adapter *)(eth_dev->data->dev_private);
1657
1658         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1659                 return -EPERM;
1660
1661         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1662                 ena_close(eth_dev);
1663
1664         eth_dev->dev_ops = NULL;
1665         eth_dev->rx_pkt_burst = NULL;
1666         eth_dev->tx_pkt_burst = NULL;
1667         eth_dev->tx_pkt_prepare = NULL;
1668
1669         rte_free(adapter->drv_stats);
1670         adapter->drv_stats = NULL;
1671
1672         rte_intr_disable(intr_handle);
1673         rte_intr_callback_unregister(intr_handle,
1674                                      ena_interrupt_handler_rte,
1675                                      adapter);
1676
1677         adapter->state = ENA_ADAPTER_STATE_FREE;
1678
1679         return 0;
1680 }
1681
1682 static int ena_dev_configure(struct rte_eth_dev *dev)
1683 {
1684         struct ena_adapter *adapter =
1685                 (struct ena_adapter *)(dev->data->dev_private);
1686
1687         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1688
1689         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1690         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1691         return 0;
1692 }
1693
1694 static void ena_init_rings(struct ena_adapter *adapter)
1695 {
1696         int i;
1697
1698         for (i = 0; i < adapter->num_queues; i++) {
1699                 struct ena_ring *ring = &adapter->tx_ring[i];
1700
1701                 ring->configured = 0;
1702                 ring->type = ENA_RING_TYPE_TX;
1703                 ring->adapter = adapter;
1704                 ring->id = i;
1705                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1706                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1707                 ring->sgl_size = adapter->max_tx_sgl_size;
1708         }
1709
1710         for (i = 0; i < adapter->num_queues; i++) {
1711                 struct ena_ring *ring = &adapter->rx_ring[i];
1712
1713                 ring->configured = 0;
1714                 ring->type = ENA_RING_TYPE_RX;
1715                 ring->adapter = adapter;
1716                 ring->id = i;
1717         }
1718 }
1719
1720 static void ena_infos_get(struct rte_eth_dev *dev,
1721                           struct rte_eth_dev_info *dev_info)
1722 {
1723         struct ena_adapter *adapter;
1724         struct ena_com_dev *ena_dev;
1725         struct ena_com_dev_get_features_ctx feat;
1726         uint64_t rx_feat = 0, tx_feat = 0;
1727         int rc = 0;
1728
1729         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1730         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1731         adapter = (struct ena_adapter *)(dev->data->dev_private);
1732
1733         ena_dev = &adapter->ena_dev;
1734         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1735
1736         dev_info->speed_capa =
1737                         ETH_LINK_SPEED_1G   |
1738                         ETH_LINK_SPEED_2_5G |
1739                         ETH_LINK_SPEED_5G   |
1740                         ETH_LINK_SPEED_10G  |
1741                         ETH_LINK_SPEED_25G  |
1742                         ETH_LINK_SPEED_40G  |
1743                         ETH_LINK_SPEED_50G  |
1744                         ETH_LINK_SPEED_100G;
1745
1746         /* Get supported features from HW */
1747         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1748         if (unlikely(rc)) {
1749                 RTE_LOG(ERR, PMD,
1750                         "Cannot get attribute for ena device rc= %d\n", rc);
1751                 return;
1752         }
1753
1754         /* Set Tx & Rx features available for device */
1755         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1756                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1757
1758         if (feat.offload.tx &
1759             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1760                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1761                         DEV_TX_OFFLOAD_UDP_CKSUM |
1762                         DEV_TX_OFFLOAD_TCP_CKSUM;
1763
1764         if (feat.offload.rx_supported &
1765             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1766                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1767                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1768                         DEV_RX_OFFLOAD_TCP_CKSUM;
1769
1770         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1771
1772         /* Inform framework about available features */
1773         dev_info->rx_offload_capa = rx_feat;
1774         dev_info->rx_queue_offload_capa = rx_feat;
1775         dev_info->tx_offload_capa = tx_feat;
1776         dev_info->tx_queue_offload_capa = tx_feat;
1777
1778         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1779         dev_info->max_rx_pktlen  = adapter->max_mtu;
1780         dev_info->max_mac_addrs = 1;
1781
1782         dev_info->max_rx_queues = adapter->num_queues;
1783         dev_info->max_tx_queues = adapter->num_queues;
1784         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1785
1786         adapter->tx_supported_offloads = tx_feat;
1787         adapter->rx_supported_offloads = rx_feat;
1788
1789         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1790         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1791
1792         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1793         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1794         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1795                                         feat.max_queues.max_packet_tx_descs);
1796         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1797                                         feat.max_queues.max_packet_tx_descs);
1798 }
1799
1800 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1801                                   uint16_t nb_pkts)
1802 {
1803         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1804         unsigned int ring_size = rx_ring->ring_size;
1805         unsigned int ring_mask = ring_size - 1;
1806         uint16_t next_to_clean = rx_ring->next_to_clean;
1807         uint16_t desc_in_use = 0;
1808         uint16_t req_id;
1809         unsigned int recv_idx = 0;
1810         struct rte_mbuf *mbuf = NULL;
1811         struct rte_mbuf *mbuf_head = NULL;
1812         struct rte_mbuf *mbuf_prev = NULL;
1813         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1814         unsigned int completed;
1815
1816         struct ena_com_rx_ctx ena_rx_ctx;
1817         int rc = 0;
1818
1819         /* Check adapter state */
1820         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1821                 RTE_LOG(ALERT, PMD,
1822                         "Trying to receive pkts while device is NOT running\n");
1823                 return 0;
1824         }
1825
1826         desc_in_use = rx_ring->next_to_use - next_to_clean;
1827         if (unlikely(nb_pkts > desc_in_use))
1828                 nb_pkts = desc_in_use;
1829
1830         for (completed = 0; completed < nb_pkts; completed++) {
1831                 int segments = 0;
1832
1833                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1834                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1835                 ena_rx_ctx.descs = 0;
1836                 /* receive packet context */
1837                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1838                                     rx_ring->ena_com_io_sq,
1839                                     &ena_rx_ctx);
1840                 if (unlikely(rc)) {
1841                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1842                         return 0;
1843                 }
1844
1845                 if (unlikely(ena_rx_ctx.descs == 0))
1846                         break;
1847
1848                 while (segments < ena_rx_ctx.descs) {
1849                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1850                         rc = validate_rx_req_id(rx_ring, req_id);
1851                         if (unlikely(rc))
1852                                 break;
1853
1854                         mbuf = rx_buff_info[req_id];
1855                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1856                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1857                         mbuf->refcnt = 1;
1858                         mbuf->next = NULL;
1859                         if (unlikely(segments == 0)) {
1860                                 mbuf->nb_segs = ena_rx_ctx.descs;
1861                                 mbuf->port = rx_ring->port_id;
1862                                 mbuf->pkt_len = 0;
1863                                 mbuf_head = mbuf;
1864                         } else {
1865                                 /* for multi-segment pkts create mbuf chain */
1866                                 mbuf_prev->next = mbuf;
1867                         }
1868                         mbuf_head->pkt_len += mbuf->data_len;
1869
1870                         mbuf_prev = mbuf;
1871                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1872                                 req_id;
1873                         segments++;
1874                         next_to_clean++;
1875                 }
1876
1877                 /* fill mbuf attributes if any */
1878                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1879                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1880
1881                 /* pass to DPDK application head mbuf */
1882                 rx_pkts[recv_idx] = mbuf_head;
1883                 recv_idx++;
1884         }
1885
1886         rx_ring->next_to_clean = next_to_clean;
1887
1888         desc_in_use = desc_in_use - completed + 1;
1889         /* Burst refill to save doorbells, memory barriers, const interval */
1890         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1891                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1892
1893         return recv_idx;
1894 }
1895
1896 static uint16_t
1897 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1898                 uint16_t nb_pkts)
1899 {
1900         int32_t ret;
1901         uint32_t i;
1902         struct rte_mbuf *m;
1903         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1904         struct ipv4_hdr *ip_hdr;
1905         uint64_t ol_flags;
1906         uint16_t frag_field;
1907
1908         for (i = 0; i != nb_pkts; i++) {
1909                 m = tx_pkts[i];
1910                 ol_flags = m->ol_flags;
1911
1912                 if (!(ol_flags & PKT_TX_IPV4))
1913                         continue;
1914
1915                 /* If there was not L2 header length specified, assume it is
1916                  * length of the ethernet header.
1917                  */
1918                 if (unlikely(m->l2_len == 0))
1919                         m->l2_len = sizeof(struct ether_hdr);
1920
1921                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1922                                                  m->l2_len);
1923                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1924
1925                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1926                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1927
1928                         /* If IPv4 header has DF flag enabled and TSO support is
1929                          * disabled, partial chcecksum should not be calculated.
1930                          */
1931                         if (!tx_ring->adapter->tso4_supported)
1932                                 continue;
1933                 }
1934
1935                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1936                                 (ol_flags & PKT_TX_L4_MASK) ==
1937                                 PKT_TX_SCTP_CKSUM) {
1938                         rte_errno = -ENOTSUP;
1939                         return i;
1940                 }
1941
1942 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1943                 ret = rte_validate_tx_offload(m);
1944                 if (ret != 0) {
1945                         rte_errno = ret;
1946                         return i;
1947                 }
1948 #endif
1949
1950                 /* In case we are supposed to TSO and have DF not set (DF=0)
1951                  * hardware must be provided with partial checksum, otherwise
1952                  * it will take care of necessary calculations.
1953                  */
1954
1955                 ret = rte_net_intel_cksum_flags_prepare(m,
1956                         ol_flags & ~PKT_TX_TCP_SEG);
1957                 if (ret != 0) {
1958                         rte_errno = ret;
1959                         return i;
1960                 }
1961         }
1962
1963         return i;
1964 }
1965
1966 static void ena_update_hints(struct ena_adapter *adapter,
1967                              struct ena_admin_ena_hw_hints *hints)
1968 {
1969         if (hints->admin_completion_tx_timeout)
1970                 adapter->ena_dev.admin_queue.completion_timeout =
1971                         hints->admin_completion_tx_timeout * 1000;
1972
1973         if (hints->mmio_read_timeout)
1974                 /* convert to usec */
1975                 adapter->ena_dev.mmio_read.reg_read_to =
1976                         hints->mmio_read_timeout * 1000;
1977
1978         if (hints->driver_watchdog_timeout) {
1979                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1980                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
1981                 else
1982                         // Convert msecs to ticks
1983                         adapter->keep_alive_timeout =
1984                                 (hints->driver_watchdog_timeout *
1985                                 rte_get_timer_hz()) / 1000;
1986         }
1987 }
1988
1989 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
1990                                         struct rte_mbuf *mbuf)
1991 {
1992         int num_segments, rc;
1993
1994         num_segments = mbuf->nb_segs;
1995
1996         if (likely(num_segments < tx_ring->sgl_size))
1997                 return 0;
1998
1999         rc = rte_pktmbuf_linearize(mbuf);
2000         if (unlikely(rc))
2001                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2002
2003         return rc;
2004 }
2005
2006 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2007                                   uint16_t nb_pkts)
2008 {
2009         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2010         uint16_t next_to_use = tx_ring->next_to_use;
2011         uint16_t next_to_clean = tx_ring->next_to_clean;
2012         struct rte_mbuf *mbuf;
2013         unsigned int ring_size = tx_ring->ring_size;
2014         unsigned int ring_mask = ring_size - 1;
2015         struct ena_com_tx_ctx ena_tx_ctx;
2016         struct ena_tx_buffer *tx_info;
2017         struct ena_com_buf *ebuf;
2018         uint16_t rc, req_id, total_tx_descs = 0;
2019         uint16_t sent_idx = 0, empty_tx_reqs;
2020         int nb_hw_desc;
2021
2022         /* Check adapter state */
2023         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2024                 RTE_LOG(ALERT, PMD,
2025                         "Trying to xmit pkts while device is NOT running\n");
2026                 return 0;
2027         }
2028
2029         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2030         if (nb_pkts > empty_tx_reqs)
2031                 nb_pkts = empty_tx_reqs;
2032
2033         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2034                 mbuf = tx_pkts[sent_idx];
2035
2036                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2037                 if (unlikely(rc))
2038                         break;
2039
2040                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2041                 tx_info = &tx_ring->tx_buffer_info[req_id];
2042                 tx_info->mbuf = mbuf;
2043                 tx_info->num_of_bufs = 0;
2044                 ebuf = tx_info->bufs;
2045
2046                 /* Prepare TX context */
2047                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2048                 memset(&ena_tx_ctx.ena_meta, 0x0,
2049                        sizeof(struct ena_com_tx_meta));
2050                 ena_tx_ctx.ena_bufs = ebuf;
2051                 ena_tx_ctx.req_id = req_id;
2052                 if (tx_ring->tx_mem_queue_type ==
2053                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2054                         /* prepare the push buffer with
2055                          * virtual address of the data
2056                          */
2057                         ena_tx_ctx.header_len =
2058                                 RTE_MIN(mbuf->data_len,
2059                                         tx_ring->tx_max_header_size);
2060                         ena_tx_ctx.push_header =
2061                                 (void *)((char *)mbuf->buf_addr +
2062                                          mbuf->data_off);
2063                 } /* there's no else as we take advantage of memset zeroing */
2064
2065                 /* Set TX offloads flags, if applicable */
2066                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2067
2068                 if (unlikely(mbuf->ol_flags &
2069                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2070                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2071
2072                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2073
2074                 /* Process first segment taking into
2075                  * consideration pushed header
2076                  */
2077                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2078                         ebuf->paddr = mbuf->buf_iova +
2079                                       mbuf->data_off +
2080                                       ena_tx_ctx.header_len;
2081                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2082                         ebuf++;
2083                         tx_info->num_of_bufs++;
2084                 }
2085
2086                 while ((mbuf = mbuf->next) != NULL) {
2087                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2088                         ebuf->len = mbuf->data_len;
2089                         ebuf++;
2090                         tx_info->num_of_bufs++;
2091                 }
2092
2093                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2094
2095                 /* Write data to device */
2096                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2097                                         &ena_tx_ctx, &nb_hw_desc);
2098                 if (unlikely(rc))
2099                         break;
2100
2101                 tx_info->tx_descs = nb_hw_desc;
2102
2103                 next_to_use++;
2104         }
2105
2106         /* If there are ready packets to be xmitted... */
2107         if (sent_idx > 0) {
2108                 /* ...let HW do its best :-) */
2109                 rte_wmb();
2110                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2111
2112                 tx_ring->next_to_use = next_to_use;
2113         }
2114
2115         /* Clear complete packets  */
2116         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2117                 rc = validate_tx_req_id(tx_ring, req_id);
2118                 if (rc)
2119                         break;
2120
2121                 /* Get Tx info & store how many descs were processed  */
2122                 tx_info = &tx_ring->tx_buffer_info[req_id];
2123                 total_tx_descs += tx_info->tx_descs;
2124
2125                 /* Free whole mbuf chain  */
2126                 mbuf = tx_info->mbuf;
2127                 rte_pktmbuf_free(mbuf);
2128                 tx_info->mbuf = NULL;
2129
2130                 /* Put back descriptor to the ring for reuse */
2131                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2132                 next_to_clean++;
2133
2134                 /* If too many descs to clean, leave it for another run */
2135                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2136                         break;
2137         }
2138
2139         if (total_tx_descs > 0) {
2140                 /* acknowledge completion of sent packets */
2141                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2142                 tx_ring->next_to_clean = next_to_clean;
2143         }
2144
2145         return sent_idx;
2146 }
2147
2148 /*********************************************************************
2149  *  PMD configuration
2150  *********************************************************************/
2151 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2152         struct rte_pci_device *pci_dev)
2153 {
2154         return rte_eth_dev_pci_generic_probe(pci_dev,
2155                 sizeof(struct ena_adapter), eth_ena_dev_init);
2156 }
2157
2158 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2159 {
2160         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2161 }
2162
2163 static struct rte_pci_driver rte_ena_pmd = {
2164         .id_table = pci_id_ena_map,
2165         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2166         .probe = eth_ena_pci_probe,
2167         .remove = eth_ena_pci_remove,
2168 };
2169
2170 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2171 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2172 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2173
2174 RTE_INIT(ena_init_log);
2175 static void
2176 ena_init_log(void)
2177 {
2178         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2179         if (ena_logtype_init >= 0)
2180                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2181         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2182         if (ena_logtype_driver >= 0)
2183                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2184 }
2185
2186 /******************************************************************************
2187  ******************************** AENQ Handlers *******************************
2188  *****************************************************************************/
2189 static void ena_update_on_link_change(void *adapter_data,
2190                                       struct ena_admin_aenq_entry *aenq_e)
2191 {
2192         struct rte_eth_dev *eth_dev;
2193         struct ena_adapter *adapter;
2194         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2195         uint32_t status;
2196
2197         adapter = (struct ena_adapter *)adapter_data;
2198         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2199         eth_dev = adapter->rte_dev;
2200
2201         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2202         adapter->link_status = status;
2203
2204         ena_link_update(eth_dev, 0);
2205         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2206 }
2207
2208 static void ena_notification(void *data,
2209                              struct ena_admin_aenq_entry *aenq_e)
2210 {
2211         struct ena_adapter *adapter = (struct ena_adapter *)data;
2212         struct ena_admin_ena_hw_hints *hints;
2213
2214         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2215                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2216                         aenq_e->aenq_common_desc.group,
2217                         ENA_ADMIN_NOTIFICATION);
2218
2219         switch (aenq_e->aenq_common_desc.syndrom) {
2220         case ENA_ADMIN_UPDATE_HINTS:
2221                 hints = (struct ena_admin_ena_hw_hints *)
2222                         (&aenq_e->inline_data_w4);
2223                 ena_update_hints(adapter, hints);
2224                 break;
2225         default:
2226                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2227                         aenq_e->aenq_common_desc.syndrom);
2228         }
2229 }
2230
2231 static void ena_keep_alive(void *adapter_data,
2232                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2233 {
2234         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2235
2236         adapter->timestamp_wd = rte_get_timer_cycles();
2237 }
2238
2239 /**
2240  * This handler will called for unknown event group or unimplemented handlers
2241  **/
2242 static void unimplemented_aenq_handler(__rte_unused void *data,
2243                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2244 {
2245         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2246                           "unimplemented handler\n");
2247 }
2248
2249 static struct ena_aenq_handlers aenq_handlers = {
2250         .handlers = {
2251                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2252                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2253                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2254         },
2255         .unimplemented_handler = unimplemented_aenq_handler
2256 };