4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <rte_ether.h>
35 #include <rte_ethdev.h>
37 #include <rte_atomic.h>
39 #include <rte_errno.h>
40 #include <rte_version.h>
41 #include <rte_eal_memconfig.h>
43 #include "ena_ethdev.h"
45 #include "ena_platform.h"
47 #include "ena_eth_com.h"
49 #include <ena_common_defs.h>
50 #include <ena_regs_defs.h>
51 #include <ena_admin_defs.h>
52 #include <ena_eth_io_defs.h>
54 #define DRV_MODULE_VER_MAJOR 1
55 #define DRV_MODULE_VER_MINOR 0
56 #define DRV_MODULE_VER_SUBMINOR 0
58 #define ENA_IO_TXQ_IDX(q) (2 * (q))
59 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1)
60 /*reverse version of ENA_IO_RXQ_IDX*/
61 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2)
63 /* While processing submitted and completed descriptors (rx and tx path
64 * respectively) in a loop it is desired to:
65 * - perform batch submissions while populating sumbissmion queue
66 * - avoid blocking transmission of other packets during cleanup phase
67 * Hence the utilization ratio of 1/8 of a queue size.
69 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
71 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
72 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
74 #define GET_L4_HDR_LEN(mbuf) \
75 ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *, \
76 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
78 #define ENA_RX_RSS_TABLE_LOG_SIZE 7
79 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
80 #define ENA_HASH_KEY_SIZE 40
81 #define ENA_ETH_SS_STATS 0xFF
82 #define ETH_GSTRING_LEN 32
84 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
86 enum ethtool_stringset {
92 char name[ETH_GSTRING_LEN];
96 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
98 .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
101 #define ENA_STAT_ENTRY(stat, stat_type) { \
103 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
106 #define ENA_STAT_RX_ENTRY(stat) \
107 ENA_STAT_ENTRY(stat, rx)
109 #define ENA_STAT_TX_ENTRY(stat) \
110 ENA_STAT_ENTRY(stat, tx)
112 #define ENA_STAT_GLOBAL_ENTRY(stat) \
113 ENA_STAT_ENTRY(stat, dev)
115 static const struct ena_stats ena_stats_global_strings[] = {
116 ENA_STAT_GLOBAL_ENTRY(tx_timeout),
117 ENA_STAT_GLOBAL_ENTRY(io_suspend),
118 ENA_STAT_GLOBAL_ENTRY(io_resume),
119 ENA_STAT_GLOBAL_ENTRY(wd_expired),
120 ENA_STAT_GLOBAL_ENTRY(interface_up),
121 ENA_STAT_GLOBAL_ENTRY(interface_down),
122 ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
125 static const struct ena_stats ena_stats_tx_strings[] = {
126 ENA_STAT_TX_ENTRY(cnt),
127 ENA_STAT_TX_ENTRY(bytes),
128 ENA_STAT_TX_ENTRY(queue_stop),
129 ENA_STAT_TX_ENTRY(queue_wakeup),
130 ENA_STAT_TX_ENTRY(dma_mapping_err),
131 ENA_STAT_TX_ENTRY(linearize),
132 ENA_STAT_TX_ENTRY(linearize_failed),
133 ENA_STAT_TX_ENTRY(tx_poll),
134 ENA_STAT_TX_ENTRY(doorbells),
135 ENA_STAT_TX_ENTRY(prepare_ctx_err),
136 ENA_STAT_TX_ENTRY(missing_tx_comp),
137 ENA_STAT_TX_ENTRY(bad_req_id),
140 static const struct ena_stats ena_stats_rx_strings[] = {
141 ENA_STAT_RX_ENTRY(cnt),
142 ENA_STAT_RX_ENTRY(bytes),
143 ENA_STAT_RX_ENTRY(refil_partial),
144 ENA_STAT_RX_ENTRY(bad_csum),
145 ENA_STAT_RX_ENTRY(page_alloc_fail),
146 ENA_STAT_RX_ENTRY(skb_alloc_fail),
147 ENA_STAT_RX_ENTRY(dma_mapping_err),
148 ENA_STAT_RX_ENTRY(bad_desc_num),
149 ENA_STAT_RX_ENTRY(small_copy_len_pkt),
152 static const struct ena_stats ena_stats_ena_com_strings[] = {
153 ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
154 ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
155 ENA_STAT_ENA_COM_ENTRY(completed_cmd),
156 ENA_STAT_ENA_COM_ENTRY(out_of_space),
157 ENA_STAT_ENA_COM_ENTRY(no_completion),
160 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings)
161 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings)
162 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings)
163 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
165 /** Vendor ID used by Amazon devices */
166 #define PCI_VENDOR_ID_AMAZON 0x1D0F
167 /** Amazon devices */
168 #define PCI_DEVICE_ID_ENA_VF 0xEC20
169 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21
171 static struct rte_pci_id pci_id_ena_map[] = {
172 #define RTE_PCI_DEV_ID_DECL_ENA(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
173 RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF)
174 RTE_PCI_DEV_ID_DECL_ENA(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF)
178 static int ena_device_init(struct ena_com_dev *ena_dev,
179 struct ena_com_dev_get_features_ctx *get_feat_ctx);
180 static int ena_dev_configure(struct rte_eth_dev *dev);
181 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
183 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
184 uint16_t nb_desc, unsigned int socket_id,
185 const struct rte_eth_txconf *tx_conf);
186 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
187 uint16_t nb_desc, unsigned int socket_id,
188 const struct rte_eth_rxconf *rx_conf,
189 struct rte_mempool *mp);
190 static uint16_t eth_ena_recv_pkts(void *rx_queue,
191 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
192 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
193 static void ena_init_rings(struct ena_adapter *adapter);
194 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
195 static int ena_start(struct rte_eth_dev *dev);
196 static void ena_close(struct rte_eth_dev *dev);
197 static void ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
198 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
199 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
200 static void ena_rx_queue_release(void *queue);
201 static void ena_tx_queue_release(void *queue);
202 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
203 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
204 static int ena_link_update(struct rte_eth_dev *dev,
205 __rte_unused int wait_to_complete);
206 static int ena_queue_restart(struct ena_ring *ring);
207 static int ena_queue_restart_all(struct rte_eth_dev *dev,
208 enum ena_ring_type ring_type);
209 static void ena_stats_restart(struct rte_eth_dev *dev);
210 static void ena_infos_get(__rte_unused struct rte_eth_dev *dev,
211 struct rte_eth_dev_info *dev_info);
212 static int ena_rss_reta_update(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static int ena_rss_reta_query(struct rte_eth_dev *dev,
216 struct rte_eth_rss_reta_entry64 *reta_conf,
218 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
220 static struct eth_dev_ops ena_dev_ops = {
221 .dev_configure = ena_dev_configure,
222 .dev_infos_get = ena_infos_get,
223 .rx_queue_setup = ena_rx_queue_setup,
224 .tx_queue_setup = ena_tx_queue_setup,
225 .dev_start = ena_start,
226 .link_update = ena_link_update,
227 .stats_get = ena_stats_get,
228 .mtu_set = ena_mtu_set,
229 .rx_queue_release = ena_rx_queue_release,
230 .tx_queue_release = ena_tx_queue_release,
231 .dev_close = ena_close,
232 .reta_update = ena_rss_reta_update,
233 .reta_query = ena_rss_reta_query,
236 #define NUMA_NO_NODE SOCKET_ID_ANY
238 static inline int ena_cpu_to_node(int cpu)
240 struct rte_config *config = rte_eal_get_configuration();
242 if (likely(cpu < RTE_MAX_MEMZONE))
243 return config->mem_config->memzone[cpu].socket_id;
248 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
249 struct ena_com_rx_ctx *ena_rx_ctx)
251 uint64_t ol_flags = 0;
253 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
254 ol_flags |= PKT_TX_TCP_CKSUM;
255 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
256 ol_flags |= PKT_TX_UDP_CKSUM;
258 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
259 ol_flags |= PKT_TX_IPV4;
260 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
261 ol_flags |= PKT_TX_IPV6;
263 if (unlikely(ena_rx_ctx->l4_csum_err))
264 ol_flags |= PKT_RX_L4_CKSUM_BAD;
265 if (unlikely(ena_rx_ctx->l3_csum_err))
266 ol_flags |= PKT_RX_IP_CKSUM_BAD;
268 mbuf->ol_flags = ol_flags;
271 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
272 struct ena_com_tx_ctx *ena_tx_ctx)
274 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
277 (PKT_TX_L4_MASK | PKT_TX_IP_CKSUM | PKT_TX_TCP_SEG)) {
278 /* check if TSO is required */
279 if (mbuf->ol_flags & PKT_TX_TCP_SEG) {
280 ena_tx_ctx->tso_enable = true;
282 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
285 /* check if L3 checksum is needed */
286 if (mbuf->ol_flags & PKT_TX_IP_CKSUM)
287 ena_tx_ctx->l3_csum_enable = true;
289 if (mbuf->ol_flags & PKT_TX_IPV6) {
290 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
292 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
294 /* set don't fragment (DF) flag */
295 if (mbuf->packet_type &
296 (RTE_PTYPE_L4_NONFRAG
297 | RTE_PTYPE_INNER_L4_NONFRAG))
298 ena_tx_ctx->df = true;
301 /* check if L4 checksum is needed */
302 switch (mbuf->ol_flags & PKT_TX_L4_MASK) {
303 case PKT_TX_TCP_CKSUM:
304 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
305 ena_tx_ctx->l4_csum_enable = true;
307 case PKT_TX_UDP_CKSUM:
308 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
309 ena_tx_ctx->l4_csum_enable = true;
312 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
313 ena_tx_ctx->l4_csum_enable = false;
317 ena_meta->mss = mbuf->tso_segsz;
318 ena_meta->l3_hdr_len = mbuf->l3_len;
319 ena_meta->l3_hdr_offset = mbuf->l2_len;
320 /* this param needed only for TSO */
321 ena_meta->l3_outer_hdr_len = 0;
322 ena_meta->l3_outer_hdr_offset = 0;
324 ena_tx_ctx->meta_valid = true;
326 ena_tx_ctx->meta_valid = false;
330 static void ena_config_host_info(struct ena_com_dev *ena_dev)
332 struct ena_admin_host_info *host_info;
335 /* Allocate only the host info */
336 rc = ena_com_allocate_host_info(ena_dev);
338 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
342 host_info = ena_dev->host_attr.host_info;
344 host_info->os_type = ENA_ADMIN_OS_DPDK;
345 host_info->kernel_ver = RTE_VERSION;
346 strncpy((char *)host_info->kernel_ver_str, rte_version(),
347 strlen(rte_version()));
348 host_info->os_dist = RTE_VERSION;
349 strncpy((char *)host_info->os_dist_str, rte_version(),
350 strlen(rte_version()));
351 host_info->driver_version =
352 (DRV_MODULE_VER_MAJOR) |
353 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
354 (DRV_MODULE_VER_SUBMINOR <<
355 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
357 rc = ena_com_set_host_attributes(ena_dev);
360 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
362 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
370 ena_com_delete_host_info(ena_dev);
374 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
376 if (sset != ETH_SS_STATS)
379 /* Workaround for clang:
380 * touch internal structures to prevent
383 ENA_TOUCH(ena_stats_global_strings);
384 ENA_TOUCH(ena_stats_tx_strings);
385 ENA_TOUCH(ena_stats_rx_strings);
386 ENA_TOUCH(ena_stats_ena_com_strings);
388 return dev->data->nb_tx_queues *
389 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
390 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
393 static void ena_config_debug_area(struct ena_adapter *adapter)
398 ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
400 RTE_LOG(ERR, PMD, "SS count is negative\n");
404 /* allocate 32 bytes for each string and 64bit for the value */
405 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
407 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
409 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
413 rc = ena_com_set_host_attributes(&adapter->ena_dev);
416 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
418 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
424 ena_com_delete_debug_area(&adapter->ena_dev);
427 static void ena_close(struct rte_eth_dev *dev)
429 struct ena_adapter *adapter =
430 (struct ena_adapter *)(dev->data->dev_private);
432 adapter->state = ENA_ADAPTER_STATE_STOPPED;
434 ena_rx_queue_release_all(dev);
435 ena_tx_queue_release_all(dev);
438 static int ena_rss_reta_update(struct rte_eth_dev *dev,
439 struct rte_eth_rss_reta_entry64 *reta_conf,
442 struct ena_adapter *adapter =
443 (struct ena_adapter *)(dev->data->dev_private);
444 struct ena_com_dev *ena_dev = &adapter->ena_dev;
450 if ((reta_size == 0) || (reta_conf == NULL))
453 if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
454 RTE_LOG(WARNING, PMD,
455 "indirection table %d is bigger than supported (%d)\n",
456 reta_size, ENA_RX_RSS_TABLE_SIZE);
461 for (i = 0 ; i < reta_size ; i++) {
462 /* each reta_conf is for 64 entries.
463 * to support 128 we use 2 conf of 64
465 conf_idx = i / RTE_RETA_GROUP_SIZE;
466 idx = i % RTE_RETA_GROUP_SIZE;
467 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
469 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
470 ret = ena_com_indirect_table_fill_entry(ena_dev,
473 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
475 "Cannot fill indirect table\n");
482 ret = ena_com_indirect_table_set(ena_dev);
483 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
484 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
489 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n",
490 __func__, reta_size, adapter->rte_dev->data->port_id);
495 /* Query redirection table. */
496 static int ena_rss_reta_query(struct rte_eth_dev *dev,
497 struct rte_eth_rss_reta_entry64 *reta_conf,
500 struct ena_adapter *adapter =
501 (struct ena_adapter *)(dev->data->dev_private);
502 struct ena_com_dev *ena_dev = &adapter->ena_dev;
505 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
509 if (reta_size == 0 || reta_conf == NULL ||
510 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
513 ret = ena_com_indirect_table_get(ena_dev, indirect_table);
514 if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
515 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
520 for (i = 0 ; i < reta_size ; i++) {
521 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
522 reta_idx = i % RTE_RETA_GROUP_SIZE;
523 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
524 reta_conf[reta_conf_idx].reta[reta_idx] =
525 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
531 static int ena_rss_init_default(struct ena_adapter *adapter)
533 struct ena_com_dev *ena_dev = &adapter->ena_dev;
534 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
538 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
540 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
544 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
545 val = i % nb_rx_queues;
546 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
547 ENA_IO_RXQ_IDX(val));
548 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
549 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
554 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
555 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
556 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
557 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
561 rc = ena_com_set_default_hash_ctrl(ena_dev);
562 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
563 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
567 rc = ena_com_indirect_table_set(ena_dev);
568 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
569 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
572 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
573 adapter->rte_dev->data->port_id);
578 ena_com_rss_destroy(ena_dev);
584 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
586 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
587 int nb_queues = dev->data->nb_rx_queues;
590 for (i = 0; i < nb_queues; i++)
591 ena_rx_queue_release(queues[i]);
594 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
596 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
597 int nb_queues = dev->data->nb_tx_queues;
600 for (i = 0; i < nb_queues; i++)
601 ena_tx_queue_release(queues[i]);
604 static void ena_rx_queue_release(void *queue)
606 struct ena_ring *ring = (struct ena_ring *)queue;
607 struct ena_adapter *adapter = ring->adapter;
610 ena_assert_msg(ring->configured,
611 "API violation - releasing not configured queue");
612 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
615 /* Destroy HW queue */
616 ena_qid = ENA_IO_RXQ_IDX(ring->id);
617 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
620 ena_rx_queue_release_bufs(ring);
622 /* Free ring resources */
623 if (ring->rx_buffer_info)
624 rte_free(ring->rx_buffer_info);
625 ring->rx_buffer_info = NULL;
627 ring->configured = 0;
629 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
630 ring->port_id, ring->id);
633 static void ena_tx_queue_release(void *queue)
635 struct ena_ring *ring = (struct ena_ring *)queue;
636 struct ena_adapter *adapter = ring->adapter;
639 ena_assert_msg(ring->configured,
640 "API violation. Releasing not configured queue");
641 ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
644 /* Destroy HW queue */
645 ena_qid = ENA_IO_TXQ_IDX(ring->id);
646 ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
649 ena_tx_queue_release_bufs(ring);
651 /* Free ring resources */
652 if (ring->tx_buffer_info)
653 rte_free(ring->tx_buffer_info);
655 if (ring->empty_tx_reqs)
656 rte_free(ring->empty_tx_reqs);
658 ring->empty_tx_reqs = NULL;
659 ring->tx_buffer_info = NULL;
661 ring->configured = 0;
663 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
664 ring->port_id, ring->id);
667 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
669 unsigned int ring_mask = ring->ring_size - 1;
671 while (ring->next_to_clean != ring->next_to_use) {
673 ring->rx_buffer_info[ring->next_to_clean & ring_mask];
676 __rte_mbuf_raw_free(m);
678 ring->next_to_clean =
679 ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
683 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
685 unsigned int ring_mask = ring->ring_size - 1;
687 while (ring->next_to_clean != ring->next_to_use) {
688 struct ena_tx_buffer *tx_buf =
689 &ring->tx_buffer_info[ring->next_to_clean & ring_mask];
692 rte_pktmbuf_free(tx_buf->mbuf);
694 ring->next_to_clean =
695 ENA_CIRC_INC(ring->next_to_clean, 1, ring->ring_size);
699 static int ena_link_update(struct rte_eth_dev *dev,
700 __rte_unused int wait_to_complete)
702 struct rte_eth_link *link = &dev->data->dev_link;
704 link->link_status = 1;
705 link->link_speed = ETH_SPEED_NUM_10G;
706 link->link_duplex = ETH_LINK_FULL_DUPLEX;
711 static int ena_queue_restart_all(struct rte_eth_dev *dev,
712 enum ena_ring_type ring_type)
714 struct ena_adapter *adapter =
715 (struct ena_adapter *)(dev->data->dev_private);
716 struct ena_ring *queues = NULL;
720 queues = (ring_type == ENA_RING_TYPE_RX) ?
721 adapter->rx_ring : adapter->tx_ring;
723 for (i = 0; i < adapter->num_queues; i++) {
724 if (queues[i].configured) {
725 if (ring_type == ENA_RING_TYPE_RX) {
727 dev->data->rx_queues[i] == &queues[i],
728 "Inconsistent state of rx queues\n");
731 dev->data->tx_queues[i] == &queues[i],
732 "Inconsistent state of tx queues\n");
735 rc = ena_queue_restart(&queues[i]);
739 "failed to restart queue %d type(%d)\n",
749 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
751 uint32_t max_frame_len = adapter->max_mtu;
753 if (adapter->rte_eth_dev_data->dev_conf.rxmode.jumbo_frame == 1)
755 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
757 return max_frame_len;
760 static int ena_check_valid_conf(struct ena_adapter *adapter)
762 uint32_t max_frame_len = ena_get_mtu_conf(adapter);
764 if (max_frame_len > adapter->max_mtu) {
765 PMD_INIT_LOG(ERR, "Unsupported MTU of %d\n", max_frame_len);
773 ena_calc_queue_size(struct ena_com_dev *ena_dev,
774 struct ena_com_dev_get_features_ctx *get_feat_ctx)
776 uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
778 queue_size = RTE_MIN(queue_size,
779 get_feat_ctx->max_queues.max_cq_depth);
780 queue_size = RTE_MIN(queue_size,
781 get_feat_ctx->max_queues.max_sq_depth);
783 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
784 queue_size = RTE_MIN(queue_size,
785 get_feat_ctx->max_queues.max_llq_depth);
787 /* Round down to power of 2 */
788 if (!rte_is_power_of_2(queue_size))
789 queue_size = rte_align32pow2(queue_size >> 1);
791 if (queue_size == 0) {
792 PMD_INIT_LOG(ERR, "Invalid queue size\n");
799 static void ena_stats_restart(struct rte_eth_dev *dev)
801 struct ena_adapter *adapter =
802 (struct ena_adapter *)(dev->data->dev_private);
804 rte_atomic64_init(&adapter->drv_stats->ierrors);
805 rte_atomic64_init(&adapter->drv_stats->oerrors);
806 rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
809 static void ena_stats_get(struct rte_eth_dev *dev,
810 struct rte_eth_stats *stats)
812 struct ena_admin_basic_stats ena_stats;
813 struct ena_adapter *adapter =
814 (struct ena_adapter *)(dev->data->dev_private);
815 struct ena_com_dev *ena_dev = &adapter->ena_dev;
818 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
821 memset(&ena_stats, 0, sizeof(ena_stats));
822 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
824 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
828 /* Set of basic statistics from ENA */
829 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
830 ena_stats.rx_pkts_low);
831 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
832 ena_stats.tx_pkts_low);
833 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
834 ena_stats.rx_bytes_low);
835 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
836 ena_stats.tx_bytes_low);
837 stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
838 ena_stats.rx_drops_low);
840 /* Driver related stats */
841 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
842 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
843 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
846 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
848 struct ena_adapter *adapter;
849 struct ena_com_dev *ena_dev;
852 ena_assert_msg(dev->data != NULL, "Uninitialized device");
853 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
854 adapter = (struct ena_adapter *)(dev->data->dev_private);
856 ena_dev = &adapter->ena_dev;
857 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
859 if (mtu > ena_get_mtu_conf(adapter)) {
861 "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
862 mtu, ena_get_mtu_conf(adapter));
867 rc = ena_com_set_dev_mtu(ena_dev, mtu);
869 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
871 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
877 static int ena_start(struct rte_eth_dev *dev)
879 struct ena_adapter *adapter =
880 (struct ena_adapter *)(dev->data->dev_private);
883 if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
884 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
885 PMD_INIT_LOG(ERR, "API violation");
889 rc = ena_check_valid_conf(adapter);
893 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
897 rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
901 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
902 ETH_MQ_RX_RSS_FLAG) {
903 rc = ena_rss_init_default(adapter);
908 ena_stats_restart(dev);
910 adapter->state = ENA_ADAPTER_STATE_RUNNING;
915 static int ena_queue_restart(struct ena_ring *ring)
919 ena_assert_msg(ring->configured == 1,
920 "Trying to restart unconfigured queue\n");
922 ring->next_to_clean = 0;
923 ring->next_to_use = 0;
925 if (ring->type == ENA_RING_TYPE_TX)
928 rc = ena_populate_rx_queue(ring, ring->ring_size - 1);
929 if ((unsigned int)rc != ring->ring_size - 1) {
930 PMD_INIT_LOG(ERR, "Failed to populate rx ring !\n");
937 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
940 __rte_unused unsigned int socket_id,
941 __rte_unused const struct rte_eth_txconf *tx_conf)
943 struct ena_com_create_io_ctx ctx =
944 /* policy set to _HOST just to satisfy icc compiler */
945 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
946 ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
947 struct ena_ring *txq = NULL;
948 struct ena_adapter *adapter =
949 (struct ena_adapter *)(dev->data->dev_private);
953 struct ena_com_dev *ena_dev = &adapter->ena_dev;
955 txq = &adapter->tx_ring[queue_idx];
957 if (txq->configured) {
959 "API violation. Queue %d is already configured\n",
964 if (nb_desc > adapter->tx_ring_size) {
966 "Unsupported size of TX queue (max size: %d)\n",
967 adapter->tx_ring_size);
971 ena_qid = ENA_IO_TXQ_IDX(queue_idx);
973 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
975 ctx.msix_vector = -1; /* admin interrupts not used */
976 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
977 ctx.queue_size = adapter->tx_ring_size;
978 ctx.numa_node = ena_cpu_to_node(queue_idx);
980 rc = ena_com_create_io_queue(ena_dev, &ctx);
983 "failed to create io TX queue #%d (qid:%d) rc: %d\n",
984 queue_idx, ena_qid, rc);
986 txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
987 txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
989 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
991 &txq->ena_com_io_cq);
994 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
996 ena_com_destroy_io_queue(ena_dev, ena_qid);
1000 txq->port_id = dev->data->port_id;
1001 txq->next_to_clean = 0;
1002 txq->next_to_use = 0;
1003 txq->ring_size = nb_desc;
1005 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1006 sizeof(struct ena_tx_buffer) *
1008 RTE_CACHE_LINE_SIZE);
1009 if (!txq->tx_buffer_info) {
1010 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1014 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1015 sizeof(u16) * txq->ring_size,
1016 RTE_CACHE_LINE_SIZE);
1017 if (!txq->empty_tx_reqs) {
1018 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1019 rte_free(txq->tx_buffer_info);
1022 for (i = 0; i < txq->ring_size; i++)
1023 txq->empty_tx_reqs[i] = i;
1025 /* Store pointer to this queue in upper layer */
1026 txq->configured = 1;
1027 dev->data->tx_queues[queue_idx] = txq;
1032 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1035 __rte_unused unsigned int socket_id,
1036 __rte_unused const struct rte_eth_rxconf *rx_conf,
1037 struct rte_mempool *mp)
1039 struct ena_com_create_io_ctx ctx =
1040 /* policy set to _HOST just to satisfy icc compiler */
1041 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1042 ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1043 struct ena_adapter *adapter =
1044 (struct ena_adapter *)(dev->data->dev_private);
1045 struct ena_ring *rxq = NULL;
1046 uint16_t ena_qid = 0;
1048 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1050 rxq = &adapter->rx_ring[queue_idx];
1051 if (rxq->configured) {
1053 "API violation. Queue %d is already configured\n",
1058 if (nb_desc > adapter->rx_ring_size) {
1060 "Unsupported size of RX queue (max size: %d)\n",
1061 adapter->rx_ring_size);
1065 ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1068 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1069 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1070 ctx.msix_vector = -1; /* admin interrupts not used */
1071 ctx.queue_size = adapter->rx_ring_size;
1072 ctx.numa_node = ena_cpu_to_node(queue_idx);
1074 rc = ena_com_create_io_queue(ena_dev, &ctx);
1076 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1079 rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1080 rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1082 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1083 &rxq->ena_com_io_sq,
1084 &rxq->ena_com_io_cq);
1087 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1089 ena_com_destroy_io_queue(ena_dev, ena_qid);
1092 rxq->port_id = dev->data->port_id;
1093 rxq->next_to_clean = 0;
1094 rxq->next_to_use = 0;
1095 rxq->ring_size = nb_desc;
1098 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1099 sizeof(struct rte_mbuf *) * nb_desc,
1100 RTE_CACHE_LINE_SIZE);
1101 if (!rxq->rx_buffer_info) {
1102 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1106 /* Store pointer to this queue in upper layer */
1107 rxq->configured = 1;
1108 dev->data->rx_queues[queue_idx] = rxq;
1113 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1117 unsigned int ring_size = rxq->ring_size;
1118 unsigned int ring_mask = ring_size - 1;
1119 int next_to_use = rxq->next_to_use & ring_mask;
1120 struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1122 if (unlikely(!count))
1125 ena_assert_msg((((ENA_CIRC_COUNT(rxq->next_to_use, rxq->next_to_clean,
1127 count) < rxq->ring_size), "bad ring state");
1129 count = RTE_MIN(count, ring_size - next_to_use);
1131 /* get resources for incoming packets */
1132 rc = rte_mempool_get_bulk(rxq->mb_pool,
1133 (void **)(&mbufs[next_to_use]), count);
1134 if (unlikely(rc < 0)) {
1135 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1136 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1140 for (i = 0; i < count; i++) {
1141 struct rte_mbuf *mbuf = mbufs[next_to_use];
1142 struct ena_com_buf ebuf;
1144 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1145 /* prepare physical address for DMA transaction */
1146 ebuf.paddr = mbuf->buf_physaddr + RTE_PKTMBUF_HEADROOM;
1147 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1148 /* pass resource to device */
1149 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1150 &ebuf, next_to_use);
1152 RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1155 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, ring_size);
1159 rxq->next_to_use = next_to_use;
1160 /* let HW know that it can fill buffers with data */
1161 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1166 static int ena_device_init(struct ena_com_dev *ena_dev,
1167 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1170 bool readless_supported;
1172 /* Initialize mmio registers */
1173 rc = ena_com_mmio_reg_read_request_init(ena_dev);
1175 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1179 /* The PCIe configuration space revision id indicate if mmio reg
1182 readless_supported =
1183 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1184 & ENA_MMIO_DISABLE_REG_READ);
1185 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1188 rc = ena_com_dev_reset(ena_dev);
1190 RTE_LOG(ERR, PMD, "cannot reset device\n");
1191 goto err_mmio_read_less;
1194 /* check FW version */
1195 rc = ena_com_validate_version(ena_dev);
1197 RTE_LOG(ERR, PMD, "device version is too low\n");
1198 goto err_mmio_read_less;
1201 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1203 /* ENA device administration layer init */
1204 rc = ena_com_admin_init(ena_dev, NULL, true);
1207 "cannot initialize ena admin queue with device\n");
1208 goto err_mmio_read_less;
1211 ena_config_host_info(ena_dev);
1213 /* To enable the msix interrupts the driver needs to know the number
1214 * of queues. So the driver uses polling mode to retrieve this
1217 ena_com_set_admin_polling_mode(ena_dev, true);
1219 /* Get Device Attributes and features */
1220 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1223 "cannot get attribute for ena device rc= %d\n", rc);
1224 goto err_admin_init;
1230 ena_com_admin_destroy(ena_dev);
1233 ena_com_mmio_reg_read_request_destroy(ena_dev);
1238 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1240 struct rte_pci_device *pci_dev;
1241 struct ena_adapter *adapter =
1242 (struct ena_adapter *)(eth_dev->data->dev_private);
1243 struct ena_com_dev *ena_dev = &adapter->ena_dev;
1244 struct ena_com_dev_get_features_ctx get_feat_ctx;
1247 static int adapters_found;
1249 memset(adapter, 0, sizeof(struct ena_adapter));
1250 ena_dev = &adapter->ena_dev;
1252 eth_dev->dev_ops = &ena_dev_ops;
1253 eth_dev->rx_pkt_burst = ð_ena_recv_pkts;
1254 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts;
1255 adapter->rte_eth_dev_data = eth_dev->data;
1256 adapter->rte_dev = eth_dev;
1258 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1261 pci_dev = eth_dev->pci_dev;
1262 adapter->pdev = pci_dev;
1264 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d\n",
1265 pci_dev->addr.domain,
1267 pci_dev->addr.devid,
1268 pci_dev->addr.function);
1270 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1271 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1273 /* Present ENA_MEM_BAR indicates available LLQ mode.
1274 * Use corresponding policy
1276 if (adapter->dev_mem_base)
1277 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1278 else if (adapter->regs)
1279 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1281 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)\n",
1284 ena_dev->reg_bar = adapter->regs;
1285 ena_dev->dmadev = adapter->pdev;
1287 adapter->id_number = adapters_found;
1289 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1290 adapter->id_number);
1292 /* device specific initialization routine */
1293 rc = ena_device_init(ena_dev, &get_feat_ctx);
1295 PMD_INIT_LOG(CRIT, "Failed to init ENA device\n");
1299 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1300 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1302 "Trying to use LLQ but llq_num is 0.\n"
1303 "Fall back into regular queues.\n");
1304 ena_dev->tx_mem_queue_type =
1305 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1306 adapter->num_queues =
1307 get_feat_ctx.max_queues.max_sq_num;
1309 adapter->num_queues =
1310 get_feat_ctx.max_queues.max_llq_num;
1313 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1316 queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1317 if ((queue_size <= 0) || (adapter->num_queues <= 0))
1320 adapter->tx_ring_size = queue_size;
1321 adapter->rx_ring_size = queue_size;
1323 /* prepare ring structures */
1324 ena_init_rings(adapter);
1326 ena_config_debug_area(adapter);
1328 /* Set max MTU for this device */
1329 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1331 /* Copy MAC address and point DPDK to it */
1332 eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1333 ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1334 (struct ether_addr *)adapter->mac_addr);
1336 adapter->drv_stats = rte_zmalloc("adapter stats",
1337 sizeof(*adapter->drv_stats),
1338 RTE_CACHE_LINE_SIZE);
1339 if (!adapter->drv_stats) {
1340 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1345 adapter->state = ENA_ADAPTER_STATE_INIT;
1350 static int ena_dev_configure(struct rte_eth_dev *dev)
1352 struct ena_adapter *adapter =
1353 (struct ena_adapter *)(dev->data->dev_private);
1355 if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1356 adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1357 PMD_INIT_LOG(ERR, "Illegal adapter state: %d\n",
1362 switch (adapter->state) {
1363 case ENA_ADAPTER_STATE_INIT:
1364 case ENA_ADAPTER_STATE_STOPPED:
1365 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1367 case ENA_ADAPTER_STATE_CONFIG:
1368 RTE_LOG(WARNING, PMD,
1369 "Ivalid driver state while trying to configure device\n");
1378 static void ena_init_rings(struct ena_adapter *adapter)
1382 for (i = 0; i < adapter->num_queues; i++) {
1383 struct ena_ring *ring = &adapter->tx_ring[i];
1385 ring->configured = 0;
1386 ring->type = ENA_RING_TYPE_TX;
1387 ring->adapter = adapter;
1389 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1390 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1393 for (i = 0; i < adapter->num_queues; i++) {
1394 struct ena_ring *ring = &adapter->rx_ring[i];
1396 ring->configured = 0;
1397 ring->type = ENA_RING_TYPE_RX;
1398 ring->adapter = adapter;
1403 static void ena_infos_get(struct rte_eth_dev *dev,
1404 struct rte_eth_dev_info *dev_info)
1406 struct ena_adapter *adapter;
1407 struct ena_com_dev *ena_dev;
1408 struct ena_com_dev_get_features_ctx feat;
1409 uint32_t rx_feat = 0, tx_feat = 0;
1412 ena_assert_msg(dev->data != NULL, "Uninitialized device");
1413 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1414 adapter = (struct ena_adapter *)(dev->data->dev_private);
1416 ena_dev = &adapter->ena_dev;
1417 ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1419 dev_info->speed_capa =
1421 ETH_LINK_SPEED_2_5G |
1423 ETH_LINK_SPEED_10G |
1424 ETH_LINK_SPEED_25G |
1425 ETH_LINK_SPEED_40G |
1426 ETH_LINK_SPEED_50G |
1427 ETH_LINK_SPEED_100G;
1429 /* Get supported features from HW */
1430 rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1433 "Cannot get attribute for ena device rc= %d\n", rc);
1437 /* Set Tx & Rx features available for device */
1438 if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1439 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1441 if (feat.offload.tx &
1442 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1443 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1444 DEV_TX_OFFLOAD_UDP_CKSUM |
1445 DEV_TX_OFFLOAD_TCP_CKSUM;
1447 if (feat.offload.tx &
1448 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1449 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1450 DEV_RX_OFFLOAD_UDP_CKSUM |
1451 DEV_RX_OFFLOAD_TCP_CKSUM;
1453 /* Inform framework about available features */
1454 dev_info->rx_offload_capa = rx_feat;
1455 dev_info->tx_offload_capa = tx_feat;
1457 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1458 dev_info->max_rx_pktlen = adapter->max_mtu;
1459 dev_info->max_mac_addrs = 1;
1461 dev_info->max_rx_queues = adapter->num_queues;
1462 dev_info->max_tx_queues = adapter->num_queues;
1463 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1466 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1469 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1470 unsigned int ring_size = rx_ring->ring_size;
1471 unsigned int ring_mask = ring_size - 1;
1472 uint16_t next_to_clean = rx_ring->next_to_clean;
1473 int desc_in_use = 0;
1474 unsigned int recv_idx = 0;
1475 struct rte_mbuf *mbuf = NULL;
1476 struct rte_mbuf *mbuf_head = NULL;
1477 struct rte_mbuf *mbuf_prev = NULL;
1478 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1479 unsigned int completed;
1481 struct ena_com_rx_ctx ena_rx_ctx;
1484 /* Check adapter state */
1485 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1487 "Trying to receive pkts while device is NOT running\n");
1491 desc_in_use = ENA_CIRC_COUNT(rx_ring->next_to_use,
1492 next_to_clean, ring_size);
1493 if (unlikely(nb_pkts > desc_in_use))
1494 nb_pkts = desc_in_use;
1496 for (completed = 0; completed < nb_pkts; completed++) {
1499 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1500 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1501 ena_rx_ctx.descs = 0;
1502 /* receive packet context */
1503 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1504 rx_ring->ena_com_io_sq,
1507 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1511 if (unlikely(ena_rx_ctx.descs == 0))
1514 while (segments < ena_rx_ctx.descs) {
1515 mbuf = rx_buff_info[next_to_clean & ring_mask];
1516 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1517 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1520 if (segments == 0) {
1521 mbuf->nb_segs = ena_rx_ctx.descs;
1522 mbuf->port = rx_ring->port_id;
1526 /* for multi-segment pkts create mbuf chain */
1527 mbuf_prev->next = mbuf;
1529 mbuf_head->pkt_len += mbuf->data_len;
1534 ENA_RX_RING_IDX_NEXT(next_to_clean, ring_size);
1537 /* fill mbuf attributes if any */
1538 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1539 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1541 /* pass to DPDK application head mbuf */
1542 rx_pkts[recv_idx] = mbuf_head;
1546 /* Burst refill to save doorbells, memory barriers, const interval */
1547 if (ring_size - desc_in_use - 1 > ENA_RING_DESCS_RATIO(ring_size))
1548 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use - 1);
1550 rx_ring->next_to_clean = next_to_clean & ring_mask;
1555 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1558 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1559 unsigned int next_to_use = tx_ring->next_to_use;
1560 struct rte_mbuf *mbuf;
1561 unsigned int ring_size = tx_ring->ring_size;
1562 unsigned int ring_mask = ring_size - 1;
1563 struct ena_com_tx_ctx ena_tx_ctx;
1564 struct ena_tx_buffer *tx_info;
1565 struct ena_com_buf *ebuf;
1566 uint16_t rc, req_id, total_tx_descs = 0;
1570 /* Check adapter state */
1571 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1573 "Trying to xmit pkts while device is NOT running\n");
1577 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1578 mbuf = tx_pkts[sent_idx];
1580 req_id = tx_ring->empty_tx_reqs[next_to_use];
1581 tx_info = &tx_ring->tx_buffer_info[req_id];
1582 tx_info->mbuf = mbuf;
1583 tx_info->num_of_bufs = 0;
1584 ebuf = tx_info->bufs;
1586 /* Prepare TX context */
1587 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1588 memset(&ena_tx_ctx.ena_meta, 0x0,
1589 sizeof(struct ena_com_tx_meta));
1590 ena_tx_ctx.ena_bufs = ebuf;
1591 ena_tx_ctx.req_id = req_id;
1592 if (tx_ring->tx_mem_queue_type ==
1593 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1594 /* prepare the push buffer with
1595 * virtual address of the data
1597 ena_tx_ctx.header_len =
1598 RTE_MIN(mbuf->data_len,
1599 tx_ring->tx_max_header_size);
1600 ena_tx_ctx.push_header =
1601 (void *)((char *)mbuf->buf_addr +
1603 } /* there's no else as we take advantage of memset zeroing */
1605 /* Set TX offloads flags, if applicable */
1606 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx);
1608 if (unlikely(mbuf->ol_flags &
1609 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1610 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1612 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1614 /* Process first segment taking into
1615 * consideration pushed header
1617 if (mbuf->data_len > ena_tx_ctx.header_len) {
1618 ebuf->paddr = mbuf->buf_physaddr +
1620 ena_tx_ctx.header_len;
1621 ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1623 tx_info->num_of_bufs++;
1626 while ((mbuf = mbuf->next) != NULL) {
1627 ebuf->paddr = mbuf->buf_physaddr + mbuf->data_off;
1628 ebuf->len = mbuf->data_len;
1630 tx_info->num_of_bufs++;
1633 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1635 /* Write data to device */
1636 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1637 &ena_tx_ctx, &nb_hw_desc);
1641 tx_info->tx_descs = nb_hw_desc;
1643 next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, ring_size);
1646 /* Let HW do it's best :-) */
1648 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1650 /* Clear complete packets */
1651 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1652 /* Get Tx info & store how many descs were processed */
1653 tx_info = &tx_ring->tx_buffer_info[req_id];
1654 total_tx_descs += tx_info->tx_descs;
1656 /* Free whole mbuf chain */
1657 mbuf = tx_info->mbuf;
1658 rte_pktmbuf_free(mbuf);
1660 /* Put back descriptor to the ring for reuse */
1661 tx_ring->empty_tx_reqs[tx_ring->next_to_clean] = req_id;
1662 tx_ring->next_to_clean =
1663 ENA_TX_RING_IDX_NEXT(tx_ring->next_to_clean,
1664 tx_ring->ring_size);
1666 /* If too many descs to clean, leave it for another run */
1667 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1671 /* acknowledge completion of sent packets */
1672 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1673 tx_ring->next_to_use = next_to_use;
1677 static struct eth_driver rte_ena_pmd = {
1679 .name = "rte_ena_pmd",
1680 .id_table = pci_id_ena_map,
1681 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1683 .eth_dev_init = eth_ena_dev_init,
1684 .dev_private_size = sizeof(struct ena_adapter),
1688 rte_ena_pmd_init(const char *name __rte_unused,
1689 const char *params __rte_unused)
1691 rte_eth_driver_register(&rte_ena_pmd);
1695 struct rte_driver ena_pmd_drv = {
1697 .init = rte_ena_pmd_init,
1700 PMD_REGISTER_DRIVER(ena_pmd_drv, ena);
1701 DRIVER_REGISTER_PCI_TABLE(ena, pci_id_ena_map);