drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 #define ENA_MAX_RING_SIZE_RX 8192
 120 #define ENA_MAX_RING_SIZE_TX 1024
 121
 122 /*
 123  * Each rte_memzone should have unique name.
 124  * To satisfy it, count number of allocation and add it to name.
 125  */
 126 uint32_t ena_alloc_cnt;
 127
 128 static const struct ena_stats ena_stats_global_strings[] = {
 129         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 130         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 131         ENA_STAT_GLOBAL_ENTRY(io_resume),
 132         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 133         ENA_STAT_GLOBAL_ENTRY(interface_up),
 134         ENA_STAT_GLOBAL_ENTRY(interface_down),
 135         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 136 };
 137
 138 static const struct ena_stats ena_stats_tx_strings[] = {
 139         ENA_STAT_TX_ENTRY(cnt),
 140         ENA_STAT_TX_ENTRY(bytes),
 141         ENA_STAT_TX_ENTRY(queue_stop),
 142         ENA_STAT_TX_ENTRY(queue_wakeup),
 143         ENA_STAT_TX_ENTRY(dma_mapping_err),
 144         ENA_STAT_TX_ENTRY(linearize),
 145         ENA_STAT_TX_ENTRY(linearize_failed),
 146         ENA_STAT_TX_ENTRY(tx_poll),
 147         ENA_STAT_TX_ENTRY(doorbells),
 148         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 149         ENA_STAT_TX_ENTRY(missing_tx_comp),
 150         ENA_STAT_TX_ENTRY(bad_req_id),
 151 };
 152
 153 static const struct ena_stats ena_stats_rx_strings[] = {
 154         ENA_STAT_RX_ENTRY(cnt),
 155         ENA_STAT_RX_ENTRY(bytes),
 156         ENA_STAT_RX_ENTRY(refil_partial),
 157         ENA_STAT_RX_ENTRY(bad_csum),
 158         ENA_STAT_RX_ENTRY(page_alloc_fail),
 159         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 160         ENA_STAT_RX_ENTRY(dma_mapping_err),
 161         ENA_STAT_RX_ENTRY(bad_desc_num),
 162         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 163         ENA_STAT_TX_ENTRY(bad_req_id),
 164 };
 165
 166 static const struct ena_stats ena_stats_ena_com_strings[] = {
 167         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 168         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 169         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 170         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 171         ENA_STAT_ENA_COM_ENTRY(no_completion),
 172 };
 173
 174 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 175 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 176 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 177 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 178
 179 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 180                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 181                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 182                         DEV_TX_OFFLOAD_TCP_TSO)
 183 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 184                        PKT_TX_IP_CKSUM |\
 185                        PKT_TX_TCP_SEG)
 186
 187 /** Vendor ID used by Amazon devices */
 188 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 189 /** Amazon devices */
 190 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 191 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 192
 193 #define ENA_TX_OFFLOAD_MASK     (\
 194         PKT_TX_L4_MASK |         \
 195         PKT_TX_IPV6 |            \
 196         PKT_TX_IPV4 |            \
 197         PKT_TX_IP_CKSUM |        \
 198         PKT_TX_TCP_SEG)
 199
 200 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 201         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 202
 203 int ena_logtype_init;
 204 int ena_logtype_driver;
 205
 206 static const struct rte_pci_id pci_id_ena_map[] = {
 207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 208         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 209         { .device_id = 0 },
 210 };
 211
 212 static struct ena_aenq_handlers aenq_handlers;
 213
 214 static int ena_device_init(struct ena_com_dev *ena_dev,
 215                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 216                            bool *wd_state);
 217 static int ena_dev_configure(struct rte_eth_dev *dev);
 218 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 219                                   uint16_t nb_pkts);
 220 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 221                 uint16_t nb_pkts);
 222 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 223                               uint16_t nb_desc, unsigned int socket_id,
 224                               const struct rte_eth_txconf *tx_conf);
 225 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 226                               uint16_t nb_desc, unsigned int socket_id,
 227                               const struct rte_eth_rxconf *rx_conf,
 228                               struct rte_mempool *mp);
 229 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 230                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 231 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 232 static void ena_init_rings(struct ena_adapter *adapter);
 233 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 234 static int ena_start(struct rte_eth_dev *dev);
 235 static void ena_stop(struct rte_eth_dev *dev);
 236 static void ena_close(struct rte_eth_dev *dev);
 237 static int ena_dev_reset(struct rte_eth_dev *dev);
 238 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 239 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 240 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 241 static void ena_rx_queue_release(void *queue);
 242 static void ena_tx_queue_release(void *queue);
 243 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 244 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 245 static int ena_link_update(struct rte_eth_dev *dev,
 246                            int wait_to_complete);
 247 static int ena_create_io_queue(struct ena_ring *ring);
 248 static void ena_queue_stop(struct ena_ring *ring);
 249 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 250                               enum ena_ring_type ring_type);
 251 static int ena_queue_start(struct ena_ring *ring);
 252 static int ena_queue_start_all(struct rte_eth_dev *dev,
 253                                enum ena_ring_type ring_type);
 254 static void ena_stats_restart(struct rte_eth_dev *dev);
 255 static void ena_infos_get(struct rte_eth_dev *dev,
 256                           struct rte_eth_dev_info *dev_info);
 257 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 258                                struct rte_eth_rss_reta_entry64 *reta_conf,
 259                                uint16_t reta_size);
 260 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 261                               struct rte_eth_rss_reta_entry64 *reta_conf,
 262                               uint16_t reta_size);
 263 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 264 static void ena_interrupt_handler_rte(void *cb_arg);
 265 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 266 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 267 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 268
 269 static const struct eth_dev_ops ena_dev_ops = {
 270         .dev_configure        = ena_dev_configure,
 271         .dev_infos_get        = ena_infos_get,
 272         .rx_queue_setup       = ena_rx_queue_setup,
 273         .tx_queue_setup       = ena_tx_queue_setup,
 274         .dev_start            = ena_start,
 275         .dev_stop             = ena_stop,
 276         .link_update          = ena_link_update,
 277         .stats_get            = ena_stats_get,
 278         .mtu_set              = ena_mtu_set,
 279         .rx_queue_release     = ena_rx_queue_release,
 280         .tx_queue_release     = ena_tx_queue_release,
 281         .dev_close            = ena_close,
 282         .dev_reset            = ena_dev_reset,
 283         .reta_update          = ena_rss_reta_update,
 284         .reta_query           = ena_rss_reta_query,
 285 };
 286
 287 #define NUMA_NO_NODE    SOCKET_ID_ANY
 288
 289 static inline int ena_cpu_to_node(int cpu)
 290 {
 291         struct rte_config *config = rte_eal_get_configuration();
 292         struct rte_fbarray *arr = &config->mem_config->memzones;
 293         const struct rte_memzone *mz;
 294
 295         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 296                 return NUMA_NO_NODE;
 297
 298         mz = rte_fbarray_get(arr, cpu);
 299
 300         return mz->socket_id;
 301 }
 302
 303 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 304                                        struct ena_com_rx_ctx *ena_rx_ctx)
 305 {
 306         uint64_t ol_flags = 0;
 307         uint32_t packet_type = 0;
 308
 309         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 310                 packet_type |= RTE_PTYPE_L4_TCP;
 311         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 312                 packet_type |= RTE_PTYPE_L4_UDP;
 313
 314         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 315                 packet_type |= RTE_PTYPE_L3_IPV4;
 316         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 317                 packet_type |= RTE_PTYPE_L3_IPV6;
 318
 319         if (unlikely(ena_rx_ctx->l4_csum_err))
 320                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 321         if (unlikely(ena_rx_ctx->l3_csum_err))
 322                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 323
 324         mbuf->ol_flags = ol_flags;
 325         mbuf->packet_type = packet_type;
 326 }
 327
 328 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 329                                        struct ena_com_tx_ctx *ena_tx_ctx,
 330                                        uint64_t queue_offloads)
 331 {
 332         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 333
 334         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 335             (queue_offloads & QUEUE_OFFLOADS)) {
 336                 /* check if TSO is required */
 337                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 339                         ena_tx_ctx->tso_enable = true;
 340
 341                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 342                 }
 343
 344                 /* check if L3 checksum is needed */
 345                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 346                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 347                         ena_tx_ctx->l3_csum_enable = true;
 348
 349                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 350                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 351                 } else {
 352                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 353
 354                         /* set don't fragment (DF) flag */
 355                         if (mbuf->packet_type &
 356                                 (RTE_PTYPE_L4_NONFRAG
 357                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 358                                 ena_tx_ctx->df = true;
 359                 }
 360
 361                 /* check if L4 checksum is needed */
 362                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 363                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 365                         ena_tx_ctx->l4_csum_enable = true;
 366                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 367                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 368                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 369                         ena_tx_ctx->l4_csum_enable = true;
 370                 } else {
 371                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 372                         ena_tx_ctx->l4_csum_enable = false;
 373                 }
 374
 375                 ena_meta->mss = mbuf->tso_segsz;
 376                 ena_meta->l3_hdr_len = mbuf->l3_len;
 377                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 378
 379                 ena_tx_ctx->meta_valid = true;
 380         } else {
 381                 ena_tx_ctx->meta_valid = false;
 382         }
 383 }
 384
 385 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 386 {
 387         if (likely(req_id < rx_ring->ring_size))
 388                 return 0;
 389
 390         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 391
 392         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 393         rx_ring->adapter->trigger_reset = true;
 394         ++rx_ring->rx_stats.bad_req_id;
 395
 396         return -EFAULT;
 397 }
 398
 399 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 400 {
 401         struct ena_tx_buffer *tx_info = NULL;
 402
 403         if (likely(req_id < tx_ring->ring_size)) {
 404                 tx_info = &tx_ring->tx_buffer_info[req_id];
 405                 if (likely(tx_info->mbuf))
 406                         return 0;
 407         }
 408
 409         if (tx_info)
 410                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 411         else
 412                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 413
 414         /* Trigger device reset */
 415         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 416         tx_ring->adapter->trigger_reset = true;
 417         return -EFAULT;
 418 }
 419
 420 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 421 {
 422         struct ena_admin_host_info *host_info;
 423         int rc;
 424
 425         /* Allocate only the host info */
 426         rc = ena_com_allocate_host_info(ena_dev);
 427         if (rc) {
 428                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 429                 return;
 430         }
 431
 432         host_info = ena_dev->host_attr.host_info;
 433
 434         host_info->os_type = ENA_ADMIN_OS_DPDK;
 435         host_info->kernel_ver = RTE_VERSION;
 436         snprintf((char *)host_info->kernel_ver_str,
 437                  sizeof(host_info->kernel_ver_str),
 438                  "%s", rte_version());
 439         host_info->os_dist = RTE_VERSION;
 440         snprintf((char *)host_info->os_dist_str,
 441                  sizeof(host_info->os_dist_str),
 442                  "%s", rte_version());
 443         host_info->driver_version =
 444                 (DRV_MODULE_VER_MAJOR) |
 445                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 446                 (DRV_MODULE_VER_SUBMINOR <<
 447                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 448         host_info->num_cpus = rte_lcore_count();
 449
 450         rc = ena_com_set_host_attributes(ena_dev);
 451         if (rc) {
 452                 if (rc == -ENA_COM_UNSUPPORTED)
 453                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 454                 else
 455                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 456
 457                 goto err;
 458         }
 459
 460         return;
 461
 462 err:
 463         ena_com_delete_host_info(ena_dev);
 464 }
 465
 466 static int
 467 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 468 {
 469         if (sset != ETH_SS_STATS)
 470                 return -EOPNOTSUPP;
 471
 472          /* Workaround for clang:
 473          * touch internal structures to prevent
 474          * compiler error
 475          */
 476         ENA_TOUCH(ena_stats_global_strings);
 477         ENA_TOUCH(ena_stats_tx_strings);
 478         ENA_TOUCH(ena_stats_rx_strings);
 479         ENA_TOUCH(ena_stats_ena_com_strings);
 480
 481         return  dev->data->nb_tx_queues *
 482                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 483                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 484 }
 485
 486 static void ena_config_debug_area(struct ena_adapter *adapter)
 487 {
 488         u32 debug_area_size;
 489         int rc, ss_count;
 490
 491         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 492         if (ss_count <= 0) {
 493                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 494                 return;
 495         }
 496
 497         /* allocate 32 bytes for each string and 64bit for the value */
 498         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 499
 500         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 501         if (rc) {
 502                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 503                 return;
 504         }
 505
 506         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 507         if (rc) {
 508                 if (rc == -ENA_COM_UNSUPPORTED)
 509                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 510                 else
 511                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 512
 513                 goto err;
 514         }
 515
 516         return;
 517 err:
 518         ena_com_delete_debug_area(&adapter->ena_dev);
 519 }
 520
 521 static void ena_close(struct rte_eth_dev *dev)
 522 {
 523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 524         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 525         struct ena_adapter *adapter =
 526                 (struct ena_adapter *)(dev->data->dev_private);
 527
 528         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 529                 ena_stop(dev);
 530         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 531
 532         ena_rx_queue_release_all(dev);
 533         ena_tx_queue_release_all(dev);
 534
 535         rte_free(adapter->drv_stats);
 536         adapter->drv_stats = NULL;
 537
 538         rte_intr_disable(intr_handle);
 539         rte_intr_callback_unregister(intr_handle,
 540                                      ena_interrupt_handler_rte,
 541                                      adapter);
 542
 543         /*
 544          * MAC is not allocated dynamically. Setting NULL should prevent from
 545          * release of the resource in the rte_eth_dev_release_port().
 546          */
 547         dev->data->mac_addrs = NULL;
 548 }
 549
 550 static int
 551 ena_dev_reset(struct rte_eth_dev *dev)
 552 {
 553         int rc = 0;
 554
 555         ena_destroy_device(dev);
 556         rc = eth_ena_dev_init(dev);
 557         if (rc)
 558                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 559
 560         return rc;
 561 }
 562
 563 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 564                                struct rte_eth_rss_reta_entry64 *reta_conf,
 565                                uint16_t reta_size)
 566 {
 567         struct ena_adapter *adapter =
 568                 (struct ena_adapter *)(dev->data->dev_private);
 569         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 570         int rc, i;
 571         u16 entry_value;
 572         int conf_idx;
 573         int idx;
 574
 575         if ((reta_size == 0) || (reta_conf == NULL))
 576                 return -EINVAL;
 577
 578         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 579                 RTE_LOG(WARNING, PMD,
 580                         "indirection table %d is bigger than supported (%d)\n",
 581                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 582                 return -EINVAL;
 583         }
 584
 585         for (i = 0 ; i < reta_size ; i++) {
 586                 /* each reta_conf is for 64 entries.
 587                  * to support 128 we use 2 conf of 64
 588                  */
 589                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 590                 idx = i % RTE_RETA_GROUP_SIZE;
 591                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 592                         entry_value =
 593                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 594
 595                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 596                                                                i,
 597                                                                entry_value);
 598                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 599                                 RTE_LOG(ERR, PMD,
 600                                         "Cannot fill indirect table\n");
 601                                 return rc;
 602                         }
 603                 }
 604         }
 605
 606         rc = ena_com_indirect_table_set(ena_dev);
 607         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 608                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 609                 return rc;
 610         }
 611
 612         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 613                 __func__, reta_size, adapter->rte_dev->data->port_id);
 614
 615         return 0;
 616 }
 617
 618 /* Query redirection table. */
 619 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 620                               struct rte_eth_rss_reta_entry64 *reta_conf,
 621                               uint16_t reta_size)
 622 {
 623         struct ena_adapter *adapter =
 624                 (struct ena_adapter *)(dev->data->dev_private);
 625         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 626         int rc;
 627         int i;
 628         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 629         int reta_conf_idx;
 630         int reta_idx;
 631
 632         if (reta_size == 0 || reta_conf == NULL ||
 633             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 634                 return -EINVAL;
 635
 636         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 637         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 638                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 639                 return -ENOTSUP;
 640         }
 641
 642         for (i = 0 ; i < reta_size ; i++) {
 643                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 644                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 645                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 646                         reta_conf[reta_conf_idx].reta[reta_idx] =
 647                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 648         }
 649
 650         return 0;
 651 }
 652
 653 static int ena_rss_init_default(struct ena_adapter *adapter)
 654 {
 655         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 656         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 657         int rc, i;
 658         u32 val;
 659
 660         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 661         if (unlikely(rc)) {
 662                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 663                 goto err_rss_init;
 664         }
 665
 666         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 667                 val = i % nb_rx_queues;
 668                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 669                                                        ENA_IO_RXQ_IDX(val));
 670                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 671                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 672                         goto err_fill_indir;
 673                 }
 674         }
 675
 676         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 677                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 678         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 679                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 680                 goto err_fill_indir;
 681         }
 682
 683         rc = ena_com_set_default_hash_ctrl(ena_dev);
 684         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 685                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 686                 goto err_fill_indir;
 687         }
 688
 689         rc = ena_com_indirect_table_set(ena_dev);
 690         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 691                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 692                 goto err_fill_indir;
 693         }
 694         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 695                 adapter->rte_dev->data->port_id);
 696
 697         return 0;
 698
 699 err_fill_indir:
 700         ena_com_rss_destroy(ena_dev);
 701 err_rss_init:
 702
 703         return rc;
 704 }
 705
 706 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 707 {
 708         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 709         int nb_queues = dev->data->nb_rx_queues;
 710         int i;
 711
 712         for (i = 0; i < nb_queues; i++)
 713                 ena_rx_queue_release(queues[i]);
 714 }
 715
 716 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 717 {
 718         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 719         int nb_queues = dev->data->nb_tx_queues;
 720         int i;
 721
 722         for (i = 0; i < nb_queues; i++)
 723                 ena_tx_queue_release(queues[i]);
 724 }
 725
 726 static void ena_rx_queue_release(void *queue)
 727 {
 728         struct ena_ring *ring = (struct ena_ring *)queue;
 729
 730         /* Free ring resources */
 731         if (ring->rx_buffer_info)
 732                 rte_free(ring->rx_buffer_info);
 733         ring->rx_buffer_info = NULL;
 734
 735         if (ring->rx_refill_buffer)
 736                 rte_free(ring->rx_refill_buffer);
 737         ring->rx_refill_buffer = NULL;
 738
 739         if (ring->empty_rx_reqs)
 740                 rte_free(ring->empty_rx_reqs);
 741         ring->empty_rx_reqs = NULL;
 742
 743         ring->configured = 0;
 744
 745         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 746                 ring->port_id, ring->id);
 747 }
 748
 749 static void ena_tx_queue_release(void *queue)
 750 {
 751         struct ena_ring *ring = (struct ena_ring *)queue;
 752
 753         /* Free ring resources */
 754         if (ring->push_buf_intermediate_buf)
 755                 rte_free(ring->push_buf_intermediate_buf);
 756
 757         if (ring->tx_buffer_info)
 758                 rte_free(ring->tx_buffer_info);
 759
 760         if (ring->empty_tx_reqs)
 761                 rte_free(ring->empty_tx_reqs);
 762
 763         ring->empty_tx_reqs = NULL;
 764         ring->tx_buffer_info = NULL;
 765         ring->push_buf_intermediate_buf = NULL;
 766
 767         ring->configured = 0;
 768
 769         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 770                 ring->port_id, ring->id);
 771 }
 772
 773 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 774 {
 775         unsigned int i;
 776
 777         for (i = 0; i < ring->ring_size; ++i)
 778                 if (ring->rx_buffer_info[i]) {
 779                         rte_mbuf_raw_free(ring->rx_buffer_info[i]);
 780                         ring->rx_buffer_info[i] = NULL;
 781                 }
 782 }
 783
 784 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 785 {
 786         unsigned int i;
 787
 788         for (i = 0; i < ring->ring_size; ++i) {
 789                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 790
 791                 if (tx_buf->mbuf)
 792                         rte_pktmbuf_free(tx_buf->mbuf);
 793         }
 794 }
 795
 796 static int ena_link_update(struct rte_eth_dev *dev,
 797                            __rte_unused int wait_to_complete)
 798 {
 799         struct rte_eth_link *link = &dev->data->dev_link;
 800         struct ena_adapter *adapter;
 801
 802         adapter = (struct ena_adapter *)(dev->data->dev_private);
 803
 804         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 805         link->link_speed = ETH_SPEED_NUM_NONE;
 806         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 807
 808         return 0;
 809 }
 810
 811 static int ena_queue_start_all(struct rte_eth_dev *dev,
 812                                enum ena_ring_type ring_type)
 813 {
 814         struct ena_adapter *adapter =
 815                 (struct ena_adapter *)(dev->data->dev_private);
 816         struct ena_ring *queues = NULL;
 817         int nb_queues;
 818         int i = 0;
 819         int rc = 0;
 820
 821         if (ring_type == ENA_RING_TYPE_RX) {
 822                 queues = adapter->rx_ring;
 823                 nb_queues = dev->data->nb_rx_queues;
 824         } else {
 825                 queues = adapter->tx_ring;
 826                 nb_queues = dev->data->nb_tx_queues;
 827         }
 828         for (i = 0; i < nb_queues; i++) {
 829                 if (queues[i].configured) {
 830                         if (ring_type == ENA_RING_TYPE_RX) {
 831                                 ena_assert_msg(
 832                                         dev->data->rx_queues[i] == &queues[i],
 833                                         "Inconsistent state of rx queues\n");
 834                         } else {
 835                                 ena_assert_msg(
 836                                         dev->data->tx_queues[i] == &queues[i],
 837                                         "Inconsistent state of tx queues\n");
 838                         }
 839
 840                         rc = ena_queue_start(&queues[i]);
 841
 842                         if (rc) {
 843                                 PMD_INIT_LOG(ERR,
 844                                              "failed to start queue %d type(%d)",
 845                                              i, ring_type);
 846                                 goto err;
 847                         }
 848                 }
 849         }
 850
 851         return 0;
 852
 853 err:
 854         while (i--)
 855                 if (queues[i].configured)
 856                         ena_queue_stop(&queues[i]);
 857
 858         return rc;
 859 }
 860
 861 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 862 {
 863         uint32_t max_frame_len = adapter->max_mtu;
 864
 865         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 866             DEV_RX_OFFLOAD_JUMBO_FRAME)
 867                 max_frame_len =
 868                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 869
 870         return max_frame_len;
 871 }
 872
 873 static int ena_check_valid_conf(struct ena_adapter *adapter)
 874 {
 875         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 876
 877         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 878                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 879                                   "max mtu: %d, min mtu: %d",
 880                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 881                 return ENA_COM_UNSUPPORTED;
 882         }
 883
 884         return 0;
 885 }
 886
 887 static int
 888 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 889 {
 890         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 891         struct ena_com_dev *ena_dev = ctx->ena_dev;
 892         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 893         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 894
 895         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 896                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 897                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 898                 rx_queue_size = RTE_MIN(rx_queue_size,
 899                         max_queue_ext->max_rx_cq_depth);
 900                 rx_queue_size = RTE_MIN(rx_queue_size,
 901                         max_queue_ext->max_rx_sq_depth);
 902                 tx_queue_size = RTE_MIN(tx_queue_size,
 903                         max_queue_ext->max_tx_cq_depth);
 904
 905                 if (ena_dev->tx_mem_queue_type ==
 906                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 907                         tx_queue_size = RTE_MIN(tx_queue_size,
 908                                 llq->max_llq_depth);
 909                 } else {
 910                         tx_queue_size = RTE_MIN(tx_queue_size,
 911                                 max_queue_ext->max_tx_sq_depth);
 912                 }
 913
 914                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 915                         max_queue_ext->max_per_packet_rx_descs);
 916                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 917                         max_queue_ext->max_per_packet_tx_descs);
 918         } else {
 919                 struct ena_admin_queue_feature_desc *max_queues =
 920                         &ctx->get_feat_ctx->max_queues;
 921                 rx_queue_size = RTE_MIN(rx_queue_size,
 922                         max_queues->max_cq_depth);
 923                 rx_queue_size = RTE_MIN(rx_queue_size,
 924                         max_queues->max_sq_depth);
 925                 tx_queue_size = RTE_MIN(tx_queue_size,
 926                         max_queues->max_cq_depth);
 927
 928                 if (ena_dev->tx_mem_queue_type ==
 929                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 930                         tx_queue_size = RTE_MIN(tx_queue_size,
 931                                 llq->max_llq_depth);
 932                 } else {
 933                         tx_queue_size = RTE_MIN(tx_queue_size,
 934                                 max_queues->max_sq_depth);
 935                 }
 936
 937                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 938                         max_queues->max_packet_tx_descs);
 939                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 940                         max_queues->max_packet_rx_descs);
 941         }
 942
 943         /* Round down to the nearest power of 2 */
 944         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 945         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 946
 947         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 948                 PMD_INIT_LOG(ERR, "Invalid queue size");
 949                 return -EFAULT;
 950         }
 951
 952         ctx->rx_queue_size = rx_queue_size;
 953         ctx->tx_queue_size = tx_queue_size;
 954
 955         return 0;
 956 }
 957
 958 static void ena_stats_restart(struct rte_eth_dev *dev)
 959 {
 960         struct ena_adapter *adapter =
 961                 (struct ena_adapter *)(dev->data->dev_private);
 962
 963         rte_atomic64_init(&adapter->drv_stats->ierrors);
 964         rte_atomic64_init(&adapter->drv_stats->oerrors);
 965         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 966 }
 967
 968 static int ena_stats_get(struct rte_eth_dev *dev,
 969                           struct rte_eth_stats *stats)
 970 {
 971         struct ena_admin_basic_stats ena_stats;
 972         struct ena_adapter *adapter =
 973                 (struct ena_adapter *)(dev->data->dev_private);
 974         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 975         int rc;
 976         int i;
 977         int max_rings_stats;
 978
 979         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 980                 return -ENOTSUP;
 981
 982         memset(&ena_stats, 0, sizeof(ena_stats));
 983         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 984         if (unlikely(rc)) {
 985                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
 986                 return rc;
 987         }
 988
 989         /* Set of basic statistics from ENA */
 990         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 991                                           ena_stats.rx_pkts_low);
 992         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 993                                           ena_stats.tx_pkts_low);
 994         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 995                                         ena_stats.rx_bytes_low);
 996         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 997                                         ena_stats.tx_bytes_low);
 998         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 999                                          ena_stats.rx_drops_low);
1000
1001         /* Driver related stats */
1002         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1003         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1004         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1005
1006         max_rings_stats = RTE_MIN(dev->data->nb_rx_queues,
1007                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1008         for (i = 0; i < max_rings_stats; ++i) {
1009                 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats;
1010
1011                 stats->q_ibytes[i] = rx_stats->bytes;
1012                 stats->q_ipackets[i] = rx_stats->cnt;
1013                 stats->q_errors[i] = rx_stats->bad_desc_num +
1014                         rx_stats->bad_req_id;
1015         }
1016
1017         max_rings_stats = RTE_MIN(dev->data->nb_tx_queues,
1018                 RTE_ETHDEV_QUEUE_STAT_CNTRS);
1019         for (i = 0; i < max_rings_stats; ++i) {
1020                 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats;
1021
1022                 stats->q_obytes[i] = tx_stats->bytes;
1023                 stats->q_opackets[i] = tx_stats->cnt;
1024         }
1025
1026         return 0;
1027 }
1028
1029 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1030 {
1031         struct ena_adapter *adapter;
1032         struct ena_com_dev *ena_dev;
1033         int rc = 0;
1034
1035         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1036         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1037         adapter = (struct ena_adapter *)(dev->data->dev_private);
1038
1039         ena_dev = &adapter->ena_dev;
1040         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1041
1042         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1043                 RTE_LOG(ERR, PMD,
1044                         "Invalid MTU setting. new_mtu: %d "
1045                         "max mtu: %d min mtu: %d\n",
1046                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1047                 return -EINVAL;
1048         }
1049
1050         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1051         if (rc)
1052                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1053         else
1054                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1055
1056         return rc;
1057 }
1058
1059 static int ena_start(struct rte_eth_dev *dev)
1060 {
1061         struct ena_adapter *adapter =
1062                 (struct ena_adapter *)(dev->data->dev_private);
1063         uint64_t ticks;
1064         int rc = 0;
1065
1066         rc = ena_check_valid_conf(adapter);
1067         if (rc)
1068                 return rc;
1069
1070         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1071         if (rc)
1072                 return rc;
1073
1074         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1075         if (rc)
1076                 goto err_start_tx;
1077
1078         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1079             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1080                 rc = ena_rss_init_default(adapter);
1081                 if (rc)
1082                         goto err_rss_init;
1083         }
1084
1085         ena_stats_restart(dev);
1086
1087         adapter->timestamp_wd = rte_get_timer_cycles();
1088         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1089
1090         ticks = rte_get_timer_hz();
1091         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1092                         ena_timer_wd_callback, adapter);
1093
1094         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1095
1096         return 0;
1097
1098 err_rss_init:
1099         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1100 err_start_tx:
1101         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1102         return rc;
1103 }
1104
1105 static void ena_stop(struct rte_eth_dev *dev)
1106 {
1107         struct ena_adapter *adapter =
1108                 (struct ena_adapter *)(dev->data->dev_private);
1109         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1110         int rc;
1111
1112         rte_timer_stop_sync(&adapter->timer_wd);
1113         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1114         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1115
1116         if (adapter->trigger_reset) {
1117                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1118                 if (rc)
1119                         RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1120         }
1121
1122         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1123 }
1124
1125 static int ena_create_io_queue(struct ena_ring *ring)
1126 {
1127         struct ena_adapter *adapter;
1128         struct ena_com_dev *ena_dev;
1129         struct ena_com_create_io_ctx ctx =
1130                 /* policy set to _HOST just to satisfy icc compiler */
1131                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1132                   0, 0, 0, 0, 0 };
1133         uint16_t ena_qid;
1134         unsigned int i;
1135         int rc;
1136
1137         adapter = ring->adapter;
1138         ena_dev = &adapter->ena_dev;
1139
1140         if (ring->type == ENA_RING_TYPE_TX) {
1141                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1142                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1143                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1144                 ctx.queue_size = adapter->tx_ring_size;
1145                 for (i = 0; i < ring->ring_size; i++)
1146                         ring->empty_tx_reqs[i] = i;
1147         } else {
1148                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1149                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1150                 ctx.queue_size = adapter->rx_ring_size;
1151                 for (i = 0; i < ring->ring_size; i++)
1152                         ring->empty_rx_reqs[i] = i;
1153         }
1154         ctx.qid = ena_qid;
1155         ctx.msix_vector = -1; /* interrupts not used */
1156         ctx.numa_node = ena_cpu_to_node(ring->id);
1157
1158         rc = ena_com_create_io_queue(ena_dev, &ctx);
1159         if (rc) {
1160                 RTE_LOG(ERR, PMD,
1161                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1162                         ring->id, ena_qid, rc);
1163                 return rc;
1164         }
1165
1166         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1167                                      &ring->ena_com_io_sq,
1168                                      &ring->ena_com_io_cq);
1169         if (rc) {
1170                 RTE_LOG(ERR, PMD,
1171                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1172                         ring->id, rc);
1173                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1174                 return rc;
1175         }
1176
1177         if (ring->type == ENA_RING_TYPE_TX)
1178                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1179
1180         return 0;
1181 }
1182
1183 static void ena_queue_stop(struct ena_ring *ring)
1184 {
1185         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1186
1187         if (ring->type == ENA_RING_TYPE_RX) {
1188                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1189                 ena_rx_queue_release_bufs(ring);
1190         } else {
1191                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1192                 ena_tx_queue_release_bufs(ring);
1193         }
1194 }
1195
1196 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1197                               enum ena_ring_type ring_type)
1198 {
1199         struct ena_adapter *adapter =
1200                 (struct ena_adapter *)(dev->data->dev_private);
1201         struct ena_ring *queues = NULL;
1202         uint16_t nb_queues, i;
1203
1204         if (ring_type == ENA_RING_TYPE_RX) {
1205                 queues = adapter->rx_ring;
1206                 nb_queues = dev->data->nb_rx_queues;
1207         } else {
1208                 queues = adapter->tx_ring;
1209                 nb_queues = dev->data->nb_tx_queues;
1210         }
1211
1212         for (i = 0; i < nb_queues; ++i)
1213                 if (queues[i].configured)
1214                         ena_queue_stop(&queues[i]);
1215 }
1216
1217 static int ena_queue_start(struct ena_ring *ring)
1218 {
1219         int rc, bufs_num;
1220
1221         ena_assert_msg(ring->configured == 1,
1222                        "Trying to start unconfigured queue\n");
1223
1224         rc = ena_create_io_queue(ring);
1225         if (rc) {
1226                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1227                 return rc;
1228         }
1229
1230         ring->next_to_clean = 0;
1231         ring->next_to_use = 0;
1232
1233         if (ring->type == ENA_RING_TYPE_TX)
1234                 return 0;
1235
1236         bufs_num = ring->ring_size - 1;
1237         rc = ena_populate_rx_queue(ring, bufs_num);
1238         if (rc != bufs_num) {
1239                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1240                                          ENA_IO_RXQ_IDX(ring->id));
1241                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1242                 return ENA_COM_FAULT;
1243         }
1244
1245         return 0;
1246 }
1247
1248 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1249                               uint16_t queue_idx,
1250                               uint16_t nb_desc,
1251                               __rte_unused unsigned int socket_id,
1252                               const struct rte_eth_txconf *tx_conf)
1253 {
1254         struct ena_ring *txq = NULL;
1255         struct ena_adapter *adapter =
1256                 (struct ena_adapter *)(dev->data->dev_private);
1257         unsigned int i;
1258
1259         txq = &adapter->tx_ring[queue_idx];
1260
1261         if (txq->configured) {
1262                 RTE_LOG(CRIT, PMD,
1263                         "API violation. Queue %d is already configured\n",
1264                         queue_idx);
1265                 return ENA_COM_FAULT;
1266         }
1267
1268         if (!rte_is_power_of_2(nb_desc)) {
1269                 RTE_LOG(ERR, PMD,
1270                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1271                         nb_desc);
1272                 return -EINVAL;
1273         }
1274
1275         if (nb_desc > adapter->tx_ring_size) {
1276                 RTE_LOG(ERR, PMD,
1277                         "Unsupported size of TX queue (max size: %d)\n",
1278                         adapter->tx_ring_size);
1279                 return -EINVAL;
1280         }
1281
1282         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1283                 nb_desc = adapter->tx_ring_size;
1284
1285         txq->port_id = dev->data->port_id;
1286         txq->next_to_clean = 0;
1287         txq->next_to_use = 0;
1288         txq->ring_size = nb_desc;
1289
1290         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1291                                           sizeof(struct ena_tx_buffer) *
1292                                           txq->ring_size,
1293                                           RTE_CACHE_LINE_SIZE);
1294         if (!txq->tx_buffer_info) {
1295                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1296                 return -ENOMEM;
1297         }
1298
1299         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1300                                          sizeof(u16) * txq->ring_size,
1301                                          RTE_CACHE_LINE_SIZE);
1302         if (!txq->empty_tx_reqs) {
1303                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1304                 rte_free(txq->tx_buffer_info);
1305                 return -ENOMEM;
1306         }
1307
1308         txq->push_buf_intermediate_buf =
1309                 rte_zmalloc("txq->push_buf_intermediate_buf",
1310                             txq->tx_max_header_size,
1311                             RTE_CACHE_LINE_SIZE);
1312         if (!txq->push_buf_intermediate_buf) {
1313                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1314                 rte_free(txq->tx_buffer_info);
1315                 rte_free(txq->empty_tx_reqs);
1316                 return -ENOMEM;
1317         }
1318
1319         for (i = 0; i < txq->ring_size; i++)
1320                 txq->empty_tx_reqs[i] = i;
1321
1322         if (tx_conf != NULL) {
1323                 txq->offloads =
1324                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1325         }
1326
1327         /* Store pointer to this queue in upper layer */
1328         txq->configured = 1;
1329         dev->data->tx_queues[queue_idx] = txq;
1330
1331         return 0;
1332 }
1333
1334 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1335                               uint16_t queue_idx,
1336                               uint16_t nb_desc,
1337                               __rte_unused unsigned int socket_id,
1338                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1339                               struct rte_mempool *mp)
1340 {
1341         struct ena_adapter *adapter =
1342                 (struct ena_adapter *)(dev->data->dev_private);
1343         struct ena_ring *rxq = NULL;
1344         int i;
1345
1346         rxq = &adapter->rx_ring[queue_idx];
1347         if (rxq->configured) {
1348                 RTE_LOG(CRIT, PMD,
1349                         "API violation. Queue %d is already configured\n",
1350                         queue_idx);
1351                 return ENA_COM_FAULT;
1352         }
1353
1354         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1355                 nb_desc = adapter->rx_ring_size;
1356
1357         if (!rte_is_power_of_2(nb_desc)) {
1358                 RTE_LOG(ERR, PMD,
1359                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1360                         nb_desc);
1361                 return -EINVAL;
1362         }
1363
1364         if (nb_desc > adapter->rx_ring_size) {
1365                 RTE_LOG(ERR, PMD,
1366                         "Unsupported size of RX queue (max size: %d)\n",
1367                         adapter->rx_ring_size);
1368                 return -EINVAL;
1369         }
1370
1371         rxq->port_id = dev->data->port_id;
1372         rxq->next_to_clean = 0;
1373         rxq->next_to_use = 0;
1374         rxq->ring_size = nb_desc;
1375         rxq->mb_pool = mp;
1376
1377         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1378                                           sizeof(struct rte_mbuf *) * nb_desc,
1379                                           RTE_CACHE_LINE_SIZE);
1380         if (!rxq->rx_buffer_info) {
1381                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1382                 return -ENOMEM;
1383         }
1384
1385         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1386                                             sizeof(struct rte_mbuf *) * nb_desc,
1387                                             RTE_CACHE_LINE_SIZE);
1388
1389         if (!rxq->rx_refill_buffer) {
1390                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1391                 rte_free(rxq->rx_buffer_info);
1392                 rxq->rx_buffer_info = NULL;
1393                 return -ENOMEM;
1394         }
1395
1396         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1397                                          sizeof(uint16_t) * nb_desc,
1398                                          RTE_CACHE_LINE_SIZE);
1399         if (!rxq->empty_rx_reqs) {
1400                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1401                 rte_free(rxq->rx_buffer_info);
1402                 rxq->rx_buffer_info = NULL;
1403                 rte_free(rxq->rx_refill_buffer);
1404                 rxq->rx_refill_buffer = NULL;
1405                 return -ENOMEM;
1406         }
1407
1408         for (i = 0; i < nb_desc; i++)
1409                 rxq->empty_rx_reqs[i] = i;
1410
1411         /* Store pointer to this queue in upper layer */
1412         rxq->configured = 1;
1413         dev->data->rx_queues[queue_idx] = rxq;
1414
1415         return 0;
1416 }
1417
1418 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1419 {
1420         unsigned int i;
1421         int rc;
1422         uint16_t ring_size = rxq->ring_size;
1423         uint16_t ring_mask = ring_size - 1;
1424         uint16_t next_to_use = rxq->next_to_use;
1425         uint16_t in_use, req_id;
1426         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1427
1428         if (unlikely(!count))
1429                 return 0;
1430
1431         in_use = rxq->next_to_use - rxq->next_to_clean;
1432         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1433
1434         /* get resources for incoming packets */
1435         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1436         if (unlikely(rc < 0)) {
1437                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1438                 ++rxq->rx_stats.page_alloc_fail;
1439                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1440                 return 0;
1441         }
1442
1443         for (i = 0; i < count; i++) {
1444                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1445                 struct rte_mbuf *mbuf = mbufs[i];
1446                 struct ena_com_buf ebuf;
1447
1448                 if (likely((i + 4) < count))
1449                         rte_prefetch0(mbufs[i + 4]);
1450
1451                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1452                 rc = validate_rx_req_id(rxq, req_id);
1453                 if (unlikely(rc < 0))
1454                         break;
1455                 rxq->rx_buffer_info[req_id] = mbuf;
1456
1457                 /* prepare physical address for DMA transaction */
1458                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1459                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1460                 /* pass resource to device */
1461                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1462                                                 &ebuf, req_id);
1463                 if (unlikely(rc)) {
1464                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1465                         rxq->rx_buffer_info[req_id] = NULL;
1466                         break;
1467                 }
1468                 next_to_use++;
1469         }
1470
1471         if (unlikely(i < count)) {
1472                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1473                         "buffers (from %d)\n", rxq->id, i, count);
1474                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1475                                      count - i);
1476         }
1477
1478         /* When we submitted free recources to device... */
1479         if (likely(i > 0)) {
1480                 /* ...let HW know that it can fill buffers with data
1481                  *
1482                  * Add memory barrier to make sure the desc were written before
1483                  * issue a doorbell
1484                  */
1485                 rte_wmb();
1486                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1487
1488                 rxq->next_to_use = next_to_use;
1489         }
1490
1491         return i;
1492 }
1493
1494 static int ena_device_init(struct ena_com_dev *ena_dev,
1495                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1496                            bool *wd_state)
1497 {
1498         uint32_t aenq_groups;
1499         int rc;
1500         bool readless_supported;
1501
1502         /* Initialize mmio registers */
1503         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1504         if (rc) {
1505                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1506                 return rc;
1507         }
1508
1509         /* The PCIe configuration space revision id indicate if mmio reg
1510          * read is disabled.
1511          */
1512         readless_supported =
1513                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1514                                & ENA_MMIO_DISABLE_REG_READ);
1515         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1516
1517         /* reset device */
1518         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1519         if (rc) {
1520                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1521                 goto err_mmio_read_less;
1522         }
1523
1524         /* check FW version */
1525         rc = ena_com_validate_version(ena_dev);
1526         if (rc) {
1527                 RTE_LOG(ERR, PMD, "device version is too low\n");
1528                 goto err_mmio_read_less;
1529         }
1530
1531         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1532
1533         /* ENA device administration layer init */
1534         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1535         if (rc) {
1536                 RTE_LOG(ERR, PMD,
1537                         "cannot initialize ena admin queue with device\n");
1538                 goto err_mmio_read_less;
1539         }
1540
1541         /* To enable the msix interrupts the driver needs to know the number
1542          * of queues. So the driver uses polling mode to retrieve this
1543          * information.
1544          */
1545         ena_com_set_admin_polling_mode(ena_dev, true);
1546
1547         ena_config_host_info(ena_dev);
1548
1549         /* Get Device Attributes and features */
1550         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1551         if (rc) {
1552                 RTE_LOG(ERR, PMD,
1553                         "cannot get attribute for ena device rc= %d\n", rc);
1554                 goto err_admin_init;
1555         }
1556
1557         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1558                       BIT(ENA_ADMIN_NOTIFICATION) |
1559                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1560                       BIT(ENA_ADMIN_FATAL_ERROR) |
1561                       BIT(ENA_ADMIN_WARNING);
1562
1563         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1564         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1565         if (rc) {
1566                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1567                 goto err_admin_init;
1568         }
1569
1570         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1571
1572         return 0;
1573
1574 err_admin_init:
1575         ena_com_admin_destroy(ena_dev);
1576
1577 err_mmio_read_less:
1578         ena_com_mmio_reg_read_request_destroy(ena_dev);
1579
1580         return rc;
1581 }
1582
1583 static void ena_interrupt_handler_rte(void *cb_arg)
1584 {
1585         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1586         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1587
1588         ena_com_admin_q_comp_intr_handler(ena_dev);
1589         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1590                 ena_com_aenq_intr_handler(ena_dev, adapter);
1591 }
1592
1593 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1594 {
1595         if (!adapter->wd_state)
1596                 return;
1597
1598         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1599                 return;
1600
1601         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1602             adapter->keep_alive_timeout)) {
1603                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1604                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1605                 adapter->trigger_reset = true;
1606         }
1607 }
1608
1609 /* Check if admin queue is enabled */
1610 static void check_for_admin_com_state(struct ena_adapter *adapter)
1611 {
1612         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1613                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1614                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1615                 adapter->trigger_reset = true;
1616         }
1617 }
1618
1619 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1620                                   void *arg)
1621 {
1622         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1623         struct rte_eth_dev *dev = adapter->rte_dev;
1624
1625         check_for_missing_keep_alive(adapter);
1626         check_for_admin_com_state(adapter);
1627
1628         if (unlikely(adapter->trigger_reset)) {
1629                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1630                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1631                         NULL);
1632         }
1633 }
1634
1635 static inline void
1636 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1637 {
1638         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1639         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1640         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1641         llq_config->llq_num_decs_before_header =
1642                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1643         llq_config->llq_ring_entry_size_value = 128;
1644 }
1645
1646 static int
1647 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1648                                 struct ena_com_dev *ena_dev,
1649                                 struct ena_admin_feature_llq_desc *llq,
1650                                 struct ena_llq_configurations *llq_default_configurations)
1651 {
1652         int rc;
1653         u32 llq_feature_mask;
1654
1655         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1656         if (!(ena_dev->supported_features & llq_feature_mask)) {
1657                 RTE_LOG(INFO, PMD,
1658                         "LLQ is not supported. Fallback to host mode policy.\n");
1659                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1660                 return 0;
1661         }
1662
1663         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1664         if (unlikely(rc)) {
1665                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1666                         "Fallback to host mode policy.");
1667                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1668                 return 0;
1669         }
1670
1671         /* Nothing to config, exit */
1672         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1673                 return 0;
1674
1675         if (!adapter->dev_mem_base) {
1676                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1677                         "Fallback to host mode policy.\n.");
1678                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1679                 return 0;
1680         }
1681
1682         ena_dev->mem_bar = adapter->dev_mem_base;
1683
1684         return 0;
1685 }
1686
1687 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1688                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1689 {
1690         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1691
1692         /* Regular queues capabilities */
1693         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1694                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1695                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1696                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1697                                     max_queue_ext->max_rx_cq_num);
1698                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1699                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1700         } else {
1701                 struct ena_admin_queue_feature_desc *max_queues =
1702                         &get_feat_ctx->max_queues;
1703                 io_tx_sq_num = max_queues->max_sq_num;
1704                 io_tx_cq_num = max_queues->max_cq_num;
1705                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1706         }
1707
1708         /* In case of LLQ use the llq number in the get feature cmd */
1709         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1710                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1711
1712         io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1713         io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1714         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1715         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1716
1717         if (unlikely(io_queue_num == 0)) {
1718                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1719                 return -EFAULT;
1720         }
1721
1722         return io_queue_num;
1723 }
1724
1725 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1726 {
1727         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1728         struct rte_pci_device *pci_dev;
1729         struct rte_intr_handle *intr_handle;
1730         struct ena_adapter *adapter =
1731                 (struct ena_adapter *)(eth_dev->data->dev_private);
1732         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1733         struct ena_com_dev_get_features_ctx get_feat_ctx;
1734         struct ena_llq_configurations llq_config;
1735         const char *queue_type_str;
1736         int rc;
1737
1738         static int adapters_found;
1739         bool wd_state;
1740
1741         memset(adapter, 0, sizeof(struct ena_adapter));
1742         ena_dev = &adapter->ena_dev;
1743
1744         eth_dev->dev_ops = &ena_dev_ops;
1745         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1746         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1747         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1748         adapter->rte_eth_dev_data = eth_dev->data;
1749         adapter->rte_dev = eth_dev;
1750
1751         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1752                 return 0;
1753
1754         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1755         adapter->pdev = pci_dev;
1756
1757         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1758                      pci_dev->addr.domain,
1759                      pci_dev->addr.bus,
1760                      pci_dev->addr.devid,
1761                      pci_dev->addr.function);
1762
1763         intr_handle = &pci_dev->intr_handle;
1764
1765         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1766         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1767
1768         if (!adapter->regs) {
1769                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1770                              ENA_REGS_BAR);
1771                 return -ENXIO;
1772         }
1773
1774         ena_dev->reg_bar = adapter->regs;
1775         ena_dev->dmadev = adapter->pdev;
1776
1777         adapter->id_number = adapters_found;
1778
1779         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1780                  adapter->id_number);
1781
1782         /* device specific initialization routine */
1783         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1784         if (rc) {
1785                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1786                 goto err;
1787         }
1788         adapter->wd_state = wd_state;
1789
1790         set_default_llq_configurations(&llq_config);
1791         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1792                                              &get_feat_ctx.llq, &llq_config);
1793         if (unlikely(rc)) {
1794                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1795                 return rc;
1796         }
1797
1798         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1799                 queue_type_str = "Regular";
1800         else
1801                 queue_type_str = "Low latency";
1802         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1803
1804         calc_queue_ctx.ena_dev = ena_dev;
1805         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1806         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1807                                                     &get_feat_ctx);
1808
1809         rc = ena_calc_queue_size(&calc_queue_ctx);
1810         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1811                 rc = -EFAULT;
1812                 goto err_device_destroy;
1813         }
1814
1815         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1816         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1817
1818         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1819         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1820
1821         /* prepare ring structures */
1822         ena_init_rings(adapter);
1823
1824         ena_config_debug_area(adapter);
1825
1826         /* Set max MTU for this device */
1827         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1828
1829         /* set device support for TSO */
1830         adapter->tso4_supported = get_feat_ctx.offload.tx &
1831                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1832
1833         /* Copy MAC address and point DPDK to it */
1834         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1835         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1836                         (struct ether_addr *)adapter->mac_addr);
1837
1838         /*
1839          * Pass the information to the rte_eth_dev_close() that it should also
1840          * release the private port resources.
1841          */
1842         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1843
1844         adapter->drv_stats = rte_zmalloc("adapter stats",
1845                                          sizeof(*adapter->drv_stats),
1846                                          RTE_CACHE_LINE_SIZE);
1847         if (!adapter->drv_stats) {
1848                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1849                 rc = -ENOMEM;
1850                 goto err_delete_debug_area;
1851         }
1852
1853         rte_intr_callback_register(intr_handle,
1854                                    ena_interrupt_handler_rte,
1855                                    adapter);
1856         rte_intr_enable(intr_handle);
1857         ena_com_set_admin_polling_mode(ena_dev, false);
1858         ena_com_admin_aenq_enable(ena_dev);
1859
1860         if (adapters_found == 0)
1861                 rte_timer_subsystem_init();
1862         rte_timer_init(&adapter->timer_wd);
1863
1864         adapters_found++;
1865         adapter->state = ENA_ADAPTER_STATE_INIT;
1866
1867         return 0;
1868
1869 err_delete_debug_area:
1870         ena_com_delete_debug_area(ena_dev);
1871
1872 err_device_destroy:
1873         ena_com_delete_host_info(ena_dev);
1874         ena_com_admin_destroy(ena_dev);
1875
1876 err:
1877         return rc;
1878 }
1879
1880 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1881 {
1882         struct ena_adapter *adapter =
1883                 (struct ena_adapter *)(eth_dev->data->dev_private);
1884         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1885
1886         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1887                 return;
1888
1889         ena_com_set_admin_running_state(ena_dev, false);
1890
1891         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1892                 ena_close(eth_dev);
1893
1894         ena_com_delete_debug_area(ena_dev);
1895         ena_com_delete_host_info(ena_dev);
1896
1897         ena_com_abort_admin_commands(ena_dev);
1898         ena_com_wait_for_abort_completion(ena_dev);
1899         ena_com_admin_destroy(ena_dev);
1900         ena_com_mmio_reg_read_request_destroy(ena_dev);
1901
1902         adapter->state = ENA_ADAPTER_STATE_FREE;
1903 }
1904
1905 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1906 {
1907         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1908                 return 0;
1909
1910         ena_destroy_device(eth_dev);
1911
1912         eth_dev->dev_ops = NULL;
1913         eth_dev->rx_pkt_burst = NULL;
1914         eth_dev->tx_pkt_burst = NULL;
1915         eth_dev->tx_pkt_prepare = NULL;
1916
1917         return 0;
1918 }
1919
1920 static int ena_dev_configure(struct rte_eth_dev *dev)
1921 {
1922         struct ena_adapter *adapter =
1923                 (struct ena_adapter *)(dev->data->dev_private);
1924
1925         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1926
1927         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1928         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1929         return 0;
1930 }
1931
1932 static void ena_init_rings(struct ena_adapter *adapter)
1933 {
1934         int i;
1935
1936         for (i = 0; i < adapter->num_queues; i++) {
1937                 struct ena_ring *ring = &adapter->tx_ring[i];
1938
1939                 ring->configured = 0;
1940                 ring->type = ENA_RING_TYPE_TX;
1941                 ring->adapter = adapter;
1942                 ring->id = i;
1943                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1944                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1945                 ring->sgl_size = adapter->max_tx_sgl_size;
1946         }
1947
1948         for (i = 0; i < adapter->num_queues; i++) {
1949                 struct ena_ring *ring = &adapter->rx_ring[i];
1950
1951                 ring->configured = 0;
1952                 ring->type = ENA_RING_TYPE_RX;
1953                 ring->adapter = adapter;
1954                 ring->id = i;
1955                 ring->sgl_size = adapter->max_rx_sgl_size;
1956         }
1957 }
1958
1959 static void ena_infos_get(struct rte_eth_dev *dev,
1960                           struct rte_eth_dev_info *dev_info)
1961 {
1962         struct ena_adapter *adapter;
1963         struct ena_com_dev *ena_dev;
1964         struct ena_com_dev_get_features_ctx feat;
1965         uint64_t rx_feat = 0, tx_feat = 0;
1966         int rc = 0;
1967
1968         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1969         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1970         adapter = (struct ena_adapter *)(dev->data->dev_private);
1971
1972         ena_dev = &adapter->ena_dev;
1973         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1974
1975         dev_info->speed_capa =
1976                         ETH_LINK_SPEED_1G   |
1977                         ETH_LINK_SPEED_2_5G |
1978                         ETH_LINK_SPEED_5G   |
1979                         ETH_LINK_SPEED_10G  |
1980                         ETH_LINK_SPEED_25G  |
1981                         ETH_LINK_SPEED_40G  |
1982                         ETH_LINK_SPEED_50G  |
1983                         ETH_LINK_SPEED_100G;
1984
1985         /* Get supported features from HW */
1986         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1987         if (unlikely(rc)) {
1988                 RTE_LOG(ERR, PMD,
1989                         "Cannot get attribute for ena device rc= %d\n", rc);
1990                 return;
1991         }
1992
1993         /* Set Tx & Rx features available for device */
1994         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1995                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1996
1997         if (feat.offload.tx &
1998             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1999                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
2000                         DEV_TX_OFFLOAD_UDP_CKSUM |
2001                         DEV_TX_OFFLOAD_TCP_CKSUM;
2002
2003         if (feat.offload.rx_supported &
2004             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2005                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
2006                         DEV_RX_OFFLOAD_UDP_CKSUM  |
2007                         DEV_RX_OFFLOAD_TCP_CKSUM;
2008
2009         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2010
2011         /* Inform framework about available features */
2012         dev_info->rx_offload_capa = rx_feat;
2013         dev_info->rx_queue_offload_capa = rx_feat;
2014         dev_info->tx_offload_capa = tx_feat;
2015         dev_info->tx_queue_offload_capa = tx_feat;
2016
2017         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
2018                                            ETH_RSS_UDP;
2019
2020         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2021         dev_info->max_rx_pktlen  = adapter->max_mtu;
2022         dev_info->max_mac_addrs = 1;
2023
2024         dev_info->max_rx_queues = adapter->num_queues;
2025         dev_info->max_tx_queues = adapter->num_queues;
2026         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2027
2028         adapter->tx_supported_offloads = tx_feat;
2029         adapter->rx_supported_offloads = rx_feat;
2030
2031         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2032         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2033         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2034                                         adapter->max_rx_sgl_size);
2035         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2036                                         adapter->max_rx_sgl_size);
2037
2038         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2039         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2040         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2041                                         adapter->max_tx_sgl_size);
2042         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2043                                         adapter->max_tx_sgl_size);
2044 }
2045
2046 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2047                                   uint16_t nb_pkts)
2048 {
2049         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2050         unsigned int ring_size = rx_ring->ring_size;
2051         unsigned int ring_mask = ring_size - 1;
2052         uint16_t next_to_clean = rx_ring->next_to_clean;
2053         uint16_t desc_in_use = 0;
2054         uint16_t req_id;
2055         unsigned int recv_idx = 0;
2056         struct rte_mbuf *mbuf = NULL;
2057         struct rte_mbuf *mbuf_head = NULL;
2058         struct rte_mbuf *mbuf_prev = NULL;
2059         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2060         unsigned int completed;
2061
2062         struct ena_com_rx_ctx ena_rx_ctx;
2063         int rc = 0;
2064
2065         /* Check adapter state */
2066         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2067                 RTE_LOG(ALERT, PMD,
2068                         "Trying to receive pkts while device is NOT running\n");
2069                 return 0;
2070         }
2071
2072         desc_in_use = rx_ring->next_to_use - next_to_clean;
2073         if (unlikely(nb_pkts > desc_in_use))
2074                 nb_pkts = desc_in_use;
2075
2076         for (completed = 0; completed < nb_pkts; completed++) {
2077                 int segments = 0;
2078
2079                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2080                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2081                 ena_rx_ctx.descs = 0;
2082                 /* receive packet context */
2083                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2084                                     rx_ring->ena_com_io_sq,
2085                                     &ena_rx_ctx);
2086                 if (unlikely(rc)) {
2087                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2088                         rx_ring->adapter->reset_reason =
2089                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2090                         rx_ring->adapter->trigger_reset = true;
2091                         return 0;
2092                 }
2093
2094                 if (unlikely(ena_rx_ctx.descs == 0))
2095                         break;
2096
2097                 while (segments < ena_rx_ctx.descs) {
2098                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2099                         rc = validate_rx_req_id(rx_ring, req_id);
2100                         if (unlikely(rc)) {
2101                                 if (segments != 0)
2102                                         rte_mbuf_raw_free(mbuf_head);
2103                                 break;
2104                         }
2105
2106                         mbuf = rx_buff_info[req_id];
2107                         rx_buff_info[req_id] = NULL;
2108                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2109                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2110                         mbuf->refcnt = 1;
2111                         mbuf->next = NULL;
2112                         if (unlikely(segments == 0)) {
2113                                 mbuf->nb_segs = ena_rx_ctx.descs;
2114                                 mbuf->port = rx_ring->port_id;
2115                                 mbuf->pkt_len = 0;
2116                                 mbuf_head = mbuf;
2117                         } else {
2118                                 /* for multi-segment pkts create mbuf chain */
2119                                 mbuf_prev->next = mbuf;
2120                         }
2121                         mbuf_head->pkt_len += mbuf->data_len;
2122
2123                         mbuf_prev = mbuf;
2124                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2125                                 req_id;
2126                         segments++;
2127                         next_to_clean++;
2128                 }
2129                 if (unlikely(rc))
2130                         break;
2131
2132                 /* fill mbuf attributes if any */
2133                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2134                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2135
2136                 /* pass to DPDK application head mbuf */
2137                 rx_pkts[recv_idx] = mbuf_head;
2138                 recv_idx++;
2139                 rx_ring->rx_stats.bytes += mbuf_head->pkt_len;
2140         }
2141
2142         rx_ring->rx_stats.cnt += recv_idx;
2143         rx_ring->next_to_clean = next_to_clean;
2144
2145         desc_in_use = desc_in_use - completed + 1;
2146         /* Burst refill to save doorbells, memory barriers, const interval */
2147         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2148                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2149
2150         return recv_idx;
2151 }
2152
2153 static uint16_t
2154 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2155                 uint16_t nb_pkts)
2156 {
2157         int32_t ret;
2158         uint32_t i;
2159         struct rte_mbuf *m;
2160         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2161         struct ipv4_hdr *ip_hdr;
2162         uint64_t ol_flags;
2163         uint16_t frag_field;
2164
2165         for (i = 0; i != nb_pkts; i++) {
2166                 m = tx_pkts[i];
2167                 ol_flags = m->ol_flags;
2168
2169                 if (!(ol_flags & PKT_TX_IPV4))
2170                         continue;
2171
2172                 /* If there was not L2 header length specified, assume it is
2173                  * length of the ethernet header.
2174                  */
2175                 if (unlikely(m->l2_len == 0))
2176                         m->l2_len = sizeof(struct ether_hdr);
2177
2178                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2179                                                  m->l2_len);
2180                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2181
2182                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2183                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2184
2185                         /* If IPv4 header has DF flag enabled and TSO support is
2186                          * disabled, partial chcecksum should not be calculated.
2187                          */
2188                         if (!tx_ring->adapter->tso4_supported)
2189                                 continue;
2190                 }
2191
2192                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2193                                 (ol_flags & PKT_TX_L4_MASK) ==
2194                                 PKT_TX_SCTP_CKSUM) {
2195                         rte_errno = -ENOTSUP;
2196                         return i;
2197                 }
2198
2199 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2200                 ret = rte_validate_tx_offload(m);
2201                 if (ret != 0) {
2202                         rte_errno = ret;
2203                         return i;
2204                 }
2205 #endif
2206
2207                 /* In case we are supposed to TSO and have DF not set (DF=0)
2208                  * hardware must be provided with partial checksum, otherwise
2209                  * it will take care of necessary calculations.
2210                  */
2211
2212                 ret = rte_net_intel_cksum_flags_prepare(m,
2213                         ol_flags & ~PKT_TX_TCP_SEG);
2214                 if (ret != 0) {
2215                         rte_errno = ret;
2216                         return i;
2217                 }
2218         }
2219
2220         return i;
2221 }
2222
2223 static void ena_update_hints(struct ena_adapter *adapter,
2224                              struct ena_admin_ena_hw_hints *hints)
2225 {
2226         if (hints->admin_completion_tx_timeout)
2227                 adapter->ena_dev.admin_queue.completion_timeout =
2228                         hints->admin_completion_tx_timeout * 1000;
2229
2230         if (hints->mmio_read_timeout)
2231                 /* convert to usec */
2232                 adapter->ena_dev.mmio_read.reg_read_to =
2233                         hints->mmio_read_timeout * 1000;
2234
2235         if (hints->driver_watchdog_timeout) {
2236                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2237                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2238                 else
2239                         // Convert msecs to ticks
2240                         adapter->keep_alive_timeout =
2241                                 (hints->driver_watchdog_timeout *
2242                                 rte_get_timer_hz()) / 1000;
2243         }
2244 }
2245
2246 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2247                                         struct rte_mbuf *mbuf)
2248 {
2249         struct ena_com_dev *ena_dev;
2250         int num_segments, header_len, rc;
2251
2252         ena_dev = &tx_ring->adapter->ena_dev;
2253         num_segments = mbuf->nb_segs;
2254         header_len = mbuf->data_len;
2255
2256         if (likely(num_segments < tx_ring->sgl_size))
2257                 return 0;
2258
2259         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2260             (num_segments == tx_ring->sgl_size) &&
2261             (header_len < tx_ring->tx_max_header_size))
2262                 return 0;
2263
2264         rc = rte_pktmbuf_linearize(mbuf);
2265         if (unlikely(rc))
2266                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2267
2268         return rc;
2269 }
2270
2271 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2272                                   uint16_t nb_pkts)
2273 {
2274         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2275         uint16_t next_to_use = tx_ring->next_to_use;
2276         uint16_t next_to_clean = tx_ring->next_to_clean;
2277         struct rte_mbuf *mbuf;
2278         uint16_t seg_len;
2279         unsigned int ring_size = tx_ring->ring_size;
2280         unsigned int ring_mask = ring_size - 1;
2281         struct ena_com_tx_ctx ena_tx_ctx;
2282         struct ena_tx_buffer *tx_info;
2283         struct ena_com_buf *ebuf;
2284         uint16_t rc, req_id, total_tx_descs = 0;
2285         uint16_t sent_idx = 0, empty_tx_reqs;
2286         uint16_t push_len = 0;
2287         uint16_t delta = 0;
2288         int nb_hw_desc;
2289         uint32_t total_length;
2290
2291         /* Check adapter state */
2292         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2293                 RTE_LOG(ALERT, PMD,
2294                         "Trying to xmit pkts while device is NOT running\n");
2295                 return 0;
2296         }
2297
2298         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2299         if (nb_pkts > empty_tx_reqs)
2300                 nb_pkts = empty_tx_reqs;
2301
2302         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2303                 mbuf = tx_pkts[sent_idx];
2304                 total_length = 0;
2305
2306                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2307                 if (unlikely(rc))
2308                         break;
2309
2310                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2311                 tx_info = &tx_ring->tx_buffer_info[req_id];
2312                 tx_info->mbuf = mbuf;
2313                 tx_info->num_of_bufs = 0;
2314                 ebuf = tx_info->bufs;
2315
2316                 /* Prepare TX context */
2317                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2318                 memset(&ena_tx_ctx.ena_meta, 0x0,
2319                        sizeof(struct ena_com_tx_meta));
2320                 ena_tx_ctx.ena_bufs = ebuf;
2321                 ena_tx_ctx.req_id = req_id;
2322
2323                 delta = 0;
2324                 seg_len = mbuf->data_len;
2325
2326                 if (tx_ring->tx_mem_queue_type ==
2327                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2328                         push_len = RTE_MIN(mbuf->pkt_len,
2329                                            tx_ring->tx_max_header_size);
2330                         ena_tx_ctx.header_len = push_len;
2331
2332                         if (likely(push_len <= seg_len)) {
2333                                 /* If the push header is in the single segment,
2334                                  * then just point it to the 1st mbuf data.
2335                                  */
2336                                 ena_tx_ctx.push_header =
2337                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2338                         } else {
2339                                 /* If the push header lays in the several
2340                                  * segments, copy it to the intermediate buffer.
2341                                  */
2342                                 rte_pktmbuf_read(mbuf, 0, push_len,
2343                                         tx_ring->push_buf_intermediate_buf);
2344                                 ena_tx_ctx.push_header =
2345                                         tx_ring->push_buf_intermediate_buf;
2346                                 delta = push_len - seg_len;
2347                         }
2348                 } /* there's no else as we take advantage of memset zeroing */
2349
2350                 /* Set TX offloads flags, if applicable */
2351                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2352
2353                 if (unlikely(mbuf->ol_flags &
2354                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2355                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2356
2357                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2358
2359                 /* Process first segment taking into
2360                  * consideration pushed header
2361                  */
2362                 if (seg_len > push_len) {
2363                         ebuf->paddr = mbuf->buf_iova +
2364                                       mbuf->data_off +
2365                                       push_len;
2366                         ebuf->len = seg_len - push_len;
2367                         ebuf++;
2368                         tx_info->num_of_bufs++;
2369                 }
2370                 total_length += mbuf->data_len;
2371
2372                 while ((mbuf = mbuf->next) != NULL) {
2373                         seg_len = mbuf->data_len;
2374
2375                         /* Skip mbufs if whole data is pushed as a header */
2376                         if (unlikely(delta > seg_len)) {
2377                                 delta -= seg_len;
2378                                 continue;
2379                         }
2380
2381                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2382                         ebuf->len = seg_len - delta;
2383                         total_length += ebuf->len;
2384                         ebuf++;
2385                         tx_info->num_of_bufs++;
2386
2387                         delta = 0;
2388                 }
2389
2390                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2391
2392                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2393                                                &ena_tx_ctx)) {
2394                         RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2395                                 " achieved, writing doorbell to send burst\n",
2396                                 tx_ring->id);
2397                         rte_wmb();
2398                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2399                 }
2400
2401                 /* prepare the packet's descriptors to dma engine */
2402                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2403                                         &ena_tx_ctx, &nb_hw_desc);
2404                 if (unlikely(rc))
2405                         break;
2406
2407                 tx_info->tx_descs = nb_hw_desc;
2408
2409                 next_to_use++;
2410                 tx_ring->tx_stats.cnt += tx_info->num_of_bufs;
2411                 tx_ring->tx_stats.bytes += total_length;
2412         }
2413
2414         /* If there are ready packets to be xmitted... */
2415         if (sent_idx > 0) {
2416                 /* ...let HW do its best :-) */
2417                 rte_wmb();
2418                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2419                 tx_ring->tx_stats.doorbells++;
2420                 tx_ring->next_to_use = next_to_use;
2421         }
2422
2423         /* Clear complete packets  */
2424         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2425                 rc = validate_tx_req_id(tx_ring, req_id);
2426                 if (rc)
2427                         break;
2428
2429                 /* Get Tx info & store how many descs were processed  */
2430                 tx_info = &tx_ring->tx_buffer_info[req_id];
2431                 total_tx_descs += tx_info->tx_descs;
2432
2433                 /* Free whole mbuf chain  */
2434                 mbuf = tx_info->mbuf;
2435                 rte_pktmbuf_free(mbuf);
2436                 tx_info->mbuf = NULL;
2437
2438                 /* Put back descriptor to the ring for reuse */
2439                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2440                 next_to_clean++;
2441
2442                 /* If too many descs to clean, leave it for another run */
2443                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2444                         break;
2445         }
2446
2447         if (total_tx_descs > 0) {
2448                 /* acknowledge completion of sent packets */
2449                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2450                 tx_ring->next_to_clean = next_to_clean;
2451         }
2452
2453         return sent_idx;
2454 }
2455
2456 /*********************************************************************
2457  *  PMD configuration
2458  *********************************************************************/
2459 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2460         struct rte_pci_device *pci_dev)
2461 {
2462         return rte_eth_dev_pci_generic_probe(pci_dev,
2463                 sizeof(struct ena_adapter), eth_ena_dev_init);
2464 }
2465
2466 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2467 {
2468         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2469 }
2470
2471 static struct rte_pci_driver rte_ena_pmd = {
2472         .id_table = pci_id_ena_map,
2473         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2474                      RTE_PCI_DRV_WC_ACTIVATE,
2475         .probe = eth_ena_pci_probe,
2476         .remove = eth_ena_pci_remove,
2477 };
2478
2479 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2480 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2481 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2482
2483 RTE_INIT(ena_init_log)
2484 {
2485         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2486         if (ena_logtype_init >= 0)
2487                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2488         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2489         if (ena_logtype_driver >= 0)
2490                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2491 }
2492
2493 /******************************************************************************
2494  ******************************** AENQ Handlers *******************************
2495  *****************************************************************************/
2496 static void ena_update_on_link_change(void *adapter_data,
2497                                       struct ena_admin_aenq_entry *aenq_e)
2498 {
2499         struct rte_eth_dev *eth_dev;
2500         struct ena_adapter *adapter;
2501         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2502         uint32_t status;
2503
2504         adapter = (struct ena_adapter *)adapter_data;
2505         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2506         eth_dev = adapter->rte_dev;
2507
2508         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2509         adapter->link_status = status;
2510
2511         ena_link_update(eth_dev, 0);
2512         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2513 }
2514
2515 static void ena_notification(void *data,
2516                              struct ena_admin_aenq_entry *aenq_e)
2517 {
2518         struct ena_adapter *adapter = (struct ena_adapter *)data;
2519         struct ena_admin_ena_hw_hints *hints;
2520
2521         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2522                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2523                         aenq_e->aenq_common_desc.group,
2524                         ENA_ADMIN_NOTIFICATION);
2525
2526         switch (aenq_e->aenq_common_desc.syndrom) {
2527         case ENA_ADMIN_UPDATE_HINTS:
2528                 hints = (struct ena_admin_ena_hw_hints *)
2529                         (&aenq_e->inline_data_w4);
2530                 ena_update_hints(adapter, hints);
2531                 break;
2532         default:
2533                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2534                         aenq_e->aenq_common_desc.syndrom);
2535         }
2536 }
2537
2538 static void ena_keep_alive(void *adapter_data,
2539                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2540 {
2541         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2542
2543         adapter->timestamp_wd = rte_get_timer_cycles();
2544 }
2545
2546 /**
2547  * This handler will called for unknown event group or unimplemented handlers
2548  **/
2549 static void unimplemented_aenq_handler(__rte_unused void *data,
2550                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2551 {
2552         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2553                           "unimplemented handler\n");
2554 }
2555
2556 static struct ena_aenq_handlers aenq_handlers = {
2557         .handlers = {
2558                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2559                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2560                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2561         },
2562         .unimplemented_handler = unimplemented_aenq_handler
2563 };