drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    0
  58 #define DRV_MODULE_VER_SUBMINOR 0
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 enum ethtool_stringset {
  89         ETH_SS_TEST             = 0,
  90         ETH_SS_STATS,
  91 };
  92
  93 struct ena_stats {
  94         char name[ETH_GSTRING_LEN];
  95         int stat_offset;
  96 };
  97
  98 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
  99         .name = #stat, \
 100         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 101 }
 102
 103 #define ENA_STAT_ENTRY(stat, stat_type) { \
 104         .name = #stat, \
 105         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 106 }
 107
 108 #define ENA_STAT_RX_ENTRY(stat) \
 109         ENA_STAT_ENTRY(stat, rx)
 110
 111 #define ENA_STAT_TX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, tx)
 113
 114 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, dev)
 116
 117 static const struct ena_stats ena_stats_global_strings[] = {
 118         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 119         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 120         ENA_STAT_GLOBAL_ENTRY(io_resume),
 121         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 122         ENA_STAT_GLOBAL_ENTRY(interface_up),
 123         ENA_STAT_GLOBAL_ENTRY(interface_down),
 124         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 125 };
 126
 127 static const struct ena_stats ena_stats_tx_strings[] = {
 128         ENA_STAT_TX_ENTRY(cnt),
 129         ENA_STAT_TX_ENTRY(bytes),
 130         ENA_STAT_TX_ENTRY(queue_stop),
 131         ENA_STAT_TX_ENTRY(queue_wakeup),
 132         ENA_STAT_TX_ENTRY(dma_mapping_err),
 133         ENA_STAT_TX_ENTRY(linearize),
 134         ENA_STAT_TX_ENTRY(linearize_failed),
 135         ENA_STAT_TX_ENTRY(tx_poll),
 136         ENA_STAT_TX_ENTRY(doorbells),
 137         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 138         ENA_STAT_TX_ENTRY(missing_tx_comp),
 139         ENA_STAT_TX_ENTRY(bad_req_id),
 140 };
 141
 142 static const struct ena_stats ena_stats_rx_strings[] = {
 143         ENA_STAT_RX_ENTRY(cnt),
 144         ENA_STAT_RX_ENTRY(bytes),
 145         ENA_STAT_RX_ENTRY(refil_partial),
 146         ENA_STAT_RX_ENTRY(bad_csum),
 147         ENA_STAT_RX_ENTRY(page_alloc_fail),
 148         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 149         ENA_STAT_RX_ENTRY(dma_mapping_err),
 150         ENA_STAT_RX_ENTRY(bad_desc_num),
 151         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 152 };
 153
 154 static const struct ena_stats ena_stats_ena_com_strings[] = {
 155         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 156         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 157         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 158         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 159         ENA_STAT_ENA_COM_ENTRY(no_completion),
 160 };
 161
 162 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 163 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 164 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 165 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 166
 167 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 168                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 169                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 170                         DEV_TX_OFFLOAD_TCP_TSO)
 171 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 172                        PKT_TX_IP_CKSUM |\
 173                        PKT_TX_TCP_SEG)
 174
 175 /** Vendor ID used by Amazon devices */
 176 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 177 /** Amazon devices */
 178 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 179 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 180
 181 #define ENA_TX_OFFLOAD_MASK     (\
 182         PKT_TX_L4_MASK |         \
 183         PKT_TX_IP_CKSUM |        \
 184         PKT_TX_TCP_SEG)
 185
 186 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 187         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 188
 189 int ena_logtype_init;
 190 int ena_logtype_driver;
 191
 192 static const struct rte_pci_id pci_id_ena_map[] = {
 193         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 194         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 195         { .device_id = 0 },
 196 };
 197
 198 static int ena_device_init(struct ena_com_dev *ena_dev,
 199                            struct ena_com_dev_get_features_ctx *get_feat_ctx);
 200 static int ena_dev_configure(struct rte_eth_dev *dev);
 201 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 202                                   uint16_t nb_pkts);
 203 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 204                 uint16_t nb_pkts);
 205 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 206                               uint16_t nb_desc, unsigned int socket_id,
 207                               const struct rte_eth_txconf *tx_conf);
 208 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 209                               uint16_t nb_desc, unsigned int socket_id,
 210                               const struct rte_eth_rxconf *rx_conf,
 211                               struct rte_mempool *mp);
 212 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 213                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 214 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 215 static void ena_init_rings(struct ena_adapter *adapter);
 216 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 217 static int ena_start(struct rte_eth_dev *dev);
 218 static void ena_close(struct rte_eth_dev *dev);
 219 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 220 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 221 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 222 static void ena_rx_queue_release(void *queue);
 223 static void ena_tx_queue_release(void *queue);
 224 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 225 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 226 static int ena_link_update(struct rte_eth_dev *dev,
 227                            int wait_to_complete);
 228 static int ena_queue_restart(struct ena_ring *ring);
 229 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 230                                  enum ena_ring_type ring_type);
 231 static void ena_stats_restart(struct rte_eth_dev *dev);
 232 static void ena_infos_get(struct rte_eth_dev *dev,
 233                           struct rte_eth_dev_info *dev_info);
 234 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 235                                struct rte_eth_rss_reta_entry64 *reta_conf,
 236                                uint16_t reta_size);
 237 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 238                               struct rte_eth_rss_reta_entry64 *reta_conf,
 239                               uint16_t reta_size);
 240 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 241 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
 242                                               uint64_t offloads);
 243 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter,
 244                                               uint64_t offloads);
 245
 246 static const struct eth_dev_ops ena_dev_ops = {
 247         .dev_configure        = ena_dev_configure,
 248         .dev_infos_get        = ena_infos_get,
 249         .rx_queue_setup       = ena_rx_queue_setup,
 250         .tx_queue_setup       = ena_tx_queue_setup,
 251         .dev_start            = ena_start,
 252         .link_update          = ena_link_update,
 253         .stats_get            = ena_stats_get,
 254         .mtu_set              = ena_mtu_set,
 255         .rx_queue_release     = ena_rx_queue_release,
 256         .tx_queue_release     = ena_tx_queue_release,
 257         .dev_close            = ena_close,
 258         .reta_update          = ena_rss_reta_update,
 259         .reta_query           = ena_rss_reta_query,
 260 };
 261
 262 #define NUMA_NO_NODE    SOCKET_ID_ANY
 263
 264 static inline int ena_cpu_to_node(int cpu)
 265 {
 266         struct rte_config *config = rte_eal_get_configuration();
 267         struct rte_fbarray *arr = &config->mem_config->memzones;
 268         const struct rte_memzone *mz;
 269
 270         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 271                 return NUMA_NO_NODE;
 272
 273         mz = rte_fbarray_get(arr, cpu);
 274
 275         return mz->socket_id;
 276 }
 277
 278 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 279                                        struct ena_com_rx_ctx *ena_rx_ctx)
 280 {
 281         uint64_t ol_flags = 0;
 282         uint32_t packet_type = 0;
 283
 284         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 285                 packet_type |= RTE_PTYPE_L4_TCP;
 286         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 287                 packet_type |= RTE_PTYPE_L4_UDP;
 288
 289         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 290                 packet_type |= RTE_PTYPE_L3_IPV4;
 291         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 292                 packet_type |= RTE_PTYPE_L3_IPV6;
 293
 294         if (unlikely(ena_rx_ctx->l4_csum_err))
 295                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 296         if (unlikely(ena_rx_ctx->l3_csum_err))
 297                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 298
 299         mbuf->ol_flags = ol_flags;
 300         mbuf->packet_type = packet_type;
 301 }
 302
 303 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 304                                        struct ena_com_tx_ctx *ena_tx_ctx,
 305                                        uint64_t queue_offloads)
 306 {
 307         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 308
 309         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 310             (queue_offloads & QUEUE_OFFLOADS)) {
 311                 /* check if TSO is required */
 312                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 313                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 314                         ena_tx_ctx->tso_enable = true;
 315
 316                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 317                 }
 318
 319                 /* check if L3 checksum is needed */
 320                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 321                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 322                         ena_tx_ctx->l3_csum_enable = true;
 323
 324                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 325                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 326                 } else {
 327                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 328
 329                         /* set don't fragment (DF) flag */
 330                         if (mbuf->packet_type &
 331                                 (RTE_PTYPE_L4_NONFRAG
 332                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 333                                 ena_tx_ctx->df = true;
 334                 }
 335
 336                 /* check if L4 checksum is needed */
 337                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 339                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 340                         ena_tx_ctx->l4_csum_enable = true;
 341                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 342                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 343                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 344                         ena_tx_ctx->l4_csum_enable = true;
 345                 } else {
 346                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 347                         ena_tx_ctx->l4_csum_enable = false;
 348                 }
 349
 350                 ena_meta->mss = mbuf->tso_segsz;
 351                 ena_meta->l3_hdr_len = mbuf->l3_len;
 352                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 353                 /* this param needed only for TSO */
 354                 ena_meta->l3_outer_hdr_len = 0;
 355                 ena_meta->l3_outer_hdr_offset = 0;
 356
 357                 ena_tx_ctx->meta_valid = true;
 358         } else {
 359                 ena_tx_ctx->meta_valid = false;
 360         }
 361 }
 362
 363 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 364 {
 365         struct ena_admin_host_info *host_info;
 366         int rc;
 367
 368         /* Allocate only the host info */
 369         rc = ena_com_allocate_host_info(ena_dev);
 370         if (rc) {
 371                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 372                 return;
 373         }
 374
 375         host_info = ena_dev->host_attr.host_info;
 376
 377         host_info->os_type = ENA_ADMIN_OS_DPDK;
 378         host_info->kernel_ver = RTE_VERSION;
 379         snprintf((char *)host_info->kernel_ver_str,
 380                  sizeof(host_info->kernel_ver_str),
 381                  "%s", rte_version());
 382         host_info->os_dist = RTE_VERSION;
 383         snprintf((char *)host_info->os_dist_str,
 384                  sizeof(host_info->os_dist_str),
 385                  "%s", rte_version());
 386         host_info->driver_version =
 387                 (DRV_MODULE_VER_MAJOR) |
 388                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 389                 (DRV_MODULE_VER_SUBMINOR <<
 390                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 391
 392         rc = ena_com_set_host_attributes(ena_dev);
 393         if (rc) {
 394                 RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 395                 if (rc != -EPERM)
 396                         goto err;
 397         }
 398
 399         return;
 400
 401 err:
 402         ena_com_delete_host_info(ena_dev);
 403 }
 404
 405 static int
 406 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 407 {
 408         if (sset != ETH_SS_STATS)
 409                 return -EOPNOTSUPP;
 410
 411          /* Workaround for clang:
 412          * touch internal structures to prevent
 413          * compiler error
 414          */
 415         ENA_TOUCH(ena_stats_global_strings);
 416         ENA_TOUCH(ena_stats_tx_strings);
 417         ENA_TOUCH(ena_stats_rx_strings);
 418         ENA_TOUCH(ena_stats_ena_com_strings);
 419
 420         return  dev->data->nb_tx_queues *
 421                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 422                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 423 }
 424
 425 static void ena_config_debug_area(struct ena_adapter *adapter)
 426 {
 427         u32 debug_area_size;
 428         int rc, ss_count;
 429
 430         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 431         if (ss_count <= 0) {
 432                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 433                 return;
 434         }
 435
 436         /* allocate 32 bytes for each string and 64bit for the value */
 437         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 438
 439         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 440         if (rc) {
 441                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 442                 return;
 443         }
 444
 445         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 446         if (rc) {
 447                 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 448                 if (rc != -EPERM)
 449                         goto err;
 450         }
 451
 452         return;
 453 err:
 454         ena_com_delete_debug_area(&adapter->ena_dev);
 455 }
 456
 457 static void ena_close(struct rte_eth_dev *dev)
 458 {
 459         struct ena_adapter *adapter =
 460                 (struct ena_adapter *)(dev->data->dev_private);
 461
 462         adapter->state = ENA_ADAPTER_STATE_STOPPED;
 463
 464         ena_rx_queue_release_all(dev);
 465         ena_tx_queue_release_all(dev);
 466 }
 467
 468 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 469                                struct rte_eth_rss_reta_entry64 *reta_conf,
 470                                uint16_t reta_size)
 471 {
 472         struct ena_adapter *adapter =
 473                 (struct ena_adapter *)(dev->data->dev_private);
 474         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 475         int ret, i;
 476         u16 entry_value;
 477         int conf_idx;
 478         int idx;
 479
 480         if ((reta_size == 0) || (reta_conf == NULL))
 481                 return -EINVAL;
 482
 483         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 484                 RTE_LOG(WARNING, PMD,
 485                         "indirection table %d is bigger than supported (%d)\n",
 486                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 487                 ret = -EINVAL;
 488                 goto err;
 489         }
 490
 491         for (i = 0 ; i < reta_size ; i++) {
 492                 /* each reta_conf is for 64 entries.
 493                  * to support 128 we use 2 conf of 64
 494                  */
 495                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 496                 idx = i % RTE_RETA_GROUP_SIZE;
 497                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 498                         entry_value =
 499                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 500                         ret = ena_com_indirect_table_fill_entry(ena_dev,
 501                                                                 i,
 502                                                                 entry_value);
 503                         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 504                                 RTE_LOG(ERR, PMD,
 505                                         "Cannot fill indirect table\n");
 506                                 ret = -ENOTSUP;
 507                                 goto err;
 508                         }
 509                 }
 510         }
 511
 512         ret = ena_com_indirect_table_set(ena_dev);
 513         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 514                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 515                 ret = -ENOTSUP;
 516                 goto err;
 517         }
 518
 519         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 520                 __func__, reta_size, adapter->rte_dev->data->port_id);
 521 err:
 522         return ret;
 523 }
 524
 525 /* Query redirection table. */
 526 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 527                               struct rte_eth_rss_reta_entry64 *reta_conf,
 528                               uint16_t reta_size)
 529 {
 530         struct ena_adapter *adapter =
 531                 (struct ena_adapter *)(dev->data->dev_private);
 532         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 533         int ret;
 534         int i;
 535         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 536         int reta_conf_idx;
 537         int reta_idx;
 538
 539         if (reta_size == 0 || reta_conf == NULL ||
 540             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 541                 return -EINVAL;
 542
 543         ret = ena_com_indirect_table_get(ena_dev, indirect_table);
 544         if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
 545                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 546                 ret = -ENOTSUP;
 547                 goto err;
 548         }
 549
 550         for (i = 0 ; i < reta_size ; i++) {
 551                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 552                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 553                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 554                         reta_conf[reta_conf_idx].reta[reta_idx] =
 555                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 556         }
 557 err:
 558         return ret;
 559 }
 560
 561 static int ena_rss_init_default(struct ena_adapter *adapter)
 562 {
 563         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 564         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 565         int rc, i;
 566         u32 val;
 567
 568         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 569         if (unlikely(rc)) {
 570                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 571                 goto err_rss_init;
 572         }
 573
 574         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 575                 val = i % nb_rx_queues;
 576                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 577                                                        ENA_IO_RXQ_IDX(val));
 578                 if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 579                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 580                         goto err_fill_indir;
 581                 }
 582         }
 583
 584         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 585                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 586         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 587                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 588                 goto err_fill_indir;
 589         }
 590
 591         rc = ena_com_set_default_hash_ctrl(ena_dev);
 592         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 593                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 594                 goto err_fill_indir;
 595         }
 596
 597         rc = ena_com_indirect_table_set(ena_dev);
 598         if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
 599                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 600                 goto err_fill_indir;
 601         }
 602         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 603                 adapter->rte_dev->data->port_id);
 604
 605         return 0;
 606
 607 err_fill_indir:
 608         ena_com_rss_destroy(ena_dev);
 609 err_rss_init:
 610
 611         return rc;
 612 }
 613
 614 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 615 {
 616         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 617         int nb_queues = dev->data->nb_rx_queues;
 618         int i;
 619
 620         for (i = 0; i < nb_queues; i++)
 621                 ena_rx_queue_release(queues[i]);
 622 }
 623
 624 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 625 {
 626         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 627         int nb_queues = dev->data->nb_tx_queues;
 628         int i;
 629
 630         for (i = 0; i < nb_queues; i++)
 631                 ena_tx_queue_release(queues[i]);
 632 }
 633
 634 static void ena_rx_queue_release(void *queue)
 635 {
 636         struct ena_ring *ring = (struct ena_ring *)queue;
 637         struct ena_adapter *adapter = ring->adapter;
 638         int ena_qid;
 639
 640         ena_assert_msg(ring->configured,
 641                        "API violation - releasing not configured queue");
 642         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 643                        "API violation");
 644
 645         /* Destroy HW queue */
 646         ena_qid = ENA_IO_RXQ_IDX(ring->id);
 647         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 648
 649         /* Free all bufs */
 650         ena_rx_queue_release_bufs(ring);
 651
 652         /* Free ring resources */
 653         if (ring->rx_buffer_info)
 654                 rte_free(ring->rx_buffer_info);
 655         ring->rx_buffer_info = NULL;
 656
 657         ring->configured = 0;
 658
 659         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 660                 ring->port_id, ring->id);
 661 }
 662
 663 static void ena_tx_queue_release(void *queue)
 664 {
 665         struct ena_ring *ring = (struct ena_ring *)queue;
 666         struct ena_adapter *adapter = ring->adapter;
 667         int ena_qid;
 668
 669         ena_assert_msg(ring->configured,
 670                        "API violation. Releasing not configured queue");
 671         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 672                        "API violation");
 673
 674         /* Destroy HW queue */
 675         ena_qid = ENA_IO_TXQ_IDX(ring->id);
 676         ena_com_destroy_io_queue(&adapter->ena_dev, ena_qid);
 677
 678         /* Free all bufs */
 679         ena_tx_queue_release_bufs(ring);
 680
 681         /* Free ring resources */
 682         if (ring->tx_buffer_info)
 683                 rte_free(ring->tx_buffer_info);
 684
 685         if (ring->empty_tx_reqs)
 686                 rte_free(ring->empty_tx_reqs);
 687
 688         ring->empty_tx_reqs = NULL;
 689         ring->tx_buffer_info = NULL;
 690
 691         ring->configured = 0;
 692
 693         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 694                 ring->port_id, ring->id);
 695 }
 696
 697 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 698 {
 699         unsigned int ring_mask = ring->ring_size - 1;
 700
 701         while (ring->next_to_clean != ring->next_to_use) {
 702                 struct rte_mbuf *m =
 703                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 704
 705                 if (m)
 706                         rte_mbuf_raw_free(m);
 707
 708                 ring->next_to_clean++;
 709         }
 710 }
 711
 712 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 713 {
 714         unsigned int i;
 715
 716         for (i = 0; i < ring->ring_size; ++i) {
 717                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 718
 719                 if (tx_buf->mbuf)
 720                         rte_pktmbuf_free(tx_buf->mbuf);
 721
 722                 ring->next_to_clean++;
 723         }
 724 }
 725
 726 static int ena_link_update(struct rte_eth_dev *dev,
 727                            __rte_unused int wait_to_complete)
 728 {
 729         struct rte_eth_link *link = &dev->data->dev_link;
 730
 731         link->link_status = 1;
 732         link->link_speed = ETH_SPEED_NUM_10G;
 733         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 734
 735         return 0;
 736 }
 737
 738 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 739                                  enum ena_ring_type ring_type)
 740 {
 741         struct ena_adapter *adapter =
 742                 (struct ena_adapter *)(dev->data->dev_private);
 743         struct ena_ring *queues = NULL;
 744         int i = 0;
 745         int rc = 0;
 746
 747         queues = (ring_type == ENA_RING_TYPE_RX) ?
 748                 adapter->rx_ring : adapter->tx_ring;
 749
 750         for (i = 0; i < adapter->num_queues; i++) {
 751                 if (queues[i].configured) {
 752                         if (ring_type == ENA_RING_TYPE_RX) {
 753                                 ena_assert_msg(
 754                                         dev->data->rx_queues[i] == &queues[i],
 755                                         "Inconsistent state of rx queues\n");
 756                         } else {
 757                                 ena_assert_msg(
 758                                         dev->data->tx_queues[i] == &queues[i],
 759                                         "Inconsistent state of tx queues\n");
 760                         }
 761
 762                         rc = ena_queue_restart(&queues[i]);
 763
 764                         if (rc) {
 765                                 PMD_INIT_LOG(ERR,
 766                                              "failed to restart queue %d type(%d)",
 767                                              i, ring_type);
 768                                 return -1;
 769                         }
 770                 }
 771         }
 772
 773         return 0;
 774 }
 775
 776 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 777 {
 778         uint32_t max_frame_len = adapter->max_mtu;
 779
 780         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 781             DEV_RX_OFFLOAD_JUMBO_FRAME)
 782                 max_frame_len =
 783                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 784
 785         return max_frame_len;
 786 }
 787
 788 static int ena_check_valid_conf(struct ena_adapter *adapter)
 789 {
 790         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 791
 792         if (max_frame_len > adapter->max_mtu) {
 793                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d", max_frame_len);
 794                 return -1;
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int
 801 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 802                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 803 {
 804         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 805
 806         queue_size = RTE_MIN(queue_size,
 807                              get_feat_ctx->max_queues.max_cq_depth);
 808         queue_size = RTE_MIN(queue_size,
 809                              get_feat_ctx->max_queues.max_sq_depth);
 810
 811         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 812                 queue_size = RTE_MIN(queue_size,
 813                                      get_feat_ctx->max_queues.max_llq_depth);
 814
 815         /* Round down to power of 2 */
 816         if (!rte_is_power_of_2(queue_size))
 817                 queue_size = rte_align32pow2(queue_size >> 1);
 818
 819         if (queue_size == 0) {
 820                 PMD_INIT_LOG(ERR, "Invalid queue size");
 821                 return -EFAULT;
 822         }
 823
 824         return queue_size;
 825 }
 826
 827 static void ena_stats_restart(struct rte_eth_dev *dev)
 828 {
 829         struct ena_adapter *adapter =
 830                 (struct ena_adapter *)(dev->data->dev_private);
 831
 832         rte_atomic64_init(&adapter->drv_stats->ierrors);
 833         rte_atomic64_init(&adapter->drv_stats->oerrors);
 834         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 835 }
 836
 837 static int ena_stats_get(struct rte_eth_dev *dev,
 838                           struct rte_eth_stats *stats)
 839 {
 840         struct ena_admin_basic_stats ena_stats;
 841         struct ena_adapter *adapter =
 842                 (struct ena_adapter *)(dev->data->dev_private);
 843         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 844         int rc;
 845
 846         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 847                 return -ENOTSUP;
 848
 849         memset(&ena_stats, 0, sizeof(ena_stats));
 850         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 851         if (unlikely(rc)) {
 852                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 853                 return rc;
 854         }
 855
 856         /* Set of basic statistics from ENA */
 857         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 858                                           ena_stats.rx_pkts_low);
 859         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 860                                           ena_stats.tx_pkts_low);
 861         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 862                                         ena_stats.rx_bytes_low);
 863         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 864                                         ena_stats.tx_bytes_low);
 865         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
 866                                          ena_stats.rx_drops_low);
 867
 868         /* Driver related stats */
 869         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
 870         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
 871         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
 872         return 0;
 873 }
 874
 875 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 876 {
 877         struct ena_adapter *adapter;
 878         struct ena_com_dev *ena_dev;
 879         int rc = 0;
 880
 881         ena_assert_msg(dev->data != NULL, "Uninitialized device");
 882         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
 883         adapter = (struct ena_adapter *)(dev->data->dev_private);
 884
 885         ena_dev = &adapter->ena_dev;
 886         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
 887
 888         if (mtu > ena_get_mtu_conf(adapter)) {
 889                 RTE_LOG(ERR, PMD,
 890                         "Given MTU (%d) exceeds maximum MTU supported (%d)\n",
 891                         mtu, ena_get_mtu_conf(adapter));
 892                 rc = -EINVAL;
 893                 goto err;
 894         }
 895
 896         rc = ena_com_set_dev_mtu(ena_dev, mtu);
 897         if (rc)
 898                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
 899         else
 900                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
 901
 902 err:
 903         return rc;
 904 }
 905
 906 static int ena_start(struct rte_eth_dev *dev)
 907 {
 908         struct ena_adapter *adapter =
 909                 (struct ena_adapter *)(dev->data->dev_private);
 910         int rc = 0;
 911
 912         if (!(adapter->state == ENA_ADAPTER_STATE_CONFIG ||
 913               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
 914                 PMD_INIT_LOG(ERR, "API violation");
 915                 return -1;
 916         }
 917
 918         rc = ena_check_valid_conf(adapter);
 919         if (rc)
 920                 return rc;
 921
 922         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
 923         if (rc)
 924                 return rc;
 925
 926         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
 927         if (rc)
 928                 return rc;
 929
 930         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
 931             ETH_MQ_RX_RSS_FLAG) {
 932                 rc = ena_rss_init_default(adapter);
 933                 if (rc)
 934                         return rc;
 935         }
 936
 937         ena_stats_restart(dev);
 938
 939         adapter->state = ENA_ADAPTER_STATE_RUNNING;
 940
 941         return 0;
 942 }
 943
 944 static int ena_queue_restart(struct ena_ring *ring)
 945 {
 946         int rc, bufs_num;
 947
 948         ena_assert_msg(ring->configured == 1,
 949                        "Trying to restart unconfigured queue\n");
 950
 951         ring->next_to_clean = 0;
 952         ring->next_to_use = 0;
 953
 954         if (ring->type == ENA_RING_TYPE_TX)
 955                 return 0;
 956
 957         bufs_num = ring->ring_size - 1;
 958         rc = ena_populate_rx_queue(ring, bufs_num);
 959         if (rc != bufs_num) {
 960                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
 961                 return (-1);
 962         }
 963
 964         return 0;
 965 }
 966
 967 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
 968                               uint16_t queue_idx,
 969                               uint16_t nb_desc,
 970                               __rte_unused unsigned int socket_id,
 971                               const struct rte_eth_txconf *tx_conf)
 972 {
 973         struct ena_com_create_io_ctx ctx =
 974                 /* policy set to _HOST just to satisfy icc compiler */
 975                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
 976                   ENA_COM_IO_QUEUE_DIRECTION_TX, 0, 0, 0, 0 };
 977         struct ena_ring *txq = NULL;
 978         struct ena_adapter *adapter =
 979                 (struct ena_adapter *)(dev->data->dev_private);
 980         unsigned int i;
 981         int ena_qid;
 982         int rc;
 983         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 984
 985         txq = &adapter->tx_ring[queue_idx];
 986
 987         if (txq->configured) {
 988                 RTE_LOG(CRIT, PMD,
 989                         "API violation. Queue %d is already configured\n",
 990                         queue_idx);
 991                 return -1;
 992         }
 993
 994         if (!rte_is_power_of_2(nb_desc)) {
 995                 RTE_LOG(ERR, PMD,
 996                         "Unsupported size of RX queue: %d is not a power of 2.",
 997                         nb_desc);
 998                 return -EINVAL;
 999         }
1000
1001         if (nb_desc > adapter->tx_ring_size) {
1002                 RTE_LOG(ERR, PMD,
1003                         "Unsupported size of TX queue (max size: %d)\n",
1004                         adapter->tx_ring_size);
1005                 return -EINVAL;
1006         }
1007
1008         if (tx_conf->txq_flags == ETH_TXQ_FLAGS_IGNORE &&
1009             !ena_are_tx_queue_offloads_allowed(adapter, tx_conf->offloads)) {
1010                 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1011                 return -EINVAL;
1012         }
1013
1014         ena_qid = ENA_IO_TXQ_IDX(queue_idx);
1015
1016         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1017         ctx.qid = ena_qid;
1018         ctx.msix_vector = -1; /* admin interrupts not used */
1019         ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1020         ctx.queue_size = adapter->tx_ring_size;
1021         ctx.numa_node = ena_cpu_to_node(queue_idx);
1022
1023         rc = ena_com_create_io_queue(ena_dev, &ctx);
1024         if (rc) {
1025                 RTE_LOG(ERR, PMD,
1026                         "failed to create io TX queue #%d (qid:%d) rc: %d\n",
1027                         queue_idx, ena_qid, rc);
1028         }
1029         txq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1030         txq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1031
1032         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1033                                      &txq->ena_com_io_sq,
1034                                      &txq->ena_com_io_cq);
1035         if (rc) {
1036                 RTE_LOG(ERR, PMD,
1037                         "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1038                         queue_idx, rc);
1039                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1040                 goto err;
1041         }
1042
1043         txq->port_id = dev->data->port_id;
1044         txq->next_to_clean = 0;
1045         txq->next_to_use = 0;
1046         txq->ring_size = nb_desc;
1047
1048         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1049                                           sizeof(struct ena_tx_buffer) *
1050                                           txq->ring_size,
1051                                           RTE_CACHE_LINE_SIZE);
1052         if (!txq->tx_buffer_info) {
1053                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1054                 return -ENOMEM;
1055         }
1056
1057         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1058                                          sizeof(u16) * txq->ring_size,
1059                                          RTE_CACHE_LINE_SIZE);
1060         if (!txq->empty_tx_reqs) {
1061                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1062                 rte_free(txq->tx_buffer_info);
1063                 return -ENOMEM;
1064         }
1065         for (i = 0; i < txq->ring_size; i++)
1066                 txq->empty_tx_reqs[i] = i;
1067
1068         txq->offloads = tx_conf->offloads;
1069
1070         /* Store pointer to this queue in upper layer */
1071         txq->configured = 1;
1072         dev->data->tx_queues[queue_idx] = txq;
1073 err:
1074         return rc;
1075 }
1076
1077 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1078                               uint16_t queue_idx,
1079                               uint16_t nb_desc,
1080                               __rte_unused unsigned int socket_id,
1081                               const struct rte_eth_rxconf *rx_conf,
1082                               struct rte_mempool *mp)
1083 {
1084         struct ena_com_create_io_ctx ctx =
1085                 /* policy set to _HOST just to satisfy icc compiler */
1086                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1087                   ENA_COM_IO_QUEUE_DIRECTION_RX, 0, 0, 0, 0 };
1088         struct ena_adapter *adapter =
1089                 (struct ena_adapter *)(dev->data->dev_private);
1090         struct ena_ring *rxq = NULL;
1091         uint16_t ena_qid = 0;
1092         int rc = 0;
1093         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1094
1095         rxq = &adapter->rx_ring[queue_idx];
1096         if (rxq->configured) {
1097                 RTE_LOG(CRIT, PMD,
1098                         "API violation. Queue %d is already configured\n",
1099                         queue_idx);
1100                 return -1;
1101         }
1102
1103         if (!rte_is_power_of_2(nb_desc)) {
1104                 RTE_LOG(ERR, PMD,
1105                         "Unsupported size of TX queue: %d is not a power of 2.",
1106                         nb_desc);
1107                 return -EINVAL;
1108         }
1109
1110         if (nb_desc > adapter->rx_ring_size) {
1111                 RTE_LOG(ERR, PMD,
1112                         "Unsupported size of RX queue (max size: %d)\n",
1113                         adapter->rx_ring_size);
1114                 return -EINVAL;
1115         }
1116
1117         if (!ena_are_rx_queue_offloads_allowed(adapter, rx_conf->offloads)) {
1118                 RTE_LOG(ERR, PMD, "Unsupported queue offloads\n");
1119                 return -EINVAL;
1120         }
1121
1122         ena_qid = ENA_IO_RXQ_IDX(queue_idx);
1123
1124         ctx.qid = ena_qid;
1125         ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1126         ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1127         ctx.msix_vector = -1; /* admin interrupts not used */
1128         ctx.queue_size = adapter->rx_ring_size;
1129         ctx.numa_node = ena_cpu_to_node(queue_idx);
1130
1131         rc = ena_com_create_io_queue(ena_dev, &ctx);
1132         if (rc)
1133                 RTE_LOG(ERR, PMD, "failed to create io RX queue #%d rc: %d\n",
1134                         queue_idx, rc);
1135
1136         rxq->ena_com_io_cq = &ena_dev->io_cq_queues[ena_qid];
1137         rxq->ena_com_io_sq = &ena_dev->io_sq_queues[ena_qid];
1138
1139         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1140                                      &rxq->ena_com_io_sq,
1141                                      &rxq->ena_com_io_cq);
1142         if (rc) {
1143                 RTE_LOG(ERR, PMD,
1144                         "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1145                         queue_idx, rc);
1146                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1147         }
1148
1149         rxq->port_id = dev->data->port_id;
1150         rxq->next_to_clean = 0;
1151         rxq->next_to_use = 0;
1152         rxq->ring_size = nb_desc;
1153         rxq->mb_pool = mp;
1154
1155         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1156                                           sizeof(struct rte_mbuf *) * nb_desc,
1157                                           RTE_CACHE_LINE_SIZE);
1158         if (!rxq->rx_buffer_info) {
1159                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1160                 return -ENOMEM;
1161         }
1162
1163         /* Store pointer to this queue in upper layer */
1164         rxq->configured = 1;
1165         dev->data->rx_queues[queue_idx] = rxq;
1166
1167         return rc;
1168 }
1169
1170 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1171 {
1172         unsigned int i;
1173         int rc;
1174         uint16_t ring_size = rxq->ring_size;
1175         uint16_t ring_mask = ring_size - 1;
1176         uint16_t next_to_use = rxq->next_to_use;
1177         uint16_t in_use;
1178         struct rte_mbuf **mbufs = &rxq->rx_buffer_info[0];
1179
1180         if (unlikely(!count))
1181                 return 0;
1182
1183         in_use = rxq->next_to_use - rxq->next_to_clean;
1184         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1185
1186         count = RTE_MIN(count,
1187                         (uint16_t)(ring_size - (next_to_use & ring_mask)));
1188
1189         /* get resources for incoming packets */
1190         rc = rte_mempool_get_bulk(rxq->mb_pool,
1191                                   (void **)(&mbufs[next_to_use & ring_mask]),
1192                                   count);
1193         if (unlikely(rc < 0)) {
1194                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1195                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1196                 return 0;
1197         }
1198
1199         for (i = 0; i < count; i++) {
1200                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1201                 struct rte_mbuf *mbuf = mbufs[next_to_use_masked];
1202                 struct ena_com_buf ebuf;
1203
1204                 rte_prefetch0(mbufs[((next_to_use + 4) & ring_mask)]);
1205                 /* prepare physical address for DMA transaction */
1206                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1207                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1208                 /* pass resource to device */
1209                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1210                                                 &ebuf, next_to_use_masked);
1211                 if (unlikely(rc)) {
1212                         rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbuf),
1213                                              count - i);
1214                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1215                         break;
1216                 }
1217                 next_to_use++;
1218         }
1219
1220         /* When we submitted free recources to device... */
1221         if (i > 0) {
1222                 /* ...let HW know that it can fill buffers with data */
1223                 rte_wmb();
1224                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1225
1226                 rxq->next_to_use = next_to_use;
1227         }
1228
1229         return i;
1230 }
1231
1232 static int ena_device_init(struct ena_com_dev *ena_dev,
1233                            struct ena_com_dev_get_features_ctx *get_feat_ctx)
1234 {
1235         int rc;
1236         bool readless_supported;
1237
1238         /* Initialize mmio registers */
1239         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1240         if (rc) {
1241                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1242                 return rc;
1243         }
1244
1245         /* The PCIe configuration space revision id indicate if mmio reg
1246          * read is disabled.
1247          */
1248         readless_supported =
1249                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1250                                & ENA_MMIO_DISABLE_REG_READ);
1251         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1252
1253         /* reset device */
1254         rc = ena_com_dev_reset(ena_dev);
1255         if (rc) {
1256                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1257                 goto err_mmio_read_less;
1258         }
1259
1260         /* check FW version */
1261         rc = ena_com_validate_version(ena_dev);
1262         if (rc) {
1263                 RTE_LOG(ERR, PMD, "device version is too low\n");
1264                 goto err_mmio_read_less;
1265         }
1266
1267         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1268
1269         /* ENA device administration layer init */
1270         rc = ena_com_admin_init(ena_dev, NULL, true);
1271         if (rc) {
1272                 RTE_LOG(ERR, PMD,
1273                         "cannot initialize ena admin queue with device\n");
1274                 goto err_mmio_read_less;
1275         }
1276
1277         /* To enable the msix interrupts the driver needs to know the number
1278          * of queues. So the driver uses polling mode to retrieve this
1279          * information.
1280          */
1281         ena_com_set_admin_polling_mode(ena_dev, true);
1282
1283         ena_config_host_info(ena_dev);
1284
1285         /* Get Device Attributes and features */
1286         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1287         if (rc) {
1288                 RTE_LOG(ERR, PMD,
1289                         "cannot get attribute for ena device rc= %d\n", rc);
1290                 goto err_admin_init;
1291         }
1292
1293         return 0;
1294
1295 err_admin_init:
1296         ena_com_admin_destroy(ena_dev);
1297
1298 err_mmio_read_less:
1299         ena_com_mmio_reg_read_request_destroy(ena_dev);
1300
1301         return rc;
1302 }
1303
1304 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1305 {
1306         struct rte_pci_device *pci_dev;
1307         struct ena_adapter *adapter =
1308                 (struct ena_adapter *)(eth_dev->data->dev_private);
1309         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1310         struct ena_com_dev_get_features_ctx get_feat_ctx;
1311         int queue_size, rc;
1312
1313         static int adapters_found;
1314
1315         memset(adapter, 0, sizeof(struct ena_adapter));
1316         ena_dev = &adapter->ena_dev;
1317
1318         eth_dev->dev_ops = &ena_dev_ops;
1319         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1320         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1321         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1322         adapter->rte_eth_dev_data = eth_dev->data;
1323         adapter->rte_dev = eth_dev;
1324
1325         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1326                 return 0;
1327
1328         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1329         adapter->pdev = pci_dev;
1330
1331         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1332                      pci_dev->addr.domain,
1333                      pci_dev->addr.bus,
1334                      pci_dev->addr.devid,
1335                      pci_dev->addr.function);
1336
1337         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1338         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1339
1340         /* Present ENA_MEM_BAR indicates available LLQ mode.
1341          * Use corresponding policy
1342          */
1343         if (adapter->dev_mem_base)
1344                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
1345         else if (adapter->regs)
1346                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1347         else
1348                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1349                              ENA_REGS_BAR);
1350
1351         ena_dev->reg_bar = adapter->regs;
1352         ena_dev->dmadev = adapter->pdev;
1353
1354         adapter->id_number = adapters_found;
1355
1356         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1357                  adapter->id_number);
1358
1359         /* device specific initialization routine */
1360         rc = ena_device_init(ena_dev, &get_feat_ctx);
1361         if (rc) {
1362                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1363                 return -1;
1364         }
1365
1366         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1367                 if (get_feat_ctx.max_queues.max_llq_num == 0) {
1368                         PMD_INIT_LOG(ERR,
1369                                      "Trying to use LLQ but llq_num is 0.\n"
1370                                      "Fall back into regular queues.");
1371                         ena_dev->tx_mem_queue_type =
1372                                 ENA_ADMIN_PLACEMENT_POLICY_HOST;
1373                         adapter->num_queues =
1374                                 get_feat_ctx.max_queues.max_sq_num;
1375                 } else {
1376                         adapter->num_queues =
1377                                 get_feat_ctx.max_queues.max_llq_num;
1378                 }
1379         } else {
1380                 adapter->num_queues = get_feat_ctx.max_queues.max_sq_num;
1381         }
1382
1383         queue_size = ena_calc_queue_size(ena_dev, &get_feat_ctx);
1384         if ((queue_size <= 0) || (adapter->num_queues <= 0))
1385                 return -EFAULT;
1386
1387         adapter->tx_ring_size = queue_size;
1388         adapter->rx_ring_size = queue_size;
1389
1390         /* prepare ring structures */
1391         ena_init_rings(adapter);
1392
1393         ena_config_debug_area(adapter);
1394
1395         /* Set max MTU for this device */
1396         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1397
1398         /* set device support for TSO */
1399         adapter->tso4_supported = get_feat_ctx.offload.tx &
1400                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1401
1402         /* Copy MAC address and point DPDK to it */
1403         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1404         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1405                         (struct ether_addr *)adapter->mac_addr);
1406
1407         adapter->drv_stats = rte_zmalloc("adapter stats",
1408                                          sizeof(*adapter->drv_stats),
1409                                          RTE_CACHE_LINE_SIZE);
1410         if (!adapter->drv_stats) {
1411                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1412                 return -ENOMEM;
1413         }
1414
1415         adapters_found++;
1416         adapter->state = ENA_ADAPTER_STATE_INIT;
1417
1418         return 0;
1419 }
1420
1421 static int ena_dev_configure(struct rte_eth_dev *dev)
1422 {
1423         struct ena_adapter *adapter =
1424                 (struct ena_adapter *)(dev->data->dev_private);
1425         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
1426         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1427
1428         if ((tx_offloads & adapter->tx_supported_offloads) != tx_offloads) {
1429                 RTE_LOG(ERR, PMD, "Some Tx offloads are not supported "
1430                     "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1431                     tx_offloads, adapter->tx_supported_offloads);
1432                 return -ENOTSUP;
1433         }
1434
1435         if ((rx_offloads & adapter->rx_supported_offloads) != rx_offloads) {
1436                 RTE_LOG(ERR, PMD, "Some Rx offloads are not supported "
1437                     "requested 0x%" PRIx64 " supported 0x%" PRIx64 "\n",
1438                     rx_offloads, adapter->rx_supported_offloads);
1439                 return -ENOTSUP;
1440         }
1441
1442         if (!(adapter->state == ENA_ADAPTER_STATE_INIT ||
1443               adapter->state == ENA_ADAPTER_STATE_STOPPED)) {
1444                 PMD_INIT_LOG(ERR, "Illegal adapter state: %d",
1445                              adapter->state);
1446                 return -1;
1447         }
1448
1449         switch (adapter->state) {
1450         case ENA_ADAPTER_STATE_INIT:
1451         case ENA_ADAPTER_STATE_STOPPED:
1452                 adapter->state = ENA_ADAPTER_STATE_CONFIG;
1453                 break;
1454         case ENA_ADAPTER_STATE_CONFIG:
1455                 RTE_LOG(WARNING, PMD,
1456                         "Ivalid driver state while trying to configure device\n");
1457                 break;
1458         default:
1459                 break;
1460         }
1461
1462         adapter->tx_selected_offloads = tx_offloads;
1463         adapter->rx_selected_offloads = rx_offloads;
1464         return 0;
1465 }
1466
1467 static void ena_init_rings(struct ena_adapter *adapter)
1468 {
1469         int i;
1470
1471         for (i = 0; i < adapter->num_queues; i++) {
1472                 struct ena_ring *ring = &adapter->tx_ring[i];
1473
1474                 ring->configured = 0;
1475                 ring->type = ENA_RING_TYPE_TX;
1476                 ring->adapter = adapter;
1477                 ring->id = i;
1478                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1479                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1480         }
1481
1482         for (i = 0; i < adapter->num_queues; i++) {
1483                 struct ena_ring *ring = &adapter->rx_ring[i];
1484
1485                 ring->configured = 0;
1486                 ring->type = ENA_RING_TYPE_RX;
1487                 ring->adapter = adapter;
1488                 ring->id = i;
1489         }
1490 }
1491
1492 static bool ena_are_tx_queue_offloads_allowed(struct ena_adapter *adapter,
1493                                               uint64_t offloads)
1494 {
1495         uint64_t port_offloads = adapter->tx_selected_offloads;
1496
1497         /* Check if port supports all requested offloads.
1498          * True if all offloads selected for queue are set for port.
1499          */
1500         if ((offloads & port_offloads) != offloads)
1501                 return false;
1502         return true;
1503 }
1504
1505 static bool ena_are_rx_queue_offloads_allowed(struct ena_adapter *adapter,
1506                                               uint64_t offloads)
1507 {
1508         uint64_t port_offloads = adapter->rx_selected_offloads;
1509
1510         /* Check if port supports all requested offloads.
1511          * True if all offloads selected for queue are set for port.
1512          */
1513         if ((offloads & port_offloads) != offloads)
1514                 return false;
1515         return true;
1516 }
1517
1518 static void ena_infos_get(struct rte_eth_dev *dev,
1519                           struct rte_eth_dev_info *dev_info)
1520 {
1521         struct ena_adapter *adapter;
1522         struct ena_com_dev *ena_dev;
1523         struct ena_com_dev_get_features_ctx feat;
1524         uint64_t rx_feat = 0, tx_feat = 0;
1525         int rc = 0;
1526
1527         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1528         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1529         adapter = (struct ena_adapter *)(dev->data->dev_private);
1530
1531         ena_dev = &adapter->ena_dev;
1532         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1533
1534         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1535
1536         dev_info->speed_capa =
1537                         ETH_LINK_SPEED_1G   |
1538                         ETH_LINK_SPEED_2_5G |
1539                         ETH_LINK_SPEED_5G   |
1540                         ETH_LINK_SPEED_10G  |
1541                         ETH_LINK_SPEED_25G  |
1542                         ETH_LINK_SPEED_40G  |
1543                         ETH_LINK_SPEED_50G  |
1544                         ETH_LINK_SPEED_100G;
1545
1546         /* Get supported features from HW */
1547         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1548         if (unlikely(rc)) {
1549                 RTE_LOG(ERR, PMD,
1550                         "Cannot get attribute for ena device rc= %d\n", rc);
1551                 return;
1552         }
1553
1554         /* Set Tx & Rx features available for device */
1555         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1556                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1557
1558         if (feat.offload.tx &
1559             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1560                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1561                         DEV_TX_OFFLOAD_UDP_CKSUM |
1562                         DEV_TX_OFFLOAD_TCP_CKSUM;
1563
1564         if (feat.offload.rx_supported &
1565             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1566                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1567                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1568                         DEV_RX_OFFLOAD_TCP_CKSUM;
1569
1570         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1571
1572         /* Inform framework about available features */
1573         dev_info->rx_offload_capa = rx_feat;
1574         dev_info->rx_queue_offload_capa = rx_feat;
1575         dev_info->tx_offload_capa = tx_feat;
1576         dev_info->tx_queue_offload_capa = tx_feat;
1577
1578         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1579         dev_info->max_rx_pktlen  = adapter->max_mtu;
1580         dev_info->max_mac_addrs = 1;
1581
1582         dev_info->max_rx_queues = adapter->num_queues;
1583         dev_info->max_tx_queues = adapter->num_queues;
1584         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1585
1586         adapter->tx_supported_offloads = tx_feat;
1587         adapter->rx_supported_offloads = rx_feat;
1588 }
1589
1590 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1591                                   uint16_t nb_pkts)
1592 {
1593         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1594         unsigned int ring_size = rx_ring->ring_size;
1595         unsigned int ring_mask = ring_size - 1;
1596         uint16_t next_to_clean = rx_ring->next_to_clean;
1597         uint16_t desc_in_use = 0;
1598         unsigned int recv_idx = 0;
1599         struct rte_mbuf *mbuf = NULL;
1600         struct rte_mbuf *mbuf_head = NULL;
1601         struct rte_mbuf *mbuf_prev = NULL;
1602         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1603         unsigned int completed;
1604
1605         struct ena_com_rx_ctx ena_rx_ctx;
1606         int rc = 0;
1607
1608         /* Check adapter state */
1609         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1610                 RTE_LOG(ALERT, PMD,
1611                         "Trying to receive pkts while device is NOT running\n");
1612                 return 0;
1613         }
1614
1615         desc_in_use = rx_ring->next_to_use - next_to_clean;
1616         if (unlikely(nb_pkts > desc_in_use))
1617                 nb_pkts = desc_in_use;
1618
1619         for (completed = 0; completed < nb_pkts; completed++) {
1620                 int segments = 0;
1621
1622                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1623                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1624                 ena_rx_ctx.descs = 0;
1625                 /* receive packet context */
1626                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1627                                     rx_ring->ena_com_io_sq,
1628                                     &ena_rx_ctx);
1629                 if (unlikely(rc)) {
1630                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1631                         return 0;
1632                 }
1633
1634                 if (unlikely(ena_rx_ctx.descs == 0))
1635                         break;
1636
1637                 while (segments < ena_rx_ctx.descs) {
1638                         mbuf = rx_buff_info[next_to_clean & ring_mask];
1639                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1640                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1641                         mbuf->refcnt = 1;
1642                         mbuf->next = NULL;
1643                         if (segments == 0) {
1644                                 mbuf->nb_segs = ena_rx_ctx.descs;
1645                                 mbuf->port = rx_ring->port_id;
1646                                 mbuf->pkt_len = 0;
1647                                 mbuf_head = mbuf;
1648                         } else {
1649                                 /* for multi-segment pkts create mbuf chain */
1650                                 mbuf_prev->next = mbuf;
1651                         }
1652                         mbuf_head->pkt_len += mbuf->data_len;
1653
1654                         mbuf_prev = mbuf;
1655                         segments++;
1656                         next_to_clean++;
1657                 }
1658
1659                 /* fill mbuf attributes if any */
1660                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1661                 mbuf_head->hash.rss = (uint32_t)rx_ring->id;
1662
1663                 /* pass to DPDK application head mbuf */
1664                 rx_pkts[recv_idx] = mbuf_head;
1665                 recv_idx++;
1666         }
1667
1668         rx_ring->next_to_clean = next_to_clean;
1669
1670         desc_in_use = desc_in_use - completed + 1;
1671         /* Burst refill to save doorbells, memory barriers, const interval */
1672         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1673                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1674
1675         return recv_idx;
1676 }
1677
1678 static uint16_t
1679 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1680                 uint16_t nb_pkts)
1681 {
1682         int32_t ret;
1683         uint32_t i;
1684         struct rte_mbuf *m;
1685         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1686         struct ipv4_hdr *ip_hdr;
1687         uint64_t ol_flags;
1688         uint16_t frag_field;
1689
1690         for (i = 0; i != nb_pkts; i++) {
1691                 m = tx_pkts[i];
1692                 ol_flags = m->ol_flags;
1693
1694                 if (!(ol_flags & PKT_TX_IPV4))
1695                         continue;
1696
1697                 /* If there was not L2 header length specified, assume it is
1698                  * length of the ethernet header.
1699                  */
1700                 if (unlikely(m->l2_len == 0))
1701                         m->l2_len = sizeof(struct ether_hdr);
1702
1703                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1704                                                  m->l2_len);
1705                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1706
1707                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1708                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1709
1710                         /* If IPv4 header has DF flag enabled and TSO support is
1711                          * disabled, partial chcecksum should not be calculated.
1712                          */
1713                         if (!tx_ring->adapter->tso4_supported)
1714                                 continue;
1715                 }
1716
1717                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
1718                                 (ol_flags & PKT_TX_L4_MASK) ==
1719                                 PKT_TX_SCTP_CKSUM) {
1720                         rte_errno = -ENOTSUP;
1721                         return i;
1722                 }
1723
1724 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1725                 ret = rte_validate_tx_offload(m);
1726                 if (ret != 0) {
1727                         rte_errno = ret;
1728                         return i;
1729                 }
1730 #endif
1731
1732                 /* In case we are supposed to TSO and have DF not set (DF=0)
1733                  * hardware must be provided with partial checksum, otherwise
1734                  * it will take care of necessary calculations.
1735                  */
1736
1737                 ret = rte_net_intel_cksum_flags_prepare(m,
1738                         ol_flags & ~PKT_TX_TCP_SEG);
1739                 if (ret != 0) {
1740                         rte_errno = ret;
1741                         return i;
1742                 }
1743         }
1744
1745         return i;
1746 }
1747
1748 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1749                                   uint16_t nb_pkts)
1750 {
1751         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1752         uint16_t next_to_use = tx_ring->next_to_use;
1753         uint16_t next_to_clean = tx_ring->next_to_clean;
1754         struct rte_mbuf *mbuf;
1755         unsigned int ring_size = tx_ring->ring_size;
1756         unsigned int ring_mask = ring_size - 1;
1757         struct ena_com_tx_ctx ena_tx_ctx;
1758         struct ena_tx_buffer *tx_info;
1759         struct ena_com_buf *ebuf;
1760         uint16_t rc, req_id, total_tx_descs = 0;
1761         uint16_t sent_idx = 0, empty_tx_reqs;
1762         int nb_hw_desc;
1763
1764         /* Check adapter state */
1765         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1766                 RTE_LOG(ALERT, PMD,
1767                         "Trying to xmit pkts while device is NOT running\n");
1768                 return 0;
1769         }
1770
1771         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
1772         if (nb_pkts > empty_tx_reqs)
1773                 nb_pkts = empty_tx_reqs;
1774
1775         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
1776                 mbuf = tx_pkts[sent_idx];
1777
1778                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
1779                 tx_info = &tx_ring->tx_buffer_info[req_id];
1780                 tx_info->mbuf = mbuf;
1781                 tx_info->num_of_bufs = 0;
1782                 ebuf = tx_info->bufs;
1783
1784                 /* Prepare TX context */
1785                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1786                 memset(&ena_tx_ctx.ena_meta, 0x0,
1787                        sizeof(struct ena_com_tx_meta));
1788                 ena_tx_ctx.ena_bufs = ebuf;
1789                 ena_tx_ctx.req_id = req_id;
1790                 if (tx_ring->tx_mem_queue_type ==
1791                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1792                         /* prepare the push buffer with
1793                          * virtual address of the data
1794                          */
1795                         ena_tx_ctx.header_len =
1796                                 RTE_MIN(mbuf->data_len,
1797                                         tx_ring->tx_max_header_size);
1798                         ena_tx_ctx.push_header =
1799                                 (void *)((char *)mbuf->buf_addr +
1800                                          mbuf->data_off);
1801                 } /* there's no else as we take advantage of memset zeroing */
1802
1803                 /* Set TX offloads flags, if applicable */
1804                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
1805
1806                 if (unlikely(mbuf->ol_flags &
1807                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
1808                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
1809
1810                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
1811
1812                 /* Process first segment taking into
1813                  * consideration pushed header
1814                  */
1815                 if (mbuf->data_len > ena_tx_ctx.header_len) {
1816                         ebuf->paddr = mbuf->buf_iova +
1817                                       mbuf->data_off +
1818                                       ena_tx_ctx.header_len;
1819                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
1820                         ebuf++;
1821                         tx_info->num_of_bufs++;
1822                 }
1823
1824                 while ((mbuf = mbuf->next) != NULL) {
1825                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
1826                         ebuf->len = mbuf->data_len;
1827                         ebuf++;
1828                         tx_info->num_of_bufs++;
1829                 }
1830
1831                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1832
1833                 /* Write data to device */
1834                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
1835                                         &ena_tx_ctx, &nb_hw_desc);
1836                 if (unlikely(rc))
1837                         break;
1838
1839                 tx_info->tx_descs = nb_hw_desc;
1840
1841                 next_to_use++;
1842         }
1843
1844         /* If there are ready packets to be xmitted... */
1845         if (sent_idx > 0) {
1846                 /* ...let HW do its best :-) */
1847                 rte_wmb();
1848                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
1849
1850                 tx_ring->next_to_use = next_to_use;
1851         }
1852
1853         /* Clear complete packets  */
1854         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
1855                 /* Get Tx info & store how many descs were processed  */
1856                 tx_info = &tx_ring->tx_buffer_info[req_id];
1857                 total_tx_descs += tx_info->tx_descs;
1858
1859                 /* Free whole mbuf chain  */
1860                 mbuf = tx_info->mbuf;
1861                 rte_pktmbuf_free(mbuf);
1862                 tx_info->mbuf = NULL;
1863
1864                 /* Put back descriptor to the ring for reuse */
1865                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
1866                 next_to_clean++;
1867
1868                 /* If too many descs to clean, leave it for another run */
1869                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
1870                         break;
1871         }
1872
1873         if (total_tx_descs > 0) {
1874                 /* acknowledge completion of sent packets */
1875                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
1876                 tx_ring->next_to_clean = next_to_clean;
1877         }
1878
1879         return sent_idx;
1880 }
1881
1882 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1883         struct rte_pci_device *pci_dev)
1884 {
1885         return rte_eth_dev_pci_generic_probe(pci_dev,
1886                 sizeof(struct ena_adapter), eth_ena_dev_init);
1887 }
1888
1889 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
1890 {
1891         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1892 }
1893
1894 static struct rte_pci_driver rte_ena_pmd = {
1895         .id_table = pci_id_ena_map,
1896         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1897         .probe = eth_ena_pci_probe,
1898         .remove = eth_ena_pci_remove,
1899 };
1900
1901 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
1902 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
1903 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
1904
1905 RTE_INIT(ena_init_log);
1906 static void
1907 ena_init_log(void)
1908 {
1909         ena_logtype_init = rte_log_register("pmd.net.ena.init");
1910         if (ena_logtype_init >= 0)
1911                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
1912         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
1913         if (ena_logtype_driver >= 0)
1914                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
1915 }