drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IPV6 |            \
 193         PKT_TX_IPV4 |            \
 194         PKT_TX_IP_CKSUM |        \
 195         PKT_TX_TCP_SEG)
 196
 197 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 198         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 199
 200 int ena_logtype_init;
 201 int ena_logtype_driver;
 202
 203 static const struct rte_pci_id pci_id_ena_map[] = {
 204         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 205         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 206         { .device_id = 0 },
 207 };
 208
 209 static struct ena_aenq_handlers aenq_handlers;
 210
 211 static int ena_device_init(struct ena_com_dev *ena_dev,
 212                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 213                            bool *wd_state);
 214 static int ena_dev_configure(struct rte_eth_dev *dev);
 215 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                                   uint16_t nb_pkts);
 217 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                 uint16_t nb_pkts);
 219 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 220                               uint16_t nb_desc, unsigned int socket_id,
 221                               const struct rte_eth_txconf *tx_conf);
 222 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 223                               uint16_t nb_desc, unsigned int socket_id,
 224                               const struct rte_eth_rxconf *rx_conf,
 225                               struct rte_mempool *mp);
 226 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 227                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 228 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 229 static void ena_init_rings(struct ena_adapter *adapter);
 230 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 231 static int ena_start(struct rte_eth_dev *dev);
 232 static void ena_stop(struct rte_eth_dev *dev);
 233 static void ena_close(struct rte_eth_dev *dev);
 234 static int ena_dev_reset(struct rte_eth_dev *dev);
 235 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 236 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 237 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 238 static void ena_rx_queue_release(void *queue);
 239 static void ena_tx_queue_release(void *queue);
 240 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 241 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 242 static int ena_link_update(struct rte_eth_dev *dev,
 243                            int wait_to_complete);
 244 static int ena_create_io_queue(struct ena_ring *ring);
 245 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 246 static int ena_queue_restart(struct ena_ring *ring);
 247 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 248                                  enum ena_ring_type ring_type);
 249 static void ena_stats_restart(struct rte_eth_dev *dev);
 250 static void ena_infos_get(struct rte_eth_dev *dev,
 251                           struct rte_eth_dev_info *dev_info);
 252 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 253                                struct rte_eth_rss_reta_entry64 *reta_conf,
 254                                uint16_t reta_size);
 255 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 256                               struct rte_eth_rss_reta_entry64 *reta_conf,
 257                               uint16_t reta_size);
 258 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 259 static void ena_interrupt_handler_rte(void *cb_arg);
 260 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 261
 262 static const struct eth_dev_ops ena_dev_ops = {
 263         .dev_configure        = ena_dev_configure,
 264         .dev_infos_get        = ena_infos_get,
 265         .rx_queue_setup       = ena_rx_queue_setup,
 266         .tx_queue_setup       = ena_tx_queue_setup,
 267         .dev_start            = ena_start,
 268         .dev_stop             = ena_stop,
 269         .link_update          = ena_link_update,
 270         .stats_get            = ena_stats_get,
 271         .mtu_set              = ena_mtu_set,
 272         .rx_queue_release     = ena_rx_queue_release,
 273         .tx_queue_release     = ena_tx_queue_release,
 274         .dev_close            = ena_close,
 275         .dev_reset            = ena_dev_reset,
 276         .reta_update          = ena_rss_reta_update,
 277         .reta_query           = ena_rss_reta_query,
 278 };
 279
 280 #define NUMA_NO_NODE    SOCKET_ID_ANY
 281
 282 static inline int ena_cpu_to_node(int cpu)
 283 {
 284         struct rte_config *config = rte_eal_get_configuration();
 285         struct rte_fbarray *arr = &config->mem_config->memzones;
 286         const struct rte_memzone *mz;
 287
 288         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 289                 return NUMA_NO_NODE;
 290
 291         mz = rte_fbarray_get(arr, cpu);
 292
 293         return mz->socket_id;
 294 }
 295
 296 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 297                                        struct ena_com_rx_ctx *ena_rx_ctx)
 298 {
 299         uint64_t ol_flags = 0;
 300         uint32_t packet_type = 0;
 301
 302         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 303                 packet_type |= RTE_PTYPE_L4_TCP;
 304         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 305                 packet_type |= RTE_PTYPE_L4_UDP;
 306
 307         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 308                 packet_type |= RTE_PTYPE_L3_IPV4;
 309         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 310                 packet_type |= RTE_PTYPE_L3_IPV6;
 311
 312         if (unlikely(ena_rx_ctx->l4_csum_err))
 313                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 314         if (unlikely(ena_rx_ctx->l3_csum_err))
 315                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 316
 317         mbuf->ol_flags = ol_flags;
 318         mbuf->packet_type = packet_type;
 319 }
 320
 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 322                                        struct ena_com_tx_ctx *ena_tx_ctx,
 323                                        uint64_t queue_offloads)
 324 {
 325         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 326
 327         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 328             (queue_offloads & QUEUE_OFFLOADS)) {
 329                 /* check if TSO is required */
 330                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 331                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 332                         ena_tx_ctx->tso_enable = true;
 333
 334                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 335                 }
 336
 337                 /* check if L3 checksum is needed */
 338                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 339                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 340                         ena_tx_ctx->l3_csum_enable = true;
 341
 342                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 343                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 344                 } else {
 345                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 346
 347                         /* set don't fragment (DF) flag */
 348                         if (mbuf->packet_type &
 349                                 (RTE_PTYPE_L4_NONFRAG
 350                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 351                                 ena_tx_ctx->df = true;
 352                 }
 353
 354                 /* check if L4 checksum is needed */
 355                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 356                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 360                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 362                         ena_tx_ctx->l4_csum_enable = true;
 363                 } else {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 365                         ena_tx_ctx->l4_csum_enable = false;
 366                 }
 367
 368                 ena_meta->mss = mbuf->tso_segsz;
 369                 ena_meta->l3_hdr_len = mbuf->l3_len;
 370                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 371
 372                 ena_tx_ctx->meta_valid = true;
 373         } else {
 374                 ena_tx_ctx->meta_valid = false;
 375         }
 376 }
 377
 378 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 379 {
 380         if (likely(req_id < rx_ring->ring_size))
 381                 return 0;
 382
 383         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 384
 385         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 386         rx_ring->adapter->trigger_reset = true;
 387
 388         return -EFAULT;
 389 }
 390
 391 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 392 {
 393         struct ena_tx_buffer *tx_info = NULL;
 394
 395         if (likely(req_id < tx_ring->ring_size)) {
 396                 tx_info = &tx_ring->tx_buffer_info[req_id];
 397                 if (likely(tx_info->mbuf))
 398                         return 0;
 399         }
 400
 401         if (tx_info)
 402                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 403         else
 404                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 405
 406         /* Trigger device reset */
 407         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 408         tx_ring->adapter->trigger_reset = true;
 409         return -EFAULT;
 410 }
 411
 412 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 413 {
 414         struct ena_admin_host_info *host_info;
 415         int rc;
 416
 417         /* Allocate only the host info */
 418         rc = ena_com_allocate_host_info(ena_dev);
 419         if (rc) {
 420                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 421                 return;
 422         }
 423
 424         host_info = ena_dev->host_attr.host_info;
 425
 426         host_info->os_type = ENA_ADMIN_OS_DPDK;
 427         host_info->kernel_ver = RTE_VERSION;
 428         snprintf((char *)host_info->kernel_ver_str,
 429                  sizeof(host_info->kernel_ver_str),
 430                  "%s", rte_version());
 431         host_info->os_dist = RTE_VERSION;
 432         snprintf((char *)host_info->os_dist_str,
 433                  sizeof(host_info->os_dist_str),
 434                  "%s", rte_version());
 435         host_info->driver_version =
 436                 (DRV_MODULE_VER_MAJOR) |
 437                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 438                 (DRV_MODULE_VER_SUBMINOR <<
 439                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 440         host_info->num_cpus = rte_lcore_count();
 441
 442         rc = ena_com_set_host_attributes(ena_dev);
 443         if (rc) {
 444                 if (rc == -ENA_COM_UNSUPPORTED)
 445                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 446                 else
 447                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 448
 449                 goto err;
 450         }
 451
 452         return;
 453
 454 err:
 455         ena_com_delete_host_info(ena_dev);
 456 }
 457
 458 static int
 459 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 460 {
 461         if (sset != ETH_SS_STATS)
 462                 return -EOPNOTSUPP;
 463
 464          /* Workaround for clang:
 465          * touch internal structures to prevent
 466          * compiler error
 467          */
 468         ENA_TOUCH(ena_stats_global_strings);
 469         ENA_TOUCH(ena_stats_tx_strings);
 470         ENA_TOUCH(ena_stats_rx_strings);
 471         ENA_TOUCH(ena_stats_ena_com_strings);
 472
 473         return  dev->data->nb_tx_queues *
 474                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 475                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 476 }
 477
 478 static void ena_config_debug_area(struct ena_adapter *adapter)
 479 {
 480         u32 debug_area_size;
 481         int rc, ss_count;
 482
 483         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 484         if (ss_count <= 0) {
 485                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 486                 return;
 487         }
 488
 489         /* allocate 32 bytes for each string and 64bit for the value */
 490         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 491
 492         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 493         if (rc) {
 494                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 495                 return;
 496         }
 497
 498         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 499         if (rc) {
 500                 if (rc == -ENA_COM_UNSUPPORTED)
 501                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 502                 else
 503                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 504
 505                 goto err;
 506         }
 507
 508         return;
 509 err:
 510         ena_com_delete_debug_area(&adapter->ena_dev);
 511 }
 512
 513 static void ena_close(struct rte_eth_dev *dev)
 514 {
 515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 517         struct ena_adapter *adapter =
 518                 (struct ena_adapter *)(dev->data->dev_private);
 519
 520         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 521                 ena_stop(dev);
 522         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 523
 524         ena_rx_queue_release_all(dev);
 525         ena_tx_queue_release_all(dev);
 526
 527         rte_free(adapter->drv_stats);
 528         adapter->drv_stats = NULL;
 529
 530         rte_intr_disable(intr_handle);
 531         rte_intr_callback_unregister(intr_handle,
 532                                      ena_interrupt_handler_rte,
 533                                      adapter);
 534
 535         /*
 536          * MAC is not allocated dynamically. Setting NULL should prevent from
 537          * release of the resource in the rte_eth_dev_release_port().
 538          */
 539         dev->data->mac_addrs = NULL;
 540 }
 541
 542 static int
 543 ena_dev_reset(struct rte_eth_dev *dev)
 544 {
 545         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 546         struct rte_eth_dev *eth_dev;
 547         struct rte_pci_device *pci_dev;
 548         struct rte_intr_handle *intr_handle;
 549         struct ena_com_dev *ena_dev;
 550         struct ena_com_dev_get_features_ctx get_feat_ctx;
 551         struct ena_adapter *adapter;
 552         int nb_queues;
 553         int rc, i;
 554         bool wd_state;
 555
 556         adapter = (struct ena_adapter *)(dev->data->dev_private);
 557         ena_dev = &adapter->ena_dev;
 558         eth_dev = adapter->rte_dev;
 559         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 560         intr_handle = &pci_dev->intr_handle;
 561         nb_queues = eth_dev->data->nb_rx_queues;
 562
 563         ena_com_set_admin_running_state(ena_dev, false);
 564
 565         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 566         if (rc)
 567                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 568
 569         for (i = 0; i < nb_queues; i++)
 570                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 571
 572         ena_rx_queue_release_all(eth_dev);
 573         ena_tx_queue_release_all(eth_dev);
 574
 575         rte_intr_disable(intr_handle);
 576
 577         ena_com_abort_admin_commands(ena_dev);
 578         ena_com_wait_for_abort_completion(ena_dev);
 579         ena_com_admin_destroy(ena_dev);
 580         ena_com_mmio_reg_read_request_destroy(ena_dev);
 581
 582         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 583         if (rc) {
 584                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 585                 return rc;
 586         }
 587         adapter->wd_state = wd_state;
 588
 589         rte_intr_enable(intr_handle);
 590         ena_com_set_admin_polling_mode(ena_dev, false);
 591         ena_com_admin_aenq_enable(ena_dev);
 592
 593         for (i = 0; i < nb_queues; ++i)
 594                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 595                         mb_pool_rx[i]);
 596
 597         for (i = 0; i < nb_queues; ++i)
 598                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 599
 600         adapter->trigger_reset = false;
 601
 602         return 0;
 603 }
 604
 605 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 606                                struct rte_eth_rss_reta_entry64 *reta_conf,
 607                                uint16_t reta_size)
 608 {
 609         struct ena_adapter *adapter =
 610                 (struct ena_adapter *)(dev->data->dev_private);
 611         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 612         int rc, i;
 613         u16 entry_value;
 614         int conf_idx;
 615         int idx;
 616
 617         if ((reta_size == 0) || (reta_conf == NULL))
 618                 return -EINVAL;
 619
 620         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 621                 RTE_LOG(WARNING, PMD,
 622                         "indirection table %d is bigger than supported (%d)\n",
 623                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 624                 return -EINVAL;
 625         }
 626
 627         for (i = 0 ; i < reta_size ; i++) {
 628                 /* each reta_conf is for 64 entries.
 629                  * to support 128 we use 2 conf of 64
 630                  */
 631                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 632                 idx = i % RTE_RETA_GROUP_SIZE;
 633                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 634                         entry_value =
 635                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 636
 637                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 638                                                                i,
 639                                                                entry_value);
 640                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 641                                 RTE_LOG(ERR, PMD,
 642                                         "Cannot fill indirect table\n");
 643                                 return rc;
 644                         }
 645                 }
 646         }
 647
 648         rc = ena_com_indirect_table_set(ena_dev);
 649         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 650                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 651                 return rc;
 652         }
 653
 654         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 655                 __func__, reta_size, adapter->rte_dev->data->port_id);
 656
 657         return 0;
 658 }
 659
 660 /* Query redirection table. */
 661 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 662                               struct rte_eth_rss_reta_entry64 *reta_conf,
 663                               uint16_t reta_size)
 664 {
 665         struct ena_adapter *adapter =
 666                 (struct ena_adapter *)(dev->data->dev_private);
 667         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 668         int rc;
 669         int i;
 670         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 671         int reta_conf_idx;
 672         int reta_idx;
 673
 674         if (reta_size == 0 || reta_conf == NULL ||
 675             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 676                 return -EINVAL;
 677
 678         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 679         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 680                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 681                 return -ENOTSUP;
 682         }
 683
 684         for (i = 0 ; i < reta_size ; i++) {
 685                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 686                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 687                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 688                         reta_conf[reta_conf_idx].reta[reta_idx] =
 689                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int ena_rss_init_default(struct ena_adapter *adapter)
 696 {
 697         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 698         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 699         int rc, i;
 700         u32 val;
 701
 702         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 703         if (unlikely(rc)) {
 704                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 705                 goto err_rss_init;
 706         }
 707
 708         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 709                 val = i % nb_rx_queues;
 710                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 711                                                        ENA_IO_RXQ_IDX(val));
 712                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 713                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 714                         goto err_fill_indir;
 715                 }
 716         }
 717
 718         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 719                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 720         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 721                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 722                 goto err_fill_indir;
 723         }
 724
 725         rc = ena_com_set_default_hash_ctrl(ena_dev);
 726         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 727                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 728                 goto err_fill_indir;
 729         }
 730
 731         rc = ena_com_indirect_table_set(ena_dev);
 732         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 733                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 734                 goto err_fill_indir;
 735         }
 736         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 737                 adapter->rte_dev->data->port_id);
 738
 739         return 0;
 740
 741 err_fill_indir:
 742         ena_com_rss_destroy(ena_dev);
 743 err_rss_init:
 744
 745         return rc;
 746 }
 747
 748 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 749 {
 750         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 751         int nb_queues = dev->data->nb_rx_queues;
 752         int i;
 753
 754         for (i = 0; i < nb_queues; i++)
 755                 ena_rx_queue_release(queues[i]);
 756 }
 757
 758 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 759 {
 760         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 761         int nb_queues = dev->data->nb_tx_queues;
 762         int i;
 763
 764         for (i = 0; i < nb_queues; i++)
 765                 ena_tx_queue_release(queues[i]);
 766 }
 767
 768 static void ena_rx_queue_release(void *queue)
 769 {
 770         struct ena_ring *ring = (struct ena_ring *)queue;
 771
 772         ena_assert_msg(ring->configured,
 773                        "API violation - releasing not configured queue");
 774         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 775                        "API violation");
 776
 777         /* Free ring resources */
 778         if (ring->rx_buffer_info)
 779                 rte_free(ring->rx_buffer_info);
 780         ring->rx_buffer_info = NULL;
 781
 782         if (ring->rx_refill_buffer)
 783                 rte_free(ring->rx_refill_buffer);
 784         ring->rx_refill_buffer = NULL;
 785
 786         if (ring->empty_rx_reqs)
 787                 rte_free(ring->empty_rx_reqs);
 788         ring->empty_rx_reqs = NULL;
 789
 790         ring->configured = 0;
 791
 792         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 793                 ring->port_id, ring->id);
 794 }
 795
 796 static void ena_tx_queue_release(void *queue)
 797 {
 798         struct ena_ring *ring = (struct ena_ring *)queue;
 799
 800         ena_assert_msg(ring->configured,
 801                        "API violation. Releasing not configured queue");
 802         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 803                        "API violation");
 804
 805         /* Free all bufs */
 806         ena_tx_queue_release_bufs(ring);
 807
 808         /* Free ring resources */
 809         if (ring->tx_buffer_info)
 810                 rte_free(ring->tx_buffer_info);
 811
 812         if (ring->empty_tx_reqs)
 813                 rte_free(ring->empty_tx_reqs);
 814
 815         ring->empty_tx_reqs = NULL;
 816         ring->tx_buffer_info = NULL;
 817
 818         ring->configured = 0;
 819
 820         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 821                 ring->port_id, ring->id);
 822 }
 823
 824 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 825 {
 826         unsigned int ring_mask = ring->ring_size - 1;
 827
 828         while (ring->next_to_clean != ring->next_to_use) {
 829                 struct rte_mbuf *m =
 830                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 831
 832                 if (m)
 833                         rte_mbuf_raw_free(m);
 834
 835                 ring->next_to_clean++;
 836         }
 837 }
 838
 839 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 840 {
 841         unsigned int i;
 842
 843         for (i = 0; i < ring->ring_size; ++i) {
 844                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 845
 846                 if (tx_buf->mbuf)
 847                         rte_pktmbuf_free(tx_buf->mbuf);
 848
 849                 ring->next_to_clean++;
 850         }
 851 }
 852
 853 static int ena_link_update(struct rte_eth_dev *dev,
 854                            __rte_unused int wait_to_complete)
 855 {
 856         struct rte_eth_link *link = &dev->data->dev_link;
 857         struct ena_adapter *adapter;
 858
 859         adapter = (struct ena_adapter *)(dev->data->dev_private);
 860
 861         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 862         link->link_speed = ETH_SPEED_NUM_NONE;
 863         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 864
 865         return 0;
 866 }
 867
 868 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 869                                  enum ena_ring_type ring_type)
 870 {
 871         struct ena_adapter *adapter =
 872                 (struct ena_adapter *)(dev->data->dev_private);
 873         struct ena_ring *queues = NULL;
 874         int nb_queues;
 875         int i = 0;
 876         int rc = 0;
 877
 878         if (ring_type == ENA_RING_TYPE_RX) {
 879                 queues = adapter->rx_ring;
 880                 nb_queues = dev->data->nb_rx_queues;
 881         } else {
 882                 queues = adapter->tx_ring;
 883                 nb_queues = dev->data->nb_tx_queues;
 884         }
 885         for (i = 0; i < nb_queues; i++) {
 886                 if (queues[i].configured) {
 887                         if (ring_type == ENA_RING_TYPE_RX) {
 888                                 ena_assert_msg(
 889                                         dev->data->rx_queues[i] == &queues[i],
 890                                         "Inconsistent state of rx queues\n");
 891                         } else {
 892                                 ena_assert_msg(
 893                                         dev->data->tx_queues[i] == &queues[i],
 894                                         "Inconsistent state of tx queues\n");
 895                         }
 896
 897                         rc = ena_queue_restart(&queues[i]);
 898
 899                         if (rc) {
 900                                 PMD_INIT_LOG(ERR,
 901                                              "failed to restart queue %d type(%d)",
 902                                              i, ring_type);
 903                                 return rc;
 904                         }
 905                 }
 906         }
 907
 908         return 0;
 909 }
 910
 911 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 912 {
 913         uint32_t max_frame_len = adapter->max_mtu;
 914
 915         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 916             DEV_RX_OFFLOAD_JUMBO_FRAME)
 917                 max_frame_len =
 918                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 919
 920         return max_frame_len;
 921 }
 922
 923 static int ena_check_valid_conf(struct ena_adapter *adapter)
 924 {
 925         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 926
 927         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 928                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 929                                   "max mtu: %d, min mtu: %d\n",
 930                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 931                 return ENA_COM_UNSUPPORTED;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int
 938 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 939                     u16 *max_tx_sgl_size,
 940                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 941 {
 942         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 943
 944         queue_size = RTE_MIN(queue_size,
 945                              get_feat_ctx->max_queues.max_cq_depth);
 946         queue_size = RTE_MIN(queue_size,
 947                              get_feat_ctx->max_queues.max_sq_depth);
 948
 949         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 950                 queue_size = RTE_MIN(queue_size,
 951                                      get_feat_ctx->max_queues.max_legacy_llq_depth);
 952
 953         /* Round down to power of 2 */
 954         if (!rte_is_power_of_2(queue_size))
 955                 queue_size = rte_align32pow2(queue_size >> 1);
 956
 957         if (unlikely(queue_size == 0)) {
 958                 PMD_INIT_LOG(ERR, "Invalid queue size");
 959                 return -EFAULT;
 960         }
 961
 962         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 963                 get_feat_ctx->max_queues.max_packet_tx_descs);
 964
 965         return queue_size;
 966 }
 967
 968 static void ena_stats_restart(struct rte_eth_dev *dev)
 969 {
 970         struct ena_adapter *adapter =
 971                 (struct ena_adapter *)(dev->data->dev_private);
 972
 973         rte_atomic64_init(&adapter->drv_stats->ierrors);
 974         rte_atomic64_init(&adapter->drv_stats->oerrors);
 975         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 976 }
 977
 978 static int ena_stats_get(struct rte_eth_dev *dev,
 979                           struct rte_eth_stats *stats)
 980 {
 981         struct ena_admin_basic_stats ena_stats;
 982         struct ena_adapter *adapter =
 983                 (struct ena_adapter *)(dev->data->dev_private);
 984         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 985         int rc;
 986
 987         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 988                 return -ENOTSUP;
 989
 990         memset(&ena_stats, 0, sizeof(ena_stats));
 991         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 992         if (unlikely(rc)) {
 993                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 994                 return rc;
 995         }
 996
 997         /* Set of basic statistics from ENA */
 998         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 999                                           ena_stats.rx_pkts_low);
1000         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1001                                           ena_stats.tx_pkts_low);
1002         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1003                                         ena_stats.rx_bytes_low);
1004         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1005                                         ena_stats.tx_bytes_low);
1006         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1007                                          ena_stats.rx_drops_low);
1008
1009         /* Driver related stats */
1010         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1011         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1012         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1013         return 0;
1014 }
1015
1016 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1017 {
1018         struct ena_adapter *adapter;
1019         struct ena_com_dev *ena_dev;
1020         int rc = 0;
1021
1022         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1023         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1024         adapter = (struct ena_adapter *)(dev->data->dev_private);
1025
1026         ena_dev = &adapter->ena_dev;
1027         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1028
1029         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1030                 RTE_LOG(ERR, PMD,
1031                         "Invalid MTU setting. new_mtu: %d "
1032                         "max mtu: %d min mtu: %d\n",
1033                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1034                 return -EINVAL;
1035         }
1036
1037         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1038         if (rc)
1039                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1040         else
1041                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1042
1043         return rc;
1044 }
1045
1046 static int ena_start(struct rte_eth_dev *dev)
1047 {
1048         struct ena_adapter *adapter =
1049                 (struct ena_adapter *)(dev->data->dev_private);
1050         uint64_t ticks;
1051         int rc = 0;
1052
1053         rc = ena_check_valid_conf(adapter);
1054         if (rc)
1055                 return rc;
1056
1057         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1058         if (rc)
1059                 return rc;
1060
1061         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1062         if (rc)
1063                 return rc;
1064
1065         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1066             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1067                 rc = ena_rss_init_default(adapter);
1068                 if (rc)
1069                         return rc;
1070         }
1071
1072         ena_stats_restart(dev);
1073
1074         adapter->timestamp_wd = rte_get_timer_cycles();
1075         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1076
1077         ticks = rte_get_timer_hz();
1078         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1079                         ena_timer_wd_callback, adapter);
1080
1081         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1082
1083         return 0;
1084 }
1085
1086 static void ena_stop(struct rte_eth_dev *dev)
1087 {
1088         struct ena_adapter *adapter =
1089                 (struct ena_adapter *)(dev->data->dev_private);
1090
1091         rte_timer_stop_sync(&adapter->timer_wd);
1092         ena_free_io_queues_all(adapter);
1093
1094         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1095 }
1096
1097 static int ena_create_io_queue(struct ena_ring *ring)
1098 {
1099         struct ena_adapter *adapter;
1100         struct ena_com_dev *ena_dev;
1101         struct ena_com_create_io_ctx ctx =
1102                 /* policy set to _HOST just to satisfy icc compiler */
1103                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1104                   0, 0, 0, 0, 0 };
1105         uint16_t ena_qid;
1106         unsigned int i;
1107         int rc;
1108
1109         adapter = ring->adapter;
1110         ena_dev = &adapter->ena_dev;
1111
1112         if (ring->type == ENA_RING_TYPE_TX) {
1113                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1114                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1115                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1116                 ctx.queue_size = adapter->tx_ring_size;
1117                 for (i = 0; i < ring->ring_size; i++)
1118                         ring->empty_tx_reqs[i] = i;
1119         } else {
1120                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1121                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1122                 ctx.queue_size = adapter->rx_ring_size;
1123                 for (i = 0; i < ring->ring_size; i++)
1124                         ring->empty_rx_reqs[i] = i;
1125         }
1126         ctx.qid = ena_qid;
1127         ctx.msix_vector = -1; /* interrupts not used */
1128         ctx.numa_node = ena_cpu_to_node(ring->id);
1129
1130         rc = ena_com_create_io_queue(ena_dev, &ctx);
1131         if (rc) {
1132                 RTE_LOG(ERR, PMD,
1133                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1134                         ring->id, ena_qid, rc);
1135                 return rc;
1136         }
1137
1138         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1139                                      &ring->ena_com_io_sq,
1140                                      &ring->ena_com_io_cq);
1141         if (rc) {
1142                 RTE_LOG(ERR, PMD,
1143                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1144                         ring->id, rc);
1145                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1146                 return rc;
1147         }
1148
1149         if (ring->type == ENA_RING_TYPE_TX)
1150                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1151
1152         return 0;
1153 }
1154
1155 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1156 {
1157         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1158         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1159         int i;
1160         uint16_t ena_qid;
1161         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1162         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1163
1164         for (i = 0; i < nb_txq; ++i) {
1165                 ena_qid = ENA_IO_TXQ_IDX(i);
1166                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1167
1168                 ena_tx_queue_release_bufs(&adapter->tx_ring[i]);
1169         }
1170
1171         for (i = 0; i < nb_rxq; ++i) {
1172                 ena_qid = ENA_IO_RXQ_IDX(i);
1173                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1174
1175                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1176         }
1177 }
1178
1179 static int ena_queue_restart(struct ena_ring *ring)
1180 {
1181         int rc, bufs_num;
1182
1183         ena_assert_msg(ring->configured == 1,
1184                        "Trying to restart unconfigured queue\n");
1185
1186         rc = ena_create_io_queue(ring);
1187         if (rc) {
1188                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1189                 return rc;
1190         }
1191
1192         ring->next_to_clean = 0;
1193         ring->next_to_use = 0;
1194
1195         if (ring->type == ENA_RING_TYPE_TX)
1196                 return 0;
1197
1198         bufs_num = ring->ring_size - 1;
1199         rc = ena_populate_rx_queue(ring, bufs_num);
1200         if (rc != bufs_num) {
1201                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1202                 return ENA_COM_FAULT;
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1209                               uint16_t queue_idx,
1210                               uint16_t nb_desc,
1211                               __rte_unused unsigned int socket_id,
1212                               const struct rte_eth_txconf *tx_conf)
1213 {
1214         struct ena_ring *txq = NULL;
1215         struct ena_adapter *adapter =
1216                 (struct ena_adapter *)(dev->data->dev_private);
1217         unsigned int i;
1218
1219         txq = &adapter->tx_ring[queue_idx];
1220
1221         if (txq->configured) {
1222                 RTE_LOG(CRIT, PMD,
1223                         "API violation. Queue %d is already configured\n",
1224                         queue_idx);
1225                 return ENA_COM_FAULT;
1226         }
1227
1228         if (!rte_is_power_of_2(nb_desc)) {
1229                 RTE_LOG(ERR, PMD,
1230                         "Unsupported size of TX queue: %d is not a power of 2.",
1231                         nb_desc);
1232                 return -EINVAL;
1233         }
1234
1235         if (nb_desc > adapter->tx_ring_size) {
1236                 RTE_LOG(ERR, PMD,
1237                         "Unsupported size of TX queue (max size: %d)\n",
1238                         adapter->tx_ring_size);
1239                 return -EINVAL;
1240         }
1241
1242         txq->port_id = dev->data->port_id;
1243         txq->next_to_clean = 0;
1244         txq->next_to_use = 0;
1245         txq->ring_size = nb_desc;
1246
1247         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1248                                           sizeof(struct ena_tx_buffer) *
1249                                           txq->ring_size,
1250                                           RTE_CACHE_LINE_SIZE);
1251         if (!txq->tx_buffer_info) {
1252                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1253                 return -ENOMEM;
1254         }
1255
1256         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1257                                          sizeof(u16) * txq->ring_size,
1258                                          RTE_CACHE_LINE_SIZE);
1259         if (!txq->empty_tx_reqs) {
1260                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1261                 rte_free(txq->tx_buffer_info);
1262                 return -ENOMEM;
1263         }
1264
1265         for (i = 0; i < txq->ring_size; i++)
1266                 txq->empty_tx_reqs[i] = i;
1267
1268         if (tx_conf != NULL) {
1269                 txq->offloads =
1270                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1271         }
1272
1273         /* Store pointer to this queue in upper layer */
1274         txq->configured = 1;
1275         dev->data->tx_queues[queue_idx] = txq;
1276
1277         return 0;
1278 }
1279
1280 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1281                               uint16_t queue_idx,
1282                               uint16_t nb_desc,
1283                               __rte_unused unsigned int socket_id,
1284                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1285                               struct rte_mempool *mp)
1286 {
1287         struct ena_adapter *adapter =
1288                 (struct ena_adapter *)(dev->data->dev_private);
1289         struct ena_ring *rxq = NULL;
1290         int i;
1291
1292         rxq = &adapter->rx_ring[queue_idx];
1293         if (rxq->configured) {
1294                 RTE_LOG(CRIT, PMD,
1295                         "API violation. Queue %d is already configured\n",
1296                         queue_idx);
1297                 return ENA_COM_FAULT;
1298         }
1299
1300         if (!rte_is_power_of_2(nb_desc)) {
1301                 RTE_LOG(ERR, PMD,
1302                         "Unsupported size of RX queue: %d is not a power of 2.",
1303                         nb_desc);
1304                 return -EINVAL;
1305         }
1306
1307         if (nb_desc > adapter->rx_ring_size) {
1308                 RTE_LOG(ERR, PMD,
1309                         "Unsupported size of RX queue (max size: %d)\n",
1310                         adapter->rx_ring_size);
1311                 return -EINVAL;
1312         }
1313
1314         rxq->port_id = dev->data->port_id;
1315         rxq->next_to_clean = 0;
1316         rxq->next_to_use = 0;
1317         rxq->ring_size = nb_desc;
1318         rxq->mb_pool = mp;
1319
1320         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1321                                           sizeof(struct rte_mbuf *) * nb_desc,
1322                                           RTE_CACHE_LINE_SIZE);
1323         if (!rxq->rx_buffer_info) {
1324                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1325                 return -ENOMEM;
1326         }
1327
1328         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1329                                             sizeof(struct rte_mbuf *) * nb_desc,
1330                                             RTE_CACHE_LINE_SIZE);
1331
1332         if (!rxq->rx_refill_buffer) {
1333                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1334                 rte_free(rxq->rx_buffer_info);
1335                 rxq->rx_buffer_info = NULL;
1336                 return -ENOMEM;
1337         }
1338
1339         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1340                                          sizeof(uint16_t) * nb_desc,
1341                                          RTE_CACHE_LINE_SIZE);
1342         if (!rxq->empty_rx_reqs) {
1343                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1344                 rte_free(rxq->rx_buffer_info);
1345                 rxq->rx_buffer_info = NULL;
1346                 rte_free(rxq->rx_refill_buffer);
1347                 rxq->rx_refill_buffer = NULL;
1348                 return -ENOMEM;
1349         }
1350
1351         for (i = 0; i < nb_desc; i++)
1352                 rxq->empty_tx_reqs[i] = i;
1353
1354         /* Store pointer to this queue in upper layer */
1355         rxq->configured = 1;
1356         dev->data->rx_queues[queue_idx] = rxq;
1357
1358         return 0;
1359 }
1360
1361 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1362 {
1363         unsigned int i;
1364         int rc;
1365         uint16_t ring_size = rxq->ring_size;
1366         uint16_t ring_mask = ring_size - 1;
1367         uint16_t next_to_use = rxq->next_to_use;
1368         uint16_t in_use, req_id;
1369         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1370
1371         if (unlikely(!count))
1372                 return 0;
1373
1374         in_use = rxq->next_to_use - rxq->next_to_clean;
1375         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1376
1377         /* get resources for incoming packets */
1378         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1379         if (unlikely(rc < 0)) {
1380                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1381                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1382                 return 0;
1383         }
1384
1385         for (i = 0; i < count; i++) {
1386                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1387                 struct rte_mbuf *mbuf = mbufs[i];
1388                 struct ena_com_buf ebuf;
1389
1390                 if (likely((i + 4) < count))
1391                         rte_prefetch0(mbufs[i + 4]);
1392
1393                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1394                 rc = validate_rx_req_id(rxq, req_id);
1395                 if (unlikely(rc < 0))
1396                         break;
1397                 rxq->rx_buffer_info[req_id] = mbuf;
1398
1399                 /* prepare physical address for DMA transaction */
1400                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1401                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1402                 /* pass resource to device */
1403                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1404                                                 &ebuf, req_id);
1405                 if (unlikely(rc)) {
1406                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1407                         rxq->rx_buffer_info[req_id] = NULL;
1408                         break;
1409                 }
1410                 next_to_use++;
1411         }
1412
1413         if (unlikely(i < count)) {
1414                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1415                         "buffers (from %d)\n", rxq->id, i, count);
1416                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1417                                      count - i);
1418         }
1419
1420         /* When we submitted free recources to device... */
1421         if (likely(i > 0)) {
1422                 /* ...let HW know that it can fill buffers with data
1423                  *
1424                  * Add memory barrier to make sure the desc were written before
1425                  * issue a doorbell
1426                  */
1427                 rte_wmb();
1428                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1429
1430                 rxq->next_to_use = next_to_use;
1431         }
1432
1433         return i;
1434 }
1435
1436 static int ena_device_init(struct ena_com_dev *ena_dev,
1437                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1438                            bool *wd_state)
1439 {
1440         uint32_t aenq_groups;
1441         int rc;
1442         bool readless_supported;
1443
1444         /* Initialize mmio registers */
1445         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1446         if (rc) {
1447                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1448                 return rc;
1449         }
1450
1451         /* The PCIe configuration space revision id indicate if mmio reg
1452          * read is disabled.
1453          */
1454         readless_supported =
1455                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1456                                & ENA_MMIO_DISABLE_REG_READ);
1457         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1458
1459         /* reset device */
1460         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1461         if (rc) {
1462                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1463                 goto err_mmio_read_less;
1464         }
1465
1466         /* check FW version */
1467         rc = ena_com_validate_version(ena_dev);
1468         if (rc) {
1469                 RTE_LOG(ERR, PMD, "device version is too low\n");
1470                 goto err_mmio_read_less;
1471         }
1472
1473         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1474
1475         /* ENA device administration layer init */
1476         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1477         if (rc) {
1478                 RTE_LOG(ERR, PMD,
1479                         "cannot initialize ena admin queue with device\n");
1480                 goto err_mmio_read_less;
1481         }
1482
1483         /* To enable the msix interrupts the driver needs to know the number
1484          * of queues. So the driver uses polling mode to retrieve this
1485          * information.
1486          */
1487         ena_com_set_admin_polling_mode(ena_dev, true);
1488
1489         ena_config_host_info(ena_dev);
1490
1491         /* Get Device Attributes and features */
1492         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1493         if (rc) {
1494                 RTE_LOG(ERR, PMD,
1495                         "cannot get attribute for ena device rc= %d\n", rc);
1496                 goto err_admin_init;
1497         }
1498
1499         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1500                       BIT(ENA_ADMIN_NOTIFICATION) |
1501                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1502                       BIT(ENA_ADMIN_FATAL_ERROR) |
1503                       BIT(ENA_ADMIN_WARNING);
1504
1505         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1506         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1507         if (rc) {
1508                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1509                 goto err_admin_init;
1510         }
1511
1512         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1513
1514         return 0;
1515
1516 err_admin_init:
1517         ena_com_admin_destroy(ena_dev);
1518
1519 err_mmio_read_less:
1520         ena_com_mmio_reg_read_request_destroy(ena_dev);
1521
1522         return rc;
1523 }
1524
1525 static void ena_interrupt_handler_rte(void *cb_arg)
1526 {
1527         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1528         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1529
1530         ena_com_admin_q_comp_intr_handler(ena_dev);
1531         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1532                 ena_com_aenq_intr_handler(ena_dev, adapter);
1533 }
1534
1535 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1536 {
1537         if (!adapter->wd_state)
1538                 return;
1539
1540         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1541                 return;
1542
1543         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1544             adapter->keep_alive_timeout)) {
1545                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1546                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1547                 adapter->trigger_reset = true;
1548         }
1549 }
1550
1551 /* Check if admin queue is enabled */
1552 static void check_for_admin_com_state(struct ena_adapter *adapter)
1553 {
1554         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1555                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1556                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1557                 adapter->trigger_reset = true;
1558         }
1559 }
1560
1561 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1562                                   void *arg)
1563 {
1564         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1565         struct rte_eth_dev *dev = adapter->rte_dev;
1566
1567         check_for_missing_keep_alive(adapter);
1568         check_for_admin_com_state(adapter);
1569
1570         if (unlikely(adapter->trigger_reset)) {
1571                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1572                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1573                         NULL);
1574         }
1575 }
1576
1577 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1578                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1579 {
1580         int io_sq_num, io_cq_num, io_queue_num;
1581
1582         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1583         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1584
1585         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1586
1587         if (unlikely(io_queue_num == 0)) {
1588                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1589                 return -EFAULT;
1590         }
1591
1592         return io_queue_num;
1593 }
1594
1595 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1596 {
1597         struct rte_pci_device *pci_dev;
1598         struct rte_intr_handle *intr_handle;
1599         struct ena_adapter *adapter =
1600                 (struct ena_adapter *)(eth_dev->data->dev_private);
1601         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1602         struct ena_com_dev_get_features_ctx get_feat_ctx;
1603         int queue_size, rc;
1604         u16 tx_sgl_size = 0;
1605
1606         static int adapters_found;
1607         bool wd_state;
1608
1609         memset(adapter, 0, sizeof(struct ena_adapter));
1610         ena_dev = &adapter->ena_dev;
1611
1612         eth_dev->dev_ops = &ena_dev_ops;
1613         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1614         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1615         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1616         adapter->rte_eth_dev_data = eth_dev->data;
1617         adapter->rte_dev = eth_dev;
1618
1619         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1620                 return 0;
1621
1622         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1623         adapter->pdev = pci_dev;
1624
1625         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1626                      pci_dev->addr.domain,
1627                      pci_dev->addr.bus,
1628                      pci_dev->addr.devid,
1629                      pci_dev->addr.function);
1630
1631         intr_handle = &pci_dev->intr_handle;
1632
1633         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1634         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1635
1636         if (!adapter->regs) {
1637                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1638                              ENA_REGS_BAR);
1639                 return -ENXIO;
1640         }
1641
1642         ena_dev->reg_bar = adapter->regs;
1643         ena_dev->dmadev = adapter->pdev;
1644
1645         adapter->id_number = adapters_found;
1646
1647         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1648                  adapter->id_number);
1649
1650         /* device specific initialization routine */
1651         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1652         if (rc) {
1653                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1654                 goto err;
1655         }
1656         adapter->wd_state = wd_state;
1657
1658         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1659         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1660                                                     &get_feat_ctx);
1661
1662         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1663         if (queue_size <= 0 || adapter->num_queues <= 0) {
1664                 rc = -EFAULT;
1665                 goto err_device_destroy;
1666         }
1667
1668         adapter->tx_ring_size = queue_size;
1669         adapter->rx_ring_size = queue_size;
1670
1671         adapter->max_tx_sgl_size = tx_sgl_size;
1672
1673         /* prepare ring structures */
1674         ena_init_rings(adapter);
1675
1676         ena_config_debug_area(adapter);
1677
1678         /* Set max MTU for this device */
1679         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1680
1681         /* set device support for TSO */
1682         adapter->tso4_supported = get_feat_ctx.offload.tx &
1683                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1684
1685         /* Copy MAC address and point DPDK to it */
1686         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1687         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1688                         (struct ether_addr *)adapter->mac_addr);
1689
1690         /*
1691          * Pass the information to the rte_eth_dev_close() that it should also
1692          * release the private port resources.
1693          */
1694         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1695
1696         adapter->drv_stats = rte_zmalloc("adapter stats",
1697                                          sizeof(*adapter->drv_stats),
1698                                          RTE_CACHE_LINE_SIZE);
1699         if (!adapter->drv_stats) {
1700                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1701                 rc = -ENOMEM;
1702                 goto err_delete_debug_area;
1703         }
1704
1705         rte_intr_callback_register(intr_handle,
1706                                    ena_interrupt_handler_rte,
1707                                    adapter);
1708         rte_intr_enable(intr_handle);
1709         ena_com_set_admin_polling_mode(ena_dev, false);
1710         ena_com_admin_aenq_enable(ena_dev);
1711
1712         if (adapters_found == 0)
1713                 rte_timer_subsystem_init();
1714         rte_timer_init(&adapter->timer_wd);
1715
1716         adapters_found++;
1717         adapter->state = ENA_ADAPTER_STATE_INIT;
1718
1719         return 0;
1720
1721 err_delete_debug_area:
1722         ena_com_delete_debug_area(ena_dev);
1723
1724 err_device_destroy:
1725         ena_com_delete_host_info(ena_dev);
1726         ena_com_admin_destroy(ena_dev);
1727
1728 err:
1729         return rc;
1730 }
1731
1732 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1733 {
1734         struct ena_adapter *adapter =
1735                 (struct ena_adapter *)(eth_dev->data->dev_private);
1736
1737         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1738                 return 0;
1739
1740         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1741                 ena_close(eth_dev);
1742
1743         eth_dev->dev_ops = NULL;
1744         eth_dev->rx_pkt_burst = NULL;
1745         eth_dev->tx_pkt_burst = NULL;
1746         eth_dev->tx_pkt_prepare = NULL;
1747
1748         adapter->state = ENA_ADAPTER_STATE_FREE;
1749
1750         return 0;
1751 }
1752
1753 static int ena_dev_configure(struct rte_eth_dev *dev)
1754 {
1755         struct ena_adapter *adapter =
1756                 (struct ena_adapter *)(dev->data->dev_private);
1757
1758         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1759
1760         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1761         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1762         return 0;
1763 }
1764
1765 static void ena_init_rings(struct ena_adapter *adapter)
1766 {
1767         int i;
1768
1769         for (i = 0; i < adapter->num_queues; i++) {
1770                 struct ena_ring *ring = &adapter->tx_ring[i];
1771
1772                 ring->configured = 0;
1773                 ring->type = ENA_RING_TYPE_TX;
1774                 ring->adapter = adapter;
1775                 ring->id = i;
1776                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1777                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1778                 ring->sgl_size = adapter->max_tx_sgl_size;
1779         }
1780
1781         for (i = 0; i < adapter->num_queues; i++) {
1782                 struct ena_ring *ring = &adapter->rx_ring[i];
1783
1784                 ring->configured = 0;
1785                 ring->type = ENA_RING_TYPE_RX;
1786                 ring->adapter = adapter;
1787                 ring->id = i;
1788         }
1789 }
1790
1791 static void ena_infos_get(struct rte_eth_dev *dev,
1792                           struct rte_eth_dev_info *dev_info)
1793 {
1794         struct ena_adapter *adapter;
1795         struct ena_com_dev *ena_dev;
1796         struct ena_com_dev_get_features_ctx feat;
1797         uint64_t rx_feat = 0, tx_feat = 0;
1798         int rc = 0;
1799
1800         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1801         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1802         adapter = (struct ena_adapter *)(dev->data->dev_private);
1803
1804         ena_dev = &adapter->ena_dev;
1805         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1806
1807         dev_info->speed_capa =
1808                         ETH_LINK_SPEED_1G   |
1809                         ETH_LINK_SPEED_2_5G |
1810                         ETH_LINK_SPEED_5G   |
1811                         ETH_LINK_SPEED_10G  |
1812                         ETH_LINK_SPEED_25G  |
1813                         ETH_LINK_SPEED_40G  |
1814                         ETH_LINK_SPEED_50G  |
1815                         ETH_LINK_SPEED_100G;
1816
1817         /* Get supported features from HW */
1818         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1819         if (unlikely(rc)) {
1820                 RTE_LOG(ERR, PMD,
1821                         "Cannot get attribute for ena device rc= %d\n", rc);
1822                 return;
1823         }
1824
1825         /* Set Tx & Rx features available for device */
1826         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1827                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1828
1829         if (feat.offload.tx &
1830             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1831                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1832                         DEV_TX_OFFLOAD_UDP_CKSUM |
1833                         DEV_TX_OFFLOAD_TCP_CKSUM;
1834
1835         if (feat.offload.rx_supported &
1836             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1837                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1838                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1839                         DEV_RX_OFFLOAD_TCP_CKSUM;
1840
1841         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1842
1843         /* Inform framework about available features */
1844         dev_info->rx_offload_capa = rx_feat;
1845         dev_info->rx_queue_offload_capa = rx_feat;
1846         dev_info->tx_offload_capa = tx_feat;
1847         dev_info->tx_queue_offload_capa = tx_feat;
1848
1849         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1850         dev_info->max_rx_pktlen  = adapter->max_mtu;
1851         dev_info->max_mac_addrs = 1;
1852
1853         dev_info->max_rx_queues = adapter->num_queues;
1854         dev_info->max_tx_queues = adapter->num_queues;
1855         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1856
1857         adapter->tx_supported_offloads = tx_feat;
1858         adapter->rx_supported_offloads = rx_feat;
1859
1860         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1861         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1862
1863         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1864         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1865         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1866                                         feat.max_queues.max_packet_tx_descs);
1867         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1868                                         feat.max_queues.max_packet_tx_descs);
1869 }
1870
1871 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1872                                   uint16_t nb_pkts)
1873 {
1874         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1875         unsigned int ring_size = rx_ring->ring_size;
1876         unsigned int ring_mask = ring_size - 1;
1877         uint16_t next_to_clean = rx_ring->next_to_clean;
1878         uint16_t desc_in_use = 0;
1879         uint16_t req_id;
1880         unsigned int recv_idx = 0;
1881         struct rte_mbuf *mbuf = NULL;
1882         struct rte_mbuf *mbuf_head = NULL;
1883         struct rte_mbuf *mbuf_prev = NULL;
1884         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1885         unsigned int completed;
1886
1887         struct ena_com_rx_ctx ena_rx_ctx;
1888         int rc = 0;
1889
1890         /* Check adapter state */
1891         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1892                 RTE_LOG(ALERT, PMD,
1893                         "Trying to receive pkts while device is NOT running\n");
1894                 return 0;
1895         }
1896
1897         desc_in_use = rx_ring->next_to_use - next_to_clean;
1898         if (unlikely(nb_pkts > desc_in_use))
1899                 nb_pkts = desc_in_use;
1900
1901         for (completed = 0; completed < nb_pkts; completed++) {
1902                 int segments = 0;
1903
1904                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1905                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1906                 ena_rx_ctx.descs = 0;
1907                 /* receive packet context */
1908                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1909                                     rx_ring->ena_com_io_sq,
1910                                     &ena_rx_ctx);
1911                 if (unlikely(rc)) {
1912                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1913                         rx_ring->adapter->reset_reason =
1914                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1915                         rx_ring->adapter->trigger_reset = true;
1916                         return 0;
1917                 }
1918
1919                 if (unlikely(ena_rx_ctx.descs == 0))
1920                         break;
1921
1922                 while (segments < ena_rx_ctx.descs) {
1923                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1924                         rc = validate_rx_req_id(rx_ring, req_id);
1925                         if (unlikely(rc))
1926                                 break;
1927
1928                         mbuf = rx_buff_info[req_id];
1929                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1930                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1931                         mbuf->refcnt = 1;
1932                         mbuf->next = NULL;
1933                         if (unlikely(segments == 0)) {
1934                                 mbuf->nb_segs = ena_rx_ctx.descs;
1935                                 mbuf->port = rx_ring->port_id;
1936                                 mbuf->pkt_len = 0;
1937                                 mbuf_head = mbuf;
1938                         } else {
1939                                 /* for multi-segment pkts create mbuf chain */
1940                                 mbuf_prev->next = mbuf;
1941                         }
1942                         mbuf_head->pkt_len += mbuf->data_len;
1943
1944                         mbuf_prev = mbuf;
1945                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1946                                 req_id;
1947                         segments++;
1948                         next_to_clean++;
1949                 }
1950
1951                 /* fill mbuf attributes if any */
1952                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1953                 mbuf_head->hash.rss = ena_rx_ctx.hash;
1954
1955                 /* pass to DPDK application head mbuf */
1956                 rx_pkts[recv_idx] = mbuf_head;
1957                 recv_idx++;
1958         }
1959
1960         rx_ring->next_to_clean = next_to_clean;
1961
1962         desc_in_use = desc_in_use - completed + 1;
1963         /* Burst refill to save doorbells, memory barriers, const interval */
1964         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1965                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1966
1967         return recv_idx;
1968 }
1969
1970 static uint16_t
1971 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1972                 uint16_t nb_pkts)
1973 {
1974         int32_t ret;
1975         uint32_t i;
1976         struct rte_mbuf *m;
1977         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1978         struct ipv4_hdr *ip_hdr;
1979         uint64_t ol_flags;
1980         uint16_t frag_field;
1981
1982         for (i = 0; i != nb_pkts; i++) {
1983                 m = tx_pkts[i];
1984                 ol_flags = m->ol_flags;
1985
1986                 if (!(ol_flags & PKT_TX_IPV4))
1987                         continue;
1988
1989                 /* If there was not L2 header length specified, assume it is
1990                  * length of the ethernet header.
1991                  */
1992                 if (unlikely(m->l2_len == 0))
1993                         m->l2_len = sizeof(struct ether_hdr);
1994
1995                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1996                                                  m->l2_len);
1997                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1998
1999                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2000                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2001
2002                         /* If IPv4 header has DF flag enabled and TSO support is
2003                          * disabled, partial chcecksum should not be calculated.
2004                          */
2005                         if (!tx_ring->adapter->tso4_supported)
2006                                 continue;
2007                 }
2008
2009                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2010                                 (ol_flags & PKT_TX_L4_MASK) ==
2011                                 PKT_TX_SCTP_CKSUM) {
2012                         rte_errno = -ENOTSUP;
2013                         return i;
2014                 }
2015
2016 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2017                 ret = rte_validate_tx_offload(m);
2018                 if (ret != 0) {
2019                         rte_errno = ret;
2020                         return i;
2021                 }
2022 #endif
2023
2024                 /* In case we are supposed to TSO and have DF not set (DF=0)
2025                  * hardware must be provided with partial checksum, otherwise
2026                  * it will take care of necessary calculations.
2027                  */
2028
2029                 ret = rte_net_intel_cksum_flags_prepare(m,
2030                         ol_flags & ~PKT_TX_TCP_SEG);
2031                 if (ret != 0) {
2032                         rte_errno = ret;
2033                         return i;
2034                 }
2035         }
2036
2037         return i;
2038 }
2039
2040 static void ena_update_hints(struct ena_adapter *adapter,
2041                              struct ena_admin_ena_hw_hints *hints)
2042 {
2043         if (hints->admin_completion_tx_timeout)
2044                 adapter->ena_dev.admin_queue.completion_timeout =
2045                         hints->admin_completion_tx_timeout * 1000;
2046
2047         if (hints->mmio_read_timeout)
2048                 /* convert to usec */
2049                 adapter->ena_dev.mmio_read.reg_read_to =
2050                         hints->mmio_read_timeout * 1000;
2051
2052         if (hints->driver_watchdog_timeout) {
2053                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2054                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2055                 else
2056                         // Convert msecs to ticks
2057                         adapter->keep_alive_timeout =
2058                                 (hints->driver_watchdog_timeout *
2059                                 rte_get_timer_hz()) / 1000;
2060         }
2061 }
2062
2063 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2064                                         struct rte_mbuf *mbuf)
2065 {
2066         int num_segments, rc;
2067
2068         num_segments = mbuf->nb_segs;
2069
2070         if (likely(num_segments < tx_ring->sgl_size))
2071                 return 0;
2072
2073         rc = rte_pktmbuf_linearize(mbuf);
2074         if (unlikely(rc))
2075                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2076
2077         return rc;
2078 }
2079
2080 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2081                                   uint16_t nb_pkts)
2082 {
2083         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2084         uint16_t next_to_use = tx_ring->next_to_use;
2085         uint16_t next_to_clean = tx_ring->next_to_clean;
2086         struct rte_mbuf *mbuf;
2087         unsigned int ring_size = tx_ring->ring_size;
2088         unsigned int ring_mask = ring_size - 1;
2089         struct ena_com_tx_ctx ena_tx_ctx;
2090         struct ena_tx_buffer *tx_info;
2091         struct ena_com_buf *ebuf;
2092         uint16_t rc, req_id, total_tx_descs = 0;
2093         uint16_t sent_idx = 0, empty_tx_reqs;
2094         int nb_hw_desc;
2095
2096         /* Check adapter state */
2097         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2098                 RTE_LOG(ALERT, PMD,
2099                         "Trying to xmit pkts while device is NOT running\n");
2100                 return 0;
2101         }
2102
2103         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2104         if (nb_pkts > empty_tx_reqs)
2105                 nb_pkts = empty_tx_reqs;
2106
2107         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2108                 mbuf = tx_pkts[sent_idx];
2109
2110                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2111                 if (unlikely(rc))
2112                         break;
2113
2114                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2115                 tx_info = &tx_ring->tx_buffer_info[req_id];
2116                 tx_info->mbuf = mbuf;
2117                 tx_info->num_of_bufs = 0;
2118                 ebuf = tx_info->bufs;
2119
2120                 /* Prepare TX context */
2121                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2122                 memset(&ena_tx_ctx.ena_meta, 0x0,
2123                        sizeof(struct ena_com_tx_meta));
2124                 ena_tx_ctx.ena_bufs = ebuf;
2125                 ena_tx_ctx.req_id = req_id;
2126                 if (tx_ring->tx_mem_queue_type ==
2127                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2128                         /* prepare the push buffer with
2129                          * virtual address of the data
2130                          */
2131                         ena_tx_ctx.header_len =
2132                                 RTE_MIN(mbuf->data_len,
2133                                         tx_ring->tx_max_header_size);
2134                         ena_tx_ctx.push_header =
2135                                 (void *)((char *)mbuf->buf_addr +
2136                                          mbuf->data_off);
2137                 } /* there's no else as we take advantage of memset zeroing */
2138
2139                 /* Set TX offloads flags, if applicable */
2140                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2141
2142                 if (unlikely(mbuf->ol_flags &
2143                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2144                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2145
2146                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2147
2148                 /* Process first segment taking into
2149                  * consideration pushed header
2150                  */
2151                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2152                         ebuf->paddr = mbuf->buf_iova +
2153                                       mbuf->data_off +
2154                                       ena_tx_ctx.header_len;
2155                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2156                         ebuf++;
2157                         tx_info->num_of_bufs++;
2158                 }
2159
2160                 while ((mbuf = mbuf->next) != NULL) {
2161                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2162                         ebuf->len = mbuf->data_len;
2163                         ebuf++;
2164                         tx_info->num_of_bufs++;
2165                 }
2166
2167                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2168
2169                 /* Write data to device */
2170                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2171                                         &ena_tx_ctx, &nb_hw_desc);
2172                 if (unlikely(rc))
2173                         break;
2174
2175                 tx_info->tx_descs = nb_hw_desc;
2176
2177                 next_to_use++;
2178         }
2179
2180         /* If there are ready packets to be xmitted... */
2181         if (sent_idx > 0) {
2182                 /* ...let HW do its best :-) */
2183                 rte_wmb();
2184                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2185
2186                 tx_ring->next_to_use = next_to_use;
2187         }
2188
2189         /* Clear complete packets  */
2190         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2191                 rc = validate_tx_req_id(tx_ring, req_id);
2192                 if (rc)
2193                         break;
2194
2195                 /* Get Tx info & store how many descs were processed  */
2196                 tx_info = &tx_ring->tx_buffer_info[req_id];
2197                 total_tx_descs += tx_info->tx_descs;
2198
2199                 /* Free whole mbuf chain  */
2200                 mbuf = tx_info->mbuf;
2201                 rte_pktmbuf_free(mbuf);
2202                 tx_info->mbuf = NULL;
2203
2204                 /* Put back descriptor to the ring for reuse */
2205                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2206                 next_to_clean++;
2207
2208                 /* If too many descs to clean, leave it for another run */
2209                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2210                         break;
2211         }
2212
2213         if (total_tx_descs > 0) {
2214                 /* acknowledge completion of sent packets */
2215                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2216                 tx_ring->next_to_clean = next_to_clean;
2217         }
2218
2219         return sent_idx;
2220 }
2221
2222 /*********************************************************************
2223  *  PMD configuration
2224  *********************************************************************/
2225 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2226         struct rte_pci_device *pci_dev)
2227 {
2228         return rte_eth_dev_pci_generic_probe(pci_dev,
2229                 sizeof(struct ena_adapter), eth_ena_dev_init);
2230 }
2231
2232 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2233 {
2234         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2235 }
2236
2237 static struct rte_pci_driver rte_ena_pmd = {
2238         .id_table = pci_id_ena_map,
2239         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2240                      RTE_PCI_DRV_WC_ACTIVATE,
2241         .probe = eth_ena_pci_probe,
2242         .remove = eth_ena_pci_remove,
2243 };
2244
2245 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2246 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2247 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2248
2249 RTE_INIT(ena_init_log)
2250 {
2251         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2252         if (ena_logtype_init >= 0)
2253                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2254         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2255         if (ena_logtype_driver >= 0)
2256                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2257 }
2258
2259 /******************************************************************************
2260  ******************************** AENQ Handlers *******************************
2261  *****************************************************************************/
2262 static void ena_update_on_link_change(void *adapter_data,
2263                                       struct ena_admin_aenq_entry *aenq_e)
2264 {
2265         struct rte_eth_dev *eth_dev;
2266         struct ena_adapter *adapter;
2267         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2268         uint32_t status;
2269
2270         adapter = (struct ena_adapter *)adapter_data;
2271         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2272         eth_dev = adapter->rte_dev;
2273
2274         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2275         adapter->link_status = status;
2276
2277         ena_link_update(eth_dev, 0);
2278         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2279 }
2280
2281 static void ena_notification(void *data,
2282                              struct ena_admin_aenq_entry *aenq_e)
2283 {
2284         struct ena_adapter *adapter = (struct ena_adapter *)data;
2285         struct ena_admin_ena_hw_hints *hints;
2286
2287         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2288                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2289                         aenq_e->aenq_common_desc.group,
2290                         ENA_ADMIN_NOTIFICATION);
2291
2292         switch (aenq_e->aenq_common_desc.syndrom) {
2293         case ENA_ADMIN_UPDATE_HINTS:
2294                 hints = (struct ena_admin_ena_hw_hints *)
2295                         (&aenq_e->inline_data_w4);
2296                 ena_update_hints(adapter, hints);
2297                 break;
2298         default:
2299                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2300                         aenq_e->aenq_common_desc.syndrom);
2301         }
2302 }
2303
2304 static void ena_keep_alive(void *adapter_data,
2305                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2306 {
2307         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2308
2309         adapter->timestamp_wd = rte_get_timer_cycles();
2310 }
2311
2312 /**
2313  * This handler will called for unknown event group or unimplemented handlers
2314  **/
2315 static void unimplemented_aenq_handler(__rte_unused void *data,
2316                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2317 {
2318         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2319                           "unimplemented handler\n");
2320 }
2321
2322 static struct ena_aenq_handlers aenq_handlers = {
2323         .handlers = {
2324                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2325                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2326                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2327         },
2328         .unimplemented_handler = unimplemented_aenq_handler
2329 };