drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MAX_RING_DESC       ENA_DEFAULT_RING_SIZE
  89 #define ENA_MIN_RING_DESC       128
  90
  91 enum ethtool_stringset {
  92         ETH_SS_TEST             = 0,
  93         ETH_SS_STATS,
  94 };
  95
  96 struct ena_stats {
  97         char name[ETH_GSTRING_LEN];
  98         int stat_offset;
  99 };
 100
 101 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 102         .name = #stat, \
 103         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 104 }
 105
 106 #define ENA_STAT_ENTRY(stat, stat_type) { \
 107         .name = #stat, \
 108         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 109 }
 110
 111 #define ENA_STAT_RX_ENTRY(stat) \
 112         ENA_STAT_ENTRY(stat, rx)
 113
 114 #define ENA_STAT_TX_ENTRY(stat) \
 115         ENA_STAT_ENTRY(stat, tx)
 116
 117 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 118         ENA_STAT_ENTRY(stat, dev)
 119
 120 /*
 121  * Each rte_memzone should have unique name.
 122  * To satisfy it, count number of allocation and add it to name.
 123  */
 124 uint32_t ena_alloc_cnt;
 125
 126 static const struct ena_stats ena_stats_global_strings[] = {
 127         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 128         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 129         ENA_STAT_GLOBAL_ENTRY(io_resume),
 130         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 131         ENA_STAT_GLOBAL_ENTRY(interface_up),
 132         ENA_STAT_GLOBAL_ENTRY(interface_down),
 133         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 134 };
 135
 136 static const struct ena_stats ena_stats_tx_strings[] = {
 137         ENA_STAT_TX_ENTRY(cnt),
 138         ENA_STAT_TX_ENTRY(bytes),
 139         ENA_STAT_TX_ENTRY(queue_stop),
 140         ENA_STAT_TX_ENTRY(queue_wakeup),
 141         ENA_STAT_TX_ENTRY(dma_mapping_err),
 142         ENA_STAT_TX_ENTRY(linearize),
 143         ENA_STAT_TX_ENTRY(linearize_failed),
 144         ENA_STAT_TX_ENTRY(tx_poll),
 145         ENA_STAT_TX_ENTRY(doorbells),
 146         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 147         ENA_STAT_TX_ENTRY(missing_tx_comp),
 148         ENA_STAT_TX_ENTRY(bad_req_id),
 149 };
 150
 151 static const struct ena_stats ena_stats_rx_strings[] = {
 152         ENA_STAT_RX_ENTRY(cnt),
 153         ENA_STAT_RX_ENTRY(bytes),
 154         ENA_STAT_RX_ENTRY(refil_partial),
 155         ENA_STAT_RX_ENTRY(bad_csum),
 156         ENA_STAT_RX_ENTRY(page_alloc_fail),
 157         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 158         ENA_STAT_RX_ENTRY(dma_mapping_err),
 159         ENA_STAT_RX_ENTRY(bad_desc_num),
 160         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 161 };
 162
 163 static const struct ena_stats ena_stats_ena_com_strings[] = {
 164         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 168         ENA_STAT_ENA_COM_ENTRY(no_completion),
 169 };
 170
 171 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 172 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 173 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 174 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 175
 176 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 177                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 178                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 179                         DEV_TX_OFFLOAD_TCP_TSO)
 180 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 181                        PKT_TX_IP_CKSUM |\
 182                        PKT_TX_TCP_SEG)
 183
 184 /** Vendor ID used by Amazon devices */
 185 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 186 /** Amazon devices */
 187 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 188 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 189
 190 #define ENA_TX_OFFLOAD_MASK     (\
 191         PKT_TX_L4_MASK |         \
 192         PKT_TX_IPV6 |            \
 193         PKT_TX_IPV4 |            \
 194         PKT_TX_IP_CKSUM |        \
 195         PKT_TX_TCP_SEG)
 196
 197 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 198         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 199
 200 int ena_logtype_init;
 201 int ena_logtype_driver;
 202
 203 static const struct rte_pci_id pci_id_ena_map[] = {
 204         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 205         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 206         { .device_id = 0 },
 207 };
 208
 209 static struct ena_aenq_handlers aenq_handlers;
 210
 211 static int ena_device_init(struct ena_com_dev *ena_dev,
 212                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 213                            bool *wd_state);
 214 static int ena_dev_configure(struct rte_eth_dev *dev);
 215 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 216                                   uint16_t nb_pkts);
 217 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                 uint16_t nb_pkts);
 219 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 220                               uint16_t nb_desc, unsigned int socket_id,
 221                               const struct rte_eth_txconf *tx_conf);
 222 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 223                               uint16_t nb_desc, unsigned int socket_id,
 224                               const struct rte_eth_rxconf *rx_conf,
 225                               struct rte_mempool *mp);
 226 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 227                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 228 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 229 static void ena_init_rings(struct ena_adapter *adapter);
 230 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 231 static int ena_start(struct rte_eth_dev *dev);
 232 static void ena_stop(struct rte_eth_dev *dev);
 233 static void ena_close(struct rte_eth_dev *dev);
 234 static int ena_dev_reset(struct rte_eth_dev *dev);
 235 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 236 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 237 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 238 static void ena_rx_queue_release(void *queue);
 239 static void ena_tx_queue_release(void *queue);
 240 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 241 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 242 static int ena_link_update(struct rte_eth_dev *dev,
 243                            int wait_to_complete);
 244 static int ena_create_io_queue(struct ena_ring *ring);
 245 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 246 static int ena_queue_restart(struct ena_ring *ring);
 247 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 248                                  enum ena_ring_type ring_type);
 249 static void ena_stats_restart(struct rte_eth_dev *dev);
 250 static void ena_infos_get(struct rte_eth_dev *dev,
 251                           struct rte_eth_dev_info *dev_info);
 252 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 253                                struct rte_eth_rss_reta_entry64 *reta_conf,
 254                                uint16_t reta_size);
 255 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 256                               struct rte_eth_rss_reta_entry64 *reta_conf,
 257                               uint16_t reta_size);
 258 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 259 static void ena_interrupt_handler_rte(void *cb_arg);
 260 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 261
 262 static const struct eth_dev_ops ena_dev_ops = {
 263         .dev_configure        = ena_dev_configure,
 264         .dev_infos_get        = ena_infos_get,
 265         .rx_queue_setup       = ena_rx_queue_setup,
 266         .tx_queue_setup       = ena_tx_queue_setup,
 267         .dev_start            = ena_start,
 268         .dev_stop             = ena_stop,
 269         .link_update          = ena_link_update,
 270         .stats_get            = ena_stats_get,
 271         .mtu_set              = ena_mtu_set,
 272         .rx_queue_release     = ena_rx_queue_release,
 273         .tx_queue_release     = ena_tx_queue_release,
 274         .dev_close            = ena_close,
 275         .dev_reset            = ena_dev_reset,
 276         .reta_update          = ena_rss_reta_update,
 277         .reta_query           = ena_rss_reta_query,
 278 };
 279
 280 #define NUMA_NO_NODE    SOCKET_ID_ANY
 281
 282 static inline int ena_cpu_to_node(int cpu)
 283 {
 284         struct rte_config *config = rte_eal_get_configuration();
 285         struct rte_fbarray *arr = &config->mem_config->memzones;
 286         const struct rte_memzone *mz;
 287
 288         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 289                 return NUMA_NO_NODE;
 290
 291         mz = rte_fbarray_get(arr, cpu);
 292
 293         return mz->socket_id;
 294 }
 295
 296 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 297                                        struct ena_com_rx_ctx *ena_rx_ctx)
 298 {
 299         uint64_t ol_flags = 0;
 300         uint32_t packet_type = 0;
 301
 302         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 303                 packet_type |= RTE_PTYPE_L4_TCP;
 304         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 305                 packet_type |= RTE_PTYPE_L4_UDP;
 306
 307         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 308                 packet_type |= RTE_PTYPE_L3_IPV4;
 309         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 310                 packet_type |= RTE_PTYPE_L3_IPV6;
 311
 312         if (unlikely(ena_rx_ctx->l4_csum_err))
 313                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 314         if (unlikely(ena_rx_ctx->l3_csum_err))
 315                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 316
 317         mbuf->ol_flags = ol_flags;
 318         mbuf->packet_type = packet_type;
 319 }
 320
 321 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 322                                        struct ena_com_tx_ctx *ena_tx_ctx,
 323                                        uint64_t queue_offloads)
 324 {
 325         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 326
 327         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 328             (queue_offloads & QUEUE_OFFLOADS)) {
 329                 /* check if TSO is required */
 330                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 331                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 332                         ena_tx_ctx->tso_enable = true;
 333
 334                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 335                 }
 336
 337                 /* check if L3 checksum is needed */
 338                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 339                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 340                         ena_tx_ctx->l3_csum_enable = true;
 341
 342                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 343                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 344                 } else {
 345                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 346
 347                         /* set don't fragment (DF) flag */
 348                         if (mbuf->packet_type &
 349                                 (RTE_PTYPE_L4_NONFRAG
 350                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 351                                 ena_tx_ctx->df = true;
 352                 }
 353
 354                 /* check if L4 checksum is needed */
 355                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 356                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 357                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 358                         ena_tx_ctx->l4_csum_enable = true;
 359                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 360                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 361                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 362                         ena_tx_ctx->l4_csum_enable = true;
 363                 } else {
 364                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 365                         ena_tx_ctx->l4_csum_enable = false;
 366                 }
 367
 368                 ena_meta->mss = mbuf->tso_segsz;
 369                 ena_meta->l3_hdr_len = mbuf->l3_len;
 370                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 371
 372                 ena_tx_ctx->meta_valid = true;
 373         } else {
 374                 ena_tx_ctx->meta_valid = false;
 375         }
 376 }
 377
 378 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 379 {
 380         if (likely(req_id < rx_ring->ring_size))
 381                 return 0;
 382
 383         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 384
 385         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 386         rx_ring->adapter->trigger_reset = true;
 387
 388         return -EFAULT;
 389 }
 390
 391 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 392 {
 393         struct ena_tx_buffer *tx_info = NULL;
 394
 395         if (likely(req_id < tx_ring->ring_size)) {
 396                 tx_info = &tx_ring->tx_buffer_info[req_id];
 397                 if (likely(tx_info->mbuf))
 398                         return 0;
 399         }
 400
 401         if (tx_info)
 402                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 403         else
 404                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 405
 406         /* Trigger device reset */
 407         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 408         tx_ring->adapter->trigger_reset = true;
 409         return -EFAULT;
 410 }
 411
 412 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 413 {
 414         struct ena_admin_host_info *host_info;
 415         int rc;
 416
 417         /* Allocate only the host info */
 418         rc = ena_com_allocate_host_info(ena_dev);
 419         if (rc) {
 420                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 421                 return;
 422         }
 423
 424         host_info = ena_dev->host_attr.host_info;
 425
 426         host_info->os_type = ENA_ADMIN_OS_DPDK;
 427         host_info->kernel_ver = RTE_VERSION;
 428         snprintf((char *)host_info->kernel_ver_str,
 429                  sizeof(host_info->kernel_ver_str),
 430                  "%s", rte_version());
 431         host_info->os_dist = RTE_VERSION;
 432         snprintf((char *)host_info->os_dist_str,
 433                  sizeof(host_info->os_dist_str),
 434                  "%s", rte_version());
 435         host_info->driver_version =
 436                 (DRV_MODULE_VER_MAJOR) |
 437                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 438                 (DRV_MODULE_VER_SUBMINOR <<
 439                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 440
 441         rc = ena_com_set_host_attributes(ena_dev);
 442         if (rc) {
 443                 if (rc == -ENA_COM_UNSUPPORTED)
 444                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 445                 else
 446                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 447
 448                 goto err;
 449         }
 450
 451         return;
 452
 453 err:
 454         ena_com_delete_host_info(ena_dev);
 455 }
 456
 457 static int
 458 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 459 {
 460         if (sset != ETH_SS_STATS)
 461                 return -EOPNOTSUPP;
 462
 463          /* Workaround for clang:
 464          * touch internal structures to prevent
 465          * compiler error
 466          */
 467         ENA_TOUCH(ena_stats_global_strings);
 468         ENA_TOUCH(ena_stats_tx_strings);
 469         ENA_TOUCH(ena_stats_rx_strings);
 470         ENA_TOUCH(ena_stats_ena_com_strings);
 471
 472         return  dev->data->nb_tx_queues *
 473                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 474                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 475 }
 476
 477 static void ena_config_debug_area(struct ena_adapter *adapter)
 478 {
 479         u32 debug_area_size;
 480         int rc, ss_count;
 481
 482         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 483         if (ss_count <= 0) {
 484                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 485                 return;
 486         }
 487
 488         /* allocate 32 bytes for each string and 64bit for the value */
 489         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 490
 491         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 492         if (rc) {
 493                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 494                 return;
 495         }
 496
 497         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 498         if (rc) {
 499                 if (rc == -ENA_COM_UNSUPPORTED)
 500                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 501                 else
 502                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 503
 504                 goto err;
 505         }
 506
 507         return;
 508 err:
 509         ena_com_delete_debug_area(&adapter->ena_dev);
 510 }
 511
 512 static void ena_close(struct rte_eth_dev *dev)
 513 {
 514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 515         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 516         struct ena_adapter *adapter =
 517                 (struct ena_adapter *)(dev->data->dev_private);
 518
 519         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 520                 ena_stop(dev);
 521         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 522
 523         ena_rx_queue_release_all(dev);
 524         ena_tx_queue_release_all(dev);
 525
 526         rte_free(adapter->drv_stats);
 527         adapter->drv_stats = NULL;
 528
 529         rte_intr_disable(intr_handle);
 530         rte_intr_callback_unregister(intr_handle,
 531                                      ena_interrupt_handler_rte,
 532                                      adapter);
 533
 534         /*
 535          * MAC is not allocated dynamically. Setting NULL should prevent from
 536          * release of the resource in the rte_eth_dev_release_port().
 537          */
 538         dev->data->mac_addrs = NULL;
 539 }
 540
 541 static int
 542 ena_dev_reset(struct rte_eth_dev *dev)
 543 {
 544         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 545         struct rte_eth_dev *eth_dev;
 546         struct rte_pci_device *pci_dev;
 547         struct rte_intr_handle *intr_handle;
 548         struct ena_com_dev *ena_dev;
 549         struct ena_com_dev_get_features_ctx get_feat_ctx;
 550         struct ena_adapter *adapter;
 551         int nb_queues;
 552         int rc, i;
 553         bool wd_state;
 554
 555         adapter = (struct ena_adapter *)(dev->data->dev_private);
 556         ena_dev = &adapter->ena_dev;
 557         eth_dev = adapter->rte_dev;
 558         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 559         intr_handle = &pci_dev->intr_handle;
 560         nb_queues = eth_dev->data->nb_rx_queues;
 561
 562         ena_com_set_admin_running_state(ena_dev, false);
 563
 564         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 565         if (rc)
 566                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 567
 568         for (i = 0; i < nb_queues; i++)
 569                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 570
 571         ena_rx_queue_release_all(eth_dev);
 572         ena_tx_queue_release_all(eth_dev);
 573
 574         rte_intr_disable(intr_handle);
 575
 576         ena_com_abort_admin_commands(ena_dev);
 577         ena_com_wait_for_abort_completion(ena_dev);
 578         ena_com_admin_destroy(ena_dev);
 579         ena_com_mmio_reg_read_request_destroy(ena_dev);
 580
 581         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 582         if (rc) {
 583                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 584                 return rc;
 585         }
 586         adapter->wd_state = wd_state;
 587
 588         rte_intr_enable(intr_handle);
 589         ena_com_set_admin_polling_mode(ena_dev, false);
 590         ena_com_admin_aenq_enable(ena_dev);
 591
 592         for (i = 0; i < nb_queues; ++i)
 593                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring_size, 0, NULL,
 594                         mb_pool_rx[i]);
 595
 596         for (i = 0; i < nb_queues; ++i)
 597                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring_size, 0, NULL);
 598
 599         adapter->trigger_reset = false;
 600
 601         return 0;
 602 }
 603
 604 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 605                                struct rte_eth_rss_reta_entry64 *reta_conf,
 606                                uint16_t reta_size)
 607 {
 608         struct ena_adapter *adapter =
 609                 (struct ena_adapter *)(dev->data->dev_private);
 610         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 611         int rc, i;
 612         u16 entry_value;
 613         int conf_idx;
 614         int idx;
 615
 616         if ((reta_size == 0) || (reta_conf == NULL))
 617                 return -EINVAL;
 618
 619         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 620                 RTE_LOG(WARNING, PMD,
 621                         "indirection table %d is bigger than supported (%d)\n",
 622                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 623                 return -EINVAL;
 624         }
 625
 626         for (i = 0 ; i < reta_size ; i++) {
 627                 /* each reta_conf is for 64 entries.
 628                  * to support 128 we use 2 conf of 64
 629                  */
 630                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 631                 idx = i % RTE_RETA_GROUP_SIZE;
 632                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 633                         entry_value =
 634                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 635
 636                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 637                                                                i,
 638                                                                entry_value);
 639                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 640                                 RTE_LOG(ERR, PMD,
 641                                         "Cannot fill indirect table\n");
 642                                 return rc;
 643                         }
 644                 }
 645         }
 646
 647         rc = ena_com_indirect_table_set(ena_dev);
 648         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 649                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 650                 return rc;
 651         }
 652
 653         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 654                 __func__, reta_size, adapter->rte_dev->data->port_id);
 655
 656         return 0;
 657 }
 658
 659 /* Query redirection table. */
 660 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 661                               struct rte_eth_rss_reta_entry64 *reta_conf,
 662                               uint16_t reta_size)
 663 {
 664         struct ena_adapter *adapter =
 665                 (struct ena_adapter *)(dev->data->dev_private);
 666         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 667         int rc;
 668         int i;
 669         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 670         int reta_conf_idx;
 671         int reta_idx;
 672
 673         if (reta_size == 0 || reta_conf == NULL ||
 674             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 675                 return -EINVAL;
 676
 677         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 678         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 679                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 680                 return -ENOTSUP;
 681         }
 682
 683         for (i = 0 ; i < reta_size ; i++) {
 684                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 685                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 686                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 687                         reta_conf[reta_conf_idx].reta[reta_idx] =
 688                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 689         }
 690
 691         return 0;
 692 }
 693
 694 static int ena_rss_init_default(struct ena_adapter *adapter)
 695 {
 696         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 697         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 698         int rc, i;
 699         u32 val;
 700
 701         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 702         if (unlikely(rc)) {
 703                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 704                 goto err_rss_init;
 705         }
 706
 707         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 708                 val = i % nb_rx_queues;
 709                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 710                                                        ENA_IO_RXQ_IDX(val));
 711                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 712                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 713                         goto err_fill_indir;
 714                 }
 715         }
 716
 717         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 718                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 719         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 720                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 721                 goto err_fill_indir;
 722         }
 723
 724         rc = ena_com_set_default_hash_ctrl(ena_dev);
 725         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 726                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 727                 goto err_fill_indir;
 728         }
 729
 730         rc = ena_com_indirect_table_set(ena_dev);
 731         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 732                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 733                 goto err_fill_indir;
 734         }
 735         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 736                 adapter->rte_dev->data->port_id);
 737
 738         return 0;
 739
 740 err_fill_indir:
 741         ena_com_rss_destroy(ena_dev);
 742 err_rss_init:
 743
 744         return rc;
 745 }
 746
 747 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 748 {
 749         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 750         int nb_queues = dev->data->nb_rx_queues;
 751         int i;
 752
 753         for (i = 0; i < nb_queues; i++)
 754                 ena_rx_queue_release(queues[i]);
 755 }
 756
 757 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 758 {
 759         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 760         int nb_queues = dev->data->nb_tx_queues;
 761         int i;
 762
 763         for (i = 0; i < nb_queues; i++)
 764                 ena_tx_queue_release(queues[i]);
 765 }
 766
 767 static void ena_rx_queue_release(void *queue)
 768 {
 769         struct ena_ring *ring = (struct ena_ring *)queue;
 770
 771         ena_assert_msg(ring->configured,
 772                        "API violation - releasing not configured queue");
 773         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 774                        "API violation");
 775
 776         /* Free ring resources */
 777         if (ring->rx_buffer_info)
 778                 rte_free(ring->rx_buffer_info);
 779         ring->rx_buffer_info = NULL;
 780
 781         if (ring->rx_refill_buffer)
 782                 rte_free(ring->rx_refill_buffer);
 783         ring->rx_refill_buffer = NULL;
 784
 785         if (ring->empty_rx_reqs)
 786                 rte_free(ring->empty_rx_reqs);
 787         ring->empty_rx_reqs = NULL;
 788
 789         ring->configured = 0;
 790
 791         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 792                 ring->port_id, ring->id);
 793 }
 794
 795 static void ena_tx_queue_release(void *queue)
 796 {
 797         struct ena_ring *ring = (struct ena_ring *)queue;
 798
 799         ena_assert_msg(ring->configured,
 800                        "API violation. Releasing not configured queue");
 801         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 802                        "API violation");
 803
 804         /* Free all bufs */
 805         ena_tx_queue_release_bufs(ring);
 806
 807         /* Free ring resources */
 808         if (ring->tx_buffer_info)
 809                 rte_free(ring->tx_buffer_info);
 810
 811         if (ring->empty_tx_reqs)
 812                 rte_free(ring->empty_tx_reqs);
 813
 814         ring->empty_tx_reqs = NULL;
 815         ring->tx_buffer_info = NULL;
 816
 817         ring->configured = 0;
 818
 819         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 820                 ring->port_id, ring->id);
 821 }
 822
 823 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 824 {
 825         unsigned int ring_mask = ring->ring_size - 1;
 826
 827         while (ring->next_to_clean != ring->next_to_use) {
 828                 struct rte_mbuf *m =
 829                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 830
 831                 if (m)
 832                         rte_mbuf_raw_free(m);
 833
 834                 ring->next_to_clean++;
 835         }
 836 }
 837
 838 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 839 {
 840         unsigned int i;
 841
 842         for (i = 0; i < ring->ring_size; ++i) {
 843                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 844
 845                 if (tx_buf->mbuf)
 846                         rte_pktmbuf_free(tx_buf->mbuf);
 847
 848                 ring->next_to_clean++;
 849         }
 850 }
 851
 852 static int ena_link_update(struct rte_eth_dev *dev,
 853                            __rte_unused int wait_to_complete)
 854 {
 855         struct rte_eth_link *link = &dev->data->dev_link;
 856         struct ena_adapter *adapter;
 857
 858         adapter = (struct ena_adapter *)(dev->data->dev_private);
 859
 860         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 861         link->link_speed = ETH_SPEED_NUM_NONE;
 862         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 863
 864         return 0;
 865 }
 866
 867 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 868                                  enum ena_ring_type ring_type)
 869 {
 870         struct ena_adapter *adapter =
 871                 (struct ena_adapter *)(dev->data->dev_private);
 872         struct ena_ring *queues = NULL;
 873         int nb_queues;
 874         int i = 0;
 875         int rc = 0;
 876
 877         if (ring_type == ENA_RING_TYPE_RX) {
 878                 queues = adapter->rx_ring;
 879                 nb_queues = dev->data->nb_rx_queues;
 880         } else {
 881                 queues = adapter->tx_ring;
 882                 nb_queues = dev->data->nb_tx_queues;
 883         }
 884         for (i = 0; i < nb_queues; i++) {
 885                 if (queues[i].configured) {
 886                         if (ring_type == ENA_RING_TYPE_RX) {
 887                                 ena_assert_msg(
 888                                         dev->data->rx_queues[i] == &queues[i],
 889                                         "Inconsistent state of rx queues\n");
 890                         } else {
 891                                 ena_assert_msg(
 892                                         dev->data->tx_queues[i] == &queues[i],
 893                                         "Inconsistent state of tx queues\n");
 894                         }
 895
 896                         rc = ena_queue_restart(&queues[i]);
 897
 898                         if (rc) {
 899                                 PMD_INIT_LOG(ERR,
 900                                              "failed to restart queue %d type(%d)",
 901                                              i, ring_type);
 902                                 return rc;
 903                         }
 904                 }
 905         }
 906
 907         return 0;
 908 }
 909
 910 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 911 {
 912         uint32_t max_frame_len = adapter->max_mtu;
 913
 914         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 915             DEV_RX_OFFLOAD_JUMBO_FRAME)
 916                 max_frame_len =
 917                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 918
 919         return max_frame_len;
 920 }
 921
 922 static int ena_check_valid_conf(struct ena_adapter *adapter)
 923 {
 924         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 925
 926         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 927                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 928                                   "max mtu: %d, min mtu: %d\n",
 929                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 930                 return ENA_COM_UNSUPPORTED;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static int
 937 ena_calc_queue_size(struct ena_com_dev *ena_dev,
 938                     u16 *max_tx_sgl_size,
 939                     struct ena_com_dev_get_features_ctx *get_feat_ctx)
 940 {
 941         uint32_t queue_size = ENA_DEFAULT_RING_SIZE;
 942
 943         queue_size = RTE_MIN(queue_size,
 944                              get_feat_ctx->max_queues.max_cq_depth);
 945         queue_size = RTE_MIN(queue_size,
 946                              get_feat_ctx->max_queues.max_sq_depth);
 947
 948         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
 949                 queue_size = RTE_MIN(queue_size,
 950                                      get_feat_ctx->max_queues.max_legacy_llq_depth);
 951
 952         /* Round down to power of 2 */
 953         if (!rte_is_power_of_2(queue_size))
 954                 queue_size = rte_align32pow2(queue_size >> 1);
 955
 956         if (unlikely(queue_size == 0)) {
 957                 PMD_INIT_LOG(ERR, "Invalid queue size");
 958                 return -EFAULT;
 959         }
 960
 961         *max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 962                 get_feat_ctx->max_queues.max_packet_tx_descs);
 963
 964         return queue_size;
 965 }
 966
 967 static void ena_stats_restart(struct rte_eth_dev *dev)
 968 {
 969         struct ena_adapter *adapter =
 970                 (struct ena_adapter *)(dev->data->dev_private);
 971
 972         rte_atomic64_init(&adapter->drv_stats->ierrors);
 973         rte_atomic64_init(&adapter->drv_stats->oerrors);
 974         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 975 }
 976
 977 static int ena_stats_get(struct rte_eth_dev *dev,
 978                           struct rte_eth_stats *stats)
 979 {
 980         struct ena_admin_basic_stats ena_stats;
 981         struct ena_adapter *adapter =
 982                 (struct ena_adapter *)(dev->data->dev_private);
 983         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 984         int rc;
 985
 986         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 987                 return -ENOTSUP;
 988
 989         memset(&ena_stats, 0, sizeof(ena_stats));
 990         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 991         if (unlikely(rc)) {
 992                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
 993                 return rc;
 994         }
 995
 996         /* Set of basic statistics from ENA */
 997         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 998                                           ena_stats.rx_pkts_low);
 999         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1000                                           ena_stats.tx_pkts_low);
1001         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1002                                         ena_stats.rx_bytes_low);
1003         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1004                                         ena_stats.tx_bytes_low);
1005         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1006                                          ena_stats.rx_drops_low);
1007
1008         /* Driver related stats */
1009         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1010         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1011         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1012         return 0;
1013 }
1014
1015 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1016 {
1017         struct ena_adapter *adapter;
1018         struct ena_com_dev *ena_dev;
1019         int rc = 0;
1020
1021         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1022         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1023         adapter = (struct ena_adapter *)(dev->data->dev_private);
1024
1025         ena_dev = &adapter->ena_dev;
1026         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1027
1028         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1029                 RTE_LOG(ERR, PMD,
1030                         "Invalid MTU setting. new_mtu: %d "
1031                         "max mtu: %d min mtu: %d\n",
1032                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1033                 return -EINVAL;
1034         }
1035
1036         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1037         if (rc)
1038                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1039         else
1040                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1041
1042         return rc;
1043 }
1044
1045 static int ena_start(struct rte_eth_dev *dev)
1046 {
1047         struct ena_adapter *adapter =
1048                 (struct ena_adapter *)(dev->data->dev_private);
1049         uint64_t ticks;
1050         int rc = 0;
1051
1052         rc = ena_check_valid_conf(adapter);
1053         if (rc)
1054                 return rc;
1055
1056         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1057         if (rc)
1058                 return rc;
1059
1060         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1061         if (rc)
1062                 return rc;
1063
1064         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1065             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1066                 rc = ena_rss_init_default(adapter);
1067                 if (rc)
1068                         return rc;
1069         }
1070
1071         ena_stats_restart(dev);
1072
1073         adapter->timestamp_wd = rte_get_timer_cycles();
1074         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1075
1076         ticks = rte_get_timer_hz();
1077         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1078                         ena_timer_wd_callback, adapter);
1079
1080         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1081
1082         return 0;
1083 }
1084
1085 static void ena_stop(struct rte_eth_dev *dev)
1086 {
1087         struct ena_adapter *adapter =
1088                 (struct ena_adapter *)(dev->data->dev_private);
1089
1090         rte_timer_stop_sync(&adapter->timer_wd);
1091         ena_free_io_queues_all(adapter);
1092
1093         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1094 }
1095
1096 static int ena_create_io_queue(struct ena_ring *ring)
1097 {
1098         struct ena_adapter *adapter;
1099         struct ena_com_dev *ena_dev;
1100         struct ena_com_create_io_ctx ctx =
1101                 /* policy set to _HOST just to satisfy icc compiler */
1102                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1103                   0, 0, 0, 0, 0 };
1104         uint16_t ena_qid;
1105         unsigned int i;
1106         int rc;
1107
1108         adapter = ring->adapter;
1109         ena_dev = &adapter->ena_dev;
1110
1111         if (ring->type == ENA_RING_TYPE_TX) {
1112                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1113                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1114                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1115                 ctx.queue_size = adapter->tx_ring_size;
1116                 for (i = 0; i < ring->ring_size; i++)
1117                         ring->empty_tx_reqs[i] = i;
1118         } else {
1119                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1120                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1121                 ctx.queue_size = adapter->rx_ring_size;
1122                 for (i = 0; i < ring->ring_size; i++)
1123                         ring->empty_rx_reqs[i] = i;
1124         }
1125         ctx.qid = ena_qid;
1126         ctx.msix_vector = -1; /* interrupts not used */
1127         ctx.numa_node = ena_cpu_to_node(ring->id);
1128
1129         rc = ena_com_create_io_queue(ena_dev, &ctx);
1130         if (rc) {
1131                 RTE_LOG(ERR, PMD,
1132                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1133                         ring->id, ena_qid, rc);
1134                 return rc;
1135         }
1136
1137         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1138                                      &ring->ena_com_io_sq,
1139                                      &ring->ena_com_io_cq);
1140         if (rc) {
1141                 RTE_LOG(ERR, PMD,
1142                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1143                         ring->id, rc);
1144                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1145                 return rc;
1146         }
1147
1148         if (ring->type == ENA_RING_TYPE_TX)
1149                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1150
1151         return 0;
1152 }
1153
1154 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1155 {
1156         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1157         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1158         int i;
1159         uint16_t ena_qid;
1160         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1161         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1162
1163         for (i = 0; i < nb_txq; ++i) {
1164                 ena_qid = ENA_IO_TXQ_IDX(i);
1165                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1166
1167                 ena_tx_queue_release_bufs(&adapter->tx_ring[i]);
1168         }
1169
1170         for (i = 0; i < nb_rxq; ++i) {
1171                 ena_qid = ENA_IO_RXQ_IDX(i);
1172                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1173
1174                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1175         }
1176 }
1177
1178 static int ena_queue_restart(struct ena_ring *ring)
1179 {
1180         int rc, bufs_num;
1181
1182         ena_assert_msg(ring->configured == 1,
1183                        "Trying to restart unconfigured queue\n");
1184
1185         rc = ena_create_io_queue(ring);
1186         if (rc) {
1187                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1188                 return rc;
1189         }
1190
1191         ring->next_to_clean = 0;
1192         ring->next_to_use = 0;
1193
1194         if (ring->type == ENA_RING_TYPE_TX)
1195                 return 0;
1196
1197         bufs_num = ring->ring_size - 1;
1198         rc = ena_populate_rx_queue(ring, bufs_num);
1199         if (rc != bufs_num) {
1200                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1201                 return ENA_COM_FAULT;
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1208                               uint16_t queue_idx,
1209                               uint16_t nb_desc,
1210                               __rte_unused unsigned int socket_id,
1211                               const struct rte_eth_txconf *tx_conf)
1212 {
1213         struct ena_ring *txq = NULL;
1214         struct ena_adapter *adapter =
1215                 (struct ena_adapter *)(dev->data->dev_private);
1216         unsigned int i;
1217
1218         txq = &adapter->tx_ring[queue_idx];
1219
1220         if (txq->configured) {
1221                 RTE_LOG(CRIT, PMD,
1222                         "API violation. Queue %d is already configured\n",
1223                         queue_idx);
1224                 return ENA_COM_FAULT;
1225         }
1226
1227         if (!rte_is_power_of_2(nb_desc)) {
1228                 RTE_LOG(ERR, PMD,
1229                         "Unsupported size of TX queue: %d is not a power of 2.",
1230                         nb_desc);
1231                 return -EINVAL;
1232         }
1233
1234         if (nb_desc > adapter->tx_ring_size) {
1235                 RTE_LOG(ERR, PMD,
1236                         "Unsupported size of TX queue (max size: %d)\n",
1237                         adapter->tx_ring_size);
1238                 return -EINVAL;
1239         }
1240
1241         txq->port_id = dev->data->port_id;
1242         txq->next_to_clean = 0;
1243         txq->next_to_use = 0;
1244         txq->ring_size = nb_desc;
1245
1246         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1247                                           sizeof(struct ena_tx_buffer) *
1248                                           txq->ring_size,
1249                                           RTE_CACHE_LINE_SIZE);
1250         if (!txq->tx_buffer_info) {
1251                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1252                 return -ENOMEM;
1253         }
1254
1255         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1256                                          sizeof(u16) * txq->ring_size,
1257                                          RTE_CACHE_LINE_SIZE);
1258         if (!txq->empty_tx_reqs) {
1259                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1260                 rte_free(txq->tx_buffer_info);
1261                 return -ENOMEM;
1262         }
1263
1264         for (i = 0; i < txq->ring_size; i++)
1265                 txq->empty_tx_reqs[i] = i;
1266
1267         if (tx_conf != NULL) {
1268                 txq->offloads =
1269                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1270         }
1271
1272         /* Store pointer to this queue in upper layer */
1273         txq->configured = 1;
1274         dev->data->tx_queues[queue_idx] = txq;
1275
1276         return 0;
1277 }
1278
1279 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1280                               uint16_t queue_idx,
1281                               uint16_t nb_desc,
1282                               __rte_unused unsigned int socket_id,
1283                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1284                               struct rte_mempool *mp)
1285 {
1286         struct ena_adapter *adapter =
1287                 (struct ena_adapter *)(dev->data->dev_private);
1288         struct ena_ring *rxq = NULL;
1289         int i;
1290
1291         rxq = &adapter->rx_ring[queue_idx];
1292         if (rxq->configured) {
1293                 RTE_LOG(CRIT, PMD,
1294                         "API violation. Queue %d is already configured\n",
1295                         queue_idx);
1296                 return ENA_COM_FAULT;
1297         }
1298
1299         if (!rte_is_power_of_2(nb_desc)) {
1300                 RTE_LOG(ERR, PMD,
1301                         "Unsupported size of RX queue: %d is not a power of 2.",
1302                         nb_desc);
1303                 return -EINVAL;
1304         }
1305
1306         if (nb_desc > adapter->rx_ring_size) {
1307                 RTE_LOG(ERR, PMD,
1308                         "Unsupported size of RX queue (max size: %d)\n",
1309                         adapter->rx_ring_size);
1310                 return -EINVAL;
1311         }
1312
1313         rxq->port_id = dev->data->port_id;
1314         rxq->next_to_clean = 0;
1315         rxq->next_to_use = 0;
1316         rxq->ring_size = nb_desc;
1317         rxq->mb_pool = mp;
1318
1319         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1320                                           sizeof(struct rte_mbuf *) * nb_desc,
1321                                           RTE_CACHE_LINE_SIZE);
1322         if (!rxq->rx_buffer_info) {
1323                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1324                 return -ENOMEM;
1325         }
1326
1327         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1328                                             sizeof(struct rte_mbuf *) * nb_desc,
1329                                             RTE_CACHE_LINE_SIZE);
1330
1331         if (!rxq->rx_refill_buffer) {
1332                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1333                 rte_free(rxq->rx_buffer_info);
1334                 rxq->rx_buffer_info = NULL;
1335                 return -ENOMEM;
1336         }
1337
1338         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1339                                          sizeof(uint16_t) * nb_desc,
1340                                          RTE_CACHE_LINE_SIZE);
1341         if (!rxq->empty_rx_reqs) {
1342                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1343                 rte_free(rxq->rx_buffer_info);
1344                 rxq->rx_buffer_info = NULL;
1345                 rte_free(rxq->rx_refill_buffer);
1346                 rxq->rx_refill_buffer = NULL;
1347                 return -ENOMEM;
1348         }
1349
1350         for (i = 0; i < nb_desc; i++)
1351                 rxq->empty_tx_reqs[i] = i;
1352
1353         /* Store pointer to this queue in upper layer */
1354         rxq->configured = 1;
1355         dev->data->rx_queues[queue_idx] = rxq;
1356
1357         return 0;
1358 }
1359
1360 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1361 {
1362         unsigned int i;
1363         int rc;
1364         uint16_t ring_size = rxq->ring_size;
1365         uint16_t ring_mask = ring_size - 1;
1366         uint16_t next_to_use = rxq->next_to_use;
1367         uint16_t in_use, req_id;
1368         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1369
1370         if (unlikely(!count))
1371                 return 0;
1372
1373         in_use = rxq->next_to_use - rxq->next_to_clean;
1374         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1375
1376         /* get resources for incoming packets */
1377         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1378         if (unlikely(rc < 0)) {
1379                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1380                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1381                 return 0;
1382         }
1383
1384         for (i = 0; i < count; i++) {
1385                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1386                 struct rte_mbuf *mbuf = mbufs[i];
1387                 struct ena_com_buf ebuf;
1388
1389                 if (likely((i + 4) < count))
1390                         rte_prefetch0(mbufs[i + 4]);
1391
1392                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1393                 rc = validate_rx_req_id(rxq, req_id);
1394                 if (unlikely(rc < 0))
1395                         break;
1396                 rxq->rx_buffer_info[req_id] = mbuf;
1397
1398                 /* prepare physical address for DMA transaction */
1399                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1400                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1401                 /* pass resource to device */
1402                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1403                                                 &ebuf, req_id);
1404                 if (unlikely(rc)) {
1405                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1406                         rxq->rx_buffer_info[req_id] = NULL;
1407                         break;
1408                 }
1409                 next_to_use++;
1410         }
1411
1412         if (unlikely(i < count)) {
1413                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1414                         "buffers (from %d)\n", rxq->id, i, count);
1415                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1416                                      count - i);
1417         }
1418
1419         /* When we submitted free recources to device... */
1420         if (likely(i > 0)) {
1421                 /* ...let HW know that it can fill buffers with data
1422                  *
1423                  * Add memory barrier to make sure the desc were written before
1424                  * issue a doorbell
1425                  */
1426                 rte_wmb();
1427                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1428
1429                 rxq->next_to_use = next_to_use;
1430         }
1431
1432         return i;
1433 }
1434
1435 static int ena_device_init(struct ena_com_dev *ena_dev,
1436                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1437                            bool *wd_state)
1438 {
1439         uint32_t aenq_groups;
1440         int rc;
1441         bool readless_supported;
1442
1443         /* Initialize mmio registers */
1444         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1445         if (rc) {
1446                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1447                 return rc;
1448         }
1449
1450         /* The PCIe configuration space revision id indicate if mmio reg
1451          * read is disabled.
1452          */
1453         readless_supported =
1454                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1455                                & ENA_MMIO_DISABLE_REG_READ);
1456         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1457
1458         /* reset device */
1459         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1460         if (rc) {
1461                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1462                 goto err_mmio_read_less;
1463         }
1464
1465         /* check FW version */
1466         rc = ena_com_validate_version(ena_dev);
1467         if (rc) {
1468                 RTE_LOG(ERR, PMD, "device version is too low\n");
1469                 goto err_mmio_read_less;
1470         }
1471
1472         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1473
1474         /* ENA device administration layer init */
1475         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1476         if (rc) {
1477                 RTE_LOG(ERR, PMD,
1478                         "cannot initialize ena admin queue with device\n");
1479                 goto err_mmio_read_less;
1480         }
1481
1482         /* To enable the msix interrupts the driver needs to know the number
1483          * of queues. So the driver uses polling mode to retrieve this
1484          * information.
1485          */
1486         ena_com_set_admin_polling_mode(ena_dev, true);
1487
1488         ena_config_host_info(ena_dev);
1489
1490         /* Get Device Attributes and features */
1491         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1492         if (rc) {
1493                 RTE_LOG(ERR, PMD,
1494                         "cannot get attribute for ena device rc= %d\n", rc);
1495                 goto err_admin_init;
1496         }
1497
1498         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1499                       BIT(ENA_ADMIN_NOTIFICATION) |
1500                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1501                       BIT(ENA_ADMIN_FATAL_ERROR) |
1502                       BIT(ENA_ADMIN_WARNING);
1503
1504         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1505         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1506         if (rc) {
1507                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1508                 goto err_admin_init;
1509         }
1510
1511         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1512
1513         return 0;
1514
1515 err_admin_init:
1516         ena_com_admin_destroy(ena_dev);
1517
1518 err_mmio_read_less:
1519         ena_com_mmio_reg_read_request_destroy(ena_dev);
1520
1521         return rc;
1522 }
1523
1524 static void ena_interrupt_handler_rte(void *cb_arg)
1525 {
1526         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1527         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1528
1529         ena_com_admin_q_comp_intr_handler(ena_dev);
1530         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1531                 ena_com_aenq_intr_handler(ena_dev, adapter);
1532 }
1533
1534 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1535 {
1536         if (!adapter->wd_state)
1537                 return;
1538
1539         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1540                 return;
1541
1542         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1543             adapter->keep_alive_timeout)) {
1544                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1545                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1546                 adapter->trigger_reset = true;
1547         }
1548 }
1549
1550 /* Check if admin queue is enabled */
1551 static void check_for_admin_com_state(struct ena_adapter *adapter)
1552 {
1553         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1554                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1555                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1556                 adapter->trigger_reset = true;
1557         }
1558 }
1559
1560 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1561                                   void *arg)
1562 {
1563         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1564         struct rte_eth_dev *dev = adapter->rte_dev;
1565
1566         check_for_missing_keep_alive(adapter);
1567         check_for_admin_com_state(adapter);
1568
1569         if (unlikely(adapter->trigger_reset)) {
1570                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1571                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1572                         NULL);
1573         }
1574 }
1575
1576 static int ena_calc_io_queue_num(__rte_unused struct ena_com_dev *ena_dev,
1577                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1578 {
1579         int io_sq_num, io_cq_num, io_queue_num;
1580
1581         io_sq_num = get_feat_ctx->max_queues.max_sq_num;
1582         io_cq_num = get_feat_ctx->max_queues.max_cq_num;
1583
1584         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1585
1586         if (unlikely(io_queue_num == 0)) {
1587                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1588                 return -EFAULT;
1589         }
1590
1591         return io_queue_num;
1592 }
1593
1594 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1595 {
1596         struct rte_pci_device *pci_dev;
1597         struct rte_intr_handle *intr_handle;
1598         struct ena_adapter *adapter =
1599                 (struct ena_adapter *)(eth_dev->data->dev_private);
1600         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1601         struct ena_com_dev_get_features_ctx get_feat_ctx;
1602         int queue_size, rc;
1603         u16 tx_sgl_size = 0;
1604
1605         static int adapters_found;
1606         bool wd_state;
1607
1608         memset(adapter, 0, sizeof(struct ena_adapter));
1609         ena_dev = &adapter->ena_dev;
1610
1611         eth_dev->dev_ops = &ena_dev_ops;
1612         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1613         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1614         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1615         adapter->rte_eth_dev_data = eth_dev->data;
1616         adapter->rte_dev = eth_dev;
1617
1618         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1619                 return 0;
1620
1621         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1622         adapter->pdev = pci_dev;
1623
1624         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1625                      pci_dev->addr.domain,
1626                      pci_dev->addr.bus,
1627                      pci_dev->addr.devid,
1628                      pci_dev->addr.function);
1629
1630         intr_handle = &pci_dev->intr_handle;
1631
1632         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1633         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1634
1635         if (!adapter->regs) {
1636                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1637                              ENA_REGS_BAR);
1638                 return -ENXIO;
1639         }
1640
1641         ena_dev->reg_bar = adapter->regs;
1642         ena_dev->dmadev = adapter->pdev;
1643
1644         adapter->id_number = adapters_found;
1645
1646         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1647                  adapter->id_number);
1648
1649         /* device specific initialization routine */
1650         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1651         if (rc) {
1652                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1653                 goto err;
1654         }
1655         adapter->wd_state = wd_state;
1656
1657         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1658         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1659                                                     &get_feat_ctx);
1660
1661         queue_size = ena_calc_queue_size(ena_dev, &tx_sgl_size, &get_feat_ctx);
1662         if (queue_size <= 0 || adapter->num_queues <= 0) {
1663                 rc = -EFAULT;
1664                 goto err_device_destroy;
1665         }
1666
1667         adapter->tx_ring_size = queue_size;
1668         adapter->rx_ring_size = queue_size;
1669
1670         adapter->max_tx_sgl_size = tx_sgl_size;
1671
1672         /* prepare ring structures */
1673         ena_init_rings(adapter);
1674
1675         ena_config_debug_area(adapter);
1676
1677         /* Set max MTU for this device */
1678         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1679
1680         /* set device support for TSO */
1681         adapter->tso4_supported = get_feat_ctx.offload.tx &
1682                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1683
1684         /* Copy MAC address and point DPDK to it */
1685         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1686         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1687                         (struct ether_addr *)adapter->mac_addr);
1688
1689         /*
1690          * Pass the information to the rte_eth_dev_close() that it should also
1691          * release the private port resources.
1692          */
1693         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1694
1695         adapter->drv_stats = rte_zmalloc("adapter stats",
1696                                          sizeof(*adapter->drv_stats),
1697                                          RTE_CACHE_LINE_SIZE);
1698         if (!adapter->drv_stats) {
1699                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1700                 rc = -ENOMEM;
1701                 goto err_delete_debug_area;
1702         }
1703
1704         rte_intr_callback_register(intr_handle,
1705                                    ena_interrupt_handler_rte,
1706                                    adapter);
1707         rte_intr_enable(intr_handle);
1708         ena_com_set_admin_polling_mode(ena_dev, false);
1709         ena_com_admin_aenq_enable(ena_dev);
1710
1711         if (adapters_found == 0)
1712                 rte_timer_subsystem_init();
1713         rte_timer_init(&adapter->timer_wd);
1714
1715         adapters_found++;
1716         adapter->state = ENA_ADAPTER_STATE_INIT;
1717
1718         return 0;
1719
1720 err_delete_debug_area:
1721         ena_com_delete_debug_area(ena_dev);
1722
1723 err_device_destroy:
1724         ena_com_delete_host_info(ena_dev);
1725         ena_com_admin_destroy(ena_dev);
1726
1727 err:
1728         return rc;
1729 }
1730
1731 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1732 {
1733         struct ena_adapter *adapter =
1734                 (struct ena_adapter *)(eth_dev->data->dev_private);
1735
1736         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1737                 return 0;
1738
1739         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1740                 ena_close(eth_dev);
1741
1742         eth_dev->dev_ops = NULL;
1743         eth_dev->rx_pkt_burst = NULL;
1744         eth_dev->tx_pkt_burst = NULL;
1745         eth_dev->tx_pkt_prepare = NULL;
1746
1747         adapter->state = ENA_ADAPTER_STATE_FREE;
1748
1749         return 0;
1750 }
1751
1752 static int ena_dev_configure(struct rte_eth_dev *dev)
1753 {
1754         struct ena_adapter *adapter =
1755                 (struct ena_adapter *)(dev->data->dev_private);
1756
1757         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1758
1759         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1760         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1761         return 0;
1762 }
1763
1764 static void ena_init_rings(struct ena_adapter *adapter)
1765 {
1766         int i;
1767
1768         for (i = 0; i < adapter->num_queues; i++) {
1769                 struct ena_ring *ring = &adapter->tx_ring[i];
1770
1771                 ring->configured = 0;
1772                 ring->type = ENA_RING_TYPE_TX;
1773                 ring->adapter = adapter;
1774                 ring->id = i;
1775                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1776                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1777                 ring->sgl_size = adapter->max_tx_sgl_size;
1778         }
1779
1780         for (i = 0; i < adapter->num_queues; i++) {
1781                 struct ena_ring *ring = &adapter->rx_ring[i];
1782
1783                 ring->configured = 0;
1784                 ring->type = ENA_RING_TYPE_RX;
1785                 ring->adapter = adapter;
1786                 ring->id = i;
1787         }
1788 }
1789
1790 static void ena_infos_get(struct rte_eth_dev *dev,
1791                           struct rte_eth_dev_info *dev_info)
1792 {
1793         struct ena_adapter *adapter;
1794         struct ena_com_dev *ena_dev;
1795         struct ena_com_dev_get_features_ctx feat;
1796         uint64_t rx_feat = 0, tx_feat = 0;
1797         int rc = 0;
1798
1799         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1800         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1801         adapter = (struct ena_adapter *)(dev->data->dev_private);
1802
1803         ena_dev = &adapter->ena_dev;
1804         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1805
1806         dev_info->speed_capa =
1807                         ETH_LINK_SPEED_1G   |
1808                         ETH_LINK_SPEED_2_5G |
1809                         ETH_LINK_SPEED_5G   |
1810                         ETH_LINK_SPEED_10G  |
1811                         ETH_LINK_SPEED_25G  |
1812                         ETH_LINK_SPEED_40G  |
1813                         ETH_LINK_SPEED_50G  |
1814                         ETH_LINK_SPEED_100G;
1815
1816         /* Get supported features from HW */
1817         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1818         if (unlikely(rc)) {
1819                 RTE_LOG(ERR, PMD,
1820                         "Cannot get attribute for ena device rc= %d\n", rc);
1821                 return;
1822         }
1823
1824         /* Set Tx & Rx features available for device */
1825         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1826                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1827
1828         if (feat.offload.tx &
1829             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1830                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1831                         DEV_TX_OFFLOAD_UDP_CKSUM |
1832                         DEV_TX_OFFLOAD_TCP_CKSUM;
1833
1834         if (feat.offload.rx_supported &
1835             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1836                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1837                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1838                         DEV_RX_OFFLOAD_TCP_CKSUM;
1839
1840         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1841
1842         /* Inform framework about available features */
1843         dev_info->rx_offload_capa = rx_feat;
1844         dev_info->rx_queue_offload_capa = rx_feat;
1845         dev_info->tx_offload_capa = tx_feat;
1846         dev_info->tx_queue_offload_capa = tx_feat;
1847
1848         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1849         dev_info->max_rx_pktlen  = adapter->max_mtu;
1850         dev_info->max_mac_addrs = 1;
1851
1852         dev_info->max_rx_queues = adapter->num_queues;
1853         dev_info->max_tx_queues = adapter->num_queues;
1854         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1855
1856         adapter->tx_supported_offloads = tx_feat;
1857         adapter->rx_supported_offloads = rx_feat;
1858
1859         dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1860         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1861
1862         dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC;
1863         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1864         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1865                                         feat.max_queues.max_packet_tx_descs);
1866         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1867                                         feat.max_queues.max_packet_tx_descs);
1868 }
1869
1870 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1871                                   uint16_t nb_pkts)
1872 {
1873         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1874         unsigned int ring_size = rx_ring->ring_size;
1875         unsigned int ring_mask = ring_size - 1;
1876         uint16_t next_to_clean = rx_ring->next_to_clean;
1877         uint16_t desc_in_use = 0;
1878         uint16_t req_id;
1879         unsigned int recv_idx = 0;
1880         struct rte_mbuf *mbuf = NULL;
1881         struct rte_mbuf *mbuf_head = NULL;
1882         struct rte_mbuf *mbuf_prev = NULL;
1883         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1884         unsigned int completed;
1885
1886         struct ena_com_rx_ctx ena_rx_ctx;
1887         int rc = 0;
1888
1889         /* Check adapter state */
1890         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1891                 RTE_LOG(ALERT, PMD,
1892                         "Trying to receive pkts while device is NOT running\n");
1893                 return 0;
1894         }
1895
1896         desc_in_use = rx_ring->next_to_use - next_to_clean;
1897         if (unlikely(nb_pkts > desc_in_use))
1898                 nb_pkts = desc_in_use;
1899
1900         for (completed = 0; completed < nb_pkts; completed++) {
1901                 int segments = 0;
1902
1903                 ena_rx_ctx.max_bufs = rx_ring->ring_size;
1904                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1905                 ena_rx_ctx.descs = 0;
1906                 /* receive packet context */
1907                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1908                                     rx_ring->ena_com_io_sq,
1909                                     &ena_rx_ctx);
1910                 if (unlikely(rc)) {
1911                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1912                         rx_ring->adapter->trigger_reset = true;
1913                         return 0;
1914                 }
1915
1916                 if (unlikely(ena_rx_ctx.descs == 0))
1917                         break;
1918
1919                 while (segments < ena_rx_ctx.descs) {
1920                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1921                         rc = validate_rx_req_id(rx_ring, req_id);
1922                         if (unlikely(rc))
1923                                 break;
1924
1925                         mbuf = rx_buff_info[req_id];
1926                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1927                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1928                         mbuf->refcnt = 1;
1929                         mbuf->next = NULL;
1930                         if (unlikely(segments == 0)) {
1931                                 mbuf->nb_segs = ena_rx_ctx.descs;
1932                                 mbuf->port = rx_ring->port_id;
1933                                 mbuf->pkt_len = 0;
1934                                 mbuf_head = mbuf;
1935                         } else {
1936                                 /* for multi-segment pkts create mbuf chain */
1937                                 mbuf_prev->next = mbuf;
1938                         }
1939                         mbuf_head->pkt_len += mbuf->data_len;
1940
1941                         mbuf_prev = mbuf;
1942                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1943                                 req_id;
1944                         segments++;
1945                         next_to_clean++;
1946                 }
1947
1948                 /* fill mbuf attributes if any */
1949                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1950                 mbuf_head->hash.rss = ena_rx_ctx.hash;
1951
1952                 /* pass to DPDK application head mbuf */
1953                 rx_pkts[recv_idx] = mbuf_head;
1954                 recv_idx++;
1955         }
1956
1957         rx_ring->next_to_clean = next_to_clean;
1958
1959         desc_in_use = desc_in_use - completed + 1;
1960         /* Burst refill to save doorbells, memory barriers, const interval */
1961         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
1962                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
1963
1964         return recv_idx;
1965 }
1966
1967 static uint16_t
1968 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
1969                 uint16_t nb_pkts)
1970 {
1971         int32_t ret;
1972         uint32_t i;
1973         struct rte_mbuf *m;
1974         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
1975         struct ipv4_hdr *ip_hdr;
1976         uint64_t ol_flags;
1977         uint16_t frag_field;
1978
1979         for (i = 0; i != nb_pkts; i++) {
1980                 m = tx_pkts[i];
1981                 ol_flags = m->ol_flags;
1982
1983                 if (!(ol_flags & PKT_TX_IPV4))
1984                         continue;
1985
1986                 /* If there was not L2 header length specified, assume it is
1987                  * length of the ethernet header.
1988                  */
1989                 if (unlikely(m->l2_len == 0))
1990                         m->l2_len = sizeof(struct ether_hdr);
1991
1992                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1993                                                  m->l2_len);
1994                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
1995
1996                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
1997                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
1998
1999                         /* If IPv4 header has DF flag enabled and TSO support is
2000                          * disabled, partial chcecksum should not be calculated.
2001                          */
2002                         if (!tx_ring->adapter->tso4_supported)
2003                                 continue;
2004                 }
2005
2006                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2007                                 (ol_flags & PKT_TX_L4_MASK) ==
2008                                 PKT_TX_SCTP_CKSUM) {
2009                         rte_errno = -ENOTSUP;
2010                         return i;
2011                 }
2012
2013 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2014                 ret = rte_validate_tx_offload(m);
2015                 if (ret != 0) {
2016                         rte_errno = ret;
2017                         return i;
2018                 }
2019 #endif
2020
2021                 /* In case we are supposed to TSO and have DF not set (DF=0)
2022                  * hardware must be provided with partial checksum, otherwise
2023                  * it will take care of necessary calculations.
2024                  */
2025
2026                 ret = rte_net_intel_cksum_flags_prepare(m,
2027                         ol_flags & ~PKT_TX_TCP_SEG);
2028                 if (ret != 0) {
2029                         rte_errno = ret;
2030                         return i;
2031                 }
2032         }
2033
2034         return i;
2035 }
2036
2037 static void ena_update_hints(struct ena_adapter *adapter,
2038                              struct ena_admin_ena_hw_hints *hints)
2039 {
2040         if (hints->admin_completion_tx_timeout)
2041                 adapter->ena_dev.admin_queue.completion_timeout =
2042                         hints->admin_completion_tx_timeout * 1000;
2043
2044         if (hints->mmio_read_timeout)
2045                 /* convert to usec */
2046                 adapter->ena_dev.mmio_read.reg_read_to =
2047                         hints->mmio_read_timeout * 1000;
2048
2049         if (hints->driver_watchdog_timeout) {
2050                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2051                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2052                 else
2053                         // Convert msecs to ticks
2054                         adapter->keep_alive_timeout =
2055                                 (hints->driver_watchdog_timeout *
2056                                 rte_get_timer_hz()) / 1000;
2057         }
2058 }
2059
2060 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2061                                         struct rte_mbuf *mbuf)
2062 {
2063         int num_segments, rc;
2064
2065         num_segments = mbuf->nb_segs;
2066
2067         if (likely(num_segments < tx_ring->sgl_size))
2068                 return 0;
2069
2070         rc = rte_pktmbuf_linearize(mbuf);
2071         if (unlikely(rc))
2072                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2073
2074         return rc;
2075 }
2076
2077 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2078                                   uint16_t nb_pkts)
2079 {
2080         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2081         uint16_t next_to_use = tx_ring->next_to_use;
2082         uint16_t next_to_clean = tx_ring->next_to_clean;
2083         struct rte_mbuf *mbuf;
2084         unsigned int ring_size = tx_ring->ring_size;
2085         unsigned int ring_mask = ring_size - 1;
2086         struct ena_com_tx_ctx ena_tx_ctx;
2087         struct ena_tx_buffer *tx_info;
2088         struct ena_com_buf *ebuf;
2089         uint16_t rc, req_id, total_tx_descs = 0;
2090         uint16_t sent_idx = 0, empty_tx_reqs;
2091         int nb_hw_desc;
2092
2093         /* Check adapter state */
2094         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2095                 RTE_LOG(ALERT, PMD,
2096                         "Trying to xmit pkts while device is NOT running\n");
2097                 return 0;
2098         }
2099
2100         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2101         if (nb_pkts > empty_tx_reqs)
2102                 nb_pkts = empty_tx_reqs;
2103
2104         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2105                 mbuf = tx_pkts[sent_idx];
2106
2107                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2108                 if (unlikely(rc))
2109                         break;
2110
2111                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2112                 tx_info = &tx_ring->tx_buffer_info[req_id];
2113                 tx_info->mbuf = mbuf;
2114                 tx_info->num_of_bufs = 0;
2115                 ebuf = tx_info->bufs;
2116
2117                 /* Prepare TX context */
2118                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2119                 memset(&ena_tx_ctx.ena_meta, 0x0,
2120                        sizeof(struct ena_com_tx_meta));
2121                 ena_tx_ctx.ena_bufs = ebuf;
2122                 ena_tx_ctx.req_id = req_id;
2123                 if (tx_ring->tx_mem_queue_type ==
2124                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2125                         /* prepare the push buffer with
2126                          * virtual address of the data
2127                          */
2128                         ena_tx_ctx.header_len =
2129                                 RTE_MIN(mbuf->data_len,
2130                                         tx_ring->tx_max_header_size);
2131                         ena_tx_ctx.push_header =
2132                                 (void *)((char *)mbuf->buf_addr +
2133                                          mbuf->data_off);
2134                 } /* there's no else as we take advantage of memset zeroing */
2135
2136                 /* Set TX offloads flags, if applicable */
2137                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2138
2139                 if (unlikely(mbuf->ol_flags &
2140                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2141                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2142
2143                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2144
2145                 /* Process first segment taking into
2146                  * consideration pushed header
2147                  */
2148                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2149                         ebuf->paddr = mbuf->buf_iova +
2150                                       mbuf->data_off +
2151                                       ena_tx_ctx.header_len;
2152                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2153                         ebuf++;
2154                         tx_info->num_of_bufs++;
2155                 }
2156
2157                 while ((mbuf = mbuf->next) != NULL) {
2158                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2159                         ebuf->len = mbuf->data_len;
2160                         ebuf++;
2161                         tx_info->num_of_bufs++;
2162                 }
2163
2164                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2165
2166                 /* Write data to device */
2167                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2168                                         &ena_tx_ctx, &nb_hw_desc);
2169                 if (unlikely(rc))
2170                         break;
2171
2172                 tx_info->tx_descs = nb_hw_desc;
2173
2174                 next_to_use++;
2175         }
2176
2177         /* If there are ready packets to be xmitted... */
2178         if (sent_idx > 0) {
2179                 /* ...let HW do its best :-) */
2180                 rte_wmb();
2181                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2182
2183                 tx_ring->next_to_use = next_to_use;
2184         }
2185
2186         /* Clear complete packets  */
2187         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2188                 rc = validate_tx_req_id(tx_ring, req_id);
2189                 if (rc)
2190                         break;
2191
2192                 /* Get Tx info & store how many descs were processed  */
2193                 tx_info = &tx_ring->tx_buffer_info[req_id];
2194                 total_tx_descs += tx_info->tx_descs;
2195
2196                 /* Free whole mbuf chain  */
2197                 mbuf = tx_info->mbuf;
2198                 rte_pktmbuf_free(mbuf);
2199                 tx_info->mbuf = NULL;
2200
2201                 /* Put back descriptor to the ring for reuse */
2202                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2203                 next_to_clean++;
2204
2205                 /* If too many descs to clean, leave it for another run */
2206                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2207                         break;
2208         }
2209
2210         if (total_tx_descs > 0) {
2211                 /* acknowledge completion of sent packets */
2212                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2213                 tx_ring->next_to_clean = next_to_clean;
2214         }
2215
2216         return sent_idx;
2217 }
2218
2219 /*********************************************************************
2220  *  PMD configuration
2221  *********************************************************************/
2222 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2223         struct rte_pci_device *pci_dev)
2224 {
2225         return rte_eth_dev_pci_generic_probe(pci_dev,
2226                 sizeof(struct ena_adapter), eth_ena_dev_init);
2227 }
2228
2229 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2230 {
2231         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2232 }
2233
2234 static struct rte_pci_driver rte_ena_pmd = {
2235         .id_table = pci_id_ena_map,
2236         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2237                      RTE_PCI_DRV_WC_ACTIVATE,
2238         .probe = eth_ena_pci_probe,
2239         .remove = eth_ena_pci_remove,
2240 };
2241
2242 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2243 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2244 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2245
2246 RTE_INIT(ena_init_log)
2247 {
2248         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2249         if (ena_logtype_init >= 0)
2250                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2251         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2252         if (ena_logtype_driver >= 0)
2253                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2254 }
2255
2256 /******************************************************************************
2257  ******************************** AENQ Handlers *******************************
2258  *****************************************************************************/
2259 static void ena_update_on_link_change(void *adapter_data,
2260                                       struct ena_admin_aenq_entry *aenq_e)
2261 {
2262         struct rte_eth_dev *eth_dev;
2263         struct ena_adapter *adapter;
2264         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2265         uint32_t status;
2266
2267         adapter = (struct ena_adapter *)adapter_data;
2268         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2269         eth_dev = adapter->rte_dev;
2270
2271         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2272         adapter->link_status = status;
2273
2274         ena_link_update(eth_dev, 0);
2275         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2276 }
2277
2278 static void ena_notification(void *data,
2279                              struct ena_admin_aenq_entry *aenq_e)
2280 {
2281         struct ena_adapter *adapter = (struct ena_adapter *)data;
2282         struct ena_admin_ena_hw_hints *hints;
2283
2284         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2285                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2286                         aenq_e->aenq_common_desc.group,
2287                         ENA_ADMIN_NOTIFICATION);
2288
2289         switch (aenq_e->aenq_common_desc.syndrom) {
2290         case ENA_ADMIN_UPDATE_HINTS:
2291                 hints = (struct ena_admin_ena_hw_hints *)
2292                         (&aenq_e->inline_data_w4);
2293                 ena_update_hints(adapter, hints);
2294                 break;
2295         default:
2296                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2297                         aenq_e->aenq_common_desc.syndrom);
2298         }
2299 }
2300
2301 static void ena_keep_alive(void *adapter_data,
2302                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2303 {
2304         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2305
2306         adapter->timestamp_wd = rte_get_timer_cycles();
2307 }
2308
2309 /**
2310  * This handler will called for unknown event group or unimplemented handlers
2311  **/
2312 static void unimplemented_aenq_handler(__rte_unused void *data,
2313                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2314 {
2315         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2316                           "unimplemented handler\n");
2317 }
2318
2319 static struct ena_aenq_handlers aenq_handlers = {
2320         .handlers = {
2321                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2322                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2323                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2324         },
2325         .unimplemented_handler = unimplemented_aenq_handler
2326 };