drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 #define ENA_MAX_RING_SIZE_RX 8192
 120 #define ENA_MAX_RING_SIZE_TX 1024
 121
 122 /*
 123  * Each rte_memzone should have unique name.
 124  * To satisfy it, count number of allocation and add it to name.
 125  */
 126 uint32_t ena_alloc_cnt;
 127
 128 static const struct ena_stats ena_stats_global_strings[] = {
 129         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 130         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 131         ENA_STAT_GLOBAL_ENTRY(io_resume),
 132         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 133         ENA_STAT_GLOBAL_ENTRY(interface_up),
 134         ENA_STAT_GLOBAL_ENTRY(interface_down),
 135         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 136 };
 137
 138 static const struct ena_stats ena_stats_tx_strings[] = {
 139         ENA_STAT_TX_ENTRY(cnt),
 140         ENA_STAT_TX_ENTRY(bytes),
 141         ENA_STAT_TX_ENTRY(queue_stop),
 142         ENA_STAT_TX_ENTRY(queue_wakeup),
 143         ENA_STAT_TX_ENTRY(dma_mapping_err),
 144         ENA_STAT_TX_ENTRY(linearize),
 145         ENA_STAT_TX_ENTRY(linearize_failed),
 146         ENA_STAT_TX_ENTRY(tx_poll),
 147         ENA_STAT_TX_ENTRY(doorbells),
 148         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 149         ENA_STAT_TX_ENTRY(missing_tx_comp),
 150         ENA_STAT_TX_ENTRY(bad_req_id),
 151 };
 152
 153 static const struct ena_stats ena_stats_rx_strings[] = {
 154         ENA_STAT_RX_ENTRY(cnt),
 155         ENA_STAT_RX_ENTRY(bytes),
 156         ENA_STAT_RX_ENTRY(refil_partial),
 157         ENA_STAT_RX_ENTRY(bad_csum),
 158         ENA_STAT_RX_ENTRY(page_alloc_fail),
 159         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 160         ENA_STAT_RX_ENTRY(dma_mapping_err),
 161         ENA_STAT_RX_ENTRY(bad_desc_num),
 162         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 163 };
 164
 165 static const struct ena_stats ena_stats_ena_com_strings[] = {
 166         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 167         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 168         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 169         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 170         ENA_STAT_ENA_COM_ENTRY(no_completion),
 171 };
 172
 173 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 174 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 175 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 176 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 177
 178 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 179                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 180                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 181                         DEV_TX_OFFLOAD_TCP_TSO)
 182 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 183                        PKT_TX_IP_CKSUM |\
 184                        PKT_TX_TCP_SEG)
 185
 186 /** Vendor ID used by Amazon devices */
 187 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 188 /** Amazon devices */
 189 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 190 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 191
 192 #define ENA_TX_OFFLOAD_MASK     (\
 193         PKT_TX_L4_MASK |         \
 194         PKT_TX_IPV6 |            \
 195         PKT_TX_IPV4 |            \
 196         PKT_TX_IP_CKSUM |        \
 197         PKT_TX_TCP_SEG)
 198
 199 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 200         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 201
 202 int ena_logtype_init;
 203 int ena_logtype_driver;
 204
 205 static const struct rte_pci_id pci_id_ena_map[] = {
 206         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 207         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 208         { .device_id = 0 },
 209 };
 210
 211 static struct ena_aenq_handlers aenq_handlers;
 212
 213 static int ena_device_init(struct ena_com_dev *ena_dev,
 214                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 215                            bool *wd_state);
 216 static int ena_dev_configure(struct rte_eth_dev *dev);
 217 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 218                                   uint16_t nb_pkts);
 219 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 220                 uint16_t nb_pkts);
 221 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 222                               uint16_t nb_desc, unsigned int socket_id,
 223                               const struct rte_eth_txconf *tx_conf);
 224 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 225                               uint16_t nb_desc, unsigned int socket_id,
 226                               const struct rte_eth_rxconf *rx_conf,
 227                               struct rte_mempool *mp);
 228 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 229                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 230 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 231 static void ena_init_rings(struct ena_adapter *adapter);
 232 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 233 static int ena_start(struct rte_eth_dev *dev);
 234 static void ena_stop(struct rte_eth_dev *dev);
 235 static void ena_close(struct rte_eth_dev *dev);
 236 static int ena_dev_reset(struct rte_eth_dev *dev);
 237 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 238 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 239 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 240 static void ena_rx_queue_release(void *queue);
 241 static void ena_tx_queue_release(void *queue);
 242 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 243 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 244 static int ena_link_update(struct rte_eth_dev *dev,
 245                            int wait_to_complete);
 246 static int ena_create_io_queue(struct ena_ring *ring);
 247 static void ena_queue_stop(struct ena_ring *ring);
 248 static void ena_queue_stop_all(struct rte_eth_dev *dev,
 249                               enum ena_ring_type ring_type);
 250 static int ena_queue_start(struct ena_ring *ring);
 251 static int ena_queue_start_all(struct rte_eth_dev *dev,
 252                                enum ena_ring_type ring_type);
 253 static void ena_stats_restart(struct rte_eth_dev *dev);
 254 static void ena_infos_get(struct rte_eth_dev *dev,
 255                           struct rte_eth_dev_info *dev_info);
 256 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 257                                struct rte_eth_rss_reta_entry64 *reta_conf,
 258                                uint16_t reta_size);
 259 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 260                               struct rte_eth_rss_reta_entry64 *reta_conf,
 261                               uint16_t reta_size);
 262 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 263 static void ena_interrupt_handler_rte(void *cb_arg);
 264 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 265 static void ena_destroy_device(struct rte_eth_dev *eth_dev);
 266 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev);
 267
 268 static const struct eth_dev_ops ena_dev_ops = {
 269         .dev_configure        = ena_dev_configure,
 270         .dev_infos_get        = ena_infos_get,
 271         .rx_queue_setup       = ena_rx_queue_setup,
 272         .tx_queue_setup       = ena_tx_queue_setup,
 273         .dev_start            = ena_start,
 274         .dev_stop             = ena_stop,
 275         .link_update          = ena_link_update,
 276         .stats_get            = ena_stats_get,
 277         .mtu_set              = ena_mtu_set,
 278         .rx_queue_release     = ena_rx_queue_release,
 279         .tx_queue_release     = ena_tx_queue_release,
 280         .dev_close            = ena_close,
 281         .dev_reset            = ena_dev_reset,
 282         .reta_update          = ena_rss_reta_update,
 283         .reta_query           = ena_rss_reta_query,
 284 };
 285
 286 #define NUMA_NO_NODE    SOCKET_ID_ANY
 287
 288 static inline int ena_cpu_to_node(int cpu)
 289 {
 290         struct rte_config *config = rte_eal_get_configuration();
 291         struct rte_fbarray *arr = &config->mem_config->memzones;
 292         const struct rte_memzone *mz;
 293
 294         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 295                 return NUMA_NO_NODE;
 296
 297         mz = rte_fbarray_get(arr, cpu);
 298
 299         return mz->socket_id;
 300 }
 301
 302 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 303                                        struct ena_com_rx_ctx *ena_rx_ctx)
 304 {
 305         uint64_t ol_flags = 0;
 306         uint32_t packet_type = 0;
 307
 308         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 309                 packet_type |= RTE_PTYPE_L4_TCP;
 310         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 311                 packet_type |= RTE_PTYPE_L4_UDP;
 312
 313         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 314                 packet_type |= RTE_PTYPE_L3_IPV4;
 315         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 316                 packet_type |= RTE_PTYPE_L3_IPV6;
 317
 318         if (unlikely(ena_rx_ctx->l4_csum_err))
 319                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 320         if (unlikely(ena_rx_ctx->l3_csum_err))
 321                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 322
 323         mbuf->ol_flags = ol_flags;
 324         mbuf->packet_type = packet_type;
 325 }
 326
 327 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 328                                        struct ena_com_tx_ctx *ena_tx_ctx,
 329                                        uint64_t queue_offloads)
 330 {
 331         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 332
 333         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 334             (queue_offloads & QUEUE_OFFLOADS)) {
 335                 /* check if TSO is required */
 336                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 337                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 338                         ena_tx_ctx->tso_enable = true;
 339
 340                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 341                 }
 342
 343                 /* check if L3 checksum is needed */
 344                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 345                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 346                         ena_tx_ctx->l3_csum_enable = true;
 347
 348                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 349                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 350                 } else {
 351                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 352
 353                         /* set don't fragment (DF) flag */
 354                         if (mbuf->packet_type &
 355                                 (RTE_PTYPE_L4_NONFRAG
 356                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 357                                 ena_tx_ctx->df = true;
 358                 }
 359
 360                 /* check if L4 checksum is needed */
 361                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 362                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 364                         ena_tx_ctx->l4_csum_enable = true;
 365                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 366                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 367                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 368                         ena_tx_ctx->l4_csum_enable = true;
 369                 } else {
 370                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 371                         ena_tx_ctx->l4_csum_enable = false;
 372                 }
 373
 374                 ena_meta->mss = mbuf->tso_segsz;
 375                 ena_meta->l3_hdr_len = mbuf->l3_len;
 376                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 377
 378                 ena_tx_ctx->meta_valid = true;
 379         } else {
 380                 ena_tx_ctx->meta_valid = false;
 381         }
 382 }
 383
 384 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 385 {
 386         if (likely(req_id < rx_ring->ring_size))
 387                 return 0;
 388
 389         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 390
 391         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 392         rx_ring->adapter->trigger_reset = true;
 393
 394         return -EFAULT;
 395 }
 396
 397 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 398 {
 399         struct ena_tx_buffer *tx_info = NULL;
 400
 401         if (likely(req_id < tx_ring->ring_size)) {
 402                 tx_info = &tx_ring->tx_buffer_info[req_id];
 403                 if (likely(tx_info->mbuf))
 404                         return 0;
 405         }
 406
 407         if (tx_info)
 408                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 409         else
 410                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 411
 412         /* Trigger device reset */
 413         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 414         tx_ring->adapter->trigger_reset = true;
 415         return -EFAULT;
 416 }
 417
 418 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 419 {
 420         struct ena_admin_host_info *host_info;
 421         int rc;
 422
 423         /* Allocate only the host info */
 424         rc = ena_com_allocate_host_info(ena_dev);
 425         if (rc) {
 426                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 427                 return;
 428         }
 429
 430         host_info = ena_dev->host_attr.host_info;
 431
 432         host_info->os_type = ENA_ADMIN_OS_DPDK;
 433         host_info->kernel_ver = RTE_VERSION;
 434         snprintf((char *)host_info->kernel_ver_str,
 435                  sizeof(host_info->kernel_ver_str),
 436                  "%s", rte_version());
 437         host_info->os_dist = RTE_VERSION;
 438         snprintf((char *)host_info->os_dist_str,
 439                  sizeof(host_info->os_dist_str),
 440                  "%s", rte_version());
 441         host_info->driver_version =
 442                 (DRV_MODULE_VER_MAJOR) |
 443                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 444                 (DRV_MODULE_VER_SUBMINOR <<
 445                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 446         host_info->num_cpus = rte_lcore_count();
 447
 448         rc = ena_com_set_host_attributes(ena_dev);
 449         if (rc) {
 450                 if (rc == -ENA_COM_UNSUPPORTED)
 451                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 452                 else
 453                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 454
 455                 goto err;
 456         }
 457
 458         return;
 459
 460 err:
 461         ena_com_delete_host_info(ena_dev);
 462 }
 463
 464 static int
 465 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 466 {
 467         if (sset != ETH_SS_STATS)
 468                 return -EOPNOTSUPP;
 469
 470          /* Workaround for clang:
 471          * touch internal structures to prevent
 472          * compiler error
 473          */
 474         ENA_TOUCH(ena_stats_global_strings);
 475         ENA_TOUCH(ena_stats_tx_strings);
 476         ENA_TOUCH(ena_stats_rx_strings);
 477         ENA_TOUCH(ena_stats_ena_com_strings);
 478
 479         return  dev->data->nb_tx_queues *
 480                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 481                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 482 }
 483
 484 static void ena_config_debug_area(struct ena_adapter *adapter)
 485 {
 486         u32 debug_area_size;
 487         int rc, ss_count;
 488
 489         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 490         if (ss_count <= 0) {
 491                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 492                 return;
 493         }
 494
 495         /* allocate 32 bytes for each string and 64bit for the value */
 496         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 497
 498         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 499         if (rc) {
 500                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 501                 return;
 502         }
 503
 504         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 505         if (rc) {
 506                 if (rc == -ENA_COM_UNSUPPORTED)
 507                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 508                 else
 509                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 510
 511                 goto err;
 512         }
 513
 514         return;
 515 err:
 516         ena_com_delete_debug_area(&adapter->ena_dev);
 517 }
 518
 519 static void ena_close(struct rte_eth_dev *dev)
 520 {
 521         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 522         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 523         struct ena_adapter *adapter =
 524                 (struct ena_adapter *)(dev->data->dev_private);
 525
 526         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 527                 ena_stop(dev);
 528         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 529
 530         ena_rx_queue_release_all(dev);
 531         ena_tx_queue_release_all(dev);
 532
 533         rte_free(adapter->drv_stats);
 534         adapter->drv_stats = NULL;
 535
 536         rte_intr_disable(intr_handle);
 537         rte_intr_callback_unregister(intr_handle,
 538                                      ena_interrupt_handler_rte,
 539                                      adapter);
 540
 541         /*
 542          * MAC is not allocated dynamically. Setting NULL should prevent from
 543          * release of the resource in the rte_eth_dev_release_port().
 544          */
 545         dev->data->mac_addrs = NULL;
 546 }
 547
 548 static int
 549 ena_dev_reset(struct rte_eth_dev *dev)
 550 {
 551         int rc = 0;
 552
 553         ena_destroy_device(dev);
 554         rc = eth_ena_dev_init(dev);
 555         if (rc)
 556                 PMD_INIT_LOG(CRIT, "Cannot initialize device");
 557
 558         return rc;
 559 }
 560
 561 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 562                                struct rte_eth_rss_reta_entry64 *reta_conf,
 563                                uint16_t reta_size)
 564 {
 565         struct ena_adapter *adapter =
 566                 (struct ena_adapter *)(dev->data->dev_private);
 567         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 568         int rc, i;
 569         u16 entry_value;
 570         int conf_idx;
 571         int idx;
 572
 573         if ((reta_size == 0) || (reta_conf == NULL))
 574                 return -EINVAL;
 575
 576         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 577                 RTE_LOG(WARNING, PMD,
 578                         "indirection table %d is bigger than supported (%d)\n",
 579                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 580                 return -EINVAL;
 581         }
 582
 583         for (i = 0 ; i < reta_size ; i++) {
 584                 /* each reta_conf is for 64 entries.
 585                  * to support 128 we use 2 conf of 64
 586                  */
 587                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 588                 idx = i % RTE_RETA_GROUP_SIZE;
 589                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 590                         entry_value =
 591                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 592
 593                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 594                                                                i,
 595                                                                entry_value);
 596                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 597                                 RTE_LOG(ERR, PMD,
 598                                         "Cannot fill indirect table\n");
 599                                 return rc;
 600                         }
 601                 }
 602         }
 603
 604         rc = ena_com_indirect_table_set(ena_dev);
 605         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 606                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 607                 return rc;
 608         }
 609
 610         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 611                 __func__, reta_size, adapter->rte_dev->data->port_id);
 612
 613         return 0;
 614 }
 615
 616 /* Query redirection table. */
 617 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 618                               struct rte_eth_rss_reta_entry64 *reta_conf,
 619                               uint16_t reta_size)
 620 {
 621         struct ena_adapter *adapter =
 622                 (struct ena_adapter *)(dev->data->dev_private);
 623         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 624         int rc;
 625         int i;
 626         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 627         int reta_conf_idx;
 628         int reta_idx;
 629
 630         if (reta_size == 0 || reta_conf == NULL ||
 631             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 632                 return -EINVAL;
 633
 634         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 635         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 636                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 637                 return -ENOTSUP;
 638         }
 639
 640         for (i = 0 ; i < reta_size ; i++) {
 641                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 642                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 643                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 644                         reta_conf[reta_conf_idx].reta[reta_idx] =
 645                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 646         }
 647
 648         return 0;
 649 }
 650
 651 static int ena_rss_init_default(struct ena_adapter *adapter)
 652 {
 653         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 654         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 655         int rc, i;
 656         u32 val;
 657
 658         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 659         if (unlikely(rc)) {
 660                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 661                 goto err_rss_init;
 662         }
 663
 664         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 665                 val = i % nb_rx_queues;
 666                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 667                                                        ENA_IO_RXQ_IDX(val));
 668                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 669                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 670                         goto err_fill_indir;
 671                 }
 672         }
 673
 674         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 675                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 676         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 677                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 678                 goto err_fill_indir;
 679         }
 680
 681         rc = ena_com_set_default_hash_ctrl(ena_dev);
 682         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 683                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 684                 goto err_fill_indir;
 685         }
 686
 687         rc = ena_com_indirect_table_set(ena_dev);
 688         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 689                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 690                 goto err_fill_indir;
 691         }
 692         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 693                 adapter->rte_dev->data->port_id);
 694
 695         return 0;
 696
 697 err_fill_indir:
 698         ena_com_rss_destroy(ena_dev);
 699 err_rss_init:
 700
 701         return rc;
 702 }
 703
 704 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 705 {
 706         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 707         int nb_queues = dev->data->nb_rx_queues;
 708         int i;
 709
 710         for (i = 0; i < nb_queues; i++)
 711                 ena_rx_queue_release(queues[i]);
 712 }
 713
 714 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 715 {
 716         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 717         int nb_queues = dev->data->nb_tx_queues;
 718         int i;
 719
 720         for (i = 0; i < nb_queues; i++)
 721                 ena_tx_queue_release(queues[i]);
 722 }
 723
 724 static void ena_rx_queue_release(void *queue)
 725 {
 726         struct ena_ring *ring = (struct ena_ring *)queue;
 727
 728         /* Free ring resources */
 729         if (ring->rx_buffer_info)
 730                 rte_free(ring->rx_buffer_info);
 731         ring->rx_buffer_info = NULL;
 732
 733         if (ring->rx_refill_buffer)
 734                 rte_free(ring->rx_refill_buffer);
 735         ring->rx_refill_buffer = NULL;
 736
 737         if (ring->empty_rx_reqs)
 738                 rte_free(ring->empty_rx_reqs);
 739         ring->empty_rx_reqs = NULL;
 740
 741         ring->configured = 0;
 742
 743         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 744                 ring->port_id, ring->id);
 745 }
 746
 747 static void ena_tx_queue_release(void *queue)
 748 {
 749         struct ena_ring *ring = (struct ena_ring *)queue;
 750
 751         /* Free ring resources */
 752         if (ring->push_buf_intermediate_buf)
 753                 rte_free(ring->push_buf_intermediate_buf);
 754
 755         if (ring->tx_buffer_info)
 756                 rte_free(ring->tx_buffer_info);
 757
 758         if (ring->empty_tx_reqs)
 759                 rte_free(ring->empty_tx_reqs);
 760
 761         ring->empty_tx_reqs = NULL;
 762         ring->tx_buffer_info = NULL;
 763         ring->push_buf_intermediate_buf = NULL;
 764
 765         ring->configured = 0;
 766
 767         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 768                 ring->port_id, ring->id);
 769 }
 770
 771 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 772 {
 773         unsigned int ring_mask = ring->ring_size - 1;
 774
 775         while (ring->next_to_clean != ring->next_to_use) {
 776                 struct rte_mbuf *m =
 777                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 778
 779                 if (m)
 780                         rte_mbuf_raw_free(m);
 781
 782                 ring->next_to_clean++;
 783         }
 784 }
 785
 786 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 787 {
 788         unsigned int i;
 789
 790         for (i = 0; i < ring->ring_size; ++i) {
 791                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 792
 793                 if (tx_buf->mbuf)
 794                         rte_pktmbuf_free(tx_buf->mbuf);
 795
 796                 ring->next_to_clean++;
 797         }
 798 }
 799
 800 static int ena_link_update(struct rte_eth_dev *dev,
 801                            __rte_unused int wait_to_complete)
 802 {
 803         struct rte_eth_link *link = &dev->data->dev_link;
 804         struct ena_adapter *adapter;
 805
 806         adapter = (struct ena_adapter *)(dev->data->dev_private);
 807
 808         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 809         link->link_speed = ETH_SPEED_NUM_NONE;
 810         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 811
 812         return 0;
 813 }
 814
 815 static int ena_queue_start_all(struct rte_eth_dev *dev,
 816                                enum ena_ring_type ring_type)
 817 {
 818         struct ena_adapter *adapter =
 819                 (struct ena_adapter *)(dev->data->dev_private);
 820         struct ena_ring *queues = NULL;
 821         int nb_queues;
 822         int i = 0;
 823         int rc = 0;
 824
 825         if (ring_type == ENA_RING_TYPE_RX) {
 826                 queues = adapter->rx_ring;
 827                 nb_queues = dev->data->nb_rx_queues;
 828         } else {
 829                 queues = adapter->tx_ring;
 830                 nb_queues = dev->data->nb_tx_queues;
 831         }
 832         for (i = 0; i < nb_queues; i++) {
 833                 if (queues[i].configured) {
 834                         if (ring_type == ENA_RING_TYPE_RX) {
 835                                 ena_assert_msg(
 836                                         dev->data->rx_queues[i] == &queues[i],
 837                                         "Inconsistent state of rx queues\n");
 838                         } else {
 839                                 ena_assert_msg(
 840                                         dev->data->tx_queues[i] == &queues[i],
 841                                         "Inconsistent state of tx queues\n");
 842                         }
 843
 844                         rc = ena_queue_start(&queues[i]);
 845
 846                         if (rc) {
 847                                 PMD_INIT_LOG(ERR,
 848                                              "failed to start queue %d type(%d)",
 849                                              i, ring_type);
 850                                 goto err;
 851                         }
 852                 }
 853         }
 854
 855         return 0;
 856
 857 err:
 858         while (i--)
 859                 if (queues[i].configured)
 860                         ena_queue_stop(&queues[i]);
 861
 862         return rc;
 863 }
 864
 865 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 866 {
 867         uint32_t max_frame_len = adapter->max_mtu;
 868
 869         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 870             DEV_RX_OFFLOAD_JUMBO_FRAME)
 871                 max_frame_len =
 872                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 873
 874         return max_frame_len;
 875 }
 876
 877 static int ena_check_valid_conf(struct ena_adapter *adapter)
 878 {
 879         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 880
 881         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 882                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 883                                   "max mtu: %d, min mtu: %d",
 884                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 885                 return ENA_COM_UNSUPPORTED;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int
 892 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 893 {
 894         struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq;
 895         struct ena_com_dev *ena_dev = ctx->ena_dev;
 896         uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX;
 897         uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX;
 898
 899         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 900                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 901                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 902                 rx_queue_size = RTE_MIN(rx_queue_size,
 903                         max_queue_ext->max_rx_cq_depth);
 904                 rx_queue_size = RTE_MIN(rx_queue_size,
 905                         max_queue_ext->max_rx_sq_depth);
 906                 tx_queue_size = RTE_MIN(tx_queue_size,
 907                         max_queue_ext->max_tx_cq_depth);
 908
 909                 if (ena_dev->tx_mem_queue_type ==
 910                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 911                         tx_queue_size = RTE_MIN(tx_queue_size,
 912                                 llq->max_llq_depth);
 913                 } else {
 914                         tx_queue_size = RTE_MIN(tx_queue_size,
 915                                 max_queue_ext->max_tx_sq_depth);
 916                 }
 917
 918                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 919                         max_queue_ext->max_per_packet_rx_descs);
 920                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 921                         max_queue_ext->max_per_packet_tx_descs);
 922         } else {
 923                 struct ena_admin_queue_feature_desc *max_queues =
 924                         &ctx->get_feat_ctx->max_queues;
 925                 rx_queue_size = RTE_MIN(rx_queue_size,
 926                         max_queues->max_cq_depth);
 927                 rx_queue_size = RTE_MIN(rx_queue_size,
 928                         max_queues->max_sq_depth);
 929                 tx_queue_size = RTE_MIN(tx_queue_size,
 930                         max_queues->max_cq_depth);
 931
 932                 if (ena_dev->tx_mem_queue_type ==
 933                     ENA_ADMIN_PLACEMENT_POLICY_DEV) {
 934                         tx_queue_size = RTE_MIN(tx_queue_size,
 935                                 llq->max_llq_depth);
 936                 } else {
 937                         tx_queue_size = RTE_MIN(tx_queue_size,
 938                                 max_queues->max_sq_depth);
 939                 }
 940
 941                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 942                         max_queues->max_packet_tx_descs);
 943                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 944                         max_queues->max_packet_rx_descs);
 945         }
 946
 947         /* Round down to the nearest power of 2 */
 948         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 949         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 950
 951         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 952                 PMD_INIT_LOG(ERR, "Invalid queue size");
 953                 return -EFAULT;
 954         }
 955
 956         ctx->rx_queue_size = rx_queue_size;
 957         ctx->tx_queue_size = tx_queue_size;
 958
 959         return 0;
 960 }
 961
 962 static void ena_stats_restart(struct rte_eth_dev *dev)
 963 {
 964         struct ena_adapter *adapter =
 965                 (struct ena_adapter *)(dev->data->dev_private);
 966
 967         rte_atomic64_init(&adapter->drv_stats->ierrors);
 968         rte_atomic64_init(&adapter->drv_stats->oerrors);
 969         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 970 }
 971
 972 static int ena_stats_get(struct rte_eth_dev *dev,
 973                           struct rte_eth_stats *stats)
 974 {
 975         struct ena_admin_basic_stats ena_stats;
 976         struct ena_adapter *adapter =
 977                 (struct ena_adapter *)(dev->data->dev_private);
 978         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 979         int rc;
 980
 981         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 982                 return -ENOTSUP;
 983
 984         memset(&ena_stats, 0, sizeof(ena_stats));
 985         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
 986         if (unlikely(rc)) {
 987                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n");
 988                 return rc;
 989         }
 990
 991         /* Set of basic statistics from ENA */
 992         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
 993                                           ena_stats.rx_pkts_low);
 994         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
 995                                           ena_stats.tx_pkts_low);
 996         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
 997                                         ena_stats.rx_bytes_low);
 998         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
 999                                         ena_stats.tx_bytes_low);
1000         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1001                                          ena_stats.rx_drops_low);
1002
1003         /* Driver related stats */
1004         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1005         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1006         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1007         return 0;
1008 }
1009
1010 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1011 {
1012         struct ena_adapter *adapter;
1013         struct ena_com_dev *ena_dev;
1014         int rc = 0;
1015
1016         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1017         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1018         adapter = (struct ena_adapter *)(dev->data->dev_private);
1019
1020         ena_dev = &adapter->ena_dev;
1021         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1022
1023         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1024                 RTE_LOG(ERR, PMD,
1025                         "Invalid MTU setting. new_mtu: %d "
1026                         "max mtu: %d min mtu: %d\n",
1027                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1028                 return -EINVAL;
1029         }
1030
1031         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1032         if (rc)
1033                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1034         else
1035                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1036
1037         return rc;
1038 }
1039
1040 static int ena_start(struct rte_eth_dev *dev)
1041 {
1042         struct ena_adapter *adapter =
1043                 (struct ena_adapter *)(dev->data->dev_private);
1044         uint64_t ticks;
1045         int rc = 0;
1046
1047         rc = ena_check_valid_conf(adapter);
1048         if (rc)
1049                 return rc;
1050
1051         rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX);
1052         if (rc)
1053                 return rc;
1054
1055         rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX);
1056         if (rc)
1057                 goto err_start_tx;
1058
1059         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1060             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1061                 rc = ena_rss_init_default(adapter);
1062                 if (rc)
1063                         goto err_rss_init;
1064         }
1065
1066         ena_stats_restart(dev);
1067
1068         adapter->timestamp_wd = rte_get_timer_cycles();
1069         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1070
1071         ticks = rte_get_timer_hz();
1072         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1073                         ena_timer_wd_callback, adapter);
1074
1075         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1076
1077         return 0;
1078
1079 err_rss_init:
1080         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1081 err_start_tx:
1082         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1083         return rc;
1084 }
1085
1086 static void ena_stop(struct rte_eth_dev *dev)
1087 {
1088         struct ena_adapter *adapter =
1089                 (struct ena_adapter *)(dev->data->dev_private);
1090         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1091         int rc;
1092
1093         rte_timer_stop_sync(&adapter->timer_wd);
1094         ena_queue_stop_all(dev, ENA_RING_TYPE_TX);
1095         ena_queue_stop_all(dev, ENA_RING_TYPE_RX);
1096
1097         if (adapter->trigger_reset) {
1098                 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
1099                 if (rc)
1100                         RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc);
1101         }
1102
1103         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1104 }
1105
1106 static int ena_create_io_queue(struct ena_ring *ring)
1107 {
1108         struct ena_adapter *adapter;
1109         struct ena_com_dev *ena_dev;
1110         struct ena_com_create_io_ctx ctx =
1111                 /* policy set to _HOST just to satisfy icc compiler */
1112                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1113                   0, 0, 0, 0, 0 };
1114         uint16_t ena_qid;
1115         unsigned int i;
1116         int rc;
1117
1118         adapter = ring->adapter;
1119         ena_dev = &adapter->ena_dev;
1120
1121         if (ring->type == ENA_RING_TYPE_TX) {
1122                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1123                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1124                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1125                 ctx.queue_size = adapter->tx_ring_size;
1126                 for (i = 0; i < ring->ring_size; i++)
1127                         ring->empty_tx_reqs[i] = i;
1128         } else {
1129                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1130                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1131                 ctx.queue_size = adapter->rx_ring_size;
1132                 for (i = 0; i < ring->ring_size; i++)
1133                         ring->empty_rx_reqs[i] = i;
1134         }
1135         ctx.qid = ena_qid;
1136         ctx.msix_vector = -1; /* interrupts not used */
1137         ctx.numa_node = ena_cpu_to_node(ring->id);
1138
1139         rc = ena_com_create_io_queue(ena_dev, &ctx);
1140         if (rc) {
1141                 RTE_LOG(ERR, PMD,
1142                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1143                         ring->id, ena_qid, rc);
1144                 return rc;
1145         }
1146
1147         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1148                                      &ring->ena_com_io_sq,
1149                                      &ring->ena_com_io_cq);
1150         if (rc) {
1151                 RTE_LOG(ERR, PMD,
1152                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1153                         ring->id, rc);
1154                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1155                 return rc;
1156         }
1157
1158         if (ring->type == ENA_RING_TYPE_TX)
1159                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1160
1161         return 0;
1162 }
1163
1164 static void ena_queue_stop(struct ena_ring *ring)
1165 {
1166         struct ena_com_dev *ena_dev = &ring->adapter->ena_dev;
1167
1168         if (ring->type == ENA_RING_TYPE_RX) {
1169                 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id));
1170                 ena_rx_queue_release_bufs(ring);
1171         } else {
1172                 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id));
1173                 ena_tx_queue_release_bufs(ring);
1174         }
1175 }
1176
1177 static void ena_queue_stop_all(struct rte_eth_dev *dev,
1178                               enum ena_ring_type ring_type)
1179 {
1180         struct ena_adapter *adapter =
1181                 (struct ena_adapter *)(dev->data->dev_private);
1182         struct ena_ring *queues = NULL;
1183         uint16_t nb_queues, i;
1184
1185         if (ring_type == ENA_RING_TYPE_RX) {
1186                 queues = adapter->rx_ring;
1187                 nb_queues = dev->data->nb_rx_queues;
1188         } else {
1189                 queues = adapter->tx_ring;
1190                 nb_queues = dev->data->nb_tx_queues;
1191         }
1192
1193         for (i = 0; i < nb_queues; ++i)
1194                 if (queues[i].configured)
1195                         ena_queue_stop(&queues[i]);
1196 }
1197
1198 static int ena_queue_start(struct ena_ring *ring)
1199 {
1200         int rc, bufs_num;
1201
1202         ena_assert_msg(ring->configured == 1,
1203                        "Trying to start unconfigured queue\n");
1204
1205         rc = ena_create_io_queue(ring);
1206         if (rc) {
1207                 PMD_INIT_LOG(ERR, "Failed to create IO queue!");
1208                 return rc;
1209         }
1210
1211         ring->next_to_clean = 0;
1212         ring->next_to_use = 0;
1213
1214         if (ring->type == ENA_RING_TYPE_TX)
1215                 return 0;
1216
1217         bufs_num = ring->ring_size - 1;
1218         rc = ena_populate_rx_queue(ring, bufs_num);
1219         if (rc != bufs_num) {
1220                 ena_com_destroy_io_queue(&ring->adapter->ena_dev,
1221                                          ENA_IO_RXQ_IDX(ring->id));
1222                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1223                 return ENA_COM_FAULT;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1230                               uint16_t queue_idx,
1231                               uint16_t nb_desc,
1232                               __rte_unused unsigned int socket_id,
1233                               const struct rte_eth_txconf *tx_conf)
1234 {
1235         struct ena_ring *txq = NULL;
1236         struct ena_adapter *adapter =
1237                 (struct ena_adapter *)(dev->data->dev_private);
1238         unsigned int i;
1239
1240         txq = &adapter->tx_ring[queue_idx];
1241
1242         if (txq->configured) {
1243                 RTE_LOG(CRIT, PMD,
1244                         "API violation. Queue %d is already configured\n",
1245                         queue_idx);
1246                 return ENA_COM_FAULT;
1247         }
1248
1249         if (!rte_is_power_of_2(nb_desc)) {
1250                 RTE_LOG(ERR, PMD,
1251                         "Unsupported size of TX queue: %d is not a power of 2.\n",
1252                         nb_desc);
1253                 return -EINVAL;
1254         }
1255
1256         if (nb_desc > adapter->tx_ring_size) {
1257                 RTE_LOG(ERR, PMD,
1258                         "Unsupported size of TX queue (max size: %d)\n",
1259                         adapter->tx_ring_size);
1260                 return -EINVAL;
1261         }
1262
1263         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1264                 nb_desc = adapter->tx_ring_size;
1265
1266         txq->port_id = dev->data->port_id;
1267         txq->next_to_clean = 0;
1268         txq->next_to_use = 0;
1269         txq->ring_size = nb_desc;
1270
1271         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1272                                           sizeof(struct ena_tx_buffer) *
1273                                           txq->ring_size,
1274                                           RTE_CACHE_LINE_SIZE);
1275         if (!txq->tx_buffer_info) {
1276                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1277                 return -ENOMEM;
1278         }
1279
1280         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1281                                          sizeof(u16) * txq->ring_size,
1282                                          RTE_CACHE_LINE_SIZE);
1283         if (!txq->empty_tx_reqs) {
1284                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1285                 rte_free(txq->tx_buffer_info);
1286                 return -ENOMEM;
1287         }
1288
1289         txq->push_buf_intermediate_buf =
1290                 rte_zmalloc("txq->push_buf_intermediate_buf",
1291                             txq->tx_max_header_size,
1292                             RTE_CACHE_LINE_SIZE);
1293         if (!txq->push_buf_intermediate_buf) {
1294                 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n");
1295                 rte_free(txq->tx_buffer_info);
1296                 rte_free(txq->empty_tx_reqs);
1297                 return -ENOMEM;
1298         }
1299
1300         for (i = 0; i < txq->ring_size; i++)
1301                 txq->empty_tx_reqs[i] = i;
1302
1303         if (tx_conf != NULL) {
1304                 txq->offloads =
1305                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1306         }
1307
1308         /* Store pointer to this queue in upper layer */
1309         txq->configured = 1;
1310         dev->data->tx_queues[queue_idx] = txq;
1311
1312         return 0;
1313 }
1314
1315 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1316                               uint16_t queue_idx,
1317                               uint16_t nb_desc,
1318                               __rte_unused unsigned int socket_id,
1319                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1320                               struct rte_mempool *mp)
1321 {
1322         struct ena_adapter *adapter =
1323                 (struct ena_adapter *)(dev->data->dev_private);
1324         struct ena_ring *rxq = NULL;
1325         int i;
1326
1327         rxq = &adapter->rx_ring[queue_idx];
1328         if (rxq->configured) {
1329                 RTE_LOG(CRIT, PMD,
1330                         "API violation. Queue %d is already configured\n",
1331                         queue_idx);
1332                 return ENA_COM_FAULT;
1333         }
1334
1335         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1336                 nb_desc = adapter->rx_ring_size;
1337
1338         if (!rte_is_power_of_2(nb_desc)) {
1339                 RTE_LOG(ERR, PMD,
1340                         "Unsupported size of RX queue: %d is not a power of 2.\n",
1341                         nb_desc);
1342                 return -EINVAL;
1343         }
1344
1345         if (nb_desc > adapter->rx_ring_size) {
1346                 RTE_LOG(ERR, PMD,
1347                         "Unsupported size of RX queue (max size: %d)\n",
1348                         adapter->rx_ring_size);
1349                 return -EINVAL;
1350         }
1351
1352         rxq->port_id = dev->data->port_id;
1353         rxq->next_to_clean = 0;
1354         rxq->next_to_use = 0;
1355         rxq->ring_size = nb_desc;
1356         rxq->mb_pool = mp;
1357
1358         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1359                                           sizeof(struct rte_mbuf *) * nb_desc,
1360                                           RTE_CACHE_LINE_SIZE);
1361         if (!rxq->rx_buffer_info) {
1362                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1363                 return -ENOMEM;
1364         }
1365
1366         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1367                                             sizeof(struct rte_mbuf *) * nb_desc,
1368                                             RTE_CACHE_LINE_SIZE);
1369
1370         if (!rxq->rx_refill_buffer) {
1371                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1372                 rte_free(rxq->rx_buffer_info);
1373                 rxq->rx_buffer_info = NULL;
1374                 return -ENOMEM;
1375         }
1376
1377         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1378                                          sizeof(uint16_t) * nb_desc,
1379                                          RTE_CACHE_LINE_SIZE);
1380         if (!rxq->empty_rx_reqs) {
1381                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1382                 rte_free(rxq->rx_buffer_info);
1383                 rxq->rx_buffer_info = NULL;
1384                 rte_free(rxq->rx_refill_buffer);
1385                 rxq->rx_refill_buffer = NULL;
1386                 return -ENOMEM;
1387         }
1388
1389         for (i = 0; i < nb_desc; i++)
1390                 rxq->empty_rx_reqs[i] = i;
1391
1392         /* Store pointer to this queue in upper layer */
1393         rxq->configured = 1;
1394         dev->data->rx_queues[queue_idx] = rxq;
1395
1396         return 0;
1397 }
1398
1399 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1400 {
1401         unsigned int i;
1402         int rc;
1403         uint16_t ring_size = rxq->ring_size;
1404         uint16_t ring_mask = ring_size - 1;
1405         uint16_t next_to_use = rxq->next_to_use;
1406         uint16_t in_use, req_id;
1407         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1408
1409         if (unlikely(!count))
1410                 return 0;
1411
1412         in_use = rxq->next_to_use - rxq->next_to_clean;
1413         ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n");
1414
1415         /* get resources for incoming packets */
1416         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1417         if (unlikely(rc < 0)) {
1418                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1419                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1420                 return 0;
1421         }
1422
1423         for (i = 0; i < count; i++) {
1424                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1425                 struct rte_mbuf *mbuf = mbufs[i];
1426                 struct ena_com_buf ebuf;
1427
1428                 if (likely((i + 4) < count))
1429                         rte_prefetch0(mbufs[i + 4]);
1430
1431                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1432                 rc = validate_rx_req_id(rxq, req_id);
1433                 if (unlikely(rc < 0))
1434                         break;
1435                 rxq->rx_buffer_info[req_id] = mbuf;
1436
1437                 /* prepare physical address for DMA transaction */
1438                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1439                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1440                 /* pass resource to device */
1441                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1442                                                 &ebuf, req_id);
1443                 if (unlikely(rc)) {
1444                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1445                         rxq->rx_buffer_info[req_id] = NULL;
1446                         break;
1447                 }
1448                 next_to_use++;
1449         }
1450
1451         if (unlikely(i < count)) {
1452                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1453                         "buffers (from %d)\n", rxq->id, i, count);
1454                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1455                                      count - i);
1456         }
1457
1458         /* When we submitted free recources to device... */
1459         if (likely(i > 0)) {
1460                 /* ...let HW know that it can fill buffers with data
1461                  *
1462                  * Add memory barrier to make sure the desc were written before
1463                  * issue a doorbell
1464                  */
1465                 rte_wmb();
1466                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1467
1468                 rxq->next_to_use = next_to_use;
1469         }
1470
1471         return i;
1472 }
1473
1474 static int ena_device_init(struct ena_com_dev *ena_dev,
1475                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1476                            bool *wd_state)
1477 {
1478         uint32_t aenq_groups;
1479         int rc;
1480         bool readless_supported;
1481
1482         /* Initialize mmio registers */
1483         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1484         if (rc) {
1485                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1486                 return rc;
1487         }
1488
1489         /* The PCIe configuration space revision id indicate if mmio reg
1490          * read is disabled.
1491          */
1492         readless_supported =
1493                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1494                                & ENA_MMIO_DISABLE_REG_READ);
1495         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1496
1497         /* reset device */
1498         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1499         if (rc) {
1500                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1501                 goto err_mmio_read_less;
1502         }
1503
1504         /* check FW version */
1505         rc = ena_com_validate_version(ena_dev);
1506         if (rc) {
1507                 RTE_LOG(ERR, PMD, "device version is too low\n");
1508                 goto err_mmio_read_less;
1509         }
1510
1511         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1512
1513         /* ENA device administration layer init */
1514         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1515         if (rc) {
1516                 RTE_LOG(ERR, PMD,
1517                         "cannot initialize ena admin queue with device\n");
1518                 goto err_mmio_read_less;
1519         }
1520
1521         /* To enable the msix interrupts the driver needs to know the number
1522          * of queues. So the driver uses polling mode to retrieve this
1523          * information.
1524          */
1525         ena_com_set_admin_polling_mode(ena_dev, true);
1526
1527         ena_config_host_info(ena_dev);
1528
1529         /* Get Device Attributes and features */
1530         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1531         if (rc) {
1532                 RTE_LOG(ERR, PMD,
1533                         "cannot get attribute for ena device rc= %d\n", rc);
1534                 goto err_admin_init;
1535         }
1536
1537         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1538                       BIT(ENA_ADMIN_NOTIFICATION) |
1539                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1540                       BIT(ENA_ADMIN_FATAL_ERROR) |
1541                       BIT(ENA_ADMIN_WARNING);
1542
1543         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1544         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1545         if (rc) {
1546                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1547                 goto err_admin_init;
1548         }
1549
1550         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1551
1552         return 0;
1553
1554 err_admin_init:
1555         ena_com_admin_destroy(ena_dev);
1556
1557 err_mmio_read_less:
1558         ena_com_mmio_reg_read_request_destroy(ena_dev);
1559
1560         return rc;
1561 }
1562
1563 static void ena_interrupt_handler_rte(void *cb_arg)
1564 {
1565         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1566         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1567
1568         ena_com_admin_q_comp_intr_handler(ena_dev);
1569         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1570                 ena_com_aenq_intr_handler(ena_dev, adapter);
1571 }
1572
1573 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1574 {
1575         if (!adapter->wd_state)
1576                 return;
1577
1578         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1579                 return;
1580
1581         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1582             adapter->keep_alive_timeout)) {
1583                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1584                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1585                 adapter->trigger_reset = true;
1586         }
1587 }
1588
1589 /* Check if admin queue is enabled */
1590 static void check_for_admin_com_state(struct ena_adapter *adapter)
1591 {
1592         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1593                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1594                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1595                 adapter->trigger_reset = true;
1596         }
1597 }
1598
1599 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1600                                   void *arg)
1601 {
1602         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1603         struct rte_eth_dev *dev = adapter->rte_dev;
1604
1605         check_for_missing_keep_alive(adapter);
1606         check_for_admin_com_state(adapter);
1607
1608         if (unlikely(adapter->trigger_reset)) {
1609                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1610                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1611                         NULL);
1612         }
1613 }
1614
1615 static inline void
1616 set_default_llq_configurations(struct ena_llq_configurations *llq_config)
1617 {
1618         llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER;
1619         llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
1620         llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
1621         llq_config->llq_num_decs_before_header =
1622                 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
1623         llq_config->llq_ring_entry_size_value = 128;
1624 }
1625
1626 static int
1627 ena_set_queues_placement_policy(struct ena_adapter *adapter,
1628                                 struct ena_com_dev *ena_dev,
1629                                 struct ena_admin_feature_llq_desc *llq,
1630                                 struct ena_llq_configurations *llq_default_configurations)
1631 {
1632         int rc;
1633         u32 llq_feature_mask;
1634
1635         llq_feature_mask = 1 << ENA_ADMIN_LLQ;
1636         if (!(ena_dev->supported_features & llq_feature_mask)) {
1637                 RTE_LOG(INFO, PMD,
1638                         "LLQ is not supported. Fallback to host mode policy.\n");
1639                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1640                 return 0;
1641         }
1642
1643         rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations);
1644         if (unlikely(rc)) {
1645                 PMD_INIT_LOG(WARNING, "Failed to config dev mode. "
1646                         "Fallback to host mode policy.");
1647                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1648                 return 0;
1649         }
1650
1651         /* Nothing to config, exit */
1652         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1653                 return 0;
1654
1655         if (!adapter->dev_mem_base) {
1656                 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. "
1657                         "Fallback to host mode policy.\n.");
1658                 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1659                 return 0;
1660         }
1661
1662         ena_dev->mem_bar = adapter->dev_mem_base;
1663
1664         return 0;
1665 }
1666
1667 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1668                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1669 {
1670         uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num;
1671
1672         /* Regular queues capabilities */
1673         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1674                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1675                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1676                 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num,
1677                                     max_queue_ext->max_rx_cq_num);
1678                 io_tx_sq_num = max_queue_ext->max_tx_sq_num;
1679                 io_tx_cq_num = max_queue_ext->max_tx_cq_num;
1680         } else {
1681                 struct ena_admin_queue_feature_desc *max_queues =
1682                         &get_feat_ctx->max_queues;
1683                 io_tx_sq_num = max_queues->max_sq_num;
1684                 io_tx_cq_num = max_queues->max_cq_num;
1685                 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num);
1686         }
1687
1688         /* In case of LLQ use the llq number in the get feature cmd */
1689         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
1690                 io_tx_sq_num = get_feat_ctx->llq.max_llq_num;
1691
1692         io_queue_num = RTE_MIN(rte_lcore_count(), ENA_MAX_NUM_IO_QUEUES);
1693         io_queue_num = RTE_MIN(io_queue_num, io_rx_num);
1694         io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num);
1695         io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num);
1696
1697         if (unlikely(io_queue_num == 0)) {
1698                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1699                 return -EFAULT;
1700         }
1701
1702         return io_queue_num;
1703 }
1704
1705 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1706 {
1707         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1708         struct rte_pci_device *pci_dev;
1709         struct rte_intr_handle *intr_handle;
1710         struct ena_adapter *adapter =
1711                 (struct ena_adapter *)(eth_dev->data->dev_private);
1712         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1713         struct ena_com_dev_get_features_ctx get_feat_ctx;
1714         struct ena_llq_configurations llq_config;
1715         const char *queue_type_str;
1716         int rc;
1717
1718         static int adapters_found;
1719         bool wd_state;
1720
1721         memset(adapter, 0, sizeof(struct ena_adapter));
1722         ena_dev = &adapter->ena_dev;
1723
1724         eth_dev->dev_ops = &ena_dev_ops;
1725         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1726         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1727         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1728         adapter->rte_eth_dev_data = eth_dev->data;
1729         adapter->rte_dev = eth_dev;
1730
1731         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1732                 return 0;
1733
1734         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1735         adapter->pdev = pci_dev;
1736
1737         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1738                      pci_dev->addr.domain,
1739                      pci_dev->addr.bus,
1740                      pci_dev->addr.devid,
1741                      pci_dev->addr.function);
1742
1743         intr_handle = &pci_dev->intr_handle;
1744
1745         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1746         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1747
1748         if (!adapter->regs) {
1749                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1750                              ENA_REGS_BAR);
1751                 return -ENXIO;
1752         }
1753
1754         ena_dev->reg_bar = adapter->regs;
1755         ena_dev->dmadev = adapter->pdev;
1756
1757         adapter->id_number = adapters_found;
1758
1759         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1760                  adapter->id_number);
1761
1762         /* device specific initialization routine */
1763         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1764         if (rc) {
1765                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1766                 goto err;
1767         }
1768         adapter->wd_state = wd_state;
1769
1770         set_default_llq_configurations(&llq_config);
1771         rc = ena_set_queues_placement_policy(adapter, ena_dev,
1772                                              &get_feat_ctx.llq, &llq_config);
1773         if (unlikely(rc)) {
1774                 PMD_INIT_LOG(CRIT, "Failed to set placement policy");
1775                 return rc;
1776         }
1777
1778         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
1779                 queue_type_str = "Regular";
1780         else
1781                 queue_type_str = "Low latency";
1782         RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str);
1783
1784         calc_queue_ctx.ena_dev = ena_dev;
1785         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1786         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1787                                                     &get_feat_ctx);
1788
1789         rc = ena_calc_queue_size(&calc_queue_ctx);
1790         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1791                 rc = -EFAULT;
1792                 goto err_device_destroy;
1793         }
1794
1795         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1796         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1797
1798         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1799         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1800
1801         /* prepare ring structures */
1802         ena_init_rings(adapter);
1803
1804         ena_config_debug_area(adapter);
1805
1806         /* Set max MTU for this device */
1807         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1808
1809         /* set device support for TSO */
1810         adapter->tso4_supported = get_feat_ctx.offload.tx &
1811                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1812
1813         /* Copy MAC address and point DPDK to it */
1814         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1815         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1816                         (struct ether_addr *)adapter->mac_addr);
1817
1818         /*
1819          * Pass the information to the rte_eth_dev_close() that it should also
1820          * release the private port resources.
1821          */
1822         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1823
1824         adapter->drv_stats = rte_zmalloc("adapter stats",
1825                                          sizeof(*adapter->drv_stats),
1826                                          RTE_CACHE_LINE_SIZE);
1827         if (!adapter->drv_stats) {
1828                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1829                 rc = -ENOMEM;
1830                 goto err_delete_debug_area;
1831         }
1832
1833         rte_intr_callback_register(intr_handle,
1834                                    ena_interrupt_handler_rte,
1835                                    adapter);
1836         rte_intr_enable(intr_handle);
1837         ena_com_set_admin_polling_mode(ena_dev, false);
1838         ena_com_admin_aenq_enable(ena_dev);
1839
1840         if (adapters_found == 0)
1841                 rte_timer_subsystem_init();
1842         rte_timer_init(&adapter->timer_wd);
1843
1844         adapters_found++;
1845         adapter->state = ENA_ADAPTER_STATE_INIT;
1846
1847         return 0;
1848
1849 err_delete_debug_area:
1850         ena_com_delete_debug_area(ena_dev);
1851
1852 err_device_destroy:
1853         ena_com_delete_host_info(ena_dev);
1854         ena_com_admin_destroy(ena_dev);
1855
1856 err:
1857         return rc;
1858 }
1859
1860 static void ena_destroy_device(struct rte_eth_dev *eth_dev)
1861 {
1862         struct ena_adapter *adapter =
1863                 (struct ena_adapter *)(eth_dev->data->dev_private);
1864         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1865
1866         if (adapter->state == ENA_ADAPTER_STATE_FREE)
1867                 return;
1868
1869         ena_com_set_admin_running_state(ena_dev, false);
1870
1871         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1872                 ena_close(eth_dev);
1873
1874         ena_com_delete_debug_area(ena_dev);
1875         ena_com_delete_host_info(ena_dev);
1876
1877         ena_com_abort_admin_commands(ena_dev);
1878         ena_com_wait_for_abort_completion(ena_dev);
1879         ena_com_admin_destroy(ena_dev);
1880         ena_com_mmio_reg_read_request_destroy(ena_dev);
1881
1882         adapter->state = ENA_ADAPTER_STATE_FREE;
1883 }
1884
1885 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1886 {
1887         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1888                 return 0;
1889
1890         ena_destroy_device(eth_dev);
1891
1892         eth_dev->dev_ops = NULL;
1893         eth_dev->rx_pkt_burst = NULL;
1894         eth_dev->tx_pkt_burst = NULL;
1895         eth_dev->tx_pkt_prepare = NULL;
1896
1897         return 0;
1898 }
1899
1900 static int ena_dev_configure(struct rte_eth_dev *dev)
1901 {
1902         struct ena_adapter *adapter =
1903                 (struct ena_adapter *)(dev->data->dev_private);
1904
1905         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1906
1907         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1908         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1909         return 0;
1910 }
1911
1912 static void ena_init_rings(struct ena_adapter *adapter)
1913 {
1914         int i;
1915
1916         for (i = 0; i < adapter->num_queues; i++) {
1917                 struct ena_ring *ring = &adapter->tx_ring[i];
1918
1919                 ring->configured = 0;
1920                 ring->type = ENA_RING_TYPE_TX;
1921                 ring->adapter = adapter;
1922                 ring->id = i;
1923                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1924                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1925                 ring->sgl_size = adapter->max_tx_sgl_size;
1926         }
1927
1928         for (i = 0; i < adapter->num_queues; i++) {
1929                 struct ena_ring *ring = &adapter->rx_ring[i];
1930
1931                 ring->configured = 0;
1932                 ring->type = ENA_RING_TYPE_RX;
1933                 ring->adapter = adapter;
1934                 ring->id = i;
1935                 ring->sgl_size = adapter->max_rx_sgl_size;
1936         }
1937 }
1938
1939 static void ena_infos_get(struct rte_eth_dev *dev,
1940                           struct rte_eth_dev_info *dev_info)
1941 {
1942         struct ena_adapter *adapter;
1943         struct ena_com_dev *ena_dev;
1944         struct ena_com_dev_get_features_ctx feat;
1945         uint64_t rx_feat = 0, tx_feat = 0;
1946         int rc = 0;
1947
1948         ena_assert_msg(dev->data != NULL, "Uninitialized device\n");
1949         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n");
1950         adapter = (struct ena_adapter *)(dev->data->dev_private);
1951
1952         ena_dev = &adapter->ena_dev;
1953         ena_assert_msg(ena_dev != NULL, "Uninitialized device\n");
1954
1955         dev_info->speed_capa =
1956                         ETH_LINK_SPEED_1G   |
1957                         ETH_LINK_SPEED_2_5G |
1958                         ETH_LINK_SPEED_5G   |
1959                         ETH_LINK_SPEED_10G  |
1960                         ETH_LINK_SPEED_25G  |
1961                         ETH_LINK_SPEED_40G  |
1962                         ETH_LINK_SPEED_50G  |
1963                         ETH_LINK_SPEED_100G;
1964
1965         /* Get supported features from HW */
1966         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1967         if (unlikely(rc)) {
1968                 RTE_LOG(ERR, PMD,
1969                         "Cannot get attribute for ena device rc= %d\n", rc);
1970                 return;
1971         }
1972
1973         /* Set Tx & Rx features available for device */
1974         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1975                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1976
1977         if (feat.offload.tx &
1978             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1979                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1980                         DEV_TX_OFFLOAD_UDP_CKSUM |
1981                         DEV_TX_OFFLOAD_TCP_CKSUM;
1982
1983         if (feat.offload.rx_supported &
1984             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1985                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1986                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1987                         DEV_RX_OFFLOAD_TCP_CKSUM;
1988
1989         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1990
1991         /* Inform framework about available features */
1992         dev_info->rx_offload_capa = rx_feat;
1993         dev_info->rx_queue_offload_capa = rx_feat;
1994         dev_info->tx_offload_capa = tx_feat;
1995         dev_info->tx_queue_offload_capa = tx_feat;
1996
1997         dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP |
1998                                            ETH_RSS_UDP;
1999
2000         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
2001         dev_info->max_rx_pktlen  = adapter->max_mtu;
2002         dev_info->max_mac_addrs = 1;
2003
2004         dev_info->max_rx_queues = adapter->num_queues;
2005         dev_info->max_tx_queues = adapter->num_queues;
2006         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
2007
2008         adapter->tx_supported_offloads = tx_feat;
2009         adapter->rx_supported_offloads = rx_feat;
2010
2011         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
2012         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2013         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2014                                         adapter->max_rx_sgl_size);
2015         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2016                                         adapter->max_rx_sgl_size);
2017
2018         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
2019         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
2020         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2021                                         adapter->max_tx_sgl_size);
2022         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
2023                                         adapter->max_tx_sgl_size);
2024 }
2025
2026 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
2027                                   uint16_t nb_pkts)
2028 {
2029         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
2030         unsigned int ring_size = rx_ring->ring_size;
2031         unsigned int ring_mask = ring_size - 1;
2032         uint16_t next_to_clean = rx_ring->next_to_clean;
2033         uint16_t desc_in_use = 0;
2034         uint16_t req_id;
2035         unsigned int recv_idx = 0;
2036         struct rte_mbuf *mbuf = NULL;
2037         struct rte_mbuf *mbuf_head = NULL;
2038         struct rte_mbuf *mbuf_prev = NULL;
2039         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
2040         unsigned int completed;
2041
2042         struct ena_com_rx_ctx ena_rx_ctx;
2043         int rc = 0;
2044
2045         /* Check adapter state */
2046         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2047                 RTE_LOG(ALERT, PMD,
2048                         "Trying to receive pkts while device is NOT running\n");
2049                 return 0;
2050         }
2051
2052         desc_in_use = rx_ring->next_to_use - next_to_clean;
2053         if (unlikely(nb_pkts > desc_in_use))
2054                 nb_pkts = desc_in_use;
2055
2056         for (completed = 0; completed < nb_pkts; completed++) {
2057                 int segments = 0;
2058
2059                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
2060                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
2061                 ena_rx_ctx.descs = 0;
2062                 /* receive packet context */
2063                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
2064                                     rx_ring->ena_com_io_sq,
2065                                     &ena_rx_ctx);
2066                 if (unlikely(rc)) {
2067                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
2068                         rx_ring->adapter->reset_reason =
2069                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
2070                         rx_ring->adapter->trigger_reset = true;
2071                         return 0;
2072                 }
2073
2074                 if (unlikely(ena_rx_ctx.descs == 0))
2075                         break;
2076
2077                 while (segments < ena_rx_ctx.descs) {
2078                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
2079                         rc = validate_rx_req_id(rx_ring, req_id);
2080                         if (unlikely(rc))
2081                                 break;
2082
2083                         mbuf = rx_buff_info[req_id];
2084                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
2085                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2086                         mbuf->refcnt = 1;
2087                         mbuf->next = NULL;
2088                         if (unlikely(segments == 0)) {
2089                                 mbuf->nb_segs = ena_rx_ctx.descs;
2090                                 mbuf->port = rx_ring->port_id;
2091                                 mbuf->pkt_len = 0;
2092                                 mbuf_head = mbuf;
2093                         } else {
2094                                 /* for multi-segment pkts create mbuf chain */
2095                                 mbuf_prev->next = mbuf;
2096                         }
2097                         mbuf_head->pkt_len += mbuf->data_len;
2098
2099                         mbuf_prev = mbuf;
2100                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
2101                                 req_id;
2102                         segments++;
2103                         next_to_clean++;
2104                 }
2105                 if (unlikely(rc))
2106                         break;
2107
2108                 /* fill mbuf attributes if any */
2109                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
2110                 mbuf_head->hash.rss = ena_rx_ctx.hash;
2111
2112                 /* pass to DPDK application head mbuf */
2113                 rx_pkts[recv_idx] = mbuf_head;
2114                 recv_idx++;
2115         }
2116
2117         rx_ring->next_to_clean = next_to_clean;
2118
2119         desc_in_use = desc_in_use - completed + 1;
2120         /* Burst refill to save doorbells, memory barriers, const interval */
2121         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2122                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2123
2124         return recv_idx;
2125 }
2126
2127 static uint16_t
2128 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2129                 uint16_t nb_pkts)
2130 {
2131         int32_t ret;
2132         uint32_t i;
2133         struct rte_mbuf *m;
2134         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2135         struct ipv4_hdr *ip_hdr;
2136         uint64_t ol_flags;
2137         uint16_t frag_field;
2138
2139         for (i = 0; i != nb_pkts; i++) {
2140                 m = tx_pkts[i];
2141                 ol_flags = m->ol_flags;
2142
2143                 if (!(ol_flags & PKT_TX_IPV4))
2144                         continue;
2145
2146                 /* If there was not L2 header length specified, assume it is
2147                  * length of the ethernet header.
2148                  */
2149                 if (unlikely(m->l2_len == 0))
2150                         m->l2_len = sizeof(struct ether_hdr);
2151
2152                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2153                                                  m->l2_len);
2154                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2155
2156                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2157                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2158
2159                         /* If IPv4 header has DF flag enabled and TSO support is
2160                          * disabled, partial chcecksum should not be calculated.
2161                          */
2162                         if (!tx_ring->adapter->tso4_supported)
2163                                 continue;
2164                 }
2165
2166                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2167                                 (ol_flags & PKT_TX_L4_MASK) ==
2168                                 PKT_TX_SCTP_CKSUM) {
2169                         rte_errno = -ENOTSUP;
2170                         return i;
2171                 }
2172
2173 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2174                 ret = rte_validate_tx_offload(m);
2175                 if (ret != 0) {
2176                         rte_errno = ret;
2177                         return i;
2178                 }
2179 #endif
2180
2181                 /* In case we are supposed to TSO and have DF not set (DF=0)
2182                  * hardware must be provided with partial checksum, otherwise
2183                  * it will take care of necessary calculations.
2184                  */
2185
2186                 ret = rte_net_intel_cksum_flags_prepare(m,
2187                         ol_flags & ~PKT_TX_TCP_SEG);
2188                 if (ret != 0) {
2189                         rte_errno = ret;
2190                         return i;
2191                 }
2192         }
2193
2194         return i;
2195 }
2196
2197 static void ena_update_hints(struct ena_adapter *adapter,
2198                              struct ena_admin_ena_hw_hints *hints)
2199 {
2200         if (hints->admin_completion_tx_timeout)
2201                 adapter->ena_dev.admin_queue.completion_timeout =
2202                         hints->admin_completion_tx_timeout * 1000;
2203
2204         if (hints->mmio_read_timeout)
2205                 /* convert to usec */
2206                 adapter->ena_dev.mmio_read.reg_read_to =
2207                         hints->mmio_read_timeout * 1000;
2208
2209         if (hints->driver_watchdog_timeout) {
2210                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2211                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2212                 else
2213                         // Convert msecs to ticks
2214                         adapter->keep_alive_timeout =
2215                                 (hints->driver_watchdog_timeout *
2216                                 rte_get_timer_hz()) / 1000;
2217         }
2218 }
2219
2220 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2221                                         struct rte_mbuf *mbuf)
2222 {
2223         struct ena_com_dev *ena_dev;
2224         int num_segments, header_len, rc;
2225
2226         ena_dev = &tx_ring->adapter->ena_dev;
2227         num_segments = mbuf->nb_segs;
2228         header_len = mbuf->data_len;
2229
2230         if (likely(num_segments < tx_ring->sgl_size))
2231                 return 0;
2232
2233         if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV &&
2234             (num_segments == tx_ring->sgl_size) &&
2235             (header_len < tx_ring->tx_max_header_size))
2236                 return 0;
2237
2238         rc = rte_pktmbuf_linearize(mbuf);
2239         if (unlikely(rc))
2240                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2241
2242         return rc;
2243 }
2244
2245 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2246                                   uint16_t nb_pkts)
2247 {
2248         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2249         uint16_t next_to_use = tx_ring->next_to_use;
2250         uint16_t next_to_clean = tx_ring->next_to_clean;
2251         struct rte_mbuf *mbuf;
2252         uint16_t seg_len;
2253         unsigned int ring_size = tx_ring->ring_size;
2254         unsigned int ring_mask = ring_size - 1;
2255         struct ena_com_tx_ctx ena_tx_ctx;
2256         struct ena_tx_buffer *tx_info;
2257         struct ena_com_buf *ebuf;
2258         uint16_t rc, req_id, total_tx_descs = 0;
2259         uint16_t sent_idx = 0, empty_tx_reqs;
2260         uint16_t push_len = 0;
2261         uint16_t delta = 0;
2262         int nb_hw_desc;
2263
2264         /* Check adapter state */
2265         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2266                 RTE_LOG(ALERT, PMD,
2267                         "Trying to xmit pkts while device is NOT running\n");
2268                 return 0;
2269         }
2270
2271         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2272         if (nb_pkts > empty_tx_reqs)
2273                 nb_pkts = empty_tx_reqs;
2274
2275         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2276                 mbuf = tx_pkts[sent_idx];
2277
2278                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2279                 if (unlikely(rc))
2280                         break;
2281
2282                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2283                 tx_info = &tx_ring->tx_buffer_info[req_id];
2284                 tx_info->mbuf = mbuf;
2285                 tx_info->num_of_bufs = 0;
2286                 ebuf = tx_info->bufs;
2287
2288                 /* Prepare TX context */
2289                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2290                 memset(&ena_tx_ctx.ena_meta, 0x0,
2291                        sizeof(struct ena_com_tx_meta));
2292                 ena_tx_ctx.ena_bufs = ebuf;
2293                 ena_tx_ctx.req_id = req_id;
2294
2295                 delta = 0;
2296                 seg_len = mbuf->data_len;
2297
2298                 if (tx_ring->tx_mem_queue_type ==
2299                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2300                         push_len = RTE_MIN(mbuf->pkt_len,
2301                                            tx_ring->tx_max_header_size);
2302                         ena_tx_ctx.header_len = push_len;
2303
2304                         if (likely(push_len <= seg_len)) {
2305                                 /* If the push header is in the single segment,
2306                                  * then just point it to the 1st mbuf data.
2307                                  */
2308                                 ena_tx_ctx.push_header =
2309                                         rte_pktmbuf_mtod(mbuf, uint8_t *);
2310                         } else {
2311                                 /* If the push header lays in the several
2312                                  * segments, copy it to the intermediate buffer.
2313                                  */
2314                                 rte_pktmbuf_read(mbuf, 0, push_len,
2315                                         tx_ring->push_buf_intermediate_buf);
2316                                 ena_tx_ctx.push_header =
2317                                         tx_ring->push_buf_intermediate_buf;
2318                                 delta = push_len - seg_len;
2319                         }
2320                 } /* there's no else as we take advantage of memset zeroing */
2321
2322                 /* Set TX offloads flags, if applicable */
2323                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2324
2325                 if (unlikely(mbuf->ol_flags &
2326                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2327                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2328
2329                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2330
2331                 /* Process first segment taking into
2332                  * consideration pushed header
2333                  */
2334                 if (seg_len > push_len) {
2335                         ebuf->paddr = mbuf->buf_iova +
2336                                       mbuf->data_off +
2337                                       push_len;
2338                         ebuf->len = seg_len - push_len;
2339                         ebuf++;
2340                         tx_info->num_of_bufs++;
2341                 }
2342
2343                 while ((mbuf = mbuf->next) != NULL) {
2344                         seg_len = mbuf->data_len;
2345
2346                         /* Skip mbufs if whole data is pushed as a header */
2347                         if (unlikely(delta > seg_len)) {
2348                                 delta -= seg_len;
2349                                 continue;
2350                         }
2351
2352                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta;
2353                         ebuf->len = seg_len - delta;
2354                         ebuf++;
2355                         tx_info->num_of_bufs++;
2356
2357                         delta = 0;
2358                 }
2359
2360                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2361
2362                 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq,
2363                                                &ena_tx_ctx)) {
2364                         RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d"
2365                                 " achieved, writing doorbell to send burst\n",
2366                                 tx_ring->id);
2367                         rte_wmb();
2368                         ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2369                 }
2370
2371                 /* prepare the packet's descriptors to dma engine */
2372                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2373                                         &ena_tx_ctx, &nb_hw_desc);
2374                 if (unlikely(rc))
2375                         break;
2376
2377                 tx_info->tx_descs = nb_hw_desc;
2378
2379                 next_to_use++;
2380         }
2381
2382         /* If there are ready packets to be xmitted... */
2383         if (sent_idx > 0) {
2384                 /* ...let HW do its best :-) */
2385                 rte_wmb();
2386                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2387
2388                 tx_ring->next_to_use = next_to_use;
2389         }
2390
2391         /* Clear complete packets  */
2392         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2393                 rc = validate_tx_req_id(tx_ring, req_id);
2394                 if (rc)
2395                         break;
2396
2397                 /* Get Tx info & store how many descs were processed  */
2398                 tx_info = &tx_ring->tx_buffer_info[req_id];
2399                 total_tx_descs += tx_info->tx_descs;
2400
2401                 /* Free whole mbuf chain  */
2402                 mbuf = tx_info->mbuf;
2403                 rte_pktmbuf_free(mbuf);
2404                 tx_info->mbuf = NULL;
2405
2406                 /* Put back descriptor to the ring for reuse */
2407                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2408                 next_to_clean++;
2409
2410                 /* If too many descs to clean, leave it for another run */
2411                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2412                         break;
2413         }
2414
2415         if (total_tx_descs > 0) {
2416                 /* acknowledge completion of sent packets */
2417                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2418                 tx_ring->next_to_clean = next_to_clean;
2419         }
2420
2421         return sent_idx;
2422 }
2423
2424 /*********************************************************************
2425  *  PMD configuration
2426  *********************************************************************/
2427 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2428         struct rte_pci_device *pci_dev)
2429 {
2430         return rte_eth_dev_pci_generic_probe(pci_dev,
2431                 sizeof(struct ena_adapter), eth_ena_dev_init);
2432 }
2433
2434 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2435 {
2436         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2437 }
2438
2439 static struct rte_pci_driver rte_ena_pmd = {
2440         .id_table = pci_id_ena_map,
2441         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2442                      RTE_PCI_DRV_WC_ACTIVATE,
2443         .probe = eth_ena_pci_probe,
2444         .remove = eth_ena_pci_remove,
2445 };
2446
2447 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2448 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2449 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2450
2451 RTE_INIT(ena_init_log)
2452 {
2453         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2454         if (ena_logtype_init >= 0)
2455                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2456         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2457         if (ena_logtype_driver >= 0)
2458                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2459 }
2460
2461 /******************************************************************************
2462  ******************************** AENQ Handlers *******************************
2463  *****************************************************************************/
2464 static void ena_update_on_link_change(void *adapter_data,
2465                                       struct ena_admin_aenq_entry *aenq_e)
2466 {
2467         struct rte_eth_dev *eth_dev;
2468         struct ena_adapter *adapter;
2469         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2470         uint32_t status;
2471
2472         adapter = (struct ena_adapter *)adapter_data;
2473         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2474         eth_dev = adapter->rte_dev;
2475
2476         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2477         adapter->link_status = status;
2478
2479         ena_link_update(eth_dev, 0);
2480         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2481 }
2482
2483 static void ena_notification(void *data,
2484                              struct ena_admin_aenq_entry *aenq_e)
2485 {
2486         struct ena_adapter *adapter = (struct ena_adapter *)data;
2487         struct ena_admin_ena_hw_hints *hints;
2488
2489         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2490                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2491                         aenq_e->aenq_common_desc.group,
2492                         ENA_ADMIN_NOTIFICATION);
2493
2494         switch (aenq_e->aenq_common_desc.syndrom) {
2495         case ENA_ADMIN_UPDATE_HINTS:
2496                 hints = (struct ena_admin_ena_hw_hints *)
2497                         (&aenq_e->inline_data_w4);
2498                 ena_update_hints(adapter, hints);
2499                 break;
2500         default:
2501                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2502                         aenq_e->aenq_common_desc.syndrom);
2503         }
2504 }
2505
2506 static void ena_keep_alive(void *adapter_data,
2507                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2508 {
2509         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2510
2511         adapter->timestamp_wd = rte_get_timer_cycles();
2512 }
2513
2514 /**
2515  * This handler will called for unknown event group or unimplemented handlers
2516  **/
2517 static void unimplemented_aenq_handler(__rte_unused void *data,
2518                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2519 {
2520         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2521                           "unimplemented handler\n");
2522 }
2523
2524 static struct ena_aenq_handlers aenq_handlers = {
2525         .handlers = {
2526                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2527                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2528                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2529         },
2530         .unimplemented_handler = unimplemented_aenq_handler
2531 };