drivers/net/ena/ena_ethdev.c

   1 /*-
   2 * BSD LICENSE
   3 *
   4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 *
  11 * * Redistributions of source code must retain the above copyright
  12 * notice, this list of conditions and the following disclaimer.
  13 * * Redistributions in binary form must reproduce the above copyright
  14 * notice, this list of conditions and the following disclaimer in
  15 * the documentation and/or other materials provided with the
  16 * distribution.
  17 * * Neither the name of copyright holder nor the names of its
  18 * contributors may be used to endorse or promote products derived
  19 * from this software without specific prior written permission.
  20 *
  21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32 */
  33
  34 #include <rte_ether.h>
  35 #include <rte_ethdev_driver.h>
  36 #include <rte_ethdev_pci.h>
  37 #include <rte_tcp.h>
  38 #include <rte_atomic.h>
  39 #include <rte_dev.h>
  40 #include <rte_errno.h>
  41 #include <rte_version.h>
  42 #include <rte_eal_memconfig.h>
  43 #include <rte_net.h>
  44
  45 #include "ena_ethdev.h"
  46 #include "ena_logs.h"
  47 #include "ena_platform.h"
  48 #include "ena_com.h"
  49 #include "ena_eth_com.h"
  50
  51 #include <ena_common_defs.h>
  52 #include <ena_regs_defs.h>
  53 #include <ena_admin_defs.h>
  54 #include <ena_eth_io_defs.h>
  55
  56 #define DRV_MODULE_VER_MAJOR    1
  57 #define DRV_MODULE_VER_MINOR    1
  58 #define DRV_MODULE_VER_SUBMINOR 1
  59
  60 #define ENA_IO_TXQ_IDX(q)       (2 * (q))
  61 #define ENA_IO_RXQ_IDX(q)       (2 * (q) + 1)
  62 /*reverse version of ENA_IO_RXQ_IDX*/
  63 #define ENA_IO_RXQ_IDX_REV(q)   ((q - 1) / 2)
  64
  65 /* While processing submitted and completed descriptors (rx and tx path
  66  * respectively) in a loop it is desired to:
  67  *  - perform batch submissions while populating sumbissmion queue
  68  *  - avoid blocking transmission of other packets during cleanup phase
  69  * Hence the utilization ratio of 1/8 of a queue size.
  70  */
  71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8)
  72
  73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l)
  74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift))
  75
  76 #define GET_L4_HDR_LEN(mbuf)                                    \
  77         ((rte_pktmbuf_mtod_offset(mbuf, struct tcp_hdr *,       \
  78                 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4)
  79
  80 #define ENA_RX_RSS_TABLE_LOG_SIZE  7
  81 #define ENA_RX_RSS_TABLE_SIZE   (1 << ENA_RX_RSS_TABLE_LOG_SIZE)
  82 #define ENA_HASH_KEY_SIZE       40
  83 #define ENA_ETH_SS_STATS        0xFF
  84 #define ETH_GSTRING_LEN 32
  85
  86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
  87
  88 #define ENA_MIN_RING_DESC       128
  89
  90 enum ethtool_stringset {
  91         ETH_SS_TEST             = 0,
  92         ETH_SS_STATS,
  93 };
  94
  95 struct ena_stats {
  96         char name[ETH_GSTRING_LEN];
  97         int stat_offset;
  98 };
  99
 100 #define ENA_STAT_ENA_COM_ENTRY(stat) { \
 101         .name = #stat, \
 102         .stat_offset = offsetof(struct ena_com_stats_admin, stat) \
 103 }
 104
 105 #define ENA_STAT_ENTRY(stat, stat_type) { \
 106         .name = #stat, \
 107         .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \
 108 }
 109
 110 #define ENA_STAT_RX_ENTRY(stat) \
 111         ENA_STAT_ENTRY(stat, rx)
 112
 113 #define ENA_STAT_TX_ENTRY(stat) \
 114         ENA_STAT_ENTRY(stat, tx)
 115
 116 #define ENA_STAT_GLOBAL_ENTRY(stat) \
 117         ENA_STAT_ENTRY(stat, dev)
 118
 119 /*
 120  * Each rte_memzone should have unique name.
 121  * To satisfy it, count number of allocation and add it to name.
 122  */
 123 uint32_t ena_alloc_cnt;
 124
 125 static const struct ena_stats ena_stats_global_strings[] = {
 126         ENA_STAT_GLOBAL_ENTRY(tx_timeout),
 127         ENA_STAT_GLOBAL_ENTRY(io_suspend),
 128         ENA_STAT_GLOBAL_ENTRY(io_resume),
 129         ENA_STAT_GLOBAL_ENTRY(wd_expired),
 130         ENA_STAT_GLOBAL_ENTRY(interface_up),
 131         ENA_STAT_GLOBAL_ENTRY(interface_down),
 132         ENA_STAT_GLOBAL_ENTRY(admin_q_pause),
 133 };
 134
 135 static const struct ena_stats ena_stats_tx_strings[] = {
 136         ENA_STAT_TX_ENTRY(cnt),
 137         ENA_STAT_TX_ENTRY(bytes),
 138         ENA_STAT_TX_ENTRY(queue_stop),
 139         ENA_STAT_TX_ENTRY(queue_wakeup),
 140         ENA_STAT_TX_ENTRY(dma_mapping_err),
 141         ENA_STAT_TX_ENTRY(linearize),
 142         ENA_STAT_TX_ENTRY(linearize_failed),
 143         ENA_STAT_TX_ENTRY(tx_poll),
 144         ENA_STAT_TX_ENTRY(doorbells),
 145         ENA_STAT_TX_ENTRY(prepare_ctx_err),
 146         ENA_STAT_TX_ENTRY(missing_tx_comp),
 147         ENA_STAT_TX_ENTRY(bad_req_id),
 148 };
 149
 150 static const struct ena_stats ena_stats_rx_strings[] = {
 151         ENA_STAT_RX_ENTRY(cnt),
 152         ENA_STAT_RX_ENTRY(bytes),
 153         ENA_STAT_RX_ENTRY(refil_partial),
 154         ENA_STAT_RX_ENTRY(bad_csum),
 155         ENA_STAT_RX_ENTRY(page_alloc_fail),
 156         ENA_STAT_RX_ENTRY(skb_alloc_fail),
 157         ENA_STAT_RX_ENTRY(dma_mapping_err),
 158         ENA_STAT_RX_ENTRY(bad_desc_num),
 159         ENA_STAT_RX_ENTRY(small_copy_len_pkt),
 160 };
 161
 162 static const struct ena_stats ena_stats_ena_com_strings[] = {
 163         ENA_STAT_ENA_COM_ENTRY(aborted_cmd),
 164         ENA_STAT_ENA_COM_ENTRY(submitted_cmd),
 165         ENA_STAT_ENA_COM_ENTRY(completed_cmd),
 166         ENA_STAT_ENA_COM_ENTRY(out_of_space),
 167         ENA_STAT_ENA_COM_ENTRY(no_completion),
 168 };
 169
 170 #define ENA_STATS_ARRAY_GLOBAL  ARRAY_SIZE(ena_stats_global_strings)
 171 #define ENA_STATS_ARRAY_TX      ARRAY_SIZE(ena_stats_tx_strings)
 172 #define ENA_STATS_ARRAY_RX      ARRAY_SIZE(ena_stats_rx_strings)
 173 #define ENA_STATS_ARRAY_ENA_COM ARRAY_SIZE(ena_stats_ena_com_strings)
 174
 175 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\
 176                         DEV_TX_OFFLOAD_UDP_CKSUM |\
 177                         DEV_TX_OFFLOAD_IPV4_CKSUM |\
 178                         DEV_TX_OFFLOAD_TCP_TSO)
 179 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\
 180                        PKT_TX_IP_CKSUM |\
 181                        PKT_TX_TCP_SEG)
 182
 183 /** Vendor ID used by Amazon devices */
 184 #define PCI_VENDOR_ID_AMAZON 0x1D0F
 185 /** Amazon devices */
 186 #define PCI_DEVICE_ID_ENA_VF    0xEC20
 187 #define PCI_DEVICE_ID_ENA_LLQ_VF        0xEC21
 188
 189 #define ENA_TX_OFFLOAD_MASK     (\
 190         PKT_TX_L4_MASK |         \
 191         PKT_TX_IPV6 |            \
 192         PKT_TX_IPV4 |            \
 193         PKT_TX_IP_CKSUM |        \
 194         PKT_TX_TCP_SEG)
 195
 196 #define ENA_TX_OFFLOAD_NOTSUP_MASK      \
 197         (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK)
 198
 199 int ena_logtype_init;
 200 int ena_logtype_driver;
 201
 202 static const struct rte_pci_id pci_id_ena_map[] = {
 203         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) },
 204         { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) },
 205         { .device_id = 0 },
 206 };
 207
 208 static struct ena_aenq_handlers aenq_handlers;
 209
 210 static int ena_device_init(struct ena_com_dev *ena_dev,
 211                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
 212                            bool *wd_state);
 213 static int ena_dev_configure(struct rte_eth_dev *dev);
 214 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 215                                   uint16_t nb_pkts);
 216 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 217                 uint16_t nb_pkts);
 218 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 219                               uint16_t nb_desc, unsigned int socket_id,
 220                               const struct rte_eth_txconf *tx_conf);
 221 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 222                               uint16_t nb_desc, unsigned int socket_id,
 223                               const struct rte_eth_rxconf *rx_conf,
 224                               struct rte_mempool *mp);
 225 static uint16_t eth_ena_recv_pkts(void *rx_queue,
 226                                   struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 227 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count);
 228 static void ena_init_rings(struct ena_adapter *adapter);
 229 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 230 static int ena_start(struct rte_eth_dev *dev);
 231 static void ena_stop(struct rte_eth_dev *dev);
 232 static void ena_close(struct rte_eth_dev *dev);
 233 static int ena_dev_reset(struct rte_eth_dev *dev);
 234 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
 235 static void ena_rx_queue_release_all(struct rte_eth_dev *dev);
 236 static void ena_tx_queue_release_all(struct rte_eth_dev *dev);
 237 static void ena_rx_queue_release(void *queue);
 238 static void ena_tx_queue_release(void *queue);
 239 static void ena_rx_queue_release_bufs(struct ena_ring *ring);
 240 static void ena_tx_queue_release_bufs(struct ena_ring *ring);
 241 static int ena_link_update(struct rte_eth_dev *dev,
 242                            int wait_to_complete);
 243 static int ena_create_io_queue(struct ena_ring *ring);
 244 static void ena_free_io_queues_all(struct ena_adapter *adapter);
 245 static int ena_queue_restart(struct ena_ring *ring);
 246 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 247                                  enum ena_ring_type ring_type);
 248 static void ena_stats_restart(struct rte_eth_dev *dev);
 249 static void ena_infos_get(struct rte_eth_dev *dev,
 250                           struct rte_eth_dev_info *dev_info);
 251 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 252                                struct rte_eth_rss_reta_entry64 *reta_conf,
 253                                uint16_t reta_size);
 254 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 255                               struct rte_eth_rss_reta_entry64 *reta_conf,
 256                               uint16_t reta_size);
 257 static int ena_get_sset_count(struct rte_eth_dev *dev, int sset);
 258 static void ena_interrupt_handler_rte(void *cb_arg);
 259 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg);
 260
 261 static const struct eth_dev_ops ena_dev_ops = {
 262         .dev_configure        = ena_dev_configure,
 263         .dev_infos_get        = ena_infos_get,
 264         .rx_queue_setup       = ena_rx_queue_setup,
 265         .tx_queue_setup       = ena_tx_queue_setup,
 266         .dev_start            = ena_start,
 267         .dev_stop             = ena_stop,
 268         .link_update          = ena_link_update,
 269         .stats_get            = ena_stats_get,
 270         .mtu_set              = ena_mtu_set,
 271         .rx_queue_release     = ena_rx_queue_release,
 272         .tx_queue_release     = ena_tx_queue_release,
 273         .dev_close            = ena_close,
 274         .dev_reset            = ena_dev_reset,
 275         .reta_update          = ena_rss_reta_update,
 276         .reta_query           = ena_rss_reta_query,
 277 };
 278
 279 #define NUMA_NO_NODE    SOCKET_ID_ANY
 280
 281 static inline int ena_cpu_to_node(int cpu)
 282 {
 283         struct rte_config *config = rte_eal_get_configuration();
 284         struct rte_fbarray *arr = &config->mem_config->memzones;
 285         const struct rte_memzone *mz;
 286
 287         if (unlikely(cpu >= RTE_MAX_MEMZONE))
 288                 return NUMA_NO_NODE;
 289
 290         mz = rte_fbarray_get(arr, cpu);
 291
 292         return mz->socket_id;
 293 }
 294
 295 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 296                                        struct ena_com_rx_ctx *ena_rx_ctx)
 297 {
 298         uint64_t ol_flags = 0;
 299         uint32_t packet_type = 0;
 300
 301         if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP)
 302                 packet_type |= RTE_PTYPE_L4_TCP;
 303         else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 304                 packet_type |= RTE_PTYPE_L4_UDP;
 305
 306         if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
 307                 packet_type |= RTE_PTYPE_L3_IPV4;
 308         else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
 309                 packet_type |= RTE_PTYPE_L3_IPV6;
 310
 311         if (unlikely(ena_rx_ctx->l4_csum_err))
 312                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
 313         if (unlikely(ena_rx_ctx->l3_csum_err))
 314                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
 315
 316         mbuf->ol_flags = ol_flags;
 317         mbuf->packet_type = packet_type;
 318 }
 319
 320 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
 321                                        struct ena_com_tx_ctx *ena_tx_ctx,
 322                                        uint64_t queue_offloads)
 323 {
 324         struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
 325
 326         if ((mbuf->ol_flags & MBUF_OFFLOADS) &&
 327             (queue_offloads & QUEUE_OFFLOADS)) {
 328                 /* check if TSO is required */
 329                 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) &&
 330                     (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) {
 331                         ena_tx_ctx->tso_enable = true;
 332
 333                         ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf);
 334                 }
 335
 336                 /* check if L3 checksum is needed */
 337                 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) &&
 338                     (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM))
 339                         ena_tx_ctx->l3_csum_enable = true;
 340
 341                 if (mbuf->ol_flags & PKT_TX_IPV6) {
 342                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
 343                 } else {
 344                         ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
 345
 346                         /* set don't fragment (DF) flag */
 347                         if (mbuf->packet_type &
 348                                 (RTE_PTYPE_L4_NONFRAG
 349                                  | RTE_PTYPE_INNER_L4_NONFRAG))
 350                                 ena_tx_ctx->df = true;
 351                 }
 352
 353                 /* check if L4 checksum is needed */
 354                 if ((mbuf->ol_flags & PKT_TX_TCP_CKSUM) &&
 355                     (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) {
 356                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
 357                         ena_tx_ctx->l4_csum_enable = true;
 358                 } else if ((mbuf->ol_flags & PKT_TX_UDP_CKSUM) &&
 359                            (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) {
 360                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
 361                         ena_tx_ctx->l4_csum_enable = true;
 362                 } else {
 363                         ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN;
 364                         ena_tx_ctx->l4_csum_enable = false;
 365                 }
 366
 367                 ena_meta->mss = mbuf->tso_segsz;
 368                 ena_meta->l3_hdr_len = mbuf->l3_len;
 369                 ena_meta->l3_hdr_offset = mbuf->l2_len;
 370
 371                 ena_tx_ctx->meta_valid = true;
 372         } else {
 373                 ena_tx_ctx->meta_valid = false;
 374         }
 375 }
 376
 377 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id)
 378 {
 379         if (likely(req_id < rx_ring->ring_size))
 380                 return 0;
 381
 382         RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id);
 383
 384         rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID;
 385         rx_ring->adapter->trigger_reset = true;
 386
 387         return -EFAULT;
 388 }
 389
 390 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
 391 {
 392         struct ena_tx_buffer *tx_info = NULL;
 393
 394         if (likely(req_id < tx_ring->ring_size)) {
 395                 tx_info = &tx_ring->tx_buffer_info[req_id];
 396                 if (likely(tx_info->mbuf))
 397                         return 0;
 398         }
 399
 400         if (tx_info)
 401                 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n");
 402         else
 403                 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id);
 404
 405         /* Trigger device reset */
 406         tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID;
 407         tx_ring->adapter->trigger_reset = true;
 408         return -EFAULT;
 409 }
 410
 411 static void ena_config_host_info(struct ena_com_dev *ena_dev)
 412 {
 413         struct ena_admin_host_info *host_info;
 414         int rc;
 415
 416         /* Allocate only the host info */
 417         rc = ena_com_allocate_host_info(ena_dev);
 418         if (rc) {
 419                 RTE_LOG(ERR, PMD, "Cannot allocate host info\n");
 420                 return;
 421         }
 422
 423         host_info = ena_dev->host_attr.host_info;
 424
 425         host_info->os_type = ENA_ADMIN_OS_DPDK;
 426         host_info->kernel_ver = RTE_VERSION;
 427         snprintf((char *)host_info->kernel_ver_str,
 428                  sizeof(host_info->kernel_ver_str),
 429                  "%s", rte_version());
 430         host_info->os_dist = RTE_VERSION;
 431         snprintf((char *)host_info->os_dist_str,
 432                  sizeof(host_info->os_dist_str),
 433                  "%s", rte_version());
 434         host_info->driver_version =
 435                 (DRV_MODULE_VER_MAJOR) |
 436                 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
 437                 (DRV_MODULE_VER_SUBMINOR <<
 438                         ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
 439         host_info->num_cpus = rte_lcore_count();
 440
 441         rc = ena_com_set_host_attributes(ena_dev);
 442         if (rc) {
 443                 if (rc == -ENA_COM_UNSUPPORTED)
 444                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 445                 else
 446                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 447
 448                 goto err;
 449         }
 450
 451         return;
 452
 453 err:
 454         ena_com_delete_host_info(ena_dev);
 455 }
 456
 457 static int
 458 ena_get_sset_count(struct rte_eth_dev *dev, int sset)
 459 {
 460         if (sset != ETH_SS_STATS)
 461                 return -EOPNOTSUPP;
 462
 463          /* Workaround for clang:
 464          * touch internal structures to prevent
 465          * compiler error
 466          */
 467         ENA_TOUCH(ena_stats_global_strings);
 468         ENA_TOUCH(ena_stats_tx_strings);
 469         ENA_TOUCH(ena_stats_rx_strings);
 470         ENA_TOUCH(ena_stats_ena_com_strings);
 471
 472         return  dev->data->nb_tx_queues *
 473                 (ENA_STATS_ARRAY_TX + ENA_STATS_ARRAY_RX) +
 474                 ENA_STATS_ARRAY_GLOBAL + ENA_STATS_ARRAY_ENA_COM;
 475 }
 476
 477 static void ena_config_debug_area(struct ena_adapter *adapter)
 478 {
 479         u32 debug_area_size;
 480         int rc, ss_count;
 481
 482         ss_count = ena_get_sset_count(adapter->rte_dev, ETH_SS_STATS);
 483         if (ss_count <= 0) {
 484                 RTE_LOG(ERR, PMD, "SS count is negative\n");
 485                 return;
 486         }
 487
 488         /* allocate 32 bytes for each string and 64bit for the value */
 489         debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
 490
 491         rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size);
 492         if (rc) {
 493                 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n");
 494                 return;
 495         }
 496
 497         rc = ena_com_set_host_attributes(&adapter->ena_dev);
 498         if (rc) {
 499                 if (rc == -ENA_COM_UNSUPPORTED)
 500                         RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
 501                 else
 502                         RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
 503
 504                 goto err;
 505         }
 506
 507         return;
 508 err:
 509         ena_com_delete_debug_area(&adapter->ena_dev);
 510 }
 511
 512 static void ena_close(struct rte_eth_dev *dev)
 513 {
 514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 515         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 516         struct ena_adapter *adapter =
 517                 (struct ena_adapter *)(dev->data->dev_private);
 518
 519         if (adapter->state == ENA_ADAPTER_STATE_RUNNING)
 520                 ena_stop(dev);
 521         adapter->state = ENA_ADAPTER_STATE_CLOSED;
 522
 523         ena_rx_queue_release_all(dev);
 524         ena_tx_queue_release_all(dev);
 525
 526         rte_free(adapter->drv_stats);
 527         adapter->drv_stats = NULL;
 528
 529         rte_intr_disable(intr_handle);
 530         rte_intr_callback_unregister(intr_handle,
 531                                      ena_interrupt_handler_rte,
 532                                      adapter);
 533
 534         /*
 535          * MAC is not allocated dynamically. Setting NULL should prevent from
 536          * release of the resource in the rte_eth_dev_release_port().
 537          */
 538         dev->data->mac_addrs = NULL;
 539 }
 540
 541 static int
 542 ena_dev_reset(struct rte_eth_dev *dev)
 543 {
 544         struct rte_mempool *mb_pool_rx[ENA_MAX_NUM_QUEUES];
 545         struct rte_eth_dev *eth_dev;
 546         struct rte_pci_device *pci_dev;
 547         struct rte_intr_handle *intr_handle;
 548         struct ena_com_dev *ena_dev;
 549         struct ena_com_dev_get_features_ctx get_feat_ctx;
 550         struct ena_adapter *adapter;
 551         int nb_queues;
 552         int rc, i;
 553         bool wd_state;
 554
 555         adapter = (struct ena_adapter *)(dev->data->dev_private);
 556         ena_dev = &adapter->ena_dev;
 557         eth_dev = adapter->rte_dev;
 558         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 559         intr_handle = &pci_dev->intr_handle;
 560         nb_queues = eth_dev->data->nb_rx_queues;
 561
 562         ena_com_set_admin_running_state(ena_dev, false);
 563
 564         rc = ena_com_dev_reset(ena_dev, adapter->reset_reason);
 565         if (rc)
 566                 RTE_LOG(ERR, PMD, "Device reset failed\n");
 567
 568         for (i = 0; i < nb_queues; i++)
 569                 mb_pool_rx[i] = adapter->rx_ring[i].mb_pool;
 570
 571         ena_rx_queue_release_all(eth_dev);
 572         ena_tx_queue_release_all(eth_dev);
 573
 574         rte_intr_disable(intr_handle);
 575
 576         ena_com_abort_admin_commands(ena_dev);
 577         ena_com_wait_for_abort_completion(ena_dev);
 578         ena_com_admin_destroy(ena_dev);
 579         ena_com_mmio_reg_read_request_destroy(ena_dev);
 580
 581         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
 582         if (rc) {
 583                 PMD_INIT_LOG(CRIT, "Cannot initialize device\n");
 584                 return rc;
 585         }
 586         adapter->wd_state = wd_state;
 587
 588         rte_intr_enable(intr_handle);
 589         ena_com_set_admin_polling_mode(ena_dev, false);
 590         ena_com_admin_aenq_enable(ena_dev);
 591
 592         for (i = 0; i < nb_queues; ++i)
 593                 ena_rx_queue_setup(eth_dev, i, adapter->rx_ring[i].ring_size, 0,
 594                         NULL, mb_pool_rx[i]);
 595
 596         for (i = 0; i < nb_queues; ++i)
 597                 ena_tx_queue_setup(eth_dev, i, adapter->tx_ring[i].ring_size, 0,
 598                         NULL);
 599
 600         adapter->trigger_reset = false;
 601
 602         return 0;
 603 }
 604
 605 static int ena_rss_reta_update(struct rte_eth_dev *dev,
 606                                struct rte_eth_rss_reta_entry64 *reta_conf,
 607                                uint16_t reta_size)
 608 {
 609         struct ena_adapter *adapter =
 610                 (struct ena_adapter *)(dev->data->dev_private);
 611         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 612         int rc, i;
 613         u16 entry_value;
 614         int conf_idx;
 615         int idx;
 616
 617         if ((reta_size == 0) || (reta_conf == NULL))
 618                 return -EINVAL;
 619
 620         if (reta_size > ENA_RX_RSS_TABLE_SIZE) {
 621                 RTE_LOG(WARNING, PMD,
 622                         "indirection table %d is bigger than supported (%d)\n",
 623                         reta_size, ENA_RX_RSS_TABLE_SIZE);
 624                 return -EINVAL;
 625         }
 626
 627         for (i = 0 ; i < reta_size ; i++) {
 628                 /* each reta_conf is for 64 entries.
 629                  * to support 128 we use 2 conf of 64
 630                  */
 631                 conf_idx = i / RTE_RETA_GROUP_SIZE;
 632                 idx = i % RTE_RETA_GROUP_SIZE;
 633                 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) {
 634                         entry_value =
 635                                 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]);
 636
 637                         rc = ena_com_indirect_table_fill_entry(ena_dev,
 638                                                                i,
 639                                                                entry_value);
 640                         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 641                                 RTE_LOG(ERR, PMD,
 642                                         "Cannot fill indirect table\n");
 643                                 return rc;
 644                         }
 645                 }
 646         }
 647
 648         rc = ena_com_indirect_table_set(ena_dev);
 649         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 650                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 651                 return rc;
 652         }
 653
 654         RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries  for port %d\n",
 655                 __func__, reta_size, adapter->rte_dev->data->port_id);
 656
 657         return 0;
 658 }
 659
 660 /* Query redirection table. */
 661 static int ena_rss_reta_query(struct rte_eth_dev *dev,
 662                               struct rte_eth_rss_reta_entry64 *reta_conf,
 663                               uint16_t reta_size)
 664 {
 665         struct ena_adapter *adapter =
 666                 (struct ena_adapter *)(dev->data->dev_private);
 667         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 668         int rc;
 669         int i;
 670         u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0};
 671         int reta_conf_idx;
 672         int reta_idx;
 673
 674         if (reta_size == 0 || reta_conf == NULL ||
 675             (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL)))
 676                 return -EINVAL;
 677
 678         rc = ena_com_indirect_table_get(ena_dev, indirect_table);
 679         if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) {
 680                 RTE_LOG(ERR, PMD, "cannot get indirect table\n");
 681                 return -ENOTSUP;
 682         }
 683
 684         for (i = 0 ; i < reta_size ; i++) {
 685                 reta_conf_idx = i / RTE_RETA_GROUP_SIZE;
 686                 reta_idx = i % RTE_RETA_GROUP_SIZE;
 687                 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx))
 688                         reta_conf[reta_conf_idx].reta[reta_idx] =
 689                                 ENA_IO_RXQ_IDX_REV(indirect_table[i]);
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int ena_rss_init_default(struct ena_adapter *adapter)
 696 {
 697         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 698         uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues;
 699         int rc, i;
 700         u32 val;
 701
 702         rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
 703         if (unlikely(rc)) {
 704                 RTE_LOG(ERR, PMD, "Cannot init indirect table\n");
 705                 goto err_rss_init;
 706         }
 707
 708         for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
 709                 val = i % nb_rx_queues;
 710                 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
 711                                                        ENA_IO_RXQ_IDX(val));
 712                 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 713                         RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
 714                         goto err_fill_indir;
 715                 }
 716         }
 717
 718         rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
 719                                         ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
 720         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 721                 RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
 722                 goto err_fill_indir;
 723         }
 724
 725         rc = ena_com_set_default_hash_ctrl(ena_dev);
 726         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 727                 RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
 728                 goto err_fill_indir;
 729         }
 730
 731         rc = ena_com_indirect_table_set(ena_dev);
 732         if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
 733                 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
 734                 goto err_fill_indir;
 735         }
 736         RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n",
 737                 adapter->rte_dev->data->port_id);
 738
 739         return 0;
 740
 741 err_fill_indir:
 742         ena_com_rss_destroy(ena_dev);
 743 err_rss_init:
 744
 745         return rc;
 746 }
 747
 748 static void ena_rx_queue_release_all(struct rte_eth_dev *dev)
 749 {
 750         struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues;
 751         int nb_queues = dev->data->nb_rx_queues;
 752         int i;
 753
 754         for (i = 0; i < nb_queues; i++)
 755                 ena_rx_queue_release(queues[i]);
 756 }
 757
 758 static void ena_tx_queue_release_all(struct rte_eth_dev *dev)
 759 {
 760         struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues;
 761         int nb_queues = dev->data->nb_tx_queues;
 762         int i;
 763
 764         for (i = 0; i < nb_queues; i++)
 765                 ena_tx_queue_release(queues[i]);
 766 }
 767
 768 static void ena_rx_queue_release(void *queue)
 769 {
 770         struct ena_ring *ring = (struct ena_ring *)queue;
 771
 772         ena_assert_msg(ring->configured,
 773                        "API violation - releasing not configured queue");
 774         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 775                        "API violation");
 776
 777         /* Free ring resources */
 778         if (ring->rx_buffer_info)
 779                 rte_free(ring->rx_buffer_info);
 780         ring->rx_buffer_info = NULL;
 781
 782         if (ring->rx_refill_buffer)
 783                 rte_free(ring->rx_refill_buffer);
 784         ring->rx_refill_buffer = NULL;
 785
 786         if (ring->empty_rx_reqs)
 787                 rte_free(ring->empty_rx_reqs);
 788         ring->empty_rx_reqs = NULL;
 789
 790         ring->configured = 0;
 791
 792         RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n",
 793                 ring->port_id, ring->id);
 794 }
 795
 796 static void ena_tx_queue_release(void *queue)
 797 {
 798         struct ena_ring *ring = (struct ena_ring *)queue;
 799
 800         ena_assert_msg(ring->configured,
 801                        "API violation. Releasing not configured queue");
 802         ena_assert_msg(ring->adapter->state != ENA_ADAPTER_STATE_RUNNING,
 803                        "API violation");
 804
 805         /* Free all bufs */
 806         ena_tx_queue_release_bufs(ring);
 807
 808         /* Free ring resources */
 809         if (ring->tx_buffer_info)
 810                 rte_free(ring->tx_buffer_info);
 811
 812         if (ring->empty_tx_reqs)
 813                 rte_free(ring->empty_tx_reqs);
 814
 815         ring->empty_tx_reqs = NULL;
 816         ring->tx_buffer_info = NULL;
 817
 818         ring->configured = 0;
 819
 820         RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n",
 821                 ring->port_id, ring->id);
 822 }
 823
 824 static void ena_rx_queue_release_bufs(struct ena_ring *ring)
 825 {
 826         unsigned int ring_mask = ring->ring_size - 1;
 827
 828         while (ring->next_to_clean != ring->next_to_use) {
 829                 struct rte_mbuf *m =
 830                         ring->rx_buffer_info[ring->next_to_clean & ring_mask];
 831
 832                 if (m)
 833                         rte_mbuf_raw_free(m);
 834
 835                 ring->next_to_clean++;
 836         }
 837 }
 838
 839 static void ena_tx_queue_release_bufs(struct ena_ring *ring)
 840 {
 841         unsigned int i;
 842
 843         for (i = 0; i < ring->ring_size; ++i) {
 844                 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i];
 845
 846                 if (tx_buf->mbuf)
 847                         rte_pktmbuf_free(tx_buf->mbuf);
 848
 849                 ring->next_to_clean++;
 850         }
 851 }
 852
 853 static int ena_link_update(struct rte_eth_dev *dev,
 854                            __rte_unused int wait_to_complete)
 855 {
 856         struct rte_eth_link *link = &dev->data->dev_link;
 857         struct ena_adapter *adapter;
 858
 859         adapter = (struct ena_adapter *)(dev->data->dev_private);
 860
 861         link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
 862         link->link_speed = ETH_SPEED_NUM_NONE;
 863         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 864
 865         return 0;
 866 }
 867
 868 static int ena_queue_restart_all(struct rte_eth_dev *dev,
 869                                  enum ena_ring_type ring_type)
 870 {
 871         struct ena_adapter *adapter =
 872                 (struct ena_adapter *)(dev->data->dev_private);
 873         struct ena_ring *queues = NULL;
 874         int nb_queues;
 875         int i = 0;
 876         int rc = 0;
 877
 878         if (ring_type == ENA_RING_TYPE_RX) {
 879                 queues = adapter->rx_ring;
 880                 nb_queues = dev->data->nb_rx_queues;
 881         } else {
 882                 queues = adapter->tx_ring;
 883                 nb_queues = dev->data->nb_tx_queues;
 884         }
 885         for (i = 0; i < nb_queues; i++) {
 886                 if (queues[i].configured) {
 887                         if (ring_type == ENA_RING_TYPE_RX) {
 888                                 ena_assert_msg(
 889                                         dev->data->rx_queues[i] == &queues[i],
 890                                         "Inconsistent state of rx queues\n");
 891                         } else {
 892                                 ena_assert_msg(
 893                                         dev->data->tx_queues[i] == &queues[i],
 894                                         "Inconsistent state of tx queues\n");
 895                         }
 896
 897                         rc = ena_queue_restart(&queues[i]);
 898
 899                         if (rc) {
 900                                 PMD_INIT_LOG(ERR,
 901                                              "failed to restart queue %d type(%d)",
 902                                              i, ring_type);
 903                                 return rc;
 904                         }
 905                 }
 906         }
 907
 908         return 0;
 909 }
 910
 911 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter)
 912 {
 913         uint32_t max_frame_len = adapter->max_mtu;
 914
 915         if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads &
 916             DEV_RX_OFFLOAD_JUMBO_FRAME)
 917                 max_frame_len =
 918                         adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len;
 919
 920         return max_frame_len;
 921 }
 922
 923 static int ena_check_valid_conf(struct ena_adapter *adapter)
 924 {
 925         uint32_t max_frame_len = ena_get_mtu_conf(adapter);
 926
 927         if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) {
 928                 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. "
 929                                   "max mtu: %d, min mtu: %d\n",
 930                              max_frame_len, adapter->max_mtu, ENA_MIN_MTU);
 931                 return ENA_COM_UNSUPPORTED;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int
 938 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx)
 939 {
 940         uint32_t tx_queue_size, rx_queue_size;
 941
 942         if (ctx->ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
 943                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
 944                         &ctx->get_feat_ctx->max_queue_ext.max_queue_ext;
 945                 rx_queue_size = RTE_MIN(max_queue_ext->max_rx_cq_depth,
 946                         max_queue_ext->max_rx_sq_depth);
 947                 tx_queue_size = RTE_MIN(max_queue_ext->max_tx_cq_depth,
 948                         max_queue_ext->max_tx_sq_depth);
 949                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 950                         max_queue_ext->max_per_packet_rx_descs);
 951                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 952                         max_queue_ext->max_per_packet_tx_descs);
 953         } else {
 954                 struct ena_admin_queue_feature_desc *max_queues =
 955                         &ctx->get_feat_ctx->max_queues;
 956                 rx_queue_size = RTE_MIN(max_queues->max_cq_depth,
 957                         max_queues->max_sq_depth);
 958                 tx_queue_size = rx_queue_size;
 959                 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 960                         max_queues->max_packet_tx_descs);
 961                 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS,
 962                         max_queues->max_packet_rx_descs);
 963         }
 964
 965         /* Round down to the nearest power of 2 */
 966         rx_queue_size = rte_align32prevpow2(rx_queue_size);
 967         tx_queue_size = rte_align32prevpow2(tx_queue_size);
 968
 969         if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) {
 970                 PMD_INIT_LOG(ERR, "Invalid queue size");
 971                 return -EFAULT;
 972         }
 973
 974         ctx->rx_queue_size = rx_queue_size;
 975         ctx->tx_queue_size = tx_queue_size;
 976
 977         return 0;
 978 }
 979
 980 static void ena_stats_restart(struct rte_eth_dev *dev)
 981 {
 982         struct ena_adapter *adapter =
 983                 (struct ena_adapter *)(dev->data->dev_private);
 984
 985         rte_atomic64_init(&adapter->drv_stats->ierrors);
 986         rte_atomic64_init(&adapter->drv_stats->oerrors);
 987         rte_atomic64_init(&adapter->drv_stats->rx_nombuf);
 988 }
 989
 990 static int ena_stats_get(struct rte_eth_dev *dev,
 991                           struct rte_eth_stats *stats)
 992 {
 993         struct ena_admin_basic_stats ena_stats;
 994         struct ena_adapter *adapter =
 995                 (struct ena_adapter *)(dev->data->dev_private);
 996         struct ena_com_dev *ena_dev = &adapter->ena_dev;
 997         int rc;
 998
 999         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1000                 return -ENOTSUP;
1001
1002         memset(&ena_stats, 0, sizeof(ena_stats));
1003         rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats);
1004         if (unlikely(rc)) {
1005                 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA");
1006                 return rc;
1007         }
1008
1009         /* Set of basic statistics from ENA */
1010         stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high,
1011                                           ena_stats.rx_pkts_low);
1012         stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high,
1013                                           ena_stats.tx_pkts_low);
1014         stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high,
1015                                         ena_stats.rx_bytes_low);
1016         stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high,
1017                                         ena_stats.tx_bytes_low);
1018         stats->imissed = __MERGE_64B_H_L(ena_stats.rx_drops_high,
1019                                          ena_stats.rx_drops_low);
1020
1021         /* Driver related stats */
1022         stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors);
1023         stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors);
1024         stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf);
1025         return 0;
1026 }
1027
1028 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1029 {
1030         struct ena_adapter *adapter;
1031         struct ena_com_dev *ena_dev;
1032         int rc = 0;
1033
1034         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1035         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1036         adapter = (struct ena_adapter *)(dev->data->dev_private);
1037
1038         ena_dev = &adapter->ena_dev;
1039         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1040
1041         if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) {
1042                 RTE_LOG(ERR, PMD,
1043                         "Invalid MTU setting. new_mtu: %d "
1044                         "max mtu: %d min mtu: %d\n",
1045                         mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU);
1046                 return -EINVAL;
1047         }
1048
1049         rc = ena_com_set_dev_mtu(ena_dev, mtu);
1050         if (rc)
1051                 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu);
1052         else
1053                 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu);
1054
1055         return rc;
1056 }
1057
1058 static int ena_start(struct rte_eth_dev *dev)
1059 {
1060         struct ena_adapter *adapter =
1061                 (struct ena_adapter *)(dev->data->dev_private);
1062         uint64_t ticks;
1063         int rc = 0;
1064
1065         rc = ena_check_valid_conf(adapter);
1066         if (rc)
1067                 return rc;
1068
1069         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_RX);
1070         if (rc)
1071                 return rc;
1072
1073         rc = ena_queue_restart_all(dev, ENA_RING_TYPE_TX);
1074         if (rc)
1075                 return rc;
1076
1077         if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode &
1078             ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) {
1079                 rc = ena_rss_init_default(adapter);
1080                 if (rc)
1081                         return rc;
1082         }
1083
1084         ena_stats_restart(dev);
1085
1086         adapter->timestamp_wd = rte_get_timer_cycles();
1087         adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT;
1088
1089         ticks = rte_get_timer_hz();
1090         rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(),
1091                         ena_timer_wd_callback, adapter);
1092
1093         adapter->state = ENA_ADAPTER_STATE_RUNNING;
1094
1095         return 0;
1096 }
1097
1098 static void ena_stop(struct rte_eth_dev *dev)
1099 {
1100         struct ena_adapter *adapter =
1101                 (struct ena_adapter *)(dev->data->dev_private);
1102
1103         rte_timer_stop_sync(&adapter->timer_wd);
1104         ena_free_io_queues_all(adapter);
1105
1106         adapter->state = ENA_ADAPTER_STATE_STOPPED;
1107 }
1108
1109 static int ena_create_io_queue(struct ena_ring *ring)
1110 {
1111         struct ena_adapter *adapter;
1112         struct ena_com_dev *ena_dev;
1113         struct ena_com_create_io_ctx ctx =
1114                 /* policy set to _HOST just to satisfy icc compiler */
1115                 { ENA_ADMIN_PLACEMENT_POLICY_HOST,
1116                   0, 0, 0, 0, 0 };
1117         uint16_t ena_qid;
1118         unsigned int i;
1119         int rc;
1120
1121         adapter = ring->adapter;
1122         ena_dev = &adapter->ena_dev;
1123
1124         if (ring->type == ENA_RING_TYPE_TX) {
1125                 ena_qid = ENA_IO_TXQ_IDX(ring->id);
1126                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1127                 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1128                 ctx.queue_size = adapter->tx_ring_size;
1129                 for (i = 0; i < ring->ring_size; i++)
1130                         ring->empty_tx_reqs[i] = i;
1131         } else {
1132                 ena_qid = ENA_IO_RXQ_IDX(ring->id);
1133                 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1134                 ctx.queue_size = adapter->rx_ring_size;
1135                 for (i = 0; i < ring->ring_size; i++)
1136                         ring->empty_rx_reqs[i] = i;
1137         }
1138         ctx.qid = ena_qid;
1139         ctx.msix_vector = -1; /* interrupts not used */
1140         ctx.numa_node = ena_cpu_to_node(ring->id);
1141
1142         rc = ena_com_create_io_queue(ena_dev, &ctx);
1143         if (rc) {
1144                 RTE_LOG(ERR, PMD,
1145                         "failed to create io queue #%d (qid:%d) rc: %d\n",
1146                         ring->id, ena_qid, rc);
1147                 return rc;
1148         }
1149
1150         rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1151                                      &ring->ena_com_io_sq,
1152                                      &ring->ena_com_io_cq);
1153         if (rc) {
1154                 RTE_LOG(ERR, PMD,
1155                         "Failed to get io queue handlers. queue num %d rc: %d\n",
1156                         ring->id, rc);
1157                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1158                 return rc;
1159         }
1160
1161         if (ring->type == ENA_RING_TYPE_TX)
1162                 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node);
1163
1164         return 0;
1165 }
1166
1167 static void ena_free_io_queues_all(struct ena_adapter *adapter)
1168 {
1169         struct rte_eth_dev *eth_dev = adapter->rte_dev;
1170         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1171         int i;
1172         uint16_t ena_qid;
1173         uint16_t nb_rxq = eth_dev->data->nb_rx_queues;
1174         uint16_t nb_txq = eth_dev->data->nb_tx_queues;
1175
1176         for (i = 0; i < nb_txq; ++i) {
1177                 ena_qid = ENA_IO_TXQ_IDX(i);
1178                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1179
1180                 ena_tx_queue_release_bufs(&adapter->tx_ring[i]);
1181         }
1182
1183         for (i = 0; i < nb_rxq; ++i) {
1184                 ena_qid = ENA_IO_RXQ_IDX(i);
1185                 ena_com_destroy_io_queue(ena_dev, ena_qid);
1186
1187                 ena_rx_queue_release_bufs(&adapter->rx_ring[i]);
1188         }
1189 }
1190
1191 static int ena_queue_restart(struct ena_ring *ring)
1192 {
1193         int rc, bufs_num;
1194
1195         ena_assert_msg(ring->configured == 1,
1196                        "Trying to restart unconfigured queue\n");
1197
1198         rc = ena_create_io_queue(ring);
1199         if (rc) {
1200                 PMD_INIT_LOG(ERR, "Failed to create IO queue!\n");
1201                 return rc;
1202         }
1203
1204         ring->next_to_clean = 0;
1205         ring->next_to_use = 0;
1206
1207         if (ring->type == ENA_RING_TYPE_TX)
1208                 return 0;
1209
1210         bufs_num = ring->ring_size - 1;
1211         rc = ena_populate_rx_queue(ring, bufs_num);
1212         if (rc != bufs_num) {
1213                 PMD_INIT_LOG(ERR, "Failed to populate rx ring !");
1214                 return ENA_COM_FAULT;
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int ena_tx_queue_setup(struct rte_eth_dev *dev,
1221                               uint16_t queue_idx,
1222                               uint16_t nb_desc,
1223                               __rte_unused unsigned int socket_id,
1224                               const struct rte_eth_txconf *tx_conf)
1225 {
1226         struct ena_ring *txq = NULL;
1227         struct ena_adapter *adapter =
1228                 (struct ena_adapter *)(dev->data->dev_private);
1229         unsigned int i;
1230
1231         txq = &adapter->tx_ring[queue_idx];
1232
1233         if (txq->configured) {
1234                 RTE_LOG(CRIT, PMD,
1235                         "API violation. Queue %d is already configured\n",
1236                         queue_idx);
1237                 return ENA_COM_FAULT;
1238         }
1239
1240         if (!rte_is_power_of_2(nb_desc)) {
1241                 RTE_LOG(ERR, PMD,
1242                         "Unsupported size of TX queue: %d is not a power of 2.",
1243                         nb_desc);
1244                 return -EINVAL;
1245         }
1246
1247         if (nb_desc > adapter->tx_ring_size) {
1248                 RTE_LOG(ERR, PMD,
1249                         "Unsupported size of TX queue (max size: %d)\n",
1250                         adapter->tx_ring_size);
1251                 return -EINVAL;
1252         }
1253
1254         if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE)
1255                 nb_desc = adapter->tx_ring_size;
1256
1257         txq->port_id = dev->data->port_id;
1258         txq->next_to_clean = 0;
1259         txq->next_to_use = 0;
1260         txq->ring_size = nb_desc;
1261
1262         txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info",
1263                                           sizeof(struct ena_tx_buffer) *
1264                                           txq->ring_size,
1265                                           RTE_CACHE_LINE_SIZE);
1266         if (!txq->tx_buffer_info) {
1267                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n");
1268                 return -ENOMEM;
1269         }
1270
1271         txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs",
1272                                          sizeof(u16) * txq->ring_size,
1273                                          RTE_CACHE_LINE_SIZE);
1274         if (!txq->empty_tx_reqs) {
1275                 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n");
1276                 rte_free(txq->tx_buffer_info);
1277                 return -ENOMEM;
1278         }
1279
1280         for (i = 0; i < txq->ring_size; i++)
1281                 txq->empty_tx_reqs[i] = i;
1282
1283         if (tx_conf != NULL) {
1284                 txq->offloads =
1285                         tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1286         }
1287
1288         /* Store pointer to this queue in upper layer */
1289         txq->configured = 1;
1290         dev->data->tx_queues[queue_idx] = txq;
1291
1292         return 0;
1293 }
1294
1295 static int ena_rx_queue_setup(struct rte_eth_dev *dev,
1296                               uint16_t queue_idx,
1297                               uint16_t nb_desc,
1298                               __rte_unused unsigned int socket_id,
1299                               __rte_unused const struct rte_eth_rxconf *rx_conf,
1300                               struct rte_mempool *mp)
1301 {
1302         struct ena_adapter *adapter =
1303                 (struct ena_adapter *)(dev->data->dev_private);
1304         struct ena_ring *rxq = NULL;
1305         int i;
1306
1307         rxq = &adapter->rx_ring[queue_idx];
1308         if (rxq->configured) {
1309                 RTE_LOG(CRIT, PMD,
1310                         "API violation. Queue %d is already configured\n",
1311                         queue_idx);
1312                 return ENA_COM_FAULT;
1313         }
1314
1315         if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE)
1316                 nb_desc = adapter->rx_ring_size;
1317
1318         if (!rte_is_power_of_2(nb_desc)) {
1319                 RTE_LOG(ERR, PMD,
1320                         "Unsupported size of RX queue: %d is not a power of 2.",
1321                         nb_desc);
1322                 return -EINVAL;
1323         }
1324
1325         if (nb_desc > adapter->rx_ring_size) {
1326                 RTE_LOG(ERR, PMD,
1327                         "Unsupported size of RX queue (max size: %d)\n",
1328                         adapter->rx_ring_size);
1329                 return -EINVAL;
1330         }
1331
1332         rxq->port_id = dev->data->port_id;
1333         rxq->next_to_clean = 0;
1334         rxq->next_to_use = 0;
1335         rxq->ring_size = nb_desc;
1336         rxq->mb_pool = mp;
1337
1338         rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info",
1339                                           sizeof(struct rte_mbuf *) * nb_desc,
1340                                           RTE_CACHE_LINE_SIZE);
1341         if (!rxq->rx_buffer_info) {
1342                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n");
1343                 return -ENOMEM;
1344         }
1345
1346         rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer",
1347                                             sizeof(struct rte_mbuf *) * nb_desc,
1348                                             RTE_CACHE_LINE_SIZE);
1349
1350         if (!rxq->rx_refill_buffer) {
1351                 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n");
1352                 rte_free(rxq->rx_buffer_info);
1353                 rxq->rx_buffer_info = NULL;
1354                 return -ENOMEM;
1355         }
1356
1357         rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs",
1358                                          sizeof(uint16_t) * nb_desc,
1359                                          RTE_CACHE_LINE_SIZE);
1360         if (!rxq->empty_rx_reqs) {
1361                 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n");
1362                 rte_free(rxq->rx_buffer_info);
1363                 rxq->rx_buffer_info = NULL;
1364                 rte_free(rxq->rx_refill_buffer);
1365                 rxq->rx_refill_buffer = NULL;
1366                 return -ENOMEM;
1367         }
1368
1369         for (i = 0; i < nb_desc; i++)
1370                 rxq->empty_tx_reqs[i] = i;
1371
1372         /* Store pointer to this queue in upper layer */
1373         rxq->configured = 1;
1374         dev->data->rx_queues[queue_idx] = rxq;
1375
1376         return 0;
1377 }
1378
1379 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)
1380 {
1381         unsigned int i;
1382         int rc;
1383         uint16_t ring_size = rxq->ring_size;
1384         uint16_t ring_mask = ring_size - 1;
1385         uint16_t next_to_use = rxq->next_to_use;
1386         uint16_t in_use, req_id;
1387         struct rte_mbuf **mbufs = rxq->rx_refill_buffer;
1388
1389         if (unlikely(!count))
1390                 return 0;
1391
1392         in_use = rxq->next_to_use - rxq->next_to_clean;
1393         ena_assert_msg(((in_use + count) < ring_size), "bad ring state");
1394
1395         /* get resources for incoming packets */
1396         rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);
1397         if (unlikely(rc < 0)) {
1398                 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf);
1399                 PMD_RX_LOG(DEBUG, "there are no enough free buffers");
1400                 return 0;
1401         }
1402
1403         for (i = 0; i < count; i++) {
1404                 uint16_t next_to_use_masked = next_to_use & ring_mask;
1405                 struct rte_mbuf *mbuf = mbufs[i];
1406                 struct ena_com_buf ebuf;
1407
1408                 if (likely((i + 4) < count))
1409                         rte_prefetch0(mbufs[i + 4]);
1410
1411                 req_id = rxq->empty_rx_reqs[next_to_use_masked];
1412                 rc = validate_rx_req_id(rxq, req_id);
1413                 if (unlikely(rc < 0))
1414                         break;
1415                 rxq->rx_buffer_info[req_id] = mbuf;
1416
1417                 /* prepare physical address for DMA transaction */
1418                 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM;
1419                 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM;
1420                 /* pass resource to device */
1421                 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq,
1422                                                 &ebuf, req_id);
1423                 if (unlikely(rc)) {
1424                         RTE_LOG(WARNING, PMD, "failed adding rx desc\n");
1425                         rxq->rx_buffer_info[req_id] = NULL;
1426                         break;
1427                 }
1428                 next_to_use++;
1429         }
1430
1431         if (unlikely(i < count)) {
1432                 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d "
1433                         "buffers (from %d)\n", rxq->id, i, count);
1434                 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]),
1435                                      count - i);
1436         }
1437
1438         /* When we submitted free recources to device... */
1439         if (likely(i > 0)) {
1440                 /* ...let HW know that it can fill buffers with data
1441                  *
1442                  * Add memory barrier to make sure the desc were written before
1443                  * issue a doorbell
1444                  */
1445                 rte_wmb();
1446                 ena_com_write_sq_doorbell(rxq->ena_com_io_sq);
1447
1448                 rxq->next_to_use = next_to_use;
1449         }
1450
1451         return i;
1452 }
1453
1454 static int ena_device_init(struct ena_com_dev *ena_dev,
1455                            struct ena_com_dev_get_features_ctx *get_feat_ctx,
1456                            bool *wd_state)
1457 {
1458         uint32_t aenq_groups;
1459         int rc;
1460         bool readless_supported;
1461
1462         /* Initialize mmio registers */
1463         rc = ena_com_mmio_reg_read_request_init(ena_dev);
1464         if (rc) {
1465                 RTE_LOG(ERR, PMD, "failed to init mmio read less\n");
1466                 return rc;
1467         }
1468
1469         /* The PCIe configuration space revision id indicate if mmio reg
1470          * read is disabled.
1471          */
1472         readless_supported =
1473                 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id
1474                                & ENA_MMIO_DISABLE_REG_READ);
1475         ena_com_set_mmio_read_mode(ena_dev, readless_supported);
1476
1477         /* reset device */
1478         rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
1479         if (rc) {
1480                 RTE_LOG(ERR, PMD, "cannot reset device\n");
1481                 goto err_mmio_read_less;
1482         }
1483
1484         /* check FW version */
1485         rc = ena_com_validate_version(ena_dev);
1486         if (rc) {
1487                 RTE_LOG(ERR, PMD, "device version is too low\n");
1488                 goto err_mmio_read_less;
1489         }
1490
1491         ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
1492
1493         /* ENA device administration layer init */
1494         rc = ena_com_admin_init(ena_dev, &aenq_handlers);
1495         if (rc) {
1496                 RTE_LOG(ERR, PMD,
1497                         "cannot initialize ena admin queue with device\n");
1498                 goto err_mmio_read_less;
1499         }
1500
1501         /* To enable the msix interrupts the driver needs to know the number
1502          * of queues. So the driver uses polling mode to retrieve this
1503          * information.
1504          */
1505         ena_com_set_admin_polling_mode(ena_dev, true);
1506
1507         ena_config_host_info(ena_dev);
1508
1509         /* Get Device Attributes and features */
1510         rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
1511         if (rc) {
1512                 RTE_LOG(ERR, PMD,
1513                         "cannot get attribute for ena device rc= %d\n", rc);
1514                 goto err_admin_init;
1515         }
1516
1517         aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
1518                       BIT(ENA_ADMIN_NOTIFICATION) |
1519                       BIT(ENA_ADMIN_KEEP_ALIVE) |
1520                       BIT(ENA_ADMIN_FATAL_ERROR) |
1521                       BIT(ENA_ADMIN_WARNING);
1522
1523         aenq_groups &= get_feat_ctx->aenq.supported_groups;
1524         rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
1525         if (rc) {
1526                 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc);
1527                 goto err_admin_init;
1528         }
1529
1530         *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
1531
1532         return 0;
1533
1534 err_admin_init:
1535         ena_com_admin_destroy(ena_dev);
1536
1537 err_mmio_read_less:
1538         ena_com_mmio_reg_read_request_destroy(ena_dev);
1539
1540         return rc;
1541 }
1542
1543 static void ena_interrupt_handler_rte(void *cb_arg)
1544 {
1545         struct ena_adapter *adapter = (struct ena_adapter *)cb_arg;
1546         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1547
1548         ena_com_admin_q_comp_intr_handler(ena_dev);
1549         if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED))
1550                 ena_com_aenq_intr_handler(ena_dev, adapter);
1551 }
1552
1553 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
1554 {
1555         if (!adapter->wd_state)
1556                 return;
1557
1558         if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT)
1559                 return;
1560
1561         if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >=
1562             adapter->keep_alive_timeout)) {
1563                 RTE_LOG(ERR, PMD, "Keep alive timeout\n");
1564                 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO;
1565                 adapter->trigger_reset = true;
1566         }
1567 }
1568
1569 /* Check if admin queue is enabled */
1570 static void check_for_admin_com_state(struct ena_adapter *adapter)
1571 {
1572         if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) {
1573                 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n");
1574                 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO;
1575                 adapter->trigger_reset = true;
1576         }
1577 }
1578
1579 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer,
1580                                   void *arg)
1581 {
1582         struct ena_adapter *adapter = (struct ena_adapter *)arg;
1583         struct rte_eth_dev *dev = adapter->rte_dev;
1584
1585         check_for_missing_keep_alive(adapter);
1586         check_for_admin_com_state(adapter);
1587
1588         if (unlikely(adapter->trigger_reset)) {
1589                 RTE_LOG(ERR, PMD, "Trigger reset is on\n");
1590                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1591                         NULL);
1592         }
1593 }
1594
1595 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev,
1596                                  struct ena_com_dev_get_features_ctx *get_feat_ctx)
1597 {
1598         uint32_t io_sq_num, io_cq_num, io_queue_num;
1599
1600         /* Regular queues capabilities */
1601         if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1602                 struct ena_admin_queue_ext_feature_fields *max_queue_ext =
1603                         &get_feat_ctx->max_queue_ext.max_queue_ext;
1604                 io_sq_num = max_queue_ext->max_rx_sq_num;
1605                 io_sq_num = RTE_MIN(io_sq_num, max_queue_ext->max_tx_sq_num);
1606
1607                 io_cq_num = max_queue_ext->max_rx_cq_num;
1608                 io_cq_num = RTE_MIN(io_cq_num, max_queue_ext->max_tx_cq_num);
1609         } else {
1610                 struct ena_admin_queue_feature_desc *max_queues =
1611                         &get_feat_ctx->max_queues;
1612                 io_sq_num = max_queues->max_sq_num;
1613                 io_cq_num = max_queues->max_cq_num;
1614         }
1615
1616         io_queue_num = RTE_MIN(io_sq_num, io_cq_num);
1617
1618         if (unlikely(io_queue_num == 0)) {
1619                 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n");
1620                 return -EFAULT;
1621         }
1622
1623         return io_queue_num;
1624 }
1625
1626 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev)
1627 {
1628         struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 };
1629         struct rte_pci_device *pci_dev;
1630         struct rte_intr_handle *intr_handle;
1631         struct ena_adapter *adapter =
1632                 (struct ena_adapter *)(eth_dev->data->dev_private);
1633         struct ena_com_dev *ena_dev = &adapter->ena_dev;
1634         struct ena_com_dev_get_features_ctx get_feat_ctx;
1635         int rc;
1636
1637         static int adapters_found;
1638         bool wd_state;
1639
1640         memset(adapter, 0, sizeof(struct ena_adapter));
1641         ena_dev = &adapter->ena_dev;
1642
1643         eth_dev->dev_ops = &ena_dev_ops;
1644         eth_dev->rx_pkt_burst = &eth_ena_recv_pkts;
1645         eth_dev->tx_pkt_burst = &eth_ena_xmit_pkts;
1646         eth_dev->tx_pkt_prepare = &eth_ena_prep_pkts;
1647         adapter->rte_eth_dev_data = eth_dev->data;
1648         adapter->rte_dev = eth_dev;
1649
1650         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1651                 return 0;
1652
1653         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1654         adapter->pdev = pci_dev;
1655
1656         PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d",
1657                      pci_dev->addr.domain,
1658                      pci_dev->addr.bus,
1659                      pci_dev->addr.devid,
1660                      pci_dev->addr.function);
1661
1662         intr_handle = &pci_dev->intr_handle;
1663
1664         adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr;
1665         adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr;
1666
1667         if (!adapter->regs) {
1668                 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)",
1669                              ENA_REGS_BAR);
1670                 return -ENXIO;
1671         }
1672
1673         ena_dev->reg_bar = adapter->regs;
1674         ena_dev->dmadev = adapter->pdev;
1675
1676         adapter->id_number = adapters_found;
1677
1678         snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d",
1679                  adapter->id_number);
1680
1681         /* device specific initialization routine */
1682         rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state);
1683         if (rc) {
1684                 PMD_INIT_LOG(CRIT, "Failed to init ENA device");
1685                 goto err;
1686         }
1687         adapter->wd_state = wd_state;
1688
1689         ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1690
1691         calc_queue_ctx.ena_dev = ena_dev;
1692         calc_queue_ctx.get_feat_ctx = &get_feat_ctx;
1693
1694         adapter->num_queues = ena_calc_io_queue_num(ena_dev,
1695                                                     &get_feat_ctx);
1696
1697         rc = ena_calc_queue_size(&calc_queue_ctx);
1698         if (unlikely((rc != 0) || (adapter->num_queues <= 0))) {
1699                 rc = -EFAULT;
1700                 goto err_device_destroy;
1701         }
1702
1703         adapter->tx_ring_size = calc_queue_ctx.tx_queue_size;
1704         adapter->rx_ring_size = calc_queue_ctx.rx_queue_size;
1705
1706         adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size;
1707         adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size;
1708
1709         /* prepare ring structures */
1710         ena_init_rings(adapter);
1711
1712         ena_config_debug_area(adapter);
1713
1714         /* Set max MTU for this device */
1715         adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu;
1716
1717         /* set device support for TSO */
1718         adapter->tso4_supported = get_feat_ctx.offload.tx &
1719                                   ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1720
1721         /* Copy MAC address and point DPDK to it */
1722         eth_dev->data->mac_addrs = (struct ether_addr *)adapter->mac_addr;
1723         ether_addr_copy((struct ether_addr *)get_feat_ctx.dev_attr.mac_addr,
1724                         (struct ether_addr *)adapter->mac_addr);
1725
1726         /*
1727          * Pass the information to the rte_eth_dev_close() that it should also
1728          * release the private port resources.
1729          */
1730         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1731
1732         adapter->drv_stats = rte_zmalloc("adapter stats",
1733                                          sizeof(*adapter->drv_stats),
1734                                          RTE_CACHE_LINE_SIZE);
1735         if (!adapter->drv_stats) {
1736                 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n");
1737                 rc = -ENOMEM;
1738                 goto err_delete_debug_area;
1739         }
1740
1741         rte_intr_callback_register(intr_handle,
1742                                    ena_interrupt_handler_rte,
1743                                    adapter);
1744         rte_intr_enable(intr_handle);
1745         ena_com_set_admin_polling_mode(ena_dev, false);
1746         ena_com_admin_aenq_enable(ena_dev);
1747
1748         if (adapters_found == 0)
1749                 rte_timer_subsystem_init();
1750         rte_timer_init(&adapter->timer_wd);
1751
1752         adapters_found++;
1753         adapter->state = ENA_ADAPTER_STATE_INIT;
1754
1755         return 0;
1756
1757 err_delete_debug_area:
1758         ena_com_delete_debug_area(ena_dev);
1759
1760 err_device_destroy:
1761         ena_com_delete_host_info(ena_dev);
1762         ena_com_admin_destroy(ena_dev);
1763
1764 err:
1765         return rc;
1766 }
1767
1768 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev)
1769 {
1770         struct ena_adapter *adapter =
1771                 (struct ena_adapter *)(eth_dev->data->dev_private);
1772
1773         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1774                 return 0;
1775
1776         if (adapter->state != ENA_ADAPTER_STATE_CLOSED)
1777                 ena_close(eth_dev);
1778
1779         eth_dev->dev_ops = NULL;
1780         eth_dev->rx_pkt_burst = NULL;
1781         eth_dev->tx_pkt_burst = NULL;
1782         eth_dev->tx_pkt_prepare = NULL;
1783
1784         adapter->state = ENA_ADAPTER_STATE_FREE;
1785
1786         return 0;
1787 }
1788
1789 static int ena_dev_configure(struct rte_eth_dev *dev)
1790 {
1791         struct ena_adapter *adapter =
1792                 (struct ena_adapter *)(dev->data->dev_private);
1793
1794         adapter->state = ENA_ADAPTER_STATE_CONFIG;
1795
1796         adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads;
1797         adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads;
1798         return 0;
1799 }
1800
1801 static void ena_init_rings(struct ena_adapter *adapter)
1802 {
1803         int i;
1804
1805         for (i = 0; i < adapter->num_queues; i++) {
1806                 struct ena_ring *ring = &adapter->tx_ring[i];
1807
1808                 ring->configured = 0;
1809                 ring->type = ENA_RING_TYPE_TX;
1810                 ring->adapter = adapter;
1811                 ring->id = i;
1812                 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type;
1813                 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size;
1814                 ring->sgl_size = adapter->max_tx_sgl_size;
1815         }
1816
1817         for (i = 0; i < adapter->num_queues; i++) {
1818                 struct ena_ring *ring = &adapter->rx_ring[i];
1819
1820                 ring->configured = 0;
1821                 ring->type = ENA_RING_TYPE_RX;
1822                 ring->adapter = adapter;
1823                 ring->id = i;
1824                 ring->sgl_size = adapter->max_rx_sgl_size;
1825         }
1826 }
1827
1828 static void ena_infos_get(struct rte_eth_dev *dev,
1829                           struct rte_eth_dev_info *dev_info)
1830 {
1831         struct ena_adapter *adapter;
1832         struct ena_com_dev *ena_dev;
1833         struct ena_com_dev_get_features_ctx feat;
1834         uint64_t rx_feat = 0, tx_feat = 0;
1835         int rc = 0;
1836
1837         ena_assert_msg(dev->data != NULL, "Uninitialized device");
1838         ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device");
1839         adapter = (struct ena_adapter *)(dev->data->dev_private);
1840
1841         ena_dev = &adapter->ena_dev;
1842         ena_assert_msg(ena_dev != NULL, "Uninitialized device");
1843
1844         dev_info->speed_capa =
1845                         ETH_LINK_SPEED_1G   |
1846                         ETH_LINK_SPEED_2_5G |
1847                         ETH_LINK_SPEED_5G   |
1848                         ETH_LINK_SPEED_10G  |
1849                         ETH_LINK_SPEED_25G  |
1850                         ETH_LINK_SPEED_40G  |
1851                         ETH_LINK_SPEED_50G  |
1852                         ETH_LINK_SPEED_100G;
1853
1854         /* Get supported features from HW */
1855         rc = ena_com_get_dev_attr_feat(ena_dev, &feat);
1856         if (unlikely(rc)) {
1857                 RTE_LOG(ERR, PMD,
1858                         "Cannot get attribute for ena device rc= %d\n", rc);
1859                 return;
1860         }
1861
1862         /* Set Tx & Rx features available for device */
1863         if (feat.offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
1864                 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO;
1865
1866         if (feat.offload.tx &
1867             ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
1868                 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM |
1869                         DEV_TX_OFFLOAD_UDP_CKSUM |
1870                         DEV_TX_OFFLOAD_TCP_CKSUM;
1871
1872         if (feat.offload.rx_supported &
1873             ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
1874                 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM |
1875                         DEV_RX_OFFLOAD_UDP_CKSUM  |
1876                         DEV_RX_OFFLOAD_TCP_CKSUM;
1877
1878         rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME;
1879
1880         /* Inform framework about available features */
1881         dev_info->rx_offload_capa = rx_feat;
1882         dev_info->rx_queue_offload_capa = rx_feat;
1883         dev_info->tx_offload_capa = tx_feat;
1884         dev_info->tx_queue_offload_capa = tx_feat;
1885
1886         dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN;
1887         dev_info->max_rx_pktlen  = adapter->max_mtu;
1888         dev_info->max_mac_addrs = 1;
1889
1890         dev_info->max_rx_queues = adapter->num_queues;
1891         dev_info->max_tx_queues = adapter->num_queues;
1892         dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE;
1893
1894         adapter->tx_supported_offloads = tx_feat;
1895         adapter->rx_supported_offloads = rx_feat;
1896
1897         dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size;
1898         dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1899         dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1900                                         adapter->max_rx_sgl_size);
1901         dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1902                                         adapter->max_rx_sgl_size);
1903
1904         dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size;
1905         dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC;
1906         dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1907                                         adapter->max_tx_sgl_size);
1908         dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS,
1909                                         adapter->max_tx_sgl_size);
1910 }
1911
1912 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1913                                   uint16_t nb_pkts)
1914 {
1915         struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);
1916         unsigned int ring_size = rx_ring->ring_size;
1917         unsigned int ring_mask = ring_size - 1;
1918         uint16_t next_to_clean = rx_ring->next_to_clean;
1919         uint16_t desc_in_use = 0;
1920         uint16_t req_id;
1921         unsigned int recv_idx = 0;
1922         struct rte_mbuf *mbuf = NULL;
1923         struct rte_mbuf *mbuf_head = NULL;
1924         struct rte_mbuf *mbuf_prev = NULL;
1925         struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info;
1926         unsigned int completed;
1927
1928         struct ena_com_rx_ctx ena_rx_ctx;
1929         int rc = 0;
1930
1931         /* Check adapter state */
1932         if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
1933                 RTE_LOG(ALERT, PMD,
1934                         "Trying to receive pkts while device is NOT running\n");
1935                 return 0;
1936         }
1937
1938         desc_in_use = rx_ring->next_to_use - next_to_clean;
1939         if (unlikely(nb_pkts > desc_in_use))
1940                 nb_pkts = desc_in_use;
1941
1942         for (completed = 0; completed < nb_pkts; completed++) {
1943                 int segments = 0;
1944
1945                 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
1946                 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
1947                 ena_rx_ctx.descs = 0;
1948                 /* receive packet context */
1949                 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
1950                                     rx_ring->ena_com_io_sq,
1951                                     &ena_rx_ctx);
1952                 if (unlikely(rc)) {
1953                         RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc);
1954                         rx_ring->adapter->reset_reason =
1955                                 ENA_REGS_RESET_TOO_MANY_RX_DESCS;
1956                         rx_ring->adapter->trigger_reset = true;
1957                         return 0;
1958                 }
1959
1960                 if (unlikely(ena_rx_ctx.descs == 0))
1961                         break;
1962
1963                 while (segments < ena_rx_ctx.descs) {
1964                         req_id = ena_rx_ctx.ena_bufs[segments].req_id;
1965                         rc = validate_rx_req_id(rx_ring, req_id);
1966                         if (unlikely(rc))
1967                                 break;
1968
1969                         mbuf = rx_buff_info[req_id];
1970                         mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len;
1971                         mbuf->data_off = RTE_PKTMBUF_HEADROOM;
1972                         mbuf->refcnt = 1;
1973                         mbuf->next = NULL;
1974                         if (unlikely(segments == 0)) {
1975                                 mbuf->nb_segs = ena_rx_ctx.descs;
1976                                 mbuf->port = rx_ring->port_id;
1977                                 mbuf->pkt_len = 0;
1978                                 mbuf_head = mbuf;
1979                         } else {
1980                                 /* for multi-segment pkts create mbuf chain */
1981                                 mbuf_prev->next = mbuf;
1982                         }
1983                         mbuf_head->pkt_len += mbuf->data_len;
1984
1985                         mbuf_prev = mbuf;
1986                         rx_ring->empty_rx_reqs[next_to_clean & ring_mask] =
1987                                 req_id;
1988                         segments++;
1989                         next_to_clean++;
1990                 }
1991                 if (unlikely(rc))
1992                         break;
1993
1994                 /* fill mbuf attributes if any */
1995                 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx);
1996                 mbuf_head->hash.rss = ena_rx_ctx.hash;
1997
1998                 /* pass to DPDK application head mbuf */
1999                 rx_pkts[recv_idx] = mbuf_head;
2000                 recv_idx++;
2001         }
2002
2003         rx_ring->next_to_clean = next_to_clean;
2004
2005         desc_in_use = desc_in_use - completed + 1;
2006         /* Burst refill to save doorbells, memory barriers, const interval */
2007         if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size))
2008                 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use);
2009
2010         return recv_idx;
2011 }
2012
2013 static uint16_t
2014 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2015                 uint16_t nb_pkts)
2016 {
2017         int32_t ret;
2018         uint32_t i;
2019         struct rte_mbuf *m;
2020         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2021         struct ipv4_hdr *ip_hdr;
2022         uint64_t ol_flags;
2023         uint16_t frag_field;
2024
2025         for (i = 0; i != nb_pkts; i++) {
2026                 m = tx_pkts[i];
2027                 ol_flags = m->ol_flags;
2028
2029                 if (!(ol_flags & PKT_TX_IPV4))
2030                         continue;
2031
2032                 /* If there was not L2 header length specified, assume it is
2033                  * length of the ethernet header.
2034                  */
2035                 if (unlikely(m->l2_len == 0))
2036                         m->l2_len = sizeof(struct ether_hdr);
2037
2038                 ip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
2039                                                  m->l2_len);
2040                 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset);
2041
2042                 if ((frag_field & IPV4_HDR_DF_FLAG) != 0) {
2043                         m->packet_type |= RTE_PTYPE_L4_NONFRAG;
2044
2045                         /* If IPv4 header has DF flag enabled and TSO support is
2046                          * disabled, partial chcecksum should not be calculated.
2047                          */
2048                         if (!tx_ring->adapter->tso4_supported)
2049                                 continue;
2050                 }
2051
2052                 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 ||
2053                                 (ol_flags & PKT_TX_L4_MASK) ==
2054                                 PKT_TX_SCTP_CKSUM) {
2055                         rte_errno = -ENOTSUP;
2056                         return i;
2057                 }
2058
2059 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2060                 ret = rte_validate_tx_offload(m);
2061                 if (ret != 0) {
2062                         rte_errno = ret;
2063                         return i;
2064                 }
2065 #endif
2066
2067                 /* In case we are supposed to TSO and have DF not set (DF=0)
2068                  * hardware must be provided with partial checksum, otherwise
2069                  * it will take care of necessary calculations.
2070                  */
2071
2072                 ret = rte_net_intel_cksum_flags_prepare(m,
2073                         ol_flags & ~PKT_TX_TCP_SEG);
2074                 if (ret != 0) {
2075                         rte_errno = ret;
2076                         return i;
2077                 }
2078         }
2079
2080         return i;
2081 }
2082
2083 static void ena_update_hints(struct ena_adapter *adapter,
2084                              struct ena_admin_ena_hw_hints *hints)
2085 {
2086         if (hints->admin_completion_tx_timeout)
2087                 adapter->ena_dev.admin_queue.completion_timeout =
2088                         hints->admin_completion_tx_timeout * 1000;
2089
2090         if (hints->mmio_read_timeout)
2091                 /* convert to usec */
2092                 adapter->ena_dev.mmio_read.reg_read_to =
2093                         hints->mmio_read_timeout * 1000;
2094
2095         if (hints->driver_watchdog_timeout) {
2096                 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT)
2097                         adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT;
2098                 else
2099                         // Convert msecs to ticks
2100                         adapter->keep_alive_timeout =
2101                                 (hints->driver_watchdog_timeout *
2102                                 rte_get_timer_hz()) / 1000;
2103         }
2104 }
2105
2106 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring,
2107                                         struct rte_mbuf *mbuf)
2108 {
2109         int num_segments, rc;
2110
2111         num_segments = mbuf->nb_segs;
2112
2113         if (likely(num_segments < tx_ring->sgl_size))
2114                 return 0;
2115
2116         rc = rte_pktmbuf_linearize(mbuf);
2117         if (unlikely(rc))
2118                 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n");
2119
2120         return rc;
2121 }
2122
2123 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
2124                                   uint16_t nb_pkts)
2125 {
2126         struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue);
2127         uint16_t next_to_use = tx_ring->next_to_use;
2128         uint16_t next_to_clean = tx_ring->next_to_clean;
2129         struct rte_mbuf *mbuf;
2130         unsigned int ring_size = tx_ring->ring_size;
2131         unsigned int ring_mask = ring_size - 1;
2132         struct ena_com_tx_ctx ena_tx_ctx;
2133         struct ena_tx_buffer *tx_info;
2134         struct ena_com_buf *ebuf;
2135         uint16_t rc, req_id, total_tx_descs = 0;
2136         uint16_t sent_idx = 0, empty_tx_reqs;
2137         int nb_hw_desc;
2138
2139         /* Check adapter state */
2140         if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) {
2141                 RTE_LOG(ALERT, PMD,
2142                         "Trying to xmit pkts while device is NOT running\n");
2143                 return 0;
2144         }
2145
2146         empty_tx_reqs = ring_size - (next_to_use - next_to_clean);
2147         if (nb_pkts > empty_tx_reqs)
2148                 nb_pkts = empty_tx_reqs;
2149
2150         for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) {
2151                 mbuf = tx_pkts[sent_idx];
2152
2153                 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf);
2154                 if (unlikely(rc))
2155                         break;
2156
2157                 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];
2158                 tx_info = &tx_ring->tx_buffer_info[req_id];
2159                 tx_info->mbuf = mbuf;
2160                 tx_info->num_of_bufs = 0;
2161                 ebuf = tx_info->bufs;
2162
2163                 /* Prepare TX context */
2164                 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
2165                 memset(&ena_tx_ctx.ena_meta, 0x0,
2166                        sizeof(struct ena_com_tx_meta));
2167                 ena_tx_ctx.ena_bufs = ebuf;
2168                 ena_tx_ctx.req_id = req_id;
2169                 if (tx_ring->tx_mem_queue_type ==
2170                                 ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2171                         /* prepare the push buffer with
2172                          * virtual address of the data
2173                          */
2174                         ena_tx_ctx.header_len =
2175                                 RTE_MIN(mbuf->data_len,
2176                                         tx_ring->tx_max_header_size);
2177                         ena_tx_ctx.push_header =
2178                                 (void *)((char *)mbuf->buf_addr +
2179                                          mbuf->data_off);
2180                 } /* there's no else as we take advantage of memset zeroing */
2181
2182                 /* Set TX offloads flags, if applicable */
2183                 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads);
2184
2185                 if (unlikely(mbuf->ol_flags &
2186                              (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD)))
2187                         rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors);
2188
2189                 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);
2190
2191                 /* Process first segment taking into
2192                  * consideration pushed header
2193                  */
2194                 if (mbuf->data_len > ena_tx_ctx.header_len) {
2195                         ebuf->paddr = mbuf->buf_iova +
2196                                       mbuf->data_off +
2197                                       ena_tx_ctx.header_len;
2198                         ebuf->len = mbuf->data_len - ena_tx_ctx.header_len;
2199                         ebuf++;
2200                         tx_info->num_of_bufs++;
2201                 }
2202
2203                 while ((mbuf = mbuf->next) != NULL) {
2204                         ebuf->paddr = mbuf->buf_iova + mbuf->data_off;
2205                         ebuf->len = mbuf->data_len;
2206                         ebuf++;
2207                         tx_info->num_of_bufs++;
2208                 }
2209
2210                 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
2211
2212                 /* Write data to device */
2213                 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq,
2214                                         &ena_tx_ctx, &nb_hw_desc);
2215                 if (unlikely(rc))
2216                         break;
2217
2218                 tx_info->tx_descs = nb_hw_desc;
2219
2220                 next_to_use++;
2221         }
2222
2223         /* If there are ready packets to be xmitted... */
2224         if (sent_idx > 0) {
2225                 /* ...let HW do its best :-) */
2226                 rte_wmb();
2227                 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2228
2229                 tx_ring->next_to_use = next_to_use;
2230         }
2231
2232         /* Clear complete packets  */
2233         while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) {
2234                 rc = validate_tx_req_id(tx_ring, req_id);
2235                 if (rc)
2236                         break;
2237
2238                 /* Get Tx info & store how many descs were processed  */
2239                 tx_info = &tx_ring->tx_buffer_info[req_id];
2240                 total_tx_descs += tx_info->tx_descs;
2241
2242                 /* Free whole mbuf chain  */
2243                 mbuf = tx_info->mbuf;
2244                 rte_pktmbuf_free(mbuf);
2245                 tx_info->mbuf = NULL;
2246
2247                 /* Put back descriptor to the ring for reuse */
2248                 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;
2249                 next_to_clean++;
2250
2251                 /* If too many descs to clean, leave it for another run */
2252                 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size)))
2253                         break;
2254         }
2255
2256         if (total_tx_descs > 0) {
2257                 /* acknowledge completion of sent packets */
2258                 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs);
2259                 tx_ring->next_to_clean = next_to_clean;
2260         }
2261
2262         return sent_idx;
2263 }
2264
2265 /*********************************************************************
2266  *  PMD configuration
2267  *********************************************************************/
2268 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2269         struct rte_pci_device *pci_dev)
2270 {
2271         return rte_eth_dev_pci_generic_probe(pci_dev,
2272                 sizeof(struct ena_adapter), eth_ena_dev_init);
2273 }
2274
2275 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev)
2276 {
2277         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit);
2278 }
2279
2280 static struct rte_pci_driver rte_ena_pmd = {
2281         .id_table = pci_id_ena_map,
2282         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
2283                      RTE_PCI_DRV_WC_ACTIVATE,
2284         .probe = eth_ena_pci_probe,
2285         .remove = eth_ena_pci_remove,
2286 };
2287
2288 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd);
2289 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map);
2290 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci");
2291
2292 RTE_INIT(ena_init_log)
2293 {
2294         ena_logtype_init = rte_log_register("pmd.net.ena.init");
2295         if (ena_logtype_init >= 0)
2296                 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE);
2297         ena_logtype_driver = rte_log_register("pmd.net.ena.driver");
2298         if (ena_logtype_driver >= 0)
2299                 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
2300 }
2301
2302 /******************************************************************************
2303  ******************************** AENQ Handlers *******************************
2304  *****************************************************************************/
2305 static void ena_update_on_link_change(void *adapter_data,
2306                                       struct ena_admin_aenq_entry *aenq_e)
2307 {
2308         struct rte_eth_dev *eth_dev;
2309         struct ena_adapter *adapter;
2310         struct ena_admin_aenq_link_change_desc *aenq_link_desc;
2311         uint32_t status;
2312
2313         adapter = (struct ena_adapter *)adapter_data;
2314         aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e;
2315         eth_dev = adapter->rte_dev;
2316
2317         status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc);
2318         adapter->link_status = status;
2319
2320         ena_link_update(eth_dev, 0);
2321         _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);
2322 }
2323
2324 static void ena_notification(void *data,
2325                              struct ena_admin_aenq_entry *aenq_e)
2326 {
2327         struct ena_adapter *adapter = (struct ena_adapter *)data;
2328         struct ena_admin_ena_hw_hints *hints;
2329
2330         if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION)
2331                 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n",
2332                         aenq_e->aenq_common_desc.group,
2333                         ENA_ADMIN_NOTIFICATION);
2334
2335         switch (aenq_e->aenq_common_desc.syndrom) {
2336         case ENA_ADMIN_UPDATE_HINTS:
2337                 hints = (struct ena_admin_ena_hw_hints *)
2338                         (&aenq_e->inline_data_w4);
2339                 ena_update_hints(adapter, hints);
2340                 break;
2341         default:
2342                 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n",
2343                         aenq_e->aenq_common_desc.syndrom);
2344         }
2345 }
2346
2347 static void ena_keep_alive(void *adapter_data,
2348                            __rte_unused struct ena_admin_aenq_entry *aenq_e)
2349 {
2350         struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
2351
2352         adapter->timestamp_wd = rte_get_timer_cycles();
2353 }
2354
2355 /**
2356  * This handler will called for unknown event group or unimplemented handlers
2357  **/
2358 static void unimplemented_aenq_handler(__rte_unused void *data,
2359                                        __rte_unused struct ena_admin_aenq_entry *aenq_e)
2360 {
2361         RTE_LOG(ERR, PMD, "Unknown event was received or event with "
2362                           "unimplemented handler\n");
2363 }
2364
2365 static struct ena_aenq_handlers aenq_handlers = {
2366         .handlers = {
2367                 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
2368                 [ENA_ADMIN_NOTIFICATION] = ena_notification,
2369                 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive
2370         },
2371         .unimplemented_handler = unimplemented_aenq_handler
2372 };