4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _ENA_ETHDEV_H_
35 #define _ENA_ETHDEV_H_
37 #include <rte_cycles.h>
39 #include <rte_bus_pci.h>
40 #include <rte_timer.h>
44 #define ENA_REGS_BAR 0
47 #define ENA_MAX_NUM_QUEUES 128
48 #define ENA_MIN_FRAME_LEN 64
49 #define ENA_NAME_MAX_LEN 20
50 #define ENA_PKT_MAX_BUFS 17
52 #define ENA_MIN_MTU 128
54 #define ENA_MMIO_DISABLE_REG_READ BIT(0)
56 #define ENA_WD_TIMEOUT_SEC 3
57 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz())
66 struct ena_tx_buffer {
67 struct rte_mbuf *mbuf;
68 unsigned int tx_descs;
69 unsigned int num_of_bufs;
70 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS];
73 struct ena_calc_queue_size_ctx {
74 struct ena_com_dev_get_features_ctx *get_feat_ctx;
75 struct ena_com_dev *ena_dev;
106 u64 small_copy_len_pkt;
114 enum ena_ring_type type;
115 enum ena_admin_placement_policy_type tx_mem_queue_type;
116 /* Holds the empty requests for TX/RX OOO completions */
118 uint16_t *empty_tx_reqs;
119 uint16_t *empty_rx_reqs;
123 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */
124 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */
126 struct rte_mbuf **rx_refill_buffer;
127 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */
129 struct ena_com_io_cq *ena_com_io_cq;
130 struct ena_com_io_sq *ena_com_io_sq;
132 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]
135 struct rte_mempool *mb_pool;
136 unsigned int port_id;
138 /* Max length PMD can push to device for LLQ */
139 uint8_t tx_max_header_size;
142 uint8_t *push_buf_intermediate_buf;
144 struct ena_adapter *adapter;
149 struct ena_stats_rx rx_stats;
150 struct ena_stats_tx tx_stats;
152 } __rte_cache_aligned;
154 enum ena_adapter_state {
155 ENA_ADAPTER_STATE_FREE = 0,
156 ENA_ADAPTER_STATE_INIT = 1,
157 ENA_ADAPTER_STATE_RUNNING = 2,
158 ENA_ADAPTER_STATE_STOPPED = 3,
159 ENA_ADAPTER_STATE_CONFIG = 4,
160 ENA_ADAPTER_STATE_CLOSED = 5,
163 struct ena_driver_stats {
164 rte_atomic64_t ierrors;
165 rte_atomic64_t oerrors;
166 rte_atomic64_t rx_nombuf;
169 struct ena_stats_dev {
179 /* board specific private data structure */
181 /* OS defined structs */
182 struct rte_pci_device *pdev;
183 struct rte_eth_dev_data *rte_eth_dev_data;
184 struct rte_eth_dev *rte_dev;
186 struct ena_com_dev ena_dev __rte_cache_aligned;
189 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
194 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned;
203 char name[ENA_NAME_MAX_LEN];
204 u8 mac_addr[ETHER_ADDR_LEN];
209 struct ena_driver_stats *drv_stats;
210 enum ena_adapter_state state;
212 uint64_t tx_supported_offloads;
213 uint64_t tx_selected_offloads;
214 uint64_t rx_supported_offloads;
215 uint64_t rx_selected_offloads;
219 enum ena_regs_reset_reason_types reset_reason;
221 struct rte_timer timer_wd;
222 uint64_t timestamp_wd;
223 uint64_t keep_alive_timeout;
230 #endif /* _ENA_ETHDEV_H_ */