drivers/net/enetc/enetc_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018-2020 NXP
   3  */
   4
   5 #include <stdbool.h>
   6 #include <rte_ethdev_pci.h>
   7 #include <rte_random.h>
   8 #include <dpaax_iova_table.h>
   9
  10 #include "enetc_logs.h"
  11 #include "enetc.h"
  12
  13 int enetc_logtype_pmd;
  14
  15 static int
  16 enetc_dev_start(struct rte_eth_dev *dev)
  17 {
  18         struct enetc_eth_hw *hw =
  19                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  20         struct enetc_hw *enetc_hw = &hw->hw;
  21         uint32_t val;
  22
  23         PMD_INIT_FUNC_TRACE();
  24         val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
  25         enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
  26                       val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
  27
  28         /* Enable port */
  29         val = enetc_port_rd(enetc_hw, ENETC_PMR);
  30         enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN);
  31
  32         /* set auto-speed for RGMII */
  33         if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) {
  34                 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
  35                               ENETC_PM0_IFM_RGAUTO);
  36                 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
  37                               ENETC_PM0_IFM_RGAUTO);
  38         }
  39         if (enetc_global_rd(enetc_hw,
  40                             ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) {
  41                 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE,
  42                               ENETC_PM0_IFM_XGMII);
  43                 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE,
  44                               ENETC_PM0_IFM_XGMII);
  45         }
  46
  47         return 0;
  48 }
  49
  50 static void
  51 enetc_dev_stop(struct rte_eth_dev *dev)
  52 {
  53         struct enetc_eth_hw *hw =
  54                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  55         struct enetc_hw *enetc_hw = &hw->hw;
  56         uint32_t val;
  57
  58         PMD_INIT_FUNC_TRACE();
  59         /* Disable port */
  60         val = enetc_port_rd(enetc_hw, ENETC_PMR);
  61         enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
  62
  63         val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
  64         enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
  65                       val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN)));
  66 }
  67
  68 static const uint32_t *
  69 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
  70 {
  71         static const uint32_t ptypes[] = {
  72                 RTE_PTYPE_L2_ETHER,
  73                 RTE_PTYPE_L3_IPV4,
  74                 RTE_PTYPE_L3_IPV6,
  75                 RTE_PTYPE_L4_TCP,
  76                 RTE_PTYPE_L4_UDP,
  77                 RTE_PTYPE_L4_SCTP,
  78                 RTE_PTYPE_L4_ICMP,
  79                 RTE_PTYPE_UNKNOWN
  80         };
  81
  82         return ptypes;
  83 }
  84
  85 /* return 0 means link status changed, -1 means not changed */
  86 static int
  87 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused)
  88 {
  89         struct enetc_eth_hw *hw =
  90                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
  91         struct enetc_hw *enetc_hw = &hw->hw;
  92         struct rte_eth_link link;
  93         uint32_t status;
  94
  95         PMD_INIT_FUNC_TRACE();
  96
  97         memset(&link, 0, sizeof(link));
  98
  99         status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS);
 100
 101         if (status & ENETC_LINK_MODE)
 102                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
 103         else
 104                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
 105
 106         if (status & ENETC_LINK_STATUS)
 107                 link.link_status = ETH_LINK_UP;
 108         else
 109                 link.link_status = ETH_LINK_DOWN;
 110
 111         switch (status & ENETC_LINK_SPEED_MASK) {
 112         case ENETC_LINK_SPEED_1G:
 113                 link.link_speed = ETH_SPEED_NUM_1G;
 114                 break;
 115
 116         case ENETC_LINK_SPEED_100M:
 117                 link.link_speed = ETH_SPEED_NUM_100M;
 118                 break;
 119
 120         default:
 121         case ENETC_LINK_SPEED_10M:
 122                 link.link_speed = ETH_SPEED_NUM_10M;
 123         }
 124
 125         return rte_eth_linkstatus_set(dev, &link);
 126 }
 127
 128 static void
 129 print_ethaddr(const char *name, const struct rte_ether_addr *eth_addr)
 130 {
 131         char buf[RTE_ETHER_ADDR_FMT_SIZE];
 132
 133         rte_ether_format_addr(buf, RTE_ETHER_ADDR_FMT_SIZE, eth_addr);
 134         ENETC_PMD_NOTICE("%s%s\n", name, buf);
 135 }
 136
 137 static int
 138 enetc_hardware_init(struct enetc_eth_hw *hw)
 139 {
 140         struct enetc_hw *enetc_hw = &hw->hw;
 141         uint32_t *mac = (uint32_t *)hw->mac.addr;
 142         uint32_t high_mac = 0;
 143         uint16_t low_mac = 0;
 144
 145         PMD_INIT_FUNC_TRACE();
 146         /* Calculating and storing the base HW addresses */
 147         hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE);
 148         hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE);
 149
 150         /* WA for Rx lock-up HW erratum */
 151         enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1);
 152
 153         /* Enabling Station Interface */
 154         enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
 155
 156         *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
 157         high_mac = (uint32_t)*mac;
 158         mac++;
 159         *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
 160         low_mac = (uint16_t)*mac;
 161
 162         if ((high_mac | low_mac) == 0) {
 163                 char *first_byte;
 164
 165                 ENETC_PMD_NOTICE("MAC is not available for this SI, "
 166                                 "set random MAC\n");
 167                 mac = (uint32_t *)hw->mac.addr;
 168                 *mac = (uint32_t)rte_rand();
 169                 first_byte = (char *)mac;
 170                 *first_byte &= 0xfe;    /* clear multicast bit */
 171                 *first_byte |= 0x02;    /* set local assignment bit (IEEE802) */
 172
 173                 enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), *mac);
 174                 mac++;
 175                 *mac = (uint16_t)rte_rand();
 176                 enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), *mac);
 177                 print_ethaddr("New address: ",
 178                               (const struct rte_ether_addr *)hw->mac.addr);
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int
 185 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused,
 186                     struct rte_eth_dev_info *dev_info)
 187 {
 188         PMD_INIT_FUNC_TRACE();
 189         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 190                 .nb_max = MAX_BD_COUNT,
 191                 .nb_min = MIN_BD_COUNT,
 192                 .nb_align = BD_ALIGN,
 193         };
 194         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 195                 .nb_max = MAX_BD_COUNT,
 196                 .nb_min = MIN_BD_COUNT,
 197                 .nb_align = BD_ALIGN,
 198         };
 199         dev_info->max_rx_queues = MAX_RX_RINGS;
 200         dev_info->max_tx_queues = MAX_TX_RINGS;
 201         dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE;
 202         dev_info->rx_offload_capa =
 203                 (DEV_RX_OFFLOAD_IPV4_CKSUM |
 204                  DEV_RX_OFFLOAD_UDP_CKSUM |
 205                  DEV_RX_OFFLOAD_TCP_CKSUM |
 206                  DEV_RX_OFFLOAD_KEEP_CRC |
 207                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc)
 214 {
 215         int size;
 216
 217         size = nb_desc * sizeof(struct enetc_swbd);
 218         txr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 219         if (txr->q_swbd == NULL)
 220                 return -ENOMEM;
 221
 222         size = nb_desc * sizeof(struct enetc_tx_bd);
 223         txr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 224         if (txr->bd_base == NULL) {
 225                 rte_free(txr->q_swbd);
 226                 txr->q_swbd = NULL;
 227                 return -ENOMEM;
 228         }
 229
 230         txr->bd_count = nb_desc;
 231         txr->next_to_clean = 0;
 232         txr->next_to_use = 0;
 233
 234         return 0;
 235 }
 236
 237 static void
 238 enetc_free_bdr(struct enetc_bdr *rxr)
 239 {
 240         rte_free(rxr->q_swbd);
 241         rte_free(rxr->bd_base);
 242         rxr->q_swbd = NULL;
 243         rxr->bd_base = NULL;
 244 }
 245
 246 static void
 247 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring)
 248 {
 249         int idx = tx_ring->index;
 250         phys_addr_t bd_address;
 251
 252         bd_address = (phys_addr_t)
 253                      rte_mem_virt2iova((const void *)tx_ring->bd_base);
 254         enetc_txbdr_wr(hw, idx, ENETC_TBBAR0,
 255                        lower_32_bits((uint64_t)bd_address));
 256         enetc_txbdr_wr(hw, idx, ENETC_TBBAR1,
 257                        upper_32_bits((uint64_t)bd_address));
 258         enetc_txbdr_wr(hw, idx, ENETC_TBLENR,
 259                        ENETC_RTBLENR_LEN(tx_ring->bd_count));
 260
 261         enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
 262         enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0);
 263         tx_ring->tcir = (void *)((size_t)hw->reg +
 264                         ENETC_BDR(TX, idx, ENETC_TBCIR));
 265         tx_ring->tcisr = (void *)((size_t)hw->reg +
 266                          ENETC_BDR(TX, idx, ENETC_TBCISR));
 267 }
 268
 269 static int
 270 enetc_tx_queue_setup(struct rte_eth_dev *dev,
 271                      uint16_t queue_idx,
 272                      uint16_t nb_desc,
 273                      unsigned int socket_id __rte_unused,
 274                      const struct rte_eth_txconf *tx_conf)
 275 {
 276         int err = 0;
 277         struct enetc_bdr *tx_ring;
 278         struct rte_eth_dev_data *data = dev->data;
 279         struct enetc_eth_adapter *priv =
 280                         ENETC_DEV_PRIVATE(data->dev_private);
 281
 282         PMD_INIT_FUNC_TRACE();
 283         if (nb_desc > MAX_BD_COUNT)
 284                 return -1;
 285
 286         tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
 287         if (tx_ring == NULL) {
 288                 ENETC_PMD_ERR("Failed to allocate TX ring memory");
 289                 err = -ENOMEM;
 290                 return -1;
 291         }
 292
 293         err = enetc_alloc_txbdr(tx_ring, nb_desc);
 294         if (err)
 295                 goto fail;
 296
 297         tx_ring->index = queue_idx;
 298         tx_ring->ndev = dev;
 299         enetc_setup_txbdr(&priv->hw.hw, tx_ring);
 300         data->tx_queues[queue_idx] = tx_ring;
 301
 302         if (!tx_conf->tx_deferred_start) {
 303                 /* enable ring */
 304                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index,
 305                                ENETC_TBMR, ENETC_TBMR_EN);
 306                 dev->data->tx_queue_state[tx_ring->index] =
 307                                RTE_ETH_QUEUE_STATE_STARTED;
 308         } else {
 309                 dev->data->tx_queue_state[tx_ring->index] =
 310                                RTE_ETH_QUEUE_STATE_STOPPED;
 311         }
 312
 313         return 0;
 314 fail:
 315         rte_free(tx_ring);
 316
 317         return err;
 318 }
 319
 320 static void
 321 enetc_tx_queue_release(void *txq)
 322 {
 323         if (txq == NULL)
 324                 return;
 325
 326         struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq;
 327         struct enetc_eth_hw *eth_hw =
 328                 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private);
 329         struct enetc_hw *hw;
 330         struct enetc_swbd *tx_swbd;
 331         int i;
 332         uint32_t val;
 333
 334         /* Disable the ring */
 335         hw = &eth_hw->hw;
 336         val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR);
 337         val &= (~ENETC_TBMR_EN);
 338         enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val);
 339
 340         /* clean the ring*/
 341         i = tx_ring->next_to_clean;
 342         tx_swbd = &tx_ring->q_swbd[i];
 343         while (tx_swbd->buffer_addr != NULL) {
 344                 rte_pktmbuf_free(tx_swbd->buffer_addr);
 345                 tx_swbd->buffer_addr = NULL;
 346                 tx_swbd++;
 347                 i++;
 348                 if (unlikely(i == tx_ring->bd_count)) {
 349                         i = 0;
 350                         tx_swbd = &tx_ring->q_swbd[i];
 351                 }
 352         }
 353
 354         enetc_free_bdr(tx_ring);
 355         rte_free(tx_ring);
 356 }
 357
 358 static int
 359 enetc_alloc_rxbdr(struct enetc_bdr *rxr,
 360                   uint16_t nb_rx_desc)
 361 {
 362         int size;
 363
 364         size = nb_rx_desc * sizeof(struct enetc_swbd);
 365         rxr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 366         if (rxr->q_swbd == NULL)
 367                 return -ENOMEM;
 368
 369         size = nb_rx_desc * sizeof(union enetc_rx_bd);
 370         rxr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN);
 371         if (rxr->bd_base == NULL) {
 372                 rte_free(rxr->q_swbd);
 373                 rxr->q_swbd = NULL;
 374                 return -ENOMEM;
 375         }
 376
 377         rxr->bd_count = nb_rx_desc;
 378         rxr->next_to_clean = 0;
 379         rxr->next_to_use = 0;
 380         rxr->next_to_alloc = 0;
 381
 382         return 0;
 383 }
 384
 385 static void
 386 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring,
 387                   struct rte_mempool *mb_pool)
 388 {
 389         int idx = rx_ring->index;
 390         uint16_t buf_size;
 391         phys_addr_t bd_address;
 392
 393         bd_address = (phys_addr_t)
 394                      rte_mem_virt2iova((const void *)rx_ring->bd_base);
 395         enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0,
 396                        lower_32_bits((uint64_t)bd_address));
 397         enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1,
 398                        upper_32_bits((uint64_t)bd_address));
 399         enetc_rxbdr_wr(hw, idx, ENETC_RBLENR,
 400                        ENETC_RTBLENR_LEN(rx_ring->bd_count));
 401
 402         rx_ring->mb_pool = mb_pool;
 403         rx_ring->rcir = (void *)((size_t)hw->reg +
 404                         ENETC_BDR(RX, idx, ENETC_RBCIR));
 405         enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring)));
 406         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) -
 407                    RTE_PKTMBUF_HEADROOM);
 408         enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size);
 409         enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0);
 410 }
 411
 412 static int
 413 enetc_rx_queue_setup(struct rte_eth_dev *dev,
 414                      uint16_t rx_queue_id,
 415                      uint16_t nb_rx_desc,
 416                      unsigned int socket_id __rte_unused,
 417                      const struct rte_eth_rxconf *rx_conf,
 418                      struct rte_mempool *mb_pool)
 419 {
 420         int err = 0;
 421         struct enetc_bdr *rx_ring;
 422         struct rte_eth_dev_data *data =  dev->data;
 423         struct enetc_eth_adapter *adapter =
 424                         ENETC_DEV_PRIVATE(data->dev_private);
 425         uint64_t rx_offloads = data->dev_conf.rxmode.offloads;
 426
 427         PMD_INIT_FUNC_TRACE();
 428         if (nb_rx_desc > MAX_BD_COUNT)
 429                 return -1;
 430
 431         rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0);
 432         if (rx_ring == NULL) {
 433                 ENETC_PMD_ERR("Failed to allocate RX ring memory");
 434                 err = -ENOMEM;
 435                 return err;
 436         }
 437
 438         err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc);
 439         if (err)
 440                 goto fail;
 441
 442         rx_ring->index = rx_queue_id;
 443         rx_ring->ndev = dev;
 444         enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool);
 445         data->rx_queues[rx_queue_id] = rx_ring;
 446
 447         if (!rx_conf->rx_deferred_start) {
 448                 /* enable ring */
 449                 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR,
 450                                ENETC_RBMR_EN);
 451                 dev->data->rx_queue_state[rx_ring->index] =
 452                                RTE_ETH_QUEUE_STATE_STARTED;
 453         } else {
 454                 dev->data->rx_queue_state[rx_ring->index] =
 455                                RTE_ETH_QUEUE_STATE_STOPPED;
 456         }
 457
 458         rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ?
 459                                      RTE_ETHER_CRC_LEN : 0);
 460
 461         return 0;
 462 fail:
 463         rte_free(rx_ring);
 464
 465         return err;
 466 }
 467
 468 static void
 469 enetc_rx_queue_release(void *rxq)
 470 {
 471         if (rxq == NULL)
 472                 return;
 473
 474         struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq;
 475         struct enetc_eth_hw *eth_hw =
 476                 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private);
 477         struct enetc_swbd *q_swbd;
 478         struct enetc_hw *hw;
 479         uint32_t val;
 480         int i;
 481
 482         /* Disable the ring */
 483         hw = &eth_hw->hw;
 484         val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR);
 485         val &= (~ENETC_RBMR_EN);
 486         enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val);
 487
 488         /* Clean the ring */
 489         i = rx_ring->next_to_clean;
 490         q_swbd = &rx_ring->q_swbd[i];
 491         while (i != rx_ring->next_to_use) {
 492                 rte_pktmbuf_free(q_swbd->buffer_addr);
 493                 q_swbd->buffer_addr = NULL;
 494                 q_swbd++;
 495                 i++;
 496                 if (unlikely(i == rx_ring->bd_count)) {
 497                         i = 0;
 498                         q_swbd = &rx_ring->q_swbd[i];
 499                 }
 500         }
 501
 502         enetc_free_bdr(rx_ring);
 503         rte_free(rx_ring);
 504 }
 505
 506 static
 507 int enetc_stats_get(struct rte_eth_dev *dev,
 508                     struct rte_eth_stats *stats)
 509 {
 510         struct enetc_eth_hw *hw =
 511                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512         struct enetc_hw *enetc_hw = &hw->hw;
 513
 514         /* Total received packets, bad + good, if we want to get counters of
 515          * only good received packets then use ENETC_PM0_RFRM,
 516          * ENETC_PM0_TFRM registers.
 517          */
 518         stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT);
 519         stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT);
 520         stats->ibytes =  enetc_port_rd(enetc_hw, ENETC_PM0_REOCT);
 521         stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT);
 522         /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without
 523          * truncated packets
 524          */
 525         stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP);
 526         stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR);
 527         stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR);
 528
 529         return 0;
 530 }
 531
 532 static int
 533 enetc_stats_reset(struct rte_eth_dev *dev)
 534 {
 535         struct enetc_eth_hw *hw =
 536                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 537         struct enetc_hw *enetc_hw = &hw->hw;
 538
 539         enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS);
 540
 541         return 0;
 542 }
 543
 544 static void
 545 enetc_dev_close(struct rte_eth_dev *dev)
 546 {
 547         uint16_t i;
 548
 549         PMD_INIT_FUNC_TRACE();
 550         enetc_dev_stop(dev);
 551
 552         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 553                 enetc_rx_queue_release(dev->data->rx_queues[i]);
 554                 dev->data->rx_queues[i] = NULL;
 555         }
 556         dev->data->nb_rx_queues = 0;
 557
 558         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 559                 enetc_tx_queue_release(dev->data->tx_queues[i]);
 560                 dev->data->tx_queues[i] = NULL;
 561         }
 562         dev->data->nb_tx_queues = 0;
 563 }
 564
 565 static int
 566 enetc_promiscuous_enable(struct rte_eth_dev *dev)
 567 {
 568         struct enetc_eth_hw *hw =
 569                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 570         struct enetc_hw *enetc_hw = &hw->hw;
 571         uint32_t psipmr = 0;
 572
 573         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 574
 575         /* Setting to enable promiscuous mode*/
 576         psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
 577
 578         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 579
 580         return 0;
 581 }
 582
 583 static int
 584 enetc_promiscuous_disable(struct rte_eth_dev *dev)
 585 {
 586         struct enetc_eth_hw *hw =
 587                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 588         struct enetc_hw *enetc_hw = &hw->hw;
 589         uint32_t psipmr = 0;
 590
 591         /* Setting to disable promiscuous mode for SI0*/
 592         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 593         psipmr &= (~ENETC_PSIPMR_SET_UP(0));
 594
 595         if (dev->data->all_multicast == 0)
 596                 psipmr &= (~ENETC_PSIPMR_SET_MP(0));
 597
 598         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 599
 600         return 0;
 601 }
 602
 603 static int
 604 enetc_allmulticast_enable(struct rte_eth_dev *dev)
 605 {
 606         struct enetc_eth_hw *hw =
 607                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 608         struct enetc_hw *enetc_hw = &hw->hw;
 609         uint32_t psipmr = 0;
 610
 611         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR);
 612
 613         /* Setting to enable allmulticast mode for SI0*/
 614         psipmr |= ENETC_PSIPMR_SET_MP(0);
 615
 616         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 617
 618         return 0;
 619 }
 620
 621 static int
 622 enetc_allmulticast_disable(struct rte_eth_dev *dev)
 623 {
 624         struct enetc_eth_hw *hw =
 625                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 626         struct enetc_hw *enetc_hw = &hw->hw;
 627         uint32_t psipmr = 0;
 628
 629         if (dev->data->promiscuous == 1)
 630                 return 0; /* must remain in all_multicast mode */
 631
 632         /* Setting to disable all multicast mode for SI0*/
 633         psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) &
 634                                ~(ENETC_PSIPMR_SET_MP(0));
 635
 636         enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr);
 637
 638         return 0;
 639 }
 640
 641 static int
 642 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 643 {
 644         struct enetc_eth_hw *hw =
 645                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 646         struct enetc_hw *enetc_hw = &hw->hw;
 647         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 648
 649         /* check that mtu is within the allowed range */
 650         if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE)
 651                 return -EINVAL;
 652
 653         /*
 654          * Refuse mtu that requires the support of scattered packets
 655          * when this feature has not been enabled before.
 656          */
 657         if (dev->data->min_rx_buf_size &&
 658                 !dev->data->scattered_rx && frame_size >
 659                 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
 660                 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer");
 661                 return -EINVAL;
 662         }
 663
 664         if (frame_size > RTE_ETHER_MAX_LEN)
 665                 dev->data->dev_conf.rxmode.offloads &=
 666                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 667         else
 668                 dev->data->dev_conf.rxmode.offloads &=
 669                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 670
 671         enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE);
 672         enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE);
 673
 674         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 675
 676         /*setting the MTU*/
 677         enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) |
 678                       ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE));
 679
 680         return 0;
 681 }
 682
 683 static int
 684 enetc_dev_configure(struct rte_eth_dev *dev)
 685 {
 686         struct enetc_eth_hw *hw =
 687                 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 688         struct enetc_hw *enetc_hw = &hw->hw;
 689         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 690         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 691         uint32_t checksum = L3_CKSUM | L4_CKSUM;
 692
 693         PMD_INIT_FUNC_TRACE();
 694
 695         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 696                 uint32_t max_len;
 697
 698                 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 699
 700                 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM,
 701                               ENETC_SET_MAXFRM(max_len));
 702                 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0),
 703                               ENETC_MAC_MAXFRM_SIZE);
 704                 enetc_port_wr(enetc_hw, ENETC_PTXMBAR,
 705                               2 * ENETC_MAC_MAXFRM_SIZE);
 706                 dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
 707                         RTE_ETHER_CRC_LEN;
 708         }
 709
 710         if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
 711                 int config;
 712
 713                 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
 714                 config |= ENETC_PM0_CRC;
 715                 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config);
 716         }
 717
 718         if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
 719                 checksum &= ~L3_CKSUM;
 720
 721         if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM))
 722                 checksum &= ~L4_CKSUM;
 723
 724         enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum);
 725
 726
 727         return 0;
 728 }
 729
 730 static int
 731 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
 732 {
 733         struct enetc_eth_adapter *priv =
 734                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 735         struct enetc_bdr *rx_ring;
 736         uint32_t rx_data;
 737
 738         rx_ring = dev->data->rx_queues[qidx];
 739         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
 740                 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
 741                                          ENETC_RBMR);
 742                 rx_data = rx_data | ENETC_RBMR_EN;
 743                 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
 744                                rx_data);
 745                 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int
 752 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
 753 {
 754         struct enetc_eth_adapter *priv =
 755                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 756         struct enetc_bdr *rx_ring;
 757         uint32_t rx_data;
 758
 759         rx_ring = dev->data->rx_queues[qidx];
 760         if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
 761                 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index,
 762                                          ENETC_RBMR);
 763                 rx_data = rx_data & (~ENETC_RBMR_EN);
 764                 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR,
 765                                rx_data);
 766                 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 767         }
 768
 769         return 0;
 770 }
 771
 772 static int
 773 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
 774 {
 775         struct enetc_eth_adapter *priv =
 776                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 777         struct enetc_bdr *tx_ring;
 778         uint32_t tx_data;
 779
 780         tx_ring = dev->data->tx_queues[qidx];
 781         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) {
 782                 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
 783                                          ENETC_TBMR);
 784                 tx_data = tx_data | ENETC_TBMR_EN;
 785                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
 786                                tx_data);
 787                 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static int
 794 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
 795 {
 796         struct enetc_eth_adapter *priv =
 797                         ENETC_DEV_PRIVATE(dev->data->dev_private);
 798         struct enetc_bdr *tx_ring;
 799         uint32_t tx_data;
 800
 801         tx_ring = dev->data->tx_queues[qidx];
 802         if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) {
 803                 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index,
 804                                          ENETC_TBMR);
 805                 tx_data = tx_data & (~ENETC_TBMR_EN);
 806                 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR,
 807                                tx_data);
 808                 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 809         }
 810
 811         return 0;
 812 }
 813
 814 /*
 815  * The set of PCI devices this driver supports
 816  */
 817 static const struct rte_pci_id pci_id_enetc_map[] = {
 818         { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) },
 819         { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) },
 820         { .vendor_id = 0, /* sentinel */ },
 821 };
 822
 823 /* Features supported by this driver */
 824 static const struct eth_dev_ops enetc_ops = {
 825         .dev_configure        = enetc_dev_configure,
 826         .dev_start            = enetc_dev_start,
 827         .dev_stop             = enetc_dev_stop,
 828         .dev_close            = enetc_dev_close,
 829         .link_update          = enetc_link_update,
 830         .stats_get            = enetc_stats_get,
 831         .stats_reset          = enetc_stats_reset,
 832         .promiscuous_enable   = enetc_promiscuous_enable,
 833         .promiscuous_disable  = enetc_promiscuous_disable,
 834         .allmulticast_enable  = enetc_allmulticast_enable,
 835         .allmulticast_disable = enetc_allmulticast_disable,
 836         .dev_infos_get        = enetc_dev_infos_get,
 837         .mtu_set              = enetc_mtu_set,
 838         .rx_queue_setup       = enetc_rx_queue_setup,
 839         .rx_queue_start       = enetc_rx_queue_start,
 840         .rx_queue_stop        = enetc_rx_queue_stop,
 841         .rx_queue_release     = enetc_rx_queue_release,
 842         .tx_queue_setup       = enetc_tx_queue_setup,
 843         .tx_queue_start       = enetc_tx_queue_start,
 844         .tx_queue_stop        = enetc_tx_queue_stop,
 845         .tx_queue_release     = enetc_tx_queue_release,
 846         .dev_supported_ptypes_get = enetc_supported_ptypes_get,
 847 };
 848
 849 /**
 850  * Initialisation of the enetc device
 851  *
 852  * @param eth_dev
 853  *   - Pointer to the structure rte_eth_dev
 854  *
 855  * @return
 856  *   - On success, zero.
 857  *   - On failure, negative value.
 858  */
 859 static int
 860 enetc_dev_init(struct rte_eth_dev *eth_dev)
 861 {
 862         int error = 0;
 863         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 864         struct enetc_eth_hw *hw =
 865                 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 866
 867         PMD_INIT_FUNC_TRACE();
 868         eth_dev->dev_ops = &enetc_ops;
 869         eth_dev->rx_pkt_burst = &enetc_recv_pkts;
 870         eth_dev->tx_pkt_burst = &enetc_xmit_pkts;
 871
 872         /* Retrieving and storing the HW base address of device */
 873         hw->hw.reg = (void *)pci_dev->mem_resource[0].addr;
 874         hw->device_id = pci_dev->id.device_id;
 875
 876         error = enetc_hardware_init(hw);
 877         if (error != 0) {
 878                 ENETC_PMD_ERR("Hardware initialization failed");
 879                 return -1;
 880         }
 881
 882         /* Allocate memory for storing MAC addresses */
 883         eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth",
 884                                         RTE_ETHER_ADDR_LEN, 0);
 885         if (!eth_dev->data->mac_addrs) {
 886                 ENETC_PMD_ERR("Failed to allocate %d bytes needed to "
 887                               "store MAC addresses",
 888                               RTE_ETHER_ADDR_LEN * 1);
 889                 error = -ENOMEM;
 890                 return -1;
 891         }
 892
 893         /* Copy the permanent MAC address */
 894         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
 895                         &eth_dev->data->mac_addrs[0]);
 896
 897         /* Set MTU */
 898         enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM,
 899                       ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN));
 900         eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN -
 901                 RTE_ETHER_CRC_LEN;
 902
 903         if (rte_eal_iova_mode() == RTE_IOVA_PA)
 904                 dpaax_iova_table_populate();
 905
 906         ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x",
 907                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 908                         pci_dev->id.device_id);
 909         return 0;
 910 }
 911
 912 static int
 913 enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused)
 914 {
 915         PMD_INIT_FUNC_TRACE();
 916
 917         if (rte_eal_iova_mode() == RTE_IOVA_PA)
 918                 dpaax_iova_table_depopulate();
 919
 920         return 0;
 921 }
 922
 923 static int
 924 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 925                            struct rte_pci_device *pci_dev)
 926 {
 927         return rte_eth_dev_pci_generic_probe(pci_dev,
 928                                              sizeof(struct enetc_eth_adapter),
 929                                              enetc_dev_init);
 930 }
 931
 932 static int
 933 enetc_pci_remove(struct rte_pci_device *pci_dev)
 934 {
 935         return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit);
 936 }
 937
 938 static struct rte_pci_driver rte_enetc_pmd = {
 939         .id_table = pci_id_enetc_map,
 940         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 941         .probe = enetc_pci_probe,
 942         .remove = enetc_pci_remove,
 943 };
 944
 945 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd);
 946 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map);
 947 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci");
 948
 949 RTE_INIT(enetc_pmd_init_log)
 950 {
 951         enetc_logtype_pmd = rte_log_register("pmd.net.enetc");
 952         if (enetc_logtype_pmd >= 0)
 953                 rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE);
 954 }