drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* A period of quiescence for switch */
  56 #define FM10K_SWITCH_QUIESCE_US 10000
  57 /* Number of chars per uint32 type */
  58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  60
  61 /* default 1:1 map from queue ID to interrupt vector ID */
  62 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  63
  64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  65 #define MAX_LPORT_NUM    128
  66 #define GLORT_FD_Q_BASE  0x40
  67 #define GLORT_PF_MASK    0xFFC0
  68 #define GLORT_FD_MASK    GLORT_PF_MASK
  69 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  70
  71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  77 static int
  78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  80         const u8 *mac, bool add, uint32_t pool);
  81 static void fm10k_tx_queue_release(void *queue);
  82 static void fm10k_rx_queue_release(void *queue);
  83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  85 static int fm10k_check_ftag(struct rte_devargs *devargs);
  86
  87 struct fm10k_xstats_name_off {
  88         char name[RTE_ETH_XSTATS_NAME_SIZE];
  89         unsigned offset;
  90 };
  91
  92 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  93         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  94         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  95         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  96         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  97         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  98         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  99         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 100         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 101                 nodesc_drop)},
 102 };
 103
 104 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 105                 sizeof(fm10k_hw_stats_strings[0]))
 106
 107 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 108         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 109         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 110         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 111 };
 112
 113 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 114                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 115
 116 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 117         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 118         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 119 };
 120
 121 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 122                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 123
 124 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 125                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 126 static int
 127 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 128
 129 static void
 130 fm10k_mbx_initlock(struct fm10k_hw *hw)
 131 {
 132         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 133 }
 134
 135 static void
 136 fm10k_mbx_lock(struct fm10k_hw *hw)
 137 {
 138         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 139                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 140 }
 141
 142 static void
 143 fm10k_mbx_unlock(struct fm10k_hw *hw)
 144 {
 145         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 146 }
 147
 148 /* Stubs needed for linkage when vPMD is disabled */
 149 int __attribute__((weak))
 150 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 151 {
 152         return -1;
 153 }
 154
 155 uint16_t __attribute__((weak))
 156 fm10k_recv_pkts_vec(
 157         __rte_unused void *rx_queue,
 158         __rte_unused struct rte_mbuf **rx_pkts,
 159         __rte_unused uint16_t nb_pkts)
 160 {
 161         return 0;
 162 }
 163
 164 uint16_t __attribute__((weak))
 165 fm10k_recv_scattered_pkts_vec(
 166                 __rte_unused void *rx_queue,
 167                 __rte_unused struct rte_mbuf **rx_pkts,
 168                 __rte_unused uint16_t nb_pkts)
 169 {
 170         return 0;
 171 }
 172
 173 int __attribute__((weak))
 174 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 175
 176 {
 177         return -1;
 178 }
 179
 180 void __attribute__((weak))
 181 fm10k_rx_queue_release_mbufs_vec(
 182                 __rte_unused struct fm10k_rx_queue *rxq)
 183 {
 184         return;
 185 }
 186
 187 void __attribute__((weak))
 188 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 189 {
 190         return;
 191 }
 192
 193 int __attribute__((weak))
 194 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 195 {
 196         return -1;
 197 }
 198
 199 uint16_t __attribute__((weak))
 200 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 201                 __rte_unused struct rte_mbuf **tx_pkts,
 202                 __rte_unused uint16_t nb_pkts)
 203 {
 204         return 0;
 205 }
 206
 207 /*
 208  * reset queue to initial state, allocate software buffers used when starting
 209  * device.
 210  * return 0 on success
 211  * return -ENOMEM if buffers cannot be allocated
 212  * return -EINVAL if buffers do not satisfy alignment condition
 213  */
 214 static inline int
 215 rx_queue_reset(struct fm10k_rx_queue *q)
 216 {
 217         static const union fm10k_rx_desc zero = {{0} };
 218         uint64_t dma_addr;
 219         int i, diag;
 220         PMD_INIT_FUNC_TRACE();
 221
 222         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 223         if (diag != 0)
 224                 return -ENOMEM;
 225
 226         for (i = 0; i < q->nb_desc; ++i) {
 227                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 228                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 229                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 230                                                 q->nb_desc);
 231                         return -EINVAL;
 232                 }
 233                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 234                 q->hw_ring[i].q.pkt_addr = dma_addr;
 235                 q->hw_ring[i].q.hdr_addr = dma_addr;
 236         }
 237
 238         /* initialize extra software ring entries. Space for these extra
 239          * entries is always allocated.
 240          */
 241         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 242         for (i = 0; i < q->nb_fake_desc; ++i) {
 243                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 244                 q->hw_ring[q->nb_desc + i] = zero;
 245         }
 246
 247         q->next_dd = 0;
 248         q->next_alloc = 0;
 249         q->next_trigger = q->alloc_thresh - 1;
 250         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 251         q->rxrearm_start = 0;
 252         q->rxrearm_nb = 0;
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * clean queue, descriptor rings, free software buffers used when stopping
 259  * device.
 260  */
 261 static inline void
 262 rx_queue_clean(struct fm10k_rx_queue *q)
 263 {
 264         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 265         uint32_t i;
 266         PMD_INIT_FUNC_TRACE();
 267
 268         /* zero descriptor rings */
 269         for (i = 0; i < q->nb_desc; ++i)
 270                 q->hw_ring[i] = zero;
 271
 272         /* zero faked descriptors */
 273         for (i = 0; i < q->nb_fake_desc; ++i)
 274                 q->hw_ring[q->nb_desc + i] = zero;
 275
 276         /* vPMD driver has a different way of releasing mbufs. */
 277         if (q->rx_using_sse) {
 278                 fm10k_rx_queue_release_mbufs_vec(q);
 279                 return;
 280         }
 281
 282         /* free software buffers */
 283         for (i = 0; i < q->nb_desc; ++i) {
 284                 if (q->sw_ring[i]) {
 285                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 286                         q->sw_ring[i] = NULL;
 287                 }
 288         }
 289 }
 290
 291 /*
 292  * free all queue memory used when releasing the queue (i.e. configure)
 293  */
 294 static inline void
 295 rx_queue_free(struct fm10k_rx_queue *q)
 296 {
 297         PMD_INIT_FUNC_TRACE();
 298         if (q) {
 299                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 300                 rx_queue_clean(q);
 301                 if (q->sw_ring) {
 302                         rte_free(q->sw_ring);
 303                         q->sw_ring = NULL;
 304                 }
 305                 rte_free(q);
 306                 q = NULL;
 307         }
 308 }
 309
 310 /*
 311  * disable RX queue, wait unitl HW finished necessary flush operation
 312  */
 313 static inline int
 314 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 315 {
 316         uint32_t reg, i;
 317
 318         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 319         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 320                         reg & ~FM10K_RXQCTL_ENABLE);
 321
 322         /* Wait 100us at most */
 323         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 324                 rte_delay_us(1);
 325                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 326                 if (!(reg & FM10K_RXQCTL_ENABLE))
 327                         break;
 328         }
 329
 330         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 331                 return -1;
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * reset queue to initial state, allocate software buffers used when starting
 338  * device
 339  */
 340 static inline void
 341 tx_queue_reset(struct fm10k_tx_queue *q)
 342 {
 343         PMD_INIT_FUNC_TRACE();
 344         q->last_free = 0;
 345         q->next_free = 0;
 346         q->nb_used = 0;
 347         q->nb_free = q->nb_desc - 1;
 348         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 349         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 350 }
 351
 352 /*
 353  * clean queue, descriptor rings, free software buffers used when stopping
 354  * device
 355  */
 356 static inline void
 357 tx_queue_clean(struct fm10k_tx_queue *q)
 358 {
 359         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 360         uint32_t i;
 361         PMD_INIT_FUNC_TRACE();
 362
 363         /* zero descriptor rings */
 364         for (i = 0; i < q->nb_desc; ++i)
 365                 q->hw_ring[i] = zero;
 366
 367         /* free software buffers */
 368         for (i = 0; i < q->nb_desc; ++i) {
 369                 if (q->sw_ring[i]) {
 370                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 371                         q->sw_ring[i] = NULL;
 372                 }
 373         }
 374 }
 375
 376 /*
 377  * free all queue memory used when releasing the queue (i.e. configure)
 378  */
 379 static inline void
 380 tx_queue_free(struct fm10k_tx_queue *q)
 381 {
 382         PMD_INIT_FUNC_TRACE();
 383         if (q) {
 384                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 385                 tx_queue_clean(q);
 386                 if (q->rs_tracker.list) {
 387                         rte_free(q->rs_tracker.list);
 388                         q->rs_tracker.list = NULL;
 389                 }
 390                 if (q->sw_ring) {
 391                         rte_free(q->sw_ring);
 392                         q->sw_ring = NULL;
 393                 }
 394                 rte_free(q);
 395                 q = NULL;
 396         }
 397 }
 398
 399 /*
 400  * disable TX queue, wait unitl HW finished necessary flush operation
 401  */
 402 static inline int
 403 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 404 {
 405         uint32_t reg, i;
 406
 407         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 408         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 409                         reg & ~FM10K_TXDCTL_ENABLE);
 410
 411         /* Wait 100us at most */
 412         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 413                 rte_delay_us(1);
 414                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 415                 if (!(reg & FM10K_TXDCTL_ENABLE))
 416                         break;
 417         }
 418
 419         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 420                 return -1;
 421
 422         return 0;
 423 }
 424
 425 static int
 426 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 427 {
 428         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 429         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 430         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 431         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 432
 433         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 434
 435         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 436                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 437                 return -EINVAL;
 438         }
 439
 440         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 441                 return 0;
 442
 443         if (hw->mac.type == fm10k_mac_vf) {
 444                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 445                 return -EINVAL;
 446         }
 447
 448         /* Check VMDQ queue pool number */
 449         if (vmdq_conf->nb_queue_pools >
 450                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 451                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 452                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 453                         vmdq_conf->nb_queue_pools);
 454                 return -EINVAL;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static const struct fm10k_txq_ops def_txq_ops = {
 461         .reset = tx_queue_reset,
 462 };
 463
 464 static int
 465 fm10k_dev_configure(struct rte_eth_dev *dev)
 466 {
 467         int ret;
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 472                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 473         /* multipe queue mode checking */
 474         ret  = fm10k_check_mq_mode(dev);
 475         if (ret != 0) {
 476                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 477                             ret);
 478                 return ret;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* fls = find last set bit = 32 minus the number of leading zeros */
 485 #ifndef fls
 486 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 487 #endif
 488
 489 static void
 490 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 491 {
 492         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 493         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 494         uint32_t i;
 495
 496         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 497
 498         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 499                 if (!vmdq_conf->pool_map[i].pools)
 500                         continue;
 501                 fm10k_mbx_lock(hw);
 502                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 503                 fm10k_mbx_unlock(hw);
 504         }
 505 }
 506
 507 static void
 508 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 509 {
 510         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         /* Add default mac address */
 513         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 514                 MAIN_VSI_POOL_NUMBER);
 515 }
 516
 517 static void
 518 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 519 {
 520         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 521         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 522         uint32_t mrqc, *key, i, reta, j;
 523         uint64_t hf;
 524
 525 #define RSS_KEY_SIZE 40
 526         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 527                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 528                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 529                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 530                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 531                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 532         };
 533
 534         if (dev->data->nb_rx_queues == 1 ||
 535             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 536             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 537                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 538                 return;
 539         }
 540
 541         /* random key is rss_intel_key (default) or user provided (rss_key) */
 542         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 543                 key = (uint32_t *)rss_intel_key;
 544         else
 545                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 546
 547         /* Now fill our hash function seeds, 4 bytes at a time */
 548         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 549                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 550
 551         /*
 552          * Fill in redirection table
 553          * The byte-swap is needed because NIC registers are in
 554          * little-endian order.
 555          */
 556         reta = 0;
 557         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 558                 if (j == dev->data->nb_rx_queues)
 559                         j = 0;
 560                 reta = (reta << CHAR_BIT) | j;
 561                 if ((i & 3) == 3)
 562                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 563                                         rte_bswap32(reta));
 564         }
 565
 566         /*
 567          * Generate RSS hash based on packet types, TCP/UDP
 568          * port numbers and/or IPv4/v6 src and dst addresses
 569          */
 570         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 571         mrqc = 0;
 572         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 573         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 577         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 580         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 581
 582         if (mrqc == 0) {
 583                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 584                         "supported", hf);
 585                 return;
 586         }
 587
 588         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 589 }
 590
 591 static void
 592 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 593 {
 594         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 595         uint32_t i;
 596
 597         for (i = 0; i < nb_lport_new; i++) {
 598                 /* Set unicast mode by default. App can change
 599                  * to other mode in other API func.
 600                  */
 601                 fm10k_mbx_lock(hw);
 602                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 603                         FM10K_XCAST_MODE_NONE);
 604                 fm10k_mbx_unlock(hw);
 605         }
 606 }
 607
 608 static void
 609 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 610 {
 611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 613         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 614         struct fm10k_macvlan_filter_info *macvlan;
 615         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 616         uint16_t nb_lport_new;
 617
 618         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 619         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 620
 621         fm10k_dev_rss_configure(dev);
 622
 623         /* only PF supports VMDQ */
 624         if (hw->mac.type != fm10k_mac_pf)
 625                 return;
 626
 627         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 628                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 629
 630         /* no pool number change, no need to update logic port and VLAN/MAC */
 631         if (macvlan->nb_queue_pools == nb_queue_pools)
 632                 return;
 633
 634         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 635         fm10k_dev_logic_port_update(dev, nb_lport_new);
 636
 637         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 638         memset(dev->data->mac_addrs, 0,
 639                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 640         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 641                 &dev->data->mac_addrs[0]);
 642         memset(macvlan, 0, sizeof(*macvlan));
 643         macvlan->nb_queue_pools = nb_queue_pools;
 644
 645         if (nb_queue_pools)
 646                 fm10k_dev_vmdq_rx_configure(dev);
 647         else
 648                 fm10k_dev_pf_main_vsi_reset(dev);
 649 }
 650
 651 static int
 652 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 653 {
 654         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         int i, ret;
 656         struct fm10k_tx_queue *txq;
 657         uint64_t base_addr;
 658         uint32_t size;
 659
 660         /* Disable TXINT to avoid possible interrupt */
 661         for (i = 0; i < hw->mac.max_queues; i++)
 662                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 663                                 3 << FM10K_TXINT_TIMER_SHIFT);
 664
 665         /* Setup TX queue */
 666         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 667                 txq = dev->data->tx_queues[i];
 668                 base_addr = txq->hw_ring_phys_addr;
 669                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 670
 671                 /* disable queue to avoid issues while updating state */
 672                 ret = tx_queue_disable(hw, i);
 673                 if (ret) {
 674                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 675                         return -1;
 676                 }
 677                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 678                  * register is read-only for VF.
 679                  */
 680                 if (fm10k_check_ftag(dev->pci_dev->device.devargs)) {
 681                         if (hw->mac.type == fm10k_mac_pf) {
 682                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 683                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 684                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 685                         } else {
 686                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 687                                 return -ENOTSUP;
 688                         }
 689                 }
 690
 691                 /* set location and size for descriptor ring */
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 693                                 base_addr & UINT64_LOWER_32BITS_MASK);
 694                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 695                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 696                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 697
 698                 /* assign default SGLORT for each TX queue by PF */
 699                 if (hw->mac.type == fm10k_mac_pf)
 700                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 701         }
 702
 703         /* set up vector or scalar TX function as appropriate */
 704         fm10k_set_tx_function(dev);
 705
 706         return 0;
 707 }
 708
 709 static int
 710 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 711 {
 712         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct fm10k_macvlan_filter_info *macvlan;
 714         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 715         int i, ret;
 716         struct fm10k_rx_queue *rxq;
 717         uint64_t base_addr;
 718         uint32_t size;
 719         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 720         uint32_t logic_port = hw->mac.dglort_map;
 721         uint16_t buf_size;
 722         uint16_t queue_stride = 0;
 723
 724         /* enable RXINT for interrupt mode */
 725         i = 0;
 726         if (rte_intr_dp_is_en(intr_handle)) {
 727                 for (; i < dev->data->nb_rx_queues; i++) {
 728                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 729                         if (hw->mac.type == fm10k_mac_pf)
 730                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 731                                         FM10K_ITR_AUTOMASK |
 732                                         FM10K_ITR_MASK_CLEAR);
 733                         else
 734                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 735                                         FM10K_ITR_AUTOMASK |
 736                                         FM10K_ITR_MASK_CLEAR);
 737                 }
 738         }
 739         /* Disable other RXINT to avoid possible interrupt */
 740         for (; i < hw->mac.max_queues; i++)
 741                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 742                         3 << FM10K_RXINT_TIMER_SHIFT);
 743
 744         /* Setup RX queues */
 745         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 746                 rxq = dev->data->rx_queues[i];
 747                 base_addr = rxq->hw_ring_phys_addr;
 748                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 749
 750                 /* disable queue to avoid issues while updating state */
 751                 ret = rx_queue_disable(hw, i);
 752                 if (ret) {
 753                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 754                         return -1;
 755                 }
 756
 757                 /* Setup the Base and Length of the Rx Descriptor Ring */
 758                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 759                                 base_addr & UINT64_LOWER_32BITS_MASK);
 760                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 761                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 762                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 763
 764                 /* Configure the Rx buffer size for one buff without split */
 765                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 766                         RTE_PKTMBUF_HEADROOM);
 767                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 768                  * reserved for this purpose, and the worst case could be 511B.
 769                  * But SRR reg assumes all buffers have the same size. In order
 770                  * to fill the gap, we'll have to consider the worst case and
 771                  * assume 512B is reserved. If we don't do so, it's possible
 772                  * for HW to overwrite data to next mbuf.
 773                  */
 774                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 775
 776                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 777                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 778                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 779
 780                 /* It adds dual VLAN length for supporting dual VLAN */
 781                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 782                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 783                         dev->data->dev_conf.rxmode.enable_scatter) {
 784                         uint32_t reg;
 785                         dev->data->scattered_rx = 1;
 786                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 787                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 788                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 789                 }
 790
 791                 /* Enable drop on empty, it's RO for VF */
 792                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 793                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 794
 795                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 796                 FM10K_WRITE_FLUSH(hw);
 797         }
 798
 799         /* Configure VMDQ/RSS if applicable */
 800         fm10k_dev_mq_rx_configure(dev);
 801
 802         /* Decide the best RX function */
 803         fm10k_set_rx_function(dev);
 804
 805         /* update RX_SGLORT for loopback suppress*/
 806         if (hw->mac.type != fm10k_mac_pf)
 807                 return 0;
 808         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 809         if (macvlan->nb_queue_pools)
 810                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 811         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 812                 if (i && queue_stride && !(i % queue_stride))
 813                         logic_port++;
 814                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int
 821 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 822 {
 823         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 824         int err = -1;
 825         uint32_t reg;
 826         struct fm10k_rx_queue *rxq;
 827
 828         PMD_INIT_FUNC_TRACE();
 829
 830         if (rx_queue_id < dev->data->nb_rx_queues) {
 831                 rxq = dev->data->rx_queues[rx_queue_id];
 832                 err = rx_queue_reset(rxq);
 833                 if (err == -ENOMEM) {
 834                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 835                         return err;
 836                 } else if (err == -EINVAL) {
 837                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 838                                 " %d", err);
 839                         return err;
 840                 }
 841
 842                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 843                  * Note: this must be done AFTER the queue is enabled on real
 844                  * hardware, but BEFORE the queue is enabled when using the
 845                  * emulation platform. Do it in both places for now and remove
 846                  * this comment and the following two register writes when the
 847                  * emulation platform is no longer being used.
 848                  */
 849                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 850                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 851
 852                 /* Set PF ownership flag for PF devices */
 853                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 854                 if (hw->mac.type == fm10k_mac_pf)
 855                         reg |= FM10K_RXQCTL_PF;
 856                 reg |= FM10K_RXQCTL_ENABLE;
 857                 /* enable RX queue */
 858                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 859                 FM10K_WRITE_FLUSH(hw);
 860
 861                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 862                  * Note: this must be done AFTER the queue is enabled
 863                  */
 864                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 865                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 866                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 867         }
 868
 869         return err;
 870 }
 871
 872 static int
 873 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 874 {
 875         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 876
 877         PMD_INIT_FUNC_TRACE();
 878
 879         if (rx_queue_id < dev->data->nb_rx_queues) {
 880                 /* Disable RX queue */
 881                 rx_queue_disable(hw, rx_queue_id);
 882
 883                 /* Free mbuf and clean HW ring */
 884                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 885                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int
 892 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 893 {
 894         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 895         /** @todo - this should be defined in the shared code */
 896 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 897         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 898         int err = 0;
 899
 900         PMD_INIT_FUNC_TRACE();
 901
 902         if (tx_queue_id < dev->data->nb_tx_queues) {
 903                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 904
 905                 q->ops->reset(q);
 906
 907                 /* reset head and tail pointers */
 908                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 909                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 910
 911                 /* enable TX queue */
 912                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 913                                         FM10K_TXDCTL_ENABLE | txdctl);
 914                 FM10K_WRITE_FLUSH(hw);
 915                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 916         } else
 917                 err = -1;
 918
 919         return err;
 920 }
 921
 922 static int
 923 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 924 {
 925         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         if (tx_queue_id < dev->data->nb_tx_queues) {
 930                 tx_queue_disable(hw, tx_queue_id);
 931                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 932                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 933         }
 934
 935         return 0;
 936 }
 937
 938 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 939 {
 940         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 941                 != FM10K_DGLORTMAP_NONE);
 942 }
 943
 944 static void
 945 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 946 {
 947         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 948         int status;
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         /* Return if it didn't acquire valid glort range */
 953         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 954                 return;
 955
 956         fm10k_mbx_lock(hw);
 957         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 958                                 FM10K_XCAST_MODE_PROMISC);
 959         fm10k_mbx_unlock(hw);
 960
 961         if (status != FM10K_SUCCESS)
 962                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 963 }
 964
 965 static void
 966 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 967 {
 968         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 969         uint8_t mode;
 970         int status;
 971
 972         PMD_INIT_FUNC_TRACE();
 973
 974         /* Return if it didn't acquire valid glort range */
 975         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 976                 return;
 977
 978         if (dev->data->all_multicast == 1)
 979                 mode = FM10K_XCAST_MODE_ALLMULTI;
 980         else
 981                 mode = FM10K_XCAST_MODE_NONE;
 982
 983         fm10k_mbx_lock(hw);
 984         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 985                                 mode);
 986         fm10k_mbx_unlock(hw);
 987
 988         if (status != FM10K_SUCCESS)
 989                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 990 }
 991
 992 static void
 993 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 994 {
 995         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 996         int status;
 997
 998         PMD_INIT_FUNC_TRACE();
 999
1000         /* Return if it didn't acquire valid glort range */
1001         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1002                 return;
1003
1004         /* If promiscuous mode is enabled, it doesn't make sense to enable
1005          * allmulticast and disable promiscuous since fm10k only can select
1006          * one of the modes.
1007          */
1008         if (dev->data->promiscuous) {
1009                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1010                         "needn't enable allmulticast");
1011                 return;
1012         }
1013
1014         fm10k_mbx_lock(hw);
1015         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1016                                 FM10K_XCAST_MODE_ALLMULTI);
1017         fm10k_mbx_unlock(hw);
1018
1019         if (status != FM10K_SUCCESS)
1020                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1021 }
1022
1023 static void
1024 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1025 {
1026         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         int status;
1028
1029         PMD_INIT_FUNC_TRACE();
1030
1031         /* Return if it didn't acquire valid glort range */
1032         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1033                 return;
1034
1035         if (dev->data->promiscuous) {
1036                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1037                         "since promisc mode is enabled");
1038                 return;
1039         }
1040
1041         fm10k_mbx_lock(hw);
1042         /* Change mode to unicast mode */
1043         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1044                                 FM10K_XCAST_MODE_NONE);
1045         fm10k_mbx_unlock(hw);
1046
1047         if (status != FM10K_SUCCESS)
1048                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1049 }
1050
1051 static void
1052 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1053 {
1054         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1056         uint16_t nb_queue_pools;
1057         struct fm10k_macvlan_filter_info *macvlan;
1058
1059         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1060         nb_queue_pools = macvlan->nb_queue_pools;
1061         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1062         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1063
1064         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1065         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1066         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1067                         hw->mac.dglort_map;
1068         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1069         /* Configure VMDQ/RSS DGlort Decoder */
1070         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1071
1072         /* Flow Director configurations, only queue number is valid. */
1073         dglortdec = fls(dev->data->nb_rx_queues - 1);
1074         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1075                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1076         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1077         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1078
1079         /* Invalidate all other GLORT entries */
1080         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1081                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1082                                 FM10K_DGLORTMAP_NONE);
1083 }
1084
1085 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1086 static int
1087 fm10k_dev_start(struct rte_eth_dev *dev)
1088 {
1089         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090         int i, diag;
1091
1092         PMD_INIT_FUNC_TRACE();
1093
1094         /* stop, init, then start the hw */
1095         diag = fm10k_stop_hw(hw);
1096         if (diag != FM10K_SUCCESS) {
1097                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1098                 return -EIO;
1099         }
1100
1101         diag = fm10k_init_hw(hw);
1102         if (diag != FM10K_SUCCESS) {
1103                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1104                 return -EIO;
1105         }
1106
1107         diag = fm10k_start_hw(hw);
1108         if (diag != FM10K_SUCCESS) {
1109                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1110                 return -EIO;
1111         }
1112
1113         diag = fm10k_dev_tx_init(dev);
1114         if (diag) {
1115                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1116                 return diag;
1117         }
1118
1119         if (fm10k_dev_rxq_interrupt_setup(dev))
1120                 return -EIO;
1121
1122         diag = fm10k_dev_rx_init(dev);
1123         if (diag) {
1124                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1125                 return diag;
1126         }
1127
1128         if (hw->mac.type == fm10k_mac_pf)
1129                 fm10k_dev_dglort_map_configure(dev);
1130
1131         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1132                 struct fm10k_rx_queue *rxq;
1133                 rxq = dev->data->rx_queues[i];
1134
1135                 if (rxq->rx_deferred_start)
1136                         continue;
1137                 diag = fm10k_dev_rx_queue_start(dev, i);
1138                 if (diag != 0) {
1139                         int j;
1140                         for (j = 0; j < i; ++j)
1141                                 rx_queue_clean(dev->data->rx_queues[j]);
1142                         return diag;
1143                 }
1144         }
1145
1146         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1147                 struct fm10k_tx_queue *txq;
1148                 txq = dev->data->tx_queues[i];
1149
1150                 if (txq->tx_deferred_start)
1151                         continue;
1152                 diag = fm10k_dev_tx_queue_start(dev, i);
1153                 if (diag != 0) {
1154                         int j;
1155                         for (j = 0; j < i; ++j)
1156                                 tx_queue_clean(dev->data->tx_queues[j]);
1157                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1158                                 rx_queue_clean(dev->data->rx_queues[j]);
1159                         return diag;
1160                 }
1161         }
1162
1163         /* Update default vlan when not in VMDQ mode */
1164         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1165                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1166
1167         return 0;
1168 }
1169
1170 static void
1171 fm10k_dev_stop(struct rte_eth_dev *dev)
1172 {
1173         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1174         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175         int i;
1176
1177         PMD_INIT_FUNC_TRACE();
1178
1179         if (dev->data->tx_queues)
1180                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1181                         fm10k_dev_tx_queue_stop(dev, i);
1182
1183         if (dev->data->rx_queues)
1184                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1185                         fm10k_dev_rx_queue_stop(dev, i);
1186
1187         /* Disable datapath event */
1188         if (rte_intr_dp_is_en(intr_handle)) {
1189                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1190                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1191                                 3 << FM10K_RXINT_TIMER_SHIFT);
1192                         if (hw->mac.type == fm10k_mac_pf)
1193                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1194                                         FM10K_ITR_MASK_SET);
1195                         else
1196                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1197                                         FM10K_ITR_MASK_SET);
1198                 }
1199         }
1200         /* Clean datapath event and queue/vec mapping */
1201         rte_intr_efd_disable(intr_handle);
1202         rte_free(intr_handle->intr_vec);
1203         intr_handle->intr_vec = NULL;
1204 }
1205
1206 static void
1207 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1208 {
1209         int i;
1210
1211         PMD_INIT_FUNC_TRACE();
1212
1213         if (dev->data->tx_queues) {
1214                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1215                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1216
1217                         tx_queue_free(txq);
1218                 }
1219         }
1220
1221         if (dev->data->rx_queues) {
1222                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1223                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1224         }
1225 }
1226
1227 static void
1228 fm10k_dev_close(struct rte_eth_dev *dev)
1229 {
1230         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231
1232         PMD_INIT_FUNC_TRACE();
1233
1234         fm10k_mbx_lock(hw);
1235         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1236                 MAX_LPORT_NUM, false);
1237         fm10k_mbx_unlock(hw);
1238
1239         /* allow 10ms for device to quiesce */
1240         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1241
1242         /* Stop mailbox service first */
1243         fm10k_close_mbx_service(hw);
1244         fm10k_dev_stop(dev);
1245         fm10k_dev_queue_release(dev);
1246         fm10k_stop_hw(hw);
1247 }
1248
1249 static int
1250 fm10k_link_update(struct rte_eth_dev *dev,
1251         __rte_unused int wait_to_complete)
1252 {
1253         PMD_INIT_FUNC_TRACE();
1254
1255         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1256          * x8 PCIe interface. For now, we leave the speed undefined since there
1257          * is no 50Gbps Ethernet. */
1258         dev->data->dev_link.link_speed  = 0;
1259         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1260         dev->data->dev_link.link_status = ETH_LINK_UP;
1261
1262         return 0;
1263 }
1264
1265 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1266         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1267 {
1268         unsigned i, q;
1269         unsigned count = 0;
1270
1271         if (xstats_names != NULL) {
1272                 /* Note: limit checked in rte_eth_xstats_names() */
1273
1274                 /* Global stats */
1275                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1276                         snprintf(xstats_names[count].name,
1277                                 sizeof(xstats_names[count].name),
1278                                 "%s", fm10k_hw_stats_strings[count].name);
1279                         count++;
1280                 }
1281
1282                 /* PF queue stats */
1283                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1284                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1285                                 snprintf(xstats_names[count].name,
1286                                         sizeof(xstats_names[count].name),
1287                                         "rx_q%u_%s", q,
1288                                         fm10k_hw_stats_rx_q_strings[i].name);
1289                                 count++;
1290                         }
1291                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1292                                 snprintf(xstats_names[count].name,
1293                                         sizeof(xstats_names[count].name),
1294                                         "tx_q%u_%s", q,
1295                                         fm10k_hw_stats_tx_q_strings[i].name);
1296                                 count++;
1297                         }
1298                 }
1299         }
1300         return FM10K_NB_XSTATS;
1301 }
1302
1303 static int
1304 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1305                  unsigned n)
1306 {
1307         struct fm10k_hw_stats *hw_stats =
1308                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1309         unsigned i, q, count = 0;
1310
1311         if (n < FM10K_NB_XSTATS)
1312                 return FM10K_NB_XSTATS;
1313
1314         /* Global stats */
1315         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1316                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1317                         fm10k_hw_stats_strings[count].offset);
1318                 count++;
1319         }
1320
1321         /* PF queue stats */
1322         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1323                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1324                         xstats[count].value =
1325                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1326                                 fm10k_hw_stats_rx_q_strings[i].offset);
1327                         count++;
1328                 }
1329                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1330                         xstats[count].value =
1331                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1332                                 fm10k_hw_stats_tx_q_strings[i].offset);
1333                         count++;
1334                 }
1335         }
1336
1337         return FM10K_NB_XSTATS;
1338 }
1339
1340 static void
1341 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1342 {
1343         uint64_t ipackets, opackets, ibytes, obytes;
1344         struct fm10k_hw *hw =
1345                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346         struct fm10k_hw_stats *hw_stats =
1347                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1348         int i;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         fm10k_update_hw_stats(hw, hw_stats);
1353
1354         ipackets = opackets = ibytes = obytes = 0;
1355         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1356                 (i < hw->mac.max_queues); ++i) {
1357                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1358                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1359                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1360                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1361                 ipackets += stats->q_ipackets[i];
1362                 opackets += stats->q_opackets[i];
1363                 ibytes   += stats->q_ibytes[i];
1364                 obytes   += stats->q_obytes[i];
1365         }
1366         stats->ipackets = ipackets;
1367         stats->opackets = opackets;
1368         stats->ibytes = ibytes;
1369         stats->obytes = obytes;
1370 }
1371
1372 static void
1373 fm10k_stats_reset(struct rte_eth_dev *dev)
1374 {
1375         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         struct fm10k_hw_stats *hw_stats =
1377                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         memset(hw_stats, 0, sizeof(*hw_stats));
1382         fm10k_rebind_hw_stats(hw, hw_stats);
1383 }
1384
1385 static void
1386 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1387         struct rte_eth_dev_info *dev_info)
1388 {
1389         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1394         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1395         dev_info->max_rx_queues      = hw->mac.max_queues;
1396         dev_info->max_tx_queues      = hw->mac.max_queues;
1397         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1398         dev_info->max_hash_mac_addrs = 0;
1399         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1400         dev_info->vmdq_pool_base     = 0;
1401         dev_info->vmdq_queue_base    = 0;
1402         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1403         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1404         dev_info->rx_offload_capa =
1405                 DEV_RX_OFFLOAD_VLAN_STRIP |
1406                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1407                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1408                 DEV_RX_OFFLOAD_TCP_CKSUM;
1409         dev_info->tx_offload_capa =
1410                 DEV_TX_OFFLOAD_VLAN_INSERT |
1411                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1412                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1413                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1414                 DEV_TX_OFFLOAD_TCP_TSO;
1415
1416         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1417         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1418
1419         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1420                 .rx_thresh = {
1421                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1422                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1423                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1424                 },
1425                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1426                 .rx_drop_en = 0,
1427         };
1428
1429         dev_info->default_txconf = (struct rte_eth_txconf) {
1430                 .tx_thresh = {
1431                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1432                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1433                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1434                 },
1435                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1436                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1437                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1438         };
1439
1440         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1441                 .nb_max = FM10K_MAX_RX_DESC,
1442                 .nb_min = FM10K_MIN_RX_DESC,
1443                 .nb_align = FM10K_MULT_RX_DESC,
1444         };
1445
1446         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1447                 .nb_max = FM10K_MAX_TX_DESC,
1448                 .nb_min = FM10K_MIN_TX_DESC,
1449                 .nb_align = FM10K_MULT_TX_DESC,
1450         };
1451
1452         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1453                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1454                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1455 }
1456
1457 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1458 static const uint32_t *
1459 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1460 {
1461         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1462             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1463                 static uint32_t ptypes[] = {
1464                         /* refers to rx_desc_to_ol_flags() */
1465                         RTE_PTYPE_L2_ETHER,
1466                         RTE_PTYPE_L3_IPV4,
1467                         RTE_PTYPE_L3_IPV4_EXT,
1468                         RTE_PTYPE_L3_IPV6,
1469                         RTE_PTYPE_L3_IPV6_EXT,
1470                         RTE_PTYPE_L4_TCP,
1471                         RTE_PTYPE_L4_UDP,
1472                         RTE_PTYPE_UNKNOWN
1473                 };
1474
1475                 return ptypes;
1476         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1477                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1478                 static uint32_t ptypes_vec[] = {
1479                         /* refers to fm10k_desc_to_pktype_v() */
1480                         RTE_PTYPE_L3_IPV4,
1481                         RTE_PTYPE_L3_IPV4_EXT,
1482                         RTE_PTYPE_L3_IPV6,
1483                         RTE_PTYPE_L3_IPV6_EXT,
1484                         RTE_PTYPE_L4_TCP,
1485                         RTE_PTYPE_L4_UDP,
1486                         RTE_PTYPE_TUNNEL_GENEVE,
1487                         RTE_PTYPE_TUNNEL_NVGRE,
1488                         RTE_PTYPE_TUNNEL_VXLAN,
1489                         RTE_PTYPE_TUNNEL_GRE,
1490                         RTE_PTYPE_UNKNOWN
1491                 };
1492
1493                 return ptypes_vec;
1494         }
1495
1496         return NULL;
1497 }
1498 #else
1499 static const uint32_t *
1500 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1501 {
1502         return NULL;
1503 }
1504 #endif
1505
1506 static int
1507 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1508 {
1509         s32 result;
1510         uint16_t mac_num = 0;
1511         uint32_t vid_idx, vid_bit, mac_index;
1512         struct fm10k_hw *hw;
1513         struct fm10k_macvlan_filter_info *macvlan;
1514         struct rte_eth_dev_data *data = dev->data;
1515
1516         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1518
1519         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1520                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1521                 return -EINVAL;
1522         }
1523
1524         if (vlan_id > ETH_VLAN_ID_MAX) {
1525                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1526                 return -EINVAL;
1527         }
1528
1529         vid_idx = FM10K_VFTA_IDX(vlan_id);
1530         vid_bit = FM10K_VFTA_BIT(vlan_id);
1531         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1532         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1533                 return 0;
1534         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1535         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1536                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1537                         "in the VLAN filter table");
1538                 return -EINVAL;
1539         }
1540
1541         fm10k_mbx_lock(hw);
1542         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1543         fm10k_mbx_unlock(hw);
1544         if (result != FM10K_SUCCESS) {
1545                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1546                 return -EIO;
1547         }
1548
1549         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1550                         (result == FM10K_SUCCESS); mac_index++) {
1551                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1552                         continue;
1553                 if (mac_num > macvlan->mac_num - 1) {
1554                         PMD_INIT_LOG(ERR, "MAC address number "
1555                                         "not match");
1556                         break;
1557                 }
1558                 fm10k_mbx_lock(hw);
1559                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1560                         data->mac_addrs[mac_index].addr_bytes,
1561                         vlan_id, on, 0);
1562                 fm10k_mbx_unlock(hw);
1563                 mac_num++;
1564         }
1565         if (result != FM10K_SUCCESS) {
1566                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1567                 return -EIO;
1568         }
1569
1570         if (on) {
1571                 macvlan->vlan_num++;
1572                 macvlan->vfta[vid_idx] |= vid_bit;
1573         } else {
1574                 macvlan->vlan_num--;
1575                 macvlan->vfta[vid_idx] &= ~vid_bit;
1576         }
1577         return 0;
1578 }
1579
1580 static void
1581 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1582 {
1583         if (mask & ETH_VLAN_STRIP_MASK) {
1584                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1585                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1586                                         "always on in fm10k");
1587         }
1588
1589         if (mask & ETH_VLAN_EXTEND_MASK) {
1590                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1591                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1592                                         "supported in fm10k");
1593         }
1594
1595         if (mask & ETH_VLAN_FILTER_MASK) {
1596                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1597                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1598         }
1599 }
1600
1601 /* Add/Remove a MAC address, and update filters to main VSI */
1602 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1603                 const u8 *mac, bool add, uint32_t pool)
1604 {
1605         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         struct fm10k_macvlan_filter_info *macvlan;
1607         uint32_t i, j, k;
1608
1609         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1610
1611         if (pool != MAIN_VSI_POOL_NUMBER) {
1612                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1613                         "mac to pool %u", pool);
1614                 return;
1615         }
1616         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1617                 if (!macvlan->vfta[j])
1618                         continue;
1619                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1620                         if (!(macvlan->vfta[j] & (1 << k)))
1621                                 continue;
1622                         if (i + 1 > macvlan->vlan_num) {
1623                                 PMD_INIT_LOG(ERR, "vlan number not match");
1624                                 return;
1625                         }
1626                         fm10k_mbx_lock(hw);
1627                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1628                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1629                         fm10k_mbx_unlock(hw);
1630                         i++;
1631                 }
1632         }
1633 }
1634
1635 /* Add/Remove a MAC address, and update filters to VMDQ */
1636 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1637                 const u8 *mac, bool add, uint32_t pool)
1638 {
1639         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct fm10k_macvlan_filter_info *macvlan;
1641         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1642         uint32_t i;
1643
1644         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1645         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1646
1647         if (pool > macvlan->nb_queue_pools) {
1648                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1649                         " Max pool is %u",
1650                         pool, macvlan->nb_queue_pools);
1651                 return;
1652         }
1653         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1654                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1655                         continue;
1656                 fm10k_mbx_lock(hw);
1657                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1658                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1659                 fm10k_mbx_unlock(hw);
1660         }
1661 }
1662
1663 /* Add/Remove a MAC address, and update filters */
1664 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1665                 const u8 *mac, bool add, uint32_t pool)
1666 {
1667         struct fm10k_macvlan_filter_info *macvlan;
1668
1669         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1670
1671         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1672                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1673         else
1674                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1675
1676         if (add)
1677                 macvlan->mac_num++;
1678         else
1679                 macvlan->mac_num--;
1680 }
1681
1682 /* Add a MAC address, and update filters */
1683 static void
1684 fm10k_macaddr_add(struct rte_eth_dev *dev,
1685                 struct ether_addr *mac_addr,
1686                 uint32_t index,
1687                 uint32_t pool)
1688 {
1689         struct fm10k_macvlan_filter_info *macvlan;
1690
1691         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1692         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1693         macvlan->mac_vmdq_id[index] = pool;
1694 }
1695
1696 /* Remove a MAC address, and update filters */
1697 static void
1698 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1699 {
1700         struct rte_eth_dev_data *data = dev->data;
1701         struct fm10k_macvlan_filter_info *macvlan;
1702
1703         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1704         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1705                         FALSE, macvlan->mac_vmdq_id[index]);
1706         macvlan->mac_vmdq_id[index] = 0;
1707 }
1708
1709 static inline int
1710 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1711 {
1712         if ((request < min) || (request > max) || ((request % mult) != 0))
1713                 return -1;
1714         else
1715                 return 0;
1716 }
1717
1718
1719 static inline int
1720 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1721 {
1722         if ((request < min) || (request > max) || ((div % request) != 0))
1723                 return -1;
1724         else
1725                 return 0;
1726 }
1727
1728 static inline int
1729 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1730 {
1731         uint16_t rx_free_thresh;
1732
1733         if (conf->rx_free_thresh == 0)
1734                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1735         else
1736                 rx_free_thresh = conf->rx_free_thresh;
1737
1738         /* make sure the requested threshold satisfies the constraints */
1739         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1740                         FM10K_RX_FREE_THRESH_MAX(q),
1741                         FM10K_RX_FREE_THRESH_DIV(q),
1742                         rx_free_thresh)) {
1743                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1744                         "less than or equal to %u, "
1745                         "greater than or equal to %u, "
1746                         "and a divisor of %u",
1747                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1748                         FM10K_RX_FREE_THRESH_MIN(q),
1749                         FM10K_RX_FREE_THRESH_DIV(q));
1750                 return -EINVAL;
1751         }
1752
1753         q->alloc_thresh = rx_free_thresh;
1754         q->drop_en = conf->rx_drop_en;
1755         q->rx_deferred_start = conf->rx_deferred_start;
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Hardware requires specific alignment for Rx packet buffers. At
1762  * least one of the following two conditions must be satisfied.
1763  *  1. Address is 512B aligned
1764  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1765  *
1766  * As such, the driver may need to adjust the DMA address within the
1767  * buffer by up to 512B.
1768  *
1769  * return 1 if the element size is valid, otherwise return 0.
1770  */
1771 static int
1772 mempool_element_size_valid(struct rte_mempool *mp)
1773 {
1774         uint32_t min_size;
1775
1776         /* elt_size includes mbuf header and headroom */
1777         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1778                         RTE_PKTMBUF_HEADROOM;
1779
1780         /* account for up to 512B of alignment */
1781         min_size -= FM10K_RX_DATABUF_ALIGN;
1782
1783         /* sanity check for overflow */
1784         if (min_size > mp->elt_size)
1785                 return 0;
1786
1787         /* size is valid */
1788         return 1;
1789 }
1790
1791 static int
1792 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1793         uint16_t nb_desc, unsigned int socket_id,
1794         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1795 {
1796         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1798         struct fm10k_rx_queue *q;
1799         const struct rte_memzone *mz;
1800
1801         PMD_INIT_FUNC_TRACE();
1802
1803         /* make sure the mempool element size can account for alignment. */
1804         if (!mempool_element_size_valid(mp)) {
1805                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1806                 return -EINVAL;
1807         }
1808
1809         /* make sure a valid number of descriptors have been requested */
1810         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1811                                 FM10K_MULT_RX_DESC, nb_desc)) {
1812                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1813                         "less than or equal to %"PRIu32", "
1814                         "greater than or equal to %u, "
1815                         "and a multiple of %u",
1816                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1817                         FM10K_MULT_RX_DESC);
1818                 return -EINVAL;
1819         }
1820
1821         /*
1822          * if this queue existed already, free the associated memory. The
1823          * queue cannot be reused in case we need to allocate memory on
1824          * different socket than was previously used.
1825          */
1826         if (dev->data->rx_queues[queue_id] != NULL) {
1827                 rx_queue_free(dev->data->rx_queues[queue_id]);
1828                 dev->data->rx_queues[queue_id] = NULL;
1829         }
1830
1831         /* allocate memory for the queue structure */
1832         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1833                                 socket_id);
1834         if (q == NULL) {
1835                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1836                 return -ENOMEM;
1837         }
1838
1839         /* setup queue */
1840         q->mp = mp;
1841         q->nb_desc = nb_desc;
1842         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1843         q->port_id = dev->data->port_id;
1844         q->queue_id = queue_id;
1845         q->tail_ptr = (volatile uint32_t *)
1846                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1847         if (handle_rxconf(q, conf))
1848                 return -EINVAL;
1849
1850         /* allocate memory for the software ring */
1851         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1852                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1853                         RTE_CACHE_LINE_SIZE, socket_id);
1854         if (q->sw_ring == NULL) {
1855                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1856                 rte_free(q);
1857                 return -ENOMEM;
1858         }
1859
1860         /*
1861          * allocate memory for the hardware descriptor ring. A memzone large
1862          * enough to hold the maximum ring size is requested to allow for
1863          * resizing in later calls to the queue setup function.
1864          */
1865         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1866                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1867                                       socket_id);
1868         if (mz == NULL) {
1869                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1870                 rte_free(q->sw_ring);
1871                 rte_free(q);
1872                 return -ENOMEM;
1873         }
1874         q->hw_ring = mz->addr;
1875         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1876
1877         /* Check if number of descs satisfied Vector requirement */
1878         if (!rte_is_power_of_2(nb_desc)) {
1879                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1880                                     "preconditions - canceling the feature for "
1881                                     "the whole port[%d]",
1882                              q->queue_id, q->port_id);
1883                 dev_info->rx_vec_allowed = false;
1884         } else
1885                 fm10k_rxq_vec_setup(q);
1886
1887         dev->data->rx_queues[queue_id] = q;
1888         return 0;
1889 }
1890
1891 static void
1892 fm10k_rx_queue_release(void *queue)
1893 {
1894         PMD_INIT_FUNC_TRACE();
1895
1896         rx_queue_free(queue);
1897 }
1898
1899 static inline int
1900 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1901 {
1902         uint16_t tx_free_thresh;
1903         uint16_t tx_rs_thresh;
1904
1905         /* constraint MACROs require that tx_free_thresh is configured
1906          * before tx_rs_thresh */
1907         if (conf->tx_free_thresh == 0)
1908                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1909         else
1910                 tx_free_thresh = conf->tx_free_thresh;
1911
1912         /* make sure the requested threshold satisfies the constraints */
1913         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1914                         FM10K_TX_FREE_THRESH_MAX(q),
1915                         FM10K_TX_FREE_THRESH_DIV(q),
1916                         tx_free_thresh)) {
1917                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1918                         "less than or equal to %u, "
1919                         "greater than or equal to %u, "
1920                         "and a divisor of %u",
1921                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1922                         FM10K_TX_FREE_THRESH_MIN(q),
1923                         FM10K_TX_FREE_THRESH_DIV(q));
1924                 return -EINVAL;
1925         }
1926
1927         q->free_thresh = tx_free_thresh;
1928
1929         if (conf->tx_rs_thresh == 0)
1930                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1931         else
1932                 tx_rs_thresh = conf->tx_rs_thresh;
1933
1934         q->tx_deferred_start = conf->tx_deferred_start;
1935
1936         /* make sure the requested threshold satisfies the constraints */
1937         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1938                         FM10K_TX_RS_THRESH_MAX(q),
1939                         FM10K_TX_RS_THRESH_DIV(q),
1940                         tx_rs_thresh)) {
1941                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1942                         "less than or equal to %u, "
1943                         "greater than or equal to %u, "
1944                         "and a divisor of %u",
1945                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1946                         FM10K_TX_RS_THRESH_MIN(q),
1947                         FM10K_TX_RS_THRESH_DIV(q));
1948                 return -EINVAL;
1949         }
1950
1951         q->rs_thresh = tx_rs_thresh;
1952
1953         return 0;
1954 }
1955
1956 static int
1957 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1958         uint16_t nb_desc, unsigned int socket_id,
1959         const struct rte_eth_txconf *conf)
1960 {
1961         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct fm10k_tx_queue *q;
1963         const struct rte_memzone *mz;
1964
1965         PMD_INIT_FUNC_TRACE();
1966
1967         /* make sure a valid number of descriptors have been requested */
1968         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1969                                 FM10K_MULT_TX_DESC, nb_desc)) {
1970                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1971                         "less than or equal to %"PRIu32", "
1972                         "greater than or equal to %u, "
1973                         "and a multiple of %u",
1974                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1975                         FM10K_MULT_TX_DESC);
1976                 return -EINVAL;
1977         }
1978
1979         /*
1980          * if this queue existed already, free the associated memory. The
1981          * queue cannot be reused in case we need to allocate memory on
1982          * different socket than was previously used.
1983          */
1984         if (dev->data->tx_queues[queue_id] != NULL) {
1985                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1986
1987                 tx_queue_free(txq);
1988                 dev->data->tx_queues[queue_id] = NULL;
1989         }
1990
1991         /* allocate memory for the queue structure */
1992         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1993                                 socket_id);
1994         if (q == NULL) {
1995                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1996                 return -ENOMEM;
1997         }
1998
1999         /* setup queue */
2000         q->nb_desc = nb_desc;
2001         q->port_id = dev->data->port_id;
2002         q->queue_id = queue_id;
2003         q->txq_flags = conf->txq_flags;
2004         q->ops = &def_txq_ops;
2005         q->tail_ptr = (volatile uint32_t *)
2006                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2007         if (handle_txconf(q, conf))
2008                 return -EINVAL;
2009
2010         /* allocate memory for the software ring */
2011         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2012                                         nb_desc * sizeof(struct rte_mbuf *),
2013                                         RTE_CACHE_LINE_SIZE, socket_id);
2014         if (q->sw_ring == NULL) {
2015                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2016                 rte_free(q);
2017                 return -ENOMEM;
2018         }
2019
2020         /*
2021          * allocate memory for the hardware descriptor ring. A memzone large
2022          * enough to hold the maximum ring size is requested to allow for
2023          * resizing in later calls to the queue setup function.
2024          */
2025         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2026                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2027                                       socket_id);
2028         if (mz == NULL) {
2029                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2030                 rte_free(q->sw_ring);
2031                 rte_free(q);
2032                 return -ENOMEM;
2033         }
2034         q->hw_ring = mz->addr;
2035         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2036
2037         /*
2038          * allocate memory for the RS bit tracker. Enough slots to hold the
2039          * descriptor index for each RS bit needing to be set are required.
2040          */
2041         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2042                                 ((nb_desc + 1) / q->rs_thresh) *
2043                                 sizeof(uint16_t),
2044                                 RTE_CACHE_LINE_SIZE, socket_id);
2045         if (q->rs_tracker.list == NULL) {
2046                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2047                 rte_free(q->sw_ring);
2048                 rte_free(q);
2049                 return -ENOMEM;
2050         }
2051
2052         dev->data->tx_queues[queue_id] = q;
2053         return 0;
2054 }
2055
2056 static void
2057 fm10k_tx_queue_release(void *queue)
2058 {
2059         struct fm10k_tx_queue *q = queue;
2060         PMD_INIT_FUNC_TRACE();
2061
2062         tx_queue_free(q);
2063 }
2064
2065 static int
2066 fm10k_reta_update(struct rte_eth_dev *dev,
2067                         struct rte_eth_rss_reta_entry64 *reta_conf,
2068                         uint16_t reta_size)
2069 {
2070         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         uint16_t i, j, idx, shift;
2072         uint8_t mask;
2073         uint32_t reta;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         if (reta_size > FM10K_MAX_RSS_INDICES) {
2078                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2079                         "(%d) doesn't match the number hardware can supported "
2080                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2081                 return -EINVAL;
2082         }
2083
2084         /*
2085          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2086          * 128-entries in 32 registers
2087          */
2088         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2089                 idx = i / RTE_RETA_GROUP_SIZE;
2090                 shift = i % RTE_RETA_GROUP_SIZE;
2091                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2092                                 BIT_MASK_PER_UINT32);
2093                 if (mask == 0)
2094                         continue;
2095
2096                 reta = 0;
2097                 if (mask != BIT_MASK_PER_UINT32)
2098                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2099
2100                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2101                         if (mask & (0x1 << j)) {
2102                                 if (mask != 0xF)
2103                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2104                                 reta |= reta_conf[idx].reta[shift + j] <<
2105                                                 (CHAR_BIT * j);
2106                         }
2107                 }
2108                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int
2115 fm10k_reta_query(struct rte_eth_dev *dev,
2116                         struct rte_eth_rss_reta_entry64 *reta_conf,
2117                         uint16_t reta_size)
2118 {
2119         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         uint16_t i, j, idx, shift;
2121         uint8_t mask;
2122         uint32_t reta;
2123
2124         PMD_INIT_FUNC_TRACE();
2125
2126         if (reta_size < FM10K_MAX_RSS_INDICES) {
2127                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2128                         "(%d) doesn't match the number hardware can supported "
2129                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2130                 return -EINVAL;
2131         }
2132
2133         /*
2134          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2135          * 128-entries in 32 registers
2136          */
2137         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2138                 idx = i / RTE_RETA_GROUP_SIZE;
2139                 shift = i % RTE_RETA_GROUP_SIZE;
2140                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2141                                 BIT_MASK_PER_UINT32);
2142                 if (mask == 0)
2143                         continue;
2144
2145                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2146                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2147                         if (mask & (0x1 << j))
2148                                 reta_conf[idx].reta[shift + j] = ((reta >>
2149                                         CHAR_BIT * j) & UINT8_MAX);
2150                 }
2151         }
2152
2153         return 0;
2154 }
2155
2156 static int
2157 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2158         struct rte_eth_rss_conf *rss_conf)
2159 {
2160         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2162         uint32_t mrqc;
2163         uint64_t hf = rss_conf->rss_hf;
2164         int i;
2165
2166         PMD_INIT_FUNC_TRACE();
2167
2168         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2169                                 FM10K_RSSRK_ENTRIES_PER_REG))
2170                 return -EINVAL;
2171
2172         if (hf == 0)
2173                 return -EINVAL;
2174
2175         mrqc = 0;
2176         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2177         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2178         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2179         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2180         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2181         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2182         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2183         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2185
2186         /* If the mapping doesn't fit any supported, return */
2187         if (mrqc == 0)
2188                 return -EINVAL;
2189
2190         if (key != NULL)
2191                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2192                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2193
2194         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2195
2196         return 0;
2197 }
2198
2199 static int
2200 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2201         struct rte_eth_rss_conf *rss_conf)
2202 {
2203         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2205         uint32_t mrqc;
2206         uint64_t hf;
2207         int i;
2208
2209         PMD_INIT_FUNC_TRACE();
2210
2211         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2212                                 FM10K_RSSRK_ENTRIES_PER_REG))
2213                 return -EINVAL;
2214
2215         if (key != NULL)
2216                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2217                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2218
2219         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2220         hf = 0;
2221         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2222         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2223         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2224         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2225         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2226         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2227         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2228         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2229         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2230
2231         rss_conf->rss_hf = hf;
2232
2233         return 0;
2234 }
2235
2236 static void
2237 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2238 {
2239         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2241
2242         /* Bind all local non-queue interrupt to vector 0 */
2243         int_map |= FM10K_MISC_VEC_ID;
2244
2245         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2246         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2247         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2248         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2249         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2250         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2251
2252         /* Enable misc causes */
2253         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2254                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2255                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2256                                 FM10K_EIMR_ENABLE(MAILBOX) |
2257                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2258                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2259                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2260                                 FM10K_EIMR_ENABLE(VFLR));
2261
2262         /* Enable ITR 0 */
2263         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2264                                         FM10K_ITR_MASK_CLEAR);
2265         FM10K_WRITE_FLUSH(hw);
2266 }
2267
2268 static void
2269 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2270 {
2271         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2273
2274         int_map |= FM10K_MISC_VEC_ID;
2275
2276         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2277         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2278         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2279         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2280         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2281         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2282
2283         /* Disable misc causes */
2284         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2285                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2286                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2287                                 FM10K_EIMR_DISABLE(MAILBOX) |
2288                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2289                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2290                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2291                                 FM10K_EIMR_DISABLE(VFLR));
2292
2293         /* Disable ITR 0 */
2294         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2295         FM10K_WRITE_FLUSH(hw);
2296 }
2297
2298 static void
2299 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2300 {
2301         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2303
2304         /* Bind all local non-queue interrupt to vector 0 */
2305         int_map |= FM10K_MISC_VEC_ID;
2306
2307         /* Only INT 0 available, other 15 are reserved. */
2308         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2309
2310         /* Enable ITR 0 */
2311         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2312                                         FM10K_ITR_MASK_CLEAR);
2313         FM10K_WRITE_FLUSH(hw);
2314 }
2315
2316 static void
2317 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2318 {
2319         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2321
2322         int_map |= FM10K_MISC_VEC_ID;
2323
2324         /* Only INT 0 available, other 15 are reserved. */
2325         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2326
2327         /* Disable ITR 0 */
2328         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2329         FM10K_WRITE_FLUSH(hw);
2330 }
2331
2332 static int
2333 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2334 {
2335         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336
2337         /* Enable ITR */
2338         if (hw->mac.type == fm10k_mac_pf)
2339                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2340                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2341         else
2342                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2343                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2344         rte_intr_enable(&dev->pci_dev->intr_handle);
2345         return 0;
2346 }
2347
2348 static int
2349 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2350 {
2351         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352
2353         /* Disable ITR */
2354         if (hw->mac.type == fm10k_mac_pf)
2355                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2356                         FM10K_ITR_MASK_SET);
2357         else
2358                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2359                         FM10K_ITR_MASK_SET);
2360         return 0;
2361 }
2362
2363 static int
2364 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2365 {
2366         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2368         uint32_t intr_vector, vec;
2369         uint16_t queue_id;
2370         int result = 0;
2371
2372         /* fm10k needs one separate interrupt for mailbox,
2373          * so only drivers which support multiple interrupt vectors
2374          * e.g. vfio-pci can work for fm10k interrupt mode
2375          */
2376         if (!rte_intr_cap_multiple(intr_handle) ||
2377                         dev->data->dev_conf.intr_conf.rxq == 0)
2378                 return result;
2379
2380         intr_vector = dev->data->nb_rx_queues;
2381
2382         /* disable interrupt first */
2383         rte_intr_disable(&dev->pci_dev->intr_handle);
2384         if (hw->mac.type == fm10k_mac_pf)
2385                 fm10k_dev_disable_intr_pf(dev);
2386         else
2387                 fm10k_dev_disable_intr_vf(dev);
2388
2389         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2390                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2391                 result = -EIO;
2392         }
2393
2394         if (rte_intr_dp_is_en(intr_handle) && !result) {
2395                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2396                         dev->data->nb_rx_queues * sizeof(int), 0);
2397                 if (intr_handle->intr_vec) {
2398                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2399                                         queue_id < dev->data->nb_rx_queues;
2400                                         queue_id++) {
2401                                 intr_handle->intr_vec[queue_id] = vec;
2402                                 if (vec < intr_handle->nb_efd - 1
2403                                                 + FM10K_RX_VEC_START)
2404                                         vec++;
2405                         }
2406                 } else {
2407                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2408                                 " intr_vec", dev->data->nb_rx_queues);
2409                         rte_intr_efd_disable(intr_handle);
2410                         result = -ENOMEM;
2411                 }
2412         }
2413
2414         if (hw->mac.type == fm10k_mac_pf)
2415                 fm10k_dev_enable_intr_pf(dev);
2416         else
2417                 fm10k_dev_enable_intr_vf(dev);
2418         rte_intr_enable(&dev->pci_dev->intr_handle);
2419         hw->mac.ops.update_int_moderator(hw);
2420         return result;
2421 }
2422
2423 static int
2424 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2425 {
2426         struct fm10k_fault fault;
2427         int err;
2428         const char *estr = "Unknown error";
2429
2430         /* Process PCA fault */
2431         if (eicr & FM10K_EICR_PCA_FAULT) {
2432                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2433                 if (err)
2434                         goto error;
2435                 switch (fault.type) {
2436                 case PCA_NO_FAULT:
2437                         estr = "PCA_NO_FAULT"; break;
2438                 case PCA_UNMAPPED_ADDR:
2439                         estr = "PCA_UNMAPPED_ADDR"; break;
2440                 case PCA_BAD_QACCESS_PF:
2441                         estr = "PCA_BAD_QACCESS_PF"; break;
2442                 case PCA_BAD_QACCESS_VF:
2443                         estr = "PCA_BAD_QACCESS_VF"; break;
2444                 case PCA_MALICIOUS_REQ:
2445                         estr = "PCA_MALICIOUS_REQ"; break;
2446                 case PCA_POISONED_TLP:
2447                         estr = "PCA_POISONED_TLP"; break;
2448                 case PCA_TLP_ABORT:
2449                         estr = "PCA_TLP_ABORT"; break;
2450                 default:
2451                         goto error;
2452                 }
2453                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2454                         estr, fault.func ? "VF" : "PF", fault.func,
2455                         fault.address, fault.specinfo);
2456         }
2457
2458         /* Process THI fault */
2459         if (eicr & FM10K_EICR_THI_FAULT) {
2460                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2461                 if (err)
2462                         goto error;
2463                 switch (fault.type) {
2464                 case THI_NO_FAULT:
2465                         estr = "THI_NO_FAULT"; break;
2466                 case THI_MAL_DIS_Q_FAULT:
2467                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2468                 default:
2469                         goto error;
2470                 }
2471                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2472                         estr, fault.func ? "VF" : "PF", fault.func,
2473                         fault.address, fault.specinfo);
2474         }
2475
2476         /* Process FUM fault */
2477         if (eicr & FM10K_EICR_FUM_FAULT) {
2478                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2479                 if (err)
2480                         goto error;
2481                 switch (fault.type) {
2482                 case FUM_NO_FAULT:
2483                         estr = "FUM_NO_FAULT"; break;
2484                 case FUM_UNMAPPED_ADDR:
2485                         estr = "FUM_UNMAPPED_ADDR"; break;
2486                 case FUM_POISONED_TLP:
2487                         estr = "FUM_POISONED_TLP"; break;
2488                 case FUM_BAD_VF_QACCESS:
2489                         estr = "FUM_BAD_VF_QACCESS"; break;
2490                 case FUM_ADD_DECODE_ERR:
2491                         estr = "FUM_ADD_DECODE_ERR"; break;
2492                 case FUM_RO_ERROR:
2493                         estr = "FUM_RO_ERROR"; break;
2494                 case FUM_QPRC_CRC_ERROR:
2495                         estr = "FUM_QPRC_CRC_ERROR"; break;
2496                 case FUM_CSR_TIMEOUT:
2497                         estr = "FUM_CSR_TIMEOUT"; break;
2498                 case FUM_INVALID_TYPE:
2499                         estr = "FUM_INVALID_TYPE"; break;
2500                 case FUM_INVALID_LENGTH:
2501                         estr = "FUM_INVALID_LENGTH"; break;
2502                 case FUM_INVALID_BE:
2503                         estr = "FUM_INVALID_BE"; break;
2504                 case FUM_INVALID_ALIGN:
2505                         estr = "FUM_INVALID_ALIGN"; break;
2506                 default:
2507                         goto error;
2508                 }
2509                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2510                         estr, fault.func ? "VF" : "PF", fault.func,
2511                         fault.address, fault.specinfo);
2512         }
2513
2514         return 0;
2515 error:
2516         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2517         return err;
2518 }
2519
2520 /**
2521  * PF interrupt handler triggered by NIC for handling specific interrupt.
2522  *
2523  * @param handle
2524  *  Pointer to interrupt handle.
2525  * @param param
2526  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2527  *
2528  * @return
2529  *  void
2530  */
2531 static void
2532 fm10k_dev_interrupt_handler_pf(
2533                         __rte_unused struct rte_intr_handle *handle,
2534                         void *param)
2535 {
2536         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2537         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t cause, status;
2539
2540         if (hw->mac.type != fm10k_mac_pf)
2541                 return;
2542
2543         cause = FM10K_READ_REG(hw, FM10K_EICR);
2544
2545         /* Handle PCI fault cases */
2546         if (cause & FM10K_EICR_FAULT_MASK) {
2547                 PMD_INIT_LOG(ERR, "INT: find fault!");
2548                 fm10k_dev_handle_fault(hw, cause);
2549         }
2550
2551         /* Handle switch up/down */
2552         if (cause & FM10K_EICR_SWITCHNOTREADY)
2553                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2554
2555         if (cause & FM10K_EICR_SWITCHREADY)
2556                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2557
2558         /* Handle mailbox message */
2559         fm10k_mbx_lock(hw);
2560         hw->mbx.ops.process(hw, &hw->mbx);
2561         fm10k_mbx_unlock(hw);
2562
2563         /* Handle SRAM error */
2564         if (cause & FM10K_EICR_SRAMERROR) {
2565                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2566
2567                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2568                 /* Write to clear pending bits */
2569                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2570
2571                 /* Todo: print out error message after shared code  updates */
2572         }
2573
2574         /* Clear these 3 events if having any */
2575         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2576                  FM10K_EICR_SWITCHREADY;
2577         if (cause)
2578                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2579
2580         /* Re-enable interrupt from device side */
2581         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2582                                         FM10K_ITR_MASK_CLEAR);
2583         /* Re-enable interrupt from host side */
2584         rte_intr_enable(&(dev->pci_dev->intr_handle));
2585 }
2586
2587 /**
2588  * VF interrupt handler triggered by NIC for handling specific interrupt.
2589  *
2590  * @param handle
2591  *  Pointer to interrupt handle.
2592  * @param param
2593  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2594  *
2595  * @return
2596  *  void
2597  */
2598 static void
2599 fm10k_dev_interrupt_handler_vf(
2600                         __rte_unused struct rte_intr_handle *handle,
2601                         void *param)
2602 {
2603         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2604         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605
2606         if (hw->mac.type != fm10k_mac_vf)
2607                 return;
2608
2609         /* Handle mailbox message if lock is acquired */
2610         fm10k_mbx_lock(hw);
2611         hw->mbx.ops.process(hw, &hw->mbx);
2612         fm10k_mbx_unlock(hw);
2613
2614         /* Re-enable interrupt from device side */
2615         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2616                                         FM10K_ITR_MASK_CLEAR);
2617         /* Re-enable interrupt from host side */
2618         rte_intr_enable(&(dev->pci_dev->intr_handle));
2619 }
2620
2621 /* Mailbox message handler in VF */
2622 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2623         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2624         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2625         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2626         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2627 };
2628
2629 static int
2630 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2631 {
2632         int err = 0;
2633
2634         /* Initialize mailbox lock */
2635         fm10k_mbx_initlock(hw);
2636
2637         /* Replace default message handler with new ones */
2638         if (hw->mac.type == fm10k_mac_vf)
2639                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2640
2641         if (err) {
2642                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2643                                 err);
2644                 return err;
2645         }
2646         /* Connect to SM for PF device or PF for VF device */
2647         return hw->mbx.ops.connect(hw, &hw->mbx);
2648 }
2649
2650 static void
2651 fm10k_close_mbx_service(struct fm10k_hw *hw)
2652 {
2653         /* Disconnect from SM for PF device or PF for VF device */
2654         hw->mbx.ops.disconnect(hw, &hw->mbx);
2655 }
2656
2657 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2658         .dev_configure          = fm10k_dev_configure,
2659         .dev_start              = fm10k_dev_start,
2660         .dev_stop               = fm10k_dev_stop,
2661         .dev_close              = fm10k_dev_close,
2662         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2663         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2664         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2665         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2666         .stats_get              = fm10k_stats_get,
2667         .xstats_get             = fm10k_xstats_get,
2668         .xstats_get_names       = fm10k_xstats_get_names,
2669         .stats_reset            = fm10k_stats_reset,
2670         .xstats_reset           = fm10k_stats_reset,
2671         .link_update            = fm10k_link_update,
2672         .dev_infos_get          = fm10k_dev_infos_get,
2673         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2674         .vlan_filter_set        = fm10k_vlan_filter_set,
2675         .vlan_offload_set       = fm10k_vlan_offload_set,
2676         .mac_addr_add           = fm10k_macaddr_add,
2677         .mac_addr_remove        = fm10k_macaddr_remove,
2678         .rx_queue_start         = fm10k_dev_rx_queue_start,
2679         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2680         .tx_queue_start         = fm10k_dev_tx_queue_start,
2681         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2682         .rx_queue_setup         = fm10k_rx_queue_setup,
2683         .rx_queue_release       = fm10k_rx_queue_release,
2684         .tx_queue_setup         = fm10k_tx_queue_setup,
2685         .tx_queue_release       = fm10k_tx_queue_release,
2686         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2687         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2688         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2689         .reta_update            = fm10k_reta_update,
2690         .reta_query             = fm10k_reta_query,
2691         .rss_hash_update        = fm10k_rss_hash_update,
2692         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2693 };
2694
2695 static int ftag_check_handler(__rte_unused const char *key,
2696                 const char *value, __rte_unused void *opaque)
2697 {
2698         if (strcmp(value, "1"))
2699                 return -1;
2700
2701         return 0;
2702 }
2703
2704 static int
2705 fm10k_check_ftag(struct rte_devargs *devargs)
2706 {
2707         struct rte_kvargs *kvlist;
2708         const char *ftag_key = "enable_ftag";
2709
2710         if (devargs == NULL)
2711                 return 0;
2712
2713         kvlist = rte_kvargs_parse(devargs->args, NULL);
2714         if (kvlist == NULL)
2715                 return 0;
2716
2717         if (!rte_kvargs_count(kvlist, ftag_key)) {
2718                 rte_kvargs_free(kvlist);
2719                 return 0;
2720         }
2721         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2722         if (rte_kvargs_process(kvlist, ftag_key,
2723                                 ftag_check_handler, NULL) < 0) {
2724                 rte_kvargs_free(kvlist);
2725                 return 0;
2726         }
2727         rte_kvargs_free(kvlist);
2728
2729         return 1;
2730 }
2731
2732 static void __attribute__((cold))
2733 fm10k_set_tx_function(struct rte_eth_dev *dev)
2734 {
2735         struct fm10k_tx_queue *txq;
2736         int i;
2737         int use_sse = 1;
2738         uint16_t tx_ftag_en = 0;
2739
2740         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2741                 tx_ftag_en = 1;
2742
2743         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2744                 txq = dev->data->tx_queues[i];
2745                 txq->tx_ftag_en = tx_ftag_en;
2746                 /* Check if Vector Tx is satisfied */
2747                 if (fm10k_tx_vec_condition_check(txq))
2748                         use_sse = 0;
2749         }
2750
2751         if (use_sse) {
2752                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2753                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2754                         txq = dev->data->tx_queues[i];
2755                         fm10k_txq_vec_setup(txq);
2756                 }
2757                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2758         } else {
2759                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2760                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2761         }
2762 }
2763
2764 static void __attribute__((cold))
2765 fm10k_set_rx_function(struct rte_eth_dev *dev)
2766 {
2767         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2768         uint16_t i, rx_using_sse;
2769         uint16_t rx_ftag_en = 0;
2770
2771         if (fm10k_check_ftag(dev->pci_dev->device.devargs))
2772                 rx_ftag_en = 1;
2773
2774         /* In order to allow Vector Rx there are a few configuration
2775          * conditions to be met.
2776          */
2777         if (!fm10k_rx_vec_condition_check(dev) &&
2778                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2779                 if (dev->data->scattered_rx)
2780                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2781                 else
2782                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2783         } else if (dev->data->scattered_rx)
2784                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2785         else
2786                 dev->rx_pkt_burst = fm10k_recv_pkts;
2787
2788         rx_using_sse =
2789                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2790                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2791
2792         if (rx_using_sse)
2793                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2794         else
2795                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2796
2797         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2798                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2799
2800                 rxq->rx_using_sse = rx_using_sse;
2801                 rxq->rx_ftag_en = rx_ftag_en;
2802         }
2803 }
2804
2805 static void
2806 fm10k_params_init(struct rte_eth_dev *dev)
2807 {
2808         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2810
2811         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2812          * there is no way to get link status without reading BAR4.  Until this
2813          * works, assume we have maximum bandwidth.
2814          * @todo - fix bus info
2815          */
2816         hw->bus_caps.speed = fm10k_bus_speed_8000;
2817         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2818         hw->bus_caps.payload = fm10k_bus_payload_512;
2819         hw->bus.speed = fm10k_bus_speed_8000;
2820         hw->bus.width = fm10k_bus_width_pcie_x8;
2821         hw->bus.payload = fm10k_bus_payload_256;
2822
2823         info->rx_vec_allowed = true;
2824 }
2825
2826 static int
2827 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2828 {
2829         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830         int diag, i;
2831         struct fm10k_macvlan_filter_info *macvlan;
2832
2833         PMD_INIT_FUNC_TRACE();
2834
2835         dev->dev_ops = &fm10k_eth_dev_ops;
2836         dev->rx_pkt_burst = &fm10k_recv_pkts;
2837         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2838
2839         /* only initialize in the primary process */
2840         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2841                 return 0;
2842
2843         rte_eth_copy_pci_info(dev, dev->pci_dev);
2844
2845         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2846         memset(macvlan, 0, sizeof(*macvlan));
2847         /* Vendor and Device ID need to be set before init of shared code */
2848         memset(hw, 0, sizeof(*hw));
2849         hw->device_id = dev->pci_dev->id.device_id;
2850         hw->vendor_id = dev->pci_dev->id.vendor_id;
2851         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2852         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2853         hw->revision_id = 0;
2854         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2855         if (hw->hw_addr == NULL) {
2856                 PMD_INIT_LOG(ERR, "Bad mem resource."
2857                         " Try to blacklist unused devices.");
2858                 return -EIO;
2859         }
2860
2861         /* Store fm10k_adapter pointer */
2862         hw->back = dev->data->dev_private;
2863
2864         /* Initialize the shared code */
2865         diag = fm10k_init_shared_code(hw);
2866         if (diag != FM10K_SUCCESS) {
2867                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2868                 return -EIO;
2869         }
2870
2871         /* Initialize parameters */
2872         fm10k_params_init(dev);
2873
2874         /* Initialize the hw */
2875         diag = fm10k_init_hw(hw);
2876         if (diag != FM10K_SUCCESS) {
2877                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2878                 return -EIO;
2879         }
2880
2881         /* Initialize MAC address(es) */
2882         dev->data->mac_addrs = rte_zmalloc("fm10k",
2883                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2884         if (dev->data->mac_addrs == NULL) {
2885                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2886                 return -ENOMEM;
2887         }
2888
2889         diag = fm10k_read_mac_addr(hw);
2890
2891         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2892                         &dev->data->mac_addrs[0]);
2893
2894         if (diag != FM10K_SUCCESS ||
2895                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2896
2897                 /* Generate a random addr */
2898                 eth_random_addr(hw->mac.addr);
2899                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2900                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2901                 &dev->data->mac_addrs[0]);
2902         }
2903
2904         /* Reset the hw statistics */
2905         fm10k_stats_reset(dev);
2906
2907         /* Reset the hw */
2908         diag = fm10k_reset_hw(hw);
2909         if (diag != FM10K_SUCCESS) {
2910                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2911                 return -EIO;
2912         }
2913
2914         /* Setup mailbox service */
2915         diag = fm10k_setup_mbx_service(hw);
2916         if (diag != FM10K_SUCCESS) {
2917                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2918                 return -EIO;
2919         }
2920
2921         /*PF/VF has different interrupt handling mechanism */
2922         if (hw->mac.type == fm10k_mac_pf) {
2923                 /* register callback func to eal lib */
2924                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2925                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2926
2927                 /* enable MISC interrupt */
2928                 fm10k_dev_enable_intr_pf(dev);
2929         } else { /* VF */
2930                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2931                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2932
2933                 fm10k_dev_enable_intr_vf(dev);
2934         }
2935
2936         /* Enable intr after callback registered */
2937         rte_intr_enable(&(dev->pci_dev->intr_handle));
2938
2939         hw->mac.ops.update_int_moderator(hw);
2940
2941         /* Make sure Switch Manager is ready before going forward. */
2942         if (hw->mac.type == fm10k_mac_pf) {
2943                 int switch_ready = 0;
2944
2945                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2946                         fm10k_mbx_lock(hw);
2947                         hw->mac.ops.get_host_state(hw, &switch_ready);
2948                         fm10k_mbx_unlock(hw);
2949                         if (switch_ready)
2950                                 break;
2951                         /* Delay some time to acquire async LPORT_MAP info. */
2952                         rte_delay_us(WAIT_SWITCH_MSG_US);
2953                 }
2954
2955                 if (switch_ready == 0) {
2956                         PMD_INIT_LOG(ERR, "switch is not ready");
2957                         return -1;
2958                 }
2959         }
2960
2961         /*
2962          * Below function will trigger operations on mailbox, acquire lock to
2963          * avoid race condition from interrupt handler. Operations on mailbox
2964          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2965          * will handle and generate an interrupt to our side. Then,  FIFO in
2966          * mailbox will be touched.
2967          */
2968         fm10k_mbx_lock(hw);
2969         /* Enable port first */
2970         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2971                                         MAX_LPORT_NUM, 1);
2972
2973         /* Set unicast mode by default. App can change to other mode in other
2974          * API func.
2975          */
2976         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2977                                         FM10K_XCAST_MODE_NONE);
2978
2979         fm10k_mbx_unlock(hw);
2980
2981         /* Make sure default VID is ready before going forward. */
2982         if (hw->mac.type == fm10k_mac_pf) {
2983                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2984                         if (hw->mac.default_vid)
2985                                 break;
2986                         /* Delay some time to acquire async port VLAN info. */
2987                         rte_delay_us(WAIT_SWITCH_MSG_US);
2988                 }
2989
2990                 if (!hw->mac.default_vid) {
2991                         PMD_INIT_LOG(ERR, "default VID is not ready");
2992                         return -1;
2993                 }
2994         }
2995
2996         /* Add default mac address */
2997         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
2998                 MAIN_VSI_POOL_NUMBER);
2999
3000         return 0;
3001 }
3002
3003 static int
3004 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3005 {
3006         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007
3008         PMD_INIT_FUNC_TRACE();
3009
3010         /* only uninitialize in the primary process */
3011         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3012                 return 0;
3013
3014         /* safe to close dev here */
3015         fm10k_dev_close(dev);
3016
3017         dev->dev_ops = NULL;
3018         dev->rx_pkt_burst = NULL;
3019         dev->tx_pkt_burst = NULL;
3020
3021         /* disable uio/vfio intr */
3022         rte_intr_disable(&(dev->pci_dev->intr_handle));
3023
3024         /*PF/VF has different interrupt handling mechanism */
3025         if (hw->mac.type == fm10k_mac_pf) {
3026                 /* disable interrupt */
3027                 fm10k_dev_disable_intr_pf(dev);
3028
3029                 /* unregister callback func to eal lib */
3030                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3031                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3032         } else {
3033                 /* disable interrupt */
3034                 fm10k_dev_disable_intr_vf(dev);
3035
3036                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3037                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3038         }
3039
3040         /* free mac memory */
3041         if (dev->data->mac_addrs) {
3042                 rte_free(dev->data->mac_addrs);
3043                 dev->data->mac_addrs = NULL;
3044         }
3045
3046         memset(hw, 0, sizeof(*hw));
3047
3048         return 0;
3049 }
3050
3051 /*
3052  * The set of PCI devices this driver supports. This driver will enable both PF
3053  * and SRIOV-VF devices.
3054  */
3055 static const struct rte_pci_id pci_id_fm10k_map[] = {
3056         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3057         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3058         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3059         { .vendor_id = 0, /* sentinel */ },
3060 };
3061
3062 static struct eth_driver rte_pmd_fm10k = {
3063         .pci_drv = {
3064                 .id_table = pci_id_fm10k_map,
3065                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3066                         RTE_PCI_DRV_DETACHABLE,
3067                 .probe = rte_eth_dev_pci_probe,
3068                 .remove = rte_eth_dev_pci_remove,
3069         },
3070         .eth_dev_init = eth_fm10k_dev_init,
3071         .eth_dev_uninit = eth_fm10k_dev_uninit,
3072         .dev_private_size = sizeof(struct fm10k_adapter),
3073 };
3074
3075 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3076 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3077 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio");