drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* Number of chars per uint32 type */
  56 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  57 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  58
  59 /* default 1:1 map from queue ID to interrupt vector ID */
  60 #define Q2V(dev, queue_id) (dev->pci_dev->intr_handle.intr_vec[queue_id])
  61
  62 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  63 #define MAX_LPORT_NUM    128
  64 #define GLORT_FD_Q_BASE  0x40
  65 #define GLORT_PF_MASK    0xFFC0
  66 #define GLORT_FD_MASK    GLORT_PF_MASK
  67 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  68
  69 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  70 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  71 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  72 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  74 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  75 static int
  76 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  77 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  78         const u8 *mac, bool add, uint32_t pool);
  79 static void fm10k_tx_queue_release(void *queue);
  80 static void fm10k_rx_queue_release(void *queue);
  81 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  82 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  83 static int fm10k_check_ftag(struct rte_devargs *devargs);
  84
  85 struct fm10k_xstats_name_off {
  86         char name[RTE_ETH_XSTATS_NAME_SIZE];
  87         unsigned offset;
  88 };
  89
  90 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  91         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  92         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  93         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  94         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  95         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  96         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  97         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
  98         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
  99                 nodesc_drop)},
 100 };
 101
 102 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 103                 sizeof(fm10k_hw_stats_strings[0]))
 104
 105 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 106         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 107         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 108         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 109 };
 110
 111 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 112                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 113
 114 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 115         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 116         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 117 };
 118
 119 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 120                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 121
 122 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 123                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 124 static int
 125 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 126
 127 static void
 128 fm10k_mbx_initlock(struct fm10k_hw *hw)
 129 {
 130         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 131 }
 132
 133 static void
 134 fm10k_mbx_lock(struct fm10k_hw *hw)
 135 {
 136         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 137                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 138 }
 139
 140 static void
 141 fm10k_mbx_unlock(struct fm10k_hw *hw)
 142 {
 143         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 144 }
 145
 146 /* Stubs needed for linkage when vPMD is disabled */
 147 int __attribute__((weak))
 148 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 149 {
 150         return -1;
 151 }
 152
 153 uint16_t __attribute__((weak))
 154 fm10k_recv_pkts_vec(
 155         __rte_unused void *rx_queue,
 156         __rte_unused struct rte_mbuf **rx_pkts,
 157         __rte_unused uint16_t nb_pkts)
 158 {
 159         return 0;
 160 }
 161
 162 uint16_t __attribute__((weak))
 163 fm10k_recv_scattered_pkts_vec(
 164                 __rte_unused void *rx_queue,
 165                 __rte_unused struct rte_mbuf **rx_pkts,
 166                 __rte_unused uint16_t nb_pkts)
 167 {
 168         return 0;
 169 }
 170
 171 int __attribute__((weak))
 172 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 173
 174 {
 175         return -1;
 176 }
 177
 178 void __attribute__((weak))
 179 fm10k_rx_queue_release_mbufs_vec(
 180                 __rte_unused struct fm10k_rx_queue *rxq)
 181 {
 182         return;
 183 }
 184
 185 void __attribute__((weak))
 186 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 187 {
 188         return;
 189 }
 190
 191 int __attribute__((weak))
 192 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 193 {
 194         return -1;
 195 }
 196
 197 uint16_t __attribute__((weak))
 198 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 199                 __rte_unused struct rte_mbuf **tx_pkts,
 200                 __rte_unused uint16_t nb_pkts)
 201 {
 202         return 0;
 203 }
 204
 205 /*
 206  * reset queue to initial state, allocate software buffers used when starting
 207  * device.
 208  * return 0 on success
 209  * return -ENOMEM if buffers cannot be allocated
 210  * return -EINVAL if buffers do not satisfy alignment condition
 211  */
 212 static inline int
 213 rx_queue_reset(struct fm10k_rx_queue *q)
 214 {
 215         static const union fm10k_rx_desc zero = {{0} };
 216         uint64_t dma_addr;
 217         int i, diag;
 218         PMD_INIT_FUNC_TRACE();
 219
 220         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 221         if (diag != 0)
 222                 return -ENOMEM;
 223
 224         for (i = 0; i < q->nb_desc; ++i) {
 225                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 226                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 227                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 228                                                 q->nb_desc);
 229                         return -EINVAL;
 230                 }
 231                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 232                 q->hw_ring[i].q.pkt_addr = dma_addr;
 233                 q->hw_ring[i].q.hdr_addr = dma_addr;
 234         }
 235
 236         /* initialize extra software ring entries. Space for these extra
 237          * entries is always allocated.
 238          */
 239         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 240         for (i = 0; i < q->nb_fake_desc; ++i) {
 241                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 242                 q->hw_ring[q->nb_desc + i] = zero;
 243         }
 244
 245         q->next_dd = 0;
 246         q->next_alloc = 0;
 247         q->next_trigger = q->alloc_thresh - 1;
 248         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 249         q->rxrearm_start = 0;
 250         q->rxrearm_nb = 0;
 251
 252         return 0;
 253 }
 254
 255 /*
 256  * clean queue, descriptor rings, free software buffers used when stopping
 257  * device.
 258  */
 259 static inline void
 260 rx_queue_clean(struct fm10k_rx_queue *q)
 261 {
 262         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 263         uint32_t i;
 264         PMD_INIT_FUNC_TRACE();
 265
 266         /* zero descriptor rings */
 267         for (i = 0; i < q->nb_desc; ++i)
 268                 q->hw_ring[i] = zero;
 269
 270         /* zero faked descriptors */
 271         for (i = 0; i < q->nb_fake_desc; ++i)
 272                 q->hw_ring[q->nb_desc + i] = zero;
 273
 274         /* vPMD driver has a different way of releasing mbufs. */
 275         if (q->rx_using_sse) {
 276                 fm10k_rx_queue_release_mbufs_vec(q);
 277                 return;
 278         }
 279
 280         /* free software buffers */
 281         for (i = 0; i < q->nb_desc; ++i) {
 282                 if (q->sw_ring[i]) {
 283                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 284                         q->sw_ring[i] = NULL;
 285                 }
 286         }
 287 }
 288
 289 /*
 290  * free all queue memory used when releasing the queue (i.e. configure)
 291  */
 292 static inline void
 293 rx_queue_free(struct fm10k_rx_queue *q)
 294 {
 295         PMD_INIT_FUNC_TRACE();
 296         if (q) {
 297                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 298                 rx_queue_clean(q);
 299                 if (q->sw_ring) {
 300                         rte_free(q->sw_ring);
 301                         q->sw_ring = NULL;
 302                 }
 303                 rte_free(q);
 304                 q = NULL;
 305         }
 306 }
 307
 308 /*
 309  * disable RX queue, wait unitl HW finished necessary flush operation
 310  */
 311 static inline int
 312 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 313 {
 314         uint32_t reg, i;
 315
 316         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 317         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 318                         reg & ~FM10K_RXQCTL_ENABLE);
 319
 320         /* Wait 100us at most */
 321         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 322                 rte_delay_us(1);
 323                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 324                 if (!(reg & FM10K_RXQCTL_ENABLE))
 325                         break;
 326         }
 327
 328         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 329                 return -1;
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * reset queue to initial state, allocate software buffers used when starting
 336  * device
 337  */
 338 static inline void
 339 tx_queue_reset(struct fm10k_tx_queue *q)
 340 {
 341         PMD_INIT_FUNC_TRACE();
 342         q->last_free = 0;
 343         q->next_free = 0;
 344         q->nb_used = 0;
 345         q->nb_free = q->nb_desc - 1;
 346         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 347         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 348 }
 349
 350 /*
 351  * clean queue, descriptor rings, free software buffers used when stopping
 352  * device
 353  */
 354 static inline void
 355 tx_queue_clean(struct fm10k_tx_queue *q)
 356 {
 357         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 358         uint32_t i;
 359         PMD_INIT_FUNC_TRACE();
 360
 361         /* zero descriptor rings */
 362         for (i = 0; i < q->nb_desc; ++i)
 363                 q->hw_ring[i] = zero;
 364
 365         /* free software buffers */
 366         for (i = 0; i < q->nb_desc; ++i) {
 367                 if (q->sw_ring[i]) {
 368                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 369                         q->sw_ring[i] = NULL;
 370                 }
 371         }
 372 }
 373
 374 /*
 375  * free all queue memory used when releasing the queue (i.e. configure)
 376  */
 377 static inline void
 378 tx_queue_free(struct fm10k_tx_queue *q)
 379 {
 380         PMD_INIT_FUNC_TRACE();
 381         if (q) {
 382                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 383                 tx_queue_clean(q);
 384                 if (q->rs_tracker.list) {
 385                         rte_free(q->rs_tracker.list);
 386                         q->rs_tracker.list = NULL;
 387                 }
 388                 if (q->sw_ring) {
 389                         rte_free(q->sw_ring);
 390                         q->sw_ring = NULL;
 391                 }
 392                 rte_free(q);
 393                 q = NULL;
 394         }
 395 }
 396
 397 /*
 398  * disable TX queue, wait unitl HW finished necessary flush operation
 399  */
 400 static inline int
 401 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 402 {
 403         uint32_t reg, i;
 404
 405         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 406         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 407                         reg & ~FM10K_TXDCTL_ENABLE);
 408
 409         /* Wait 100us at most */
 410         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 411                 rte_delay_us(1);
 412                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 413                 if (!(reg & FM10K_TXDCTL_ENABLE))
 414                         break;
 415         }
 416
 417         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 418                 return -1;
 419
 420         return 0;
 421 }
 422
 423 static int
 424 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 425 {
 426         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 427         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 428         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 429         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 430
 431         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 432
 433         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 434                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 435                 return -EINVAL;
 436         }
 437
 438         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 439                 return 0;
 440
 441         if (hw->mac.type == fm10k_mac_vf) {
 442                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 443                 return -EINVAL;
 444         }
 445
 446         /* Check VMDQ queue pool number */
 447         if (vmdq_conf->nb_queue_pools >
 448                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 449                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 450                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 451                         vmdq_conf->nb_queue_pools);
 452                 return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static const struct fm10k_txq_ops def_txq_ops = {
 459         .reset = tx_queue_reset,
 460 };
 461
 462 static int
 463 fm10k_dev_configure(struct rte_eth_dev *dev)
 464 {
 465         int ret;
 466
 467         PMD_INIT_FUNC_TRACE();
 468
 469         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 470                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 471         /* multipe queue mode checking */
 472         ret  = fm10k_check_mq_mode(dev);
 473         if (ret != 0) {
 474                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 475                             ret);
 476                 return ret;
 477         }
 478
 479         return 0;
 480 }
 481
 482 /* fls = find last set bit = 32 minus the number of leading zeros */
 483 #ifndef fls
 484 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 485 #endif
 486
 487 static void
 488 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 489 {
 490         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 491         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 492         uint32_t i;
 493
 494         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 495
 496         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 497                 if (!vmdq_conf->pool_map[i].pools)
 498                         continue;
 499                 fm10k_mbx_lock(hw);
 500                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 501                 fm10k_mbx_unlock(hw);
 502         }
 503 }
 504
 505 static void
 506 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 507 {
 508         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 509
 510         /* Add default mac address */
 511         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 512                 MAIN_VSI_POOL_NUMBER);
 513 }
 514
 515 static void
 516 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 517 {
 518         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 520         uint32_t mrqc, *key, i, reta, j;
 521         uint64_t hf;
 522
 523 #define RSS_KEY_SIZE 40
 524         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 525                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 526                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 527                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 528                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 529                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 530         };
 531
 532         if (dev->data->nb_rx_queues == 1 ||
 533             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 534             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 535                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 536                 return;
 537         }
 538
 539         /* random key is rss_intel_key (default) or user provided (rss_key) */
 540         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 541                 key = (uint32_t *)rss_intel_key;
 542         else
 543                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 544
 545         /* Now fill our hash function seeds, 4 bytes at a time */
 546         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 547                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 548
 549         /*
 550          * Fill in redirection table
 551          * The byte-swap is needed because NIC registers are in
 552          * little-endian order.
 553          */
 554         reta = 0;
 555         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 556                 if (j == dev->data->nb_rx_queues)
 557                         j = 0;
 558                 reta = (reta << CHAR_BIT) | j;
 559                 if ((i & 3) == 3)
 560                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 561                                         rte_bswap32(reta));
 562         }
 563
 564         /*
 565          * Generate RSS hash based on packet types, TCP/UDP
 566          * port numbers and/or IPv4/v6 src and dst addresses
 567          */
 568         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 569         mrqc = 0;
 570         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 571         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 572         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 573         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 574         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 575         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 577         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 579
 580         if (mrqc == 0) {
 581                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 582                         "supported", hf);
 583                 return;
 584         }
 585
 586         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 587 }
 588
 589 static void
 590 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 591 {
 592         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 593         uint32_t i;
 594
 595         for (i = 0; i < nb_lport_new; i++) {
 596                 /* Set unicast mode by default. App can change
 597                  * to other mode in other API func.
 598                  */
 599                 fm10k_mbx_lock(hw);
 600                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 601                         FM10K_XCAST_MODE_NONE);
 602                 fm10k_mbx_unlock(hw);
 603         }
 604 }
 605
 606 static void
 607 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 608 {
 609         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 610         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 611         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 612         struct fm10k_macvlan_filter_info *macvlan;
 613         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 614         uint16_t nb_lport_new;
 615
 616         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 617         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 618
 619         fm10k_dev_rss_configure(dev);
 620
 621         /* only PF supports VMDQ */
 622         if (hw->mac.type != fm10k_mac_pf)
 623                 return;
 624
 625         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 626                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 627
 628         /* no pool number change, no need to update logic port and VLAN/MAC */
 629         if (macvlan->nb_queue_pools == nb_queue_pools)
 630                 return;
 631
 632         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 633         fm10k_dev_logic_port_update(dev, nb_lport_new);
 634
 635         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 636         memset(dev->data->mac_addrs, 0,
 637                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 638         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 639                 &dev->data->mac_addrs[0]);
 640         memset(macvlan, 0, sizeof(*macvlan));
 641         macvlan->nb_queue_pools = nb_queue_pools;
 642
 643         if (nb_queue_pools)
 644                 fm10k_dev_vmdq_rx_configure(dev);
 645         else
 646                 fm10k_dev_pf_main_vsi_reset(dev);
 647 }
 648
 649 static int
 650 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 651 {
 652         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 653         int i, ret;
 654         struct fm10k_tx_queue *txq;
 655         uint64_t base_addr;
 656         uint32_t size;
 657
 658         /* Disable TXINT to avoid possible interrupt */
 659         for (i = 0; i < hw->mac.max_queues; i++)
 660                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 661                                 3 << FM10K_TXINT_TIMER_SHIFT);
 662
 663         /* Setup TX queue */
 664         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 665                 txq = dev->data->tx_queues[i];
 666                 base_addr = txq->hw_ring_phys_addr;
 667                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 668
 669                 /* disable queue to avoid issues while updating state */
 670                 ret = tx_queue_disable(hw, i);
 671                 if (ret) {
 672                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 673                         return -1;
 674                 }
 675                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 676                  * register is read-only for VF.
 677                  */
 678                 if (fm10k_check_ftag(dev->pci_dev->devargs)) {
 679                         if (hw->mac.type == fm10k_mac_pf) {
 680                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 681                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 682                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 683                         } else {
 684                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 685                                 return -ENOTSUP;
 686                         }
 687                 }
 688
 689                 /* set location and size for descriptor ring */
 690                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 691                                 base_addr & UINT64_LOWER_32BITS_MASK);
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 693                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 694                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 695
 696                 /* assign default SGLORT for each TX queue */
 697                 FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 698         }
 699
 700         /* set up vector or scalar TX function as appropriate */
 701         fm10k_set_tx_function(dev);
 702
 703         return 0;
 704 }
 705
 706 static int
 707 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 708 {
 709         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 710         struct fm10k_macvlan_filter_info *macvlan;
 711         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
 712         int i, ret;
 713         struct fm10k_rx_queue *rxq;
 714         uint64_t base_addr;
 715         uint32_t size;
 716         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 717         uint32_t logic_port = hw->mac.dglort_map;
 718         uint16_t buf_size;
 719         uint16_t queue_stride = 0;
 720
 721         /* enable RXINT for interrupt mode */
 722         i = 0;
 723         if (rte_intr_dp_is_en(intr_handle)) {
 724                 for (; i < dev->data->nb_rx_queues; i++) {
 725                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(dev, i));
 726                         if (hw->mac.type == fm10k_mac_pf)
 727                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
 728                                         FM10K_ITR_AUTOMASK |
 729                                         FM10K_ITR_MASK_CLEAR);
 730                         else
 731                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                 }
 735         }
 736         /* Disable other RXINT to avoid possible interrupt */
 737         for (; i < hw->mac.max_queues; i++)
 738                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 739                         3 << FM10K_RXINT_TIMER_SHIFT);
 740
 741         /* Setup RX queues */
 742         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 743                 rxq = dev->data->rx_queues[i];
 744                 base_addr = rxq->hw_ring_phys_addr;
 745                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 746
 747                 /* disable queue to avoid issues while updating state */
 748                 ret = rx_queue_disable(hw, i);
 749                 if (ret) {
 750                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 751                         return -1;
 752                 }
 753
 754                 /* Setup the Base and Length of the Rx Descriptor Ring */
 755                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 756                                 base_addr & UINT64_LOWER_32BITS_MASK);
 757                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 758                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 759                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 760
 761                 /* Configure the Rx buffer size for one buff without split */
 762                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 763                         RTE_PKTMBUF_HEADROOM);
 764                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 765                  * reserved for this purpose, and the worst case could be 511B.
 766                  * But SRR reg assumes all buffers have the same size. In order
 767                  * to fill the gap, we'll have to consider the worst case and
 768                  * assume 512B is reserved. If we don't do so, it's possible
 769                  * for HW to overwrite data to next mbuf.
 770                  */
 771                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 772
 773                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 774                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 775                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 776
 777                 /* It adds dual VLAN length for supporting dual VLAN */
 778                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 779                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 780                         dev->data->dev_conf.rxmode.enable_scatter) {
 781                         uint32_t reg;
 782                         dev->data->scattered_rx = 1;
 783                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 784                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 785                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 786                 }
 787
 788                 /* Enable drop on empty, it's RO for VF */
 789                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 790                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 791
 792                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 793                 FM10K_WRITE_FLUSH(hw);
 794         }
 795
 796         /* Configure VMDQ/RSS if applicable */
 797         fm10k_dev_mq_rx_configure(dev);
 798
 799         /* Decide the best RX function */
 800         fm10k_set_rx_function(dev);
 801
 802         /* update RX_SGLORT for loopback suppress*/
 803         if (hw->mac.type != fm10k_mac_pf)
 804                 return 0;
 805         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 806         if (macvlan->nb_queue_pools)
 807                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 808         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 809                 if (i && queue_stride && !(i % queue_stride))
 810                         logic_port++;
 811                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int
 818 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 819 {
 820         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 821         int err = -1;
 822         uint32_t reg;
 823         struct fm10k_rx_queue *rxq;
 824
 825         PMD_INIT_FUNC_TRACE();
 826
 827         if (rx_queue_id < dev->data->nb_rx_queues) {
 828                 rxq = dev->data->rx_queues[rx_queue_id];
 829                 err = rx_queue_reset(rxq);
 830                 if (err == -ENOMEM) {
 831                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 832                         return err;
 833                 } else if (err == -EINVAL) {
 834                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 835                                 " %d", err);
 836                         return err;
 837                 }
 838
 839                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 840                  * Note: this must be done AFTER the queue is enabled on real
 841                  * hardware, but BEFORE the queue is enabled when using the
 842                  * emulation platform. Do it in both places for now and remove
 843                  * this comment and the following two register writes when the
 844                  * emulation platform is no longer being used.
 845                  */
 846                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 847                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 848
 849                 /* Set PF ownership flag for PF devices */
 850                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 851                 if (hw->mac.type == fm10k_mac_pf)
 852                         reg |= FM10K_RXQCTL_PF;
 853                 reg |= FM10K_RXQCTL_ENABLE;
 854                 /* enable RX queue */
 855                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 856                 FM10K_WRITE_FLUSH(hw);
 857
 858                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 859                  * Note: this must be done AFTER the queue is enabled
 860                  */
 861                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 862                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 863                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 864         }
 865
 866         return err;
 867 }
 868
 869 static int
 870 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 871 {
 872         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 873
 874         PMD_INIT_FUNC_TRACE();
 875
 876         if (rx_queue_id < dev->data->nb_rx_queues) {
 877                 /* Disable RX queue */
 878                 rx_queue_disable(hw, rx_queue_id);
 879
 880                 /* Free mbuf and clean HW ring */
 881                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 882                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static int
 889 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 890 {
 891         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 892         /** @todo - this should be defined in the shared code */
 893 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 894         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 895         int err = 0;
 896
 897         PMD_INIT_FUNC_TRACE();
 898
 899         if (tx_queue_id < dev->data->nb_tx_queues) {
 900                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 901
 902                 q->ops->reset(q);
 903
 904                 /* reset head and tail pointers */
 905                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 906                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 907
 908                 /* enable TX queue */
 909                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 910                                         FM10K_TXDCTL_ENABLE | txdctl);
 911                 FM10K_WRITE_FLUSH(hw);
 912                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 913         } else
 914                 err = -1;
 915
 916         return err;
 917 }
 918
 919 static int
 920 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 921 {
 922         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         PMD_INIT_FUNC_TRACE();
 925
 926         if (tx_queue_id < dev->data->nb_tx_queues) {
 927                 tx_queue_disable(hw, tx_queue_id);
 928                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 929                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 930         }
 931
 932         return 0;
 933 }
 934
 935 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 936 {
 937         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 938                 != FM10K_DGLORTMAP_NONE);
 939 }
 940
 941 static void
 942 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 943 {
 944         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945         int status;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         /* Return if it didn't acquire valid glort range */
 950         if (!fm10k_glort_valid(hw))
 951                 return;
 952
 953         fm10k_mbx_lock(hw);
 954         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 955                                 FM10K_XCAST_MODE_PROMISC);
 956         fm10k_mbx_unlock(hw);
 957
 958         if (status != FM10K_SUCCESS)
 959                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 960 }
 961
 962 static void
 963 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 964 {
 965         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         uint8_t mode;
 967         int status;
 968
 969         PMD_INIT_FUNC_TRACE();
 970
 971         /* Return if it didn't acquire valid glort range */
 972         if (!fm10k_glort_valid(hw))
 973                 return;
 974
 975         if (dev->data->all_multicast == 1)
 976                 mode = FM10K_XCAST_MODE_ALLMULTI;
 977         else
 978                 mode = FM10K_XCAST_MODE_NONE;
 979
 980         fm10k_mbx_lock(hw);
 981         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 982                                 mode);
 983         fm10k_mbx_unlock(hw);
 984
 985         if (status != FM10K_SUCCESS)
 986                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 987 }
 988
 989 static void
 990 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 991 {
 992         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 993         int status;
 994
 995         PMD_INIT_FUNC_TRACE();
 996
 997         /* Return if it didn't acquire valid glort range */
 998         if (!fm10k_glort_valid(hw))
 999                 return;
1000
1001         /* If promiscuous mode is enabled, it doesn't make sense to enable
1002          * allmulticast and disable promiscuous since fm10k only can select
1003          * one of the modes.
1004          */
1005         if (dev->data->promiscuous) {
1006                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1007                         "needn't enable allmulticast");
1008                 return;
1009         }
1010
1011         fm10k_mbx_lock(hw);
1012         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1013                                 FM10K_XCAST_MODE_ALLMULTI);
1014         fm10k_mbx_unlock(hw);
1015
1016         if (status != FM10K_SUCCESS)
1017                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1018 }
1019
1020 static void
1021 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1022 {
1023         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         int status;
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         /* Return if it didn't acquire valid glort range */
1029         if (!fm10k_glort_valid(hw))
1030                 return;
1031
1032         if (dev->data->promiscuous) {
1033                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1034                         "since promisc mode is enabled");
1035                 return;
1036         }
1037
1038         fm10k_mbx_lock(hw);
1039         /* Change mode to unicast mode */
1040         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1041                                 FM10K_XCAST_MODE_NONE);
1042         fm10k_mbx_unlock(hw);
1043
1044         if (status != FM10K_SUCCESS)
1045                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1046 }
1047
1048 static void
1049 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1050 {
1051         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1053         uint16_t nb_queue_pools;
1054         struct fm10k_macvlan_filter_info *macvlan;
1055
1056         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1057         nb_queue_pools = macvlan->nb_queue_pools;
1058         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1059         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1060
1061         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1062         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1063         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1064                         hw->mac.dglort_map;
1065         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1066         /* Configure VMDQ/RSS DGlort Decoder */
1067         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1068
1069         /* Flow Director configurations, only queue number is valid. */
1070         dglortdec = fls(dev->data->nb_rx_queues - 1);
1071         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1072                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1073         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1074         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1075
1076         /* Invalidate all other GLORT entries */
1077         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1078                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1079                                 FM10K_DGLORTMAP_NONE);
1080 }
1081
1082 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1083 static int
1084 fm10k_dev_start(struct rte_eth_dev *dev)
1085 {
1086         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1087         int i, diag;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         /* stop, init, then start the hw */
1092         diag = fm10k_stop_hw(hw);
1093         if (diag != FM10K_SUCCESS) {
1094                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1095                 return -EIO;
1096         }
1097
1098         diag = fm10k_init_hw(hw);
1099         if (diag != FM10K_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1101                 return -EIO;
1102         }
1103
1104         diag = fm10k_start_hw(hw);
1105         if (diag != FM10K_SUCCESS) {
1106                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1107                 return -EIO;
1108         }
1109
1110         diag = fm10k_dev_tx_init(dev);
1111         if (diag) {
1112                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1113                 return diag;
1114         }
1115
1116         if (fm10k_dev_rxq_interrupt_setup(dev))
1117                 return -EIO;
1118
1119         diag = fm10k_dev_rx_init(dev);
1120         if (diag) {
1121                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1122                 return diag;
1123         }
1124
1125         if (hw->mac.type == fm10k_mac_pf)
1126                 fm10k_dev_dglort_map_configure(dev);
1127
1128         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1129                 struct fm10k_rx_queue *rxq;
1130                 rxq = dev->data->rx_queues[i];
1131
1132                 if (rxq->rx_deferred_start)
1133                         continue;
1134                 diag = fm10k_dev_rx_queue_start(dev, i);
1135                 if (diag != 0) {
1136                         int j;
1137                         for (j = 0; j < i; ++j)
1138                                 rx_queue_clean(dev->data->rx_queues[j]);
1139                         return diag;
1140                 }
1141         }
1142
1143         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1144                 struct fm10k_tx_queue *txq;
1145                 txq = dev->data->tx_queues[i];
1146
1147                 if (txq->tx_deferred_start)
1148                         continue;
1149                 diag = fm10k_dev_tx_queue_start(dev, i);
1150                 if (diag != 0) {
1151                         int j;
1152                         for (j = 0; j < i; ++j)
1153                                 tx_queue_clean(dev->data->tx_queues[j]);
1154                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1155                                 rx_queue_clean(dev->data->rx_queues[j]);
1156                         return diag;
1157                 }
1158         }
1159
1160         /* Update default vlan when not in VMDQ mode */
1161         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1162                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1163
1164         return 0;
1165 }
1166
1167 static void
1168 fm10k_dev_stop(struct rte_eth_dev *dev)
1169 {
1170         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1172         int i;
1173
1174         PMD_INIT_FUNC_TRACE();
1175
1176         if (dev->data->tx_queues)
1177                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1178                         fm10k_dev_tx_queue_stop(dev, i);
1179
1180         if (dev->data->rx_queues)
1181                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1182                         fm10k_dev_rx_queue_stop(dev, i);
1183
1184         /* Disable datapath event */
1185         if (rte_intr_dp_is_en(intr_handle)) {
1186                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1187                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1188                                 3 << FM10K_RXINT_TIMER_SHIFT);
1189                         if (hw->mac.type == fm10k_mac_pf)
1190                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, i)),
1191                                         FM10K_ITR_MASK_SET);
1192                         else
1193                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, i)),
1194                                         FM10K_ITR_MASK_SET);
1195                 }
1196         }
1197         /* Clean datapath event and queue/vec mapping */
1198         rte_intr_efd_disable(intr_handle);
1199         rte_free(intr_handle->intr_vec);
1200         intr_handle->intr_vec = NULL;
1201 }
1202
1203 static void
1204 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1205 {
1206         int i;
1207
1208         PMD_INIT_FUNC_TRACE();
1209
1210         if (dev->data->tx_queues) {
1211                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1212                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1213
1214                         tx_queue_free(txq);
1215                 }
1216         }
1217
1218         if (dev->data->rx_queues) {
1219                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1220                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1221         }
1222 }
1223
1224 static void
1225 fm10k_dev_close(struct rte_eth_dev *dev)
1226 {
1227         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1228
1229         PMD_INIT_FUNC_TRACE();
1230
1231         fm10k_mbx_lock(hw);
1232         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1233                 MAX_LPORT_NUM, false);
1234         fm10k_mbx_unlock(hw);
1235
1236         /* Stop mailbox service first */
1237         fm10k_close_mbx_service(hw);
1238         fm10k_dev_stop(dev);
1239         fm10k_dev_queue_release(dev);
1240         fm10k_stop_hw(hw);
1241 }
1242
1243 static int
1244 fm10k_link_update(struct rte_eth_dev *dev,
1245         __rte_unused int wait_to_complete)
1246 {
1247         PMD_INIT_FUNC_TRACE();
1248
1249         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1250          * x8 PCIe interface. For now, we leave the speed undefined since there
1251          * is no 50Gbps Ethernet. */
1252         dev->data->dev_link.link_speed  = 0;
1253         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1254         dev->data->dev_link.link_status = ETH_LINK_UP;
1255
1256         return 0;
1257 }
1258
1259 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1260         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1261 {
1262         unsigned i, q;
1263         unsigned count = 0;
1264
1265         if (xstats_names != NULL) {
1266                 /* Note: limit checked in rte_eth_xstats_names() */
1267
1268                 /* Global stats */
1269                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1270                         snprintf(xstats_names[count].name,
1271                                 sizeof(xstats_names[count].name),
1272                                 "%s", fm10k_hw_stats_strings[count].name);
1273                         xstats_names[count].id = count;
1274                         count++;
1275                 }
1276
1277                 /* PF queue stats */
1278                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1279                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1280                                 snprintf(xstats_names[count].name,
1281                                         sizeof(xstats_names[count].name),
1282                                         "rx_q%u_%s", q,
1283                                         fm10k_hw_stats_rx_q_strings[i].name);
1284                                 xstats_names[count].id = count;
1285                                 count++;
1286                         }
1287                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1288                                 snprintf(xstats_names[count].name,
1289                                         sizeof(xstats_names[count].name),
1290                                         "tx_q%u_%s", q,
1291                                         fm10k_hw_stats_tx_q_strings[i].name);
1292                                 xstats_names[count].id = count;
1293                                 count++;
1294                         }
1295                 }
1296         }
1297         return FM10K_NB_XSTATS;
1298 }
1299
1300 static int
1301 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1302                  unsigned n)
1303 {
1304         struct fm10k_hw_stats *hw_stats =
1305                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1306         unsigned i, q, count = 0;
1307
1308         if (n < FM10K_NB_XSTATS)
1309                 return FM10K_NB_XSTATS;
1310
1311         /* Global stats */
1312         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1313                 xstats[count].name[0] = '\0';
1314                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1315                         fm10k_hw_stats_strings[count].offset);
1316                 count++;
1317         }
1318
1319         /* PF queue stats */
1320         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1321                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1322                         xstats[count].name[0] = '\0';
1323                         xstats[count].value =
1324                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1325                                 fm10k_hw_stats_rx_q_strings[i].offset);
1326                         count++;
1327                 }
1328                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1329                         xstats[count].name[0] = '\0';
1330                         xstats[count].value =
1331                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1332                                 fm10k_hw_stats_tx_q_strings[i].offset);
1333                         count++;
1334                 }
1335         }
1336
1337         return FM10K_NB_XSTATS;
1338 }
1339
1340 static void
1341 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1342 {
1343         uint64_t ipackets, opackets, ibytes, obytes;
1344         struct fm10k_hw *hw =
1345                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1346         struct fm10k_hw_stats *hw_stats =
1347                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1348         int i;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         fm10k_update_hw_stats(hw, hw_stats);
1353
1354         ipackets = opackets = ibytes = obytes = 0;
1355         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1356                 (i < hw->mac.max_queues); ++i) {
1357                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1358                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1359                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1360                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1361                 ipackets += stats->q_ipackets[i];
1362                 opackets += stats->q_opackets[i];
1363                 ibytes   += stats->q_ibytes[i];
1364                 obytes   += stats->q_obytes[i];
1365         }
1366         stats->ipackets = ipackets;
1367         stats->opackets = opackets;
1368         stats->ibytes = ibytes;
1369         stats->obytes = obytes;
1370 }
1371
1372 static void
1373 fm10k_stats_reset(struct rte_eth_dev *dev)
1374 {
1375         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         struct fm10k_hw_stats *hw_stats =
1377                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1378
1379         PMD_INIT_FUNC_TRACE();
1380
1381         memset(hw_stats, 0, sizeof(*hw_stats));
1382         fm10k_rebind_hw_stats(hw, hw_stats);
1383 }
1384
1385 static void
1386 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1387         struct rte_eth_dev_info *dev_info)
1388 {
1389         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390
1391         PMD_INIT_FUNC_TRACE();
1392
1393         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1394         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1395         dev_info->max_rx_queues      = hw->mac.max_queues;
1396         dev_info->max_tx_queues      = hw->mac.max_queues;
1397         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1398         dev_info->max_hash_mac_addrs = 0;
1399         dev_info->max_vfs            = dev->pci_dev->max_vfs;
1400         dev_info->vmdq_pool_base     = 0;
1401         dev_info->vmdq_queue_base    = 0;
1402         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1403         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1404         dev_info->rx_offload_capa =
1405                 DEV_RX_OFFLOAD_VLAN_STRIP |
1406                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1407                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1408                 DEV_RX_OFFLOAD_TCP_CKSUM;
1409         dev_info->tx_offload_capa =
1410                 DEV_TX_OFFLOAD_VLAN_INSERT |
1411                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1412                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1413                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1414                 DEV_TX_OFFLOAD_TCP_TSO;
1415
1416         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1417         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1418
1419         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1420                 .rx_thresh = {
1421                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1422                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1423                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1424                 },
1425                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1426                 .rx_drop_en = 0,
1427         };
1428
1429         dev_info->default_txconf = (struct rte_eth_txconf) {
1430                 .tx_thresh = {
1431                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1432                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1433                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1434                 },
1435                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1436                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1437                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1438         };
1439
1440         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1441                 .nb_max = FM10K_MAX_RX_DESC,
1442                 .nb_min = FM10K_MIN_RX_DESC,
1443                 .nb_align = FM10K_MULT_RX_DESC,
1444         };
1445
1446         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1447                 .nb_max = FM10K_MAX_TX_DESC,
1448                 .nb_min = FM10K_MIN_TX_DESC,
1449                 .nb_align = FM10K_MULT_TX_DESC,
1450         };
1451
1452         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1453                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1454                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1455 }
1456
1457 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1458 static const uint32_t *
1459 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1460 {
1461         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1462             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1463                 static uint32_t ptypes[] = {
1464                         /* refers to rx_desc_to_ol_flags() */
1465                         RTE_PTYPE_L2_ETHER,
1466                         RTE_PTYPE_L3_IPV4,
1467                         RTE_PTYPE_L3_IPV4_EXT,
1468                         RTE_PTYPE_L3_IPV6,
1469                         RTE_PTYPE_L3_IPV6_EXT,
1470                         RTE_PTYPE_L4_TCP,
1471                         RTE_PTYPE_L4_UDP,
1472                         RTE_PTYPE_UNKNOWN
1473                 };
1474
1475                 return ptypes;
1476         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1477                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1478                 static uint32_t ptypes_vec[] = {
1479                         /* refers to fm10k_desc_to_pktype_v() */
1480                         RTE_PTYPE_L3_IPV4,
1481                         RTE_PTYPE_L3_IPV4_EXT,
1482                         RTE_PTYPE_L3_IPV6,
1483                         RTE_PTYPE_L3_IPV6_EXT,
1484                         RTE_PTYPE_L4_TCP,
1485                         RTE_PTYPE_L4_UDP,
1486                         RTE_PTYPE_TUNNEL_GENEVE,
1487                         RTE_PTYPE_TUNNEL_NVGRE,
1488                         RTE_PTYPE_TUNNEL_VXLAN,
1489                         RTE_PTYPE_TUNNEL_GRE,
1490                         RTE_PTYPE_UNKNOWN
1491                 };
1492
1493                 return ptypes_vec;
1494         }
1495
1496         return NULL;
1497 }
1498 #else
1499 static const uint32_t *
1500 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1501 {
1502         return NULL;
1503 }
1504 #endif
1505
1506 static int
1507 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1508 {
1509         s32 result;
1510         uint16_t mac_num = 0;
1511         uint32_t vid_idx, vid_bit, mac_index;
1512         struct fm10k_hw *hw;
1513         struct fm10k_macvlan_filter_info *macvlan;
1514         struct rte_eth_dev_data *data = dev->data;
1515
1516         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1518
1519         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1520                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1521                 return -EINVAL;
1522         }
1523
1524         if (vlan_id > ETH_VLAN_ID_MAX) {
1525                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1526                 return -EINVAL;
1527         }
1528
1529         vid_idx = FM10K_VFTA_IDX(vlan_id);
1530         vid_bit = FM10K_VFTA_BIT(vlan_id);
1531         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1532         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1533                 return 0;
1534         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1535         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1536                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1537                         "in the VLAN filter table");
1538                 return -EINVAL;
1539         }
1540
1541         fm10k_mbx_lock(hw);
1542         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1543         fm10k_mbx_unlock(hw);
1544         if (result != FM10K_SUCCESS) {
1545                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1546                 return -EIO;
1547         }
1548
1549         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1550                         (result == FM10K_SUCCESS); mac_index++) {
1551                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1552                         continue;
1553                 if (mac_num > macvlan->mac_num - 1) {
1554                         PMD_INIT_LOG(ERR, "MAC address number "
1555                                         "not match");
1556                         break;
1557                 }
1558                 fm10k_mbx_lock(hw);
1559                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1560                         data->mac_addrs[mac_index].addr_bytes,
1561                         vlan_id, on, 0);
1562                 fm10k_mbx_unlock(hw);
1563                 mac_num++;
1564         }
1565         if (result != FM10K_SUCCESS) {
1566                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1567                 return -EIO;
1568         }
1569
1570         if (on) {
1571                 macvlan->vlan_num++;
1572                 macvlan->vfta[vid_idx] |= vid_bit;
1573         } else {
1574                 macvlan->vlan_num--;
1575                 macvlan->vfta[vid_idx] &= ~vid_bit;
1576         }
1577         return 0;
1578 }
1579
1580 static void
1581 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1582 {
1583         if (mask & ETH_VLAN_STRIP_MASK) {
1584                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1585                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1586                                         "always on in fm10k");
1587         }
1588
1589         if (mask & ETH_VLAN_EXTEND_MASK) {
1590                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1591                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1592                                         "supported in fm10k");
1593         }
1594
1595         if (mask & ETH_VLAN_FILTER_MASK) {
1596                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1597                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1598         }
1599 }
1600
1601 /* Add/Remove a MAC address, and update filters to main VSI */
1602 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1603                 const u8 *mac, bool add, uint32_t pool)
1604 {
1605         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606         struct fm10k_macvlan_filter_info *macvlan;
1607         uint32_t i, j, k;
1608
1609         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1610
1611         if (pool != MAIN_VSI_POOL_NUMBER) {
1612                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1613                         "mac to pool %u", pool);
1614                 return;
1615         }
1616         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1617                 if (!macvlan->vfta[j])
1618                         continue;
1619                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1620                         if (!(macvlan->vfta[j] & (1 << k)))
1621                                 continue;
1622                         if (i + 1 > macvlan->vlan_num) {
1623                                 PMD_INIT_LOG(ERR, "vlan number not match");
1624                                 return;
1625                         }
1626                         fm10k_mbx_lock(hw);
1627                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1628                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1629                         fm10k_mbx_unlock(hw);
1630                         i++;
1631                 }
1632         }
1633 }
1634
1635 /* Add/Remove a MAC address, and update filters to VMDQ */
1636 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1637                 const u8 *mac, bool add, uint32_t pool)
1638 {
1639         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct fm10k_macvlan_filter_info *macvlan;
1641         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1642         uint32_t i;
1643
1644         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1645         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1646
1647         if (pool > macvlan->nb_queue_pools) {
1648                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1649                         " Max pool is %u",
1650                         pool, macvlan->nb_queue_pools);
1651                 return;
1652         }
1653         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1654                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1655                         continue;
1656                 fm10k_mbx_lock(hw);
1657                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1658                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1659                 fm10k_mbx_unlock(hw);
1660         }
1661 }
1662
1663 /* Add/Remove a MAC address, and update filters */
1664 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1665                 const u8 *mac, bool add, uint32_t pool)
1666 {
1667         struct fm10k_macvlan_filter_info *macvlan;
1668
1669         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1670
1671         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1672                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1673         else
1674                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1675
1676         if (add)
1677                 macvlan->mac_num++;
1678         else
1679                 macvlan->mac_num--;
1680 }
1681
1682 /* Add a MAC address, and update filters */
1683 static void
1684 fm10k_macaddr_add(struct rte_eth_dev *dev,
1685                 struct ether_addr *mac_addr,
1686                 uint32_t index,
1687                 uint32_t pool)
1688 {
1689         struct fm10k_macvlan_filter_info *macvlan;
1690
1691         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1692         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1693         macvlan->mac_vmdq_id[index] = pool;
1694 }
1695
1696 /* Remove a MAC address, and update filters */
1697 static void
1698 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1699 {
1700         struct rte_eth_dev_data *data = dev->data;
1701         struct fm10k_macvlan_filter_info *macvlan;
1702
1703         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1704         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1705                         FALSE, macvlan->mac_vmdq_id[index]);
1706         macvlan->mac_vmdq_id[index] = 0;
1707 }
1708
1709 static inline int
1710 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1711 {
1712         if ((request < min) || (request > max) || ((request % mult) != 0))
1713                 return -1;
1714         else
1715                 return 0;
1716 }
1717
1718
1719 static inline int
1720 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1721 {
1722         if ((request < min) || (request > max) || ((div % request) != 0))
1723                 return -1;
1724         else
1725                 return 0;
1726 }
1727
1728 static inline int
1729 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1730 {
1731         uint16_t rx_free_thresh;
1732
1733         if (conf->rx_free_thresh == 0)
1734                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1735         else
1736                 rx_free_thresh = conf->rx_free_thresh;
1737
1738         /* make sure the requested threshold satisfies the constraints */
1739         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1740                         FM10K_RX_FREE_THRESH_MAX(q),
1741                         FM10K_RX_FREE_THRESH_DIV(q),
1742                         rx_free_thresh)) {
1743                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1744                         "less than or equal to %u, "
1745                         "greater than or equal to %u, "
1746                         "and a divisor of %u",
1747                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1748                         FM10K_RX_FREE_THRESH_MIN(q),
1749                         FM10K_RX_FREE_THRESH_DIV(q));
1750                 return -EINVAL;
1751         }
1752
1753         q->alloc_thresh = rx_free_thresh;
1754         q->drop_en = conf->rx_drop_en;
1755         q->rx_deferred_start = conf->rx_deferred_start;
1756
1757         return 0;
1758 }
1759
1760 /*
1761  * Hardware requires specific alignment for Rx packet buffers. At
1762  * least one of the following two conditions must be satisfied.
1763  *  1. Address is 512B aligned
1764  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1765  *
1766  * As such, the driver may need to adjust the DMA address within the
1767  * buffer by up to 512B.
1768  *
1769  * return 1 if the element size is valid, otherwise return 0.
1770  */
1771 static int
1772 mempool_element_size_valid(struct rte_mempool *mp)
1773 {
1774         uint32_t min_size;
1775
1776         /* elt_size includes mbuf header and headroom */
1777         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1778                         RTE_PKTMBUF_HEADROOM;
1779
1780         /* account for up to 512B of alignment */
1781         min_size -= FM10K_RX_DATABUF_ALIGN;
1782
1783         /* sanity check for overflow */
1784         if (min_size > mp->elt_size)
1785                 return 0;
1786
1787         /* size is valid */
1788         return 1;
1789 }
1790
1791 static int
1792 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1793         uint16_t nb_desc, unsigned int socket_id,
1794         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1795 {
1796         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1797         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1798         struct fm10k_rx_queue *q;
1799         const struct rte_memzone *mz;
1800
1801         PMD_INIT_FUNC_TRACE();
1802
1803         /* make sure the mempool element size can account for alignment. */
1804         if (!mempool_element_size_valid(mp)) {
1805                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1806                 return -EINVAL;
1807         }
1808
1809         /* make sure a valid number of descriptors have been requested */
1810         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1811                                 FM10K_MULT_RX_DESC, nb_desc)) {
1812                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1813                         "less than or equal to %"PRIu32", "
1814                         "greater than or equal to %u, "
1815                         "and a multiple of %u",
1816                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1817                         FM10K_MULT_RX_DESC);
1818                 return -EINVAL;
1819         }
1820
1821         /*
1822          * if this queue existed already, free the associated memory. The
1823          * queue cannot be reused in case we need to allocate memory on
1824          * different socket than was previously used.
1825          */
1826         if (dev->data->rx_queues[queue_id] != NULL) {
1827                 rx_queue_free(dev->data->rx_queues[queue_id]);
1828                 dev->data->rx_queues[queue_id] = NULL;
1829         }
1830
1831         /* allocate memory for the queue structure */
1832         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1833                                 socket_id);
1834         if (q == NULL) {
1835                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1836                 return -ENOMEM;
1837         }
1838
1839         /* setup queue */
1840         q->mp = mp;
1841         q->nb_desc = nb_desc;
1842         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1843         q->port_id = dev->data->port_id;
1844         q->queue_id = queue_id;
1845         q->tail_ptr = (volatile uint32_t *)
1846                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1847         if (handle_rxconf(q, conf))
1848                 return -EINVAL;
1849
1850         /* allocate memory for the software ring */
1851         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1852                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1853                         RTE_CACHE_LINE_SIZE, socket_id);
1854         if (q->sw_ring == NULL) {
1855                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1856                 rte_free(q);
1857                 return -ENOMEM;
1858         }
1859
1860         /*
1861          * allocate memory for the hardware descriptor ring. A memzone large
1862          * enough to hold the maximum ring size is requested to allow for
1863          * resizing in later calls to the queue setup function.
1864          */
1865         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1866                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1867                                       socket_id);
1868         if (mz == NULL) {
1869                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1870                 rte_free(q->sw_ring);
1871                 rte_free(q);
1872                 return -ENOMEM;
1873         }
1874         q->hw_ring = mz->addr;
1875         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1876
1877         /* Check if number of descs satisfied Vector requirement */
1878         if (!rte_is_power_of_2(nb_desc)) {
1879                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1880                                     "preconditions - canceling the feature for "
1881                                     "the whole port[%d]",
1882                              q->queue_id, q->port_id);
1883                 dev_info->rx_vec_allowed = false;
1884         } else
1885                 fm10k_rxq_vec_setup(q);
1886
1887         dev->data->rx_queues[queue_id] = q;
1888         return 0;
1889 }
1890
1891 static void
1892 fm10k_rx_queue_release(void *queue)
1893 {
1894         PMD_INIT_FUNC_TRACE();
1895
1896         rx_queue_free(queue);
1897 }
1898
1899 static inline int
1900 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1901 {
1902         uint16_t tx_free_thresh;
1903         uint16_t tx_rs_thresh;
1904
1905         /* constraint MACROs require that tx_free_thresh is configured
1906          * before tx_rs_thresh */
1907         if (conf->tx_free_thresh == 0)
1908                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1909         else
1910                 tx_free_thresh = conf->tx_free_thresh;
1911
1912         /* make sure the requested threshold satisfies the constraints */
1913         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1914                         FM10K_TX_FREE_THRESH_MAX(q),
1915                         FM10K_TX_FREE_THRESH_DIV(q),
1916                         tx_free_thresh)) {
1917                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1918                         "less than or equal to %u, "
1919                         "greater than or equal to %u, "
1920                         "and a divisor of %u",
1921                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1922                         FM10K_TX_FREE_THRESH_MIN(q),
1923                         FM10K_TX_FREE_THRESH_DIV(q));
1924                 return -EINVAL;
1925         }
1926
1927         q->free_thresh = tx_free_thresh;
1928
1929         if (conf->tx_rs_thresh == 0)
1930                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1931         else
1932                 tx_rs_thresh = conf->tx_rs_thresh;
1933
1934         q->tx_deferred_start = conf->tx_deferred_start;
1935
1936         /* make sure the requested threshold satisfies the constraints */
1937         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1938                         FM10K_TX_RS_THRESH_MAX(q),
1939                         FM10K_TX_RS_THRESH_DIV(q),
1940                         tx_rs_thresh)) {
1941                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1942                         "less than or equal to %u, "
1943                         "greater than or equal to %u, "
1944                         "and a divisor of %u",
1945                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1946                         FM10K_TX_RS_THRESH_MIN(q),
1947                         FM10K_TX_RS_THRESH_DIV(q));
1948                 return -EINVAL;
1949         }
1950
1951         q->rs_thresh = tx_rs_thresh;
1952
1953         return 0;
1954 }
1955
1956 static int
1957 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1958         uint16_t nb_desc, unsigned int socket_id,
1959         const struct rte_eth_txconf *conf)
1960 {
1961         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct fm10k_tx_queue *q;
1963         const struct rte_memzone *mz;
1964
1965         PMD_INIT_FUNC_TRACE();
1966
1967         /* make sure a valid number of descriptors have been requested */
1968         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1969                                 FM10K_MULT_TX_DESC, nb_desc)) {
1970                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1971                         "less than or equal to %"PRIu32", "
1972                         "greater than or equal to %u, "
1973                         "and a multiple of %u",
1974                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1975                         FM10K_MULT_TX_DESC);
1976                 return -EINVAL;
1977         }
1978
1979         /*
1980          * if this queue existed already, free the associated memory. The
1981          * queue cannot be reused in case we need to allocate memory on
1982          * different socket than was previously used.
1983          */
1984         if (dev->data->tx_queues[queue_id] != NULL) {
1985                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1986
1987                 tx_queue_free(txq);
1988                 dev->data->tx_queues[queue_id] = NULL;
1989         }
1990
1991         /* allocate memory for the queue structure */
1992         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1993                                 socket_id);
1994         if (q == NULL) {
1995                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1996                 return -ENOMEM;
1997         }
1998
1999         /* setup queue */
2000         q->nb_desc = nb_desc;
2001         q->port_id = dev->data->port_id;
2002         q->queue_id = queue_id;
2003         q->txq_flags = conf->txq_flags;
2004         q->ops = &def_txq_ops;
2005         q->tail_ptr = (volatile uint32_t *)
2006                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2007         if (handle_txconf(q, conf))
2008                 return -EINVAL;
2009
2010         /* allocate memory for the software ring */
2011         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2012                                         nb_desc * sizeof(struct rte_mbuf *),
2013                                         RTE_CACHE_LINE_SIZE, socket_id);
2014         if (q->sw_ring == NULL) {
2015                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2016                 rte_free(q);
2017                 return -ENOMEM;
2018         }
2019
2020         /*
2021          * allocate memory for the hardware descriptor ring. A memzone large
2022          * enough to hold the maximum ring size is requested to allow for
2023          * resizing in later calls to the queue setup function.
2024          */
2025         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2026                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2027                                       socket_id);
2028         if (mz == NULL) {
2029                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2030                 rte_free(q->sw_ring);
2031                 rte_free(q);
2032                 return -ENOMEM;
2033         }
2034         q->hw_ring = mz->addr;
2035         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2036
2037         /*
2038          * allocate memory for the RS bit tracker. Enough slots to hold the
2039          * descriptor index for each RS bit needing to be set are required.
2040          */
2041         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2042                                 ((nb_desc + 1) / q->rs_thresh) *
2043                                 sizeof(uint16_t),
2044                                 RTE_CACHE_LINE_SIZE, socket_id);
2045         if (q->rs_tracker.list == NULL) {
2046                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2047                 rte_free(q->sw_ring);
2048                 rte_free(q);
2049                 return -ENOMEM;
2050         }
2051
2052         dev->data->tx_queues[queue_id] = q;
2053         return 0;
2054 }
2055
2056 static void
2057 fm10k_tx_queue_release(void *queue)
2058 {
2059         struct fm10k_tx_queue *q = queue;
2060         PMD_INIT_FUNC_TRACE();
2061
2062         tx_queue_free(q);
2063 }
2064
2065 static int
2066 fm10k_reta_update(struct rte_eth_dev *dev,
2067                         struct rte_eth_rss_reta_entry64 *reta_conf,
2068                         uint16_t reta_size)
2069 {
2070         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2071         uint16_t i, j, idx, shift;
2072         uint8_t mask;
2073         uint32_t reta;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         if (reta_size > FM10K_MAX_RSS_INDICES) {
2078                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2079                         "(%d) doesn't match the number hardware can supported "
2080                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2081                 return -EINVAL;
2082         }
2083
2084         /*
2085          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2086          * 128-entries in 32 registers
2087          */
2088         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2089                 idx = i / RTE_RETA_GROUP_SIZE;
2090                 shift = i % RTE_RETA_GROUP_SIZE;
2091                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2092                                 BIT_MASK_PER_UINT32);
2093                 if (mask == 0)
2094                         continue;
2095
2096                 reta = 0;
2097                 if (mask != BIT_MASK_PER_UINT32)
2098                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2099
2100                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2101                         if (mask & (0x1 << j)) {
2102                                 if (mask != 0xF)
2103                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2104                                 reta |= reta_conf[idx].reta[shift + j] <<
2105                                                 (CHAR_BIT * j);
2106                         }
2107                 }
2108                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2109         }
2110
2111         return 0;
2112 }
2113
2114 static int
2115 fm10k_reta_query(struct rte_eth_dev *dev,
2116                         struct rte_eth_rss_reta_entry64 *reta_conf,
2117                         uint16_t reta_size)
2118 {
2119         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         uint16_t i, j, idx, shift;
2121         uint8_t mask;
2122         uint32_t reta;
2123
2124         PMD_INIT_FUNC_TRACE();
2125
2126         if (reta_size < FM10K_MAX_RSS_INDICES) {
2127                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2128                         "(%d) doesn't match the number hardware can supported "
2129                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2130                 return -EINVAL;
2131         }
2132
2133         /*
2134          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2135          * 128-entries in 32 registers
2136          */
2137         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2138                 idx = i / RTE_RETA_GROUP_SIZE;
2139                 shift = i % RTE_RETA_GROUP_SIZE;
2140                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2141                                 BIT_MASK_PER_UINT32);
2142                 if (mask == 0)
2143                         continue;
2144
2145                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2146                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2147                         if (mask & (0x1 << j))
2148                                 reta_conf[idx].reta[shift + j] = ((reta >>
2149                                         CHAR_BIT * j) & UINT8_MAX);
2150                 }
2151         }
2152
2153         return 0;
2154 }
2155
2156 static int
2157 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2158         struct rte_eth_rss_conf *rss_conf)
2159 {
2160         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2161         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2162         uint32_t mrqc;
2163         uint64_t hf = rss_conf->rss_hf;
2164         int i;
2165
2166         PMD_INIT_FUNC_TRACE();
2167
2168         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2169                 FM10K_RSSRK_ENTRIES_PER_REG)
2170                 return -EINVAL;
2171
2172         if (hf == 0)
2173                 return -EINVAL;
2174
2175         mrqc = 0;
2176         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2177         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2178         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2179         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2180         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2181         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2182         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2183         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2185
2186         /* If the mapping doesn't fit any supported, return */
2187         if (mrqc == 0)
2188                 return -EINVAL;
2189
2190         if (key != NULL)
2191                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2192                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2193
2194         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2195
2196         return 0;
2197 }
2198
2199 static int
2200 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2201         struct rte_eth_rss_conf *rss_conf)
2202 {
2203         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2205         uint32_t mrqc;
2206         uint64_t hf;
2207         int i;
2208
2209         PMD_INIT_FUNC_TRACE();
2210
2211         if (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2212                                 FM10K_RSSRK_ENTRIES_PER_REG)
2213                 return -EINVAL;
2214
2215         if (key != NULL)
2216                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2217                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2218
2219         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2220         hf = 0;
2221         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2222         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2223         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2224         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2225         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2226         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2227         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2228         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2229         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2230
2231         rss_conf->rss_hf = hf;
2232
2233         return 0;
2234 }
2235
2236 static void
2237 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2238 {
2239         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2241
2242         /* Bind all local non-queue interrupt to vector 0 */
2243         int_map |= FM10K_MISC_VEC_ID;
2244
2245         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2246         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2247         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2248         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2249         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2250         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2251
2252         /* Enable misc causes */
2253         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2254                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2255                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2256                                 FM10K_EIMR_ENABLE(MAILBOX) |
2257                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2258                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2259                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2260                                 FM10K_EIMR_ENABLE(VFLR));
2261
2262         /* Enable ITR 0 */
2263         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2264                                         FM10K_ITR_MASK_CLEAR);
2265         FM10K_WRITE_FLUSH(hw);
2266 }
2267
2268 static void
2269 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2270 {
2271         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2273
2274         int_map |= FM10K_MISC_VEC_ID;
2275
2276         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2277         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2278         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2279         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2280         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2281         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2282
2283         /* Disable misc causes */
2284         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2285                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2286                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2287                                 FM10K_EIMR_DISABLE(MAILBOX) |
2288                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2289                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2290                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2291                                 FM10K_EIMR_DISABLE(VFLR));
2292
2293         /* Disable ITR 0 */
2294         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2295         FM10K_WRITE_FLUSH(hw);
2296 }
2297
2298 static void
2299 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2300 {
2301         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2303
2304         /* Bind all local non-queue interrupt to vector 0 */
2305         int_map |= FM10K_MISC_VEC_ID;
2306
2307         /* Only INT 0 available, other 15 are reserved. */
2308         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2309
2310         /* Enable ITR 0 */
2311         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2312                                         FM10K_ITR_MASK_CLEAR);
2313         FM10K_WRITE_FLUSH(hw);
2314 }
2315
2316 static void
2317 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2318 {
2319         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2321
2322         int_map |= FM10K_MISC_VEC_ID;
2323
2324         /* Only INT 0 available, other 15 are reserved. */
2325         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2326
2327         /* Disable ITR 0 */
2328         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2329         FM10K_WRITE_FLUSH(hw);
2330 }
2331
2332 static int
2333 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2334 {
2335         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336
2337         /* Enable ITR */
2338         if (hw->mac.type == fm10k_mac_pf)
2339                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2340                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2341         else
2342                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2343                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2344         rte_intr_enable(&dev->pci_dev->intr_handle);
2345         return 0;
2346 }
2347
2348 static int
2349 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2350 {
2351         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352
2353         /* Disable ITR */
2354         if (hw->mac.type == fm10k_mac_pf)
2355                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)),
2356                         FM10K_ITR_MASK_SET);
2357         else
2358                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)),
2359                         FM10K_ITR_MASK_SET);
2360         return 0;
2361 }
2362
2363 static int
2364 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2365 {
2366         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2368         uint32_t intr_vector, vec;
2369         uint16_t queue_id;
2370         int result = 0;
2371
2372         /* fm10k needs one separate interrupt for mailbox,
2373          * so only drivers which support multiple interrupt vectors
2374          * e.g. vfio-pci can work for fm10k interrupt mode
2375          */
2376         if (!rte_intr_cap_multiple(intr_handle) ||
2377                         dev->data->dev_conf.intr_conf.rxq == 0)
2378                 return result;
2379
2380         intr_vector = dev->data->nb_rx_queues;
2381
2382         /* disable interrupt first */
2383         rte_intr_disable(&dev->pci_dev->intr_handle);
2384         if (hw->mac.type == fm10k_mac_pf)
2385                 fm10k_dev_disable_intr_pf(dev);
2386         else
2387                 fm10k_dev_disable_intr_vf(dev);
2388
2389         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2390                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2391                 result = -EIO;
2392         }
2393
2394         if (rte_intr_dp_is_en(intr_handle) && !result) {
2395                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2396                         dev->data->nb_rx_queues * sizeof(int), 0);
2397                 if (intr_handle->intr_vec) {
2398                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2399                                         queue_id < dev->data->nb_rx_queues;
2400                                         queue_id++) {
2401                                 intr_handle->intr_vec[queue_id] = vec;
2402                                 if (vec < intr_handle->nb_efd - 1
2403                                                 + FM10K_RX_VEC_START)
2404                                         vec++;
2405                         }
2406                 } else {
2407                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2408                                 " intr_vec", dev->data->nb_rx_queues);
2409                         rte_intr_efd_disable(intr_handle);
2410                         result = -ENOMEM;
2411                 }
2412         }
2413
2414         if (hw->mac.type == fm10k_mac_pf)
2415                 fm10k_dev_enable_intr_pf(dev);
2416         else
2417                 fm10k_dev_enable_intr_vf(dev);
2418         rte_intr_enable(&dev->pci_dev->intr_handle);
2419         hw->mac.ops.update_int_moderator(hw);
2420         return result;
2421 }
2422
2423 static int
2424 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2425 {
2426         struct fm10k_fault fault;
2427         int err;
2428         const char *estr = "Unknown error";
2429
2430         /* Process PCA fault */
2431         if (eicr & FM10K_EICR_PCA_FAULT) {
2432                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2433                 if (err)
2434                         goto error;
2435                 switch (fault.type) {
2436                 case PCA_NO_FAULT:
2437                         estr = "PCA_NO_FAULT"; break;
2438                 case PCA_UNMAPPED_ADDR:
2439                         estr = "PCA_UNMAPPED_ADDR"; break;
2440                 case PCA_BAD_QACCESS_PF:
2441                         estr = "PCA_BAD_QACCESS_PF"; break;
2442                 case PCA_BAD_QACCESS_VF:
2443                         estr = "PCA_BAD_QACCESS_VF"; break;
2444                 case PCA_MALICIOUS_REQ:
2445                         estr = "PCA_MALICIOUS_REQ"; break;
2446                 case PCA_POISONED_TLP:
2447                         estr = "PCA_POISONED_TLP"; break;
2448                 case PCA_TLP_ABORT:
2449                         estr = "PCA_TLP_ABORT"; break;
2450                 default:
2451                         goto error;
2452                 }
2453                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2454                         estr, fault.func ? "VF" : "PF", fault.func,
2455                         fault.address, fault.specinfo);
2456         }
2457
2458         /* Process THI fault */
2459         if (eicr & FM10K_EICR_THI_FAULT) {
2460                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2461                 if (err)
2462                         goto error;
2463                 switch (fault.type) {
2464                 case THI_NO_FAULT:
2465                         estr = "THI_NO_FAULT"; break;
2466                 case THI_MAL_DIS_Q_FAULT:
2467                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2468                 default:
2469                         goto error;
2470                 }
2471                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2472                         estr, fault.func ? "VF" : "PF", fault.func,
2473                         fault.address, fault.specinfo);
2474         }
2475
2476         /* Process FUM fault */
2477         if (eicr & FM10K_EICR_FUM_FAULT) {
2478                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2479                 if (err)
2480                         goto error;
2481                 switch (fault.type) {
2482                 case FUM_NO_FAULT:
2483                         estr = "FUM_NO_FAULT"; break;
2484                 case FUM_UNMAPPED_ADDR:
2485                         estr = "FUM_UNMAPPED_ADDR"; break;
2486                 case FUM_POISONED_TLP:
2487                         estr = "FUM_POISONED_TLP"; break;
2488                 case FUM_BAD_VF_QACCESS:
2489                         estr = "FUM_BAD_VF_QACCESS"; break;
2490                 case FUM_ADD_DECODE_ERR:
2491                         estr = "FUM_ADD_DECODE_ERR"; break;
2492                 case FUM_RO_ERROR:
2493                         estr = "FUM_RO_ERROR"; break;
2494                 case FUM_QPRC_CRC_ERROR:
2495                         estr = "FUM_QPRC_CRC_ERROR"; break;
2496                 case FUM_CSR_TIMEOUT:
2497                         estr = "FUM_CSR_TIMEOUT"; break;
2498                 case FUM_INVALID_TYPE:
2499                         estr = "FUM_INVALID_TYPE"; break;
2500                 case FUM_INVALID_LENGTH:
2501                         estr = "FUM_INVALID_LENGTH"; break;
2502                 case FUM_INVALID_BE:
2503                         estr = "FUM_INVALID_BE"; break;
2504                 case FUM_INVALID_ALIGN:
2505                         estr = "FUM_INVALID_ALIGN"; break;
2506                 default:
2507                         goto error;
2508                 }
2509                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2510                         estr, fault.func ? "VF" : "PF", fault.func,
2511                         fault.address, fault.specinfo);
2512         }
2513
2514         return 0;
2515 error:
2516         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2517         return err;
2518 }
2519
2520 /**
2521  * PF interrupt handler triggered by NIC for handling specific interrupt.
2522  *
2523  * @param handle
2524  *  Pointer to interrupt handle.
2525  * @param param
2526  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2527  *
2528  * @return
2529  *  void
2530  */
2531 static void
2532 fm10k_dev_interrupt_handler_pf(
2533                         __rte_unused struct rte_intr_handle *handle,
2534                         void *param)
2535 {
2536         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2537         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t cause, status;
2539
2540         if (hw->mac.type != fm10k_mac_pf)
2541                 return;
2542
2543         cause = FM10K_READ_REG(hw, FM10K_EICR);
2544
2545         /* Handle PCI fault cases */
2546         if (cause & FM10K_EICR_FAULT_MASK) {
2547                 PMD_INIT_LOG(ERR, "INT: find fault!");
2548                 fm10k_dev_handle_fault(hw, cause);
2549         }
2550
2551         /* Handle switch up/down */
2552         if (cause & FM10K_EICR_SWITCHNOTREADY)
2553                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2554
2555         if (cause & FM10K_EICR_SWITCHREADY)
2556                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2557
2558         /* Handle mailbox message */
2559         fm10k_mbx_lock(hw);
2560         hw->mbx.ops.process(hw, &hw->mbx);
2561         fm10k_mbx_unlock(hw);
2562
2563         /* Handle SRAM error */
2564         if (cause & FM10K_EICR_SRAMERROR) {
2565                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2566
2567                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2568                 /* Write to clear pending bits */
2569                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2570
2571                 /* Todo: print out error message after shared code  updates */
2572         }
2573
2574         /* Clear these 3 events if having any */
2575         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2576                  FM10K_EICR_SWITCHREADY;
2577         if (cause)
2578                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2579
2580         /* Re-enable interrupt from device side */
2581         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2582                                         FM10K_ITR_MASK_CLEAR);
2583         /* Re-enable interrupt from host side */
2584         rte_intr_enable(&(dev->pci_dev->intr_handle));
2585 }
2586
2587 /**
2588  * VF interrupt handler triggered by NIC for handling specific interrupt.
2589  *
2590  * @param handle
2591  *  Pointer to interrupt handle.
2592  * @param param
2593  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2594  *
2595  * @return
2596  *  void
2597  */
2598 static void
2599 fm10k_dev_interrupt_handler_vf(
2600                         __rte_unused struct rte_intr_handle *handle,
2601                         void *param)
2602 {
2603         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2604         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605
2606         if (hw->mac.type != fm10k_mac_vf)
2607                 return;
2608
2609         /* Handle mailbox message if lock is acquired */
2610         fm10k_mbx_lock(hw);
2611         hw->mbx.ops.process(hw, &hw->mbx);
2612         fm10k_mbx_unlock(hw);
2613
2614         /* Re-enable interrupt from device side */
2615         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2616                                         FM10K_ITR_MASK_CLEAR);
2617         /* Re-enable interrupt from host side */
2618         rte_intr_enable(&(dev->pci_dev->intr_handle));
2619 }
2620
2621 /* Mailbox message handler in VF */
2622 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2623         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2624         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2625         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2626         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2627 };
2628
2629 static int
2630 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2631 {
2632         int err = 0;
2633
2634         /* Initialize mailbox lock */
2635         fm10k_mbx_initlock(hw);
2636
2637         /* Replace default message handler with new ones */
2638         if (hw->mac.type == fm10k_mac_vf)
2639                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2640
2641         if (err) {
2642                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2643                                 err);
2644                 return err;
2645         }
2646         /* Connect to SM for PF device or PF for VF device */
2647         return hw->mbx.ops.connect(hw, &hw->mbx);
2648 }
2649
2650 static void
2651 fm10k_close_mbx_service(struct fm10k_hw *hw)
2652 {
2653         /* Disconnect from SM for PF device or PF for VF device */
2654         hw->mbx.ops.disconnect(hw, &hw->mbx);
2655 }
2656
2657 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2658         .dev_configure          = fm10k_dev_configure,
2659         .dev_start              = fm10k_dev_start,
2660         .dev_stop               = fm10k_dev_stop,
2661         .dev_close              = fm10k_dev_close,
2662         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2663         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2664         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2665         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2666         .stats_get              = fm10k_stats_get,
2667         .xstats_get             = fm10k_xstats_get,
2668         .xstats_get_names       = fm10k_xstats_get_names,
2669         .stats_reset            = fm10k_stats_reset,
2670         .xstats_reset           = fm10k_stats_reset,
2671         .link_update            = fm10k_link_update,
2672         .dev_infos_get          = fm10k_dev_infos_get,
2673         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2674         .vlan_filter_set        = fm10k_vlan_filter_set,
2675         .vlan_offload_set       = fm10k_vlan_offload_set,
2676         .mac_addr_add           = fm10k_macaddr_add,
2677         .mac_addr_remove        = fm10k_macaddr_remove,
2678         .rx_queue_start         = fm10k_dev_rx_queue_start,
2679         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2680         .tx_queue_start         = fm10k_dev_tx_queue_start,
2681         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2682         .rx_queue_setup         = fm10k_rx_queue_setup,
2683         .rx_queue_release       = fm10k_rx_queue_release,
2684         .tx_queue_setup         = fm10k_tx_queue_setup,
2685         .tx_queue_release       = fm10k_tx_queue_release,
2686         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2687         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2688         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2689         .reta_update            = fm10k_reta_update,
2690         .reta_query             = fm10k_reta_query,
2691         .rss_hash_update        = fm10k_rss_hash_update,
2692         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2693 };
2694
2695 static int ftag_check_handler(__rte_unused const char *key,
2696                 const char *value, __rte_unused void *opaque)
2697 {
2698         if (strcmp(value, "1"))
2699                 return -1;
2700
2701         return 0;
2702 }
2703
2704 static int
2705 fm10k_check_ftag(struct rte_devargs *devargs)
2706 {
2707         struct rte_kvargs *kvlist;
2708         const char *ftag_key = "enable_ftag";
2709
2710         if (devargs == NULL)
2711                 return 0;
2712
2713         kvlist = rte_kvargs_parse(devargs->args, NULL);
2714         if (kvlist == NULL)
2715                 return 0;
2716
2717         if (!rte_kvargs_count(kvlist, ftag_key)) {
2718                 rte_kvargs_free(kvlist);
2719                 return 0;
2720         }
2721         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2722         if (rte_kvargs_process(kvlist, ftag_key,
2723                                 ftag_check_handler, NULL) < 0) {
2724                 rte_kvargs_free(kvlist);
2725                 return 0;
2726         }
2727         rte_kvargs_free(kvlist);
2728
2729         return 1;
2730 }
2731
2732 static void __attribute__((cold))
2733 fm10k_set_tx_function(struct rte_eth_dev *dev)
2734 {
2735         struct fm10k_tx_queue *txq;
2736         int i;
2737         int use_sse = 1;
2738         uint16_t tx_ftag_en = 0;
2739
2740         if (fm10k_check_ftag(dev->pci_dev->devargs))
2741                 tx_ftag_en = 1;
2742
2743         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2744                 txq = dev->data->tx_queues[i];
2745                 txq->tx_ftag_en = tx_ftag_en;
2746                 /* Check if Vector Tx is satisfied */
2747                 if (fm10k_tx_vec_condition_check(txq)) {
2748                         use_sse = 0;
2749                         break;
2750                 }
2751         }
2752
2753         if (use_sse) {
2754                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2755                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2756                         txq = dev->data->tx_queues[i];
2757                         fm10k_txq_vec_setup(txq);
2758                 }
2759                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2760         } else {
2761                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2762                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2763         }
2764 }
2765
2766 static void __attribute__((cold))
2767 fm10k_set_rx_function(struct rte_eth_dev *dev)
2768 {
2769         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2770         uint16_t i, rx_using_sse;
2771         uint16_t rx_ftag_en = 0;
2772
2773         if (fm10k_check_ftag(dev->pci_dev->devargs))
2774                 rx_ftag_en = 1;
2775
2776         /* In order to allow Vector Rx there are a few configuration
2777          * conditions to be met.
2778          */
2779         if (!fm10k_rx_vec_condition_check(dev) &&
2780                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2781                 if (dev->data->scattered_rx)
2782                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2783                 else
2784                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2785         } else if (dev->data->scattered_rx)
2786                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2787         else
2788                 dev->rx_pkt_burst = fm10k_recv_pkts;
2789
2790         rx_using_sse =
2791                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2792                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2793
2794         if (rx_using_sse)
2795                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2796         else
2797                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2798
2799         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2800                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2801
2802                 rxq->rx_using_sse = rx_using_sse;
2803                 rxq->rx_ftag_en = rx_ftag_en;
2804         }
2805 }
2806
2807 static void
2808 fm10k_params_init(struct rte_eth_dev *dev)
2809 {
2810         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2812
2813         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2814          * there is no way to get link status without reading BAR4.  Until this
2815          * works, assume we have maximum bandwidth.
2816          * @todo - fix bus info
2817          */
2818         hw->bus_caps.speed = fm10k_bus_speed_8000;
2819         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2820         hw->bus_caps.payload = fm10k_bus_payload_512;
2821         hw->bus.speed = fm10k_bus_speed_8000;
2822         hw->bus.width = fm10k_bus_width_pcie_x8;
2823         hw->bus.payload = fm10k_bus_payload_256;
2824
2825         info->rx_vec_allowed = true;
2826 }
2827
2828 static int
2829 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2830 {
2831         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         int diag, i;
2833         struct fm10k_macvlan_filter_info *macvlan;
2834
2835         PMD_INIT_FUNC_TRACE();
2836
2837         dev->dev_ops = &fm10k_eth_dev_ops;
2838         dev->rx_pkt_burst = &fm10k_recv_pkts;
2839         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2840
2841         /* only initialize in the primary process */
2842         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2843                 return 0;
2844
2845         rte_eth_copy_pci_info(dev, dev->pci_dev);
2846
2847         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2848         memset(macvlan, 0, sizeof(*macvlan));
2849         /* Vendor and Device ID need to be set before init of shared code */
2850         memset(hw, 0, sizeof(*hw));
2851         hw->device_id = dev->pci_dev->id.device_id;
2852         hw->vendor_id = dev->pci_dev->id.vendor_id;
2853         hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
2854         hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
2855         hw->revision_id = 0;
2856         hw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;
2857         if (hw->hw_addr == NULL) {
2858                 PMD_INIT_LOG(ERR, "Bad mem resource."
2859                         " Try to blacklist unused devices.");
2860                 return -EIO;
2861         }
2862
2863         /* Store fm10k_adapter pointer */
2864         hw->back = dev->data->dev_private;
2865
2866         /* Initialize the shared code */
2867         diag = fm10k_init_shared_code(hw);
2868         if (diag != FM10K_SUCCESS) {
2869                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2870                 return -EIO;
2871         }
2872
2873         /* Initialize parameters */
2874         fm10k_params_init(dev);
2875
2876         /* Initialize the hw */
2877         diag = fm10k_init_hw(hw);
2878         if (diag != FM10K_SUCCESS) {
2879                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2880                 return -EIO;
2881         }
2882
2883         /* Initialize MAC address(es) */
2884         dev->data->mac_addrs = rte_zmalloc("fm10k",
2885                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2886         if (dev->data->mac_addrs == NULL) {
2887                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2888                 return -ENOMEM;
2889         }
2890
2891         diag = fm10k_read_mac_addr(hw);
2892
2893         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2894                         &dev->data->mac_addrs[0]);
2895
2896         if (diag != FM10K_SUCCESS ||
2897                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2898
2899                 /* Generate a random addr */
2900                 eth_random_addr(hw->mac.addr);
2901                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2902                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2903                 &dev->data->mac_addrs[0]);
2904         }
2905
2906         /* Reset the hw statistics */
2907         fm10k_stats_reset(dev);
2908
2909         /* Reset the hw */
2910         diag = fm10k_reset_hw(hw);
2911         if (diag != FM10K_SUCCESS) {
2912                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2913                 return -EIO;
2914         }
2915
2916         /* Setup mailbox service */
2917         diag = fm10k_setup_mbx_service(hw);
2918         if (diag != FM10K_SUCCESS) {
2919                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2920                 return -EIO;
2921         }
2922
2923         /*PF/VF has different interrupt handling mechanism */
2924         if (hw->mac.type == fm10k_mac_pf) {
2925                 /* register callback func to eal lib */
2926                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2927                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2928
2929                 /* enable MISC interrupt */
2930                 fm10k_dev_enable_intr_pf(dev);
2931         } else { /* VF */
2932                 rte_intr_callback_register(&(dev->pci_dev->intr_handle),
2933                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2934
2935                 fm10k_dev_enable_intr_vf(dev);
2936         }
2937
2938         /* Enable intr after callback registered */
2939         rte_intr_enable(&(dev->pci_dev->intr_handle));
2940
2941         hw->mac.ops.update_int_moderator(hw);
2942
2943         /* Make sure Switch Manager is ready before going forward. */
2944         if (hw->mac.type == fm10k_mac_pf) {
2945                 int switch_ready = 0;
2946
2947                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2948                         fm10k_mbx_lock(hw);
2949                         hw->mac.ops.get_host_state(hw, &switch_ready);
2950                         fm10k_mbx_unlock(hw);
2951                         if (switch_ready)
2952                                 break;
2953                         /* Delay some time to acquire async LPORT_MAP info. */
2954                         rte_delay_us(WAIT_SWITCH_MSG_US);
2955                 }
2956
2957                 if (switch_ready == 0) {
2958                         PMD_INIT_LOG(ERR, "switch is not ready");
2959                         return -1;
2960                 }
2961         }
2962
2963         /*
2964          * Below function will trigger operations on mailbox, acquire lock to
2965          * avoid race condition from interrupt handler. Operations on mailbox
2966          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2967          * will handle and generate an interrupt to our side. Then,  FIFO in
2968          * mailbox will be touched.
2969          */
2970         fm10k_mbx_lock(hw);
2971         /* Enable port first */
2972         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2973                                         MAX_LPORT_NUM, 1);
2974
2975         /* Set unicast mode by default. App can change to other mode in other
2976          * API func.
2977          */
2978         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2979                                         FM10K_XCAST_MODE_NONE);
2980
2981         fm10k_mbx_unlock(hw);
2982
2983         /* Make sure default VID is ready before going forward. */
2984         if (hw->mac.type == fm10k_mac_pf) {
2985                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2986                         if (hw->mac.default_vid)
2987                                 break;
2988                         /* Delay some time to acquire async port VLAN info. */
2989                         rte_delay_us(WAIT_SWITCH_MSG_US);
2990                 }
2991
2992                 if (!hw->mac.default_vid) {
2993                         PMD_INIT_LOG(ERR, "default VID is not ready");
2994                         return -1;
2995                 }
2996         }
2997
2998         /* Add default mac address */
2999         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3000                 MAIN_VSI_POOL_NUMBER);
3001
3002         return 0;
3003 }
3004
3005 static int
3006 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3007 {
3008         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009
3010         PMD_INIT_FUNC_TRACE();
3011
3012         /* only uninitialize in the primary process */
3013         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3014                 return 0;
3015
3016         /* safe to close dev here */
3017         fm10k_dev_close(dev);
3018
3019         dev->dev_ops = NULL;
3020         dev->rx_pkt_burst = NULL;
3021         dev->tx_pkt_burst = NULL;
3022
3023         /* disable uio/vfio intr */
3024         rte_intr_disable(&(dev->pci_dev->intr_handle));
3025
3026         /*PF/VF has different interrupt handling mechanism */
3027         if (hw->mac.type == fm10k_mac_pf) {
3028                 /* disable interrupt */
3029                 fm10k_dev_disable_intr_pf(dev);
3030
3031                 /* unregister callback func to eal lib */
3032                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3033                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3034         } else {
3035                 /* disable interrupt */
3036                 fm10k_dev_disable_intr_vf(dev);
3037
3038                 rte_intr_callback_unregister(&(dev->pci_dev->intr_handle),
3039                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3040         }
3041
3042         /* free mac memory */
3043         if (dev->data->mac_addrs) {
3044                 rte_free(dev->data->mac_addrs);
3045                 dev->data->mac_addrs = NULL;
3046         }
3047
3048         memset(hw, 0, sizeof(*hw));
3049
3050         return 0;
3051 }
3052
3053 /*
3054  * The set of PCI devices this driver supports. This driver will enable both PF
3055  * and SRIOV-VF devices.
3056  */
3057 static const struct rte_pci_id pci_id_fm10k_map[] = {
3058 #define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3059 #define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev) { RTE_PCI_DEVICE(vend, dev) },
3060 #include "rte_pci_dev_ids.h"
3061         { .vendor_id = 0, /* sentinel */ },
3062 };
3063
3064 static struct eth_driver rte_pmd_fm10k = {
3065         .pci_drv = {
3066                 .name = "rte_pmd_fm10k",
3067                 .id_table = pci_id_fm10k_map,
3068                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3069                         RTE_PCI_DRV_DETACHABLE,
3070         },
3071         .eth_dev_init = eth_fm10k_dev_init,
3072         .eth_dev_uninit = eth_fm10k_dev_uninit,
3073         .dev_private_size = sizeof(struct fm10k_adapter),
3074 };
3075
3076 /*
3077  * Driver initialization routine.
3078  * Invoked once at EAL init time.
3079  * Register itself as the [Poll Mode] Driver of PCI FM10K devices.
3080  */
3081 static int
3082 rte_pmd_fm10k_init(__rte_unused const char *name,
3083         __rte_unused const char *params)
3084 {
3085         PMD_INIT_FUNC_TRACE();
3086         rte_eth_driver_register(&rte_pmd_fm10k);
3087         return 0;
3088 }
3089
3090 static struct rte_driver rte_fm10k_driver = {
3091         .type = PMD_PDEV,
3092         .init = rte_pmd_fm10k_init,
3093 };
3094
3095 PMD_REGISTER_DRIVER(rte_fm10k_driver);