drivers/net/fm10k/fm10k_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2013-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <rte_ethdev.h>
  35 #include <rte_malloc.h>
  36 #include <rte_memzone.h>
  37 #include <rte_string_fns.h>
  38 #include <rte_dev.h>
  39 #include <rte_spinlock.h>
  40 #include <rte_kvargs.h>
  41
  42 #include "fm10k.h"
  43 #include "base/fm10k_api.h"
  44
  45 /* Default delay to acquire mailbox lock */
  46 #define FM10K_MBXLOCK_DELAY_US 20
  47 #define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL
  48
  49 #define MAIN_VSI_POOL_NUMBER 0
  50
  51 /* Max try times to acquire switch status */
  52 #define MAX_QUERY_SWITCH_STATE_TIMES 10
  53 /* Wait interval to get switch status */
  54 #define WAIT_SWITCH_MSG_US    100000
  55 /* A period of quiescence for switch */
  56 #define FM10K_SWITCH_QUIESCE_US 10000
  57 /* Number of chars per uint32 type */
  58 #define CHARS_PER_UINT32 (sizeof(uint32_t))
  59 #define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)
  60
  61 /* default 1:1 map from queue ID to interrupt vector ID */
  62 #define Q2V(pci_dev, queue_id) ((pci_dev)->intr_handle.intr_vec[queue_id])
  63
  64 /* First 64 Logical ports for PF/VMDQ, second 64 for Flow director */
  65 #define MAX_LPORT_NUM    128
  66 #define GLORT_FD_Q_BASE  0x40
  67 #define GLORT_PF_MASK    0xFFC0
  68 #define GLORT_FD_MASK    GLORT_PF_MASK
  69 #define GLORT_FD_INDEX   GLORT_FD_Q_BASE
  70
  71 static void fm10k_close_mbx_service(struct fm10k_hw *hw);
  72 static void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static inline int fm10k_glort_valid(struct fm10k_hw *hw);
  77 static int
  78 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
  79 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
  80         const u8 *mac, bool add, uint32_t pool);
  81 static void fm10k_tx_queue_release(void *queue);
  82 static void fm10k_rx_queue_release(void *queue);
  83 static void fm10k_set_rx_function(struct rte_eth_dev *dev);
  84 static void fm10k_set_tx_function(struct rte_eth_dev *dev);
  85 static int fm10k_check_ftag(struct rte_devargs *devargs);
  86
  87 struct fm10k_xstats_name_off {
  88         char name[RTE_ETH_XSTATS_NAME_SIZE];
  89         unsigned offset;
  90 };
  91
  92 struct fm10k_xstats_name_off fm10k_hw_stats_strings[] = {
  93         {"completion_timeout_count", offsetof(struct fm10k_hw_stats, timeout)},
  94         {"unsupported_requests_count", offsetof(struct fm10k_hw_stats, ur)},
  95         {"completer_abort_count", offsetof(struct fm10k_hw_stats, ca)},
  96         {"unsupported_message_count", offsetof(struct fm10k_hw_stats, um)},
  97         {"checksum_error_count", offsetof(struct fm10k_hw_stats, xec)},
  98         {"vlan_dropped", offsetof(struct fm10k_hw_stats, vlan_drop)},
  99         {"loopback_dropped", offsetof(struct fm10k_hw_stats, loopback_drop)},
 100         {"rx_mbuf_allocation_errors", offsetof(struct fm10k_hw_stats,
 101                 nodesc_drop)},
 102 };
 103
 104 #define FM10K_NB_HW_XSTATS (sizeof(fm10k_hw_stats_strings) / \
 105                 sizeof(fm10k_hw_stats_strings[0]))
 106
 107 struct fm10k_xstats_name_off fm10k_hw_stats_rx_q_strings[] = {
 108         {"packets", offsetof(struct fm10k_hw_stats_q, rx_packets)},
 109         {"bytes", offsetof(struct fm10k_hw_stats_q, rx_bytes)},
 110         {"dropped", offsetof(struct fm10k_hw_stats_q, rx_drops)},
 111 };
 112
 113 #define FM10K_NB_RX_Q_XSTATS (sizeof(fm10k_hw_stats_rx_q_strings) / \
 114                 sizeof(fm10k_hw_stats_rx_q_strings[0]))
 115
 116 struct fm10k_xstats_name_off fm10k_hw_stats_tx_q_strings[] = {
 117         {"packets", offsetof(struct fm10k_hw_stats_q, tx_packets)},
 118         {"bytes", offsetof(struct fm10k_hw_stats_q, tx_bytes)},
 119 };
 120
 121 #define FM10K_NB_TX_Q_XSTATS (sizeof(fm10k_hw_stats_tx_q_strings) / \
 122                 sizeof(fm10k_hw_stats_tx_q_strings[0]))
 123
 124 #define FM10K_NB_XSTATS (FM10K_NB_HW_XSTATS + FM10K_MAX_QUEUES_PF * \
 125                 (FM10K_NB_RX_Q_XSTATS + FM10K_NB_TX_Q_XSTATS))
 126 static int
 127 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 128
 129 static void
 130 fm10k_mbx_initlock(struct fm10k_hw *hw)
 131 {
 132         rte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 133 }
 134
 135 static void
 136 fm10k_mbx_lock(struct fm10k_hw *hw)
 137 {
 138         while (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))
 139                 rte_delay_us(FM10K_MBXLOCK_DELAY_US);
 140 }
 141
 142 static void
 143 fm10k_mbx_unlock(struct fm10k_hw *hw)
 144 {
 145         rte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));
 146 }
 147
 148 /* Stubs needed for linkage when vPMD is disabled */
 149 int __attribute__((weak))
 150 fm10k_rx_vec_condition_check(__rte_unused struct rte_eth_dev *dev)
 151 {
 152         return -1;
 153 }
 154
 155 uint16_t __attribute__((weak))
 156 fm10k_recv_pkts_vec(
 157         __rte_unused void *rx_queue,
 158         __rte_unused struct rte_mbuf **rx_pkts,
 159         __rte_unused uint16_t nb_pkts)
 160 {
 161         return 0;
 162 }
 163
 164 uint16_t __attribute__((weak))
 165 fm10k_recv_scattered_pkts_vec(
 166                 __rte_unused void *rx_queue,
 167                 __rte_unused struct rte_mbuf **rx_pkts,
 168                 __rte_unused uint16_t nb_pkts)
 169 {
 170         return 0;
 171 }
 172
 173 int __attribute__((weak))
 174 fm10k_rxq_vec_setup(__rte_unused struct fm10k_rx_queue *rxq)
 175
 176 {
 177         return -1;
 178 }
 179
 180 void __attribute__((weak))
 181 fm10k_rx_queue_release_mbufs_vec(
 182                 __rte_unused struct fm10k_rx_queue *rxq)
 183 {
 184         return;
 185 }
 186
 187 void __attribute__((weak))
 188 fm10k_txq_vec_setup(__rte_unused struct fm10k_tx_queue *txq)
 189 {
 190         return;
 191 }
 192
 193 int __attribute__((weak))
 194 fm10k_tx_vec_condition_check(__rte_unused struct fm10k_tx_queue *txq)
 195 {
 196         return -1;
 197 }
 198
 199 uint16_t __attribute__((weak))
 200 fm10k_xmit_pkts_vec(__rte_unused void *tx_queue,
 201                 __rte_unused struct rte_mbuf **tx_pkts,
 202                 __rte_unused uint16_t nb_pkts)
 203 {
 204         return 0;
 205 }
 206
 207 /*
 208  * reset queue to initial state, allocate software buffers used when starting
 209  * device.
 210  * return 0 on success
 211  * return -ENOMEM if buffers cannot be allocated
 212  * return -EINVAL if buffers do not satisfy alignment condition
 213  */
 214 static inline int
 215 rx_queue_reset(struct fm10k_rx_queue *q)
 216 {
 217         static const union fm10k_rx_desc zero = {{0} };
 218         uint64_t dma_addr;
 219         int i, diag;
 220         PMD_INIT_FUNC_TRACE();
 221
 222         diag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);
 223         if (diag != 0)
 224                 return -ENOMEM;
 225
 226         for (i = 0; i < q->nb_desc; ++i) {
 227                 fm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);
 228                 if (!fm10k_addr_alignment_valid(q->sw_ring[i])) {
 229                         rte_mempool_put_bulk(q->mp, (void **)q->sw_ring,
 230                                                 q->nb_desc);
 231                         return -EINVAL;
 232                 }
 233                 dma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);
 234                 q->hw_ring[i].q.pkt_addr = dma_addr;
 235                 q->hw_ring[i].q.hdr_addr = dma_addr;
 236         }
 237
 238         /* initialize extra software ring entries. Space for these extra
 239          * entries is always allocated.
 240          */
 241         memset(&q->fake_mbuf, 0x0, sizeof(q->fake_mbuf));
 242         for (i = 0; i < q->nb_fake_desc; ++i) {
 243                 q->sw_ring[q->nb_desc + i] = &q->fake_mbuf;
 244                 q->hw_ring[q->nb_desc + i] = zero;
 245         }
 246
 247         q->next_dd = 0;
 248         q->next_alloc = 0;
 249         q->next_trigger = q->alloc_thresh - 1;
 250         FM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);
 251         q->rxrearm_start = 0;
 252         q->rxrearm_nb = 0;
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * clean queue, descriptor rings, free software buffers used when stopping
 259  * device.
 260  */
 261 static inline void
 262 rx_queue_clean(struct fm10k_rx_queue *q)
 263 {
 264         union fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };
 265         uint32_t i;
 266         PMD_INIT_FUNC_TRACE();
 267
 268         /* zero descriptor rings */
 269         for (i = 0; i < q->nb_desc; ++i)
 270                 q->hw_ring[i] = zero;
 271
 272         /* zero faked descriptors */
 273         for (i = 0; i < q->nb_fake_desc; ++i)
 274                 q->hw_ring[q->nb_desc + i] = zero;
 275
 276         /* vPMD driver has a different way of releasing mbufs. */
 277         if (q->rx_using_sse) {
 278                 fm10k_rx_queue_release_mbufs_vec(q);
 279                 return;
 280         }
 281
 282         /* free software buffers */
 283         for (i = 0; i < q->nb_desc; ++i) {
 284                 if (q->sw_ring[i]) {
 285                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 286                         q->sw_ring[i] = NULL;
 287                 }
 288         }
 289 }
 290
 291 /*
 292  * free all queue memory used when releasing the queue (i.e. configure)
 293  */
 294 static inline void
 295 rx_queue_free(struct fm10k_rx_queue *q)
 296 {
 297         PMD_INIT_FUNC_TRACE();
 298         if (q) {
 299                 PMD_INIT_LOG(DEBUG, "Freeing rx queue %p", q);
 300                 rx_queue_clean(q);
 301                 if (q->sw_ring) {
 302                         rte_free(q->sw_ring);
 303                         q->sw_ring = NULL;
 304                 }
 305                 rte_free(q);
 306                 q = NULL;
 307         }
 308 }
 309
 310 /*
 311  * disable RX queue, wait unitl HW finished necessary flush operation
 312  */
 313 static inline int
 314 rx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 315 {
 316         uint32_t reg, i;
 317
 318         reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 319         FM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),
 320                         reg & ~FM10K_RXQCTL_ENABLE);
 321
 322         /* Wait 100us at most */
 323         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 324                 rte_delay_us(1);
 325                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));
 326                 if (!(reg & FM10K_RXQCTL_ENABLE))
 327                         break;
 328         }
 329
 330         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 331                 return -1;
 332
 333         return 0;
 334 }
 335
 336 /*
 337  * reset queue to initial state, allocate software buffers used when starting
 338  * device
 339  */
 340 static inline void
 341 tx_queue_reset(struct fm10k_tx_queue *q)
 342 {
 343         PMD_INIT_FUNC_TRACE();
 344         q->last_free = 0;
 345         q->next_free = 0;
 346         q->nb_used = 0;
 347         q->nb_free = q->nb_desc - 1;
 348         fifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);
 349         FM10K_PCI_REG_WRITE(q->tail_ptr, 0);
 350 }
 351
 352 /*
 353  * clean queue, descriptor rings, free software buffers used when stopping
 354  * device
 355  */
 356 static inline void
 357 tx_queue_clean(struct fm10k_tx_queue *q)
 358 {
 359         struct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};
 360         uint32_t i;
 361         PMD_INIT_FUNC_TRACE();
 362
 363         /* zero descriptor rings */
 364         for (i = 0; i < q->nb_desc; ++i)
 365                 q->hw_ring[i] = zero;
 366
 367         /* free software buffers */
 368         for (i = 0; i < q->nb_desc; ++i) {
 369                 if (q->sw_ring[i]) {
 370                         rte_pktmbuf_free_seg(q->sw_ring[i]);
 371                         q->sw_ring[i] = NULL;
 372                 }
 373         }
 374 }
 375
 376 /*
 377  * free all queue memory used when releasing the queue (i.e. configure)
 378  */
 379 static inline void
 380 tx_queue_free(struct fm10k_tx_queue *q)
 381 {
 382         PMD_INIT_FUNC_TRACE();
 383         if (q) {
 384                 PMD_INIT_LOG(DEBUG, "Freeing tx queue %p", q);
 385                 tx_queue_clean(q);
 386                 if (q->rs_tracker.list) {
 387                         rte_free(q->rs_tracker.list);
 388                         q->rs_tracker.list = NULL;
 389                 }
 390                 if (q->sw_ring) {
 391                         rte_free(q->sw_ring);
 392                         q->sw_ring = NULL;
 393                 }
 394                 rte_free(q);
 395                 q = NULL;
 396         }
 397 }
 398
 399 /*
 400  * disable TX queue, wait unitl HW finished necessary flush operation
 401  */
 402 static inline int
 403 tx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)
 404 {
 405         uint32_t reg, i;
 406
 407         reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 408         FM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),
 409                         reg & ~FM10K_TXDCTL_ENABLE);
 410
 411         /* Wait 100us at most */
 412         for (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {
 413                 rte_delay_us(1);
 414                 reg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));
 415                 if (!(reg & FM10K_TXDCTL_ENABLE))
 416                         break;
 417         }
 418
 419         if (i == FM10K_QUEUE_DISABLE_TIMEOUT)
 420                 return -1;
 421
 422         return 0;
 423 }
 424
 425 static int
 426 fm10k_check_mq_mode(struct rte_eth_dev *dev)
 427 {
 428         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 429         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 430         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 431         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 432
 433         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 434
 435         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
 436                 PMD_INIT_LOG(ERR, "DCB mode is not supported.");
 437                 return -EINVAL;
 438         }
 439
 440         if (!(rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG))
 441                 return 0;
 442
 443         if (hw->mac.type == fm10k_mac_vf) {
 444                 PMD_INIT_LOG(ERR, "VMDQ mode is not supported in VF.");
 445                 return -EINVAL;
 446         }
 447
 448         /* Check VMDQ queue pool number */
 449         if (vmdq_conf->nb_queue_pools >
 450                         sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT ||
 451                         vmdq_conf->nb_queue_pools > nb_rx_q) {
 452                 PMD_INIT_LOG(ERR, "Too many of queue pools: %d",
 453                         vmdq_conf->nb_queue_pools);
 454                 return -EINVAL;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static const struct fm10k_txq_ops def_txq_ops = {
 461         .reset = tx_queue_reset,
 462 };
 463
 464 static int
 465 fm10k_dev_configure(struct rte_eth_dev *dev)
 466 {
 467         int ret;
 468
 469         PMD_INIT_FUNC_TRACE();
 470
 471         if (dev->data->dev_conf.rxmode.hw_strip_crc == 0)
 472                 PMD_INIT_LOG(WARNING, "fm10k always strip CRC");
 473         /* multipe queue mode checking */
 474         ret  = fm10k_check_mq_mode(dev);
 475         if (ret != 0) {
 476                 PMD_DRV_LOG(ERR, "fm10k_check_mq_mode fails with %d.",
 477                             ret);
 478                 return ret;
 479         }
 480
 481         return 0;
 482 }
 483
 484 /* fls = find last set bit = 32 minus the number of leading zeros */
 485 #ifndef fls
 486 #define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))
 487 #endif
 488
 489 static void
 490 fm10k_dev_vmdq_rx_configure(struct rte_eth_dev *dev)
 491 {
 492         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 493         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 494         uint32_t i;
 495
 496         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 497
 498         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
 499                 if (!vmdq_conf->pool_map[i].pools)
 500                         continue;
 501                 fm10k_mbx_lock(hw);
 502                 fm10k_update_vlan(hw, vmdq_conf->pool_map[i].vlan_id, 0, true);
 503                 fm10k_mbx_unlock(hw);
 504         }
 505 }
 506
 507 static void
 508 fm10k_dev_pf_main_vsi_reset(struct rte_eth_dev *dev)
 509 {
 510         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         /* Add default mac address */
 513         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
 514                 MAIN_VSI_POOL_NUMBER);
 515 }
 516
 517 static void
 518 fm10k_dev_rss_configure(struct rte_eth_dev *dev)
 519 {
 520         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 521         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 522         uint32_t mrqc, *key, i, reta, j;
 523         uint64_t hf;
 524
 525 #define RSS_KEY_SIZE 40
 526         static uint8_t rss_intel_key[RSS_KEY_SIZE] = {
 527                 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
 528                 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
 529                 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
 530                 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
 531                 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
 532         };
 533
 534         if (dev->data->nb_rx_queues == 1 ||
 535             dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||
 536             dev_conf->rx_adv_conf.rss_conf.rss_hf == 0) {
 537                 FM10K_WRITE_REG(hw, FM10K_MRQC(0), 0);
 538                 return;
 539         }
 540
 541         /* random key is rss_intel_key (default) or user provided (rss_key) */
 542         if (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)
 543                 key = (uint32_t *)rss_intel_key;
 544         else
 545                 key = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;
 546
 547         /* Now fill our hash function seeds, 4 bytes at a time */
 548         for (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)
 549                 FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
 550
 551         /*
 552          * Fill in redirection table
 553          * The byte-swap is needed because NIC registers are in
 554          * little-endian order.
 555          */
 556         reta = 0;
 557         for (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {
 558                 if (j == dev->data->nb_rx_queues)
 559                         j = 0;
 560                 reta = (reta << CHAR_BIT) | j;
 561                 if ((i & 3) == 3)
 562                         FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),
 563                                         rte_bswap32(reta));
 564         }
 565
 566         /*
 567          * Generate RSS hash based on packet types, TCP/UDP
 568          * port numbers and/or IPv4/v6 src and dst addresses
 569          */
 570         hf = dev_conf->rx_adv_conf.rss_conf.rss_hf;
 571         mrqc = 0;
 572         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
 573         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
 574         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
 575         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
 576         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
 577         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
 578         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
 579         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
 580         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
 581
 582         if (mrqc == 0) {
 583                 PMD_INIT_LOG(ERR, "Specified RSS mode 0x%"PRIx64"is not"
 584                         "supported", hf);
 585                 return;
 586         }
 587
 588         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
 589 }
 590
 591 static void
 592 fm10k_dev_logic_port_update(struct rte_eth_dev *dev, uint16_t nb_lport_new)
 593 {
 594         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 595         uint32_t i;
 596
 597         for (i = 0; i < nb_lport_new; i++) {
 598                 /* Set unicast mode by default. App can change
 599                  * to other mode in other API func.
 600                  */
 601                 fm10k_mbx_lock(hw);
 602                 hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map + i,
 603                         FM10K_XCAST_MODE_NONE);
 604                 fm10k_mbx_unlock(hw);
 605         }
 606 }
 607
 608 static void
 609 fm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)
 610 {
 611         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 612         struct rte_eth_vmdq_rx_conf *vmdq_conf;
 613         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 614         struct fm10k_macvlan_filter_info *macvlan;
 615         uint16_t nb_queue_pools = 0; /* pool number in configuration */
 616         uint16_t nb_lport_new;
 617
 618         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 619         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
 620
 621         fm10k_dev_rss_configure(dev);
 622
 623         /* only PF supports VMDQ */
 624         if (hw->mac.type != fm10k_mac_pf)
 625                 return;
 626
 627         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
 628                 nb_queue_pools = vmdq_conf->nb_queue_pools;
 629
 630         /* no pool number change, no need to update logic port and VLAN/MAC */
 631         if (macvlan->nb_queue_pools == nb_queue_pools)
 632                 return;
 633
 634         nb_lport_new = nb_queue_pools ? nb_queue_pools : 1;
 635         fm10k_dev_logic_port_update(dev, nb_lport_new);
 636
 637         /* reset MAC/VLAN as it's based on VMDQ or PF main VSI */
 638         memset(dev->data->mac_addrs, 0,
 639                 ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM);
 640         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
 641                 &dev->data->mac_addrs[0]);
 642         memset(macvlan, 0, sizeof(*macvlan));
 643         macvlan->nb_queue_pools = nb_queue_pools;
 644
 645         if (nb_queue_pools)
 646                 fm10k_dev_vmdq_rx_configure(dev);
 647         else
 648                 fm10k_dev_pf_main_vsi_reset(dev);
 649 }
 650
 651 static int
 652 fm10k_dev_tx_init(struct rte_eth_dev *dev)
 653 {
 654         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 655         int i, ret;
 656         struct fm10k_tx_queue *txq;
 657         uint64_t base_addr;
 658         uint32_t size;
 659
 660         /* Disable TXINT to avoid possible interrupt */
 661         for (i = 0; i < hw->mac.max_queues; i++)
 662                 FM10K_WRITE_REG(hw, FM10K_TXINT(i),
 663                                 3 << FM10K_TXINT_TIMER_SHIFT);
 664
 665         /* Setup TX queue */
 666         for (i = 0; i < dev->data->nb_tx_queues; ++i) {
 667                 txq = dev->data->tx_queues[i];
 668                 base_addr = txq->hw_ring_phys_addr;
 669                 size = txq->nb_desc * sizeof(struct fm10k_tx_desc);
 670
 671                 /* disable queue to avoid issues while updating state */
 672                 ret = tx_queue_disable(hw, i);
 673                 if (ret) {
 674                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 675                         return -1;
 676                 }
 677                 /* Enable use of FTAG bit in TX descriptor, PFVTCTL
 678                  * register is read-only for VF.
 679                  */
 680                 if (fm10k_check_ftag(dev->device->devargs)) {
 681                         if (hw->mac.type == fm10k_mac_pf) {
 682                                 FM10K_WRITE_REG(hw, FM10K_PFVTCTL(i),
 683                                                 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
 684                                 PMD_INIT_LOG(DEBUG, "FTAG mode is enabled");
 685                         } else {
 686                                 PMD_INIT_LOG(ERR, "VF FTAG is not supported.");
 687                                 return -ENOTSUP;
 688                         }
 689                 }
 690
 691                 /* set location and size for descriptor ring */
 692                 FM10K_WRITE_REG(hw, FM10K_TDBAL(i),
 693                                 base_addr & UINT64_LOWER_32BITS_MASK);
 694                 FM10K_WRITE_REG(hw, FM10K_TDBAH(i),
 695                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 696                 FM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);
 697
 698                 /* assign default SGLORT for each TX queue by PF */
 699                 if (hw->mac.type == fm10k_mac_pf)
 700                         FM10K_WRITE_REG(hw, FM10K_TX_SGLORT(i), hw->mac.dglort_map);
 701         }
 702
 703         /* set up vector or scalar TX function as appropriate */
 704         fm10k_set_tx_function(dev);
 705
 706         return 0;
 707 }
 708
 709 static int
 710 fm10k_dev_rx_init(struct rte_eth_dev *dev)
 711 {
 712         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 713         struct fm10k_macvlan_filter_info *macvlan;
 714         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
 715         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
 716         int i, ret;
 717         struct fm10k_rx_queue *rxq;
 718         uint64_t base_addr;
 719         uint32_t size;
 720         uint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
 721         uint32_t logic_port = hw->mac.dglort_map;
 722         uint16_t buf_size;
 723         uint16_t queue_stride = 0;
 724
 725         /* enable RXINT for interrupt mode */
 726         i = 0;
 727         if (rte_intr_dp_is_en(intr_handle)) {
 728                 for (; i < dev->data->nb_rx_queues; i++) {
 729                         FM10K_WRITE_REG(hw, FM10K_RXINT(i), Q2V(pdev, i));
 730                         if (hw->mac.type == fm10k_mac_pf)
 731                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
 732                                         FM10K_ITR_AUTOMASK |
 733                                         FM10K_ITR_MASK_CLEAR);
 734                         else
 735                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
 736                                         FM10K_ITR_AUTOMASK |
 737                                         FM10K_ITR_MASK_CLEAR);
 738                 }
 739         }
 740         /* Disable other RXINT to avoid possible interrupt */
 741         for (; i < hw->mac.max_queues; i++)
 742                 FM10K_WRITE_REG(hw, FM10K_RXINT(i),
 743                         3 << FM10K_RXINT_TIMER_SHIFT);
 744
 745         /* Setup RX queues */
 746         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 747                 rxq = dev->data->rx_queues[i];
 748                 base_addr = rxq->hw_ring_phys_addr;
 749                 size = rxq->nb_desc * sizeof(union fm10k_rx_desc);
 750
 751                 /* disable queue to avoid issues while updating state */
 752                 ret = rx_queue_disable(hw, i);
 753                 if (ret) {
 754                         PMD_INIT_LOG(ERR, "failed to disable queue %d", i);
 755                         return -1;
 756                 }
 757
 758                 /* Setup the Base and Length of the Rx Descriptor Ring */
 759                 FM10K_WRITE_REG(hw, FM10K_RDBAL(i),
 760                                 base_addr & UINT64_LOWER_32BITS_MASK);
 761                 FM10K_WRITE_REG(hw, FM10K_RDBAH(i),
 762                                 base_addr >> (CHAR_BIT * sizeof(uint32_t)));
 763                 FM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);
 764
 765                 /* Configure the Rx buffer size for one buff without split */
 766                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 767                         RTE_PKTMBUF_HEADROOM);
 768                 /* As RX buffer is aligned to 512B within mbuf, some bytes are
 769                  * reserved for this purpose, and the worst case could be 511B.
 770                  * But SRR reg assumes all buffers have the same size. In order
 771                  * to fill the gap, we'll have to consider the worst case and
 772                  * assume 512B is reserved. If we don't do so, it's possible
 773                  * for HW to overwrite data to next mbuf.
 774                  */
 775                 buf_size -= FM10K_RX_DATABUF_ALIGN;
 776
 777                 FM10K_WRITE_REG(hw, FM10K_SRRCTL(i),
 778                                 (buf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT) |
 779                                 FM10K_SRRCTL_LOOPBACK_SUPPRESS);
 780
 781                 /* It adds dual VLAN length for supporting dual VLAN */
 782                 if ((dev->data->dev_conf.rxmode.max_rx_pkt_len +
 783                                 2 * FM10K_VLAN_TAG_SIZE) > buf_size ||
 784                         dev->data->dev_conf.rxmode.enable_scatter) {
 785                         uint32_t reg;
 786                         dev->data->scattered_rx = 1;
 787                         reg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));
 788                         reg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;
 789                         FM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);
 790                 }
 791
 792                 /* Enable drop on empty, it's RO for VF */
 793                 if (hw->mac.type == fm10k_mac_pf && rxq->drop_en)
 794                         rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
 795
 796                 FM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);
 797                 FM10K_WRITE_FLUSH(hw);
 798         }
 799
 800         /* Configure VMDQ/RSS if applicable */
 801         fm10k_dev_mq_rx_configure(dev);
 802
 803         /* Decide the best RX function */
 804         fm10k_set_rx_function(dev);
 805
 806         /* update RX_SGLORT for loopback suppress*/
 807         if (hw->mac.type != fm10k_mac_pf)
 808                 return 0;
 809         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
 810         if (macvlan->nb_queue_pools)
 811                 queue_stride = dev->data->nb_rx_queues / macvlan->nb_queue_pools;
 812         for (i = 0; i < dev->data->nb_rx_queues; ++i) {
 813                 if (i && queue_stride && !(i % queue_stride))
 814                         logic_port++;
 815                 FM10K_WRITE_REG(hw, FM10K_RX_SGLORT(i), logic_port);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int
 822 fm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 823 {
 824         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 825         int err = -1;
 826         uint32_t reg;
 827         struct fm10k_rx_queue *rxq;
 828
 829         PMD_INIT_FUNC_TRACE();
 830
 831         if (rx_queue_id < dev->data->nb_rx_queues) {
 832                 rxq = dev->data->rx_queues[rx_queue_id];
 833                 err = rx_queue_reset(rxq);
 834                 if (err == -ENOMEM) {
 835                         PMD_INIT_LOG(ERR, "Failed to alloc memory : %d", err);
 836                         return err;
 837                 } else if (err == -EINVAL) {
 838                         PMD_INIT_LOG(ERR, "Invalid buffer address alignment :"
 839                                 " %d", err);
 840                         return err;
 841                 }
 842
 843                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 844                  * Note: this must be done AFTER the queue is enabled on real
 845                  * hardware, but BEFORE the queue is enabled when using the
 846                  * emulation platform. Do it in both places for now and remove
 847                  * this comment and the following two register writes when the
 848                  * emulation platform is no longer being used.
 849                  */
 850                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 851                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 852
 853                 /* Set PF ownership flag for PF devices */
 854                 reg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));
 855                 if (hw->mac.type == fm10k_mac_pf)
 856                         reg |= FM10K_RXQCTL_PF;
 857                 reg |= FM10K_RXQCTL_ENABLE;
 858                 /* enable RX queue */
 859                 FM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);
 860                 FM10K_WRITE_FLUSH(hw);
 861
 862                 /* Setup the HW Rx Head and Tail Descriptor Pointers
 863                  * Note: this must be done AFTER the queue is enabled
 864                  */
 865                 FM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);
 866                 FM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);
 867                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 868         }
 869
 870         return err;
 871 }
 872
 873 static int
 874 fm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 875 {
 876         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         if (rx_queue_id < dev->data->nb_rx_queues) {
 881                 /* Disable RX queue */
 882                 rx_queue_disable(hw, rx_queue_id);
 883
 884                 /* Free mbuf and clean HW ring */
 885                 rx_queue_clean(dev->data->rx_queues[rx_queue_id]);
 886                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 887         }
 888
 889         return 0;
 890 }
 891
 892 static int
 893 fm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 896         /** @todo - this should be defined in the shared code */
 897 #define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY       0x00010000
 898         uint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;
 899         int err = 0;
 900
 901         PMD_INIT_FUNC_TRACE();
 902
 903         if (tx_queue_id < dev->data->nb_tx_queues) {
 904                 struct fm10k_tx_queue *q = dev->data->tx_queues[tx_queue_id];
 905
 906                 q->ops->reset(q);
 907
 908                 /* reset head and tail pointers */
 909                 FM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);
 910                 FM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);
 911
 912                 /* enable TX queue */
 913                 FM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),
 914                                         FM10K_TXDCTL_ENABLE | txdctl);
 915                 FM10K_WRITE_FLUSH(hw);
 916                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 917         } else
 918                 err = -1;
 919
 920         return err;
 921 }
 922
 923 static int
 924 fm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 925 {
 926         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 927
 928         PMD_INIT_FUNC_TRACE();
 929
 930         if (tx_queue_id < dev->data->nb_tx_queues) {
 931                 tx_queue_disable(hw, tx_queue_id);
 932                 tx_queue_clean(dev->data->tx_queues[tx_queue_id]);
 933                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 934         }
 935
 936         return 0;
 937 }
 938
 939 static inline int fm10k_glort_valid(struct fm10k_hw *hw)
 940 {
 941         return ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)
 942                 != FM10K_DGLORTMAP_NONE);
 943 }
 944
 945 static void
 946 fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)
 947 {
 948         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949         int status;
 950
 951         PMD_INIT_FUNC_TRACE();
 952
 953         /* Return if it didn't acquire valid glort range */
 954         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 955                 return;
 956
 957         fm10k_mbx_lock(hw);
 958         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 959                                 FM10K_XCAST_MODE_PROMISC);
 960         fm10k_mbx_unlock(hw);
 961
 962         if (status != FM10K_SUCCESS)
 963                 PMD_INIT_LOG(ERR, "Failed to enable promiscuous mode");
 964 }
 965
 966 static void
 967 fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)
 968 {
 969         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 970         uint8_t mode;
 971         int status;
 972
 973         PMD_INIT_FUNC_TRACE();
 974
 975         /* Return if it didn't acquire valid glort range */
 976         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
 977                 return;
 978
 979         if (dev->data->all_multicast == 1)
 980                 mode = FM10K_XCAST_MODE_ALLMULTI;
 981         else
 982                 mode = FM10K_XCAST_MODE_NONE;
 983
 984         fm10k_mbx_lock(hw);
 985         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
 986                                 mode);
 987         fm10k_mbx_unlock(hw);
 988
 989         if (status != FM10K_SUCCESS)
 990                 PMD_INIT_LOG(ERR, "Failed to disable promiscuous mode");
 991 }
 992
 993 static void
 994 fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)
 995 {
 996         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         int status;
 998
 999         PMD_INIT_FUNC_TRACE();
1000
1001         /* Return if it didn't acquire valid glort range */
1002         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1003                 return;
1004
1005         /* If promiscuous mode is enabled, it doesn't make sense to enable
1006          * allmulticast and disable promiscuous since fm10k only can select
1007          * one of the modes.
1008          */
1009         if (dev->data->promiscuous) {
1010                 PMD_INIT_LOG(INFO, "Promiscuous mode is enabled, "\
1011                         "needn't enable allmulticast");
1012                 return;
1013         }
1014
1015         fm10k_mbx_lock(hw);
1016         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1017                                 FM10K_XCAST_MODE_ALLMULTI);
1018         fm10k_mbx_unlock(hw);
1019
1020         if (status != FM10K_SUCCESS)
1021                 PMD_INIT_LOG(ERR, "Failed to enable allmulticast mode");
1022 }
1023
1024 static void
1025 fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)
1026 {
1027         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int status;
1029
1030         PMD_INIT_FUNC_TRACE();
1031
1032         /* Return if it didn't acquire valid glort range */
1033         if ((hw->mac.type == fm10k_mac_pf) && !fm10k_glort_valid(hw))
1034                 return;
1035
1036         if (dev->data->promiscuous) {
1037                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode "\
1038                         "since promisc mode is enabled");
1039                 return;
1040         }
1041
1042         fm10k_mbx_lock(hw);
1043         /* Change mode to unicast mode */
1044         status = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
1045                                 FM10K_XCAST_MODE_NONE);
1046         fm10k_mbx_unlock(hw);
1047
1048         if (status != FM10K_SUCCESS)
1049                 PMD_INIT_LOG(ERR, "Failed to disable allmulticast mode");
1050 }
1051
1052 static void
1053 fm10k_dev_dglort_map_configure(struct rte_eth_dev *dev)
1054 {
1055         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         uint32_t dglortdec, pool_len, rss_len, i, dglortmask;
1057         uint16_t nb_queue_pools;
1058         struct fm10k_macvlan_filter_info *macvlan;
1059
1060         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1061         nb_queue_pools = macvlan->nb_queue_pools;
1062         pool_len = nb_queue_pools ? fls(nb_queue_pools - 1) : 0;
1063         rss_len = fls(dev->data->nb_rx_queues - 1) - pool_len;
1064
1065         /* GLORT 0x0-0x3F are used by PF and VMDQ,  0x40-0x7F used by FD */
1066         dglortdec = (rss_len << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | pool_len;
1067         dglortmask = (GLORT_PF_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1068                         hw->mac.dglort_map;
1069         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), dglortmask);
1070         /* Configure VMDQ/RSS DGlort Decoder */
1071         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0), dglortdec);
1072
1073         /* Flow Director configurations, only queue number is valid. */
1074         dglortdec = fls(dev->data->nb_rx_queues - 1);
1075         dglortmask = (GLORT_FD_MASK << FM10K_DGLORTMAP_MASK_SHIFT) |
1076                         (hw->mac.dglort_map + GLORT_FD_Q_BASE);
1077         FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(1), dglortmask);
1078         FM10K_WRITE_REG(hw, FM10K_DGLORTDEC(1), dglortdec);
1079
1080         /* Invalidate all other GLORT entries */
1081         for (i = 2; i < FM10K_DGLORT_COUNT; i++)
1082                 FM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),
1083                                 FM10K_DGLORTMAP_NONE);
1084 }
1085
1086 #define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)
1087 static int
1088 fm10k_dev_start(struct rte_eth_dev *dev)
1089 {
1090         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1091         int i, diag;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         /* stop, init, then start the hw */
1096         diag = fm10k_stop_hw(hw);
1097         if (diag != FM10K_SUCCESS) {
1098                 PMD_INIT_LOG(ERR, "Hardware stop failed: %d", diag);
1099                 return -EIO;
1100         }
1101
1102         diag = fm10k_init_hw(hw);
1103         if (diag != FM10K_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
1105                 return -EIO;
1106         }
1107
1108         diag = fm10k_start_hw(hw);
1109         if (diag != FM10K_SUCCESS) {
1110                 PMD_INIT_LOG(ERR, "Hardware start failed: %d", diag);
1111                 return -EIO;
1112         }
1113
1114         diag = fm10k_dev_tx_init(dev);
1115         if (diag) {
1116                 PMD_INIT_LOG(ERR, "TX init failed: %d", diag);
1117                 return diag;
1118         }
1119
1120         if (fm10k_dev_rxq_interrupt_setup(dev))
1121                 return -EIO;
1122
1123         diag = fm10k_dev_rx_init(dev);
1124         if (diag) {
1125                 PMD_INIT_LOG(ERR, "RX init failed: %d", diag);
1126                 return diag;
1127         }
1128
1129         if (hw->mac.type == fm10k_mac_pf)
1130                 fm10k_dev_dglort_map_configure(dev);
1131
1132         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1133                 struct fm10k_rx_queue *rxq;
1134                 rxq = dev->data->rx_queues[i];
1135
1136                 if (rxq->rx_deferred_start)
1137                         continue;
1138                 diag = fm10k_dev_rx_queue_start(dev, i);
1139                 if (diag != 0) {
1140                         int j;
1141                         for (j = 0; j < i; ++j)
1142                                 rx_queue_clean(dev->data->rx_queues[j]);
1143                         return diag;
1144                 }
1145         }
1146
1147         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1148                 struct fm10k_tx_queue *txq;
1149                 txq = dev->data->tx_queues[i];
1150
1151                 if (txq->tx_deferred_start)
1152                         continue;
1153                 diag = fm10k_dev_tx_queue_start(dev, i);
1154                 if (diag != 0) {
1155                         int j;
1156                         for (j = 0; j < i; ++j)
1157                                 tx_queue_clean(dev->data->tx_queues[j]);
1158                         for (j = 0; j < dev->data->nb_rx_queues; ++j)
1159                                 rx_queue_clean(dev->data->rx_queues[j]);
1160                         return diag;
1161                 }
1162         }
1163
1164         /* Update default vlan when not in VMDQ mode */
1165         if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
1166                 fm10k_vlan_filter_set(dev, hw->mac.default_vid, true);
1167
1168         return 0;
1169 }
1170
1171 static void
1172 fm10k_dev_stop(struct rte_eth_dev *dev)
1173 {
1174         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1176         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
1177         int i;
1178
1179         PMD_INIT_FUNC_TRACE();
1180
1181         if (dev->data->tx_queues)
1182                 for (i = 0; i < dev->data->nb_tx_queues; i++)
1183                         fm10k_dev_tx_queue_stop(dev, i);
1184
1185         if (dev->data->rx_queues)
1186                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1187                         fm10k_dev_rx_queue_stop(dev, i);
1188
1189         /* Disable datapath event */
1190         if (rte_intr_dp_is_en(intr_handle)) {
1191                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192                         FM10K_WRITE_REG(hw, FM10K_RXINT(i),
1193                                 3 << FM10K_RXINT_TIMER_SHIFT);
1194                         if (hw->mac.type == fm10k_mac_pf)
1195                                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, i)),
1196                                         FM10K_ITR_MASK_SET);
1197                         else
1198                                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, i)),
1199                                         FM10K_ITR_MASK_SET);
1200                 }
1201         }
1202         /* Clean datapath event and queue/vec mapping */
1203         rte_intr_efd_disable(intr_handle);
1204         rte_free(intr_handle->intr_vec);
1205         intr_handle->intr_vec = NULL;
1206 }
1207
1208 static void
1209 fm10k_dev_queue_release(struct rte_eth_dev *dev)
1210 {
1211         int i;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (dev->data->tx_queues) {
1216                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1217                         struct fm10k_tx_queue *txq = dev->data->tx_queues[i];
1218
1219                         tx_queue_free(txq);
1220                 }
1221         }
1222
1223         if (dev->data->rx_queues) {
1224                 for (i = 0; i < dev->data->nb_rx_queues; i++)
1225                         fm10k_rx_queue_release(dev->data->rx_queues[i]);
1226         }
1227 }
1228
1229 static void
1230 fm10k_dev_close(struct rte_eth_dev *dev)
1231 {
1232         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1233
1234         PMD_INIT_FUNC_TRACE();
1235
1236         fm10k_mbx_lock(hw);
1237         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
1238                 MAX_LPORT_NUM, false);
1239         fm10k_mbx_unlock(hw);
1240
1241         /* allow 10ms for device to quiesce */
1242         rte_delay_us(FM10K_SWITCH_QUIESCE_US);
1243
1244         /* Stop mailbox service first */
1245         fm10k_close_mbx_service(hw);
1246         fm10k_dev_stop(dev);
1247         fm10k_dev_queue_release(dev);
1248         fm10k_stop_hw(hw);
1249 }
1250
1251 static int
1252 fm10k_link_update(struct rte_eth_dev *dev,
1253         __rte_unused int wait_to_complete)
1254 {
1255         PMD_INIT_FUNC_TRACE();
1256
1257         /* The host-interface link is always up.  The speed is ~50Gbps per Gen3
1258          * x8 PCIe interface. For now, we leave the speed undefined since there
1259          * is no 50Gbps Ethernet. */
1260         dev->data->dev_link.link_speed  = 0;
1261         dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
1262         dev->data->dev_link.link_status = ETH_LINK_UP;
1263
1264         return 0;
1265 }
1266
1267 static int fm10k_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1268         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
1269 {
1270         unsigned i, q;
1271         unsigned count = 0;
1272
1273         if (xstats_names != NULL) {
1274                 /* Note: limit checked in rte_eth_xstats_names() */
1275
1276                 /* Global stats */
1277                 for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1278                         snprintf(xstats_names[count].name,
1279                                 sizeof(xstats_names[count].name),
1280                                 "%s", fm10k_hw_stats_strings[count].name);
1281                         count++;
1282                 }
1283
1284                 /* PF queue stats */
1285                 for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1286                         for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1287                                 snprintf(xstats_names[count].name,
1288                                         sizeof(xstats_names[count].name),
1289                                         "rx_q%u_%s", q,
1290                                         fm10k_hw_stats_rx_q_strings[i].name);
1291                                 count++;
1292                         }
1293                         for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1294                                 snprintf(xstats_names[count].name,
1295                                         sizeof(xstats_names[count].name),
1296                                         "tx_q%u_%s", q,
1297                                         fm10k_hw_stats_tx_q_strings[i].name);
1298                                 count++;
1299                         }
1300                 }
1301         }
1302         return FM10K_NB_XSTATS;
1303 }
1304
1305 static int
1306 fm10k_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1307                  unsigned n)
1308 {
1309         struct fm10k_hw_stats *hw_stats =
1310                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1311         unsigned i, q, count = 0;
1312
1313         if (n < FM10K_NB_XSTATS)
1314                 return FM10K_NB_XSTATS;
1315
1316         /* Global stats */
1317         for (i = 0; i < FM10K_NB_HW_XSTATS; i++) {
1318                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1319                         fm10k_hw_stats_strings[count].offset);
1320                 xstats[count].id = count;
1321                 count++;
1322         }
1323
1324         /* PF queue stats */
1325         for (q = 0; q < FM10K_MAX_QUEUES_PF; q++) {
1326                 for (i = 0; i < FM10K_NB_RX_Q_XSTATS; i++) {
1327                         xstats[count].value =
1328                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1329                                 fm10k_hw_stats_rx_q_strings[i].offset);
1330                         xstats[count].id = count;
1331                         count++;
1332                 }
1333                 for (i = 0; i < FM10K_NB_TX_Q_XSTATS; i++) {
1334                         xstats[count].value =
1335                                 *(uint64_t *)(((char *)&hw_stats->q[q]) +
1336                                 fm10k_hw_stats_tx_q_strings[i].offset);
1337                         xstats[count].id = count;
1338                         count++;
1339                 }
1340         }
1341
1342         return FM10K_NB_XSTATS;
1343 }
1344
1345 static void
1346 fm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1347 {
1348         uint64_t ipackets, opackets, ibytes, obytes;
1349         struct fm10k_hw *hw =
1350                 FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         struct fm10k_hw_stats *hw_stats =
1352                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1353         int i;
1354
1355         PMD_INIT_FUNC_TRACE();
1356
1357         fm10k_update_hw_stats(hw, hw_stats);
1358
1359         ipackets = opackets = ibytes = obytes = 0;
1360         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1361                 (i < hw->mac.max_queues); ++i) {
1362                 stats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;
1363                 stats->q_opackets[i] = hw_stats->q[i].tx_packets.count;
1364                 stats->q_ibytes[i]   = hw_stats->q[i].rx_bytes.count;
1365                 stats->q_obytes[i]   = hw_stats->q[i].tx_bytes.count;
1366                 ipackets += stats->q_ipackets[i];
1367                 opackets += stats->q_opackets[i];
1368                 ibytes   += stats->q_ibytes[i];
1369                 obytes   += stats->q_obytes[i];
1370         }
1371         stats->ipackets = ipackets;
1372         stats->opackets = opackets;
1373         stats->ibytes = ibytes;
1374         stats->obytes = obytes;
1375 }
1376
1377 static void
1378 fm10k_stats_reset(struct rte_eth_dev *dev)
1379 {
1380         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381         struct fm10k_hw_stats *hw_stats =
1382                 FM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         memset(hw_stats, 0, sizeof(*hw_stats));
1387         fm10k_rebind_hw_stats(hw, hw_stats);
1388 }
1389
1390 static void
1391 fm10k_dev_infos_get(struct rte_eth_dev *dev,
1392         struct rte_eth_dev_info *dev_info)
1393 {
1394         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
1396
1397         PMD_INIT_FUNC_TRACE();
1398
1399         dev_info->pci_dev            = pdev;
1400         dev_info->min_rx_bufsize     = FM10K_MIN_RX_BUF_SIZE;
1401         dev_info->max_rx_pktlen      = FM10K_MAX_PKT_SIZE;
1402         dev_info->max_rx_queues      = hw->mac.max_queues;
1403         dev_info->max_tx_queues      = hw->mac.max_queues;
1404         dev_info->max_mac_addrs      = FM10K_MAX_MACADDR_NUM;
1405         dev_info->max_hash_mac_addrs = 0;
1406         dev_info->max_vfs            = pdev->max_vfs;
1407         dev_info->vmdq_pool_base     = 0;
1408         dev_info->vmdq_queue_base    = 0;
1409         dev_info->max_vmdq_pools     = ETH_32_POOLS;
1410         dev_info->vmdq_queue_num     = FM10K_MAX_QUEUES_PF;
1411         dev_info->rx_offload_capa =
1412                 DEV_RX_OFFLOAD_VLAN_STRIP |
1413                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1414                 DEV_RX_OFFLOAD_UDP_CKSUM  |
1415                 DEV_RX_OFFLOAD_TCP_CKSUM;
1416         dev_info->tx_offload_capa =
1417                 DEV_TX_OFFLOAD_VLAN_INSERT |
1418                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1419                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1420                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1421                 DEV_TX_OFFLOAD_TCP_TSO;
1422
1423         dev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);
1424         dev_info->reta_size = FM10K_MAX_RSS_INDICES;
1425
1426         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1427                 .rx_thresh = {
1428                         .pthresh = FM10K_DEFAULT_RX_PTHRESH,
1429                         .hthresh = FM10K_DEFAULT_RX_HTHRESH,
1430                         .wthresh = FM10K_DEFAULT_RX_WTHRESH,
1431                 },
1432                 .rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),
1433                 .rx_drop_en = 0,
1434         };
1435
1436         dev_info->default_txconf = (struct rte_eth_txconf) {
1437                 .tx_thresh = {
1438                         .pthresh = FM10K_DEFAULT_TX_PTHRESH,
1439                         .hthresh = FM10K_DEFAULT_TX_HTHRESH,
1440                         .wthresh = FM10K_DEFAULT_TX_WTHRESH,
1441                 },
1442                 .tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),
1443                 .tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),
1444                 .txq_flags = FM10K_SIMPLE_TX_FLAG,
1445         };
1446
1447         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1448                 .nb_max = FM10K_MAX_RX_DESC,
1449                 .nb_min = FM10K_MIN_RX_DESC,
1450                 .nb_align = FM10K_MULT_RX_DESC,
1451         };
1452
1453         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1454                 .nb_max = FM10K_MAX_TX_DESC,
1455                 .nb_min = FM10K_MIN_TX_DESC,
1456                 .nb_align = FM10K_MULT_TX_DESC,
1457         };
1458
1459         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
1460                         ETH_LINK_SPEED_10G | ETH_LINK_SPEED_25G |
1461                         ETH_LINK_SPEED_40G | ETH_LINK_SPEED_100G;
1462 }
1463
1464 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
1465 static const uint32_t *
1466 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1467 {
1468         if (dev->rx_pkt_burst == fm10k_recv_pkts ||
1469             dev->rx_pkt_burst == fm10k_recv_scattered_pkts) {
1470                 static uint32_t ptypes[] = {
1471                         /* refers to rx_desc_to_ol_flags() */
1472                         RTE_PTYPE_L2_ETHER,
1473                         RTE_PTYPE_L3_IPV4,
1474                         RTE_PTYPE_L3_IPV4_EXT,
1475                         RTE_PTYPE_L3_IPV6,
1476                         RTE_PTYPE_L3_IPV6_EXT,
1477                         RTE_PTYPE_L4_TCP,
1478                         RTE_PTYPE_L4_UDP,
1479                         RTE_PTYPE_UNKNOWN
1480                 };
1481
1482                 return ptypes;
1483         } else if (dev->rx_pkt_burst == fm10k_recv_pkts_vec ||
1484                    dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec) {
1485                 static uint32_t ptypes_vec[] = {
1486                         /* refers to fm10k_desc_to_pktype_v() */
1487                         RTE_PTYPE_L3_IPV4,
1488                         RTE_PTYPE_L3_IPV4_EXT,
1489                         RTE_PTYPE_L3_IPV6,
1490                         RTE_PTYPE_L3_IPV6_EXT,
1491                         RTE_PTYPE_L4_TCP,
1492                         RTE_PTYPE_L4_UDP,
1493                         RTE_PTYPE_TUNNEL_GENEVE,
1494                         RTE_PTYPE_TUNNEL_NVGRE,
1495                         RTE_PTYPE_TUNNEL_VXLAN,
1496                         RTE_PTYPE_TUNNEL_GRE,
1497                         RTE_PTYPE_UNKNOWN
1498                 };
1499
1500                 return ptypes_vec;
1501         }
1502
1503         return NULL;
1504 }
1505 #else
1506 static const uint32_t *
1507 fm10k_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
1508 {
1509         return NULL;
1510 }
1511 #endif
1512
1513 static int
1514 fm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1515 {
1516         s32 result;
1517         uint16_t mac_num = 0;
1518         uint32_t vid_idx, vid_bit, mac_index;
1519         struct fm10k_hw *hw;
1520         struct fm10k_macvlan_filter_info *macvlan;
1521         struct rte_eth_dev_data *data = dev->data;
1522
1523         hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1525
1526         if (macvlan->nb_queue_pools > 0) { /* VMDQ mode */
1527                 PMD_INIT_LOG(ERR, "Cannot change VLAN filter in VMDQ mode");
1528                 return -EINVAL;
1529         }
1530
1531         if (vlan_id > ETH_VLAN_ID_MAX) {
1532                 PMD_INIT_LOG(ERR, "Invalid vlan_id: must be < 4096");
1533                 return -EINVAL;
1534         }
1535
1536         vid_idx = FM10K_VFTA_IDX(vlan_id);
1537         vid_bit = FM10K_VFTA_BIT(vlan_id);
1538         /* this VLAN ID is already in the VLAN filter table, return SUCCESS */
1539         if (on && (macvlan->vfta[vid_idx] & vid_bit))
1540                 return 0;
1541         /* this VLAN ID is NOT in the VLAN filter table, cannot remove */
1542         if (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {
1543                 PMD_INIT_LOG(ERR, "Invalid vlan_id: not existing "
1544                         "in the VLAN filter table");
1545                 return -EINVAL;
1546         }
1547
1548         fm10k_mbx_lock(hw);
1549         result = fm10k_update_vlan(hw, vlan_id, 0, on);
1550         fm10k_mbx_unlock(hw);
1551         if (result != FM10K_SUCCESS) {
1552                 PMD_INIT_LOG(ERR, "VLAN update failed: %d", result);
1553                 return -EIO;
1554         }
1555
1556         for (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&
1557                         (result == FM10K_SUCCESS); mac_index++) {
1558                 if (is_zero_ether_addr(&data->mac_addrs[mac_index]))
1559                         continue;
1560                 if (mac_num > macvlan->mac_num - 1) {
1561                         PMD_INIT_LOG(ERR, "MAC address number "
1562                                         "not match");
1563                         break;
1564                 }
1565                 fm10k_mbx_lock(hw);
1566                 result = fm10k_update_uc_addr(hw, hw->mac.dglort_map,
1567                         data->mac_addrs[mac_index].addr_bytes,
1568                         vlan_id, on, 0);
1569                 fm10k_mbx_unlock(hw);
1570                 mac_num++;
1571         }
1572         if (result != FM10K_SUCCESS) {
1573                 PMD_INIT_LOG(ERR, "MAC address update failed: %d", result);
1574                 return -EIO;
1575         }
1576
1577         if (on) {
1578                 macvlan->vlan_num++;
1579                 macvlan->vfta[vid_idx] |= vid_bit;
1580         } else {
1581                 macvlan->vlan_num--;
1582                 macvlan->vfta[vid_idx] &= ~vid_bit;
1583         }
1584         return 0;
1585 }
1586
1587 static void
1588 fm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)
1589 {
1590         if (mask & ETH_VLAN_STRIP_MASK) {
1591                 if (!dev->data->dev_conf.rxmode.hw_vlan_strip)
1592                         PMD_INIT_LOG(ERR, "VLAN stripping is "
1593                                         "always on in fm10k");
1594         }
1595
1596         if (mask & ETH_VLAN_EXTEND_MASK) {
1597                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1598                         PMD_INIT_LOG(ERR, "VLAN QinQ is not "
1599                                         "supported in fm10k");
1600         }
1601
1602         if (mask & ETH_VLAN_FILTER_MASK) {
1603                 if (!dev->data->dev_conf.rxmode.hw_vlan_filter)
1604                         PMD_INIT_LOG(ERR, "VLAN filter is always on in fm10k");
1605         }
1606 }
1607
1608 /* Add/Remove a MAC address, and update filters to main VSI */
1609 static void fm10k_MAC_filter_set_main_vsi(struct rte_eth_dev *dev,
1610                 const u8 *mac, bool add, uint32_t pool)
1611 {
1612         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         struct fm10k_macvlan_filter_info *macvlan;
1614         uint32_t i, j, k;
1615
1616         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1617
1618         if (pool != MAIN_VSI_POOL_NUMBER) {
1619                 PMD_DRV_LOG(ERR, "VMDQ not enabled, can't set "
1620                         "mac to pool %u", pool);
1621                 return;
1622         }
1623         for (i = 0, j = 0; j < FM10K_VFTA_SIZE; j++) {
1624                 if (!macvlan->vfta[j])
1625                         continue;
1626                 for (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {
1627                         if (!(macvlan->vfta[j] & (1 << k)))
1628                                 continue;
1629                         if (i + 1 > macvlan->vlan_num) {
1630                                 PMD_INIT_LOG(ERR, "vlan number not match");
1631                                 return;
1632                         }
1633                         fm10k_mbx_lock(hw);
1634                         fm10k_update_uc_addr(hw, hw->mac.dglort_map, mac,
1635                                 j * FM10K_UINT32_BIT_SIZE + k, add, 0);
1636                         fm10k_mbx_unlock(hw);
1637                         i++;
1638                 }
1639         }
1640 }
1641
1642 /* Add/Remove a MAC address, and update filters to VMDQ */
1643 static void fm10k_MAC_filter_set_vmdq(struct rte_eth_dev *dev,
1644                 const u8 *mac, bool add, uint32_t pool)
1645 {
1646         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647         struct fm10k_macvlan_filter_info *macvlan;
1648         struct rte_eth_vmdq_rx_conf *vmdq_conf;
1649         uint32_t i;
1650
1651         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1652         vmdq_conf = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
1653
1654         if (pool > macvlan->nb_queue_pools) {
1655                 PMD_DRV_LOG(ERR, "Pool number %u invalid."
1656                         " Max pool is %u",
1657                         pool, macvlan->nb_queue_pools);
1658                 return;
1659         }
1660         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
1661                 if (!(vmdq_conf->pool_map[i].pools & (1UL << pool)))
1662                         continue;
1663                 fm10k_mbx_lock(hw);
1664                 fm10k_update_uc_addr(hw, hw->mac.dglort_map + pool, mac,
1665                         vmdq_conf->pool_map[i].vlan_id, add, 0);
1666                 fm10k_mbx_unlock(hw);
1667         }
1668 }
1669
1670 /* Add/Remove a MAC address, and update filters */
1671 static void fm10k_MAC_filter_set(struct rte_eth_dev *dev,
1672                 const u8 *mac, bool add, uint32_t pool)
1673 {
1674         struct fm10k_macvlan_filter_info *macvlan;
1675
1676         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1677
1678         if (macvlan->nb_queue_pools > 0) /* VMDQ mode */
1679                 fm10k_MAC_filter_set_vmdq(dev, mac, add, pool);
1680         else
1681                 fm10k_MAC_filter_set_main_vsi(dev, mac, add, pool);
1682
1683         if (add)
1684                 macvlan->mac_num++;
1685         else
1686                 macvlan->mac_num--;
1687 }
1688
1689 /* Add a MAC address, and update filters */
1690 static void
1691 fm10k_macaddr_add(struct rte_eth_dev *dev,
1692                 struct ether_addr *mac_addr,
1693                 uint32_t index,
1694                 uint32_t pool)
1695 {
1696         struct fm10k_macvlan_filter_info *macvlan;
1697
1698         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1699         fm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE, pool);
1700         macvlan->mac_vmdq_id[index] = pool;
1701 }
1702
1703 /* Remove a MAC address, and update filters */
1704 static void
1705 fm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1706 {
1707         struct rte_eth_dev_data *data = dev->data;
1708         struct fm10k_macvlan_filter_info *macvlan;
1709
1710         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
1711         fm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,
1712                         FALSE, macvlan->mac_vmdq_id[index]);
1713         macvlan->mac_vmdq_id[index] = 0;
1714 }
1715
1716 static inline int
1717 check_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)
1718 {
1719         if ((request < min) || (request > max) || ((request % mult) != 0))
1720                 return -1;
1721         else
1722                 return 0;
1723 }
1724
1725
1726 static inline int
1727 check_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)
1728 {
1729         if ((request < min) || (request > max) || ((div % request) != 0))
1730                 return -1;
1731         else
1732                 return 0;
1733 }
1734
1735 static inline int
1736 handle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)
1737 {
1738         uint16_t rx_free_thresh;
1739
1740         if (conf->rx_free_thresh == 0)
1741                 rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);
1742         else
1743                 rx_free_thresh = conf->rx_free_thresh;
1744
1745         /* make sure the requested threshold satisfies the constraints */
1746         if (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),
1747                         FM10K_RX_FREE_THRESH_MAX(q),
1748                         FM10K_RX_FREE_THRESH_DIV(q),
1749                         rx_free_thresh)) {
1750                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be "
1751                         "less than or equal to %u, "
1752                         "greater than or equal to %u, "
1753                         "and a divisor of %u",
1754                         rx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),
1755                         FM10K_RX_FREE_THRESH_MIN(q),
1756                         FM10K_RX_FREE_THRESH_DIV(q));
1757                 return -EINVAL;
1758         }
1759
1760         q->alloc_thresh = rx_free_thresh;
1761         q->drop_en = conf->rx_drop_en;
1762         q->rx_deferred_start = conf->rx_deferred_start;
1763
1764         return 0;
1765 }
1766
1767 /*
1768  * Hardware requires specific alignment for Rx packet buffers. At
1769  * least one of the following two conditions must be satisfied.
1770  *  1. Address is 512B aligned
1771  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
1772  *
1773  * As such, the driver may need to adjust the DMA address within the
1774  * buffer by up to 512B.
1775  *
1776  * return 1 if the element size is valid, otherwise return 0.
1777  */
1778 static int
1779 mempool_element_size_valid(struct rte_mempool *mp)
1780 {
1781         uint32_t min_size;
1782
1783         /* elt_size includes mbuf header and headroom */
1784         min_size = mp->elt_size - sizeof(struct rte_mbuf) -
1785                         RTE_PKTMBUF_HEADROOM;
1786
1787         /* account for up to 512B of alignment */
1788         min_size -= FM10K_RX_DATABUF_ALIGN;
1789
1790         /* sanity check for overflow */
1791         if (min_size > mp->elt_size)
1792                 return 0;
1793
1794         /* size is valid */
1795         return 1;
1796 }
1797
1798 static int
1799 fm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1800         uint16_t nb_desc, unsigned int socket_id,
1801         const struct rte_eth_rxconf *conf, struct rte_mempool *mp)
1802 {
1803         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1804         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
1805         struct fm10k_rx_queue *q;
1806         const struct rte_memzone *mz;
1807
1808         PMD_INIT_FUNC_TRACE();
1809
1810         /* make sure the mempool element size can account for alignment. */
1811         if (!mempool_element_size_valid(mp)) {
1812                 PMD_INIT_LOG(ERR, "Error : Mempool element size is too small");
1813                 return -EINVAL;
1814         }
1815
1816         /* make sure a valid number of descriptors have been requested */
1817         if (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,
1818                                 FM10K_MULT_RX_DESC, nb_desc)) {
1819                 PMD_INIT_LOG(ERR, "Number of Rx descriptors (%u) must be "
1820                         "less than or equal to %"PRIu32", "
1821                         "greater than or equal to %u, "
1822                         "and a multiple of %u",
1823                         nb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,
1824                         FM10K_MULT_RX_DESC);
1825                 return -EINVAL;
1826         }
1827
1828         /*
1829          * if this queue existed already, free the associated memory. The
1830          * queue cannot be reused in case we need to allocate memory on
1831          * different socket than was previously used.
1832          */
1833         if (dev->data->rx_queues[queue_id] != NULL) {
1834                 rx_queue_free(dev->data->rx_queues[queue_id]);
1835                 dev->data->rx_queues[queue_id] = NULL;
1836         }
1837
1838         /* allocate memory for the queue structure */
1839         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
1840                                 socket_id);
1841         if (q == NULL) {
1842                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
1843                 return -ENOMEM;
1844         }
1845
1846         /* setup queue */
1847         q->mp = mp;
1848         q->nb_desc = nb_desc;
1849         q->nb_fake_desc = FM10K_MULT_RX_DESC;
1850         q->port_id = dev->data->port_id;
1851         q->queue_id = queue_id;
1852         q->tail_ptr = (volatile uint32_t *)
1853                 &((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];
1854         if (handle_rxconf(q, conf))
1855                 return -EINVAL;
1856
1857         /* allocate memory for the software ring */
1858         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
1859                         (nb_desc + q->nb_fake_desc) * sizeof(struct rte_mbuf *),
1860                         RTE_CACHE_LINE_SIZE, socket_id);
1861         if (q->sw_ring == NULL) {
1862                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
1863                 rte_free(q);
1864                 return -ENOMEM;
1865         }
1866
1867         /*
1868          * allocate memory for the hardware descriptor ring. A memzone large
1869          * enough to hold the maximum ring size is requested to allow for
1870          * resizing in later calls to the queue setup function.
1871          */
1872         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_id,
1873                                       FM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC,
1874                                       socket_id);
1875         if (mz == NULL) {
1876                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
1877                 rte_free(q->sw_ring);
1878                 rte_free(q);
1879                 return -ENOMEM;
1880         }
1881         q->hw_ring = mz->addr;
1882         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
1883
1884         /* Check if number of descs satisfied Vector requirement */
1885         if (!rte_is_power_of_2(nb_desc)) {
1886                 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
1887                                     "preconditions - canceling the feature for "
1888                                     "the whole port[%d]",
1889                              q->queue_id, q->port_id);
1890                 dev_info->rx_vec_allowed = false;
1891         } else
1892                 fm10k_rxq_vec_setup(q);
1893
1894         dev->data->rx_queues[queue_id] = q;
1895         return 0;
1896 }
1897
1898 static void
1899 fm10k_rx_queue_release(void *queue)
1900 {
1901         PMD_INIT_FUNC_TRACE();
1902
1903         rx_queue_free(queue);
1904 }
1905
1906 static inline int
1907 handle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)
1908 {
1909         uint16_t tx_free_thresh;
1910         uint16_t tx_rs_thresh;
1911
1912         /* constraint MACROs require that tx_free_thresh is configured
1913          * before tx_rs_thresh */
1914         if (conf->tx_free_thresh == 0)
1915                 tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);
1916         else
1917                 tx_free_thresh = conf->tx_free_thresh;
1918
1919         /* make sure the requested threshold satisfies the constraints */
1920         if (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),
1921                         FM10K_TX_FREE_THRESH_MAX(q),
1922                         FM10K_TX_FREE_THRESH_DIV(q),
1923                         tx_free_thresh)) {
1924                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be "
1925                         "less than or equal to %u, "
1926                         "greater than or equal to %u, "
1927                         "and a divisor of %u",
1928                         tx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),
1929                         FM10K_TX_FREE_THRESH_MIN(q),
1930                         FM10K_TX_FREE_THRESH_DIV(q));
1931                 return -EINVAL;
1932         }
1933
1934         q->free_thresh = tx_free_thresh;
1935
1936         if (conf->tx_rs_thresh == 0)
1937                 tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);
1938         else
1939                 tx_rs_thresh = conf->tx_rs_thresh;
1940
1941         q->tx_deferred_start = conf->tx_deferred_start;
1942
1943         /* make sure the requested threshold satisfies the constraints */
1944         if (check_thresh(FM10K_TX_RS_THRESH_MIN(q),
1945                         FM10K_TX_RS_THRESH_MAX(q),
1946                         FM10K_TX_RS_THRESH_DIV(q),
1947                         tx_rs_thresh)) {
1948                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be "
1949                         "less than or equal to %u, "
1950                         "greater than or equal to %u, "
1951                         "and a divisor of %u",
1952                         tx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),
1953                         FM10K_TX_RS_THRESH_MIN(q),
1954                         FM10K_TX_RS_THRESH_DIV(q));
1955                 return -EINVAL;
1956         }
1957
1958         q->rs_thresh = tx_rs_thresh;
1959
1960         return 0;
1961 }
1962
1963 static int
1964 fm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
1965         uint16_t nb_desc, unsigned int socket_id,
1966         const struct rte_eth_txconf *conf)
1967 {
1968         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969         struct fm10k_tx_queue *q;
1970         const struct rte_memzone *mz;
1971
1972         PMD_INIT_FUNC_TRACE();
1973
1974         /* make sure a valid number of descriptors have been requested */
1975         if (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,
1976                                 FM10K_MULT_TX_DESC, nb_desc)) {
1977                 PMD_INIT_LOG(ERR, "Number of Tx descriptors (%u) must be "
1978                         "less than or equal to %"PRIu32", "
1979                         "greater than or equal to %u, "
1980                         "and a multiple of %u",
1981                         nb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,
1982                         FM10K_MULT_TX_DESC);
1983                 return -EINVAL;
1984         }
1985
1986         /*
1987          * if this queue existed already, free the associated memory. The
1988          * queue cannot be reused in case we need to allocate memory on
1989          * different socket than was previously used.
1990          */
1991         if (dev->data->tx_queues[queue_id] != NULL) {
1992                 struct fm10k_tx_queue *txq = dev->data->tx_queues[queue_id];
1993
1994                 tx_queue_free(txq);
1995                 dev->data->tx_queues[queue_id] = NULL;
1996         }
1997
1998         /* allocate memory for the queue structure */
1999         q = rte_zmalloc_socket("fm10k", sizeof(*q), RTE_CACHE_LINE_SIZE,
2000                                 socket_id);
2001         if (q == NULL) {
2002                 PMD_INIT_LOG(ERR, "Cannot allocate queue structure");
2003                 return -ENOMEM;
2004         }
2005
2006         /* setup queue */
2007         q->nb_desc = nb_desc;
2008         q->port_id = dev->data->port_id;
2009         q->queue_id = queue_id;
2010         q->txq_flags = conf->txq_flags;
2011         q->ops = &def_txq_ops;
2012         q->tail_ptr = (volatile uint32_t *)
2013                 &((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];
2014         if (handle_txconf(q, conf))
2015                 return -EINVAL;
2016
2017         /* allocate memory for the software ring */
2018         q->sw_ring = rte_zmalloc_socket("fm10k sw ring",
2019                                         nb_desc * sizeof(struct rte_mbuf *),
2020                                         RTE_CACHE_LINE_SIZE, socket_id);
2021         if (q->sw_ring == NULL) {
2022                 PMD_INIT_LOG(ERR, "Cannot allocate software ring");
2023                 rte_free(q);
2024                 return -ENOMEM;
2025         }
2026
2027         /*
2028          * allocate memory for the hardware descriptor ring. A memzone large
2029          * enough to hold the maximum ring size is requested to allow for
2030          * resizing in later calls to the queue setup function.
2031          */
2032         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_id,
2033                                       FM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC,
2034                                       socket_id);
2035         if (mz == NULL) {
2036                 PMD_INIT_LOG(ERR, "Cannot allocate hardware ring");
2037                 rte_free(q->sw_ring);
2038                 rte_free(q);
2039                 return -ENOMEM;
2040         }
2041         q->hw_ring = mz->addr;
2042         q->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2043
2044         /*
2045          * allocate memory for the RS bit tracker. Enough slots to hold the
2046          * descriptor index for each RS bit needing to be set are required.
2047          */
2048         q->rs_tracker.list = rte_zmalloc_socket("fm10k rs tracker",
2049                                 ((nb_desc + 1) / q->rs_thresh) *
2050                                 sizeof(uint16_t),
2051                                 RTE_CACHE_LINE_SIZE, socket_id);
2052         if (q->rs_tracker.list == NULL) {
2053                 PMD_INIT_LOG(ERR, "Cannot allocate RS bit tracker");
2054                 rte_free(q->sw_ring);
2055                 rte_free(q);
2056                 return -ENOMEM;
2057         }
2058
2059         dev->data->tx_queues[queue_id] = q;
2060         return 0;
2061 }
2062
2063 static void
2064 fm10k_tx_queue_release(void *queue)
2065 {
2066         struct fm10k_tx_queue *q = queue;
2067         PMD_INIT_FUNC_TRACE();
2068
2069         tx_queue_free(q);
2070 }
2071
2072 static int
2073 fm10k_reta_update(struct rte_eth_dev *dev,
2074                         struct rte_eth_rss_reta_entry64 *reta_conf,
2075                         uint16_t reta_size)
2076 {
2077         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2078         uint16_t i, j, idx, shift;
2079         uint8_t mask;
2080         uint32_t reta;
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         if (reta_size > FM10K_MAX_RSS_INDICES) {
2085                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2086                         "(%d) doesn't match the number hardware can supported "
2087                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2088                 return -EINVAL;
2089         }
2090
2091         /*
2092          * Update Redirection Table RETA[n], n=0..31. The redirection table has
2093          * 128-entries in 32 registers
2094          */
2095         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2096                 idx = i / RTE_RETA_GROUP_SIZE;
2097                 shift = i % RTE_RETA_GROUP_SIZE;
2098                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2099                                 BIT_MASK_PER_UINT32);
2100                 if (mask == 0)
2101                         continue;
2102
2103                 reta = 0;
2104                 if (mask != BIT_MASK_PER_UINT32)
2105                         reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2106
2107                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2108                         if (mask & (0x1 << j)) {
2109                                 if (mask != 0xF)
2110                                         reta &= ~(UINT8_MAX << CHAR_BIT * j);
2111                                 reta |= reta_conf[idx].reta[shift + j] <<
2112                                                 (CHAR_BIT * j);
2113                         }
2114                 }
2115                 FM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);
2116         }
2117
2118         return 0;
2119 }
2120
2121 static int
2122 fm10k_reta_query(struct rte_eth_dev *dev,
2123                         struct rte_eth_rss_reta_entry64 *reta_conf,
2124                         uint16_t reta_size)
2125 {
2126         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         uint16_t i, j, idx, shift;
2128         uint8_t mask;
2129         uint32_t reta;
2130
2131         PMD_INIT_FUNC_TRACE();
2132
2133         if (reta_size < FM10K_MAX_RSS_INDICES) {
2134                 PMD_INIT_LOG(ERR, "The size of hash lookup table configured "
2135                         "(%d) doesn't match the number hardware can supported "
2136                         "(%d)", reta_size, FM10K_MAX_RSS_INDICES);
2137                 return -EINVAL;
2138         }
2139
2140         /*
2141          * Read Redirection Table RETA[n], n=0..31. The redirection table has
2142          * 128-entries in 32 registers
2143          */
2144         for (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {
2145                 idx = i / RTE_RETA_GROUP_SIZE;
2146                 shift = i % RTE_RETA_GROUP_SIZE;
2147                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2148                                 BIT_MASK_PER_UINT32);
2149                 if (mask == 0)
2150                         continue;
2151
2152                 reta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));
2153                 for (j = 0; j < CHARS_PER_UINT32; j++) {
2154                         if (mask & (0x1 << j))
2155                                 reta_conf[idx].reta[shift + j] = ((reta >>
2156                                         CHAR_BIT * j) & UINT8_MAX);
2157                 }
2158         }
2159
2160         return 0;
2161 }
2162
2163 static int
2164 fm10k_rss_hash_update(struct rte_eth_dev *dev,
2165         struct rte_eth_rss_conf *rss_conf)
2166 {
2167         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2169         uint32_t mrqc;
2170         uint64_t hf = rss_conf->rss_hf;
2171         int i;
2172
2173         PMD_INIT_FUNC_TRACE();
2174
2175         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2176                                 FM10K_RSSRK_ENTRIES_PER_REG))
2177                 return -EINVAL;
2178
2179         if (hf == 0)
2180                 return -EINVAL;
2181
2182         mrqc = 0;
2183         mrqc |= (hf & ETH_RSS_IPV4)              ? FM10K_MRQC_IPV4     : 0;
2184         mrqc |= (hf & ETH_RSS_IPV6)              ? FM10K_MRQC_IPV6     : 0;
2185         mrqc |= (hf & ETH_RSS_IPV6_EX)           ? FM10K_MRQC_IPV6     : 0;
2186         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? FM10K_MRQC_TCP_IPV4 : 0;
2187         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? FM10K_MRQC_TCP_IPV6 : 0;
2188         mrqc |= (hf & ETH_RSS_IPV6_TCP_EX)       ? FM10K_MRQC_TCP_IPV6 : 0;
2189         mrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? FM10K_MRQC_UDP_IPV4 : 0;
2190         mrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? FM10K_MRQC_UDP_IPV6 : 0;
2191         mrqc |= (hf & ETH_RSS_IPV6_UDP_EX)       ? FM10K_MRQC_UDP_IPV6 : 0;
2192
2193         /* If the mapping doesn't fit any supported, return */
2194         if (mrqc == 0)
2195                 return -EINVAL;
2196
2197         if (key != NULL)
2198                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2199                         FM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);
2200
2201         FM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);
2202
2203         return 0;
2204 }
2205
2206 static int
2207 fm10k_rss_hash_conf_get(struct rte_eth_dev *dev,
2208         struct rte_eth_rss_conf *rss_conf)
2209 {
2210         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2212         uint32_t mrqc;
2213         uint64_t hf;
2214         int i;
2215
2216         PMD_INIT_FUNC_TRACE();
2217
2218         if (key && (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *
2219                                 FM10K_RSSRK_ENTRIES_PER_REG))
2220                 return -EINVAL;
2221
2222         if (key != NULL)
2223                 for (i = 0; i < FM10K_RSSRK_SIZE; ++i)
2224                         key[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));
2225
2226         mrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));
2227         hf = 0;
2228         hf |= (mrqc & FM10K_MRQC_IPV4)     ? ETH_RSS_IPV4              : 0;
2229         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6              : 0;
2230         hf |= (mrqc & FM10K_MRQC_IPV6)     ? ETH_RSS_IPV6_EX           : 0;
2231         hf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP  : 0;
2232         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP  : 0;
2233         hf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX       : 0;
2234         hf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP  : 0;
2235         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP  : 0;
2236         hf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX       : 0;
2237
2238         rss_conf->rss_hf = hf;
2239
2240         return 0;
2241 }
2242
2243 static void
2244 fm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)
2245 {
2246         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2248
2249         /* Bind all local non-queue interrupt to vector 0 */
2250         int_map |= FM10K_MISC_VEC_ID;
2251
2252         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2253         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2254         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2255         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2256         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2257         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2258
2259         /* Enable misc causes */
2260         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
2261                                 FM10K_EIMR_ENABLE(THI_FAULT) |
2262                                 FM10K_EIMR_ENABLE(FUM_FAULT) |
2263                                 FM10K_EIMR_ENABLE(MAILBOX) |
2264                                 FM10K_EIMR_ENABLE(SWITCHREADY) |
2265                                 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
2266                                 FM10K_EIMR_ENABLE(SRAMERROR) |
2267                                 FM10K_EIMR_ENABLE(VFLR));
2268
2269         /* Enable ITR 0 */
2270         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2271                                         FM10K_ITR_MASK_CLEAR);
2272         FM10K_WRITE_FLUSH(hw);
2273 }
2274
2275 static void
2276 fm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)
2277 {
2278         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2280
2281         int_map |= FM10K_MISC_VEC_ID;
2282
2283         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_mailbox), int_map);
2284         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), int_map);
2285         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), int_map);
2286         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_switch_event), int_map);
2287         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_sram), int_map);
2288         FM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_vflr), int_map);
2289
2290         /* Disable misc causes */
2291         FM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |
2292                                 FM10K_EIMR_DISABLE(THI_FAULT) |
2293                                 FM10K_EIMR_DISABLE(FUM_FAULT) |
2294                                 FM10K_EIMR_DISABLE(MAILBOX) |
2295                                 FM10K_EIMR_DISABLE(SWITCHREADY) |
2296                                 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
2297                                 FM10K_EIMR_DISABLE(SRAMERROR) |
2298                                 FM10K_EIMR_DISABLE(VFLR));
2299
2300         /* Disable ITR 0 */
2301         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);
2302         FM10K_WRITE_FLUSH(hw);
2303 }
2304
2305 static void
2306 fm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)
2307 {
2308         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309         uint32_t int_map = FM10K_INT_MAP_IMMEDIATE;
2310
2311         /* Bind all local non-queue interrupt to vector 0 */
2312         int_map |= FM10K_MISC_VEC_ID;
2313
2314         /* Only INT 0 available, other 15 are reserved. */
2315         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2316
2317         /* Enable ITR 0 */
2318         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2319                                         FM10K_ITR_MASK_CLEAR);
2320         FM10K_WRITE_FLUSH(hw);
2321 }
2322
2323 static void
2324 fm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)
2325 {
2326         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2327         uint32_t int_map = FM10K_INT_MAP_DISABLE;
2328
2329         int_map |= FM10K_MISC_VEC_ID;
2330
2331         /* Only INT 0 available, other 15 are reserved. */
2332         FM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);
2333
2334         /* Disable ITR 0 */
2335         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);
2336         FM10K_WRITE_FLUSH(hw);
2337 }
2338
2339 static int
2340 fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2341 {
2342         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2344
2345         /* Enable ITR */
2346         if (hw->mac.type == fm10k_mac_pf)
2347                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2348                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2349         else
2350                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2351                         FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR);
2352         rte_intr_enable(&pdev->intr_handle);
2353         return 0;
2354 }
2355
2356 static int
2357 fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2358 {
2359         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2361
2362         /* Disable ITR */
2363         if (hw->mac.type == fm10k_mac_pf)
2364                 FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(pdev, queue_id)),
2365                         FM10K_ITR_MASK_SET);
2366         else
2367                 FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(pdev, queue_id)),
2368                         FM10K_ITR_MASK_SET);
2369         return 0;
2370 }
2371
2372 static int
2373 fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2374 {
2375         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2376         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2377         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2378         uint32_t intr_vector, vec;
2379         uint16_t queue_id;
2380         int result = 0;
2381
2382         /* fm10k needs one separate interrupt for mailbox,
2383          * so only drivers which support multiple interrupt vectors
2384          * e.g. vfio-pci can work for fm10k interrupt mode
2385          */
2386         if (!rte_intr_cap_multiple(intr_handle) ||
2387                         dev->data->dev_conf.intr_conf.rxq == 0)
2388                 return result;
2389
2390         intr_vector = dev->data->nb_rx_queues;
2391
2392         /* disable interrupt first */
2393         rte_intr_disable(intr_handle);
2394         if (hw->mac.type == fm10k_mac_pf)
2395                 fm10k_dev_disable_intr_pf(dev);
2396         else
2397                 fm10k_dev_disable_intr_vf(dev);
2398
2399         if (rte_intr_efd_enable(intr_handle, intr_vector)) {
2400                 PMD_INIT_LOG(ERR, "Failed to init event fd");
2401                 result = -EIO;
2402         }
2403
2404         if (rte_intr_dp_is_en(intr_handle) && !result) {
2405                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
2406                         dev->data->nb_rx_queues * sizeof(int), 0);
2407                 if (intr_handle->intr_vec) {
2408                         for (queue_id = 0, vec = FM10K_RX_VEC_START;
2409                                         queue_id < dev->data->nb_rx_queues;
2410                                         queue_id++) {
2411                                 intr_handle->intr_vec[queue_id] = vec;
2412                                 if (vec < intr_handle->nb_efd - 1
2413                                                 + FM10K_RX_VEC_START)
2414                                         vec++;
2415                         }
2416                 } else {
2417                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2418                                 " intr_vec", dev->data->nb_rx_queues);
2419                         rte_intr_efd_disable(intr_handle);
2420                         result = -ENOMEM;
2421                 }
2422         }
2423
2424         if (hw->mac.type == fm10k_mac_pf)
2425                 fm10k_dev_enable_intr_pf(dev);
2426         else
2427                 fm10k_dev_enable_intr_vf(dev);
2428         rte_intr_enable(intr_handle);
2429         hw->mac.ops.update_int_moderator(hw);
2430         return result;
2431 }
2432
2433 static int
2434 fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)
2435 {
2436         struct fm10k_fault fault;
2437         int err;
2438         const char *estr = "Unknown error";
2439
2440         /* Process PCA fault */
2441         if (eicr & FM10K_EICR_PCA_FAULT) {
2442                 err = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);
2443                 if (err)
2444                         goto error;
2445                 switch (fault.type) {
2446                 case PCA_NO_FAULT:
2447                         estr = "PCA_NO_FAULT"; break;
2448                 case PCA_UNMAPPED_ADDR:
2449                         estr = "PCA_UNMAPPED_ADDR"; break;
2450                 case PCA_BAD_QACCESS_PF:
2451                         estr = "PCA_BAD_QACCESS_PF"; break;
2452                 case PCA_BAD_QACCESS_VF:
2453                         estr = "PCA_BAD_QACCESS_VF"; break;
2454                 case PCA_MALICIOUS_REQ:
2455                         estr = "PCA_MALICIOUS_REQ"; break;
2456                 case PCA_POISONED_TLP:
2457                         estr = "PCA_POISONED_TLP"; break;
2458                 case PCA_TLP_ABORT:
2459                         estr = "PCA_TLP_ABORT"; break;
2460                 default:
2461                         goto error;
2462                 }
2463                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2464                         estr, fault.func ? "VF" : "PF", fault.func,
2465                         fault.address, fault.specinfo);
2466         }
2467
2468         /* Process THI fault */
2469         if (eicr & FM10K_EICR_THI_FAULT) {
2470                 err = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);
2471                 if (err)
2472                         goto error;
2473                 switch (fault.type) {
2474                 case THI_NO_FAULT:
2475                         estr = "THI_NO_FAULT"; break;
2476                 case THI_MAL_DIS_Q_FAULT:
2477                         estr = "THI_MAL_DIS_Q_FAULT"; break;
2478                 default:
2479                         goto error;
2480                 }
2481                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2482                         estr, fault.func ? "VF" : "PF", fault.func,
2483                         fault.address, fault.specinfo);
2484         }
2485
2486         /* Process FUM fault */
2487         if (eicr & FM10K_EICR_FUM_FAULT) {
2488                 err = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);
2489                 if (err)
2490                         goto error;
2491                 switch (fault.type) {
2492                 case FUM_NO_FAULT:
2493                         estr = "FUM_NO_FAULT"; break;
2494                 case FUM_UNMAPPED_ADDR:
2495                         estr = "FUM_UNMAPPED_ADDR"; break;
2496                 case FUM_POISONED_TLP:
2497                         estr = "FUM_POISONED_TLP"; break;
2498                 case FUM_BAD_VF_QACCESS:
2499                         estr = "FUM_BAD_VF_QACCESS"; break;
2500                 case FUM_ADD_DECODE_ERR:
2501                         estr = "FUM_ADD_DECODE_ERR"; break;
2502                 case FUM_RO_ERROR:
2503                         estr = "FUM_RO_ERROR"; break;
2504                 case FUM_QPRC_CRC_ERROR:
2505                         estr = "FUM_QPRC_CRC_ERROR"; break;
2506                 case FUM_CSR_TIMEOUT:
2507                         estr = "FUM_CSR_TIMEOUT"; break;
2508                 case FUM_INVALID_TYPE:
2509                         estr = "FUM_INVALID_TYPE"; break;
2510                 case FUM_INVALID_LENGTH:
2511                         estr = "FUM_INVALID_LENGTH"; break;
2512                 case FUM_INVALID_BE:
2513                         estr = "FUM_INVALID_BE"; break;
2514                 case FUM_INVALID_ALIGN:
2515                         estr = "FUM_INVALID_ALIGN"; break;
2516                 default:
2517                         goto error;
2518                 }
2519                 PMD_INIT_LOG(ERR, "%s: %s(%d) Addr:0x%"PRIx64" Spec: 0x%x",
2520                         estr, fault.func ? "VF" : "PF", fault.func,
2521                         fault.address, fault.specinfo);
2522         }
2523
2524         return 0;
2525 error:
2526         PMD_INIT_LOG(ERR, "Failed to handle fault event.");
2527         return err;
2528 }
2529
2530 /**
2531  * PF interrupt handler triggered by NIC for handling specific interrupt.
2532  *
2533  * @param handle
2534  *  Pointer to interrupt handle.
2535  * @param param
2536  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2537  *
2538  * @return
2539  *  void
2540  */
2541 static void
2542 fm10k_dev_interrupt_handler_pf(
2543                         struct rte_intr_handle *handle,
2544                         void *param)
2545 {
2546         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2547         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         uint32_t cause, status;
2549
2550         if (hw->mac.type != fm10k_mac_pf)
2551                 return;
2552
2553         cause = FM10K_READ_REG(hw, FM10K_EICR);
2554
2555         /* Handle PCI fault cases */
2556         if (cause & FM10K_EICR_FAULT_MASK) {
2557                 PMD_INIT_LOG(ERR, "INT: find fault!");
2558                 fm10k_dev_handle_fault(hw, cause);
2559         }
2560
2561         /* Handle switch up/down */
2562         if (cause & FM10K_EICR_SWITCHNOTREADY)
2563                 PMD_INIT_LOG(ERR, "INT: Switch is not ready");
2564
2565         if (cause & FM10K_EICR_SWITCHREADY)
2566                 PMD_INIT_LOG(INFO, "INT: Switch is ready");
2567
2568         /* Handle mailbox message */
2569         fm10k_mbx_lock(hw);
2570         hw->mbx.ops.process(hw, &hw->mbx);
2571         fm10k_mbx_unlock(hw);
2572
2573         /* Handle SRAM error */
2574         if (cause & FM10K_EICR_SRAMERROR) {
2575                 PMD_INIT_LOG(ERR, "INT: SRAM error on PEP");
2576
2577                 status = FM10K_READ_REG(hw, FM10K_SRAM_IP);
2578                 /* Write to clear pending bits */
2579                 FM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);
2580
2581                 /* Todo: print out error message after shared code  updates */
2582         }
2583
2584         /* Clear these 3 events if having any */
2585         cause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |
2586                  FM10K_EICR_SWITCHREADY;
2587         if (cause)
2588                 FM10K_WRITE_REG(hw, FM10K_EICR, cause);
2589
2590         /* Re-enable interrupt from device side */
2591         FM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |
2592                                         FM10K_ITR_MASK_CLEAR);
2593         /* Re-enable interrupt from host side */
2594         rte_intr_enable(handle);
2595 }
2596
2597 /**
2598  * VF interrupt handler triggered by NIC for handling specific interrupt.
2599  *
2600  * @param handle
2601  *  Pointer to interrupt handle.
2602  * @param param
2603  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2604  *
2605  * @return
2606  *  void
2607  */
2608 static void
2609 fm10k_dev_interrupt_handler_vf(
2610                         struct rte_intr_handle *handle,
2611                         void *param)
2612 {
2613         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2614         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615
2616         if (hw->mac.type != fm10k_mac_vf)
2617                 return;
2618
2619         /* Handle mailbox message if lock is acquired */
2620         fm10k_mbx_lock(hw);
2621         hw->mbx.ops.process(hw, &hw->mbx);
2622         fm10k_mbx_unlock(hw);
2623
2624         /* Re-enable interrupt from device side */
2625         FM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |
2626                                         FM10K_ITR_MASK_CLEAR);
2627         /* Re-enable interrupt from host side */
2628         rte_intr_enable(handle);
2629 }
2630
2631 /* Mailbox message handler in VF */
2632 static const struct fm10k_msg_data fm10k_msgdata_vf[] = {
2633         FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
2634         FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
2635         FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
2636         FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
2637 };
2638
2639 static int
2640 fm10k_setup_mbx_service(struct fm10k_hw *hw)
2641 {
2642         int err = 0;
2643
2644         /* Initialize mailbox lock */
2645         fm10k_mbx_initlock(hw);
2646
2647         /* Replace default message handler with new ones */
2648         if (hw->mac.type == fm10k_mac_vf)
2649                 err = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);
2650
2651         if (err) {
2652                 PMD_INIT_LOG(ERR, "Failed to register mailbox handler.err:%d",
2653                                 err);
2654                 return err;
2655         }
2656         /* Connect to SM for PF device or PF for VF device */
2657         return hw->mbx.ops.connect(hw, &hw->mbx);
2658 }
2659
2660 static void
2661 fm10k_close_mbx_service(struct fm10k_hw *hw)
2662 {
2663         /* Disconnect from SM for PF device or PF for VF device */
2664         hw->mbx.ops.disconnect(hw, &hw->mbx);
2665 }
2666
2667 static const struct eth_dev_ops fm10k_eth_dev_ops = {
2668         .dev_configure          = fm10k_dev_configure,
2669         .dev_start              = fm10k_dev_start,
2670         .dev_stop               = fm10k_dev_stop,
2671         .dev_close              = fm10k_dev_close,
2672         .promiscuous_enable     = fm10k_dev_promiscuous_enable,
2673         .promiscuous_disable    = fm10k_dev_promiscuous_disable,
2674         .allmulticast_enable    = fm10k_dev_allmulticast_enable,
2675         .allmulticast_disable   = fm10k_dev_allmulticast_disable,
2676         .stats_get              = fm10k_stats_get,
2677         .xstats_get             = fm10k_xstats_get,
2678         .xstats_get_names       = fm10k_xstats_get_names,
2679         .stats_reset            = fm10k_stats_reset,
2680         .xstats_reset           = fm10k_stats_reset,
2681         .link_update            = fm10k_link_update,
2682         .dev_infos_get          = fm10k_dev_infos_get,
2683         .dev_supported_ptypes_get = fm10k_dev_supported_ptypes_get,
2684         .vlan_filter_set        = fm10k_vlan_filter_set,
2685         .vlan_offload_set       = fm10k_vlan_offload_set,
2686         .mac_addr_add           = fm10k_macaddr_add,
2687         .mac_addr_remove        = fm10k_macaddr_remove,
2688         .rx_queue_start         = fm10k_dev_rx_queue_start,
2689         .rx_queue_stop          = fm10k_dev_rx_queue_stop,
2690         .tx_queue_start         = fm10k_dev_tx_queue_start,
2691         .tx_queue_stop          = fm10k_dev_tx_queue_stop,
2692         .rx_queue_setup         = fm10k_rx_queue_setup,
2693         .rx_queue_release       = fm10k_rx_queue_release,
2694         .tx_queue_setup         = fm10k_tx_queue_setup,
2695         .tx_queue_release       = fm10k_tx_queue_release,
2696         .rx_descriptor_done     = fm10k_dev_rx_descriptor_done,
2697         .rx_queue_intr_enable   = fm10k_dev_rx_queue_intr_enable,
2698         .rx_queue_intr_disable  = fm10k_dev_rx_queue_intr_disable,
2699         .reta_update            = fm10k_reta_update,
2700         .reta_query             = fm10k_reta_query,
2701         .rss_hash_update        = fm10k_rss_hash_update,
2702         .rss_hash_conf_get      = fm10k_rss_hash_conf_get,
2703 };
2704
2705 static int ftag_check_handler(__rte_unused const char *key,
2706                 const char *value, __rte_unused void *opaque)
2707 {
2708         if (strcmp(value, "1"))
2709                 return -1;
2710
2711         return 0;
2712 }
2713
2714 static int
2715 fm10k_check_ftag(struct rte_devargs *devargs)
2716 {
2717         struct rte_kvargs *kvlist;
2718         const char *ftag_key = "enable_ftag";
2719
2720         if (devargs == NULL)
2721                 return 0;
2722
2723         kvlist = rte_kvargs_parse(devargs->args, NULL);
2724         if (kvlist == NULL)
2725                 return 0;
2726
2727         if (!rte_kvargs_count(kvlist, ftag_key)) {
2728                 rte_kvargs_free(kvlist);
2729                 return 0;
2730         }
2731         /* FTAG is enabled when there's key-value pair: enable_ftag=1 */
2732         if (rte_kvargs_process(kvlist, ftag_key,
2733                                 ftag_check_handler, NULL) < 0) {
2734                 rte_kvargs_free(kvlist);
2735                 return 0;
2736         }
2737         rte_kvargs_free(kvlist);
2738
2739         return 1;
2740 }
2741
2742 static void __attribute__((cold))
2743 fm10k_set_tx_function(struct rte_eth_dev *dev)
2744 {
2745         struct fm10k_tx_queue *txq;
2746         int i;
2747         int use_sse = 1;
2748         uint16_t tx_ftag_en = 0;
2749
2750         if (fm10k_check_ftag(dev->device->devargs))
2751                 tx_ftag_en = 1;
2752
2753         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2754                 txq = dev->data->tx_queues[i];
2755                 txq->tx_ftag_en = tx_ftag_en;
2756                 /* Check if Vector Tx is satisfied */
2757                 if (fm10k_tx_vec_condition_check(txq))
2758                         use_sse = 0;
2759         }
2760
2761         if (use_sse) {
2762                 PMD_INIT_LOG(DEBUG, "Use vector Tx func");
2763                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2764                         txq = dev->data->tx_queues[i];
2765                         fm10k_txq_vec_setup(txq);
2766                 }
2767                 dev->tx_pkt_burst = fm10k_xmit_pkts_vec;
2768         } else {
2769                 dev->tx_pkt_burst = fm10k_xmit_pkts;
2770                 PMD_INIT_LOG(DEBUG, "Use regular Tx func");
2771         }
2772 }
2773
2774 static void __attribute__((cold))
2775 fm10k_set_rx_function(struct rte_eth_dev *dev)
2776 {
2777         struct fm10k_dev_info *dev_info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2778         uint16_t i, rx_using_sse;
2779         uint16_t rx_ftag_en = 0;
2780
2781         if (fm10k_check_ftag(dev->device->devargs))
2782                 rx_ftag_en = 1;
2783
2784         /* In order to allow Vector Rx there are a few configuration
2785          * conditions to be met.
2786          */
2787         if (!fm10k_rx_vec_condition_check(dev) &&
2788                         dev_info->rx_vec_allowed && !rx_ftag_en) {
2789                 if (dev->data->scattered_rx)
2790                         dev->rx_pkt_burst = fm10k_recv_scattered_pkts_vec;
2791                 else
2792                         dev->rx_pkt_burst = fm10k_recv_pkts_vec;
2793         } else if (dev->data->scattered_rx)
2794                 dev->rx_pkt_burst = fm10k_recv_scattered_pkts;
2795         else
2796                 dev->rx_pkt_burst = fm10k_recv_pkts;
2797
2798         rx_using_sse =
2799                 (dev->rx_pkt_burst == fm10k_recv_scattered_pkts_vec ||
2800                 dev->rx_pkt_burst == fm10k_recv_pkts_vec);
2801
2802         if (rx_using_sse)
2803                 PMD_INIT_LOG(DEBUG, "Use vector Rx func");
2804         else
2805                 PMD_INIT_LOG(DEBUG, "Use regular Rx func");
2806
2807         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2808                 struct fm10k_rx_queue *rxq = dev->data->rx_queues[i];
2809
2810                 rxq->rx_using_sse = rx_using_sse;
2811                 rxq->rx_ftag_en = rx_ftag_en;
2812         }
2813 }
2814
2815 static void
2816 fm10k_params_init(struct rte_eth_dev *dev)
2817 {
2818         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         struct fm10k_dev_info *info = FM10K_DEV_PRIVATE_TO_INFO(dev);
2820
2821         /* Inialize bus info. Normally we would call fm10k_get_bus_info(), but
2822          * there is no way to get link status without reading BAR4.  Until this
2823          * works, assume we have maximum bandwidth.
2824          * @todo - fix bus info
2825          */
2826         hw->bus_caps.speed = fm10k_bus_speed_8000;
2827         hw->bus_caps.width = fm10k_bus_width_pcie_x8;
2828         hw->bus_caps.payload = fm10k_bus_payload_512;
2829         hw->bus.speed = fm10k_bus_speed_8000;
2830         hw->bus.width = fm10k_bus_width_pcie_x8;
2831         hw->bus.payload = fm10k_bus_payload_256;
2832
2833         info->rx_vec_allowed = true;
2834 }
2835
2836 static int
2837 eth_fm10k_dev_init(struct rte_eth_dev *dev)
2838 {
2839         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
2841         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
2842         int diag, i;
2843         struct fm10k_macvlan_filter_info *macvlan;
2844
2845         PMD_INIT_FUNC_TRACE();
2846
2847         dev->dev_ops = &fm10k_eth_dev_ops;
2848         dev->rx_pkt_burst = &fm10k_recv_pkts;
2849         dev->tx_pkt_burst = &fm10k_xmit_pkts;
2850
2851         /* only initialize in the primary process */
2852         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2853                 return 0;
2854
2855         rte_eth_copy_pci_info(dev, pdev);
2856
2857         macvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);
2858         memset(macvlan, 0, sizeof(*macvlan));
2859         /* Vendor and Device ID need to be set before init of shared code */
2860         memset(hw, 0, sizeof(*hw));
2861         hw->device_id = pdev->id.device_id;
2862         hw->vendor_id = pdev->id.vendor_id;
2863         hw->subsystem_device_id = pdev->id.subsystem_device_id;
2864         hw->subsystem_vendor_id = pdev->id.subsystem_vendor_id;
2865         hw->revision_id = 0;
2866         hw->hw_addr = (void *)pdev->mem_resource[0].addr;
2867         if (hw->hw_addr == NULL) {
2868                 PMD_INIT_LOG(ERR, "Bad mem resource."
2869                         " Try to blacklist unused devices.");
2870                 return -EIO;
2871         }
2872
2873         /* Store fm10k_adapter pointer */
2874         hw->back = dev->data->dev_private;
2875
2876         /* Initialize the shared code */
2877         diag = fm10k_init_shared_code(hw);
2878         if (diag != FM10K_SUCCESS) {
2879                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
2880                 return -EIO;
2881         }
2882
2883         /* Initialize parameters */
2884         fm10k_params_init(dev);
2885
2886         /* Initialize the hw */
2887         diag = fm10k_init_hw(hw);
2888         if (diag != FM10K_SUCCESS) {
2889                 PMD_INIT_LOG(ERR, "Hardware init failed: %d", diag);
2890                 return -EIO;
2891         }
2892
2893         /* Initialize MAC address(es) */
2894         dev->data->mac_addrs = rte_zmalloc("fm10k",
2895                         ETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);
2896         if (dev->data->mac_addrs == NULL) {
2897                 PMD_INIT_LOG(ERR, "Cannot allocate memory for MAC addresses");
2898                 return -ENOMEM;
2899         }
2900
2901         diag = fm10k_read_mac_addr(hw);
2902
2903         ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2904                         &dev->data->mac_addrs[0]);
2905
2906         if (diag != FM10K_SUCCESS ||
2907                 !is_valid_assigned_ether_addr(dev->data->mac_addrs)) {
2908
2909                 /* Generate a random addr */
2910                 eth_random_addr(hw->mac.addr);
2911                 memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
2912                 ether_addr_copy((const struct ether_addr *)hw->mac.addr,
2913                 &dev->data->mac_addrs[0]);
2914         }
2915
2916         /* Reset the hw statistics */
2917         fm10k_stats_reset(dev);
2918
2919         /* Reset the hw */
2920         diag = fm10k_reset_hw(hw);
2921         if (diag != FM10K_SUCCESS) {
2922                 PMD_INIT_LOG(ERR, "Hardware reset failed: %d", diag);
2923                 return -EIO;
2924         }
2925
2926         /* Setup mailbox service */
2927         diag = fm10k_setup_mbx_service(hw);
2928         if (diag != FM10K_SUCCESS) {
2929                 PMD_INIT_LOG(ERR, "Failed to setup mailbox: %d", diag);
2930                 return -EIO;
2931         }
2932
2933         /*PF/VF has different interrupt handling mechanism */
2934         if (hw->mac.type == fm10k_mac_pf) {
2935                 /* register callback func to eal lib */
2936                 rte_intr_callback_register(intr_handle,
2937                         fm10k_dev_interrupt_handler_pf, (void *)dev);
2938
2939                 /* enable MISC interrupt */
2940                 fm10k_dev_enable_intr_pf(dev);
2941         } else { /* VF */
2942                 rte_intr_callback_register(intr_handle,
2943                         fm10k_dev_interrupt_handler_vf, (void *)dev);
2944
2945                 fm10k_dev_enable_intr_vf(dev);
2946         }
2947
2948         /* Enable intr after callback registered */
2949         rte_intr_enable(intr_handle);
2950
2951         hw->mac.ops.update_int_moderator(hw);
2952
2953         /* Make sure Switch Manager is ready before going forward. */
2954         if (hw->mac.type == fm10k_mac_pf) {
2955                 int switch_ready = 0;
2956
2957                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2958                         fm10k_mbx_lock(hw);
2959                         hw->mac.ops.get_host_state(hw, &switch_ready);
2960                         fm10k_mbx_unlock(hw);
2961                         if (switch_ready)
2962                                 break;
2963                         /* Delay some time to acquire async LPORT_MAP info. */
2964                         rte_delay_us(WAIT_SWITCH_MSG_US);
2965                 }
2966
2967                 if (switch_ready == 0) {
2968                         PMD_INIT_LOG(ERR, "switch is not ready");
2969                         return -1;
2970                 }
2971         }
2972
2973         /*
2974          * Below function will trigger operations on mailbox, acquire lock to
2975          * avoid race condition from interrupt handler. Operations on mailbox
2976          * FIFO will trigger interrupt to PF/SM, in which interrupt handler
2977          * will handle and generate an interrupt to our side. Then,  FIFO in
2978          * mailbox will be touched.
2979          */
2980         fm10k_mbx_lock(hw);
2981         /* Enable port first */
2982         hw->mac.ops.update_lport_state(hw, hw->mac.dglort_map,
2983                                         MAX_LPORT_NUM, 1);
2984
2985         /* Set unicast mode by default. App can change to other mode in other
2986          * API func.
2987          */
2988         hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,
2989                                         FM10K_XCAST_MODE_NONE);
2990
2991         fm10k_mbx_unlock(hw);
2992
2993         /* Make sure default VID is ready before going forward. */
2994         if (hw->mac.type == fm10k_mac_pf) {
2995                 for (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {
2996                         if (hw->mac.default_vid)
2997                                 break;
2998                         /* Delay some time to acquire async port VLAN info. */
2999                         rte_delay_us(WAIT_SWITCH_MSG_US);
3000                 }
3001
3002                 if (!hw->mac.default_vid) {
3003                         PMD_INIT_LOG(ERR, "default VID is not ready");
3004                         return -1;
3005                 }
3006         }
3007
3008         /* Add default mac address */
3009         fm10k_MAC_filter_set(dev, hw->mac.addr, true,
3010                 MAIN_VSI_POOL_NUMBER);
3011
3012         return 0;
3013 }
3014
3015 static int
3016 eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
3017 {
3018         struct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3019         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(dev->device);
3020         struct rte_intr_handle *intr_handle = &pdev->intr_handle;
3021         PMD_INIT_FUNC_TRACE();
3022
3023         /* only uninitialize in the primary process */
3024         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3025                 return 0;
3026
3027         /* safe to close dev here */
3028         fm10k_dev_close(dev);
3029
3030         dev->dev_ops = NULL;
3031         dev->rx_pkt_burst = NULL;
3032         dev->tx_pkt_burst = NULL;
3033
3034         /* disable uio/vfio intr */
3035         rte_intr_disable(intr_handle);
3036
3037         /*PF/VF has different interrupt handling mechanism */
3038         if (hw->mac.type == fm10k_mac_pf) {
3039                 /* disable interrupt */
3040                 fm10k_dev_disable_intr_pf(dev);
3041
3042                 /* unregister callback func to eal lib */
3043                 rte_intr_callback_unregister(intr_handle,
3044                         fm10k_dev_interrupt_handler_pf, (void *)dev);
3045         } else {
3046                 /* disable interrupt */
3047                 fm10k_dev_disable_intr_vf(dev);
3048
3049                 rte_intr_callback_unregister(intr_handle,
3050                         fm10k_dev_interrupt_handler_vf, (void *)dev);
3051         }
3052
3053         /* free mac memory */
3054         if (dev->data->mac_addrs) {
3055                 rte_free(dev->data->mac_addrs);
3056                 dev->data->mac_addrs = NULL;
3057         }
3058
3059         memset(hw, 0, sizeof(*hw));
3060
3061         return 0;
3062 }
3063
3064 /*
3065  * The set of PCI devices this driver supports. This driver will enable both PF
3066  * and SRIOV-VF devices.
3067  */
3068 static const struct rte_pci_id pci_id_fm10k_map[] = {
3069         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
3070         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
3071         { RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
3072         { .vendor_id = 0, /* sentinel */ },
3073 };
3074
3075 static struct eth_driver rte_pmd_fm10k = {
3076         .pci_drv = {
3077                 .id_table = pci_id_fm10k_map,
3078                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3079                         RTE_PCI_DRV_DETACHABLE,
3080                 .probe = rte_eth_dev_pci_probe,
3081                 .remove = rte_eth_dev_pci_remove,
3082         },
3083         .eth_dev_init = eth_fm10k_dev_init,
3084         .eth_dev_uninit = eth_fm10k_dev_uninit,
3085         .dev_private_size = sizeof(struct fm10k_adapter),
3086 };
3087
3088 RTE_PMD_REGISTER_PCI(net_fm10k, rte_pmd_fm10k.pci_drv);
3089 RTE_PMD_REGISTER_PCI_TABLE(net_fm10k, pci_id_fm10k_map);
3090 RTE_PMD_REGISTER_KMOD_DEP(net_fm10k, "* igb_uio | uio_pci_generic | vfio");