drivers/net/fm10k/fm10k_rxtx_vec.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013-2015 Intel Corporation
   3  */
   4
   5 #include <inttypes.h>
   6
   7 #include <ethdev_driver.h>
   8 #include <rte_common.h>
   9 #include "fm10k.h"
  10 #include "base/fm10k_type.h"
  11
  12 #include <tmmintrin.h>
  13
  14 #ifndef __INTEL_COMPILER
  15 #pragma GCC diagnostic ignored "-Wcast-qual"
  16 #endif
  17
  18 static void
  19 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq);
  20
  21 /* Handling the offload flags (olflags) field takes computation
  22  * time when receiving packets. Therefore we provide a flag to disable
  23  * the processing of the olflags field when they are not needed. This
  24  * gives improved performance, at the cost of losing the offload info
  25  * in the received packet
  26  */
  27 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
  28
  29 /* Vlan present flag shift */
  30 #define VP_SHIFT     (2)
  31 /* L3 type shift */
  32 #define L3TYPE_SHIFT     (4)
  33 /* L4 type shift */
  34 #define L4TYPE_SHIFT     (7)
  35 /* HBO flag shift */
  36 #define HBOFLAG_SHIFT     (10)
  37 /* RXE flag shift */
  38 #define RXEFLAG_SHIFT     (13)
  39 /* IPE/L4E flag shift */
  40 #define L3L4EFLAG_SHIFT     (14)
  41 /* shift RTE_MBUF_F_RX_L4_CKSUM_GOOD into one byte by 1 bit */
  42 #define CKSUM_SHIFT     (1)
  43
  44 static inline void
  45 fm10k_desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
  46 {
  47         __m128i ptype0, ptype1, vtag0, vtag1, eflag0, eflag1, cksumflag;
  48         union {
  49                 uint16_t e[4];
  50                 uint64_t dword;
  51         } vol;
  52
  53         const __m128i pkttype_msk = _mm_set_epi16(
  54                         0x0000, 0x0000, 0x0000, 0x0000,
  55                         RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
  56                         RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
  57                         RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
  58                         RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED);
  59
  60         /* mask everything except rss type */
  61         const __m128i rsstype_msk = _mm_set_epi16(
  62                         0x0000, 0x0000, 0x0000, 0x0000,
  63                         0x000F, 0x000F, 0x000F, 0x000F);
  64
  65         /* mask for HBO and RXE flag flags */
  66         const __m128i rxe_msk = _mm_set_epi16(
  67                         0x0000, 0x0000, 0x0000, 0x0000,
  68                         0x0001, 0x0001, 0x0001, 0x0001);
  69
  70         /* mask the lower byte of ol_flags */
  71         const __m128i ol_flags_msk = _mm_set_epi16(
  72                         0x0000, 0x0000, 0x0000, 0x0000,
  73                         0x00FF, 0x00FF, 0x00FF, 0x00FF);
  74
  75         const __m128i l3l4cksum_flag = _mm_set_epi8(0, 0, 0, 0,
  76                         0, 0, 0, 0,
  77                         0, 0, 0, 0,
  78                         (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
  79                         (RTE_MBUF_F_RX_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT,
  80                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> CKSUM_SHIFT,
  81                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> CKSUM_SHIFT);
  82
  83         const __m128i rxe_flag = _mm_set_epi8(0, 0, 0, 0,
  84                         0, 0, 0, 0,
  85                         0, 0, 0, 0,
  86                         0, 0, 0, 0);
  87
  88         /* map rss type to rss hash flag */
  89         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
  90                         0, 0, 0, RTE_MBUF_F_RX_RSS_HASH,
  91                         RTE_MBUF_F_RX_RSS_HASH, 0, RTE_MBUF_F_RX_RSS_HASH, 0,
  92                         RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH,
  93                         RTE_MBUF_F_RX_RSS_HASH, 0);
  94
  95         /* Calculate RSS_hash and Vlan fields */
  96         ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
  97         ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
  98         vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
  99         vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
 100
 101         ptype0 = _mm_unpacklo_epi32(ptype0, ptype1);
 102         ptype0 = _mm_and_si128(ptype0, rsstype_msk);
 103         ptype0 = _mm_shuffle_epi8(rss_flags, ptype0);
 104
 105         vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
 106         eflag0 = vtag1;
 107         cksumflag = vtag1;
 108         vtag1 = _mm_srli_epi16(vtag1, VP_SHIFT);
 109         vtag1 = _mm_and_si128(vtag1, pkttype_msk);
 110
 111         vtag1 = _mm_or_si128(ptype0, vtag1);
 112
 113         /* Process err flags, simply set RECIP_ERR bit if HBO/IXE is set */
 114         eflag1 = _mm_srli_epi16(eflag0, RXEFLAG_SHIFT);
 115         eflag0 = _mm_srli_epi16(eflag0, HBOFLAG_SHIFT);
 116         eflag0 = _mm_or_si128(eflag0, eflag1);
 117         eflag0 = _mm_and_si128(eflag0, rxe_msk);
 118         eflag0 = _mm_shuffle_epi8(rxe_flag, eflag0);
 119
 120         vtag1 = _mm_or_si128(eflag0, vtag1);
 121
 122         /* Process L4/L3 checksum error flags */
 123         cksumflag = _mm_srli_epi16(cksumflag, L3L4EFLAG_SHIFT);
 124         cksumflag = _mm_shuffle_epi8(l3l4cksum_flag, cksumflag);
 125
 126         /* clean the higher byte and shift back the flag bits */
 127         cksumflag = _mm_and_si128(cksumflag, ol_flags_msk);
 128         cksumflag = _mm_slli_epi16(cksumflag, CKSUM_SHIFT);
 129         vtag1 = _mm_or_si128(cksumflag, vtag1);
 130
 131         vol.dword = _mm_cvtsi128_si64(vtag1);
 132
 133         rx_pkts[0]->ol_flags = vol.e[0];
 134         rx_pkts[1]->ol_flags = vol.e[1];
 135         rx_pkts[2]->ol_flags = vol.e[2];
 136         rx_pkts[3]->ol_flags = vol.e[3];
 137 }
 138
 139 /* @note: When this function is changed, make corresponding change to
 140  * fm10k_dev_supported_ptypes_get().
 141  */
 142 static inline void
 143 fm10k_desc_to_pktype_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
 144 {
 145         __m128i l3l4type0, l3l4type1, l3type, l4type;
 146         union {
 147                 uint16_t e[4];
 148                 uint64_t dword;
 149         } vol;
 150
 151         /* L3 pkt type mask  Bit4 to Bit6 */
 152         const __m128i l3type_msk = _mm_set_epi16(
 153                         0x0000, 0x0000, 0x0000, 0x0000,
 154                         0x0070, 0x0070, 0x0070, 0x0070);
 155
 156         /* L4 pkt type mask  Bit7 to Bit9 */
 157         const __m128i l4type_msk = _mm_set_epi16(
 158                         0x0000, 0x0000, 0x0000, 0x0000,
 159                         0x0380, 0x0380, 0x0380, 0x0380);
 160
 161         /* convert RRC l3 type to mbuf format */
 162         const __m128i l3type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 163                         0, 0, 0, RTE_PTYPE_L3_IPV6_EXT,
 164                         RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV4_EXT,
 165                         RTE_PTYPE_L3_IPV4, 0);
 166
 167         /* Convert RRC l4 type to mbuf format l4type_flags shift-left 8 bits
 168          * to fill into8 bits length.
 169          */
 170         const __m128i l4type_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0, 0,
 171                         RTE_PTYPE_TUNNEL_GENEVE >> 8,
 172                         RTE_PTYPE_TUNNEL_NVGRE >> 8,
 173                         RTE_PTYPE_TUNNEL_VXLAN >> 8,
 174                         RTE_PTYPE_TUNNEL_GRE >> 8,
 175                         RTE_PTYPE_L4_UDP >> 8,
 176                         RTE_PTYPE_L4_TCP >> 8,
 177                         0);
 178
 179         l3l4type0 = _mm_unpacklo_epi16(descs[0], descs[1]);
 180         l3l4type1 = _mm_unpacklo_epi16(descs[2], descs[3]);
 181         l3l4type0 = _mm_unpacklo_epi32(l3l4type0, l3l4type1);
 182
 183         l3type = _mm_and_si128(l3l4type0, l3type_msk);
 184         l4type = _mm_and_si128(l3l4type0, l4type_msk);
 185
 186         l3type = _mm_srli_epi16(l3type, L3TYPE_SHIFT);
 187         l4type = _mm_srli_epi16(l4type, L4TYPE_SHIFT);
 188
 189         l3type = _mm_shuffle_epi8(l3type_flags, l3type);
 190         /* l4type_flags shift-left for 8 bits, need shift-right back */
 191         l4type = _mm_shuffle_epi8(l4type_flags, l4type);
 192
 193         l4type = _mm_slli_epi16(l4type, 8);
 194         l3l4type0 = _mm_or_si128(l3type, l4type);
 195         vol.dword = _mm_cvtsi128_si64(l3l4type0);
 196
 197         rx_pkts[0]->packet_type = vol.e[0];
 198         rx_pkts[1]->packet_type = vol.e[1];
 199         rx_pkts[2]->packet_type = vol.e[2];
 200         rx_pkts[3]->packet_type = vol.e[3];
 201 }
 202 #else
 203 #define fm10k_desc_to_olflags_v(desc, rx_pkts) do {} while (0)
 204 #define fm10k_desc_to_pktype_v(desc, rx_pkts) do {} while (0)
 205 #endif
 206
 207 int __rte_cold
 208 fm10k_rx_vec_condition_check(struct rte_eth_dev *dev)
 209 {
 210 #ifndef RTE_LIBRTE_IEEE1588
 211         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 212         struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
 213
 214 #ifndef RTE_FM10K_RX_OLFLAGS_ENABLE
 215         /* whithout rx ol_flags, no VP flag report */
 216         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
 217                 return -1;
 218 #endif
 219
 220         /* no fdir support */
 221         if (fconf->mode != RTE_FDIR_MODE_NONE)
 222                 return -1;
 223
 224         /* no header split support */
 225         if (rxmode->offloads & DEV_RX_OFFLOAD_HEADER_SPLIT)
 226                 return -1;
 227
 228         return 0;
 229 #else
 230         RTE_SET_USED(dev);
 231         return -1;
 232 #endif
 233 }
 234
 235 int __rte_cold
 236 fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)
 237 {
 238         uintptr_t p;
 239         struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 240
 241         mb_def.nb_segs = 1;
 242         /* data_off will be ajusted after new mbuf allocated for 512-byte
 243          * alignment.
 244          */
 245         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
 246         mb_def.port = rxq->port_id;
 247         rte_mbuf_refcnt_set(&mb_def, 1);
 248
 249         /* prevent compiler reordering: rearm_data covers previous fields */
 250         rte_compiler_barrier();
 251         p = (uintptr_t)&mb_def.rearm_data;
 252         rxq->mbuf_initializer = *(uint64_t *)p;
 253         return 0;
 254 }
 255
 256 static inline void
 257 fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)
 258 {
 259         int i;
 260         uint16_t rx_id;
 261         volatile union fm10k_rx_desc *rxdp;
 262         struct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];
 263         struct rte_mbuf *mb0, *mb1;
 264         __m128i head_off = _mm_set_epi64x(
 265                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,
 266                         RTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);
 267         __m128i dma_addr0, dma_addr1;
 268         /* Rx buffer need to be aligned with 512 byte */
 269         const __m128i hba_msk = _mm_set_epi64x(0,
 270                                 UINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);
 271
 272         rxdp = rxq->hw_ring + rxq->rxrearm_start;
 273
 274         /* Pull 'n' more MBUFs into the software ring */
 275         if (rte_mempool_get_bulk(rxq->mp,
 276                                  (void *)mb_alloc,
 277                                  RTE_FM10K_RXQ_REARM_THRESH) < 0) {
 278                 dma_addr0 = _mm_setzero_si128();
 279                 /* Clean up all the HW/SW ring content */
 280                 for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i++) {
 281                         mb_alloc[i] = &rxq->fake_mbuf;
 282                         _mm_store_si128((__m128i *)&rxdp[i].q,
 283                                                 dma_addr0);
 284                 }
 285
 286                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
 287                         RTE_FM10K_RXQ_REARM_THRESH;
 288                 return;
 289         }
 290
 291         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
 292         for (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {
 293                 __m128i vaddr0, vaddr1;
 294                 uintptr_t p0, p1;
 295
 296                 mb0 = mb_alloc[0];
 297                 mb1 = mb_alloc[1];
 298
 299                 /* Flush mbuf with pkt template.
 300                  * Data to be rearmed is 6 bytes long.
 301                  */
 302                 p0 = (uintptr_t)&mb0->rearm_data;
 303                 *(uint64_t *)p0 = rxq->mbuf_initializer;
 304                 p1 = (uintptr_t)&mb1->rearm_data;
 305                 *(uint64_t *)p1 = rxq->mbuf_initializer;
 306
 307                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
 308                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
 309                                 offsetof(struct rte_mbuf, buf_addr) + 8);
 310                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
 311                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
 312
 313                 /* convert pa to dma_addr hdr/data */
 314                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
 315                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
 316
 317                 /* add headroom to pa values */
 318                 dma_addr0 = _mm_add_epi64(dma_addr0, head_off);
 319                 dma_addr1 = _mm_add_epi64(dma_addr1, head_off);
 320
 321                 /* Do 512 byte alignment to satisfy HW requirement, in the
 322                  * meanwhile, set Header Buffer Address to zero.
 323                  */
 324                 dma_addr0 = _mm_and_si128(dma_addr0, hba_msk);
 325                 dma_addr1 = _mm_and_si128(dma_addr1, hba_msk);
 326
 327                 /* flush desc with pa dma_addr */
 328                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);
 329                 _mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);
 330
 331                 /* enforce 512B alignment on default Rx virtual addresses */
 332                 mb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr
 333                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 334                                 - (char *)mb0->buf_addr);
 335                 mb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr
 336                                 + RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 337                                 - (char *)mb1->buf_addr);
 338         }
 339
 340         rxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;
 341         if (rxq->rxrearm_start >= rxq->nb_desc)
 342                 rxq->rxrearm_start = 0;
 343
 344         rxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;
 345
 346         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 347                         (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));
 348
 349         /* Update the tail pointer on the NIC */
 350         FM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);
 351 }
 352
 353 void __rte_cold
 354 fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq)
 355 {
 356         const unsigned mask = rxq->nb_desc - 1;
 357         unsigned i;
 358
 359         if (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_desc)
 360                 return;
 361
 362         /* free all mbufs that are valid in the ring */
 363         if (rxq->rxrearm_nb == 0) {
 364                 for (i = 0; i < rxq->nb_desc; i++)
 365                         if (rxq->sw_ring[i] != NULL)
 366                                 rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 367         } else {
 368                 for (i = rxq->next_dd; i != rxq->rxrearm_start;
 369                                 i = (i + 1) & mask)
 370                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 371         }
 372         rxq->rxrearm_nb = rxq->nb_desc;
 373
 374         /* set all entries to NULL */
 375         memset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_desc);
 376 }
 377
 378 static inline uint16_t
 379 fm10k_recv_raw_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 380                 uint16_t nb_pkts, uint8_t *split_packet)
 381 {
 382         volatile union fm10k_rx_desc *rxdp;
 383         struct rte_mbuf **mbufp;
 384         uint16_t nb_pkts_recd;
 385         int pos;
 386         struct fm10k_rx_queue *rxq = rx_queue;
 387         uint64_t var;
 388         __m128i shuf_msk;
 389         __m128i dd_check, eop_check;
 390         uint16_t next_dd;
 391
 392         next_dd = rxq->next_dd;
 393
 394         /* Just the act of getting into the function from the application is
 395          * going to cost about 7 cycles
 396          */
 397         rxdp = rxq->hw_ring + next_dd;
 398
 399         rte_prefetch0(rxdp);
 400
 401         /* See if we need to rearm the RX queue - gives the prefetch a bit
 402          * of time to act
 403          */
 404         if (rxq->rxrearm_nb > RTE_FM10K_RXQ_REARM_THRESH)
 405                 fm10k_rxq_rearm(rxq);
 406
 407         /* Before we start moving massive data around, check to see if
 408          * there is actually a packet available
 409          */
 410         if (!(rxdp->d.staterr & FM10K_RXD_STATUS_DD))
 411                 return 0;
 412
 413         /* Vecotr RX will process 4 packets at a time, strip the unaligned
 414          * tails in case it's not multiple of 4.
 415          */
 416         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_FM10K_DESCS_PER_LOOP);
 417
 418         /* 4 packets DD mask */
 419         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
 420
 421         /* 4 packets EOP mask */
 422         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
 423
 424         /* mask to shuffle from desc. to mbuf */
 425         shuf_msk = _mm_set_epi8(
 426                 7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 427                 15, 14,      /* octet 14~15, low 16 bits vlan_macip */
 428                 13, 12,      /* octet 12~13, 16 bits data_len */
 429                 0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 430                 13, 12,      /* octet 12~13, low 16 bits pkt_len */
 431                 0xFF, 0xFF,  /* skip high 16 bits pkt_type */
 432                 0xFF, 0xFF   /* Skip pkt_type field in shuffle operation */
 433                 );
 434         /*
 435          * Compile-time verify the shuffle mask
 436          * NOTE: some field positions already verified above, but duplicated
 437          * here for completeness in case of future modifications.
 438          */
 439         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 440                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 441         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 442                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 443         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 444                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 445         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 446                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 447
 448         /* Cache is empty -> need to scan the buffer rings, but first move
 449          * the next 'n' mbufs into the cache
 450          */
 451         mbufp = &rxq->sw_ring[next_dd];
 452
 453         /* A. load 4 packet in one loop
 454          * [A*. mask out 4 unused dirty field in desc]
 455          * B. copy 4 mbuf point from swring to rx_pkts
 456          * C. calc the number of DD bits among the 4 packets
 457          * [C*. extract the end-of-packet bit, if requested]
 458          * D. fill info. from desc to mbuf
 459          */
 460         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 461                         pos += RTE_FM10K_DESCS_PER_LOOP,
 462                         rxdp += RTE_FM10K_DESCS_PER_LOOP) {
 463                 __m128i descs0[RTE_FM10K_DESCS_PER_LOOP];
 464                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
 465                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
 466                 __m128i mbp1;
 467                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 468 #if defined(RTE_ARCH_X86_64)
 469                 __m128i mbp2;
 470 #endif
 471
 472                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 473                 mbp1 = _mm_loadu_si128((__m128i *)&mbufp[pos]);
 474
 475                 /* Read desc statuses backwards to avoid race condition */
 476                 /* A.1 load 4 pkts desc */
 477                 descs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 478                 rte_compiler_barrier();
 479
 480                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 481                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 482
 483 #if defined(RTE_ARCH_X86_64)
 484                 /* B.1 load 2 64 bit mbuf poitns */
 485                 mbp2 = _mm_loadu_si128((__m128i *)&mbufp[pos+2]);
 486 #endif
 487
 488                 descs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 489                 rte_compiler_barrier();
 490                 /* B.1 load 2 mbuf point */
 491                 descs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 492                 rte_compiler_barrier();
 493                 descs0[0] = _mm_loadu_si128((__m128i *)(rxdp));
 494
 495 #if defined(RTE_ARCH_X86_64)
 496                 /* B.2 copy 2 mbuf point into rx_pkts  */
 497                 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
 498 #endif
 499
 500                 /* avoid compiler reorder optimization */
 501                 rte_compiler_barrier();
 502
 503                 if (split_packet) {
 504                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 505                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 506                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 507                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 508                 }
 509
 510                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 511                 pkt_mb4 = _mm_shuffle_epi8(descs0[3], shuf_msk);
 512                 pkt_mb3 = _mm_shuffle_epi8(descs0[2], shuf_msk);
 513
 514                 /* C.1 4=>2 filter staterr info only */
 515                 sterr_tmp2 = _mm_unpackhi_epi32(descs0[3], descs0[2]);
 516                 /* C.1 4=>2 filter staterr info only */
 517                 sterr_tmp1 = _mm_unpackhi_epi32(descs0[1], descs0[0]);
 518
 519                 /* set ol_flags with vlan packet type */
 520                 fm10k_desc_to_olflags_v(descs0, &rx_pkts[pos]);
 521
 522                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 523                 pkt_mb2 = _mm_shuffle_epi8(descs0[1], shuf_msk);
 524                 pkt_mb1 = _mm_shuffle_epi8(descs0[0], shuf_msk);
 525
 526                 /* C.2 get 4 pkts staterr value  */
 527                 zero = _mm_xor_si128(dd_check, dd_check);
 528                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 529
 530                 /* D.3 copy final 3,4 data to rx_pkts */
 531                 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
 532                                 pkt_mb4);
 533                 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
 534                                 pkt_mb3);
 535
 536                 /* C* extract and record EOP bit */
 537                 if (split_packet) {
 538                         __m128i eop_shuf_mask = _mm_set_epi8(
 539                                         0xFF, 0xFF, 0xFF, 0xFF,
 540                                         0xFF, 0xFF, 0xFF, 0xFF,
 541                                         0xFF, 0xFF, 0xFF, 0xFF,
 542                                         0x04, 0x0C, 0x00, 0x08
 543                                         );
 544
 545                         /* and with mask to extract bits, flipping 1-0 */
 546                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 547                         /* the staterr values are not in order, as the count
 548                          * count of dd bits doesn't care. However, for end of
 549                          * packet tracking, we do care, so shuffle. This also
 550                          * compresses the 32-bit values to 8-bit
 551                          */
 552                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 553                         /* store the resulting 32-bit value */
 554                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 555                         split_packet += RTE_FM10K_DESCS_PER_LOOP;
 556
 557                         /* zero-out next pointers */
 558                         rx_pkts[pos]->next = NULL;
 559                         rx_pkts[pos + 1]->next = NULL;
 560                         rx_pkts[pos + 2]->next = NULL;
 561                         rx_pkts[pos + 3]->next = NULL;
 562                 }
 563
 564                 /* C.3 calc available number of desc */
 565                 staterr = _mm_and_si128(staterr, dd_check);
 566                 staterr = _mm_packs_epi32(staterr, zero);
 567
 568                 /* D.3 copy final 1,2 data to rx_pkts */
 569                 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
 570                                 pkt_mb2);
 571                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 572                                 pkt_mb1);
 573
 574                 fm10k_desc_to_pktype_v(descs0, &rx_pkts[pos]);
 575
 576                 /* C.4 calc avaialbe number of desc */
 577                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 578                 nb_pkts_recd += var;
 579                 if (likely(var != RTE_FM10K_DESCS_PER_LOOP))
 580                         break;
 581         }
 582
 583         /* Update our internal tail pointer */
 584         rxq->next_dd = (uint16_t)(rxq->next_dd + nb_pkts_recd);
 585         rxq->next_dd = (uint16_t)(rxq->next_dd & (rxq->nb_desc - 1));
 586         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 587
 588         return nb_pkts_recd;
 589 }
 590
 591 /* vPMD receive routine
 592  *
 593  * Notice:
 594  * - don't support ol_flags for rss and csum err
 595  */
 596 uint16_t
 597 fm10k_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 598                 uint16_t nb_pkts)
 599 {
 600         return fm10k_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 601 }
 602
 603 static inline uint16_t
 604 fm10k_reassemble_packets(struct fm10k_rx_queue *rxq,
 605                 struct rte_mbuf **rx_bufs,
 606                 uint16_t nb_bufs, uint8_t *split_flags)
 607 {
 608         struct rte_mbuf *pkts[RTE_FM10K_MAX_RX_BURST]; /*finished pkts*/
 609         struct rte_mbuf *start = rxq->pkt_first_seg;
 610         struct rte_mbuf *end =  rxq->pkt_last_seg;
 611         unsigned pkt_idx, buf_idx;
 612
 613         for (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {
 614                 if (end != NULL) {
 615                         /* processing a split packet */
 616                         end->next = rx_bufs[buf_idx];
 617                         start->nb_segs++;
 618                         start->pkt_len += rx_bufs[buf_idx]->data_len;
 619                         end = end->next;
 620
 621                         if (!split_flags[buf_idx]) {
 622                                 /* it's the last packet of the set */
 623 #ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE
 624                                 start->hash = end->hash;
 625                                 start->ol_flags = end->ol_flags;
 626                                 start->packet_type = end->packet_type;
 627 #endif
 628                                 pkts[pkt_idx++] = start;
 629                                 start = end = NULL;
 630                         }
 631                 } else {
 632                         /* not processing a split packet */
 633                         if (!split_flags[buf_idx]) {
 634                                 /* not a split packet, save and skip */
 635                                 pkts[pkt_idx++] = rx_bufs[buf_idx];
 636                                 continue;
 637                         }
 638                         end = start = rx_bufs[buf_idx];
 639                 }
 640         }
 641
 642         /* save the partial packet for next time */
 643         rxq->pkt_first_seg = start;
 644         rxq->pkt_last_seg = end;
 645         memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
 646         return pkt_idx;
 647 }
 648
 649 /**
 650  * vPMD receive routine that reassembles single burst of 32 scattered packets
 651  *
 652  * Notice:
 653  * - don't support ol_flags for rss and csum err
 654  */
 655 static uint16_t
 656 fm10k_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 657                                uint16_t nb_pkts)
 658 {
 659         struct fm10k_rx_queue *rxq = rx_queue;
 660         uint8_t split_flags[RTE_FM10K_MAX_RX_BURST] = {0};
 661         unsigned i = 0;
 662
 663         /* Split_flags only can support max of RTE_FM10K_MAX_RX_BURST */
 664         nb_pkts = RTE_MIN(nb_pkts, RTE_FM10K_MAX_RX_BURST);
 665         /* get some new buffers */
 666         uint16_t nb_bufs = fm10k_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 667                         split_flags);
 668         if (nb_bufs == 0)
 669                 return 0;
 670
 671         /* happy day case, full burst + no packets to be joined */
 672         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 673
 674         if (rxq->pkt_first_seg == NULL &&
 675                         split_fl64[0] == 0 && split_fl64[1] == 0 &&
 676                         split_fl64[2] == 0 && split_fl64[3] == 0)
 677                 return nb_bufs;
 678
 679         /* reassemble any packets that need reassembly*/
 680         if (rxq->pkt_first_seg == NULL) {
 681                 /* find the first split flag, and only reassemble then*/
 682                 while (i < nb_bufs && !split_flags[i])
 683                         i++;
 684                 if (i == nb_bufs)
 685                         return nb_bufs;
 686                 rxq->pkt_first_seg = rx_pkts[i];
 687         }
 688         return i + fm10k_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 689                 &split_flags[i]);
 690 }
 691
 692 /**
 693  * vPMD receive routine that reassembles scattered packets.
 694  */
 695 uint16_t
 696 fm10k_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 697                               uint16_t nb_pkts)
 698 {
 699         uint16_t retval = 0;
 700
 701         while (nb_pkts > RTE_FM10K_MAX_RX_BURST) {
 702                 uint16_t burst;
 703
 704                 burst = fm10k_recv_scattered_burst_vec(rx_queue,
 705                                                        rx_pkts + retval,
 706                                                        RTE_FM10K_MAX_RX_BURST);
 707                 retval += burst;
 708                 nb_pkts -= burst;
 709                 if (burst < RTE_FM10K_MAX_RX_BURST)
 710                         return retval;
 711         }
 712
 713         return retval + fm10k_recv_scattered_burst_vec(rx_queue,
 714                                                        rx_pkts + retval,
 715                                                        nb_pkts);
 716 }
 717
 718 static const struct fm10k_txq_ops vec_txq_ops = {
 719         .reset = fm10k_reset_tx_queue,
 720 };
 721
 722 void __rte_cold
 723 fm10k_txq_vec_setup(struct fm10k_tx_queue *txq)
 724 {
 725         txq->ops = &vec_txq_ops;
 726 }
 727
 728 int __rte_cold
 729 fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq)
 730 {
 731         /* Vector TX can't offload any features yet */
 732         if (txq->offloads != 0)
 733                 return -1;
 734
 735         if (txq->tx_ftag_en)
 736                 return -1;
 737
 738         return 0;
 739 }
 740
 741 static inline void
 742 vtx1(volatile struct fm10k_tx_desc *txdp,
 743                 struct rte_mbuf *pkt, uint64_t flags)
 744 {
 745         __m128i descriptor = _mm_set_epi64x(flags << 56 |
 746                         (uint64_t)pkt->vlan_tci << 16 | (uint64_t)pkt->data_len,
 747                         MBUF_DMA_ADDR(pkt));
 748         _mm_store_si128((__m128i *)txdp, descriptor);
 749 }
 750
 751 static inline void
 752 vtx(volatile struct fm10k_tx_desc *txdp,
 753                 struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 754 {
 755         int i;
 756
 757         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 758                 vtx1(txdp, *pkt, flags);
 759 }
 760
 761 static __rte_always_inline int
 762 fm10k_tx_free_bufs(struct fm10k_tx_queue *txq)
 763 {
 764         struct rte_mbuf **txep;
 765         uint8_t flags;
 766         uint32_t n;
 767         uint32_t i;
 768         int nb_free = 0;
 769         struct rte_mbuf *m, *free[RTE_FM10K_TX_MAX_FREE_BUF_SZ];
 770
 771         /* check DD bit on threshold descriptor */
 772         flags = txq->hw_ring[txq->next_dd].flags;
 773         if (!(flags & FM10K_TXD_FLAG_DONE))
 774                 return 0;
 775
 776         n = txq->rs_thresh;
 777
 778         /* First buffer to free from S/W ring is at index
 779          * next_dd - (rs_thresh-1)
 780          */
 781         txep = &txq->sw_ring[txq->next_dd - (n - 1)];
 782         m = rte_pktmbuf_prefree_seg(txep[0]);
 783         if (likely(m != NULL)) {
 784                 free[0] = m;
 785                 nb_free = 1;
 786                 for (i = 1; i < n; i++) {
 787                         m = rte_pktmbuf_prefree_seg(txep[i]);
 788                         if (likely(m != NULL)) {
 789                                 if (likely(m->pool == free[0]->pool))
 790                                         free[nb_free++] = m;
 791                                 else {
 792                                         rte_mempool_put_bulk(free[0]->pool,
 793                                                         (void *)free, nb_free);
 794                                         free[0] = m;
 795                                         nb_free = 1;
 796                                 }
 797                         }
 798                 }
 799                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
 800         } else {
 801                 for (i = 1; i < n; i++) {
 802                         m = rte_pktmbuf_prefree_seg(txep[i]);
 803                         if (m != NULL)
 804                                 rte_mempool_put(m->pool, m);
 805                 }
 806         }
 807
 808         /* buffers were freed, update counters */
 809         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
 810         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
 811         if (txq->next_dd >= txq->nb_desc)
 812                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 813
 814         return txq->rs_thresh;
 815 }
 816
 817 static __rte_always_inline void
 818 tx_backlog_entry(struct rte_mbuf **txep,
 819                  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
 820 {
 821         int i;
 822
 823         for (i = 0; i < (int)nb_pkts; ++i)
 824                 txep[i] = tx_pkts[i];
 825 }
 826
 827 uint16_t
 828 fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 829                            uint16_t nb_pkts)
 830 {
 831         struct fm10k_tx_queue *txq = (struct fm10k_tx_queue *)tx_queue;
 832         volatile struct fm10k_tx_desc *txdp;
 833         struct rte_mbuf **txep;
 834         uint16_t n, nb_commit, tx_id;
 835         uint64_t flags = FM10K_TXD_FLAG_LAST;
 836         uint64_t rs = FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_LAST;
 837         int i;
 838
 839         /* cross rx_thresh boundary is not allowed */
 840         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 841
 842         if (txq->nb_free < txq->free_thresh)
 843                 fm10k_tx_free_bufs(txq);
 844
 845         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 846         if (unlikely(nb_pkts == 0))
 847                 return 0;
 848
 849         tx_id = txq->next_free;
 850         txdp = &txq->hw_ring[tx_id];
 851         txep = &txq->sw_ring[tx_id];
 852
 853         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 854
 855         n = (uint16_t)(txq->nb_desc - tx_id);
 856         if (nb_commit >= n) {
 857                 tx_backlog_entry(txep, tx_pkts, n);
 858
 859                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 860                         vtx1(txdp, *tx_pkts, flags);
 861
 862                 vtx1(txdp, *tx_pkts++, rs);
 863
 864                 nb_commit = (uint16_t)(nb_commit - n);
 865
 866                 tx_id = 0;
 867                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 868
 869                 /* avoid reach the end of ring */
 870                 txdp = &(txq->hw_ring[tx_id]);
 871                 txep = &txq->sw_ring[tx_id];
 872         }
 873
 874         tx_backlog_entry(txep, tx_pkts, nb_commit);
 875
 876         vtx(txdp, tx_pkts, nb_commit, flags);
 877
 878         tx_id = (uint16_t)(tx_id + nb_commit);
 879         if (tx_id > txq->next_rs) {
 880                 txq->hw_ring[txq->next_rs].flags |= FM10K_TXD_FLAG_RS;
 881                 txq->next_rs = (uint16_t)(txq->next_rs + txq->rs_thresh);
 882         }
 883
 884         txq->next_free = tx_id;
 885
 886         FM10K_PCI_REG_WRITE(txq->tail_ptr, txq->next_free);
 887
 888         return nb_pkts;
 889 }
 890
 891 static void __rte_cold
 892 fm10k_reset_tx_queue(struct fm10k_tx_queue *txq)
 893 {
 894         static const struct fm10k_tx_desc zeroed_desc = {0};
 895         struct rte_mbuf **txe = txq->sw_ring;
 896         uint16_t i;
 897
 898         /* Zero out HW ring memory */
 899         for (i = 0; i < txq->nb_desc; i++)
 900                 txq->hw_ring[i] = zeroed_desc;
 901
 902         /* Initialize SW ring entries */
 903         for (i = 0; i < txq->nb_desc; i++)
 904                 txe[i] = NULL;
 905
 906         txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
 907         txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 908
 909         txq->next_free = 0;
 910         txq->nb_used = 0;
 911         /* Always allow 1 descriptor to be un-allocated to avoid
 912          * a H/W race condition
 913          */
 914         txq->nb_free = (uint16_t)(txq->nb_desc - 1);
 915         FM10K_PCI_REG_WRITE(txq->tail_ptr, 0);
 916 }