1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_COMPAT_H_
6 #define _HINIC_COMPAT_H_
10 #include <rte_common.h>
11 #include <rte_byteorder.h>
12 #include <rte_memzone.h>
13 #include <rte_memcpy.h>
14 #include <rte_malloc.h>
15 #include <rte_atomic.h>
16 #include <rte_spinlock.h>
17 #include <rte_cycles.h>
19 #include <rte_config.h>
29 typedef uint64_t dma_addr_t;
33 #define gfp_t unsigned
57 #define NULL ((void *)0)
60 #define HINIC_ERROR (-1)
64 #define BIT(n) (1 << (n))
67 #define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
68 #define lower_32_bits(n) ((u32)(n))
70 /* Returns X / Y, rounding up. X must be nonnegative to round correctly. */
71 #define DIV_ROUND_UP(X, Y) (((X) + ((Y) - 1)) / (Y))
73 /* Returns X rounded up to the nearest multiple of Y. */
74 #define ROUND_UP(X, Y) (DIV_ROUND_UP(X, Y) * (Y))
77 #define ALIGN(x, a) RTE_ALIGN(x, a)
79 #define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
81 /* Reported driver name. */
82 #define HINIC_DRIVER_NAME "net_hinic"
84 extern int hinic_logtype;
86 #define PMD_DRV_LOG(level, fmt, args...) \
87 rte_log(RTE_LOG_ ## level, hinic_logtype, \
88 HINIC_DRIVER_NAME": " fmt "\n", ##args)
90 /* common definition */
96 #define VLAN_PRIO_SHIFT 13
97 #define VLAN_N_VID 4096
99 /* bit order interface */
100 #define cpu_to_be16(o) rte_cpu_to_be_16(o)
101 #define cpu_to_be32(o) rte_cpu_to_be_32(o)
102 #define cpu_to_be64(o) rte_cpu_to_be_64(o)
103 #define cpu_to_le32(o) rte_cpu_to_le_32(o)
104 #define be16_to_cpu(o) rte_be_to_cpu_16(o)
105 #define be32_to_cpu(o) rte_be_to_cpu_32(o)
106 #define be64_to_cpu(o) rte_be_to_cpu_64(o)
107 #define le32_to_cpu(o) rte_le_to_cpu_32(o)
109 /* virt memory and dma phy memory */
111 #define GFP_KERNEL RTE_MEMZONE_IOVA_CONTIG
112 #define HINIC_PAGE_SHIFT 12
113 #define HINIC_PAGE_SIZE RTE_PGSIZE_4K
114 #define HINIC_MEM_ALLOC_ALIGNE_MIN 8
116 #define HINIC_PAGE_SIZE_DPDK 6
118 static inline int hinic_test_bit(int nr, volatile unsigned long *addr)
123 res = ((*addr) & (1UL << nr)) != 0;
128 static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr)
130 __sync_fetch_and_or(addr, (1UL << nr));
133 static inline void hinic_clear_bit(int nr, volatile unsigned long *addr)
135 __sync_fetch_and_and(addr, ~(1UL << nr));
138 static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr)
140 unsigned long mask = (1UL << nr);
142 return __sync_fetch_and_and(addr, ~mask) & mask;
145 static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr)
147 unsigned long mask = (1UL << nr);
149 return __sync_fetch_and_or(addr, mask) & mask;
152 void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle,
154 void *dma_zalloc_coherent_aligned(void *dev, size_t size,
155 dma_addr_t *dma_handle, gfp_t flag);
156 void *dma_zalloc_coherent_aligned256k(void *dev, size_t size,
157 dma_addr_t *dma_handle, gfp_t flag);
158 void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys);
160 /* dma pool alloc and free */
161 #define pci_pool dma_pool
162 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
163 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
165 struct dma_pool *dma_pool_create(const char *name, void *dev, size_t size,
166 size_t align, size_t boundary);
167 void dma_pool_destroy(struct dma_pool *pool);
168 void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr);
169 void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma);
171 #define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGNE_MIN)
172 #define kzalloc_aligned(size, flag) rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE)
173 #define kfree(ptr) rte_free(ptr)
176 static inline void writel(u32 value, volatile void *addr)
178 *(volatile u32 *)addr = value;
181 static inline u32 readl(const volatile void *addr)
183 return *(const volatile u32 *)addr;
186 #define __raw_writel(value, reg) writel((value), (reg))
187 #define __raw_readl(reg) readl((reg))
189 /* Spinlock related interface */
190 #define hinic_spinlock_t rte_spinlock_t
192 #define spinlock_t rte_spinlock_t
193 #define spin_lock_init(spinlock_prt) rte_spinlock_init(spinlock_prt)
194 #define spin_lock_deinit(lock)
195 #define spin_lock(spinlock_prt) rte_spinlock_lock(spinlock_prt)
196 #define spin_unlock(spinlock_prt) rte_spinlock_unlock(spinlock_prt)
198 static inline unsigned long get_timeofday_ms(void)
202 (void)gettimeofday(&tv, NULL);
204 return (unsigned long)tv.tv_sec * 1000 + tv.tv_usec / 1000;
207 #define jiffies get_timeofday_ms()
208 #define msecs_to_jiffies(ms) (ms)
209 #define time_before(now, end) ((now) < (end))
211 /* misc kernel utils */
212 static inline u16 ilog2(u32 n)
225 * hinic_cpu_to_be32 - convert data to big endian 32 bit format
226 * @data: the data to convert
227 * @len: length of data to convert, must be Multiple of 4B
229 static inline void hinic_cpu_to_be32(void *data, u32 len)
232 u32 *mem = (u32 *)data;
234 for (i = 0; i < (len >> 2); i++) {
235 *mem = cpu_to_be32(*mem);
241 * hinic_be32_to_cpu - convert data from big endian 32 bit format
242 * @data: the data to convert
243 * @len: length of data to convert, must be Multiple of 4B
245 static inline void hinic_be32_to_cpu(void *data, u32 len)
248 u32 *mem = (u32 *)data;
250 for (i = 0; i < (len >> 2); i++) {
251 *mem = be32_to_cpu(*mem);
256 #endif /* _HINIC_COMPAT_H_ */