drivers/net/hinic/base/hinic_pmd_cmd.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PORT_CMD_H_
   6 #define _HINIC_PORT_CMD_H_
   7
   8 enum hinic_eq_type {
   9         HINIC_AEQ,
  10         HINIC_CEQ
  11 };
  12
  13 enum hinic_resp_aeq_num {
  14         HINIC_AEQ0 = 0,
  15         HINIC_AEQ1 = 1,
  16         HINIC_AEQ2 = 2,
  17         HINIC_AEQ3 = 3,
  18 };
  19
  20 enum hinic_mod_type {
  21         HINIC_MOD_COMM = 0,     /* HW communication module */
  22         HINIC_MOD_L2NIC = 1,    /* L2NIC module */
  23         HINIC_MOD_CFGM = 7,     /* Configuration module */
  24         HINIC_MOD_HILINK = 14,
  25         HINIC_MOD_MAX   = 15
  26 };
  27
  28 /* only used by VFD communicating with PFD to register or unregister,
  29  * command mode type is HINIC_MOD_L2NIC
  30  */
  31 #define HINIC_PORT_CMD_VF_REGISTER      0x0
  32 #define HINIC_PORT_CMD_VF_UNREGISTER    0x1
  33
  34 /* cmd of mgmt CPU message for NIC module */
  35 enum hinic_port_cmd {
  36         HINIC_PORT_CMD_MGMT_RESET               = 0x0,
  37
  38         HINIC_PORT_CMD_CHANGE_MTU               = 0x2,
  39
  40         HINIC_PORT_CMD_ADD_VLAN                 = 0x3,
  41         HINIC_PORT_CMD_DEL_VLAN,
  42
  43         HINIC_PORT_CMD_SET_ETS                  = 0x7,
  44         HINIC_PORT_CMD_GET_ETS,
  45
  46         HINIC_PORT_CMD_SET_MAC                  = 0x9,
  47         HINIC_PORT_CMD_GET_MAC,
  48         HINIC_PORT_CMD_DEL_MAC,
  49
  50         HINIC_PORT_CMD_SET_RX_MODE              = 0xc,
  51         HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE     = 0xd,
  52
  53         HINIC_PORT_CMD_GET_PAUSE_INFO           = 0x14,
  54         HINIC_PORT_CMD_SET_PAUSE_INFO,
  55
  56         HINIC_PORT_CMD_GET_LINK_STATE           = 0x18,
  57         HINIC_PORT_CMD_SET_LRO                  = 0x19,
  58         HINIC_PORT_CMD_SET_RX_CSUM              = 0x1a,
  59         HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD      = 0x1b,
  60
  61         HINIC_PORT_CMD_GET_PORT_STATISTICS      = 0x1c,
  62         HINIC_PORT_CMD_CLEAR_PORT_STATISTICS,
  63         HINIC_PORT_CMD_GET_VPORT_STAT,
  64         HINIC_PORT_CMD_CLEAN_VPORT_STAT,
  65
  66         HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
  67         HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,
  68
  69         HINIC_PORT_CMD_SET_PORT_ENABLE          = 0x29,
  70         HINIC_PORT_CMD_GET_PORT_ENABLE,
  71
  72         HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL     = 0x2b,
  73         HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,
  74         HINIC_PORT_CMD_SET_RSS_HASH_ENGINE,
  75         HINIC_PORT_CMD_GET_RSS_HASH_ENGINE,
  76         HINIC_PORT_CMD_GET_RSS_CTX_TBL,
  77         HINIC_PORT_CMD_SET_RSS_CTX_TBL,
  78         HINIC_PORT_CMD_RSS_TEMP_MGR,
  79
  80         HINIC_PORT_CMD_RSS_CFG                  = 0x42,
  81
  82         HINIC_PORT_CMD_GET_PHY_TYPE             = 0x44,
  83         HINIC_PORT_CMD_INIT_FUNC                = 0x45,
  84
  85         HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE     = 0x4a,
  86         HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,
  87
  88         HINIC_PORT_CMD_GET_PORT_TYPE            = 0x5b,
  89
  90         HINIC_PORT_CMD_GET_VPORT_ENABLE         = 0x5c,
  91         HINIC_PORT_CMD_SET_VPORT_ENABLE,
  92
  93         HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID   = 0x5e,
  94
  95         HINIC_PORT_CMD_GET_LRO                  = 0x63,
  96
  97         HINIC_PORT_CMD_GET_DMA_CS               = 0x64,
  98         HINIC_PORT_CMD_SET_DMA_CS,
  99
 100         HINIC_PORT_CMD_GET_GLOBAL_QPN           = 0x66,
 101
 102         HINIC_PORT_CMD_SET_PFC_MISC             = 0x67,
 103         HINIC_PORT_CMD_GET_PFC_MISC,
 104
 105         HINIC_PORT_CMD_SET_VF_RATE              = 0x69,
 106         HINIC_PORT_CMD_SET_VF_VLAN,
 107         HINIC_PORT_CMD_CLR_VF_VLAN,
 108
 109         HINIC_PORT_CMD_SET_RQ_IQ_MAP            = 0x73,
 110         HINIC_PORT_CMD_SET_PFC_THD              = 0x75,
 111
 112         HINIC_PORT_CMD_LINK_STATUS_REPORT       = 0xa0,
 113
 114         HINIC_PORT_CMD_SET_LOSSLESS_ETH         = 0xa3,
 115         HINIC_PORT_CMD_UPDATE_MAC               = 0xa4,
 116
 117         HINIC_PORT_CMD_GET_PORT_INFO            = 0xaa,
 118
 119         HINIC_PORT_CMD_SET_IPSU_MAC             = 0xcb,
 120         HINIC_PORT_CMD_GET_IPSU_MAC             = 0xcc,
 121
 122         HINIC_PORT_CMD_GET_LINK_MODE            = 0xD9,
 123         HINIC_PORT_CMD_SET_SPEED                = 0xDA,
 124         HINIC_PORT_CMD_SET_AUTONEG              = 0xDB,
 125
 126         HINIC_PORT_CMD_CLEAR_QP_RES             = 0xDD,
 127         HINIC_PORT_CMD_SET_SUPER_CQE            = 0xDE,
 128         HINIC_PORT_CMD_SET_VF_COS               = 0xDF,
 129         HINIC_PORT_CMD_GET_VF_COS               = 0xE1,
 130
 131         HINIC_PORT_CMD_CABLE_PLUG_EVENT         = 0xE5,
 132         HINIC_PORT_CMD_LINK_ERR_EVENT           = 0xE6,
 133
 134         HINIC_PORT_CMD_SET_COS_UP_MAP           = 0xE8,
 135
 136         HINIC_PORT_CMD_RESET_LINK_CFG           = 0xEB,
 137
 138         HINIC_PORT_CMD_FORCE_PKT_DROP           = 0xF3,
 139         HINIC_PORT_CMD_SET_LRO_TIMER            = 0xF4,
 140
 141         HINIC_PORT_CMD_SET_VHD_CFG              = 0xF7,
 142         HINIC_PORT_CMD_SET_LINK_FOLLOW          = 0xF8,
 143         HINIC_PORT_CMD_SET_VLAN_FILTER          = 0xFF
 144 };
 145
 146 /* cmd of mgmt CPU message for HW module */
 147 enum hinic_mgmt_cmd {
 148         HINIC_MGMT_CMD_RESET_MGMT               = 0x0,
 149         HINIC_MGMT_CMD_START_FLR                = 0x1,
 150         HINIC_MGMT_CMD_FLUSH_DOORBELL           = 0x2,
 151         HINIC_MGMT_CMD_GET_IO_STATUS            = 0x3,
 152         HINIC_MGMT_CMD_DMA_ATTR_SET             = 0x4,
 153
 154         HINIC_MGMT_CMD_CMDQ_CTXT_SET            = 0x10,
 155         HINIC_MGMT_CMD_CMDQ_CTXT_GET,
 156
 157         HINIC_MGMT_CMD_VAT_SET                  = 0x12,
 158         HINIC_MGMT_CMD_VAT_GET,
 159
 160         HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET     = 0x14,
 161         HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,
 162
 163         HINIC_MGMT_CMD_PPF_HT_GPA_SET           = 0x23,
 164         HINIC_MGMT_CMD_RES_STATE_SET            = 0x24,
 165         HINIC_MGMT_CMD_FUNC_CACHE_OUT           = 0x25,
 166         HINIC_MGMT_CMD_FFM_SET                  = 0x26,
 167
 168         HINIC_MGMT_CMD_FUNC_RES_CLEAR           = 0x29,
 169
 170         HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP    = 0x33,
 171         HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,
 172         HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,
 173
 174         HINIC_MGMT_CMD_VF_RANDOM_ID_SET         = 0x36,
 175         HINIC_MGMT_CMD_FAULT_REPORT             = 0x37,
 176
 177         HINIC_MGMT_CMD_VPD_SET                  = 0x40,
 178         HINIC_MGMT_CMD_VPD_GET,
 179         HINIC_MGMT_CMD_LABEL_SET,
 180         HINIC_MGMT_CMD_LABEL_GET,
 181         HINIC_MGMT_CMD_SATIC_MAC_SET,
 182         HINIC_MGMT_CMD_SATIC_MAC_GET,
 183         HINIC_MGMT_CMD_SYNC_TIME                = 0x46,
 184         HINIC_MGMT_CMD_SET_LED_STATUS           = 0x4A,
 185         HINIC_MGMT_CMD_L2NIC_RESET              = 0x4b,
 186         HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET    = 0x4d,
 187         HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT        = 0x4E,
 188         HINIC_MGMT_CMD_ACTIVATE_FW              = 0x4F,
 189         HINIC_MGMT_CMD_PAGESIZE_SET             = 0x50,
 190         HINIC_MGMT_CMD_PAGESIZE_GET             = 0x51,
 191         HINIC_MGMT_CMD_GET_BOARD_INFO           = 0x52,
 192         HINIC_MGMT_CMD_WATCHDOG_INFO            = 0x56,
 193         HINIC_MGMT_CMD_FMW_ACT_NTC              = 0x57,
 194         HINIC_MGMT_CMD_SET_VF_RANDOM_ID         = 0x61,
 195         HINIC_MGMT_CMD_GET_PPF_STATE            = 0x63,
 196         HINIC_MGMT_CMD_PCIE_DFX_NTC             = 0x65,
 197         HINIC_MGMT_CMD_PCIE_DFX_GET             = 0x66,
 198 };
 199
 200 /* cmd of mgmt CPU message for HILINK module */
 201 enum hinic_hilink_cmd {
 202         HINIC_HILINK_CMD_GET_LINK_INFO          = 0x3,
 203         HINIC_HILINK_CMD_SET_LINK_SETTINGS      = 0x8,
 204 };
 205
 206 /* uCode related commands */
 207 enum hinic_ucode_cmd {
 208         HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT       = 0,
 209         HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
 210         HINIC_UCODE_CMD_ARM_SQ,
 211         HINIC_UCODE_CMD_ARM_RQ,
 212         HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
 213         HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
 214         HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
 215         HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
 216         HINIC_UCODE_CMD_SET_IQ_ENABLE,
 217         HINIC_UCODE_CMD_SET_RQ_FLUSH            = 10
 218 };
 219
 220 enum cfg_sub_cmd {
 221         /* PPF(PF) <-> FW */
 222         HINIC_CFG_NIC_CAP = 0,
 223         CFG_FW_VERSION,
 224         CFG_UCODE_VERSION,
 225         HINIC_CFG_MBOX_CAP = 6
 226 };
 227
 228 enum hinic_ack_type {
 229         HINIC_ACK_TYPE_CMDQ,
 230         HINIC_ACK_TYPE_SHARE_CQN,
 231         HINIC_ACK_TYPE_APP_CQN,
 232
 233         HINIC_MOD_ACK_MAX = 15,
 234 };
 235
 236 enum sq_l4offload_type {
 237         OFFLOAD_DISABLE   = 0,
 238         TCP_OFFLOAD_ENABLE  = 1,
 239         SCTP_OFFLOAD_ENABLE = 2,
 240         UDP_OFFLOAD_ENABLE  = 3,
 241 };
 242
 243 enum sq_vlan_offload_flag {
 244         VLAN_OFFLOAD_DISABLE = 0,
 245         VLAN_OFFLOAD_ENABLE  = 1,
 246 };
 247
 248 enum sq_pkt_parsed_flag {
 249         PKT_NOT_PARSED = 0,
 250         PKT_PARSED     = 1,
 251 };
 252
 253 enum sq_l3_type {
 254         UNKNOWN_L3TYPE = 0,
 255         IPV6_PKT = 1,
 256         IPV4_PKT_NO_CHKSUM_OFFLOAD = 2,
 257         IPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,
 258 };
 259
 260 enum sq_md_type {
 261         UNKNOWN_MD_TYPE = 0,
 262 };
 263
 264 enum sq_l2type {
 265         ETHERNET = 0,
 266 };
 267
 268 enum sq_tunnel_l4_type {
 269         NOT_TUNNEL,
 270         TUNNEL_UDP_NO_CSUM,
 271         TUNNEL_UDP_CSUM,
 272 };
 273
 274 #define NIC_RSS_CMD_TEMP_ALLOC  0x01
 275 #define NIC_RSS_CMD_TEMP_FREE   0x02
 276
 277 #define HINIC_RSS_TYPE_VALID_SHIFT                      23
 278 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT               24
 279 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT                   25
 280 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT                   26
 281 #define HINIC_RSS_TYPE_IPV6_SHIFT                       27
 282 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT                   28
 283 #define HINIC_RSS_TYPE_IPV4_SHIFT                       29
 284 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT                   30
 285 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT                   31
 286
 287 #define HINIC_RSS_TYPE_SET(val, member)         \
 288                 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
 289
 290 #define HINIC_RSS_TYPE_GET(val, member)         \
 291                 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
 292
 293 enum hinic_speed {
 294         HINIC_SPEED_10MB_LINK = 0,
 295         HINIC_SPEED_100MB_LINK,
 296         HINIC_SPEED_1000MB_LINK,
 297         HINIC_SPEED_10GB_LINK,
 298         HINIC_SPEED_25GB_LINK,
 299         HINIC_SPEED_40GB_LINK,
 300         HINIC_SPEED_100GB_LINK,
 301         HINIC_SPEED_UNKNOWN = 0xFF,
 302 };
 303
 304 enum {
 305         HINIC_IFLA_VF_LINK_STATE_AUTO,  /* link state of the uplink */
 306         HINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */
 307         HINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */
 308 };
 309
 310 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT         0
 311 #define HINIC_AF0_P2P_IDX_SHIFT                 10
 312 #define HINIC_AF0_PCI_INTF_IDX_SHIFT            14
 313 #define HINIC_AF0_VF_IN_PF_SHIFT                16
 314 #define HINIC_AF0_FUNC_TYPE_SHIFT               24
 315
 316 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK          0x3FF
 317 #define HINIC_AF0_P2P_IDX_MASK                  0xF
 318 #define HINIC_AF0_PCI_INTF_IDX_MASK             0x3
 319 #define HINIC_AF0_VF_IN_PF_MASK                 0xFF
 320 #define HINIC_AF0_FUNC_TYPE_MASK                0x1
 321
 322 #define HINIC_AF0_GET(val, member)                              \
 323         (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
 324
 325 #define HINIC_AF1_PPF_IDX_SHIFT                 0
 326 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT           8
 327 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT           12
 328 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT           20
 329 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT       24
 330 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT        30
 331 #define HINIC_AF1_PF_INIT_STATUS_SHIFT          31
 332
 333 #define HINIC_AF1_PPF_IDX_MASK                  0x1F
 334 #define HINIC_AF1_AEQS_PER_FUNC_MASK            0x3
 335 #define HINIC_AF1_CEQS_PER_FUNC_MASK            0x7
 336 #define HINIC_AF1_IRQS_PER_FUNC_MASK            0xF
 337 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK        0x7
 338 #define HINIC_AF1_MGMT_INIT_STATUS_MASK         0x1
 339 #define HINIC_AF1_PF_INIT_STATUS_MASK           0x1
 340
 341 #define HINIC_AF1_GET(val, member)                              \
 342         (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
 343
 344 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT      16
 345 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK       0x3FF
 346
 347 #define HINIC_AF2_GET(val, member)                              \
 348         (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
 349
 350 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT           0
 351 #define HINIC_AF4_DOORBELL_CTRL_SHIFT           1
 352 #define HINIC_AF4_OUTBOUND_CTRL_MASK            0x1
 353 #define HINIC_AF4_DOORBELL_CTRL_MASK            0x1
 354
 355 #define HINIC_AF4_GET(val, member)                              \
 356         (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
 357
 358 #define HINIC_AF4_SET(val, member)                              \
 359         (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
 360
 361 #define HINIC_AF4_CLEAR(val, member)                            \
 362         ((val) & (~(HINIC_AF4_##member##_MASK <<                \
 363         HINIC_AF4_##member##_SHIFT)))
 364
 365 #define HINIC_AF5_PF_STATUS_SHIFT               0
 366 #define HINIC_AF5_PF_STATUS_MASK                0xFFFF
 367
 368 #define HINIC_AF5_SET(val, member)                              \
 369         (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
 370
 371 #define HINIC_AF5_GET(val, member)                              \
 372         (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
 373
 374 #define HINIC_AF5_CLEAR(val, member)                            \
 375         ((val) & (~(HINIC_AF5_##member##_MASK <<                \
 376         HINIC_AF5_##member##_SHIFT)))
 377
 378 #define HINIC_PPF_ELECTION_IDX_SHIFT            0
 379
 380 #define HINIC_PPF_ELECTION_IDX_MASK             0x1F
 381
 382 #define HINIC_PPF_ELECTION_SET(val, member)                     \
 383         (((val) & HINIC_PPF_ELECTION_##member##_MASK) <<        \
 384                 HINIC_PPF_ELECTION_##member##_SHIFT)
 385
 386 #define HINIC_PPF_ELECTION_GET(val, member)                     \
 387         (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &       \
 388                 HINIC_PPF_ELECTION_##member##_MASK)
 389
 390 #define HINIC_PPF_ELECTION_CLEAR(val, member)                   \
 391         ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK  \
 392                 << HINIC_PPF_ELECTION_##member##_SHIFT)))
 393
 394 #define DB_IDX(db, db_base)     \
 395         ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) /       \
 396         HINIC_DB_PAGE_SIZE))
 397
 398 enum hinic_pcie_nosnoop {
 399         HINIC_PCIE_SNOOP = 0,
 400         HINIC_PCIE_NO_SNOOP = 1,
 401 };
 402
 403 enum hinic_pcie_tph {
 404         HINIC_PCIE_TPH_DISABLE = 0,
 405         HINIC_PCIE_TPH_ENABLE = 1,
 406 };
 407
 408 enum hinic_outbound_ctrl {
 409         ENABLE_OUTBOUND  = 0x0,
 410         DISABLE_OUTBOUND = 0x1,
 411 };
 412
 413 enum hinic_doorbell_ctrl {
 414         ENABLE_DOORBELL  = 0x0,
 415         DISABLE_DOORBELL = 0x1,
 416 };
 417
 418 enum hinic_pf_status {
 419         HINIC_PF_STATUS_INIT = 0X0,
 420         HINIC_PF_STATUS_ACTIVE_FLAG = 0x11,
 421         HINIC_PF_STATUS_FLR_START_FLAG = 0x12,
 422         HINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,
 423 };
 424
 425 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
 426 #define HINIC_DB_DWQE_SIZE      0x00080000
 427
 428 /* db page size: 4K */
 429 #define HINIC_DB_PAGE_SIZE      0x00001000ULL
 430
 431 #define HINIC_DB_MAX_AREAS      (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
 432
 433 #define HINIC_PCI_MSIX_ENTRY_SIZE                       16
 434 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL                12
 435 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT               1
 436
 437 struct hinic_mgmt_msg_head {
 438         u8      status;
 439         u8      version;
 440         u8      resp_aeq_num;
 441         u8      rsvd0[5];
 442 };
 443
 444 struct hinic_root_ctxt {
 445         struct hinic_mgmt_msg_head mgmt_msg_head;
 446
 447         u16     func_idx;
 448         u16     rsvd1;
 449         u8      set_cmdq_depth;
 450         u8      cmdq_depth;
 451         u8      lro_en;
 452         u8      rsvd2;
 453         u8      ppf_idx;
 454         u8      rsvd3;
 455         u16     rq_depth;
 456         u16     rx_buf_sz;
 457         u16     sq_depth;
 458 };
 459
 460 #endif /* _HINIC_PORT_CMD_H_ */