drivers/net/hinic/base/hinic_pmd_eqs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PMD_EQS_H_
   6 #define _HINIC_PMD_EQS_H_
   7
   8 #define HINIC_EQ_PAGE_SIZE              0x00001000
   9
  10 #define HINIC_AEQN_START                0
  11 #define HINIC_MAX_AEQS                  4
  12
  13 #define HINIC_EQ_MAX_PAGES              8
  14
  15 #define HINIC_AEQE_SIZE                 64
  16 #define HINIC_CEQE_SIZE                 4
  17
  18 #define HINIC_AEQE_DESC_SIZE            4
  19 #define HINIC_AEQE_DATA_SIZE            \
  20                         (HINIC_AEQE_SIZE - HINIC_AEQE_DESC_SIZE)
  21
  22 #define HINIC_DEFAULT_AEQ_LEN           64
  23
  24 #define HINIC_RECV_NEXT_AEQE            HINIC_ERROR
  25 #define HINIC_RECV_DONE                 HINIC_OK
  26
  27 #define GET_EQ_ELEMENT(eq, idx)         \
  28                 (((u8 *)(eq)->virt_addr[(idx) / (eq)->num_elem_in_pg]) + \
  29                 (((u32)(idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))
  30
  31 #define GET_AEQ_ELEM(eq, idx)           \
  32                         ((struct hinic_aeq_elem *)GET_EQ_ELEMENT((eq), (idx)))
  33
  34 #define GET_CEQ_ELEM(eq, idx)   ((u32 *)GET_EQ_ELEMENT((eq), (idx)))
  35
  36 enum hinic_eq_intr_mode {
  37         HINIC_INTR_MODE_ARMED,
  38         HINIC_INTR_MODE_ALWAYS,
  39 };
  40
  41 enum hinic_eq_ci_arm_state {
  42         HINIC_EQ_NOT_ARMED,
  43         HINIC_EQ_ARMED,
  44 };
  45
  46 enum hinic_aeq_type {
  47         HINIC_HW_INTER_INT = 0,
  48         HINIC_MBX_FROM_FUNC = 1,
  49         HINIC_MSG_FROM_MGMT_CPU = 2,
  50         HINIC_API_RSP = 3,
  51         HINIC_API_CHAIN_STS = 4,
  52         HINIC_MBX_SEND_RSLT = 5,
  53         HINIC_MAX_AEQ_EVENTS
  54 };
  55
  56 #define HINIC_RETRY_NUM (10)
  57
  58 struct hinic_eq {
  59         struct hinic_hwdev              *hwdev;
  60         u16                             q_id;
  61         enum hinic_eq_type              type;
  62         u32                             page_size;
  63         u16                             eq_len;
  64
  65         u16                             cons_idx;
  66         u16                             wrapped;
  67
  68         u16                             elem_size;
  69         u16                             num_pages;
  70         u32                             num_elem_in_pg;
  71
  72         struct irq_info                 eq_irq;
  73
  74         dma_addr_t                      *dma_addr;
  75         u8                              **virt_addr;
  76
  77         u16                             poll_retry_nr;
  78 };
  79
  80 struct hinic_aeq_elem {
  81         u8      aeqe_data[HINIC_AEQE_DATA_SIZE];
  82         u32     desc;
  83 };
  84
  85 struct hinic_aeqs {
  86         struct hinic_hwdev      *hwdev;
  87         u16                     poll_retry_nr;
  88
  89         struct hinic_eq         aeq[HINIC_MAX_AEQS];
  90         u16                     num_aeqs;
  91 };
  92
  93 void eq_update_ci(struct hinic_eq *eq);
  94
  95 void hinic_dump_aeq_info(struct hinic_hwdev *hwdev);
  96
  97 int hinic_comm_aeqs_init(struct hinic_hwdev *hwdev);
  98
  99 void hinic_comm_aeqs_free(struct hinic_hwdev *hwdev);
 100
 101 #endif /* _HINIC_PMD_EQS_H_ */