drivers/net/hinic/base/hinic_pmd_hwdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PMD_HWDEV_H_
   6 #define _HINIC_PMD_HWDEV_H_
   7
   8 #include "hinic_pmd_cmd.h"
   9
  10 #define HINIC_PAGE_SIZE_MAX     20
  11
  12 #define HINIC_MGMT_CMD_UNSUPPORTED      0xFF
  13 #define HINIC_PF_SET_VF_ALREADY         0x4
  14
  15 #define MAX_PCIE_DFX_BUF_SIZE           1024
  16
  17 /* dma pool */
  18 struct dma_pool {
  19         u32 inuse;
  20         size_t elem_size;
  21         size_t align;
  22         size_t boundary;
  23         void *hwdev;
  24
  25         char name[32];
  26 };
  27
  28 enum hinic_res_state {
  29         HINIC_RES_CLEAN = 0,
  30         HINIC_RES_ACTIVE = 1,
  31 };
  32
  33 enum hilink_info_print_event {
  34         HILINK_EVENT_LINK_UP = 1,
  35         HILINK_EVENT_LINK_DOWN,
  36         HILINK_EVENT_CABLE_PLUGGED,
  37         HILINK_EVENT_MAX_TYPE,
  38 };
  39
  40 struct hinic_port_link_status {
  41         struct hinic_mgmt_msg_head mgmt_msg_head;
  42
  43         u16     func_id;
  44         u8      link;
  45         u8      port_id;
  46 };
  47
  48 enum link_err_status {
  49         LINK_ERR_MODULE_UNRECOGENIZED,
  50         LINK_ERR_NUM,
  51 };
  52
  53 struct hinic_cable_plug_event {
  54         struct hinic_mgmt_msg_head mgmt_msg_head;
  55
  56         u16     func_id;
  57         u8      plugged;        /* 0: unplugged, 1: plugged */
  58         u8      port_id;
  59 };
  60
  61 struct hinic_link_err_event {
  62         struct hinic_mgmt_msg_head mgmt_msg_head;
  63
  64         u16     func_id;
  65         u8      err_type;
  66         u8      port_id;
  67 };
  68
  69 struct hinic_cons_idx_attr {
  70         struct hinic_mgmt_msg_head mgmt_msg_head;
  71
  72         u16     func_idx;
  73         u8      dma_attr_off;
  74         u8      pending_limit;
  75         u8      coalescing_time;
  76         u8      intr_en;
  77         u16     intr_idx;
  78         u32     l2nic_sqn;
  79         u32     sq_id;
  80         u64     ci_addr;
  81 };
  82
  83 struct hinic_clear_doorbell {
  84         struct hinic_mgmt_msg_head mgmt_msg_head;
  85
  86         u16     func_idx;
  87         u8      ppf_idx;
  88         u8      rsvd1;
  89 };
  90
  91 struct hinic_clear_resource {
  92         struct hinic_mgmt_msg_head mgmt_msg_head;
  93
  94         u16     func_idx;
  95         u8      ppf_idx;
  96         u8      rsvd1;
  97 };
  98
  99 struct hinic_cmd_set_res_state {
 100         struct hinic_mgmt_msg_head mgmt_msg_head;
 101
 102         u16     func_idx;
 103         u8      state;
 104         u8      rsvd1;
 105         u32     rsvd2;
 106 };
 107
 108 struct hinic_l2nic_reset {
 109         struct hinic_mgmt_msg_head mgmt_msg_head;
 110
 111         u16 func_id;
 112         u16 rsvd1;
 113 };
 114
 115 struct hinic_page_size {
 116         struct hinic_mgmt_msg_head mgmt_msg_head;
 117
 118         u16     func_idx;
 119         u8      ppf_idx;
 120         u8      page_size;
 121         u32     rsvd;
 122 };
 123
 124 struct hinic_msix_config {
 125         struct hinic_mgmt_msg_head mgmt_msg_head;
 126
 127         u16     func_id;
 128         u16     msix_index;
 129         u8      pending_cnt;
 130         u8      coalesct_timer_cnt;
 131         u8      lli_tmier_cnt;
 132         u8      lli_credit_cnt;
 133         u8      resend_timer_cnt;
 134         u8      rsvd1[3];
 135 };
 136
 137 /* defined by chip */
 138 enum hinic_fault_type {
 139         FAULT_TYPE_CHIP,
 140         FAULT_TYPE_UCODE,
 141         FAULT_TYPE_MEM_RD_TIMEOUT,
 142         FAULT_TYPE_MEM_WR_TIMEOUT,
 143         FAULT_TYPE_REG_RD_TIMEOUT,
 144         FAULT_TYPE_REG_WR_TIMEOUT,
 145         FAULT_TYPE_MAX,
 146 };
 147
 148 /* defined by chip */
 149 enum hinic_fault_err_level {
 150         /* default err_level=FAULT_LEVEL_FATAL if
 151          * type==FAULT_TYPE_MEM_RD_TIMEOUT || FAULT_TYPE_MEM_WR_TIMEOUT ||
 152          *       FAULT_TYPE_REG_RD_TIMEOUT || FAULT_TYPE_REG_WR_TIMEOUT ||
 153          *       FAULT_TYPE_UCODE
 154          * other: err_level in event.chip.err_level if type==FAULT_TYPE_CHIP
 155          */
 156         FAULT_LEVEL_FATAL,
 157         FAULT_LEVEL_SERIOUS_RESET,
 158         FAULT_LEVEL_SERIOUS_FLR,
 159         FAULT_LEVEL_GENERAL,
 160         FAULT_LEVEL_SUGGESTION,
 161         FAULT_LEVEL_MAX
 162 };
 163
 164 /* defined by chip */
 165 struct hinic_fault_event {
 166         /* enum hinic_fault_type */
 167         u8 type;
 168         u8 rsvd0[3];
 169         union {
 170                 u32 val[4];
 171                 /* valid only type==FAULT_TYPE_CHIP */
 172                 struct {
 173                         u8 node_id;
 174                         /* enum hinic_fault_err_level */
 175                         u8 err_level;
 176                         u8 err_type;
 177                         u8 rsvd1;
 178                         u32 err_csr_addr;
 179                         u32 err_csr_value;
 180                 /* func_id valid only err_level==FAULT_LEVEL_SERIOUS_FLR */
 181                         u16 func_id;
 182                         u16 rsvd2;
 183                 } chip;
 184
 185                 /* valid only type==FAULT_TYPE_UCODE */
 186                 struct {
 187                         u8 cause_id;
 188                         u8 core_id;
 189                         u8 c_id;
 190                         u8 rsvd3;
 191                         u32 epc;
 192                         u32 rsvd4;
 193                         u32 rsvd5;
 194                 } ucode;
 195
 196                 /* valid only type==FAULT_TYPE_MEM_RD_TIMEOUT ||
 197                  *              FAULT_TYPE_MEM_WR_TIMEOUT
 198                  */
 199                 struct {
 200                         u32 err_csr_ctrl;
 201                         u32 err_csr_data;
 202                         u32 ctrl_tab;
 203                         u32 mem_index;
 204                 } mem_timeout;
 205
 206                 /* valid only type==FAULT_TYPE_REG_RD_TIMEOUT ||
 207                  *                  FAULT_TYPE_REG_WR_TIMEOUT
 208                  */
 209                 struct {
 210                         u32 err_csr;
 211                         u32 rsvd6;
 212                         u32 rsvd7;
 213                         u32 rsvd8;
 214                 } reg_timeout;
 215         } event;
 216 };
 217
 218 struct hinic_cmd_fault_event {
 219         struct hinic_mgmt_msg_head mgmt_msg_head;
 220
 221         struct hinic_fault_event event;
 222 };
 223
 224 struct hinic_mgmt_watchdog_info {
 225         struct hinic_mgmt_msg_head mgmt_msg_head;
 226
 227         u32 curr_time_h;
 228         u32 curr_time_l;
 229         u32 task_id;
 230         u32 rsv;
 231
 232         u32 reg[13];
 233         u32 pc;
 234         u32 lr;
 235         u32 cpsr;
 236
 237         u32 stack_top;
 238         u32 stack_bottom;
 239         u32 sp;
 240         u32 curr_used;
 241         u32 peak_used;
 242         u32 is_overflow;
 243
 244         u32 stack_actlen;
 245         u8 data[1024];
 246 };
 247
 248 struct hinic_pcie_dfx_ntc {
 249         struct hinic_mgmt_msg_head mgmt_msg_head;
 250
 251         int len;
 252         u32 rsvd;
 253 };
 254
 255 struct hinic_pcie_dfx_info {
 256         struct hinic_mgmt_msg_head mgmt_msg_head;
 257
 258         u8 host_id;
 259         u8 last;
 260         u8 rsvd[2];
 261         u32 offset;
 262
 263         u8 data[MAX_PCIE_DFX_BUF_SIZE];
 264 };
 265
 266 struct ffm_intr_info {
 267         u8 node_id;
 268         /* error level of the interrupt source */
 269         u8 err_level;
 270         /* Classification by interrupt source properties */
 271         u16 err_type;
 272         u32 err_csr_addr;
 273         u32 err_csr_value;
 274 };
 275
 276 struct hinic_board_info {
 277         u32     board_type;
 278         u32     port_num;
 279         u32     port_speed;
 280         u32     pcie_width;
 281         u32     host_num;
 282         u32     pf_num;
 283         u32     vf_total_num;
 284         u32     tile_num;
 285         u32     qcm_num;
 286         u32     core_num;
 287         u32     work_mode;
 288         u32     service_mode;
 289         u32     pcie_mode;
 290         u32     cfg_addr;
 291         u32     boot_sel;
 292 };
 293
 294 struct hinic_comm_board_info {
 295         struct hinic_mgmt_msg_head mgmt_msg_head;
 296
 297         struct hinic_board_info info;
 298
 299         u32     rsvd1[5];
 300 };
 301
 302 struct hi30_ctle_data {
 303         u8 ctlebst[3];
 304         u8 ctlecmband[3];
 305         u8 ctlermband[3];
 306         u8 ctleza[3];
 307         u8 ctlesqh[3];
 308         u8 ctleactgn[3];
 309         u8 ctlepassgn;
 310 };
 311
 312 struct hi30_ffe_data {
 313         u8 PRE2;
 314         u8 PRE1;
 315         u8 POST1;
 316         u8 POST2;
 317         u8 MAIN;
 318 };
 319
 320 enum hilink_fec_type {
 321         HILINK_FEC_RSFEC,
 322         HILINK_FEC_BASEFEC,
 323         HILINK_FEC_NOFEC,
 324         HILINK_FEC_MAX_TYPE,
 325 };
 326
 327 enum hinic_link_port_type {
 328         LINK_PORT_FIBRE = 1,
 329         LINK_PORT_ELECTRIC,
 330         LINK_PORT_COPPER,
 331         LINK_PORT_AOC,
 332         LINK_PORT_BACKPLANE,
 333         LINK_PORT_BASET,
 334         LINK_PORT_MAX_TYPE,
 335 };
 336
 337 enum hilink_fibre_subtype {
 338         FIBRE_SUBTYPE_SR = 1,
 339         FIBRE_SUBTYPE_LR,
 340         FIBRE_SUBTYPE_MAX,
 341 };
 342
 343 struct hinic_link_info {
 344         u8      vendor_name[16];
 345         /* port type:
 346          * 1 - fiber; 2 - electric; 3 - copper; 4 - AOC; 5 - backplane;
 347          * 6 - baseT; 0xffff - unknown
 348          *
 349          * port subtype:
 350          * Only when port_type is fiber:
 351          * 1 - SR; 2 - LR
 352          */
 353         u32     port_type;
 354         u32     port_sub_type;
 355         u32     cable_length;
 356         u8      cable_temp;
 357         u8      cable_max_speed;/* 1(G)/10(G)/25(G)... */
 358         u8      sfp_type;       /* 0 - qsfp; 1 - sfp */
 359         u8      rsvd0;
 360         u32     power[4];       /* uW; if is sfp, only power[2] is valid */
 361
 362         u8      an_state;       /* 0 - off; 1 - on */
 363         u8      fec;            /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */
 364         u16     speed;          /* 1(G)/10(G)/25(G)... */
 365
 366         u8      cable_absent;   /* 0 - cable present; 1 - cable unpresent */
 367         u8      alos;           /* 0 - yes; 1 - no */
 368         u8      rx_los;         /* 0 - yes; 1 - no */
 369         u8      pma_status;
 370         u32     pma_dbg_info_reg;       /* pma debug info: */
 371         u32     pma_signal_ok_reg;      /* signal ok: */
 372
 373         u32     pcs_err_blk_cnt_reg;    /* error block counter: */
 374         u32     rf_lf_status_reg;       /* RF/LF status: */
 375         u8      pcs_link_reg;           /* pcs link: */
 376         u8      mac_link_reg;           /* mac link: */
 377         u8      mac_tx_en;
 378         u8      mac_rx_en;
 379         u32     pcs_err_cnt;
 380
 381         u8      lane_used;
 382         u8      hi30_ffe[5];
 383         u8      hi30_ctle[19];
 384         u8      hi30_dfe[14];
 385         u8      rsvd4;
 386 };
 387
 388 struct hinic_hilink_link_info {
 389         struct hinic_mgmt_msg_head mgmt_msg_head;
 390
 391         u16     port_id;
 392         u8      info_type;      /* 1: link up  2: link down  3 cable plugged */
 393         u8      rsvd1;
 394
 395         struct hinic_link_info info;
 396
 397         u8      rsvd2[780];
 398 };
 399
 400 /* dma os dependency implementation */
 401 struct hinic_os_dep {
 402         /* kernel dma alloc api */
 403         rte_atomic32_t dma_alloc_cnt;
 404         rte_spinlock_t  dma_hash_lock;
 405         struct rte_hash *dma_addr_hash;
 406 };
 407
 408 struct nic_interrupt_info {
 409         u32 lli_set;
 410         u32 interrupt_coalesc_set;
 411         u16 msix_index;
 412         u8 lli_credit_limit;
 413         u8 lli_timer_cfg;
 414         u8 pending_limt;
 415         u8 coalesc_timer_cfg;
 416         u8 resend_timer_cfg;
 417 };
 418
 419 struct hinic_sq_attr {
 420         u8 dma_attr_off;
 421         u8 pending_limit;
 422         u8 coalescing_time;
 423         u8 intr_en;
 424         u16 intr_idx;
 425         u32 l2nic_sqn;
 426         /* bit[63:2] is addr's high 62bit, bit[0] is valid flag */
 427         u64 ci_dma_base;
 428 };
 429
 430 struct hinic_hwdev {
 431         struct rte_pci_device *pcidev_hdl;
 432         u32 ffm_num;
 433
 434         /* dma memory allocator */
 435         struct hinic_os_dep os_dep;
 436         struct hinic_hwif *hwif;
 437         struct cfg_mgmt_info *cfg_mgmt;
 438         struct hinic_aeqs *aeqs;
 439         struct hinic_msg_pf_to_mgmt *pf_to_mgmt;
 440         struct hinic_cmdqs *cmdqs;
 441         struct hinic_nic_io *nic_io;
 442
 443 };
 444
 445 int hinic_osdep_init(struct hinic_hwdev *hwdev);
 446
 447 void hinic_osdep_deinit(struct hinic_hwdev *hwdev);
 448
 449 void dma_free_coherent_volatile(void *hwdev, size_t size,
 450                                 volatile void *virt, dma_addr_t phys);
 451
 452 int hinic_get_board_info(void *hwdev, struct hinic_board_info *info);
 453
 454 int hinic_set_ci_table(void *hwdev, u16 q_id, struct hinic_sq_attr *attr);
 455
 456 int hinic_func_rx_tx_flush(struct hinic_hwdev *hwdev);
 457
 458 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev,
 459                             struct nic_interrupt_info interrupt_info);
 460
 461 int init_aeqs_msix_attr(void *hwdev);
 462
 463 void hinic_comm_async_event_handle(struct hinic_hwdev *hwdev, u8 cmd,
 464                                    void *buf_in, u16 in_size,
 465                                    void *buf_out, u16 *out_size);
 466
 467 void hinic_l2nic_async_event_handle(struct hinic_hwdev *hwdev, void *param,
 468                                     u8 cmd, void *buf_in, u16 in_size,
 469                                     void *buf_out, u16 *out_size);
 470
 471 void hinic_hilink_async_event_handle(struct hinic_hwdev *hwdev, u8 cmd,
 472                                      void *buf_in, u16 in_size, void *buf_out,
 473                                      u16 *out_size);
 474
 475 int hinic_init_attr_table(struct hinic_hwdev *hwdev);
 476
 477 int hinic_activate_hwdev_state(struct hinic_hwdev *hwdev);
 478
 479 void hinic_deactivate_hwdev_state(struct hinic_hwdev *hwdev);
 480
 481 int hinic_l2nic_reset(struct hinic_hwdev *hwdev);
 482
 483 int hinic_set_pagesize(void *hwdev, u8 page_size);
 484
 485 #endif /* _HINIC_PMD_HWDEV_H_ */