1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PMD_NICCFG_H_
6 #define _HINIC_PMD_NICCFG_H_
8 #define OS_VF_ID_TO_HW(os_vf_id) ((os_vf_id) + 1)
9 #define HW_VF_ID_TO_OS(hw_vf_id) ((hw_vf_id) - 1)
11 #define HINIC_VLAN_PRIORITY_SHIFT 13
13 #define HINIC_RSS_INDIR_SIZE 256
14 #define HINIC_DCB_TC_MAX 0x8
15 #define HINIC_DCB_UP_MAX 0x8
16 #define HINIC_DCB_PG_MAX 0x8
17 #define HINIC_RSS_KEY_SIZE 40
19 #define HINIC_MAX_NUM_RQ 64
21 #define ANTI_ATTACK_DEFAULT_CIR 500000
22 #define ANTI_ATTACK_DEFAULT_XIR 600000
23 #define ANTI_ATTACK_DEFAULT_CBS 10000000
24 #define ANTI_ATTACK_DEFAULT_XBS 12000000
26 #define NIC_RSS_INDIR_SIZE 256
27 #define NIC_RSS_KEY_SIZE 40
28 #define NIC_RSS_CMD_TEMP_ALLOC 0x01
29 #define NIC_RSS_CMD_TEMP_FREE 0x02
30 #define NIC_DCB_UP_MAX 0x8
32 enum hinic_rss_hash_type {
33 HINIC_RSS_HASH_ENGINE_TYPE_XOR = 0,
34 HINIC_RSS_HASH_ENGINE_TYPE_TOEP,
36 HINIC_RSS_HASH_ENGINE_TYPE_MAX,
39 struct nic_port_info {
47 enum nic_speed_level {
58 enum hinic_link_status {
63 struct hinic_up_ets_cfg {
64 struct hinic_mgmt_msg_head mgmt_msg_head;
68 u8 up_tc[HINIC_DCB_UP_MAX];
69 u8 pg_bw[HINIC_DCB_PG_MAX];
70 u8 pgid[HINIC_DCB_UP_MAX];
71 u8 up_bw[HINIC_DCB_UP_MAX];
72 u8 prio[HINIC_DCB_PG_MAX];
75 struct nic_pause_config {
93 HINIC_RX_MODE_UC = 1 << 0,
94 HINIC_RX_MODE_MC = 1 << 1,
95 HINIC_RX_MODE_BC = 1 << 2,
96 HINIC_RX_MODE_MC_ALL = 1 << 3,
97 HINIC_RX_MODE_PROMISC = 1 << 4,
100 enum hinic_link_mode {
101 HINIC_10GE_BASE_KR = 0,
102 HINIC_40GE_BASE_KR4 = 1,
103 HINIC_40GE_BASE_CR4 = 2,
104 HINIC_100GE_BASE_KR4 = 3,
105 HINIC_100GE_BASE_CR4 = 4,
106 HINIC_25GE_BASE_KR_S = 5,
107 HINIC_25GE_BASE_CR_S = 6,
108 HINIC_25GE_BASE_KR = 7,
109 HINIC_25GE_BASE_CR = 8,
110 HINIC_GE_BASE_KX = 9,
111 HINIC_LINK_MODE_NUMBERS,
113 HINIC_SUPPORTED_UNKNOWN = 0xFFFF,
116 #define HINIC_DEFAULT_RX_MODE (HINIC_RX_MODE_UC | HINIC_RX_MODE_MC | \
119 #define HINIC_MAX_MTU_SIZE (9600)
120 #define HINIC_MIN_MTU_SIZE (256)
122 /* MIN_MTU + ETH_HLEN + CRC (256+14+4) */
123 #define HINIC_MIN_FRAME_SIZE 274
125 /* MAX_MTU + ETH_HLEN + CRC + VLAN(9600+14+4+4) */
126 #define HINIC_MAX_JUMBO_FRAME_SIZE (9622)
128 #define HINIC_PORT_DISABLE 0x0
129 #define HINIC_PORT_ENABLE 0x3
131 struct hinic_vport_stats {
132 u64 tx_unicast_pkts_vport;
133 u64 tx_unicast_bytes_vport;
134 u64 tx_multicast_pkts_vport;
135 u64 tx_multicast_bytes_vport;
136 u64 tx_broadcast_pkts_vport;
137 u64 tx_broadcast_bytes_vport;
139 u64 rx_unicast_pkts_vport;
140 u64 rx_unicast_bytes_vport;
141 u64 rx_multicast_pkts_vport;
142 u64 rx_multicast_bytes_vport;
143 u64 rx_broadcast_pkts_vport;
144 u64 rx_broadcast_bytes_vport;
146 u64 tx_discard_vport;
147 u64 rx_discard_vport;
149 u64 rx_err_vport; /* rx checksum err pkts in ucode */
152 struct hinic_phy_port_stats {
153 u64 mac_rx_total_pkt_num;
154 u64 mac_rx_total_oct_num;
155 u64 mac_rx_bad_pkt_num;
156 u64 mac_rx_bad_oct_num;
157 u64 mac_rx_good_pkt_num;
158 u64 mac_rx_good_oct_num;
159 u64 mac_rx_uni_pkt_num;
160 u64 mac_rx_multi_pkt_num;
161 u64 mac_rx_broad_pkt_num;
163 u64 mac_tx_total_pkt_num;
164 u64 mac_tx_total_oct_num;
165 u64 mac_tx_bad_pkt_num;
166 u64 mac_tx_bad_oct_num;
167 u64 mac_tx_good_pkt_num;
168 u64 mac_tx_good_oct_num;
169 u64 mac_tx_uni_pkt_num;
170 u64 mac_tx_multi_pkt_num;
171 u64 mac_tx_broad_pkt_num;
173 u64 mac_rx_fragment_pkt_num;
174 u64 mac_rx_undersize_pkt_num;
175 u64 mac_rx_undermin_pkt_num;
176 u64 mac_rx_64_oct_pkt_num;
177 u64 mac_rx_65_127_oct_pkt_num;
178 u64 mac_rx_128_255_oct_pkt_num;
179 u64 mac_rx_256_511_oct_pkt_num;
180 u64 mac_rx_512_1023_oct_pkt_num;
181 u64 mac_rx_1024_1518_oct_pkt_num;
182 u64 mac_rx_1519_2047_oct_pkt_num;
183 u64 mac_rx_2048_4095_oct_pkt_num;
184 u64 mac_rx_4096_8191_oct_pkt_num;
185 u64 mac_rx_8192_9216_oct_pkt_num;
186 u64 mac_rx_9217_12287_oct_pkt_num;
187 u64 mac_rx_12288_16383_oct_pkt_num;
188 u64 mac_rx_1519_max_bad_pkt_num;
189 u64 mac_rx_1519_max_good_pkt_num;
190 u64 mac_rx_oversize_pkt_num;
191 u64 mac_rx_jabber_pkt_num;
193 u64 mac_rx_mac_pause_num;
194 u64 mac_rx_pfc_pkt_num;
195 u64 mac_rx_pfc_pri0_pkt_num;
196 u64 mac_rx_pfc_pri1_pkt_num;
197 u64 mac_rx_pfc_pri2_pkt_num;
198 u64 mac_rx_pfc_pri3_pkt_num;
199 u64 mac_rx_pfc_pri4_pkt_num;
200 u64 mac_rx_pfc_pri5_pkt_num;
201 u64 mac_rx_pfc_pri6_pkt_num;
202 u64 mac_rx_pfc_pri7_pkt_num;
203 u64 mac_rx_mac_control_pkt_num;
204 u64 mac_rx_y1731_pkt_num;
205 u64 mac_rx_sym_err_pkt_num;
206 u64 mac_rx_fcs_err_pkt_num;
207 u64 mac_rx_send_app_good_pkt_num;
208 u64 mac_rx_send_app_bad_pkt_num;
210 u64 mac_tx_fragment_pkt_num;
211 u64 mac_tx_undersize_pkt_num;
212 u64 mac_tx_undermin_pkt_num;
213 u64 mac_tx_64_oct_pkt_num;
214 u64 mac_tx_65_127_oct_pkt_num;
215 u64 mac_tx_128_255_oct_pkt_num;
216 u64 mac_tx_256_511_oct_pkt_num;
217 u64 mac_tx_512_1023_oct_pkt_num;
218 u64 mac_tx_1024_1518_oct_pkt_num;
219 u64 mac_tx_1519_2047_oct_pkt_num;
220 u64 mac_tx_2048_4095_oct_pkt_num;
221 u64 mac_tx_4096_8191_oct_pkt_num;
222 u64 mac_tx_8192_9216_oct_pkt_num;
223 u64 mac_tx_9217_12287_oct_pkt_num;
224 u64 mac_tx_12288_16383_oct_pkt_num;
225 u64 mac_tx_1519_max_bad_pkt_num;
226 u64 mac_tx_1519_max_good_pkt_num;
227 u64 mac_tx_oversize_pkt_num;
228 u64 mac_trans_jabber_pkt_num;
230 u64 mac_tx_mac_pause_num;
231 u64 mac_tx_pfc_pkt_num;
232 u64 mac_tx_pfc_pri0_pkt_num;
233 u64 mac_tx_pfc_pri1_pkt_num;
234 u64 mac_tx_pfc_pri2_pkt_num;
235 u64 mac_tx_pfc_pri3_pkt_num;
236 u64 mac_tx_pfc_pri4_pkt_num;
237 u64 mac_tx_pfc_pri5_pkt_num;
238 u64 mac_tx_pfc_pri6_pkt_num;
239 u64 mac_tx_pfc_pri7_pkt_num;
240 u64 mac_tx_mac_control_pkt_num;
241 u64 mac_tx_y1731_pkt_num;
242 u64 mac_tx_1588_pkt_num;
243 u64 mac_tx_err_all_pkt_num;
244 u64 mac_tx_from_app_good_pkt_num;
245 u64 mac_tx_from_app_bad_pkt_num;
247 u64 rx_higig2_ext_pkts_port;
248 u64 rx_higig2_message_pkts_port;
249 u64 rx_higig2_error_pkts_port;
250 u64 rx_higig2_cpu_ctrl_pkts_port;
251 u64 rx_higig2_unicast_pkts_port;
252 u64 rx_higig2_broadcast_pkts_port;
253 u64 rx_higig2_l2_multicast_pkts;
254 u64 rx_higig2_l3_multicast_pkts;
256 u64 tx_higig2_message_pkts_port;
257 u64 tx_higig2_ext_pkts_port;
258 u64 tx_higig2_cpu_ctrl_pkts_port;
259 u64 tx_higig2_unicast_pkts_port;
260 u64 tx_higig2_broadcast_pkts_port;
261 u64 tx_higig2_l2_multicast_pkts;
262 u64 tx_higig2_l3_multicast_pkts;
265 enum hinic_link_follow_status {
266 HINIC_LINK_FOLLOW_DEFAULT,
267 HINIC_LINK_FOLLOW_PORT,
268 HINIC_LINK_FOLLOW_SEPARATE,
269 HINIC_LINK_FOLLOW_STATUS_MAX,
272 #define HINIC_PORT_STATS_VERSION 0
273 struct hinic_port_stats_info {
274 struct hinic_mgmt_msg_head mgmt_msg_head;
282 struct hinic_port_stats {
283 struct hinic_mgmt_msg_head mgmt_msg_head;
285 struct hinic_phy_port_stats stats;
288 struct hinic_cmd_vport_stats {
289 struct hinic_mgmt_msg_head mgmt_msg_head;
291 struct hinic_vport_stats stats;
294 struct hinic_clear_port_stats {
295 struct hinic_mgmt_msg_head mgmt_msg_head;
303 struct hinic_clear_vport_stats {
304 struct hinic_mgmt_msg_head mgmt_msg_head;
312 struct hinic_fast_recycled_mode {
313 struct hinic_mgmt_msg_head mgmt_msg_head;
317 * 1: enable fast recycle, available in dpdk mode,
318 * 0: normal mode, available in kernel nic mode
320 u8 fast_recycled_mode;
324 struct hinic_function_table {
325 struct hinic_mgmt_msg_head mgmt_msg_head;
332 struct hinic_cmd_qpn {
333 struct hinic_mgmt_msg_head mgmt_msg_head;
339 struct hinic_port_mac_set {
340 struct hinic_mgmt_msg_head mgmt_msg_head;
348 struct hinic_port_mac_update {
349 struct hinic_mgmt_msg_head mgmt_msg_head;
354 u8 old_mac[ETH_ALEN];
356 u8 new_mac[ETH_ALEN];
359 struct hinic_vport_state {
360 struct hinic_mgmt_msg_head mgmt_msg_head;
368 struct hinic_port_state {
369 struct hinic_mgmt_msg_head mgmt_msg_head;
376 struct hinic_mgmt_msg_head mgmt_msg_head;
383 struct hinic_vlan_config {
384 struct hinic_mgmt_msg_head mgmt_msg_head;
390 struct hinic_vlan_filter {
391 struct hinic_mgmt_msg_head mgmt_msg_head;
395 u32 vlan_filter_ctrl;
398 struct hinic_vlan_offload {
399 struct hinic_mgmt_msg_head mgmt_msg_head;
406 struct hinic_get_link {
407 struct hinic_mgmt_msg_head mgmt_msg_head;
414 #define HINIC_DEFAUT_PAUSE_CONFIG 1
415 struct hinic_pause_config {
416 struct hinic_mgmt_msg_head mgmt_msg_head;
425 struct hinic_port_info {
426 struct hinic_mgmt_msg_head mgmt_msg_head;
438 struct hinic_tso_config {
439 struct hinic_mgmt_msg_head mgmt_msg_head;
447 struct hinic_lro_config {
448 struct hinic_mgmt_msg_head mgmt_msg_head;
458 struct hinic_checksum_offload {
459 struct hinic_mgmt_msg_head mgmt_msg_head;
466 struct hinic_rx_mode_config {
467 struct hinic_mgmt_msg_head mgmt_msg_head;
475 struct nic_rss_indirect_tbl {
480 u8 entry[NIC_RSS_INDIR_SIZE];
483 struct nic_rss_context_tbl {
491 struct hinic_rss_config {
492 struct hinic_mgmt_msg_head mgmt_msg_head;
497 u8 rq_priority_number;
499 u8 prio_tc[NIC_DCB_UP_MAX];
502 struct hinic_rss_template_mgmt {
503 struct hinic_mgmt_msg_head mgmt_msg_head;
511 struct hinic_rss_indir_table {
512 struct hinic_mgmt_msg_head mgmt_msg_head;
517 u8 indir[NIC_RSS_INDIR_SIZE];
520 struct hinic_rss_template_key {
521 struct hinic_mgmt_msg_head mgmt_msg_head;
526 u8 key[NIC_RSS_KEY_SIZE];
529 struct hinic_rss_engine_type {
530 struct hinic_mgmt_msg_head mgmt_msg_head;
538 struct hinic_rss_context_table {
539 struct hinic_mgmt_msg_head mgmt_msg_head;
547 struct hinic_reset_link_cfg {
548 struct hinic_mgmt_msg_head mgmt_msg_head;
554 struct hinic_set_vhd_mode {
555 struct hinic_mgmt_msg_head mgmt_msg_head;
559 u16 rx_wqe_buffer_size;
563 struct hinic_set_link_follow {
564 struct hinic_mgmt_msg_head mgmt_msg_head;
572 struct hinic_link_mode_cmd {
573 struct hinic_mgmt_msg_head mgmt_msg_head;
577 u16 supported; /* 0xFFFF represent Invalid value */
581 struct hinic_set_xsfp_status {
582 struct hinic_mgmt_msg_head mgmt_msg_head;
585 u32 xsfp_tx_dis; /* 0: tx enable; 1: tx disable */
588 struct hinic_clear_qp_resource {
589 struct hinic_mgmt_msg_head mgmt_msg_head;
595 struct hinic_dcb_state {
601 struct hinic_vf_default_cos {
602 struct hinic_mgmt_msg_head mgmt_msg_head;
604 struct hinic_dcb_state state;
607 /* set physical port Anti-Attack rate */
608 struct hinic_port_anti_attack_rate {
609 struct hinic_mgmt_msg_head mgmt_msg_head;
612 u16 enable; /* 1: enable rate-limiting, 0: disable rate-limiting */
613 u32 cir; /* Committed Information Rate */
614 u32 xir; /* eXtended Information Rate */
615 u32 cbs; /* Committed Burst Size */
616 u32 xbs; /* eXtended Burst Size */
644 struct tag_pa_eth_ip_header {
645 struct pa_u8_s ip_ver; /* 3bit */
646 struct pa_u8_s ipv4_option_flag; /* 1bit */
647 /* 8bit ipv4 option or ipv6 next header */
648 struct pa_u8_s protocol;
649 struct pa_u8_s dscp; /* 6bit DSCP */
652 struct tag_pa_common_l2_header {
653 struct pa_u48_s dmac; /* dmac 48bit */
654 struct pa_u16_s eth_type; /* ethernet type/length 16bit */
655 struct pa_u8_s tag_flag; /* tag flag: 4bit */
656 struct pa_u8_s np2np_hdr_qindex; /* NP2NP Header Qindex 4bit */
657 struct pa_u8_s e_tag_pcp; /* 3bit */
658 struct pa_u8_s vlan_layer; /* 2bit */
659 struct pa_u8_s s_tag; /* 3bit */
660 struct pa_u8_s c_tag; /* 3bit */
661 struct pa_u16_s vlan_id; /* 12bit */
665 struct pa_u16_s sport; /* 16bit */
666 struct pa_u16_s dport; /* 16bit */
667 struct pa_u16_s tcp_flag; /* 6bit */
671 struct pa_u16_s sport; /* 16bit */
672 struct pa_u16_s dport; /* 16bit */
674 * 1.udp dport=67/68 && ipv4 protocol=0x11
675 * 2.udp dport=546/547 && ipv6 next header=0x11
678 struct pa_u8_s dhcp_op_or_msg_type;
682 * ipv4 protocol = 0x1
683 * ipv6 next header = 0x3A
686 struct pa_u8_s type; /* 8bit */
687 struct pa_u8_s code; /* 8bit */
691 * ipv4 protocol = 0x2
693 struct tag_pa_ipv4_igmp {
694 struct pa_u32_s dip; /* 32bit */
695 struct pa_u8_s type; /* 8bit */
699 struct pa_u8_s ncsi_flag; /* 1bit valid */
700 struct tag_pa_common_l2_header l2_header;
704 struct pa_u64_s eth_other; /* eth_type=other 64bit */
705 struct pa_u8_s eth_roce_opcode; /* eth_type=roce 8bit opcode */
707 struct tag_pa_eth_ip_header ip_header; /* eth_type=ip */
711 struct tag_pa_tcp eth_ip_tcp; /* eth_type=ip && ip_protocol = tcp */
712 struct tag_pa_udp eth_ip_udp; /* eth_type=ip && ip_protocol = udp */
713 struct tag_pa_icmp eth_ip_icmp; /* eth_type=ip && ip_protocol = icmp */
715 /* eth_type=ip && ip_protocol = ipv4_igmp */
716 struct tag_pa_ipv4_igmp eth_ipv4_igmp;
718 /* eth_type=ip && ip_protocol = sctp;
719 * 16bit ipv4 protocol=0x84 or ipv6 nhr=0x84
721 struct pa_u16_s eth_ip_sctp;
724 struct tag_pa_action {
732 struct hinic_fdir_tcam_info {
733 struct hinic_mgmt_msg_head mgmt_msg_head;
736 u8 flag; /* clear or set tcam table flag */
738 struct tag_pa_rule filter_rule;
739 struct tag_pa_action filter_action;
742 int hinic_set_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id);
744 int hinic_del_mac(void *hwdev, u8 *mac_addr, u16 vlan_id, u16 func_id);
746 int hinic_update_mac(void *hwdev, u8 *old_mac, u8 *new_mac, u16 vlan_id,
749 int hinic_get_default_mac(void *hwdev, u8 *mac_addr);
751 int hinic_set_port_mtu(void *hwdev, u32 new_mtu);
753 int hinic_add_remove_vlan(void *hwdev, u16 vlan_id, u16 func_id, bool add);
755 int hinic_config_vlan_filter(void *hwdev, u32 vlan_filter_ctrl);
757 int hinic_set_rx_vlan_offload(void *hwdev, u8 en);
759 int hinic_set_vport_enable(void *hwdev, bool enable);
761 int hinic_set_port_enable(void *hwdev, bool enable);
763 int hinic_get_link_status(void *hwdev, u8 *link_state);
765 int hinic_get_port_info(void *hwdev, struct nic_port_info *port_info);
767 int hinic_set_rx_vhd_mode(void *hwdev, u16 vhd_mode, u16 rx_buf_sz);
769 int hinic_set_pause_config(void *hwdev, struct nic_pause_config nic_pause);
771 int hinic_reset_port_link_cfg(void *hwdev);
773 int hinic_dcb_set_ets(void *hwdev, u8 *up_tc, u8 *pg_bw, u8 *pgid, u8 *up_bw,
776 int hinic_set_anti_attack(void *hwdev, bool enable);
778 /* offload feature */
779 int hinic_set_rx_lro(void *hwdev, u8 ipv4_en, u8 ipv6_en, u8 max_wqe_num);
781 int hinic_get_vport_stats(void *hwdev, struct hinic_vport_stats *stats);
783 int hinic_get_phy_port_stats(void *hwdev, struct hinic_phy_port_stats *stats);
786 int hinic_set_rss_type(void *hwdev, u32 tmpl_idx,
787 struct nic_rss_type rss_type);
789 int hinic_get_rss_type(void *hwdev, u32 tmpl_idx,
790 struct nic_rss_type *rss_type);
792 int hinic_rss_set_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp);
794 int hinic_rss_get_template_tbl(void *hwdev, u32 tmpl_idx, u8 *temp);
796 int hinic_rss_set_hash_engine(void *hwdev, u8 tmpl_idx, u8 type);
798 int hinic_rss_get_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table);
800 int hinic_rss_set_indir_tbl(void *hwdev, u32 tmpl_idx, u32 *indir_table);
802 int hinic_rss_cfg(void *hwdev, u8 rss_en, u8 tmpl_idx, u8 tc_num, u8 *prio_tc);
804 int hinic_rss_template_alloc(void *hwdev, u8 *tmpl_idx);
806 int hinic_rss_template_free(void *hwdev, u8 tmpl_idx);
808 int hinic_set_rx_mode(void *hwdev, u32 enable);
810 int hinic_set_rx_csum_offload(void *hwdev, u32 en);
812 int hinic_set_link_status_follow(void *hwdev,
813 enum hinic_link_follow_status status);
815 int hinic_get_link_mode(void *hwdev, u32 *supported, u32 *advertised);
817 int hinic_set_xsfp_tx_status(void *hwdev, bool enable);
819 int hinic_flush_qp_res(void *hwdev);
821 int hinic_init_function_table(void *hwdev, u16 rx_buf_sz);
823 int hinic_set_fast_recycle_mode(void *hwdev, u8 mode);
825 int hinic_get_base_qpn(void *hwdev, u16 *global_qpn);
827 int hinic_clear_vport_stats(struct hinic_hwdev *hwdev);
829 int hinic_clear_phy_port_stats(struct hinic_hwdev *hwdev);
831 int hinic_vf_func_init(struct hinic_hwdev *hwdev);
833 void hinic_vf_func_free(struct hinic_hwdev *hwdev);
835 int hinic_vf_get_default_cos(struct hinic_hwdev *hwdev, u8 *cos_id);
837 int hinic_set_fdir_filter(void *hwdev, u8 filter_type, u8 qid,
838 u8 type_enable, bool enable);
840 int hinic_set_normal_filter(void *hwdev, u8 qid, u8 normal_type_enable,
841 u32 key, bool enable, u8 flag);
843 int hinic_set_fdir_tcam(void *hwdev, u16 type_mask,
844 struct tag_pa_rule *filter_rule, struct tag_pa_action *filter_action);
846 int hinic_clear_fdir_tcam(void *hwdev, u16 type_mask);
848 #endif /* _HINIC_PMD_NICCFG_H_ */