drivers/net/hinic/base/hinic_pmd_nicio.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
   3  */
   4
   5 #ifndef _HINIC_PMD_NICIO_H_
   6 #define _HINIC_PMD_NICIO_H_
   7
   8 #define RX_BUF_LEN_16K                  16384
   9 #define RX_BUF_LEN_1_5K                 1536
  10
  11 #define HINIC_Q_CTXT_MAX                42
  12
  13 /* performance: ci addr RTE_CACHE_SIZE(64B) alignment */
  14 #define HINIC_CI_Q_ADDR_SIZE            64
  15
  16 #define CI_TABLE_SIZE(num_qps, pg_sz)   \
  17         (ALIGN((num_qps) * HINIC_CI_Q_ADDR_SIZE, pg_sz))
  18
  19 #define HINIC_CI_VADDR(base_addr, q_id)         \
  20         ((u8 *)(base_addr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
  21
  22 #define HINIC_CI_PADDR(base_paddr, q_id)        \
  23         ((base_paddr) + (q_id) * HINIC_CI_Q_ADDR_SIZE)
  24
  25 #define Q_CTXT_SIZE                             48
  26 #define TSO_LRO_CTXT_SIZE                       240
  27
  28 #define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id)  \
  29         (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE +  \
  30                 (q_id) * Q_CTXT_SIZE)
  31
  32 #define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id)  \
  33         (((max_rqs) + (max_sqs)) * TSO_LRO_CTXT_SIZE +  \
  34                 (max_sqs) * Q_CTXT_SIZE + (q_id) * Q_CTXT_SIZE)
  35
  36 #define SQ_CTXT_SIZE(num_sqs)           \
  37         ((u16)(sizeof(struct hinic_qp_ctxt_header) +    \
  38                 (num_sqs) * sizeof(struct hinic_sq_ctxt)))
  39
  40 #define RQ_CTXT_SIZE(num_rqs)           \
  41         ((u16)(sizeof(struct hinic_qp_ctxt_header) +    \
  42                 (num_rqs) * sizeof(struct hinic_rq_ctxt)))
  43
  44 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_SHIFT                   8
  45 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT             13
  46 #define SQ_CTXT_CEQ_ATTR_EN_SHIFT                       23
  47 #define SQ_CTXT_CEQ_ATTR_ARM_SHIFT                      31
  48
  49 #define SQ_CTXT_CEQ_ATTR_CEQ_ID_MASK                    0x1FU
  50 #define SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK              0x3FFU
  51 #define SQ_CTXT_CEQ_ATTR_EN_MASK                        0x1U
  52 #define SQ_CTXT_CEQ_ATTR_ARM_MASK                       0x1U
  53
  54 #define SQ_CTXT_CEQ_ATTR_SET(val, member)       \
  55         (((val) & SQ_CTXT_CEQ_ATTR_##member##_MASK) <<  \
  56                 SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
  57
  58 #define SQ_CTXT_CI_IDX_SHIFT                            11
  59 #define SQ_CTXT_CI_OWNER_SHIFT                          23
  60
  61 #define SQ_CTXT_CI_IDX_MASK                             0xFFFU
  62 #define SQ_CTXT_CI_OWNER_MASK                           0x1U
  63
  64 #define SQ_CTXT_CI_SET(val, member)             \
  65         (((val) & SQ_CTXT_CI_##member##_MASK) << SQ_CTXT_CI_##member##_SHIFT)
  66
  67 #define SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT                    0
  68 #define SQ_CTXT_WQ_PAGE_PI_SHIFT                        20
  69
  70 #define SQ_CTXT_WQ_PAGE_HI_PFN_MASK                     0xFFFFFU
  71 #define SQ_CTXT_WQ_PAGE_PI_MASK                         0xFFFU
  72
  73 #define SQ_CTXT_WQ_PAGE_SET(val, member)        \
  74         (((val) & SQ_CTXT_WQ_PAGE_##member##_MASK) <<   \
  75                 SQ_CTXT_WQ_PAGE_##member##_SHIFT)
  76
  77 #define SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT              0
  78 #define SQ_CTXT_PREF_CACHE_MAX_SHIFT                    14
  79 #define SQ_CTXT_PREF_CACHE_MIN_SHIFT                    25
  80
  81 #define SQ_CTXT_PREF_CACHE_THRESHOLD_MASK               0x3FFFU
  82 #define SQ_CTXT_PREF_CACHE_MAX_MASK                     0x7FFU
  83 #define SQ_CTXT_PREF_CACHE_MIN_MASK                     0x7FU
  84
  85 #define SQ_CTXT_PREF_WQ_PFN_HI_SHIFT                    0
  86 #define SQ_CTXT_PREF_CI_SHIFT                           20
  87
  88 #define SQ_CTXT_PREF_WQ_PFN_HI_MASK                     0xFFFFFU
  89 #define SQ_CTXT_PREF_CI_MASK                            0xFFFU
  90
  91 #define SQ_CTXT_PREF_SET(val, member)           \
  92         (((val) & SQ_CTXT_PREF_##member##_MASK) <<      \
  93                 SQ_CTXT_PREF_##member##_SHIFT)
  94
  95 #define SQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT                   0
  96
  97 #define SQ_CTXT_WQ_BLOCK_PFN_HI_MASK                    0x7FFFFFU
  98
  99 #define SQ_CTXT_WQ_BLOCK_SET(val, member)       \
 100         (((val) & SQ_CTXT_WQ_BLOCK_##member##_MASK) <<  \
 101                 SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
 102
 103 #define RQ_CTXT_CEQ_ATTR_EN_SHIFT                       0
 104 #define RQ_CTXT_CEQ_ATTR_OWNER_SHIFT                    1
 105
 106 #define RQ_CTXT_CEQ_ATTR_EN_MASK                        0x1U
 107 #define RQ_CTXT_CEQ_ATTR_OWNER_MASK                     0x1U
 108
 109 #define RQ_CTXT_CEQ_ATTR_SET(val, member)       \
 110         (((val) & RQ_CTXT_CEQ_ATTR_##member##_MASK) <<  \
 111                 RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
 112
 113 #define RQ_CTXT_PI_IDX_SHIFT                            0
 114 #define RQ_CTXT_PI_INTR_SHIFT                           22
 115 #define RQ_CTXT_PI_CEQ_ARM_SHIFT                        31
 116
 117 #define RQ_CTXT_PI_IDX_MASK                             0xFFFU
 118 #define RQ_CTXT_PI_INTR_MASK                            0x3FFU
 119 #define RQ_CTXT_PI_CEQ_ARM_MASK                         0x1U
 120
 121 #define RQ_CTXT_PI_SET(val, member)             \
 122         (((val) & RQ_CTXT_PI_##member##_MASK) << RQ_CTXT_PI_##member##_SHIFT)
 123
 124 #define RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT                    0
 125 #define RQ_CTXT_WQ_PAGE_CI_SHIFT                        20
 126
 127 #define RQ_CTXT_WQ_PAGE_HI_PFN_MASK                     0xFFFFFU
 128 #define RQ_CTXT_WQ_PAGE_CI_MASK                         0xFFFU
 129
 130 #define RQ_CTXT_WQ_PAGE_SET(val, member)        \
 131         (((val) & RQ_CTXT_WQ_PAGE_##member##_MASK) << \
 132                 RQ_CTXT_WQ_PAGE_##member##_SHIFT)
 133
 134 #define RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT              0
 135 #define RQ_CTXT_PREF_CACHE_MAX_SHIFT                    14
 136 #define RQ_CTXT_PREF_CACHE_MIN_SHIFT                    25
 137
 138 #define RQ_CTXT_PREF_CACHE_THRESHOLD_MASK               0x3FFFU
 139 #define RQ_CTXT_PREF_CACHE_MAX_MASK                     0x7FFU
 140 #define RQ_CTXT_PREF_CACHE_MIN_MASK                     0x7FU
 141
 142 #define RQ_CTXT_PREF_WQ_PFN_HI_SHIFT                    0
 143 #define RQ_CTXT_PREF_CI_SHIFT                           20
 144
 145 #define RQ_CTXT_PREF_WQ_PFN_HI_MASK                     0xFFFFFU
 146 #define RQ_CTXT_PREF_CI_MASK                            0xFFFU
 147
 148 #define RQ_CTXT_PREF_SET(val, member)           \
 149         (((val) & RQ_CTXT_PREF_##member##_MASK) <<      \
 150                 RQ_CTXT_PREF_##member##_SHIFT)
 151
 152 #define RQ_CTXT_WQ_BLOCK_PFN_HI_SHIFT                   0
 153
 154 #define RQ_CTXT_WQ_BLOCK_PFN_HI_MASK                    0x7FFFFFU
 155
 156 #define RQ_CTXT_WQ_BLOCK_SET(val, member)       \
 157         (((val) & RQ_CTXT_WQ_BLOCK_##member##_MASK) <<  \
 158                 RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
 159
 160 #define SIZE_16BYTES(size)              (ALIGN((size), 16) >> 4)
 161
 162 enum hinic_qp_ctxt_type {
 163         HINIC_QP_CTXT_TYPE_SQ,
 164         HINIC_QP_CTXT_TYPE_RQ,
 165 };
 166
 167 struct hinic_sq {
 168         struct hinic_wq         *wq;
 169         volatile u16            *cons_idx_addr;
 170         void __iomem            *db_addr;
 171
 172         u16     q_id;
 173         u16     owner;
 174         u16     sq_depth;
 175 };
 176
 177 struct hinic_rq {
 178         struct hinic_wq         *wq;
 179         volatile u16            *pi_virt_addr;
 180         dma_addr_t              pi_dma_addr;
 181
 182         u16                     irq_id;
 183         u16                     msix_entry_idx;
 184         u16                     q_id;
 185         u16                     rq_depth;
 186 };
 187
 188 struct hinic_qp {
 189         struct hinic_sq         sq;
 190         struct hinic_rq         rq;
 191 };
 192
 193 struct hinic_event {
 194         void (*tx_ack)(void *handle, u16 q_id);
 195         /* status: 0 - link down; 1 - link up */
 196         void (*link_change)(void *handle, int status);
 197 };
 198
 199 struct hinic_nic_io {
 200         struct hinic_hwdev      *hwdev;
 201
 202         u16                     global_qpn;
 203
 204         struct hinic_wq         *sq_wq;
 205         struct hinic_wq         *rq_wq;
 206
 207         u16                     max_qps;
 208         u16                     num_qps;
 209
 210         u16                     num_sqs;
 211         u16                     num_rqs;
 212
 213         u16                     sq_depth;
 214         u16                     rq_depth;
 215
 216         u16                     rq_buf_size;
 217         u16                     vhd_mode;
 218
 219         struct hinic_qp         *qps;
 220         /* sq ci mem base addr of the function */
 221         void                    *ci_vaddr_base;
 222         dma_addr_t              ci_dma_base;
 223
 224         struct hinic_event      event;
 225         void                    *event_handle;
 226 };
 227
 228 struct hinic_sq_db {
 229         u32     db_info;
 230 };
 231
 232 int hinic_init_qp_ctxts(struct hinic_hwdev *hwdev);
 233
 234 void hinic_free_qp_ctxts(struct hinic_hwdev *hwdev);
 235
 236 int hinic_rx_tx_flush(struct hinic_hwdev *hwdev);
 237
 238 int hinic_get_sq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
 239
 240 u16 hinic_get_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
 241
 242 void hinic_update_sq_local_ci(struct hinic_hwdev *hwdev, u16 q_id,
 243                               int wqebb_cnt);
 244
 245 void hinic_return_sq_wqe(struct hinic_hwdev *hwdev, u16 q_id,
 246                          int num_wqebbs, u16 owner);
 247
 248 int hinic_get_rq_free_wqebbs(struct hinic_hwdev *hwdev, u16 q_id);
 249
 250 void *hinic_get_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, u16 *pi);
 251
 252 void hinic_return_rq_wqe(struct hinic_hwdev *hwdev, u16 q_id, int num_wqebbs);
 253
 254 u16 hinic_get_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id);
 255
 256 void hinic_update_rq_local_ci(struct hinic_hwdev *hwdev, u16 q_id, int wqe_cnt);
 257
 258 int hinic_init_nicio(struct hinic_hwdev *hwdev);
 259
 260 void hinic_deinit_nicio(struct hinic_hwdev *hwdev);
 261
 262 int hinic_convert_rx_buf_size(u32 rx_buf_sz, u32 *match_sz);
 263
 264 #endif /* _HINIC_PMD_NICIO_H_ */