drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9
  10 #include "hns3_ethdev.h"
  11 #include "hns3_common.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18 #include "hns3_flow.h"
  19
  20 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  21 #define HNS3_SERVICE_QUICK_INTERVAL     10
  22 #define HNS3_INVALID_PVID               0xFFFF
  23
  24 #define HNS3_FILTER_TYPE_VF             0
  25 #define HNS3_FILTER_TYPE_PORT           1
  26 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  27 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  28 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  29 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  30 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  31 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  32                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  33 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  35
  36 /* Reset related Registers */
  37 #define HNS3_GLOBAL_RESET_BIT           0
  38 #define HNS3_CORE_RESET_BIT             1
  39 #define HNS3_IMP_RESET_BIT              2
  40 #define HNS3_FUN_RST_ING_B              0
  41
  42 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  43 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  44 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  45 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  46
  47 #define HNS3_RESET_WAIT_MS      100
  48 #define HNS3_RESET_WAIT_CNT     200
  49
  50 /* FEC mode order defined in HNS3 hardware */
  51 #define HNS3_HW_FEC_MODE_NOFEC  0
  52 #define HNS3_HW_FEC_MODE_BASER  1
  53 #define HNS3_HW_FEC_MODE_RS     2
  54
  55 enum hns3_evt_cause {
  56         HNS3_VECTOR0_EVENT_RST,
  57         HNS3_VECTOR0_EVENT_MBX,
  58         HNS3_VECTOR0_EVENT_ERR,
  59         HNS3_VECTOR0_EVENT_PTP,
  60         HNS3_VECTOR0_EVENT_OTHER,
  61 };
  62
  63 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  64         { RTE_ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  65                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  66                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  67
  68         { RTE_ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  69                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  70                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  72
  73         { RTE_ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  74                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  75                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  76
  77         { RTE_ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  78                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  79                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  81
  82         { RTE_ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  83                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  84                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  85
  86         { RTE_ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  87                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  88                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  89 };
  90
  91 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  92                                                  uint64_t *levels);
  93 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  95                                     int on);
  96 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  97 static bool hns3_update_link_status(struct hns3_hw *hw);
  98
  99 static int hns3_add_mc_mac_addr(struct hns3_hw *hw,
 100                                 struct rte_ether_addr *mac_addr);
 101 static int hns3_remove_mc_mac_addr(struct hns3_hw *hw,
 102                                    struct rte_ether_addr *mac_addr);
 103 static int hns3_restore_fec(struct hns3_hw *hw);
 104 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 105 static int hns3_do_stop(struct hns3_adapter *hns);
 106 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 107 static int hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable);
 108
 109
 110 static void
 111 hns3_pf_disable_irq0(struct hns3_hw *hw)
 112 {
 113         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 114 }
 115
 116 static void
 117 hns3_pf_enable_irq0(struct hns3_hw *hw)
 118 {
 119         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 120 }
 121
 122 static enum hns3_evt_cause
 123 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 124                           uint32_t *vec_val)
 125 {
 126         struct hns3_hw *hw = &hns->hw;
 127
 128         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 129         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 130         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 131         if (!is_delay) {
 132                 hw->reset.stats.imp_cnt++;
 133                 hns3_warn(hw, "IMP reset detected, clear reset status");
 134         } else {
 135                 hns3_schedule_delayed_reset(hns);
 136                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 137         }
 138
 139         return HNS3_VECTOR0_EVENT_RST;
 140 }
 141
 142 static enum hns3_evt_cause
 143 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 144                              uint32_t *vec_val)
 145 {
 146         struct hns3_hw *hw = &hns->hw;
 147
 148         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 149         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 150         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 151         if (!is_delay) {
 152                 hw->reset.stats.global_cnt++;
 153                 hns3_warn(hw, "Global reset detected, clear reset status");
 154         } else {
 155                 hns3_schedule_delayed_reset(hns);
 156                 hns3_warn(hw,
 157                           "Global reset detected, don't clear reset status");
 158         }
 159
 160         return HNS3_VECTOR0_EVENT_RST;
 161 }
 162
 163 static enum hns3_evt_cause
 164 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 165 {
 166         struct hns3_hw *hw = &hns->hw;
 167         uint32_t vector0_int_stats;
 168         uint32_t cmdq_src_val;
 169         uint32_t hw_err_src_reg;
 170         uint32_t val;
 171         enum hns3_evt_cause ret;
 172         bool is_delay;
 173
 174         /* fetch the events from their corresponding regs */
 175         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 176         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 177         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 178
 179         is_delay = clearval == NULL ? true : false;
 180         /*
 181          * Assumption: If by any chance reset and mailbox events are reported
 182          * together then we will only process reset event and defer the
 183          * processing of the mailbox events. Since, we would have not cleared
 184          * RX CMDQ event this time we would receive again another interrupt
 185          * from H/W just for the mailbox.
 186          */
 187         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 188                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 189                 goto out;
 190         }
 191
 192         /* Global reset */
 193         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 194                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 195                 goto out;
 196         }
 197
 198         /* Check for vector0 1588 event source */
 199         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 200                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 201                 ret = HNS3_VECTOR0_EVENT_PTP;
 202                 goto out;
 203         }
 204
 205         /* check for vector0 msix event source */
 206         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 207             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 208                 val = vector0_int_stats | hw_err_src_reg;
 209                 ret = HNS3_VECTOR0_EVENT_ERR;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 mailbox(=CMDQ RX) event source */
 214         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 215                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 216                 val = cmdq_src_val;
 217                 ret = HNS3_VECTOR0_EVENT_MBX;
 218                 goto out;
 219         }
 220
 221         val = vector0_int_stats;
 222         ret = HNS3_VECTOR0_EVENT_OTHER;
 223 out:
 224
 225         if (clearval)
 226                 *clearval = val;
 227         return ret;
 228 }
 229
 230 static bool
 231 hns3_is_1588_event_type(uint32_t event_type)
 232 {
 233         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 234 }
 235
 236 static void
 237 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 238 {
 239         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 240             hns3_is_1588_event_type(event_type))
 241                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 242         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 243                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 244 }
 245
 246 static void
 247 hns3_clear_all_event_cause(struct hns3_hw *hw)
 248 {
 249         uint32_t vector0_int_stats;
 250
 251         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 252         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 253                 hns3_warn(hw, "Probe during IMP reset interrupt");
 254
 255         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 256                 hns3_warn(hw, "Probe during Global reset interrupt");
 257
 258         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 259                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 260                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 261                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 262         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 263         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 264                                 BIT(HNS3_VECTOR0_1588_INT_B));
 265 }
 266
 267 static void
 268 hns3_handle_mac_tnl(struct hns3_hw *hw)
 269 {
 270         struct hns3_cmd_desc desc;
 271         uint32_t status;
 272         int ret;
 273
 274         /* query and clear mac tnl interrupt */
 275         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 276         ret = hns3_cmd_send(hw, &desc, 1);
 277         if (ret) {
 278                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 279                 return;
 280         }
 281
 282         status = rte_le_to_cpu_32(desc.data[0]);
 283         if (status) {
 284                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 285                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 286                                           false);
 287                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 288                 ret = hns3_cmd_send(hw, &desc, 1);
 289                 if (ret)
 290                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 291                                  ret);
 292         }
 293 }
 294
 295 static void
 296 hns3_interrupt_handler(void *param)
 297 {
 298         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 299         struct hns3_adapter *hns = dev->data->dev_private;
 300         struct hns3_hw *hw = &hns->hw;
 301         enum hns3_evt_cause event_cause;
 302         uint32_t clearval = 0;
 303         uint32_t vector0_int;
 304         uint32_t ras_int;
 305         uint32_t cmdq_int;
 306
 307         /* Disable interrupt */
 308         hns3_pf_disable_irq0(hw);
 309
 310         event_cause = hns3_check_event_cause(hns, &clearval);
 311         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 312         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 313         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 314         hns3_clear_event_cause(hw, event_cause, clearval);
 315         /* vector 0 interrupt is shared with reset and mailbox source events. */
 316         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 317                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 318                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 319                           vector0_int, ras_int, cmdq_int);
 320                 hns3_handle_mac_tnl(hw);
 321                 hns3_handle_error(hns);
 322         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 323                 hns3_warn(hw, "received reset interrupt");
 324                 hns3_schedule_reset(hns);
 325         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 326                 hns3_dev_handle_mbx_msg(hw);
 327         } else {
 328                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 329                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 330                           vector0_int, ras_int, cmdq_int);
 331         }
 332
 333         /* Enable interrupt if it is not cause by reset */
 334         hns3_pf_enable_irq0(hw);
 335 }
 336
 337 static int
 338 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 339 {
 340 #define HNS3_VLAN_ID_OFFSET_STEP        160
 341 #define HNS3_VLAN_BYTE_SIZE             8
 342         struct hns3_vlan_filter_pf_cfg_cmd *req;
 343         struct hns3_hw *hw = &hns->hw;
 344         uint8_t vlan_offset_byte_val;
 345         struct hns3_cmd_desc desc;
 346         uint8_t vlan_offset_byte;
 347         uint8_t vlan_offset_base;
 348         int ret;
 349
 350         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 351
 352         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 353         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 354                            HNS3_VLAN_BYTE_SIZE;
 355         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 356
 357         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 358         req->vlan_offset = vlan_offset_base;
 359         req->vlan_cfg = on ? 0 : 1;
 360         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 361
 362         ret = hns3_cmd_send(hw, &desc, 1);
 363         if (ret)
 364                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 365                          vlan_id, ret);
 366
 367         return ret;
 368 }
 369
 370 static void
 371 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 372 {
 373         struct hns3_user_vlan_table *vlan_entry;
 374         struct hns3_pf *pf = &hns->pf;
 375
 376         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 377                 if (vlan_entry->vlan_id == vlan_id) {
 378                         if (vlan_entry->hd_tbl_status)
 379                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 380                         LIST_REMOVE(vlan_entry, next);
 381                         rte_free(vlan_entry);
 382                         break;
 383                 }
 384         }
 385 }
 386
 387 static void
 388 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 389                         bool writen_to_tbl)
 390 {
 391         struct hns3_user_vlan_table *vlan_entry;
 392         struct hns3_hw *hw = &hns->hw;
 393         struct hns3_pf *pf = &hns->pf;
 394
 395         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 396                 if (vlan_entry->vlan_id == vlan_id)
 397                         return;
 398         }
 399
 400         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 401         if (vlan_entry == NULL) {
 402                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 403                 return;
 404         }
 405
 406         vlan_entry->hd_tbl_status = writen_to_tbl;
 407         vlan_entry->vlan_id = vlan_id;
 408
 409         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 410 }
 411
 412 static int
 413 hns3_restore_vlan_table(struct hns3_adapter *hns)
 414 {
 415         struct hns3_user_vlan_table *vlan_entry;
 416         struct hns3_hw *hw = &hns->hw;
 417         struct hns3_pf *pf = &hns->pf;
 418         uint16_t vlan_id;
 419         int ret = 0;
 420
 421         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 422                 return hns3_vlan_pvid_configure(hns,
 423                                                 hw->port_base_vlan_cfg.pvid, 1);
 424
 425         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 426                 if (vlan_entry->hd_tbl_status) {
 427                         vlan_id = vlan_entry->vlan_id;
 428                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 429                         if (ret)
 430                                 break;
 431                 }
 432         }
 433
 434         return ret;
 435 }
 436
 437 static int
 438 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 439 {
 440         struct hns3_hw *hw = &hns->hw;
 441         bool writen_to_tbl = false;
 442         int ret = 0;
 443
 444         /*
 445          * When vlan filter is enabled, hardware regards packets without vlan
 446          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 447          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 448          */
 449         if (on == 0 && vlan_id == 0)
 450                 return 0;
 451
 452         /*
 453          * When port base vlan enabled, we use port base vlan as the vlan
 454          * filter condition. In this case, we don't update vlan filter table
 455          * when user add new vlan or remove exist vlan, just update the
 456          * vlan list. The vlan id in vlan list will be written in vlan filter
 457          * table until port base vlan disabled
 458          */
 459         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 460                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 461                 writen_to_tbl = true;
 462         }
 463
 464         if (ret == 0) {
 465                 if (on)
 466                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 467                 else
 468                         hns3_rm_dev_vlan_table(hns, vlan_id);
 469         }
 470         return ret;
 471 }
 472
 473 static int
 474 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 475 {
 476         struct hns3_adapter *hns = dev->data->dev_private;
 477         struct hns3_hw *hw = &hns->hw;
 478         int ret;
 479
 480         rte_spinlock_lock(&hw->lock);
 481         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 482         rte_spinlock_unlock(&hw->lock);
 483         return ret;
 484 }
 485
 486 static int
 487 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 488                          uint16_t tpid)
 489 {
 490         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 491         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 492         struct hns3_hw *hw = &hns->hw;
 493         struct hns3_cmd_desc desc;
 494         int ret;
 495
 496         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
 497              vlan_type != RTE_ETH_VLAN_TYPE_OUTER)) {
 498                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 499                 return -EINVAL;
 500         }
 501
 502         if (tpid != RTE_ETHER_TYPE_VLAN) {
 503                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 504                 return -EINVAL;
 505         }
 506
 507         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 508         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 509
 510         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
 511                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 512                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 513         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
 514                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 515                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 516                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 517                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 518         }
 519
 520         ret = hns3_cmd_send(hw, &desc, 1);
 521         if (ret) {
 522                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 523                          ret);
 524                 return ret;
 525         }
 526
 527         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 528
 529         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 530         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 531         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 532
 533         ret = hns3_cmd_send(hw, &desc, 1);
 534         if (ret)
 535                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 536                          ret);
 537         return ret;
 538 }
 539
 540 static int
 541 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 542                    uint16_t tpid)
 543 {
 544         struct hns3_adapter *hns = dev->data->dev_private;
 545         struct hns3_hw *hw = &hns->hw;
 546         int ret;
 547
 548         rte_spinlock_lock(&hw->lock);
 549         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 550         rte_spinlock_unlock(&hw->lock);
 551         return ret;
 552 }
 553
 554 static int
 555 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 556                              struct hns3_rx_vtag_cfg *vcfg)
 557 {
 558         struct hns3_vport_vtag_rx_cfg_cmd *req;
 559         struct hns3_hw *hw = &hns->hw;
 560         struct hns3_cmd_desc desc;
 561         uint16_t vport_id;
 562         uint8_t bitmap;
 563         int ret;
 564
 565         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 566
 567         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 568         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 569                      vcfg->strip_tag1_en ? 1 : 0);
 570         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 571                      vcfg->strip_tag2_en ? 1 : 0);
 572         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 573                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 574         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 575                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 576
 577         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 579                      vcfg->strip_tag1_discard_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 581                      vcfg->strip_tag2_discard_en ? 1 : 0);
 582         /*
 583          * In current version VF is not supported when PF is driven by DPDK
 584          * driver, just need to configure parameters for PF vport.
 585          */
 586         vport_id = HNS3_PF_FUNC_ID;
 587         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 588         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 589         req->vf_bitmap[req->vf_offset] = bitmap;
 590
 591         ret = hns3_cmd_send(hw, &desc, 1);
 592         if (ret)
 593                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 594         return ret;
 595 }
 596
 597 static void
 598 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 599                            struct hns3_rx_vtag_cfg *vcfg)
 600 {
 601         struct hns3_pf *pf = &hns->pf;
 602         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 603 }
 604
 605 static void
 606 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 607                            struct hns3_tx_vtag_cfg *vcfg)
 608 {
 609         struct hns3_pf *pf = &hns->pf;
 610         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 611 }
 612
 613 static int
 614 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 615 {
 616         struct hns3_rx_vtag_cfg rxvlan_cfg;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 621                 rxvlan_cfg.strip_tag1_en = false;
 622                 rxvlan_cfg.strip_tag2_en = enable;
 623                 rxvlan_cfg.strip_tag2_discard_en = false;
 624         } else {
 625                 rxvlan_cfg.strip_tag1_en = enable;
 626                 rxvlan_cfg.strip_tag2_en = true;
 627                 rxvlan_cfg.strip_tag2_discard_en = true;
 628         }
 629
 630         rxvlan_cfg.strip_tag1_discard_en = false;
 631         rxvlan_cfg.vlan1_vlan_prionly = false;
 632         rxvlan_cfg.vlan2_vlan_prionly = false;
 633         rxvlan_cfg.rx_vlan_offload_en = enable;
 634
 635         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 636         if (ret) {
 637                 hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
 638                                 enable ? "enable" : "disable", ret);
 639                 return ret;
 640         }
 641
 642         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 643
 644         return ret;
 645 }
 646
 647 static int
 648 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 649                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 650 {
 651         struct hns3_vlan_filter_ctrl_cmd *req;
 652         struct hns3_cmd_desc desc;
 653         int ret;
 654
 655         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 656
 657         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 658         req->vlan_type = vlan_type;
 659         req->vlan_fe = filter_en ? fe_type : 0;
 660         req->vf_id = vf_id;
 661
 662         ret = hns3_cmd_send(hw, &desc, 1);
 663         if (ret)
 664                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 665
 666         return ret;
 667 }
 668
 669 static int
 670 hns3_vlan_filter_init(struct hns3_adapter *hns)
 671 {
 672         struct hns3_hw *hw = &hns->hw;
 673         int ret;
 674
 675         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 676                                         HNS3_FILTER_FE_EGRESS, false,
 677                                         HNS3_PF_FUNC_ID);
 678         if (ret) {
 679                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 680                 return ret;
 681         }
 682
 683         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 684                                         HNS3_FILTER_FE_INGRESS, false,
 685                                         HNS3_PF_FUNC_ID);
 686         if (ret)
 687                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 688
 689         return ret;
 690 }
 691
 692 static int
 693 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 694 {
 695         struct hns3_hw *hw = &hns->hw;
 696         int ret;
 697
 698         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 699                                         HNS3_FILTER_FE_INGRESS, enable,
 700                                         HNS3_PF_FUNC_ID);
 701         if (ret)
 702                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 703                          enable ? "enable" : "disable", ret);
 704
 705         return ret;
 706 }
 707
 708 static int
 709 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 710 {
 711         struct hns3_adapter *hns = dev->data->dev_private;
 712         struct hns3_hw *hw = &hns->hw;
 713         struct rte_eth_rxmode *rxmode;
 714         unsigned int tmp_mask;
 715         bool enable;
 716         int ret = 0;
 717
 718         rte_spinlock_lock(&hw->lock);
 719         rxmode = &dev->data->dev_conf.rxmode;
 720         tmp_mask = (unsigned int)mask;
 721         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
 722                 /* ignore vlan filter configuration during promiscuous mode */
 723                 if (!dev->data->promiscuous) {
 724                         /* Enable or disable VLAN filter */
 725                         enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ?
 726                                  true : false;
 727
 728                         ret = hns3_enable_vlan_filter(hns, enable);
 729                         if (ret) {
 730                                 rte_spinlock_unlock(&hw->lock);
 731                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 732                                          enable ? "enable" : "disable", ret);
 733                                 return ret;
 734                         }
 735                 }
 736         }
 737
 738         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
 739                 /* Enable or disable VLAN stripping */
 740                 enable = rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ?
 741                     true : false;
 742
 743                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 744                 if (ret) {
 745                         rte_spinlock_unlock(&hw->lock);
 746                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 747                                  enable ? "enable" : "disable", ret);
 748                         return ret;
 749                 }
 750         }
 751
 752         rte_spinlock_unlock(&hw->lock);
 753
 754         return ret;
 755 }
 756
 757 static int
 758 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 759                              struct hns3_tx_vtag_cfg *vcfg)
 760 {
 761         struct hns3_vport_vtag_tx_cfg_cmd *req;
 762         struct hns3_cmd_desc desc;
 763         struct hns3_hw *hw = &hns->hw;
 764         uint16_t vport_id;
 765         uint8_t bitmap;
 766         int ret;
 767
 768         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 769
 770         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 771         req->def_vlan_tag1 = vcfg->default_tag1;
 772         req->def_vlan_tag2 = vcfg->default_tag2;
 773         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 774                      vcfg->accept_tag1 ? 1 : 0);
 775         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 776                      vcfg->accept_untag1 ? 1 : 0);
 777         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 778                      vcfg->accept_tag2 ? 1 : 0);
 779         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 780                      vcfg->accept_untag2 ? 1 : 0);
 781         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 782                      vcfg->insert_tag1_en ? 1 : 0);
 783         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 784                      vcfg->insert_tag2_en ? 1 : 0);
 785         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 786
 787         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 789                      vcfg->tag_shift_mode_en ? 1 : 0);
 790
 791         /*
 792          * In current version VF is not supported when PF is driven by DPDK
 793          * driver, just need to configure parameters for PF vport.
 794          */
 795         vport_id = HNS3_PF_FUNC_ID;
 796         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 797         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 798         req->vf_bitmap[req->vf_offset] = bitmap;
 799
 800         ret = hns3_cmd_send(hw, &desc, 1);
 801         if (ret)
 802                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 803
 804         return ret;
 805 }
 806
 807 static int
 808 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 809                      uint16_t pvid)
 810 {
 811         struct hns3_hw *hw = &hns->hw;
 812         struct hns3_tx_vtag_cfg txvlan_cfg;
 813         int ret;
 814
 815         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 816                 txvlan_cfg.accept_tag1 = true;
 817                 txvlan_cfg.insert_tag1_en = false;
 818                 txvlan_cfg.default_tag1 = 0;
 819         } else {
 820                 txvlan_cfg.accept_tag1 =
 821                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 822                 txvlan_cfg.insert_tag1_en = true;
 823                 txvlan_cfg.default_tag1 = pvid;
 824         }
 825
 826         txvlan_cfg.accept_untag1 = true;
 827         txvlan_cfg.accept_tag2 = true;
 828         txvlan_cfg.accept_untag2 = true;
 829         txvlan_cfg.insert_tag2_en = false;
 830         txvlan_cfg.default_tag2 = 0;
 831         txvlan_cfg.tag_shift_mode_en = true;
 832
 833         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 834         if (ret) {
 835                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 836                          ret);
 837                 return ret;
 838         }
 839
 840         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 841         return ret;
 842 }
 843
 844
 845 static void
 846 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 847 {
 848         struct hns3_user_vlan_table *vlan_entry;
 849         struct hns3_pf *pf = &hns->pf;
 850
 851         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 852                 if (vlan_entry->hd_tbl_status) {
 853                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 854                         vlan_entry->hd_tbl_status = false;
 855                 }
 856         }
 857
 858         if (is_del_list) {
 859                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 860                 while (vlan_entry) {
 861                         LIST_REMOVE(vlan_entry, next);
 862                         rte_free(vlan_entry);
 863                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 864                 }
 865         }
 866 }
 867
 868 static void
 869 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 870 {
 871         struct hns3_user_vlan_table *vlan_entry;
 872         struct hns3_pf *pf = &hns->pf;
 873
 874         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 875                 if (!vlan_entry->hd_tbl_status) {
 876                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 877                         vlan_entry->hd_tbl_status = true;
 878                 }
 879         }
 880 }
 881
 882 static void
 883 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 884 {
 885         struct hns3_hw *hw = &hns->hw;
 886         int ret;
 887
 888         hns3_rm_all_vlan_table(hns, true);
 889         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 890                 ret = hns3_set_port_vlan_filter(hns,
 891                                                 hw->port_base_vlan_cfg.pvid, 0);
 892                 if (ret) {
 893                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 894                                  ret);
 895                         return;
 896                 }
 897         }
 898 }
 899
 900 static int
 901 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 902                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 903 {
 904         struct hns3_hw *hw = &hns->hw;
 905         uint16_t old_pvid;
 906         int ret;
 907
 908         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 909                 old_pvid = hw->port_base_vlan_cfg.pvid;
 910                 if (old_pvid != HNS3_INVALID_PVID) {
 911                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 912                         if (ret) {
 913                                 hns3_err(hw, "failed to remove old pvid %u, "
 914                                                 "ret = %d", old_pvid, ret);
 915                                 return ret;
 916                         }
 917                 }
 918
 919                 hns3_rm_all_vlan_table(hns, false);
 920                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 921                 if (ret) {
 922                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 923                                         new_pvid, ret);
 924                         return ret;
 925                 }
 926         } else {
 927                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 928                 if (ret) {
 929                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 930                                         new_pvid, ret);
 931                         return ret;
 932                 }
 933
 934                 hns3_add_all_vlan_table(hns);
 935         }
 936         return 0;
 937 }
 938
 939 static int
 940 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 941 {
 942         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 943         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 944         bool rx_strip_en;
 945         int ret;
 946
 947         rx_strip_en = old_cfg->rx_vlan_offload_en;
 948         if (on) {
 949                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 950                 rx_vlan_cfg.strip_tag2_en = true;
 951                 rx_vlan_cfg.strip_tag2_discard_en = true;
 952         } else {
 953                 rx_vlan_cfg.strip_tag1_en = false;
 954                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 955                 rx_vlan_cfg.strip_tag2_discard_en = false;
 956         }
 957         rx_vlan_cfg.strip_tag1_discard_en = false;
 958         rx_vlan_cfg.vlan1_vlan_prionly = false;
 959         rx_vlan_cfg.vlan2_vlan_prionly = false;
 960         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 963         if (ret)
 964                 return ret;
 965
 966         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 967         return ret;
 968 }
 969
 970 static int
 971 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 972 {
 973         struct hns3_hw *hw = &hns->hw;
 974         uint16_t port_base_vlan_state;
 975         int ret, err;
 976
 977         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 978                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 979                         hns3_warn(hw, "Invalid operation! As current pvid set "
 980                                   "is %u, disable pvid %u is invalid",
 981                                   hw->port_base_vlan_cfg.pvid, pvid);
 982                 return 0;
 983         }
 984
 985         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 986                                     HNS3_PORT_BASE_VLAN_DISABLE;
 987         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 988         if (ret) {
 989                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 990                          ret);
 991                 return ret;
 992         }
 993
 994         ret = hns3_en_pvid_strip(hns, on);
 995         if (ret) {
 996                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 997                          "ret = %d", ret);
 998                 goto pvid_vlan_strip_fail;
 999         }
1000
1001         if (pvid == HNS3_INVALID_PVID)
1002                 goto out;
1003         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1004         if (ret) {
1005                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1006                          ret);
1007                 goto vlan_filter_set_fail;
1008         }
1009
1010 out:
1011         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1012         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1013         return ret;
1014
1015 vlan_filter_set_fail:
1016         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1017                                         HNS3_PORT_BASE_VLAN_ENABLE);
1018         if (err)
1019                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1020
1021 pvid_vlan_strip_fail:
1022         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1023                                         hw->port_base_vlan_cfg.pvid);
1024         if (err)
1025                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1026
1027         return ret;
1028 }
1029
1030 static int
1031 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1032 {
1033         struct hns3_adapter *hns = dev->data->dev_private;
1034         struct hns3_hw *hw = &hns->hw;
1035         bool pvid_en_state_change;
1036         uint16_t pvid_state;
1037         int ret;
1038
1039         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1040                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1041                          RTE_ETHER_MAX_VLAN_ID);
1042                 return -EINVAL;
1043         }
1044
1045         /*
1046          * If PVID configuration state change, should refresh the PVID
1047          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1048          */
1049         pvid_state = hw->port_base_vlan_cfg.state;
1050         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1051             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1052                 pvid_en_state_change = false;
1053         else
1054                 pvid_en_state_change = true;
1055
1056         rte_spinlock_lock(&hw->lock);
1057         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1058         rte_spinlock_unlock(&hw->lock);
1059         if (ret)
1060                 return ret;
1061         /*
1062          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1063          * need be processed by PMD.
1064          */
1065         if (pvid_en_state_change &&
1066             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1067                 hns3_update_all_queues_pvid_proc_en(hw);
1068
1069         return 0;
1070 }
1071
1072 static int
1073 hns3_default_vlan_config(struct hns3_adapter *hns)
1074 {
1075         struct hns3_hw *hw = &hns->hw;
1076         int ret;
1077
1078         /*
1079          * When vlan filter is enabled, hardware regards packets without vlan
1080          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1081          * table, packets without vlan won't be received. So, add vlan 0 as
1082          * the default vlan.
1083          */
1084         ret = hns3_vlan_filter_configure(hns, 0, 1);
1085         if (ret)
1086                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1087         return ret;
1088 }
1089
1090 static int
1091 hns3_init_vlan_config(struct hns3_adapter *hns)
1092 {
1093         struct hns3_hw *hw = &hns->hw;
1094         int ret;
1095
1096         /*
1097          * This function can be called in the initialization and reset process,
1098          * when in reset process, it means that hardware had been reseted
1099          * successfully and we need to restore the hardware configuration to
1100          * ensure that the hardware configuration remains unchanged before and
1101          * after reset.
1102          */
1103         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1104                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1105                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1106         }
1107
1108         ret = hns3_vlan_filter_init(hns);
1109         if (ret) {
1110                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1111                 return ret;
1112         }
1113
1114         ret = hns3_vlan_tpid_configure(hns, RTE_ETH_VLAN_TYPE_INNER,
1115                                        RTE_ETHER_TYPE_VLAN);
1116         if (ret) {
1117                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1118                 return ret;
1119         }
1120
1121         /*
1122          * When in the reinit dev stage of the reset process, the following
1123          * vlan-related configurations may differ from those at initialization,
1124          * we will restore configurations to hardware in hns3_restore_vlan_table
1125          * and hns3_restore_vlan_conf later.
1126          */
1127         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1128                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1129                 if (ret) {
1130                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1131                         return ret;
1132                 }
1133
1134                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1135                 if (ret) {
1136                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1137                                  ret);
1138                         return ret;
1139                 }
1140         }
1141
1142         return hns3_default_vlan_config(hns);
1143 }
1144
1145 static int
1146 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1147 {
1148         struct hns3_pf *pf = &hns->pf;
1149         struct hns3_hw *hw = &hns->hw;
1150         uint64_t offloads;
1151         bool enable;
1152         int ret;
1153
1154         if (!hw->data->promiscuous) {
1155                 /* restore vlan filter states */
1156                 offloads = hw->data->dev_conf.rxmode.offloads;
1157                 enable = offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER ? true : false;
1158                 ret = hns3_enable_vlan_filter(hns, enable);
1159                 if (ret) {
1160                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1161                                  "ret = %d", ret);
1162                         return ret;
1163                 }
1164         }
1165
1166         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1167         if (ret) {
1168                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1169                 return ret;
1170         }
1171
1172         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1173         if (ret)
1174                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1175
1176         return ret;
1177 }
1178
1179 static int
1180 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1181 {
1182         struct hns3_adapter *hns = dev->data->dev_private;
1183         struct rte_eth_dev_data *data = dev->data;
1184         struct rte_eth_txmode *txmode;
1185         struct hns3_hw *hw = &hns->hw;
1186         int mask;
1187         int ret;
1188
1189         txmode = &data->dev_conf.txmode;
1190         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1191                 hns3_warn(hw,
1192                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1193                           "configuration is not supported! Ignore these two "
1194                           "parameters: hw_vlan_reject_tagged(%u), "
1195                           "hw_vlan_reject_untagged(%u)",
1196                           txmode->hw_vlan_reject_tagged,
1197                           txmode->hw_vlan_reject_untagged);
1198
1199         /* Apply vlan offload setting */
1200         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;
1201         ret = hns3_vlan_offload_set(dev, mask);
1202         if (ret) {
1203                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1204                          ret);
1205                 return ret;
1206         }
1207
1208         /*
1209          * If pvid config is not set in rte_eth_conf, driver needn't to set
1210          * VLAN pvid related configuration to hardware.
1211          */
1212         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1213                 return 0;
1214
1215         /* Apply pvid setting */
1216         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1217                                  txmode->hw_vlan_insert_pvid);
1218         if (ret)
1219                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1220                          txmode->pvid, ret);
1221
1222         return ret;
1223 }
1224
1225 static int
1226 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1227                 unsigned int tso_mss_max)
1228 {
1229         struct hns3_cfg_tso_status_cmd *req;
1230         struct hns3_cmd_desc desc;
1231         uint16_t tso_mss;
1232
1233         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1234
1235         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1236
1237         tso_mss = 0;
1238         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1239                        tso_mss_min);
1240         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1241
1242         tso_mss = 0;
1243         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1244                        tso_mss_max);
1245         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1246
1247         return hns3_cmd_send(hw, &desc, 1);
1248 }
1249
1250 static int
1251 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1252                    uint16_t *allocated_size, bool is_alloc)
1253 {
1254         struct hns3_umv_spc_alc_cmd *req;
1255         struct hns3_cmd_desc desc;
1256         int ret;
1257
1258         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1259         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1260         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1261         req->space_size = rte_cpu_to_le_32(space_size);
1262
1263         ret = hns3_cmd_send(hw, &desc, 1);
1264         if (ret) {
1265                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1266                              is_alloc ? "allocate" : "free", ret);
1267                 return ret;
1268         }
1269
1270         if (is_alloc && allocated_size)
1271                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1272
1273         return 0;
1274 }
1275
1276 static int
1277 hns3_init_umv_space(struct hns3_hw *hw)
1278 {
1279         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1280         struct hns3_pf *pf = &hns->pf;
1281         uint16_t allocated_size = 0;
1282         int ret;
1283
1284         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1285                                  true);
1286         if (ret)
1287                 return ret;
1288
1289         if (allocated_size < pf->wanted_umv_size)
1290                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1291                              pf->wanted_umv_size, allocated_size);
1292
1293         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1294                                                 pf->wanted_umv_size;
1295         pf->used_umv_size = 0;
1296         return 0;
1297 }
1298
1299 static int
1300 hns3_uninit_umv_space(struct hns3_hw *hw)
1301 {
1302         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1303         struct hns3_pf *pf = &hns->pf;
1304         int ret;
1305
1306         if (pf->max_umv_size == 0)
1307                 return 0;
1308
1309         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1310         if (ret)
1311                 return ret;
1312
1313         pf->max_umv_size = 0;
1314
1315         return 0;
1316 }
1317
1318 static bool
1319 hns3_is_umv_space_full(struct hns3_hw *hw)
1320 {
1321         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1322         struct hns3_pf *pf = &hns->pf;
1323         bool is_full;
1324
1325         is_full = (pf->used_umv_size >= pf->max_umv_size);
1326
1327         return is_full;
1328 }
1329
1330 static void
1331 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1332 {
1333         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1334         struct hns3_pf *pf = &hns->pf;
1335
1336         if (is_free) {
1337                 if (pf->used_umv_size > 0)
1338                         pf->used_umv_size--;
1339         } else
1340                 pf->used_umv_size++;
1341 }
1342
1343 static void
1344 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1345                       const uint8_t *addr, bool is_mc)
1346 {
1347         const unsigned char *mac_addr = addr;
1348         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1349                             ((uint32_t)mac_addr[2] << 16) |
1350                             ((uint32_t)mac_addr[1] << 8) |
1351                             (uint32_t)mac_addr[0];
1352         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1353
1354         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1355         if (is_mc) {
1356                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1357                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1358                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1359         }
1360
1361         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1362         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1363 }
1364
1365 static int
1366 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1367                              uint8_t resp_code,
1368                              enum hns3_mac_vlan_tbl_opcode op)
1369 {
1370         if (cmdq_resp) {
1371                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1372                          cmdq_resp);
1373                 return -EIO;
1374         }
1375
1376         if (op == HNS3_MAC_VLAN_ADD) {
1377                 if (resp_code == 0 || resp_code == 1) {
1378                         return 0;
1379                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1380                         hns3_err(hw, "add mac addr failed for uc_overflow");
1381                         return -ENOSPC;
1382                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1383                         hns3_err(hw, "add mac addr failed for mc_overflow");
1384                         return -ENOSPC;
1385                 }
1386
1387                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1388                          resp_code);
1389                 return -EIO;
1390         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1391                 if (resp_code == 0) {
1392                         return 0;
1393                 } else if (resp_code == 1) {
1394                         hns3_dbg(hw, "remove mac addr failed for miss");
1395                         return -ENOENT;
1396                 }
1397
1398                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1399                          resp_code);
1400                 return -EIO;
1401         } else if (op == HNS3_MAC_VLAN_LKUP) {
1402                 if (resp_code == 0) {
1403                         return 0;
1404                 } else if (resp_code == 1) {
1405                         hns3_dbg(hw, "lookup mac addr failed for miss");
1406                         return -ENOENT;
1407                 }
1408
1409                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1410                          resp_code);
1411                 return -EIO;
1412         }
1413
1414         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1415                  op);
1416
1417         return -EINVAL;
1418 }
1419
1420 static int
1421 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1422                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1423                          struct hns3_cmd_desc *desc, uint8_t desc_num)
1424 {
1425         uint8_t resp_code;
1426         uint16_t retval;
1427         int ret;
1428         int i;
1429
1430         if (desc_num == HNS3_MC_MAC_VLAN_OPS_DESC_NUM) {
1431                 for (i = 0; i < desc_num - 1; i++) {
1432                         hns3_cmd_setup_basic_desc(&desc[i],
1433                                                   HNS3_OPC_MAC_VLAN_ADD, true);
1434                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1435                         if (i == 0)
1436                                 memcpy(desc[i].data, req,
1437                                 sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1438                 }
1439                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_MAC_VLAN_ADD,
1440                                           true);
1441         } else {
1442                 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD,
1443                                           true);
1444                 memcpy(desc[0].data, req,
1445                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1446         }
1447         ret = hns3_cmd_send(hw, desc, desc_num);
1448         if (ret) {
1449                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1450                          ret);
1451                 return ret;
1452         }
1453         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1454         retval = rte_le_to_cpu_16(desc[0].retval);
1455
1456         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1457                                             HNS3_MAC_VLAN_LKUP);
1458 }
1459
1460 static int
1461 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1462                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1463                       struct hns3_cmd_desc *desc, uint8_t desc_num)
1464 {
1465         uint8_t resp_code;
1466         uint16_t retval;
1467         int cfg_status;
1468         int ret;
1469         int i;
1470
1471         if (desc_num == HNS3_UC_MAC_VLAN_OPS_DESC_NUM) {
1472                 hns3_cmd_setup_basic_desc(desc, HNS3_OPC_MAC_VLAN_ADD, false);
1473                 memcpy(desc->data, req,
1474                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1475                 ret = hns3_cmd_send(hw, desc, desc_num);
1476                 resp_code = (rte_le_to_cpu_32(desc->data[0]) >> 8) & 0xff;
1477                 retval = rte_le_to_cpu_16(desc->retval);
1478
1479                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1480                                                           HNS3_MAC_VLAN_ADD);
1481         } else {
1482                 for (i = 0; i < desc_num; i++) {
1483                         hns3_cmd_reuse_desc(&desc[i], false);
1484                         if (i == desc_num - 1)
1485                                 desc[i].flag &=
1486                                         rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1487                         else
1488                                 desc[i].flag |=
1489                                         rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490                 }
1491                 memcpy(desc[0].data, req,
1492                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1493                 desc[0].retval = 0;
1494                 ret = hns3_cmd_send(hw, desc, desc_num);
1495                 resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1496                 retval = rte_le_to_cpu_16(desc[0].retval);
1497
1498                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1499                                                           HNS3_MAC_VLAN_ADD);
1500         }
1501
1502         if (ret) {
1503                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1504                 return ret;
1505         }
1506
1507         return cfg_status;
1508 }
1509
1510 static int
1511 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1512                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1513 {
1514         struct hns3_cmd_desc desc;
1515         uint8_t resp_code;
1516         uint16_t retval;
1517         int ret;
1518
1519         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1520
1521         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1522
1523         ret = hns3_cmd_send(hw, &desc, 1);
1524         if (ret) {
1525                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1526                 return ret;
1527         }
1528         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1529         retval = rte_le_to_cpu_16(desc.retval);
1530
1531         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1532                                             HNS3_MAC_VLAN_REMOVE);
1533 }
1534
1535 static int
1536 hns3_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1537 {
1538         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1539         struct hns3_mac_vlan_tbl_entry_cmd req;
1540         struct hns3_pf *pf = &hns->pf;
1541         struct hns3_cmd_desc desc;
1542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1543         uint16_t egress_port = 0;
1544         uint8_t vf_id;
1545         int ret;
1546
1547         /* check if mac addr is valid */
1548         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1549                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1550                                       mac_addr);
1551                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1552                          mac_str);
1553                 return -EINVAL;
1554         }
1555
1556         memset(&req, 0, sizeof(req));
1557
1558         /*
1559          * In current version VF is not supported when PF is driven by DPDK
1560          * driver, just need to configure parameters for PF vport.
1561          */
1562         vf_id = HNS3_PF_FUNC_ID;
1563         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1564                        HNS3_MAC_EPORT_VFID_S, vf_id);
1565
1566         req.egress_port = rte_cpu_to_le_16(egress_port);
1567
1568         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1569
1570         /*
1571          * Lookup the mac address in the mac_vlan table, and add
1572          * it if the entry is inexistent. Repeated unicast entry
1573          * is not allowed in the mac vlan table.
1574          */
1575         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc,
1576                                         HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1577         if (ret == -ENOENT) {
1578                 if (!hns3_is_umv_space_full(hw)) {
1579                         ret = hns3_add_mac_vlan_tbl(hw, &req, &desc,
1580                                                 HNS3_UC_MAC_VLAN_OPS_DESC_NUM);
1581                         if (!ret)
1582                                 hns3_update_umv_space(hw, false);
1583                         return ret;
1584                 }
1585
1586                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1587
1588                 return -ENOSPC;
1589         }
1590
1591         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1592
1593         /* check if we just hit the duplicate */
1594         if (ret == 0) {
1595                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1596                 return 0;
1597         }
1598
1599         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1600                  mac_str);
1601
1602         return ret;
1603 }
1604
1605 static int
1606 hns3_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1607 {
1608         struct hns3_mac_vlan_tbl_entry_cmd req;
1609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610         int ret;
1611
1612         /* check if mac addr is valid */
1613         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1614                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1615                                       mac_addr);
1616                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1617                          mac_str);
1618                 return -EINVAL;
1619         }
1620
1621         memset(&req, 0, sizeof(req));
1622         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1623         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1624         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1625         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1626                 return 0;
1627         else if (ret == 0)
1628                 hns3_update_umv_space(hw, true);
1629
1630         return ret;
1631 }
1632
1633 static int
1634 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1635                           struct rte_ether_addr *mac_addr)
1636 {
1637         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         struct rte_ether_addr *oaddr;
1639         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1640         int ret, ret_val;
1641
1642         rte_spinlock_lock(&hw->lock);
1643         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1644         ret = hw->ops.del_uc_mac_addr(hw, oaddr);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       oaddr);
1648                 hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1649                           mac_str, ret);
1650
1651                 rte_spinlock_unlock(&hw->lock);
1652                 return ret;
1653         }
1654
1655         ret = hw->ops.add_uc_mac_addr(hw, mac_addr);
1656         if (ret) {
1657                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1658                                       mac_addr);
1659                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1660                 goto err_add_uc_addr;
1661         }
1662
1663         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1664         if (ret) {
1665                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1666                 goto err_pause_addr_cfg;
1667         }
1668
1669         rte_ether_addr_copy(mac_addr,
1670                             (struct rte_ether_addr *)hw->mac.mac_addr);
1671         rte_spinlock_unlock(&hw->lock);
1672
1673         return 0;
1674
1675 err_pause_addr_cfg:
1676         ret_val = hw->ops.del_uc_mac_addr(hw, mac_addr);
1677         if (ret_val) {
1678                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679                                       mac_addr);
1680                 hns3_warn(hw,
1681                           "Failed to roll back to del setted mac addr(%s): %d",
1682                           mac_str, ret_val);
1683         }
1684
1685 err_add_uc_addr:
1686         ret_val = hw->ops.add_uc_mac_addr(hw, oaddr);
1687         if (ret_val) {
1688                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, oaddr);
1689                 hns3_warn(hw, "Failed to restore old uc mac addr(%s): %d",
1690                                   mac_str, ret_val);
1691         }
1692         rte_spinlock_unlock(&hw->lock);
1693
1694         return ret;
1695 }
1696
1697 static void
1698 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1699 {
1700 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1701         uint8_t word_num;
1702         uint8_t bit_num;
1703
1704         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1705                 word_num = vfid / 32;
1706                 bit_num = vfid % 32;
1707                 if (clr)
1708                         desc[1].data[word_num] &=
1709                             rte_cpu_to_le_32(~(1UL << bit_num));
1710                 else
1711                         desc[1].data[word_num] |=
1712                             rte_cpu_to_le_32(1UL << bit_num);
1713         } else {
1714                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1715                 bit_num = vfid % 32;
1716                 if (clr)
1717                         desc[2].data[word_num] &=
1718                             rte_cpu_to_le_32(~(1UL << bit_num));
1719                 else
1720                         desc[2].data[word_num] |=
1721                             rte_cpu_to_le_32(1UL << bit_num);
1722         }
1723 }
1724
1725 static int
1726 hns3_add_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1727 {
1728         struct hns3_cmd_desc desc[HNS3_MC_MAC_VLAN_OPS_DESC_NUM];
1729         struct hns3_mac_vlan_tbl_entry_cmd req;
1730         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1731         uint8_t vf_id;
1732         int ret;
1733
1734         /* Check if mac addr is valid */
1735         if (!rte_is_multicast_ether_addr(mac_addr)) {
1736                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1737                                       mac_addr);
1738                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1739                          mac_str);
1740                 return -EINVAL;
1741         }
1742
1743         memset(&req, 0, sizeof(req));
1744         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1745         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1746         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1747                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1748         if (ret) {
1749                 /* This mac addr do not exist, add new entry for it */
1750                 memset(desc[0].data, 0, sizeof(desc[0].data));
1751                 memset(desc[1].data, 0, sizeof(desc[0].data));
1752                 memset(desc[2].data, 0, sizeof(desc[0].data));
1753         }
1754
1755         /*
1756          * In current version VF is not supported when PF is driven by DPDK
1757          * driver, just need to configure parameters for PF vport.
1758          */
1759         vf_id = HNS3_PF_FUNC_ID;
1760         hns3_update_desc_vfid(desc, vf_id, false);
1761         ret = hns3_add_mac_vlan_tbl(hw, &req, desc,
1762                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1763         if (ret) {
1764                 if (ret == -ENOSPC)
1765                         hns3_err(hw, "mc mac vlan table is full");
1766                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1767                                       mac_addr);
1768                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1769         }
1770
1771         return ret;
1772 }
1773
1774 static int
1775 hns3_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1776 {
1777         struct hns3_mac_vlan_tbl_entry_cmd req;
1778         struct hns3_cmd_desc desc[3];
1779         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1780         uint8_t vf_id;
1781         int ret;
1782
1783         /* Check if mac addr is valid */
1784         if (!rte_is_multicast_ether_addr(mac_addr)) {
1785                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1786                                       mac_addr);
1787                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1788                          mac_str);
1789                 return -EINVAL;
1790         }
1791
1792         memset(&req, 0, sizeof(req));
1793         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1794         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1795         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc,
1796                                         HNS3_MC_MAC_VLAN_OPS_DESC_NUM);
1797         if (ret == 0) {
1798                 /*
1799                  * This mac addr exist, remove this handle's VFID for it.
1800                  * In current version VF is not supported when PF is driven by
1801                  * DPDK driver, just need to configure parameters for PF vport.
1802                  */
1803                 vf_id = HNS3_PF_FUNC_ID;
1804                 hns3_update_desc_vfid(desc, vf_id, true);
1805
1806                 /* All the vfid is zero, so need to delete this entry */
1807                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1808         } else if (ret == -ENOENT) {
1809                 /* This mac addr doesn't exist. */
1810                 return 0;
1811         }
1812
1813         if (ret) {
1814                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                       mac_addr);
1816                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1817         }
1818
1819         return ret;
1820 }
1821
1822 static int
1823 hns3_check_mq_mode(struct rte_eth_dev *dev)
1824 {
1825         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1826         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1827         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1829         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1830         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1831         uint8_t num_tc;
1832         int max_tc = 0;
1833         int i;
1834
1835         if (((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) ||
1836             (tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB ||
1837              tx_mq_mode == RTE_ETH_MQ_TX_VMDQ_ONLY)) {
1838                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
1839                          rx_mq_mode, tx_mq_mode);
1840                 return -EOPNOTSUPP;
1841         }
1842
1843         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1844         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1845         if ((uint32_t)rx_mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1846                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1847                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1848                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1849                         return -EINVAL;
1850                 }
1851
1852                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1853                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1854                         hns3_err(hw, "on RTE_ETH_MQ_RX_DCB_RSS mode, "
1855                                  "nb_tcs(%d) != %d or %d in rx direction.",
1856                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1857                         return -EINVAL;
1858                 }
1859
1860                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1861                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1862                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1863                         return -EINVAL;
1864                 }
1865
1866                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1867                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1868                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
1869                                          "is not equal to one in tx direction.",
1870                                          i, dcb_rx_conf->dcb_tc[i]);
1871                                 return -EINVAL;
1872                         }
1873                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1874                                 max_tc = dcb_rx_conf->dcb_tc[i];
1875                 }
1876
1877                 num_tc = max_tc + 1;
1878                 if (num_tc > dcb_rx_conf->nb_tcs) {
1879                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1880                                  num_tc, dcb_rx_conf->nb_tcs);
1881                         return -EINVAL;
1882                 }
1883         }
1884
1885         return 0;
1886 }
1887
1888 static int
1889 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
1890                            enum hns3_ring_type queue_type, uint16_t queue_id)
1891 {
1892         struct hns3_cmd_desc desc;
1893         struct hns3_ctrl_vector_chain_cmd *req =
1894                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
1895         enum hns3_opcode_type op;
1896         uint16_t tqp_type_and_id = 0;
1897         uint16_t type;
1898         uint16_t gl;
1899         int ret;
1900
1901         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
1902         hns3_cmd_setup_basic_desc(&desc, op, false);
1903         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
1904                                               HNS3_TQP_INT_ID_L_S);
1905         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
1906                                               HNS3_TQP_INT_ID_H_S);
1907
1908         if (queue_type == HNS3_RING_TYPE_RX)
1909                 gl = HNS3_RING_GL_RX;
1910         else
1911                 gl = HNS3_RING_GL_TX;
1912
1913         type = queue_type;
1914
1915         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
1916                        type);
1917         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
1918         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
1919                        gl);
1920         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
1921         req->int_cause_num = 1;
1922         ret = hns3_cmd_send(hw, &desc, 1);
1923         if (ret) {
1924                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
1925                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
1926                 return ret;
1927         }
1928
1929         return 0;
1930 }
1931
1932 static int
1933 hns3_setup_dcb(struct rte_eth_dev *dev)
1934 {
1935         struct hns3_adapter *hns = dev->data->dev_private;
1936         struct hns3_hw *hw = &hns->hw;
1937         int ret;
1938
1939         if (!hns3_dev_get_support(hw, DCB)) {
1940                 hns3_err(hw, "this port does not support dcb configurations.");
1941                 return -EOPNOTSUPP;
1942         }
1943
1944         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
1945                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
1946                 return -EOPNOTSUPP;
1947         }
1948
1949         ret = hns3_dcb_configure(hns);
1950         if (ret)
1951                 hns3_err(hw, "failed to config dcb: %d", ret);
1952
1953         return ret;
1954 }
1955
1956 static int
1957 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
1958 {
1959         int ret;
1960
1961         /*
1962          * Some hardware doesn't support auto-negotiation, but users may not
1963          * configure link_speeds (default 0), which means auto-negotiation.
1964          * In this case, it should return success.
1965          */
1966         if (link_speeds == RTE_ETH_LINK_SPEED_AUTONEG &&
1967             hw->mac.support_autoneg == 0)
1968                 return 0;
1969
1970         if (link_speeds != RTE_ETH_LINK_SPEED_AUTONEG) {
1971                 ret = hns3_check_port_speed(hw, link_speeds);
1972                 if (ret)
1973                         return ret;
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int
1980 hns3_check_dev_conf(struct rte_eth_dev *dev)
1981 {
1982         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         struct rte_eth_conf *conf = &dev->data->dev_conf;
1984         int ret;
1985
1986         ret = hns3_check_mq_mode(dev);
1987         if (ret)
1988                 return ret;
1989
1990         return hns3_check_link_speed(hw, conf->link_speeds);
1991 }
1992
1993 static int
1994 hns3_dev_configure(struct rte_eth_dev *dev)
1995 {
1996         struct hns3_adapter *hns = dev->data->dev_private;
1997         struct rte_eth_conf *conf = &dev->data->dev_conf;
1998         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
1999         struct hns3_hw *hw = &hns->hw;
2000         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2001         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2002         struct rte_eth_rss_conf rss_conf;
2003         bool gro_en;
2004         int ret;
2005
2006         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2007
2008         /*
2009          * Some versions of hardware network engine does not support
2010          * individually enable/disable/reset the Tx or Rx queue. These devices
2011          * must enable/disable/reset Tx and Rx queues at the same time. When the
2012          * numbers of Tx queues allocated by upper applications are not equal to
2013          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2014          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2015          * work as usual. But these fake queues are imperceptible, and can not
2016          * be used by upper applications.
2017          */
2018         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2019         if (ret) {
2020                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
2021                 hw->cfg_max_queues = 0;
2022                 return ret;
2023         }
2024
2025         hw->adapter_state = HNS3_NIC_CONFIGURING;
2026         ret = hns3_check_dev_conf(dev);
2027         if (ret)
2028                 goto cfg_err;
2029
2030         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
2031                 ret = hns3_setup_dcb(dev);
2032                 if (ret)
2033                         goto cfg_err;
2034         }
2035
2036         /* When RSS is not configured, redirect the packet queue 0 */
2037         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2038                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2039                 rss_conf = conf->rx_adv_conf.rss_conf;
2040                 hw->rss_dis_flag = false;
2041                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2042                 if (ret)
2043                         goto cfg_err;
2044         }
2045
2046         ret = hns3_dev_mtu_set(dev, conf->rxmode.mtu);
2047         if (ret != 0)
2048                 goto cfg_err;
2049
2050         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2051         if (ret)
2052                 goto cfg_err;
2053
2054         ret = hns3_dev_configure_vlan(dev);
2055         if (ret)
2056                 goto cfg_err;
2057
2058         /* config hardware GRO */
2059         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
2060         ret = hns3_config_gro(hw, gro_en);
2061         if (ret)
2062                 goto cfg_err;
2063
2064         hns3_init_rx_ptype_tble(dev);
2065         hw->adapter_state = HNS3_NIC_CONFIGURED;
2066
2067         return 0;
2068
2069 cfg_err:
2070         hw->cfg_max_queues = 0;
2071         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2072         hw->adapter_state = HNS3_NIC_INITIALIZED;
2073
2074         return ret;
2075 }
2076
2077 static int
2078 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2079 {
2080         struct hns3_config_max_frm_size_cmd *req;
2081         struct hns3_cmd_desc desc;
2082
2083         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2084
2085         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2086         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2087         req->min_frm_size = RTE_ETHER_MIN_LEN;
2088
2089         return hns3_cmd_send(hw, &desc, 1);
2090 }
2091
2092 static int
2093 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2094 {
2095         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2096         uint16_t original_mps = hns->pf.mps;
2097         int err;
2098         int ret;
2099
2100         ret = hns3_set_mac_mtu(hw, mps);
2101         if (ret) {
2102                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2103                 return ret;
2104         }
2105
2106         hns->pf.mps = mps;
2107         ret = hns3_buffer_alloc(hw);
2108         if (ret) {
2109                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2110                 goto rollback;
2111         }
2112
2113         return 0;
2114
2115 rollback:
2116         err = hns3_set_mac_mtu(hw, original_mps);
2117         if (err) {
2118                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2119                 return ret;
2120         }
2121         hns->pf.mps = original_mps;
2122
2123         return ret;
2124 }
2125
2126 static int
2127 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2128 {
2129         struct hns3_adapter *hns = dev->data->dev_private;
2130         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2131         struct hns3_hw *hw = &hns->hw;
2132         int ret;
2133
2134         if (dev->data->dev_started) {
2135                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2136                          "before configuration", dev->data->port_id);
2137                 return -EBUSY;
2138         }
2139
2140         rte_spinlock_lock(&hw->lock);
2141         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2142
2143         /*
2144          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2145          * assign to "uint16_t" type variable.
2146          */
2147         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2148         if (ret) {
2149                 rte_spinlock_unlock(&hw->lock);
2150                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2151                          dev->data->port_id, mtu, ret);
2152                 return ret;
2153         }
2154
2155         rte_spinlock_unlock(&hw->lock);
2156
2157         return 0;
2158 }
2159
2160 static uint32_t
2161 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2162 {
2163         uint32_t speed_capa = 0;
2164
2165         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2166                 speed_capa |= RTE_ETH_LINK_SPEED_10M_HD;
2167         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2168                 speed_capa |= RTE_ETH_LINK_SPEED_10M;
2169         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2170                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
2171         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2172                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
2173         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2174                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2175
2176         return speed_capa;
2177 }
2178
2179 static uint32_t
2180 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2181 {
2182         uint32_t speed_capa = 0;
2183
2184         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2185                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
2186         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2187                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
2188         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2189                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
2190         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2191                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
2192         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2193                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
2194         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2195                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
2196         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2197                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
2198
2199         return speed_capa;
2200 }
2201
2202 uint32_t
2203 hns3_get_speed_capa(struct hns3_hw *hw)
2204 {
2205         struct hns3_mac *mac = &hw->mac;
2206         uint32_t speed_capa;
2207
2208         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2209                 speed_capa =
2210                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2211         else
2212                 speed_capa =
2213                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2214
2215         if (mac->support_autoneg == 0)
2216                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
2217
2218         return speed_capa;
2219 }
2220
2221 static int
2222 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2223 {
2224         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2225         int ret;
2226
2227         (void)hns3_update_link_status(hw);
2228
2229         ret = hns3_update_link_info(eth_dev);
2230         if (ret)
2231                 hw->mac.link_status = RTE_ETH_LINK_DOWN;
2232
2233         return ret;
2234 }
2235
2236 static void
2237 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2238                       struct rte_eth_link *new_link)
2239 {
2240         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2241         struct hns3_mac *mac = &hw->mac;
2242
2243         switch (mac->link_speed) {
2244         case RTE_ETH_SPEED_NUM_10M:
2245         case RTE_ETH_SPEED_NUM_100M:
2246         case RTE_ETH_SPEED_NUM_1G:
2247         case RTE_ETH_SPEED_NUM_10G:
2248         case RTE_ETH_SPEED_NUM_25G:
2249         case RTE_ETH_SPEED_NUM_40G:
2250         case RTE_ETH_SPEED_NUM_50G:
2251         case RTE_ETH_SPEED_NUM_100G:
2252         case RTE_ETH_SPEED_NUM_200G:
2253                 if (mac->link_status)
2254                         new_link->link_speed = mac->link_speed;
2255                 break;
2256         default:
2257                 if (mac->link_status)
2258                         new_link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2259                 break;
2260         }
2261
2262         if (!mac->link_status)
2263                 new_link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2264
2265         new_link->link_duplex = mac->link_duplex;
2266         new_link->link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2267         new_link->link_autoneg = mac->link_autoneg;
2268 }
2269
2270 static int
2271 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2272 {
2273 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2274 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2275
2276         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2277         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2278         struct hns3_mac *mac = &hw->mac;
2279         struct rte_eth_link new_link;
2280         int ret;
2281
2282         /* When port is stopped, report link down. */
2283         if (eth_dev->data->dev_started == 0) {
2284                 new_link.link_autoneg = mac->link_autoneg;
2285                 new_link.link_duplex = mac->link_duplex;
2286                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2287                 new_link.link_status = RTE_ETH_LINK_DOWN;
2288                 goto out;
2289         }
2290
2291         do {
2292                 ret = hns3_update_port_link_info(eth_dev);
2293                 if (ret) {
2294                         hns3_err(hw, "failed to get port link info, ret = %d.",
2295                                  ret);
2296                         break;
2297                 }
2298
2299                 if (!wait_to_complete || mac->link_status == RTE_ETH_LINK_UP)
2300                         break;
2301
2302                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2303         } while (retry_cnt--);
2304
2305         memset(&new_link, 0, sizeof(new_link));
2306         hns3_setup_linkstatus(eth_dev, &new_link);
2307
2308 out:
2309         return rte_eth_linkstatus_set(eth_dev, &new_link);
2310 }
2311
2312 static int
2313 hns3_dev_set_link_up(struct rte_eth_dev *dev)
2314 {
2315         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         int ret;
2317
2318         /*
2319          * The "tx_pkt_burst" will be restored. But the secondary process does
2320          * not support the mechanism for notifying the primary process.
2321          */
2322         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2323                 hns3_err(hw, "secondary process does not support to set link up.");
2324                 return -ENOTSUP;
2325         }
2326
2327         /*
2328          * If device isn't started Rx/Tx function is still disabled, setting
2329          * link up is not allowed. But it is probably better to return success
2330          * to reduce the impact on the upper layer.
2331          */
2332         if (hw->adapter_state != HNS3_NIC_STARTED) {
2333                 hns3_info(hw, "device isn't started, can't set link up.");
2334                 return 0;
2335         }
2336
2337         if (!hw->set_link_down)
2338                 return 0;
2339
2340         rte_spinlock_lock(&hw->lock);
2341         ret = hns3_cfg_mac_mode(hw, true);
2342         if (ret) {
2343                 rte_spinlock_unlock(&hw->lock);
2344                 hns3_err(hw, "failed to set link up, ret = %d", ret);
2345                 return ret;
2346         }
2347
2348         hw->set_link_down = false;
2349         hns3_start_tx_datapath(dev);
2350         rte_spinlock_unlock(&hw->lock);
2351
2352         return 0;
2353 }
2354
2355 static int
2356 hns3_dev_set_link_down(struct rte_eth_dev *dev)
2357 {
2358         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359         int ret;
2360
2361         /*
2362          * The "tx_pkt_burst" will be set to dummy function. But the secondary
2363          * process does not support the mechanism for notifying the primary
2364          * process.
2365          */
2366         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2367                 hns3_err(hw, "secondary process does not support to set link down.");
2368                 return -ENOTSUP;
2369         }
2370
2371         /*
2372          * If device isn't started or the API has been called, link status is
2373          * down, return success.
2374          */
2375         if (hw->adapter_state != HNS3_NIC_STARTED || hw->set_link_down)
2376                 return 0;
2377
2378         rte_spinlock_lock(&hw->lock);
2379         hns3_stop_tx_datapath(dev);
2380         ret = hns3_cfg_mac_mode(hw, false);
2381         if (ret) {
2382                 hns3_start_tx_datapath(dev);
2383                 rte_spinlock_unlock(&hw->lock);
2384                 hns3_err(hw, "failed to set link down, ret = %d", ret);
2385                 return ret;
2386         }
2387
2388         hw->set_link_down = true;
2389         rte_spinlock_unlock(&hw->lock);
2390
2391         return 0;
2392 }
2393
2394 static int
2395 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2396 {
2397         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2398         struct hns3_pf *pf = &hns->pf;
2399
2400         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2401                 return -EINVAL;
2402
2403         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2404
2405         return 0;
2406 }
2407
2408 static int
2409 hns3_query_function_status(struct hns3_hw *hw)
2410 {
2411 #define HNS3_QUERY_MAX_CNT              10
2412 #define HNS3_QUERY_SLEEP_MSCOEND        1
2413         struct hns3_func_status_cmd *req;
2414         struct hns3_cmd_desc desc;
2415         int timeout = 0;
2416         int ret;
2417
2418         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2419         req = (struct hns3_func_status_cmd *)desc.data;
2420
2421         do {
2422                 ret = hns3_cmd_send(hw, &desc, 1);
2423                 if (ret) {
2424                         PMD_INIT_LOG(ERR, "query function status failed %d",
2425                                      ret);
2426                         return ret;
2427                 }
2428
2429                 /* Check pf reset is done */
2430                 if (req->pf_state)
2431                         break;
2432
2433                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2434         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2435
2436         return hns3_parse_func_status(hw, req);
2437 }
2438
2439 static int
2440 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2441 {
2442         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2443         struct hns3_pf *pf = &hns->pf;
2444
2445         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2446                 /*
2447                  * The total_tqps_num obtained from firmware is maximum tqp
2448                  * numbers of this port, which should be used for PF and VFs.
2449                  * There is no need for pf to have so many tqp numbers in
2450                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2451                  * coming from config file, is assigned to maximum queue number
2452                  * for the PF of this port by user. So users can modify the
2453                  * maximum queue number of PF according to their own application
2454                  * scenarios, which is more flexible to use. In addition, many
2455                  * memories can be saved due to allocating queue statistics
2456                  * room according to the actual number of queues required. The
2457                  * maximum queue number of PF for network engine with
2458                  * revision_id greater than 0x30 is assigned by config file.
2459                  */
2460                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2461                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2462                                  "must be greater than 0.",
2463                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2464                         return -EINVAL;
2465                 }
2466
2467                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2468                                        hw->total_tqps_num);
2469         } else {
2470                 /*
2471                  * Due to the limitation on the number of PF interrupts
2472                  * available, the maximum queue number assigned to PF on
2473                  * the network engine with revision_id 0x21 is 64.
2474                  */
2475                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2476                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2477         }
2478
2479         return 0;
2480 }
2481
2482 static int
2483 hns3_query_pf_resource(struct hns3_hw *hw)
2484 {
2485         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2486         struct hns3_pf *pf = &hns->pf;
2487         struct hns3_pf_res_cmd *req;
2488         struct hns3_cmd_desc desc;
2489         int ret;
2490
2491         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2492         ret = hns3_cmd_send(hw, &desc, 1);
2493         if (ret) {
2494                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2495                 return ret;
2496         }
2497
2498         req = (struct hns3_pf_res_cmd *)desc.data;
2499         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2500                              rte_le_to_cpu_16(req->ext_tqp_num);
2501         ret = hns3_get_pf_max_tqp_num(hw);
2502         if (ret)
2503                 return ret;
2504
2505         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2506         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2507
2508         if (req->tx_buf_size)
2509                 pf->tx_buf_size =
2510                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2511         else
2512                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2513
2514         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2515
2516         if (req->dv_buf_size)
2517                 pf->dv_buf_size =
2518                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2519         else
2520                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2521
2522         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2523
2524         hw->num_msi =
2525                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
2526                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2527
2528         return 0;
2529 }
2530
2531 static void
2532 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2533 {
2534         struct hns3_cfg_param_cmd *req;
2535         uint64_t mac_addr_tmp_high;
2536         uint8_t ext_rss_size_max;
2537         uint64_t mac_addr_tmp;
2538         uint32_t i;
2539
2540         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2541
2542         /* get the configuration */
2543         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2544                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2545         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2546                                            HNS3_CFG_TQP_DESC_N_M,
2547                                            HNS3_CFG_TQP_DESC_N_S);
2548
2549         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2550                                        HNS3_CFG_PHY_ADDR_M,
2551                                        HNS3_CFG_PHY_ADDR_S);
2552         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2553                                          HNS3_CFG_MEDIA_TP_M,
2554                                          HNS3_CFG_MEDIA_TP_S);
2555         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2556                                          HNS3_CFG_RX_BUF_LEN_M,
2557                                          HNS3_CFG_RX_BUF_LEN_S);
2558         /* get mac address */
2559         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2560         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2561                                            HNS3_CFG_MAC_ADDR_H_M,
2562                                            HNS3_CFG_MAC_ADDR_H_S);
2563
2564         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2565
2566         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2567                                             HNS3_CFG_DEFAULT_SPEED_M,
2568                                             HNS3_CFG_DEFAULT_SPEED_S);
2569         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2570                                            HNS3_CFG_RSS_SIZE_M,
2571                                            HNS3_CFG_RSS_SIZE_S);
2572
2573         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2574                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2575
2576         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2577         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2578
2579         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2580                                             HNS3_CFG_SPEED_ABILITY_M,
2581                                             HNS3_CFG_SPEED_ABILITY_S);
2582         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2583                                         HNS3_CFG_UMV_TBL_SPACE_M,
2584                                         HNS3_CFG_UMV_TBL_SPACE_S);
2585         if (!cfg->umv_space)
2586                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2587
2588         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
2589                                                HNS3_CFG_EXT_RSS_SIZE_M,
2590                                                HNS3_CFG_EXT_RSS_SIZE_S);
2591         /*
2592          * Field ext_rss_size_max obtained from firmware will be more flexible
2593          * for future changes and expansions, which is an exponent of 2, instead
2594          * of reading out directly. If this field is not zero, hns3 PF PMD
2595          * uses it as rss_size_max under one TC. Device, whose revision
2596          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
2597          * maximum number of queues supported under a TC through this field.
2598          */
2599         if (ext_rss_size_max)
2600                 cfg->rss_size_max = 1U << ext_rss_size_max;
2601 }
2602
2603 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2604  * @hw: pointer to struct hns3_hw
2605  * @hcfg: the config structure to be getted
2606  */
2607 static int
2608 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2609 {
2610         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2611         struct hns3_cfg_param_cmd *req;
2612         uint32_t offset;
2613         uint32_t i;
2614         int ret;
2615
2616         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2617                 offset = 0;
2618                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2619                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2620                                           true);
2621                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2622                                i * HNS3_CFG_RD_LEN_BYTES);
2623                 /* Len should be divided by 4 when send to hardware */
2624                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2625                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2626                 req->offset = rte_cpu_to_le_32(offset);
2627         }
2628
2629         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2630         if (ret) {
2631                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2632                 return ret;
2633         }
2634
2635         hns3_parse_cfg(hcfg, desc);
2636
2637         return 0;
2638 }
2639
2640 static int
2641 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2642 {
2643         switch (speed_cmd) {
2644         case HNS3_CFG_SPEED_10M:
2645                 *speed = RTE_ETH_SPEED_NUM_10M;
2646                 break;
2647         case HNS3_CFG_SPEED_100M:
2648                 *speed = RTE_ETH_SPEED_NUM_100M;
2649                 break;
2650         case HNS3_CFG_SPEED_1G:
2651                 *speed = RTE_ETH_SPEED_NUM_1G;
2652                 break;
2653         case HNS3_CFG_SPEED_10G:
2654                 *speed = RTE_ETH_SPEED_NUM_10G;
2655                 break;
2656         case HNS3_CFG_SPEED_25G:
2657                 *speed = RTE_ETH_SPEED_NUM_25G;
2658                 break;
2659         case HNS3_CFG_SPEED_40G:
2660                 *speed = RTE_ETH_SPEED_NUM_40G;
2661                 break;
2662         case HNS3_CFG_SPEED_50G:
2663                 *speed = RTE_ETH_SPEED_NUM_50G;
2664                 break;
2665         case HNS3_CFG_SPEED_100G:
2666                 *speed = RTE_ETH_SPEED_NUM_100G;
2667                 break;
2668         case HNS3_CFG_SPEED_200G:
2669                 *speed = RTE_ETH_SPEED_NUM_200G;
2670                 break;
2671         default:
2672                 return -EINVAL;
2673         }
2674
2675         return 0;
2676 }
2677
2678 static void
2679 hns3_set_default_dev_specifications(struct hns3_hw *hw)
2680 {
2681         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
2682         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
2683         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
2684         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
2685         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
2686 }
2687
2688 static void
2689 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
2690 {
2691         struct hns3_dev_specs_0_cmd *req0;
2692
2693         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
2694
2695         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
2696         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
2697         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
2698         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
2699         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
2700 }
2701
2702 static int
2703 hns3_check_dev_specifications(struct hns3_hw *hw)
2704 {
2705         if (hw->rss_ind_tbl_size == 0 ||
2706             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
2707                 hns3_err(hw, "the size of hash lookup table configured (%u)"
2708                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
2709                               HNS3_RSS_IND_TBL_SIZE_MAX);
2710                 return -EINVAL;
2711         }
2712
2713         return 0;
2714 }
2715
2716 static int
2717 hns3_query_dev_specifications(struct hns3_hw *hw)
2718 {
2719         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
2720         int ret;
2721         int i;
2722
2723         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
2724                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
2725                                           true);
2726                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2727         }
2728         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
2729
2730         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
2731         if (ret)
2732                 return ret;
2733
2734         hns3_parse_dev_specifications(hw, desc);
2735
2736         return hns3_check_dev_specifications(hw);
2737 }
2738
2739 static int
2740 hns3_get_capability(struct hns3_hw *hw)
2741 {
2742         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2743         struct rte_pci_device *pci_dev;
2744         struct hns3_pf *pf = &hns->pf;
2745         struct rte_eth_dev *eth_dev;
2746         uint16_t device_id;
2747         uint8_t revision;
2748         int ret;
2749
2750         eth_dev = &rte_eth_devices[hw->data->port_id];
2751         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2752         device_id = pci_dev->id.device_id;
2753
2754         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
2755             device_id == HNS3_DEV_ID_50GE_RDMA ||
2756             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
2757             device_id == HNS3_DEV_ID_200G_RDMA)
2758                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
2759
2760         /* Get PCI revision id */
2761         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2762                                   HNS3_PCI_REVISION_ID);
2763         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2764                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
2765                              ret);
2766                 return -EIO;
2767         }
2768         hw->revision = revision;
2769
2770         if (revision < PCI_REVISION_ID_HIP09_A) {
2771                 hns3_set_default_dev_specifications(hw);
2772                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
2773                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
2774                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
2775                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
2776                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
2777                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
2778                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
2779                 hw->rss_info.ipv6_sctp_offload_supported = false;
2780                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
2781                 pf->support_multi_tc_pause = false;
2782                 return 0;
2783         }
2784
2785         ret = hns3_query_dev_specifications(hw);
2786         if (ret) {
2787                 PMD_INIT_LOG(ERR,
2788                              "failed to query dev specifications, ret = %d",
2789                              ret);
2790                 return ret;
2791         }
2792
2793         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
2794         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
2795         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
2796         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
2797         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
2798         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
2799         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
2800         hw->rss_info.ipv6_sctp_offload_supported = true;
2801         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
2802         pf->support_multi_tc_pause = true;
2803
2804         return 0;
2805 }
2806
2807 static int
2808 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
2809 {
2810         int ret;
2811
2812         switch (media_type) {
2813         case HNS3_MEDIA_TYPE_COPPER:
2814                 if (!hns3_dev_get_support(hw, COPPER)) {
2815                         PMD_INIT_LOG(ERR,
2816                                      "Media type is copper, not supported.");
2817                         ret = -EOPNOTSUPP;
2818                 } else {
2819                         ret = 0;
2820                 }
2821                 break;
2822         case HNS3_MEDIA_TYPE_FIBER:
2823                 ret = 0;
2824                 break;
2825         case HNS3_MEDIA_TYPE_BACKPLANE:
2826                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
2827                 ret = -EOPNOTSUPP;
2828                 break;
2829         default:
2830                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
2831                 ret = -EINVAL;
2832                 break;
2833         }
2834
2835         return ret;
2836 }
2837
2838 static int
2839 hns3_get_board_configuration(struct hns3_hw *hw)
2840 {
2841         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2842         struct hns3_pf *pf = &hns->pf;
2843         struct hns3_cfg cfg;
2844         int ret;
2845
2846         ret = hns3_get_board_cfg(hw, &cfg);
2847         if (ret) {
2848                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2849                 return ret;
2850         }
2851
2852         ret = hns3_check_media_type(hw, cfg.media_type);
2853         if (ret)
2854                 return ret;
2855
2856         hw->mac.media_type = cfg.media_type;
2857         hw->rss_size_max = cfg.rss_size_max;
2858         hw->rss_dis_flag = false;
2859         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2860         hw->mac.phy_addr = cfg.phy_addr;
2861         hw->num_tx_desc = cfg.tqp_desc_num;
2862         hw->num_rx_desc = cfg.tqp_desc_num;
2863         hw->dcb_info.num_pg = 1;
2864         hw->dcb_info.hw_pfc_map = 0;
2865
2866         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2867         if (ret) {
2868                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
2869                              cfg.default_speed, ret);
2870                 return ret;
2871         }
2872
2873         pf->tc_max = cfg.tc_num;
2874         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2875                 PMD_INIT_LOG(WARNING,
2876                              "Get TC num(%u) from flash, set TC num to 1",
2877                              pf->tc_max);
2878                 pf->tc_max = 1;
2879         }
2880
2881         /* Dev does not support DCB */
2882         if (!hns3_dev_get_support(hw, DCB)) {
2883                 pf->tc_max = 1;
2884                 pf->pfc_max = 0;
2885         } else
2886                 pf->pfc_max = pf->tc_max;
2887
2888         hw->dcb_info.num_tc = 1;
2889         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2890                                      hw->tqps_num / hw->dcb_info.num_tc);
2891         hns3_set_bit(hw->hw_tc_map, 0, 1);
2892         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2893
2894         pf->wanted_umv_size = cfg.umv_space;
2895
2896         return ret;
2897 }
2898
2899 static int
2900 hns3_get_configuration(struct hns3_hw *hw)
2901 {
2902         int ret;
2903
2904         ret = hns3_query_function_status(hw);
2905         if (ret) {
2906                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2907                 return ret;
2908         }
2909
2910         /* Get device capability */
2911         ret = hns3_get_capability(hw);
2912         if (ret) {
2913                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
2914                 return ret;
2915         }
2916
2917         /* Get pf resource */
2918         ret = hns3_query_pf_resource(hw);
2919         if (ret) {
2920                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2921                 return ret;
2922         }
2923
2924         ret = hns3_get_board_configuration(hw);
2925         if (ret) {
2926                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
2927                 return ret;
2928         }
2929
2930         ret = hns3_query_dev_fec_info(hw);
2931         if (ret)
2932                 PMD_INIT_LOG(ERR,
2933                              "failed to query FEC information, ret = %d", ret);
2934
2935         return ret;
2936 }
2937
2938 static int
2939 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2940                       uint16_t tqp_vid, bool is_pf)
2941 {
2942         struct hns3_tqp_map_cmd *req;
2943         struct hns3_cmd_desc desc;
2944         int ret;
2945
2946         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2947
2948         req = (struct hns3_tqp_map_cmd *)desc.data;
2949         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2950         req->tqp_vf = func_id;
2951         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2952         if (!is_pf)
2953                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2954         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2955
2956         ret = hns3_cmd_send(hw, &desc, 1);
2957         if (ret)
2958                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2959
2960         return ret;
2961 }
2962
2963 static int
2964 hns3_map_tqp(struct hns3_hw *hw)
2965 {
2966         int ret;
2967         int i;
2968
2969         /*
2970          * In current version, VF is not supported when PF is driven by DPDK
2971          * driver, so we assign total tqps_num tqps allocated to this port
2972          * to PF.
2973          */
2974         for (i = 0; i < hw->total_tqps_num; i++) {
2975                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
2976                 if (ret)
2977                         return ret;
2978         }
2979
2980         return 0;
2981 }
2982
2983 static int
2984 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2985 {
2986         struct hns3_config_mac_speed_dup_cmd *req;
2987         struct hns3_cmd_desc desc;
2988         int ret;
2989
2990         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2991
2992         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2993
2994         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2995
2996         switch (speed) {
2997         case RTE_ETH_SPEED_NUM_10M:
2998                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2999                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3000                 break;
3001         case RTE_ETH_SPEED_NUM_100M:
3002                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3003                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3004                 break;
3005         case RTE_ETH_SPEED_NUM_1G:
3006                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3007                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3008                 break;
3009         case RTE_ETH_SPEED_NUM_10G:
3010                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3011                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3012                 break;
3013         case RTE_ETH_SPEED_NUM_25G:
3014                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3015                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3016                 break;
3017         case RTE_ETH_SPEED_NUM_40G:
3018                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3019                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3020                 break;
3021         case RTE_ETH_SPEED_NUM_50G:
3022                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3023                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3024                 break;
3025         case RTE_ETH_SPEED_NUM_100G:
3026                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3027                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3028                 break;
3029         case RTE_ETH_SPEED_NUM_200G:
3030                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3031                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3032                 break;
3033         default:
3034                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3035                 return -EINVAL;
3036         }
3037
3038         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3039
3040         ret = hns3_cmd_send(hw, &desc, 1);
3041         if (ret)
3042                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3043
3044         return ret;
3045 }
3046
3047 static int
3048 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3049 {
3050         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3051         struct hns3_pf *pf = &hns->pf;
3052         struct hns3_priv_buf *priv;
3053         uint32_t i, total_size;
3054
3055         total_size = pf->pkt_buf_size;
3056
3057         /* alloc tx buffer for all enabled tc */
3058         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3059                 priv = &buf_alloc->priv_buf[i];
3060
3061                 if (hw->hw_tc_map & BIT(i)) {
3062                         if (total_size < pf->tx_buf_size)
3063                                 return -ENOMEM;
3064
3065                         priv->tx_buf_size = pf->tx_buf_size;
3066                 } else
3067                         priv->tx_buf_size = 0;
3068
3069                 total_size -= priv->tx_buf_size;
3070         }
3071
3072         return 0;
3073 }
3074
3075 static int
3076 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3077 {
3078 /* TX buffer size is unit by 128 byte */
3079 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3080 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3081         struct hns3_tx_buff_alloc_cmd *req;
3082         struct hns3_cmd_desc desc;
3083         uint32_t buf_size;
3084         uint32_t i;
3085         int ret;
3086
3087         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3088
3089         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3090         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3091                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3092
3093                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3094                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3095                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3096         }
3097
3098         ret = hns3_cmd_send(hw, &desc, 1);
3099         if (ret)
3100                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3101
3102         return ret;
3103 }
3104
3105 static int
3106 hns3_get_tc_num(struct hns3_hw *hw)
3107 {
3108         int cnt = 0;
3109         uint8_t i;
3110
3111         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3112                 if (hw->hw_tc_map & BIT(i))
3113                         cnt++;
3114         return cnt;
3115 }
3116
3117 static uint32_t
3118 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3119 {
3120         struct hns3_priv_buf *priv;
3121         uint32_t rx_priv = 0;
3122         int i;
3123
3124         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3125                 priv = &buf_alloc->priv_buf[i];
3126                 if (priv->enable)
3127                         rx_priv += priv->buf_size;
3128         }
3129         return rx_priv;
3130 }
3131
3132 static uint32_t
3133 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3134 {
3135         uint32_t total_tx_size = 0;
3136         uint32_t i;
3137
3138         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3139                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3140
3141         return total_tx_size;
3142 }
3143
3144 /* Get the number of pfc enabled TCs, which have private buffer */
3145 static int
3146 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3147 {
3148         struct hns3_priv_buf *priv;
3149         int cnt = 0;
3150         uint8_t i;
3151
3152         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3153                 priv = &buf_alloc->priv_buf[i];
3154                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3155                         cnt++;
3156         }
3157
3158         return cnt;
3159 }
3160
3161 /* Get the number of pfc disabled TCs, which have private buffer */
3162 static int
3163 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3164                          struct hns3_pkt_buf_alloc *buf_alloc)
3165 {
3166         struct hns3_priv_buf *priv;
3167         int cnt = 0;
3168         uint8_t i;
3169
3170         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3171                 priv = &buf_alloc->priv_buf[i];
3172                 if (hw->hw_tc_map & BIT(i) &&
3173                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3174                         cnt++;
3175         }
3176
3177         return cnt;
3178 }
3179
3180 static bool
3181 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3182                   uint32_t rx_all)
3183 {
3184         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3185         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3186         struct hns3_pf *pf = &hns->pf;
3187         uint32_t shared_buf, aligned_mps;
3188         uint32_t rx_priv;
3189         uint8_t tc_num;
3190         uint8_t i;
3191
3192         tc_num = hns3_get_tc_num(hw);
3193         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3194
3195         if (hns3_dev_get_support(hw, DCB))
3196                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3197                                         pf->dv_buf_size;
3198         else
3199                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3200                                         + pf->dv_buf_size;
3201
3202         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3203         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3204                              HNS3_BUF_SIZE_UNIT);
3205
3206         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3207         if (rx_all < rx_priv + shared_std)
3208                 return false;
3209
3210         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3211         buf_alloc->s_buf.buf_size = shared_buf;
3212         if (hns3_dev_get_support(hw, DCB)) {
3213                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3214                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3215                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3216                                   HNS3_BUF_SIZE_UNIT);
3217         } else {
3218                 buf_alloc->s_buf.self.high =
3219                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3220                 buf_alloc->s_buf.self.low = aligned_mps;
3221         }
3222
3223         if (hns3_dev_get_support(hw, DCB)) {
3224                 hi_thrd = shared_buf - pf->dv_buf_size;
3225
3226                 if (tc_num <= NEED_RESERVE_TC_NUM)
3227                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3228                                   BUF_MAX_PERCENT;
3229
3230                 if (tc_num)
3231                         hi_thrd = hi_thrd / tc_num;
3232
3233                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3234                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3235                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3236         } else {
3237                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3238                 lo_thrd = aligned_mps;
3239         }
3240
3241         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3242                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3243                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3244         }
3245
3246         return true;
3247 }
3248
3249 static bool
3250 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3251                      struct hns3_pkt_buf_alloc *buf_alloc)
3252 {
3253         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3254         struct hns3_pf *pf = &hns->pf;
3255         struct hns3_priv_buf *priv;
3256         uint32_t aligned_mps;
3257         uint32_t rx_all;
3258         uint8_t i;
3259
3260         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3261         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3262
3263         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3264                 priv = &buf_alloc->priv_buf[i];
3265
3266                 priv->enable = 0;
3267                 priv->wl.low = 0;
3268                 priv->wl.high = 0;
3269                 priv->buf_size = 0;
3270
3271                 if (!(hw->hw_tc_map & BIT(i)))
3272                         continue;
3273
3274                 priv->enable = 1;
3275                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3276                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3277                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3278                                                 HNS3_BUF_SIZE_UNIT);
3279                 } else {
3280                         priv->wl.low = 0;
3281                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3282                                         aligned_mps;
3283                 }
3284
3285                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3286         }
3287
3288         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3289 }
3290
3291 static bool
3292 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3293                              struct hns3_pkt_buf_alloc *buf_alloc)
3294 {
3295         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3296         struct hns3_pf *pf = &hns->pf;
3297         struct hns3_priv_buf *priv;
3298         int no_pfc_priv_num;
3299         uint32_t rx_all;
3300         uint8_t mask;
3301         int i;
3302
3303         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3304         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3305
3306         /* let the last to be cleared first */
3307         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3308                 priv = &buf_alloc->priv_buf[i];
3309                 mask = BIT((uint8_t)i);
3310                 if (hw->hw_tc_map & mask &&
3311                     !(hw->dcb_info.hw_pfc_map & mask)) {
3312                         /* Clear the no pfc TC private buffer */
3313                         priv->wl.low = 0;
3314                         priv->wl.high = 0;
3315                         priv->buf_size = 0;
3316                         priv->enable = 0;
3317                         no_pfc_priv_num--;
3318                 }
3319
3320                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3321                     no_pfc_priv_num == 0)
3322                         break;
3323         }
3324
3325         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3326 }
3327
3328 static bool
3329 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3330                            struct hns3_pkt_buf_alloc *buf_alloc)
3331 {
3332         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3333         struct hns3_pf *pf = &hns->pf;
3334         struct hns3_priv_buf *priv;
3335         uint32_t rx_all;
3336         int pfc_priv_num;
3337         uint8_t mask;
3338         int i;
3339
3340         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3341         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3342
3343         /* let the last to be cleared first */
3344         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3345                 priv = &buf_alloc->priv_buf[i];
3346                 mask = BIT((uint8_t)i);
3347                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3348                         /* Reduce the number of pfc TC with private buffer */
3349                         priv->wl.low = 0;
3350                         priv->enable = 0;
3351                         priv->wl.high = 0;
3352                         priv->buf_size = 0;
3353                         pfc_priv_num--;
3354                 }
3355                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3356                     pfc_priv_num == 0)
3357                         break;
3358         }
3359
3360         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3361 }
3362
3363 static bool
3364 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3365                           struct hns3_pkt_buf_alloc *buf_alloc)
3366 {
3367 #define COMPENSATE_BUFFER       0x3C00
3368 #define COMPENSATE_HALF_MPS_NUM 5
3369 #define PRIV_WL_GAP             0x1800
3370         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3371         struct hns3_pf *pf = &hns->pf;
3372         uint32_t tc_num = hns3_get_tc_num(hw);
3373         uint32_t half_mps = pf->mps >> 1;
3374         struct hns3_priv_buf *priv;
3375         uint32_t min_rx_priv;
3376         uint32_t rx_priv;
3377         uint8_t i;
3378
3379         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3380         if (tc_num)
3381                 rx_priv = rx_priv / tc_num;
3382
3383         if (tc_num <= NEED_RESERVE_TC_NUM)
3384                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3385
3386         /*
3387          * Minimum value of private buffer in rx direction (min_rx_priv) is
3388          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3389          * buffer if rx_priv is greater than min_rx_priv.
3390          */
3391         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3392                         COMPENSATE_HALF_MPS_NUM * half_mps;
3393         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3394         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3395         if (rx_priv < min_rx_priv)
3396                 return false;
3397
3398         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3399                 priv = &buf_alloc->priv_buf[i];
3400                 priv->enable = 0;
3401                 priv->wl.low = 0;
3402                 priv->wl.high = 0;
3403                 priv->buf_size = 0;
3404
3405                 if (!(hw->hw_tc_map & BIT(i)))
3406                         continue;
3407
3408                 priv->enable = 1;
3409                 priv->buf_size = rx_priv;
3410                 priv->wl.high = rx_priv - pf->dv_buf_size;
3411                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3412         }
3413
3414         buf_alloc->s_buf.buf_size = 0;
3415
3416         return true;
3417 }
3418
3419 /*
3420  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3421  * @hw: pointer to struct hns3_hw
3422  * @buf_alloc: pointer to buffer calculation data
3423  * @return: 0: calculate sucessful, negative: fail
3424  */
3425 static int
3426 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3427 {
3428         /* When DCB is not supported, rx private buffer is not allocated. */
3429         if (!hns3_dev_get_support(hw, DCB)) {
3430                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3431                 struct hns3_pf *pf = &hns->pf;
3432                 uint32_t rx_all = pf->pkt_buf_size;
3433
3434                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3435                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3436                         return -ENOMEM;
3437
3438                 return 0;
3439         }
3440
3441         /*
3442          * Try to allocate privated packet buffer for all TCs without share
3443          * buffer.
3444          */
3445         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3446                 return 0;
3447
3448         /*
3449          * Try to allocate privated packet buffer for all TCs with share
3450          * buffer.
3451          */
3452         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3453                 return 0;
3454
3455         /*
3456          * For different application scenes, the enabled port number, TC number
3457          * and no_drop TC number are different. In order to obtain the better
3458          * performance, software could allocate the buffer size and configure
3459          * the waterline by trying to decrease the private buffer size according
3460          * to the order, namely, waterline of valid tc, pfc disabled tc, pfc
3461          * enabled tc.
3462          */
3463         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3464                 return 0;
3465
3466         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3467                 return 0;
3468
3469         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3470                 return 0;
3471
3472         return -ENOMEM;
3473 }
3474
3475 static int
3476 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3477 {
3478         struct hns3_rx_priv_buff_cmd *req;
3479         struct hns3_cmd_desc desc;
3480         uint32_t buf_size;
3481         int ret;
3482         int i;
3483
3484         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3485         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3486
3487         /* Alloc private buffer TCs */
3488         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3489                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3490
3491                 req->buf_num[i] =
3492                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3493                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3494         }
3495
3496         buf_size = buf_alloc->s_buf.buf_size;
3497         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3498                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3499
3500         ret = hns3_cmd_send(hw, &desc, 1);
3501         if (ret)
3502                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3503
3504         return ret;
3505 }
3506
3507 static int
3508 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3509 {
3510 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3511         struct hns3_rx_priv_wl_buf *req;
3512         struct hns3_priv_buf *priv;
3513         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3514         int i, j;
3515         int ret;
3516
3517         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3518                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3519                                           false);
3520                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3521
3522                 /* The first descriptor set the NEXT bit to 1 */
3523                 if (i == 0)
3524                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3525                 else
3526                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3527
3528                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3529                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3530
3531                         priv = &buf_alloc->priv_buf[idx];
3532                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3533                                                         HNS3_BUF_UNIT_S);
3534                         req->tc_wl[j].high |=
3535                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3536                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3537                                                         HNS3_BUF_UNIT_S);
3538                         req->tc_wl[j].low |=
3539                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3540                 }
3541         }
3542
3543         /* Send 2 descriptor at one time */
3544         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3545         if (ret)
3546                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3547                              ret);
3548         return ret;
3549 }
3550
3551 static int
3552 hns3_common_thrd_config(struct hns3_hw *hw,
3553                         struct hns3_pkt_buf_alloc *buf_alloc)
3554 {
3555 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3556         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3557         struct hns3_rx_com_thrd *req;
3558         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3559         struct hns3_tc_thrd *tc;
3560         int tc_idx;
3561         int i, j;
3562         int ret;
3563
3564         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3565                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3566                                           false);
3567                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3568
3569                 /* The first descriptor set the NEXT bit to 1 */
3570                 if (i == 0)
3571                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3572                 else
3573                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3574
3575                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3576                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3577                         tc = &s_buf->tc_thrd[tc_idx];
3578
3579                         req->com_thrd[j].high =
3580                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3581                         req->com_thrd[j].high |=
3582                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3583                         req->com_thrd[j].low =
3584                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3585                         req->com_thrd[j].low |=
3586                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3587                 }
3588         }
3589
3590         /* Send 2 descriptors at one time */
3591         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3592         if (ret)
3593                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3594
3595         return ret;
3596 }
3597
3598 static int
3599 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3600 {
3601         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3602         struct hns3_rx_com_wl *req;
3603         struct hns3_cmd_desc desc;
3604         int ret;
3605
3606         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3607
3608         req = (struct hns3_rx_com_wl *)desc.data;
3609         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3610         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3611
3612         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3613         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3614
3615         ret = hns3_cmd_send(hw, &desc, 1);
3616         if (ret)
3617                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3618
3619         return ret;
3620 }
3621
3622 int
3623 hns3_buffer_alloc(struct hns3_hw *hw)
3624 {
3625         struct hns3_pkt_buf_alloc pkt_buf;
3626         int ret;
3627
3628         memset(&pkt_buf, 0, sizeof(pkt_buf));
3629         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3630         if (ret) {
3631                 PMD_INIT_LOG(ERR,
3632                              "could not calc tx buffer size for all TCs %d",
3633                              ret);
3634                 return ret;
3635         }
3636
3637         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3638         if (ret) {
3639                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3640                 return ret;
3641         }
3642
3643         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3644         if (ret) {
3645                 PMD_INIT_LOG(ERR,
3646                              "could not calc rx priv buffer size for all TCs %d",
3647                              ret);
3648                 return ret;
3649         }
3650
3651         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3652         if (ret) {
3653                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3654                 return ret;
3655         }
3656
3657         if (hns3_dev_get_support(hw, DCB)) {
3658                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3659                 if (ret) {
3660                         PMD_INIT_LOG(ERR,
3661                                      "could not configure rx private waterline %d",
3662                                      ret);
3663                         return ret;
3664                 }
3665
3666                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3667                 if (ret) {
3668                         PMD_INIT_LOG(ERR,
3669                                      "could not configure common threshold %d",
3670                                      ret);
3671                         return ret;
3672                 }
3673         }
3674
3675         ret = hns3_common_wl_config(hw, &pkt_buf);
3676         if (ret)
3677                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3678                              ret);
3679
3680         return ret;
3681 }
3682
3683 static int
3684 hns3_mac_init(struct hns3_hw *hw)
3685 {
3686         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3687         struct hns3_mac *mac = &hw->mac;
3688         struct hns3_pf *pf = &hns->pf;
3689         int ret;
3690
3691         pf->support_sfp_query = true;
3692         mac->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
3693         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3694         if (ret) {
3695                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3696                 return ret;
3697         }
3698
3699         mac->link_status = RTE_ETH_LINK_DOWN;
3700
3701         return hns3_config_mtu(hw, pf->mps);
3702 }
3703
3704 static int
3705 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3706 {
3707 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3708 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3709 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3710 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3711         int return_status;
3712
3713         if (cmdq_resp) {
3714                 PMD_INIT_LOG(ERR,
3715                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
3716                              cmdq_resp);
3717                 return -EIO;
3718         }
3719
3720         switch (resp_code) {
3721         case HNS3_ETHERTYPE_SUCCESS_ADD:
3722         case HNS3_ETHERTYPE_ALREADY_ADD:
3723                 return_status = 0;
3724                 break;
3725         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3726                 PMD_INIT_LOG(ERR,
3727                              "add mac ethertype failed for manager table overflow.");
3728                 return_status = -EIO;
3729                 break;
3730         case HNS3_ETHERTYPE_KEY_CONFLICT:
3731                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3732                 return_status = -EIO;
3733                 break;
3734         default:
3735                 PMD_INIT_LOG(ERR,
3736                              "add mac ethertype failed for undefined, code=%u.",
3737                              resp_code);
3738                 return_status = -EIO;
3739                 break;
3740         }
3741
3742         return return_status;
3743 }
3744
3745 static int
3746 hns3_add_mgr_tbl(struct hns3_hw *hw,
3747                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3748 {
3749         struct hns3_cmd_desc desc;
3750         uint8_t resp_code;
3751         uint16_t retval;
3752         int ret;
3753
3754         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3755         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3756
3757         ret = hns3_cmd_send(hw, &desc, 1);
3758         if (ret) {
3759                 PMD_INIT_LOG(ERR,
3760                              "add mac ethertype failed for cmd_send, ret =%d.",
3761                              ret);
3762                 return ret;
3763         }
3764
3765         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3766         retval = rte_le_to_cpu_16(desc.retval);
3767
3768         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3769 }
3770
3771 static void
3772 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3773                      int *table_item_num)
3774 {
3775         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3776
3777         /*
3778          * In current version, we add one item in management table as below:
3779          * 0x0180C200000E -- LLDP MC address
3780          */
3781         tbl = mgr_table;
3782         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3783         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3784         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3785         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3786         tbl->i_port_bitmap = 0x1;
3787         *table_item_num = 1;
3788 }
3789
3790 static int
3791 hns3_init_mgr_tbl(struct hns3_hw *hw)
3792 {
3793 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3794         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3795         int table_item_num;
3796         int ret;
3797         int i;
3798
3799         memset(mgr_table, 0, sizeof(mgr_table));
3800         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3801         for (i = 0; i < table_item_num; i++) {
3802                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3803                 if (ret) {
3804                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3805                                      ret);
3806                         return ret;
3807                 }
3808         }
3809
3810         return 0;
3811 }
3812
3813 static void
3814 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3815                         bool en_mc, bool en_bc, int vport_id)
3816 {
3817         if (!param)
3818                 return;
3819
3820         memset(param, 0, sizeof(struct hns3_promisc_param));
3821         if (en_uc)
3822                 param->enable = HNS3_PROMISC_EN_UC;
3823         if (en_mc)
3824                 param->enable |= HNS3_PROMISC_EN_MC;
3825         if (en_bc)
3826                 param->enable |= HNS3_PROMISC_EN_BC;
3827         param->vf_id = vport_id;
3828 }
3829
3830 static int
3831 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3832 {
3833         struct hns3_promisc_cfg_cmd *req;
3834         struct hns3_cmd_desc desc;
3835         int ret;
3836
3837         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3838
3839         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3840         req->vf_id = param->vf_id;
3841         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3842             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3843
3844         ret = hns3_cmd_send(hw, &desc, 1);
3845         if (ret)
3846                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3847
3848         return ret;
3849 }
3850
3851 static int
3852 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3853 {
3854         struct hns3_promisc_param param;
3855         bool en_bc_pmc = true;
3856         uint8_t vf_id;
3857
3858         /*
3859          * In current version VF is not supported when PF is driven by DPDK
3860          * driver, just need to configure parameters for PF vport.
3861          */
3862         vf_id = HNS3_PF_FUNC_ID;
3863
3864         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3865         return hns3_cmd_set_promisc_mode(hw, &param);
3866 }
3867
3868 static int
3869 hns3_promisc_init(struct hns3_hw *hw)
3870 {
3871         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3872         struct hns3_pf *pf = &hns->pf;
3873         struct hns3_promisc_param param;
3874         uint16_t func_id;
3875         int ret;
3876
3877         ret = hns3_set_promisc_mode(hw, false, false);
3878         if (ret) {
3879                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3880                 return ret;
3881         }
3882
3883         /*
3884          * In current version VFs are not supported when PF is driven by DPDK
3885          * driver. After PF has been taken over by DPDK, the original VF will
3886          * be invalid. So, there is a possibility of entry residues. It should
3887          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3888          * during init.
3889          */
3890         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3891                 hns3_promisc_param_init(&param, false, false, false, func_id);
3892                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3893                 if (ret) {
3894                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
3895                                         " ret = %d", func_id, ret);
3896                         return ret;
3897                 }
3898         }
3899
3900         return 0;
3901 }
3902
3903 static void
3904 hns3_promisc_uninit(struct hns3_hw *hw)
3905 {
3906         struct hns3_promisc_param param;
3907         uint16_t func_id;
3908         int ret;
3909
3910         func_id = HNS3_PF_FUNC_ID;
3911
3912         /*
3913          * In current version VFs are not supported when PF is driven by
3914          * DPDK driver, and VFs' promisc mode status has been cleared during
3915          * init and their status will not change. So just clear PF's promisc
3916          * mode status during uninit.
3917          */
3918         hns3_promisc_param_init(&param, false, false, false, func_id);
3919         ret = hns3_cmd_set_promisc_mode(hw, &param);
3920         if (ret)
3921                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3922                                 " uninit, ret = %d", ret);
3923 }
3924
3925 static int
3926 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3927 {
3928         bool allmulti = dev->data->all_multicast ? true : false;
3929         struct hns3_adapter *hns = dev->data->dev_private;
3930         struct hns3_hw *hw = &hns->hw;
3931         uint64_t offloads;
3932         int err;
3933         int ret;
3934
3935         rte_spinlock_lock(&hw->lock);
3936         ret = hns3_set_promisc_mode(hw, true, true);
3937         if (ret) {
3938                 rte_spinlock_unlock(&hw->lock);
3939                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3940                          ret);
3941                 return ret;
3942         }
3943
3944         /*
3945          * When promiscuous mode was enabled, disable the vlan filter to let
3946          * all packets coming in in the receiving direction.
3947          */
3948         offloads = dev->data->dev_conf.rxmode.offloads;
3949         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3950                 ret = hns3_enable_vlan_filter(hns, false);
3951                 if (ret) {
3952                         hns3_err(hw, "failed to enable promiscuous mode due to "
3953                                      "failure to disable vlan filter, ret = %d",
3954                                  ret);
3955                         err = hns3_set_promisc_mode(hw, false, allmulti);
3956                         if (err)
3957                                 hns3_err(hw, "failed to restore promiscuous "
3958                                          "status after disable vlan filter "
3959                                          "failed during enabling promiscuous "
3960                                          "mode, ret = %d", ret);
3961                 }
3962         }
3963
3964         rte_spinlock_unlock(&hw->lock);
3965
3966         return ret;
3967 }
3968
3969 static int
3970 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3971 {
3972         bool allmulti = dev->data->all_multicast ? true : false;
3973         struct hns3_adapter *hns = dev->data->dev_private;
3974         struct hns3_hw *hw = &hns->hw;
3975         uint64_t offloads;
3976         int err;
3977         int ret;
3978
3979         /* If now in all_multicast mode, must remain in all_multicast mode. */
3980         rte_spinlock_lock(&hw->lock);
3981         ret = hns3_set_promisc_mode(hw, false, allmulti);
3982         if (ret) {
3983                 rte_spinlock_unlock(&hw->lock);
3984                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3985                          ret);
3986                 return ret;
3987         }
3988         /* when promiscuous mode was disabled, restore the vlan filter status */
3989         offloads = dev->data->dev_conf.rxmode.offloads;
3990         if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
3991                 ret = hns3_enable_vlan_filter(hns, true);
3992                 if (ret) {
3993                         hns3_err(hw, "failed to disable promiscuous mode due to"
3994                                  " failure to restore vlan filter, ret = %d",
3995                                  ret);
3996                         err = hns3_set_promisc_mode(hw, true, true);
3997                         if (err)
3998                                 hns3_err(hw, "failed to restore promiscuous "
3999                                          "status after enabling vlan filter "
4000                                          "failed during disabling promiscuous "
4001                                          "mode, ret = %d", ret);
4002                 }
4003         }
4004         rte_spinlock_unlock(&hw->lock);
4005
4006         return ret;
4007 }
4008
4009 static int
4010 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4011 {
4012         struct hns3_adapter *hns = dev->data->dev_private;
4013         struct hns3_hw *hw = &hns->hw;
4014         int ret;
4015
4016         if (dev->data->promiscuous)
4017                 return 0;
4018
4019         rte_spinlock_lock(&hw->lock);
4020         ret = hns3_set_promisc_mode(hw, false, true);
4021         rte_spinlock_unlock(&hw->lock);
4022         if (ret)
4023                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4024                          ret);
4025
4026         return ret;
4027 }
4028
4029 static int
4030 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4031 {
4032         struct hns3_adapter *hns = dev->data->dev_private;
4033         struct hns3_hw *hw = &hns->hw;
4034         int ret;
4035
4036         /* If now in promiscuous mode, must remain in all_multicast mode. */
4037         if (dev->data->promiscuous)
4038                 return 0;
4039
4040         rte_spinlock_lock(&hw->lock);
4041         ret = hns3_set_promisc_mode(hw, false, false);
4042         rte_spinlock_unlock(&hw->lock);
4043         if (ret)
4044                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4045                          ret);
4046
4047         return ret;
4048 }
4049
4050 static int
4051 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4052 {
4053         struct hns3_hw *hw = &hns->hw;
4054         bool allmulti = hw->data->all_multicast ? true : false;
4055         int ret;
4056
4057         if (hw->data->promiscuous) {
4058                 ret = hns3_set_promisc_mode(hw, true, true);
4059                 if (ret)
4060                         hns3_err(hw, "failed to restore promiscuous mode, "
4061                                  "ret = %d", ret);
4062                 return ret;
4063         }
4064
4065         ret = hns3_set_promisc_mode(hw, false, allmulti);
4066         if (ret)
4067                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4068                          ret);
4069         return ret;
4070 }
4071
4072 static int
4073 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4074 {
4075         struct hns3_sfp_info_cmd *resp;
4076         struct hns3_cmd_desc desc;
4077         int ret;
4078
4079         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4080         resp = (struct hns3_sfp_info_cmd *)desc.data;
4081         resp->query_type = HNS3_ACTIVE_QUERY;
4082
4083         ret = hns3_cmd_send(hw, &desc, 1);
4084         if (ret == -EOPNOTSUPP) {
4085                 hns3_warn(hw, "firmware does not support get SFP info,"
4086                           " ret = %d.", ret);
4087                 return ret;
4088         } else if (ret) {
4089                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4090                 return ret;
4091         }
4092
4093         /*
4094          * In some case, the speed of MAC obtained from firmware may be 0, it
4095          * shouldn't be set to mac->speed.
4096          */
4097         if (!rte_le_to_cpu_32(resp->sfp_speed))
4098                 return 0;
4099
4100         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4101         /*
4102          * if resp->supported_speed is 0, it means it's an old version
4103          * firmware, do not update these params.
4104          */
4105         if (resp->supported_speed) {
4106                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4107                 mac_info->supported_speed =
4108                                         rte_le_to_cpu_32(resp->supported_speed);
4109                 mac_info->support_autoneg = resp->autoneg_ability;
4110                 mac_info->link_autoneg = (resp->autoneg == 0) ? RTE_ETH_LINK_FIXED
4111                                         : RTE_ETH_LINK_AUTONEG;
4112         } else {
4113                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4114         }
4115
4116         return 0;
4117 }
4118
4119 static uint8_t
4120 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4121 {
4122         if (!(speed == RTE_ETH_SPEED_NUM_10M || speed == RTE_ETH_SPEED_NUM_100M))
4123                 duplex = RTE_ETH_LINK_FULL_DUPLEX;
4124
4125         return duplex;
4126 }
4127
4128 static int
4129 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4130 {
4131         struct hns3_mac *mac = &hw->mac;
4132         int ret;
4133
4134         duplex = hns3_check_speed_dup(duplex, speed);
4135         if (mac->link_speed == speed && mac->link_duplex == duplex)
4136                 return 0;
4137
4138         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4139         if (ret)
4140                 return ret;
4141
4142         ret = hns3_port_shaper_update(hw, speed);
4143         if (ret)
4144                 return ret;
4145
4146         mac->link_speed = speed;
4147         mac->link_duplex = duplex;
4148
4149         return 0;
4150 }
4151
4152 static int
4153 hns3_update_fiber_link_info(struct hns3_hw *hw)
4154 {
4155         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4156         struct hns3_mac *mac = &hw->mac;
4157         struct hns3_mac mac_info;
4158         int ret;
4159
4160         /* If firmware do not support get SFP/qSFP speed, return directly */
4161         if (!pf->support_sfp_query)
4162                 return 0;
4163
4164         memset(&mac_info, 0, sizeof(struct hns3_mac));
4165         ret = hns3_get_sfp_info(hw, &mac_info);
4166         if (ret == -EOPNOTSUPP) {
4167                 pf->support_sfp_query = false;
4168                 return ret;
4169         } else if (ret)
4170                 return ret;
4171
4172         /* Do nothing if no SFP */
4173         if (mac_info.link_speed == RTE_ETH_SPEED_NUM_NONE)
4174                 return 0;
4175
4176         /*
4177          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4178          * to reconfigure the speed of MAC. Otherwise, it indicates
4179          * that the current firmware only supports to obtain the
4180          * speed of the SFP, and the speed of MAC needs to reconfigure.
4181          */
4182         mac->query_type = mac_info.query_type;
4183         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4184                 if (mac_info.link_speed != mac->link_speed) {
4185                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4186                         if (ret)
4187                                 return ret;
4188                 }
4189
4190                 mac->link_speed = mac_info.link_speed;
4191                 mac->supported_speed = mac_info.supported_speed;
4192                 mac->support_autoneg = mac_info.support_autoneg;
4193                 mac->link_autoneg = mac_info.link_autoneg;
4194
4195                 return 0;
4196         }
4197
4198         /* Config full duplex for SFP */
4199         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4200                                       RTE_ETH_LINK_FULL_DUPLEX);
4201 }
4202
4203 static void
4204 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4205 {
4206 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4207
4208         struct hns3_phy_params_bd0_cmd *req;
4209         uint32_t supported;
4210
4211         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4212         mac->link_speed = rte_le_to_cpu_32(req->speed);
4213         mac->link_duplex = hns3_get_bit(req->duplex,
4214                                            HNS3_PHY_DUPLEX_CFG_B);
4215         mac->link_autoneg = hns3_get_bit(req->autoneg,
4216                                            HNS3_PHY_AUTONEG_CFG_B);
4217         mac->advertising = rte_le_to_cpu_32(req->advertising);
4218         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4219         supported = rte_le_to_cpu_32(req->supported);
4220         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4221         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4222 }
4223
4224 static int
4225 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4226 {
4227         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4228         uint16_t i;
4229         int ret;
4230
4231         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4232                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4233                                           true);
4234                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4235         }
4236         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4237
4238         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4239         if (ret) {
4240                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4241                 return ret;
4242         }
4243
4244         hns3_parse_copper_phy_params(desc, mac);
4245
4246         return 0;
4247 }
4248
4249 static int
4250 hns3_update_copper_link_info(struct hns3_hw *hw)
4251 {
4252         struct hns3_mac *mac = &hw->mac;
4253         struct hns3_mac mac_info;
4254         int ret;
4255
4256         memset(&mac_info, 0, sizeof(struct hns3_mac));
4257         ret = hns3_get_copper_phy_params(hw, &mac_info);
4258         if (ret)
4259                 return ret;
4260
4261         if (mac_info.link_speed != mac->link_speed) {
4262                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4263                 if (ret)
4264                         return ret;
4265         }
4266
4267         mac->link_speed = mac_info.link_speed;
4268         mac->link_duplex = mac_info.link_duplex;
4269         mac->link_autoneg = mac_info.link_autoneg;
4270         mac->supported_speed = mac_info.supported_speed;
4271         mac->advertising = mac_info.advertising;
4272         mac->lp_advertising = mac_info.lp_advertising;
4273         mac->support_autoneg = mac_info.support_autoneg;
4274
4275         return 0;
4276 }
4277
4278 static int
4279 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4280 {
4281         struct hns3_adapter *hns = eth_dev->data->dev_private;
4282         struct hns3_hw *hw = &hns->hw;
4283         int ret = 0;
4284
4285         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4286                 ret = hns3_update_copper_link_info(hw);
4287         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4288                 ret = hns3_update_fiber_link_info(hw);
4289
4290         return ret;
4291 }
4292
4293 static int
4294 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4295 {
4296         struct hns3_config_mac_mode_cmd *req;
4297         struct hns3_cmd_desc desc;
4298         uint32_t loop_en = 0;
4299         uint8_t val = 0;
4300         int ret;
4301
4302         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4303
4304         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4305         if (enable)
4306                 val = 1;
4307         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4308         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4309         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4310         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4311         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4312         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4313         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4314         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4315         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4316         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4317
4318         /*
4319          * If RTE_ETH_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4320          * when receiving frames. Otherwise, CRC will be stripped.
4321          */
4322         if (hw->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
4323                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4324         else
4325                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4326         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4327         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4328         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4329         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4330
4331         ret = hns3_cmd_send(hw, &desc, 1);
4332         if (ret)
4333                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4334
4335         return ret;
4336 }
4337
4338 static int
4339 hns3_get_mac_link_status(struct hns3_hw *hw)
4340 {
4341         struct hns3_link_status_cmd *req;
4342         struct hns3_cmd_desc desc;
4343         int link_status;
4344         int ret;
4345
4346         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4347         ret = hns3_cmd_send(hw, &desc, 1);
4348         if (ret) {
4349                 hns3_err(hw, "get link status cmd failed %d", ret);
4350                 return RTE_ETH_LINK_DOWN;
4351         }
4352
4353         req = (struct hns3_link_status_cmd *)desc.data;
4354         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4355
4356         return !!link_status;
4357 }
4358
4359 static bool
4360 hns3_update_link_status(struct hns3_hw *hw)
4361 {
4362         int state;
4363
4364         state = hns3_get_mac_link_status(hw);
4365         if (state != hw->mac.link_status) {
4366                 hw->mac.link_status = state;
4367                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4368                 return true;
4369         }
4370
4371         return false;
4372 }
4373
4374 void
4375 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4376 {
4377         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4378         struct rte_eth_link new_link;
4379         int ret;
4380
4381         if (query)
4382                 hns3_update_port_link_info(dev);
4383
4384         memset(&new_link, 0, sizeof(new_link));
4385         hns3_setup_linkstatus(dev, &new_link);
4386
4387         ret = rte_eth_linkstatus_set(dev, &new_link);
4388         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4389                 hns3_start_report_lse(dev);
4390 }
4391
4392 static void
4393 hns3_service_handler(void *param)
4394 {
4395         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4396         struct hns3_adapter *hns = eth_dev->data->dev_private;
4397         struct hns3_hw *hw = &hns->hw;
4398
4399         if (!hns3_is_reset_pending(hns))
4400                 hns3_update_linkstatus_and_event(hw, true);
4401         else
4402                 hns3_warn(hw, "Cancel the query when reset is pending");
4403
4404         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4405 }
4406
4407 static int
4408 hns3_init_hardware(struct hns3_adapter *hns)
4409 {
4410         struct hns3_hw *hw = &hns->hw;
4411         int ret;
4412
4413         ret = hns3_map_tqp(hw);
4414         if (ret) {
4415                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4416                 return ret;
4417         }
4418
4419         ret = hns3_init_umv_space(hw);
4420         if (ret) {
4421                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4422                 return ret;
4423         }
4424
4425         ret = hns3_mac_init(hw);
4426         if (ret) {
4427                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4428                 goto err_mac_init;
4429         }
4430
4431         ret = hns3_init_mgr_tbl(hw);
4432         if (ret) {
4433                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4434                 goto err_mac_init;
4435         }
4436
4437         ret = hns3_promisc_init(hw);
4438         if (ret) {
4439                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4440                              ret);
4441                 goto err_mac_init;
4442         }
4443
4444         ret = hns3_init_vlan_config(hns);
4445         if (ret) {
4446                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4447                 goto err_mac_init;
4448         }
4449
4450         ret = hns3_dcb_init(hw);
4451         if (ret) {
4452                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4453                 goto err_mac_init;
4454         }
4455
4456         ret = hns3_init_fd_config(hns);
4457         if (ret) {
4458                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4459                 goto err_mac_init;
4460         }
4461
4462         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4463         if (ret) {
4464                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4465                 goto err_mac_init;
4466         }
4467
4468         ret = hns3_config_gro(hw, false);
4469         if (ret) {
4470                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4471                 goto err_mac_init;
4472         }
4473
4474         /*
4475          * In the initialization clearing the all hardware mapping relationship
4476          * configurations between queues and interrupt vectors is needed, so
4477          * some error caused by the residual configurations, such as the
4478          * unexpected interrupt, can be avoid.
4479          */
4480         ret = hns3_init_ring_with_vector(hw);
4481         if (ret) {
4482                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4483                 goto err_mac_init;
4484         }
4485
4486         return 0;
4487
4488 err_mac_init:
4489         hns3_uninit_umv_space(hw);
4490         return ret;
4491 }
4492
4493 static int
4494 hns3_clear_hw(struct hns3_hw *hw)
4495 {
4496         struct hns3_cmd_desc desc;
4497         int ret;
4498
4499         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4500
4501         ret = hns3_cmd_send(hw, &desc, 1);
4502         if (ret && ret != -EOPNOTSUPP)
4503                 return ret;
4504
4505         return 0;
4506 }
4507
4508 static void
4509 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4510 {
4511         uint32_t val;
4512
4513         /*
4514          * The new firmware support report more hardware error types by
4515          * msix mode. These errors are defined as RAS errors in hardware
4516          * and belong to a different type from the MSI-x errors processed
4517          * by the network driver.
4518          *
4519          * Network driver should open the new error report on initialization.
4520          */
4521         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4522         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
4523         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
4524 }
4525
4526 static uint32_t
4527 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
4528 {
4529         struct hns3_mac *mac = &hw->mac;
4530
4531         switch (mac->link_speed) {
4532         case RTE_ETH_SPEED_NUM_1G:
4533                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
4534         case RTE_ETH_SPEED_NUM_10G:
4535                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
4536         case RTE_ETH_SPEED_NUM_25G:
4537                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
4538         case RTE_ETH_SPEED_NUM_40G:
4539                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
4540         case RTE_ETH_SPEED_NUM_50G:
4541                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
4542         case RTE_ETH_SPEED_NUM_100G:
4543                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
4544         case RTE_ETH_SPEED_NUM_200G:
4545                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
4546         default:
4547                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
4548                 return 0;
4549         }
4550 }
4551
4552 /*
4553  * Validity of supported_speed for firber and copper media type can be
4554  * guaranteed by the following policy:
4555  * Copper:
4556  *       Although the initialization of the phy in the firmware may not be
4557  *       completed, the firmware can guarantees that the supported_speed is
4558  *       an valid value.
4559  * Firber:
4560  *       If the version of firmware supports the acitive query way of the
4561  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
4562  *       through it. If unsupported, use the SFP's speed as the value of the
4563  *       supported_speed.
4564  */
4565 static int
4566 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
4567 {
4568         struct hns3_adapter *hns = eth_dev->data->dev_private;
4569         struct hns3_hw *hw = &hns->hw;
4570         struct hns3_mac *mac = &hw->mac;
4571         int ret;
4572
4573         ret = hns3_update_link_info(eth_dev);
4574         if (ret)
4575                 return ret;
4576
4577         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
4578                 /*
4579                  * Some firmware does not support the report of supported_speed,
4580                  * and only report the effective speed of SFP. In this case, it
4581                  * is necessary to use the SFP's speed as the supported_speed.
4582                  */
4583                 if (mac->supported_speed == 0)
4584                         mac->supported_speed =
4585                                 hns3_set_firber_default_support_speed(hw);
4586         }
4587
4588         return 0;
4589 }
4590
4591 static void
4592 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
4593 {
4594         struct hns3_mac *mac = &hns->hw.mac;
4595
4596         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
4597                 hns->pf.support_fc_autoneg = true;
4598                 return;
4599         }
4600
4601         /*
4602          * Flow control auto-negotiation requires the cooperation of the driver
4603          * and firmware. Currently, the optical port does not support flow
4604          * control auto-negotiation.
4605          */
4606         hns->pf.support_fc_autoneg = false;
4607 }
4608
4609 static int
4610 hns3_init_pf(struct rte_eth_dev *eth_dev)
4611 {
4612         struct rte_device *dev = eth_dev->device;
4613         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4614         struct hns3_adapter *hns = eth_dev->data->dev_private;
4615         struct hns3_hw *hw = &hns->hw;
4616         int ret;
4617
4618         PMD_INIT_FUNC_TRACE();
4619
4620         /* Get hardware io base address from pcie BAR2 IO space */
4621         hw->io_base = pci_dev->mem_resource[2].addr;
4622
4623         /* Firmware command queue initialize */
4624         ret = hns3_cmd_init_queue(hw);
4625         if (ret) {
4626                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4627                 goto err_cmd_init_queue;
4628         }
4629
4630         hns3_clear_all_event_cause(hw);
4631
4632         /* Firmware command initialize */
4633         ret = hns3_cmd_init(hw);
4634         if (ret) {
4635                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4636                 goto err_cmd_init;
4637         }
4638
4639         hns3_tx_push_init(eth_dev);
4640
4641         /*
4642          * To ensure that the hardware environment is clean during
4643          * initialization, the driver actively clear the hardware environment
4644          * during initialization, including PF and corresponding VFs' vlan, mac,
4645          * flow table configurations, etc.
4646          */
4647         ret = hns3_clear_hw(hw);
4648         if (ret) {
4649                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
4650                 goto err_cmd_init;
4651         }
4652
4653         /* Hardware statistics of imissed registers cleared. */
4654         ret = hns3_update_imissed_stats(hw, true);
4655         if (ret) {
4656                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
4657                 goto err_cmd_init;
4658         }
4659
4660         hns3_config_all_msix_error(hw, true);
4661
4662         ret = rte_intr_callback_register(pci_dev->intr_handle,
4663                                          hns3_interrupt_handler,
4664                                          eth_dev);
4665         if (ret) {
4666                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4667                 goto err_intr_callback_register;
4668         }
4669
4670         ret = hns3_ptp_init(hw);
4671         if (ret)
4672                 goto err_get_config;
4673
4674         /* Enable interrupt */
4675         rte_intr_enable(pci_dev->intr_handle);
4676         hns3_pf_enable_irq0(hw);
4677
4678         /* Get configuration */
4679         ret = hns3_get_configuration(hw);
4680         if (ret) {
4681                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4682                 goto err_get_config;
4683         }
4684
4685         ret = hns3_tqp_stats_init(hw);
4686         if (ret)
4687                 goto err_get_config;
4688
4689         ret = hns3_init_hardware(hns);
4690         if (ret) {
4691                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4692                 goto err_init_hw;
4693         }
4694
4695         /* Initialize flow director filter list & hash */
4696         ret = hns3_fdir_filter_init(hns);
4697         if (ret) {
4698                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4699                 goto err_fdir;
4700         }
4701
4702         hns3_rss_set_default_args(hw);
4703
4704         ret = hns3_enable_hw_error_intr(hns, true);
4705         if (ret) {
4706                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4707                              ret);
4708                 goto err_enable_intr;
4709         }
4710
4711         ret = hns3_get_port_supported_speed(eth_dev);
4712         if (ret) {
4713                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
4714                              "by device, ret = %d.", ret);
4715                 goto err_supported_speed;
4716         }
4717
4718         hns3_get_fc_autoneg_capability(hns);
4719
4720         hns3_tm_conf_init(eth_dev);
4721
4722         return 0;
4723
4724 err_supported_speed:
4725         (void)hns3_enable_hw_error_intr(hns, false);
4726 err_enable_intr:
4727         hns3_fdir_filter_uninit(hns);
4728 err_fdir:
4729         hns3_uninit_umv_space(hw);
4730 err_init_hw:
4731         hns3_tqp_stats_uninit(hw);
4732 err_get_config:
4733         hns3_pf_disable_irq0(hw);
4734         rte_intr_disable(pci_dev->intr_handle);
4735         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4736                              eth_dev);
4737 err_intr_callback_register:
4738 err_cmd_init:
4739         hns3_cmd_uninit(hw);
4740         hns3_cmd_destroy_queue(hw);
4741 err_cmd_init_queue:
4742         hw->io_base = NULL;
4743
4744         return ret;
4745 }
4746
4747 static void
4748 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4749 {
4750         struct hns3_adapter *hns = eth_dev->data->dev_private;
4751         struct rte_device *dev = eth_dev->device;
4752         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4753         struct hns3_hw *hw = &hns->hw;
4754
4755         PMD_INIT_FUNC_TRACE();
4756
4757         hns3_tm_conf_uninit(eth_dev);
4758         hns3_enable_hw_error_intr(hns, false);
4759         hns3_rss_uninit(hns);
4760         (void)hns3_config_gro(hw, false);
4761         hns3_promisc_uninit(hw);
4762         hns3_flow_uninit(eth_dev);
4763         hns3_fdir_filter_uninit(hns);
4764         hns3_uninit_umv_space(hw);
4765         hns3_tqp_stats_uninit(hw);
4766         hns3_config_mac_tnl_int(hw, false);
4767         hns3_pf_disable_irq0(hw);
4768         rte_intr_disable(pci_dev->intr_handle);
4769         hns3_intr_unregister(pci_dev->intr_handle, hns3_interrupt_handler,
4770                              eth_dev);
4771         hns3_config_all_msix_error(hw, false);
4772         hns3_cmd_uninit(hw);
4773         hns3_cmd_destroy_queue(hw);
4774         hw->io_base = NULL;
4775 }
4776
4777 static uint32_t
4778 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
4779 {
4780         uint32_t speed_bit;
4781
4782         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4783         case RTE_ETH_LINK_SPEED_10M:
4784                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
4785                 break;
4786         case RTE_ETH_LINK_SPEED_10M_HD:
4787                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
4788                 break;
4789         case RTE_ETH_LINK_SPEED_100M:
4790                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
4791                 break;
4792         case RTE_ETH_LINK_SPEED_100M_HD:
4793                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
4794                 break;
4795         case RTE_ETH_LINK_SPEED_1G:
4796                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
4797                 break;
4798         default:
4799                 speed_bit = 0;
4800                 break;
4801         }
4802
4803         return speed_bit;
4804 }
4805
4806 static uint32_t
4807 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
4808 {
4809         uint32_t speed_bit;
4810
4811         switch (link_speeds & ~RTE_ETH_LINK_SPEED_FIXED) {
4812         case RTE_ETH_LINK_SPEED_1G:
4813                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
4814                 break;
4815         case RTE_ETH_LINK_SPEED_10G:
4816                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
4817                 break;
4818         case RTE_ETH_LINK_SPEED_25G:
4819                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
4820                 break;
4821         case RTE_ETH_LINK_SPEED_40G:
4822                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
4823                 break;
4824         case RTE_ETH_LINK_SPEED_50G:
4825                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
4826                 break;
4827         case RTE_ETH_LINK_SPEED_100G:
4828                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
4829                 break;
4830         case RTE_ETH_LINK_SPEED_200G:
4831                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
4832                 break;
4833         default:
4834                 speed_bit = 0;
4835                 break;
4836         }
4837
4838         return speed_bit;
4839 }
4840
4841 static int
4842 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
4843 {
4844         struct hns3_mac *mac = &hw->mac;
4845         uint32_t supported_speed = mac->supported_speed;
4846         uint32_t speed_bit = 0;
4847
4848         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
4849                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
4850         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
4851                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
4852
4853         if (!(speed_bit & supported_speed)) {
4854                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
4855                          link_speeds);
4856                 return -EINVAL;
4857         }
4858
4859         return 0;
4860 }
4861
4862 static inline uint32_t
4863 hns3_get_link_speed(uint32_t link_speeds)
4864 {
4865         uint32_t speed = RTE_ETH_SPEED_NUM_NONE;
4866
4867         if (link_speeds & RTE_ETH_LINK_SPEED_10M ||
4868             link_speeds & RTE_ETH_LINK_SPEED_10M_HD)
4869                 speed = RTE_ETH_SPEED_NUM_10M;
4870         if (link_speeds & RTE_ETH_LINK_SPEED_100M ||
4871             link_speeds & RTE_ETH_LINK_SPEED_100M_HD)
4872                 speed = RTE_ETH_SPEED_NUM_100M;
4873         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
4874                 speed = RTE_ETH_SPEED_NUM_1G;
4875         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
4876                 speed = RTE_ETH_SPEED_NUM_10G;
4877         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
4878                 speed = RTE_ETH_SPEED_NUM_25G;
4879         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
4880                 speed = RTE_ETH_SPEED_NUM_40G;
4881         if (link_speeds & RTE_ETH_LINK_SPEED_50G)
4882                 speed = RTE_ETH_SPEED_NUM_50G;
4883         if (link_speeds & RTE_ETH_LINK_SPEED_100G)
4884                 speed = RTE_ETH_SPEED_NUM_100G;
4885         if (link_speeds & RTE_ETH_LINK_SPEED_200G)
4886                 speed = RTE_ETH_SPEED_NUM_200G;
4887
4888         return speed;
4889 }
4890
4891 static uint8_t
4892 hns3_get_link_duplex(uint32_t link_speeds)
4893 {
4894         if ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||
4895             (link_speeds & RTE_ETH_LINK_SPEED_100M_HD))
4896                 return RTE_ETH_LINK_HALF_DUPLEX;
4897         else
4898                 return RTE_ETH_LINK_FULL_DUPLEX;
4899 }
4900
4901 static int
4902 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
4903                                 struct hns3_set_link_speed_cfg *cfg)
4904 {
4905         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4906         struct hns3_phy_params_bd0_cmd *req;
4907         uint16_t i;
4908
4909         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4910                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4911                                           false);
4912                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4913         }
4914         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
4915         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4916         req->autoneg = cfg->autoneg;
4917
4918         /*
4919          * The full speed capability is used to negotiate when
4920          * auto-negotiation is enabled.
4921          */
4922         if (cfg->autoneg) {
4923                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
4924                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
4925                                     HNS3_PHY_LINK_SPEED_100M_BIT |
4926                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
4927                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
4928         } else {
4929                 req->speed = cfg->speed;
4930                 req->duplex = cfg->duplex;
4931         }
4932
4933         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4934 }
4935
4936 static int
4937 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
4938 {
4939         struct hns3_config_auto_neg_cmd *req;
4940         struct hns3_cmd_desc desc;
4941         uint32_t flag = 0;
4942         int ret;
4943
4944         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
4945
4946         req = (struct hns3_config_auto_neg_cmd *)desc.data;
4947         if (enable)
4948                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
4949         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
4950
4951         ret = hns3_cmd_send(hw, &desc, 1);
4952         if (ret)
4953                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
4954
4955         return ret;
4956 }
4957
4958 static int
4959 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
4960                                struct hns3_set_link_speed_cfg *cfg)
4961 {
4962         int ret;
4963
4964         if (hw->mac.support_autoneg) {
4965                 ret = hns3_set_autoneg(hw, cfg->autoneg);
4966                 if (ret) {
4967                         hns3_err(hw, "failed to configure auto-negotiation.");
4968                         return ret;
4969                 }
4970
4971                 /*
4972                  * To enable auto-negotiation, we only need to open the switch
4973                  * of auto-negotiation, then firmware sets all speed
4974                  * capabilities.
4975                  */
4976                 if (cfg->autoneg)
4977                         return 0;
4978         }
4979
4980         /*
4981          * Some hardware doesn't support auto-negotiation, but users may not
4982          * configure link_speeds (default 0), which means auto-negotiation.
4983          * In this case, a warning message need to be printed, instead of
4984          * an error.
4985          */
4986         if (cfg->autoneg) {
4987                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
4988                 return 0;
4989         }
4990
4991         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
4992 }
4993
4994 static int
4995 hns3_set_port_link_speed(struct hns3_hw *hw,
4996                          struct hns3_set_link_speed_cfg *cfg)
4997 {
4998         int ret;
4999
5000         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5001 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5002                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5003                 if (pf->is_tmp_phy)
5004                         return 0;
5005 #endif
5006
5007                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5008                 if (ret) {
5009                         hns3_err(hw, "failed to set copper port link speed,"
5010                                  "ret = %d.", ret);
5011                         return ret;
5012                 }
5013         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5014                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5015                 if (ret) {
5016                         hns3_err(hw, "failed to set fiber port link speed,"
5017                                  "ret = %d.", ret);
5018                         return ret;
5019                 }
5020         }
5021
5022         return 0;
5023 }
5024
5025 static int
5026 hns3_apply_link_speed(struct hns3_hw *hw)
5027 {
5028         struct rte_eth_conf *conf = &hw->data->dev_conf;
5029         struct hns3_set_link_speed_cfg cfg;
5030
5031         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5032         cfg.autoneg = (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) ?
5033                         RTE_ETH_LINK_AUTONEG : RTE_ETH_LINK_FIXED;
5034         if (cfg.autoneg != RTE_ETH_LINK_AUTONEG) {
5035                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5036                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5037         }
5038
5039         return hns3_set_port_link_speed(hw, &cfg);
5040 }
5041
5042 static int
5043 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5044 {
5045         struct hns3_hw *hw = &hns->hw;
5046         bool link_en;
5047         int ret;
5048
5049         ret = hns3_update_queue_map_configure(hns);
5050         if (ret) {
5051                 hns3_err(hw, "failed to update queue mapping configuration, ret = %d",
5052                          ret);
5053                 return ret;
5054         }
5055
5056         /* Note: hns3_tm_conf_update must be called after configuring DCB. */
5057         ret = hns3_tm_conf_update(hw);
5058         if (ret) {
5059                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5060                 return ret;
5061         }
5062
5063         hns3_enable_rxd_adv_layout(hw);
5064
5065         ret = hns3_init_queues(hns, reset_queue);
5066         if (ret) {
5067                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5068                 return ret;
5069         }
5070
5071         link_en = hw->set_link_down ? false : true;
5072         ret = hns3_cfg_mac_mode(hw, link_en);
5073         if (ret) {
5074                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5075                 goto err_config_mac_mode;
5076         }
5077
5078         ret = hns3_apply_link_speed(hw);
5079         if (ret)
5080                 goto err_set_link_speed;
5081
5082         return 0;
5083
5084 err_set_link_speed:
5085         (void)hns3_cfg_mac_mode(hw, false);
5086
5087 err_config_mac_mode:
5088         hns3_dev_release_mbufs(hns);
5089         /*
5090          * Here is exception handling, hns3_reset_all_tqps will have the
5091          * corresponding error message if it is handled incorrectly, so it is
5092          * not necessary to check hns3_reset_all_tqps return value, here keep
5093          * ret as the error code causing the exception.
5094          */
5095         (void)hns3_reset_all_tqps(hns);
5096         return ret;
5097 }
5098
5099 static void
5100 hns3_restore_filter(struct rte_eth_dev *dev)
5101 {
5102         hns3_restore_rss_filter(dev);
5103 }
5104
5105 static int
5106 hns3_dev_start(struct rte_eth_dev *dev)
5107 {
5108         struct hns3_adapter *hns = dev->data->dev_private;
5109         struct hns3_hw *hw = &hns->hw;
5110         bool old_state = hw->set_link_down;
5111         int ret;
5112
5113         PMD_INIT_FUNC_TRACE();
5114         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5115                 return -EBUSY;
5116
5117         rte_spinlock_lock(&hw->lock);
5118         hw->adapter_state = HNS3_NIC_STARTING;
5119
5120         /*
5121          * If the dev_set_link_down() API has been called, the "set_link_down"
5122          * flag can be cleared by dev_start() API. In addition, the flag should
5123          * also be cleared before calling hns3_do_start() so that MAC can be
5124          * enabled in dev_start stage.
5125          */
5126         hw->set_link_down = false;
5127         ret = hns3_do_start(hns, true);
5128         if (ret)
5129                 goto do_start_fail;
5130
5131         ret = hns3_map_rx_interrupt(dev);
5132         if (ret)
5133                 goto map_rx_inter_err;
5134
5135         /*
5136          * There are three register used to control the status of a TQP
5137          * (contains a pair of Tx queue and Rx queue) in the new version network
5138          * engine. One is used to control the enabling of Tx queue, the other is
5139          * used to control the enabling of Rx queue, and the last is the master
5140          * switch used to control the enabling of the tqp. The Tx register and
5141          * TQP register must be enabled at the same time to enable a Tx queue.
5142          * The same applies to the Rx queue. For the older network engine, this
5143          * function only refresh the enabled flag, and it is used to update the
5144          * status of queue in the dpdk framework.
5145          */
5146         ret = hns3_start_all_txqs(dev);
5147         if (ret)
5148                 goto map_rx_inter_err;
5149
5150         ret = hns3_start_all_rxqs(dev);
5151         if (ret)
5152                 goto start_all_rxqs_fail;
5153
5154         hw->adapter_state = HNS3_NIC_STARTED;
5155         rte_spinlock_unlock(&hw->lock);
5156
5157         hns3_rx_scattered_calc(dev);
5158         hns3_set_rxtx_function(dev);
5159         hns3_mp_req_start_rxtx(dev);
5160
5161         hns3_restore_filter(dev);
5162
5163         /* Enable interrupt of all rx queues before enabling queues */
5164         hns3_dev_all_rx_queue_intr_enable(hw, true);
5165
5166         /*
5167          * After finished the initialization, enable tqps to receive/transmit
5168          * packets and refresh all queue status.
5169          */
5170         hns3_start_tqps(hw);
5171
5172         hns3_tm_dev_start_proc(hw);
5173
5174         if (dev->data->dev_conf.intr_conf.lsc != 0)
5175                 hns3_dev_link_update(dev, 0);
5176         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5177
5178         hns3_info(hw, "hns3 dev start successful!");
5179
5180         return 0;
5181
5182 start_all_rxqs_fail:
5183         hns3_stop_all_txqs(dev);
5184 map_rx_inter_err:
5185         (void)hns3_do_stop(hns);
5186 do_start_fail:
5187         hw->set_link_down = old_state;
5188         hw->adapter_state = HNS3_NIC_CONFIGURED;
5189         rte_spinlock_unlock(&hw->lock);
5190
5191         return ret;
5192 }
5193
5194 static int
5195 hns3_do_stop(struct hns3_adapter *hns)
5196 {
5197         struct hns3_hw *hw = &hns->hw;
5198         int ret;
5199
5200         /*
5201          * The "hns3_do_stop" function will also be called by .stop_service to
5202          * prepare reset. At the time of global or IMP reset, the command cannot
5203          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5204          * accessed during the reset process. So the mbuf can not be released
5205          * during reset and is required to be released after the reset is
5206          * completed.
5207          */
5208         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5209                 hns3_dev_release_mbufs(hns);
5210
5211         ret = hns3_cfg_mac_mode(hw, false);
5212         if (ret)
5213                 return ret;
5214         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5215
5216         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5217                 hns3_configure_all_mac_addr(hns, true);
5218                 ret = hns3_reset_all_tqps(hns);
5219                 if (ret) {
5220                         hns3_err(hw, "failed to reset all queues ret = %d.",
5221                                  ret);
5222                         return ret;
5223                 }
5224         }
5225
5226         return 0;
5227 }
5228
5229 static int
5230 hns3_dev_stop(struct rte_eth_dev *dev)
5231 {
5232         struct hns3_adapter *hns = dev->data->dev_private;
5233         struct hns3_hw *hw = &hns->hw;
5234
5235         PMD_INIT_FUNC_TRACE();
5236         dev->data->dev_started = 0;
5237
5238         hw->adapter_state = HNS3_NIC_STOPPING;
5239         hns3_set_rxtx_function(dev);
5240         rte_wmb();
5241         /* Disable datapath on secondary process. */
5242         hns3_mp_req_stop_rxtx(dev);
5243         /* Prevent crashes when queues are still in use. */
5244         rte_delay_ms(hw->cfg_max_queues);
5245
5246         rte_spinlock_lock(&hw->lock);
5247         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5248                 hns3_tm_dev_stop_proc(hw);
5249                 hns3_config_mac_tnl_int(hw, false);
5250                 hns3_stop_tqps(hw);
5251                 hns3_do_stop(hns);
5252                 hns3_unmap_rx_interrupt(dev);
5253                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5254         }
5255         hns3_rx_scattered_reset(dev);
5256         rte_eal_alarm_cancel(hns3_service_handler, dev);
5257         hns3_stop_report_lse(dev);
5258         rte_spinlock_unlock(&hw->lock);
5259
5260         return 0;
5261 }
5262
5263 static int
5264 hns3_dev_close(struct rte_eth_dev *eth_dev)
5265 {
5266         struct hns3_adapter *hns = eth_dev->data->dev_private;
5267         struct hns3_hw *hw = &hns->hw;
5268         int ret = 0;
5269
5270         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5271                 hns3_mp_uninit(eth_dev);
5272                 return 0;
5273         }
5274
5275         if (hw->adapter_state == HNS3_NIC_STARTED)
5276                 ret = hns3_dev_stop(eth_dev);
5277
5278         hw->adapter_state = HNS3_NIC_CLOSING;
5279         hns3_reset_abort(hns);
5280         hw->adapter_state = HNS3_NIC_CLOSED;
5281
5282         hns3_configure_all_mc_mac_addr(hns, true);
5283         hns3_remove_all_vlan_table(hns);
5284         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5285         hns3_uninit_pf(eth_dev);
5286         hns3_free_all_queues(eth_dev);
5287         rte_free(hw->reset.wait_data);
5288         hns3_mp_uninit(eth_dev);
5289         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5290
5291         return ret;
5292 }
5293
5294 static void
5295 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5296                                    bool *tx_pause)
5297 {
5298         struct hns3_mac *mac = &hw->mac;
5299         uint32_t advertising = mac->advertising;
5300         uint32_t lp_advertising = mac->lp_advertising;
5301         *rx_pause = false;
5302         *tx_pause = false;
5303
5304         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5305                 *rx_pause = true;
5306                 *tx_pause = true;
5307         } else if (advertising & lp_advertising &
5308                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5309                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5310                         *rx_pause = true;
5311                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5312                         *tx_pause = true;
5313         }
5314 }
5315
5316 static enum hns3_fc_mode
5317 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5318 {
5319         enum hns3_fc_mode current_mode;
5320         bool rx_pause = false;
5321         bool tx_pause = false;
5322
5323         switch (hw->mac.media_type) {
5324         case HNS3_MEDIA_TYPE_COPPER:
5325                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5326                 break;
5327
5328         /*
5329          * Flow control auto-negotiation is not supported for fiber and
5330          * backpalne media type.
5331          */
5332         case HNS3_MEDIA_TYPE_FIBER:
5333         case HNS3_MEDIA_TYPE_BACKPLANE:
5334                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5335                 current_mode = hw->requested_fc_mode;
5336                 goto out;
5337         default:
5338                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5339                          hw->mac.media_type);
5340                 current_mode = HNS3_FC_NONE;
5341                 goto out;
5342         }
5343
5344         if (rx_pause && tx_pause)
5345                 current_mode = HNS3_FC_FULL;
5346         else if (rx_pause)
5347                 current_mode = HNS3_FC_RX_PAUSE;
5348         else if (tx_pause)
5349                 current_mode = HNS3_FC_TX_PAUSE;
5350         else
5351                 current_mode = HNS3_FC_NONE;
5352
5353 out:
5354         return current_mode;
5355 }
5356
5357 static enum hns3_fc_mode
5358 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5359 {
5360         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5361         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5362         struct hns3_mac *mac = &hw->mac;
5363
5364         /*
5365          * When the flow control mode is obtained, the device may not complete
5366          * auto-negotiation. It is necessary to wait for link establishment.
5367          */
5368         (void)hns3_dev_link_update(dev, 1);
5369
5370         /*
5371          * If the link auto-negotiation of the nic is disabled, or the flow
5372          * control auto-negotiation is not supported, the forced flow control
5373          * mode is used.
5374          */
5375         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5376                 return hw->requested_fc_mode;
5377
5378         return hns3_get_autoneg_fc_mode(hw);
5379 }
5380
5381 static int
5382 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5383 {
5384         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5385         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5386         enum hns3_fc_mode current_mode;
5387
5388         current_mode = hns3_get_current_fc_mode(dev);
5389         switch (current_mode) {
5390         case HNS3_FC_FULL:
5391                 fc_conf->mode = RTE_ETH_FC_FULL;
5392                 break;
5393         case HNS3_FC_TX_PAUSE:
5394                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
5395                 break;
5396         case HNS3_FC_RX_PAUSE:
5397                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
5398                 break;
5399         case HNS3_FC_NONE:
5400         default:
5401                 fc_conf->mode = RTE_ETH_FC_NONE;
5402                 break;
5403         }
5404
5405         fc_conf->pause_time = pf->pause_time;
5406         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
5407
5408         return 0;
5409 }
5410
5411 static int
5412 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
5413 {
5414         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5415
5416         if (!pf->support_fc_autoneg) {
5417                 if (autoneg != 0) {
5418                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
5419                         return -EOPNOTSUPP;
5420                 }
5421
5422                 /*
5423                  * Flow control auto-negotiation of the NIC is not supported,
5424                  * but other auto-negotiation features may be supported.
5425                  */
5426                 if (autoneg != hw->mac.link_autoneg) {
5427                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
5428                         return -EOPNOTSUPP;
5429                 }
5430
5431                 return 0;
5432         }
5433
5434         /*
5435          * If flow control auto-negotiation of the NIC is supported, all
5436          * auto-negotiation features are supported.
5437          */
5438         if (autoneg != hw->mac.link_autoneg) {
5439                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
5440                 return -EOPNOTSUPP;
5441         }
5442
5443         return 0;
5444 }
5445
5446 static int
5447 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5448 {
5449         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5451         int ret;
5452
5453         if (fc_conf->high_water || fc_conf->low_water ||
5454             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
5455                 hns3_err(hw, "Unsupported flow control settings specified, "
5456                          "high_water(%u), low_water(%u), send_xon(%u) and "
5457                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5458                          fc_conf->high_water, fc_conf->low_water,
5459                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
5460                 return -EINVAL;
5461         }
5462
5463         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
5464         if (ret)
5465                 return ret;
5466
5467         if (!fc_conf->pause_time) {
5468                 hns3_err(hw, "Invalid pause time %u setting.",
5469                          fc_conf->pause_time);
5470                 return -EINVAL;
5471         }
5472
5473         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5474             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
5475                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
5476                          "current_fc_status = %d", hw->current_fc_status);
5477                 return -EOPNOTSUPP;
5478         }
5479
5480         if (hw->num_tc > 1 && !pf->support_multi_tc_pause) {
5481                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
5482                 return -EOPNOTSUPP;
5483         }
5484
5485         rte_spinlock_lock(&hw->lock);
5486         ret = hns3_fc_enable(dev, fc_conf);
5487         rte_spinlock_unlock(&hw->lock);
5488
5489         return ret;
5490 }
5491
5492 static int
5493 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
5494                             struct rte_eth_pfc_conf *pfc_conf)
5495 {
5496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5497         int ret;
5498
5499         if (!hns3_dev_get_support(hw, DCB)) {
5500                 hns3_err(hw, "This port does not support dcb configurations.");
5501                 return -EOPNOTSUPP;
5502         }
5503
5504         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
5505             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
5506                 hns3_err(hw, "Unsupported flow control settings specified, "
5507                          "high_water(%u), low_water(%u), send_xon(%u) and "
5508                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
5509                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
5510                          pfc_conf->fc.send_xon,
5511                          pfc_conf->fc.mac_ctrl_frame_fwd);
5512                 return -EINVAL;
5513         }
5514         if (pfc_conf->fc.autoneg) {
5515                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
5516                 return -EINVAL;
5517         }
5518         if (pfc_conf->fc.pause_time == 0) {
5519                 hns3_err(hw, "Invalid pause time %u setting.",
5520                          pfc_conf->fc.pause_time);
5521                 return -EINVAL;
5522         }
5523
5524         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
5525             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
5526                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
5527                              "current_fc_status = %d", hw->current_fc_status);
5528                 return -EOPNOTSUPP;
5529         }
5530
5531         rte_spinlock_lock(&hw->lock);
5532         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
5533         rte_spinlock_unlock(&hw->lock);
5534
5535         return ret;
5536 }
5537
5538 static int
5539 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
5540 {
5541         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5543         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
5544         int i;
5545
5546         rte_spinlock_lock(&hw->lock);
5547         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
5548                 dcb_info->nb_tcs = pf->local_max_tc;
5549         else
5550                 dcb_info->nb_tcs = 1;
5551
5552         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
5553                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
5554         for (i = 0; i < dcb_info->nb_tcs; i++)
5555                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
5556
5557         for (i = 0; i < hw->num_tc; i++) {
5558                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
5559                 dcb_info->tc_queue.tc_txq[0][i].base =
5560                                                 hw->tc_queue[i].tqp_offset;
5561                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
5562                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
5563                                                 hw->tc_queue[i].tqp_count;
5564         }
5565         rte_spinlock_unlock(&hw->lock);
5566
5567         return 0;
5568 }
5569
5570 static int
5571 hns3_reinit_dev(struct hns3_adapter *hns)
5572 {
5573         struct hns3_hw *hw = &hns->hw;
5574         int ret;
5575
5576         ret = hns3_cmd_init(hw);
5577         if (ret) {
5578                 hns3_err(hw, "Failed to init cmd: %d", ret);
5579                 return ret;
5580         }
5581
5582         ret = hns3_reset_all_tqps(hns);
5583         if (ret) {
5584                 hns3_err(hw, "Failed to reset all queues: %d", ret);
5585                 return ret;
5586         }
5587
5588         ret = hns3_init_hardware(hns);
5589         if (ret) {
5590                 hns3_err(hw, "Failed to init hardware: %d", ret);
5591                 return ret;
5592         }
5593
5594         ret = hns3_enable_hw_error_intr(hns, true);
5595         if (ret) {
5596                 hns3_err(hw, "fail to enable hw error interrupts: %d",
5597                              ret);
5598                 return ret;
5599         }
5600         hns3_info(hw, "Reset done, driver initialization finished.");
5601
5602         return 0;
5603 }
5604
5605 static bool
5606 is_pf_reset_done(struct hns3_hw *hw)
5607 {
5608         uint32_t val, reg, reg_bit;
5609
5610         switch (hw->reset.level) {
5611         case HNS3_IMP_RESET:
5612                 reg = HNS3_GLOBAL_RESET_REG;
5613                 reg_bit = HNS3_IMP_RESET_BIT;
5614                 break;
5615         case HNS3_GLOBAL_RESET:
5616                 reg = HNS3_GLOBAL_RESET_REG;
5617                 reg_bit = HNS3_GLOBAL_RESET_BIT;
5618                 break;
5619         case HNS3_FUNC_RESET:
5620                 reg = HNS3_FUN_RST_ING;
5621                 reg_bit = HNS3_FUN_RST_ING_B;
5622                 break;
5623         case HNS3_FLR_RESET:
5624         default:
5625                 hns3_err(hw, "Wait for unsupported reset level: %d",
5626                          hw->reset.level);
5627                 return true;
5628         }
5629         val = hns3_read_dev(hw, reg);
5630         if (hns3_get_bit(val, reg_bit))
5631                 return false;
5632         else
5633                 return true;
5634 }
5635
5636 bool
5637 hns3_is_reset_pending(struct hns3_adapter *hns)
5638 {
5639         struct hns3_hw *hw = &hns->hw;
5640         enum hns3_reset_level reset;
5641
5642         hns3_check_event_cause(hns, NULL);
5643         reset = hns3_get_reset_level(hns, &hw->reset.pending);
5644         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5645             hw->reset.level < reset) {
5646                 hns3_warn(hw, "High level reset %d is pending", reset);
5647                 return true;
5648         }
5649         reset = hns3_get_reset_level(hns, &hw->reset.request);
5650         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
5651             hw->reset.level < reset) {
5652                 hns3_warn(hw, "High level reset %d is request", reset);
5653                 return true;
5654         }
5655         return false;
5656 }
5657
5658 static int
5659 hns3_wait_hardware_ready(struct hns3_adapter *hns)
5660 {
5661         struct hns3_hw *hw = &hns->hw;
5662         struct hns3_wait_data *wait_data = hw->reset.wait_data;
5663         struct timeval tv;
5664
5665         if (wait_data->result == HNS3_WAIT_SUCCESS)
5666                 return 0;
5667         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
5668                 hns3_clock_gettime(&tv);
5669                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
5670                           tv.tv_sec, tv.tv_usec);
5671                 return -ETIME;
5672         } else if (wait_data->result == HNS3_WAIT_REQUEST)
5673                 return -EAGAIN;
5674
5675         wait_data->hns = hns;
5676         wait_data->check_completion = is_pf_reset_done;
5677         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
5678                                 HNS3_RESET_WAIT_MS + hns3_clock_gettime_ms();
5679         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
5680         wait_data->count = HNS3_RESET_WAIT_CNT;
5681         wait_data->result = HNS3_WAIT_REQUEST;
5682         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
5683         return -EAGAIN;
5684 }
5685
5686 static int
5687 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
5688 {
5689         struct hns3_cmd_desc desc;
5690         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
5691
5692         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
5693         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
5694         req->fun_reset_vfid = func_id;
5695
5696         return hns3_cmd_send(hw, &desc, 1);
5697 }
5698
5699 static int
5700 hns3_imp_reset_cmd(struct hns3_hw *hw)
5701 {
5702         struct hns3_cmd_desc desc;
5703
5704         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
5705         desc.data[0] = 0xeedd;
5706
5707         return hns3_cmd_send(hw, &desc, 1);
5708 }
5709
5710 static void
5711 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5712 {
5713         struct hns3_hw *hw = &hns->hw;
5714         struct timeval tv;
5715         uint32_t val;
5716
5717         hns3_clock_gettime(&tv);
5718         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5719             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5720                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5721                           tv.tv_sec, tv.tv_usec);
5722                 return;
5723         }
5724
5725         switch (reset_level) {
5726         case HNS3_IMP_RESET:
5727                 hns3_imp_reset_cmd(hw);
5728                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5729                           tv.tv_sec, tv.tv_usec);
5730                 break;
5731         case HNS3_GLOBAL_RESET:
5732                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5733                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5734                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5735                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5736                           tv.tv_sec, tv.tv_usec);
5737                 break;
5738         case HNS3_FUNC_RESET:
5739                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5740                           tv.tv_sec, tv.tv_usec);
5741                 /* schedule again to check later */
5742                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5743                 hns3_schedule_reset(hns);
5744                 break;
5745         default:
5746                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5747                 return;
5748         }
5749         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5750 }
5751
5752 static enum hns3_reset_level
5753 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5754 {
5755         struct hns3_hw *hw = &hns->hw;
5756         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5757
5758         /* Return the highest priority reset level amongst all */
5759         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5760                 reset_level = HNS3_IMP_RESET;
5761         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5762                 reset_level = HNS3_GLOBAL_RESET;
5763         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5764                 reset_level = HNS3_FUNC_RESET;
5765         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5766                 reset_level = HNS3_FLR_RESET;
5767
5768         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5769                 return HNS3_NONE_RESET;
5770
5771         return reset_level;
5772 }
5773
5774 static void
5775 hns3_record_imp_error(struct hns3_adapter *hns)
5776 {
5777         struct hns3_hw *hw = &hns->hw;
5778         uint32_t reg_val;
5779
5780         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5781         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
5782                 hns3_warn(hw, "Detected IMP RD poison!");
5783                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
5784                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5785         }
5786
5787         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
5788                 hns3_warn(hw, "Detected IMP CMDQ error!");
5789                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
5790                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
5791         }
5792 }
5793
5794 static int
5795 hns3_prepare_reset(struct hns3_adapter *hns)
5796 {
5797         struct hns3_hw *hw = &hns->hw;
5798         uint32_t reg_val;
5799         int ret;
5800
5801         switch (hw->reset.level) {
5802         case HNS3_FUNC_RESET:
5803                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5804                 if (ret)
5805                         return ret;
5806
5807                 /*
5808                  * After performaning pf reset, it is not necessary to do the
5809                  * mailbox handling or send any command to firmware, because
5810                  * any mailbox handling or command to firmware is only valid
5811                  * after hns3_cmd_init is called.
5812                  */
5813                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
5814                 hw->reset.stats.request_cnt++;
5815                 break;
5816         case HNS3_IMP_RESET:
5817                 hns3_record_imp_error(hns);
5818                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5819                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5820                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5821                 break;
5822         default:
5823                 break;
5824         }
5825         return 0;
5826 }
5827
5828 static int
5829 hns3_set_rst_done(struct hns3_hw *hw)
5830 {
5831         struct hns3_pf_rst_done_cmd *req;
5832         struct hns3_cmd_desc desc;
5833
5834         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5835         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5836         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5837         return hns3_cmd_send(hw, &desc, 1);
5838 }
5839
5840 static int
5841 hns3_stop_service(struct hns3_adapter *hns)
5842 {
5843         struct hns3_hw *hw = &hns->hw;
5844         struct rte_eth_dev *eth_dev;
5845
5846         eth_dev = &rte_eth_devices[hw->data->port_id];
5847         hw->mac.link_status = RTE_ETH_LINK_DOWN;
5848         if (hw->adapter_state == HNS3_NIC_STARTED) {
5849                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5850                 hns3_update_linkstatus_and_event(hw, false);
5851         }
5852
5853         hns3_set_rxtx_function(eth_dev);
5854         rte_wmb();
5855         /* Disable datapath on secondary process. */
5856         hns3_mp_req_stop_rxtx(eth_dev);
5857         rte_delay_ms(hw->cfg_max_queues);
5858
5859         rte_spinlock_lock(&hw->lock);
5860         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5861             hw->adapter_state == HNS3_NIC_STOPPING) {
5862                 hns3_enable_all_queues(hw, false);
5863                 hns3_do_stop(hns);
5864                 hw->reset.mbuf_deferred_free = true;
5865         } else
5866                 hw->reset.mbuf_deferred_free = false;
5867
5868         /*
5869          * It is cumbersome for hardware to pick-and-choose entries for deletion
5870          * from table space. Hence, for function reset software intervention is
5871          * required to delete the entries
5872          */
5873         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
5874                 hns3_configure_all_mc_mac_addr(hns, true);
5875         rte_spinlock_unlock(&hw->lock);
5876
5877         return 0;
5878 }
5879
5880 static int
5881 hns3_start_service(struct hns3_adapter *hns)
5882 {
5883         struct hns3_hw *hw = &hns->hw;
5884         struct rte_eth_dev *eth_dev;
5885
5886         if (hw->reset.level == HNS3_IMP_RESET ||
5887             hw->reset.level == HNS3_GLOBAL_RESET)
5888                 hns3_set_rst_done(hw);
5889         eth_dev = &rte_eth_devices[hw->data->port_id];
5890         hns3_set_rxtx_function(eth_dev);
5891         hns3_mp_req_start_rxtx(eth_dev);
5892         if (hw->adapter_state == HNS3_NIC_STARTED) {
5893                 /*
5894                  * This API parent function already hold the hns3_hw.lock, the
5895                  * hns3_service_handler may report lse, in bonding application
5896                  * it will call driver's ops which may acquire the hns3_hw.lock
5897                  * again, thus lead to deadlock.
5898                  * We defer calls hns3_service_handler to avoid the deadlock.
5899                  */
5900                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
5901                                   hns3_service_handler, eth_dev);
5902
5903                 /* Enable interrupt of all rx queues before enabling queues */
5904                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5905                 /*
5906                  * Enable state of each rxq and txq will be recovered after
5907                  * reset, so we need to restore them before enable all tqps;
5908                  */
5909                 hns3_restore_tqp_enable_state(hw);
5910                 /*
5911                  * When finished the initialization, enable queues to receive
5912                  * and transmit packets.
5913                  */
5914                 hns3_enable_all_queues(hw, true);
5915         }
5916
5917         return 0;
5918 }
5919
5920 static int
5921 hns3_restore_conf(struct hns3_adapter *hns)
5922 {
5923         struct hns3_hw *hw = &hns->hw;
5924         int ret;
5925
5926         ret = hns3_configure_all_mac_addr(hns, false);
5927         if (ret)
5928                 return ret;
5929
5930         ret = hns3_configure_all_mc_mac_addr(hns, false);
5931         if (ret)
5932                 goto err_mc_mac;
5933
5934         ret = hns3_dev_promisc_restore(hns);
5935         if (ret)
5936                 goto err_promisc;
5937
5938         ret = hns3_restore_vlan_table(hns);
5939         if (ret)
5940                 goto err_promisc;
5941
5942         ret = hns3_restore_vlan_conf(hns);
5943         if (ret)
5944                 goto err_promisc;
5945
5946         ret = hns3_restore_all_fdir_filter(hns);
5947         if (ret)
5948                 goto err_promisc;
5949
5950         ret = hns3_restore_ptp(hns);
5951         if (ret)
5952                 goto err_promisc;
5953
5954         ret = hns3_restore_rx_interrupt(hw);
5955         if (ret)
5956                 goto err_promisc;
5957
5958         ret = hns3_restore_gro_conf(hw);
5959         if (ret)
5960                 goto err_promisc;
5961
5962         ret = hns3_restore_fec(hw);
5963         if (ret)
5964                 goto err_promisc;
5965
5966         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5967                 ret = hns3_do_start(hns, false);
5968                 if (ret)
5969                         goto err_promisc;
5970                 hns3_info(hw, "hns3 dev restart successful!");
5971         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5972                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5973         return 0;
5974
5975 err_promisc:
5976         hns3_configure_all_mc_mac_addr(hns, true);
5977 err_mc_mac:
5978         hns3_configure_all_mac_addr(hns, true);
5979         return ret;
5980 }
5981
5982 static void
5983 hns3_reset_service(void *param)
5984 {
5985         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5986         struct hns3_hw *hw = &hns->hw;
5987         enum hns3_reset_level reset_level;
5988         struct timeval tv_delta;
5989         struct timeval tv_start;
5990         struct timeval tv;
5991         uint64_t msec;
5992         int ret;
5993
5994         /*
5995          * The interrupt is not triggered within the delay time.
5996          * The interrupt may have been lost. It is necessary to handle
5997          * the interrupt to recover from the error.
5998          */
5999         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6000                             SCHEDULE_DEFERRED) {
6001                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6002                                   __ATOMIC_RELAXED);
6003                 hns3_err(hw, "Handling interrupts in delayed tasks");
6004                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6005                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6006                 if (reset_level == HNS3_NONE_RESET) {
6007                         hns3_err(hw, "No reset level is set, try IMP reset");
6008                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6009                 }
6010         }
6011         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6012
6013         /*
6014          * Check if there is any ongoing reset in the hardware. This status can
6015          * be checked from reset_pending. If there is then, we need to wait for
6016          * hardware to complete reset.
6017          *    a. If we are able to figure out in reasonable time that hardware
6018          *       has fully resetted then, we can proceed with driver, client
6019          *       reset.
6020          *    b. else, we can come back later to check this status so re-sched
6021          *       now.
6022          */
6023         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6024         if (reset_level != HNS3_NONE_RESET) {
6025                 hns3_clock_gettime(&tv_start);
6026                 ret = hns3_reset_process(hns, reset_level);
6027                 hns3_clock_gettime(&tv);
6028                 timersub(&tv, &tv_start, &tv_delta);
6029                 msec = hns3_clock_calctime_ms(&tv_delta);
6030                 if (msec > HNS3_RESET_PROCESS_MS)
6031                         hns3_err(hw, "%d handle long time delta %" PRIu64
6032                                      " ms time=%ld.%.6ld",
6033                                  hw->reset.level, msec,
6034                                  tv.tv_sec, tv.tv_usec);
6035                 if (ret == -EAGAIN)
6036                         return;
6037         }
6038
6039         /* Check if we got any *new* reset requests to be honored */
6040         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6041         if (reset_level != HNS3_NONE_RESET)
6042                 hns3_msix_process(hns, reset_level);
6043 }
6044
6045 static unsigned int
6046 hns3_get_speed_capa_num(uint16_t device_id)
6047 {
6048         unsigned int num;
6049
6050         switch (device_id) {
6051         case HNS3_DEV_ID_25GE:
6052         case HNS3_DEV_ID_25GE_RDMA:
6053                 num = 2;
6054                 break;
6055         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6056         case HNS3_DEV_ID_200G_RDMA:
6057                 num = 1;
6058                 break;
6059         default:
6060                 num = 0;
6061                 break;
6062         }
6063
6064         return num;
6065 }
6066
6067 static int
6068 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6069                         uint16_t device_id)
6070 {
6071         switch (device_id) {
6072         case HNS3_DEV_ID_25GE:
6073         /* fallthrough */
6074         case HNS3_DEV_ID_25GE_RDMA:
6075                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6076                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6077
6078                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6079                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6080                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6081                 break;
6082         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6083                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6084                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6085                 break;
6086         case HNS3_DEV_ID_200G_RDMA:
6087                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6088                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6089                 break;
6090         default:
6091                 return -ENOTSUP;
6092         }
6093
6094         return 0;
6095 }
6096
6097 static int
6098 hns3_fec_get_capability(struct rte_eth_dev *dev,
6099                         struct rte_eth_fec_capa *speed_fec_capa,
6100                         unsigned int num)
6101 {
6102         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6104         uint16_t device_id = pci_dev->id.device_id;
6105         unsigned int capa_num;
6106         int ret;
6107
6108         capa_num = hns3_get_speed_capa_num(device_id);
6109         if (capa_num == 0) {
6110                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6111                          device_id);
6112                 return -ENOTSUP;
6113         }
6114
6115         if (speed_fec_capa == NULL || num < capa_num)
6116                 return capa_num;
6117
6118         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6119         if (ret)
6120                 return -ENOTSUP;
6121
6122         return capa_num;
6123 }
6124
6125 static int
6126 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6127 {
6128         struct hns3_config_fec_cmd *req;
6129         struct hns3_cmd_desc desc;
6130         int ret;
6131
6132         /*
6133          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6134          * in device of link speed
6135          * below 10 Gbps.
6136          */
6137         if (hw->mac.link_speed < RTE_ETH_SPEED_NUM_10G) {
6138                 *state = 0;
6139                 return 0;
6140         }
6141
6142         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6143         req = (struct hns3_config_fec_cmd *)desc.data;
6144         ret = hns3_cmd_send(hw, &desc, 1);
6145         if (ret) {
6146                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6147                          ret);
6148                 return ret;
6149         }
6150
6151         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6152         return 0;
6153 }
6154
6155 static int
6156 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6157 {
6158         struct hns3_sfp_info_cmd *resp;
6159         uint32_t tmp_fec_capa;
6160         uint8_t auto_state;
6161         struct hns3_cmd_desc desc;
6162         int ret;
6163
6164         /*
6165          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6166          * configured FEC mode is returned.
6167          * If link is up, current FEC mode is returned.
6168          */
6169         if (hw->mac.link_status == RTE_ETH_LINK_DOWN) {
6170                 ret = get_current_fec_auto_state(hw, &auto_state);
6171                 if (ret)
6172                         return ret;
6173
6174                 if (auto_state == 0x1) {
6175                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6176                         return 0;
6177                 }
6178         }
6179
6180         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6181         resp = (struct hns3_sfp_info_cmd *)desc.data;
6182         resp->query_type = HNS3_ACTIVE_QUERY;
6183
6184         ret = hns3_cmd_send(hw, &desc, 1);
6185         if (ret == -EOPNOTSUPP) {
6186                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6187                 return ret;
6188         } else if (ret) {
6189                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6190                 return ret;
6191         }
6192
6193         /*
6194          * FEC mode order defined in hns3 hardware is inconsistend with
6195          * that defined in the ethdev library. So the sequence needs
6196          * to be converted.
6197          */
6198         switch (resp->active_fec) {
6199         case HNS3_HW_FEC_MODE_NOFEC:
6200                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6201                 break;
6202         case HNS3_HW_FEC_MODE_BASER:
6203                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6204                 break;
6205         case HNS3_HW_FEC_MODE_RS:
6206                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6207                 break;
6208         default:
6209                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6210                 break;
6211         }
6212
6213         *fec_capa = tmp_fec_capa;
6214         return 0;
6215 }
6216
6217 static int
6218 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6219 {
6220         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221
6222         return hns3_fec_get_internal(hw, fec_capa);
6223 }
6224
6225 static int
6226 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6227 {
6228         struct hns3_config_fec_cmd *req;
6229         struct hns3_cmd_desc desc;
6230         int ret;
6231
6232         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6233
6234         req = (struct hns3_config_fec_cmd *)desc.data;
6235         switch (mode) {
6236         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6237                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6238                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6239                 break;
6240         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6241                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6242                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6243                 break;
6244         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6245                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6246                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6247                 break;
6248         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6249                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6250                 break;
6251         default:
6252                 return 0;
6253         }
6254         ret = hns3_cmd_send(hw, &desc, 1);
6255         if (ret)
6256                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6257
6258         return ret;
6259 }
6260
6261 static uint32_t
6262 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6263 {
6264         struct hns3_mac *mac = &hw->mac;
6265         uint32_t cur_capa;
6266
6267         switch (mac->link_speed) {
6268         case RTE_ETH_SPEED_NUM_10G:
6269                 cur_capa = fec_capa[1].capa;
6270                 break;
6271         case RTE_ETH_SPEED_NUM_25G:
6272         case RTE_ETH_SPEED_NUM_100G:
6273         case RTE_ETH_SPEED_NUM_200G:
6274                 cur_capa = fec_capa[0].capa;
6275                 break;
6276         default:
6277                 cur_capa = 0;
6278                 break;
6279         }
6280
6281         return cur_capa;
6282 }
6283
6284 static bool
6285 is_fec_mode_one_bit_set(uint32_t mode)
6286 {
6287         int cnt = 0;
6288         uint8_t i;
6289
6290         for (i = 0; i < sizeof(mode); i++)
6291                 if (mode >> i & 0x1)
6292                         cnt++;
6293
6294         return cnt == 1 ? true : false;
6295 }
6296
6297 static int
6298 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6299 {
6300 #define FEC_CAPA_NUM 2
6301         struct hns3_adapter *hns = dev->data->dev_private;
6302         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6303         struct hns3_pf *pf = &hns->pf;
6304
6305         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6306         uint32_t cur_capa;
6307         uint32_t num = FEC_CAPA_NUM;
6308         int ret;
6309
6310         ret = hns3_fec_get_capability(dev, fec_capa, num);
6311         if (ret < 0)
6312                 return ret;
6313
6314         /* HNS3 PMD only support one bit set mode, e.g. 0x1, 0x4 */
6315         if (!is_fec_mode_one_bit_set(mode)) {
6316                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD, "
6317                              "FEC mode should be only one bit set", mode);
6318                 return -EINVAL;
6319         }
6320
6321         /*
6322          * Check whether the configured mode is within the FEC capability.
6323          * If not, the configured mode will not be supported.
6324          */
6325         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6326         if (!(cur_capa & mode)) {
6327                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6328                 return -EINVAL;
6329         }
6330
6331         rte_spinlock_lock(&hw->lock);
6332         ret = hns3_set_fec_hw(hw, mode);
6333         if (ret) {
6334                 rte_spinlock_unlock(&hw->lock);
6335                 return ret;
6336         }
6337
6338         pf->fec_mode = mode;
6339         rte_spinlock_unlock(&hw->lock);
6340
6341         return 0;
6342 }
6343
6344 static int
6345 hns3_restore_fec(struct hns3_hw *hw)
6346 {
6347         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6348         struct hns3_pf *pf = &hns->pf;
6349         uint32_t mode = pf->fec_mode;
6350         int ret;
6351
6352         ret = hns3_set_fec_hw(hw, mode);
6353         if (ret)
6354                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6355                          mode, ret);
6356
6357         return ret;
6358 }
6359
6360 static int
6361 hns3_query_dev_fec_info(struct hns3_hw *hw)
6362 {
6363         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6364         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
6365         int ret;
6366
6367         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
6368         if (ret)
6369                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
6370
6371         return ret;
6372 }
6373
6374 static bool
6375 hns3_optical_module_existed(struct hns3_hw *hw)
6376 {
6377         struct hns3_cmd_desc desc;
6378         bool existed;
6379         int ret;
6380
6381         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
6382         ret = hns3_cmd_send(hw, &desc, 1);
6383         if (ret) {
6384                 hns3_err(hw,
6385                          "fail to get optical module exist state, ret = %d.\n",
6386                          ret);
6387                 return false;
6388         }
6389         existed = !!desc.data[0];
6390
6391         return existed;
6392 }
6393
6394 static int
6395 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
6396                                 uint32_t len, uint8_t *data)
6397 {
6398 #define HNS3_SFP_INFO_CMD_NUM 6
6399 #define HNS3_SFP_INFO_MAX_LEN \
6400         (HNS3_SFP_INFO_BD0_LEN + \
6401         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
6402         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
6403         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
6404         uint16_t read_len;
6405         uint16_t copy_len;
6406         int ret;
6407         int i;
6408
6409         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6410                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
6411                                           true);
6412                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
6413                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
6414         }
6415
6416         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
6417         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
6418         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
6419         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
6420
6421         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
6422         if (ret) {
6423                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
6424                                 ret);
6425                 return ret;
6426         }
6427
6428         /* The data format in BD0 is different with the others. */
6429         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
6430         memcpy(data, sfp_info_bd0->data, copy_len);
6431         read_len = copy_len;
6432
6433         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
6434                 if (read_len >= len)
6435                         break;
6436
6437                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
6438                 memcpy(data + read_len, desc[i].data, copy_len);
6439                 read_len += copy_len;
6440         }
6441
6442         return (int)read_len;
6443 }
6444
6445 static int
6446 hns3_get_module_eeprom(struct rte_eth_dev *dev,
6447                        struct rte_dev_eeprom_info *info)
6448 {
6449         struct hns3_adapter *hns = dev->data->dev_private;
6450         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6451         uint32_t offset = info->offset;
6452         uint32_t len = info->length;
6453         uint8_t *data = info->data;
6454         uint32_t read_len = 0;
6455
6456         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
6457                 return -ENOTSUP;
6458
6459         if (!hns3_optical_module_existed(hw)) {
6460                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
6461                 return -EIO;
6462         }
6463
6464         while (read_len < len) {
6465                 int ret;
6466                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
6467                                                   len - read_len,
6468                                                   data + read_len);
6469                 if (ret < 0)
6470                         return -EIO;
6471                 read_len += ret;
6472         }
6473
6474         return 0;
6475 }
6476
6477 static int
6478 hns3_get_module_info(struct rte_eth_dev *dev,
6479                      struct rte_eth_dev_module_info *modinfo)
6480 {
6481 #define HNS3_SFF8024_ID_SFP             0x03
6482 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
6483 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
6484 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
6485 #define HNS3_SFF_8636_V1_3              0x03
6486         struct hns3_adapter *hns = dev->data->dev_private;
6487         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6488         struct rte_dev_eeprom_info info;
6489         struct hns3_sfp_type sfp_type;
6490         int ret;
6491
6492         memset(&sfp_type, 0, sizeof(sfp_type));
6493         memset(&info, 0, sizeof(info));
6494         info.data = (uint8_t *)&sfp_type;
6495         info.length = sizeof(sfp_type);
6496         ret = hns3_get_module_eeprom(dev, &info);
6497         if (ret)
6498                 return ret;
6499
6500         switch (sfp_type.type) {
6501         case HNS3_SFF8024_ID_SFP:
6502                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
6503                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
6504                 break;
6505         case HNS3_SFF8024_ID_QSFP_8438:
6506                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
6507                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6508                 break;
6509         case HNS3_SFF8024_ID_QSFP_8436_8636:
6510                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
6511                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
6512                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
6513                 } else {
6514                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
6515                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6516                 }
6517                 break;
6518         case HNS3_SFF8024_ID_QSFP28_8636:
6519                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
6520                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
6521                 break;
6522         default:
6523                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
6524                          sfp_type.type, sfp_type.ext_type);
6525                 return -EINVAL;
6526         }
6527
6528         return 0;
6529 }
6530
6531 static const struct eth_dev_ops hns3_eth_dev_ops = {
6532         .dev_configure      = hns3_dev_configure,
6533         .dev_start          = hns3_dev_start,
6534         .dev_stop           = hns3_dev_stop,
6535         .dev_close          = hns3_dev_close,
6536         .promiscuous_enable = hns3_dev_promiscuous_enable,
6537         .promiscuous_disable = hns3_dev_promiscuous_disable,
6538         .allmulticast_enable  = hns3_dev_allmulticast_enable,
6539         .allmulticast_disable = hns3_dev_allmulticast_disable,
6540         .mtu_set            = hns3_dev_mtu_set,
6541         .stats_get          = hns3_stats_get,
6542         .stats_reset        = hns3_stats_reset,
6543         .xstats_get         = hns3_dev_xstats_get,
6544         .xstats_get_names   = hns3_dev_xstats_get_names,
6545         .xstats_reset       = hns3_dev_xstats_reset,
6546         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
6547         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
6548         .dev_infos_get          = hns3_dev_infos_get,
6549         .fw_version_get         = hns3_fw_version_get,
6550         .rx_queue_setup         = hns3_rx_queue_setup,
6551         .tx_queue_setup         = hns3_tx_queue_setup,
6552         .rx_queue_release       = hns3_dev_rx_queue_release,
6553         .tx_queue_release       = hns3_dev_tx_queue_release,
6554         .rx_queue_start         = hns3_dev_rx_queue_start,
6555         .rx_queue_stop          = hns3_dev_rx_queue_stop,
6556         .tx_queue_start         = hns3_dev_tx_queue_start,
6557         .tx_queue_stop          = hns3_dev_tx_queue_stop,
6558         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
6559         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
6560         .rxq_info_get           = hns3_rxq_info_get,
6561         .txq_info_get           = hns3_txq_info_get,
6562         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
6563         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
6564         .flow_ctrl_get          = hns3_flow_ctrl_get,
6565         .flow_ctrl_set          = hns3_flow_ctrl_set,
6566         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
6567         .mac_addr_add           = hns3_add_mac_addr,
6568         .mac_addr_remove        = hns3_remove_mac_addr,
6569         .mac_addr_set           = hns3_set_default_mac_addr,
6570         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
6571         .link_update            = hns3_dev_link_update,
6572         .dev_set_link_up        = hns3_dev_set_link_up,
6573         .dev_set_link_down      = hns3_dev_set_link_down,
6574         .rss_hash_update        = hns3_dev_rss_hash_update,
6575         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
6576         .reta_update            = hns3_dev_rss_reta_update,
6577         .reta_query             = hns3_dev_rss_reta_query,
6578         .flow_ops_get           = hns3_dev_flow_ops_get,
6579         .vlan_filter_set        = hns3_vlan_filter_set,
6580         .vlan_tpid_set          = hns3_vlan_tpid_set,
6581         .vlan_offload_set       = hns3_vlan_offload_set,
6582         .vlan_pvid_set          = hns3_vlan_pvid_set,
6583         .get_reg                = hns3_get_regs,
6584         .get_module_info        = hns3_get_module_info,
6585         .get_module_eeprom      = hns3_get_module_eeprom,
6586         .get_dcb_info           = hns3_get_dcb_info,
6587         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
6588         .fec_get_capability     = hns3_fec_get_capability,
6589         .fec_get                = hns3_fec_get,
6590         .fec_set                = hns3_fec_set,
6591         .tm_ops_get             = hns3_tm_ops_get,
6592         .tx_done_cleanup        = hns3_tx_done_cleanup,
6593         .timesync_enable            = hns3_timesync_enable,
6594         .timesync_disable           = hns3_timesync_disable,
6595         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
6596         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
6597         .timesync_adjust_time       = hns3_timesync_adjust_time,
6598         .timesync_read_time         = hns3_timesync_read_time,
6599         .timesync_write_time        = hns3_timesync_write_time,
6600 };
6601
6602 static const struct hns3_reset_ops hns3_reset_ops = {
6603         .reset_service       = hns3_reset_service,
6604         .stop_service        = hns3_stop_service,
6605         .prepare_reset       = hns3_prepare_reset,
6606         .wait_hardware_ready = hns3_wait_hardware_ready,
6607         .reinit_dev          = hns3_reinit_dev,
6608         .restore_conf        = hns3_restore_conf,
6609         .start_service       = hns3_start_service,
6610 };
6611
6612 static void
6613 hns3_init_hw_ops(struct hns3_hw *hw)
6614 {
6615         hw->ops.add_mc_mac_addr = hns3_add_mc_mac_addr;
6616         hw->ops.del_mc_mac_addr = hns3_remove_mc_mac_addr;
6617         hw->ops.add_uc_mac_addr = hns3_add_uc_mac_addr;
6618         hw->ops.del_uc_mac_addr = hns3_remove_uc_mac_addr;
6619         hw->ops.bind_ring_with_vector = hns3_bind_ring_with_vector;
6620 }
6621
6622 static int
6623 hns3_dev_init(struct rte_eth_dev *eth_dev)
6624 {
6625         struct hns3_adapter *hns = eth_dev->data->dev_private;
6626         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
6627         struct rte_ether_addr *eth_addr;
6628         struct hns3_hw *hw = &hns->hw;
6629         int ret;
6630
6631         PMD_INIT_FUNC_TRACE();
6632
6633         hns3_flow_init(eth_dev);
6634
6635         hns3_set_rxtx_function(eth_dev);
6636         eth_dev->dev_ops = &hns3_eth_dev_ops;
6637         eth_dev->rx_queue_count = hns3_rx_queue_count;
6638         ret = hns3_mp_init(eth_dev);
6639         if (ret)
6640                 goto err_mp_init;
6641
6642         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6643                 hns3_tx_push_init(eth_dev);
6644                 return 0;
6645         }
6646
6647         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
6648         hns->is_vf = false;
6649         hw->data = eth_dev->data;
6650         hns3_parse_devargs(eth_dev);
6651
6652         /*
6653          * Set default max packet size according to the mtu
6654          * default vale in DPDK frame.
6655          */
6656         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
6657
6658         ret = hns3_reset_init(hw);
6659         if (ret)
6660                 goto err_init_reset;
6661         hw->reset.ops = &hns3_reset_ops;
6662
6663         hns3_init_hw_ops(hw);
6664         ret = hns3_init_pf(eth_dev);
6665         if (ret) {
6666                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
6667                 goto err_init_pf;
6668         }
6669
6670         /* Allocate memory for storing MAC addresses */
6671         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
6672                                                sizeof(struct rte_ether_addr) *
6673                                                HNS3_UC_MACADDR_NUM, 0);
6674         if (eth_dev->data->mac_addrs == NULL) {
6675                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
6676                              "to store MAC addresses",
6677                              sizeof(struct rte_ether_addr) *
6678                              HNS3_UC_MACADDR_NUM);
6679                 ret = -ENOMEM;
6680                 goto err_rte_zmalloc;
6681         }
6682
6683         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
6684         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
6685                 rte_eth_random_addr(hw->mac.mac_addr);
6686                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
6687                                 (struct rte_ether_addr *)hw->mac.mac_addr);
6688                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
6689                           "unicast address, using random MAC address %s",
6690                           mac_str);
6691         }
6692         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
6693                             &eth_dev->data->mac_addrs[0]);
6694
6695         hw->adapter_state = HNS3_NIC_INITIALIZED;
6696
6697         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6698                             SCHEDULE_PENDING) {
6699                 hns3_err(hw, "Reschedule reset service after dev_init");
6700                 hns3_schedule_reset(hns);
6701         } else {
6702                 /* IMP will wait ready flag before reset */
6703                 hns3_notify_reset_ready(hw, false);
6704         }
6705
6706         hns3_info(hw, "hns3 dev initialization successful!");
6707         return 0;
6708
6709 err_rte_zmalloc:
6710         hns3_uninit_pf(eth_dev);
6711
6712 err_init_pf:
6713         rte_free(hw->reset.wait_data);
6714
6715 err_init_reset:
6716         hns3_mp_uninit(eth_dev);
6717
6718 err_mp_init:
6719         eth_dev->dev_ops = NULL;
6720         eth_dev->rx_pkt_burst = NULL;
6721         eth_dev->rx_descriptor_status = NULL;
6722         eth_dev->tx_pkt_burst = NULL;
6723         eth_dev->tx_pkt_prepare = NULL;
6724         eth_dev->tx_descriptor_status = NULL;
6725         return ret;
6726 }
6727
6728 static int
6729 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
6730 {
6731         struct hns3_adapter *hns = eth_dev->data->dev_private;
6732         struct hns3_hw *hw = &hns->hw;
6733
6734         PMD_INIT_FUNC_TRACE();
6735
6736         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
6737                 hns3_mp_uninit(eth_dev);
6738                 return 0;
6739         }
6740
6741         if (hw->adapter_state < HNS3_NIC_CLOSING)
6742                 hns3_dev_close(eth_dev);
6743
6744         hw->adapter_state = HNS3_NIC_REMOVED;
6745         return 0;
6746 }
6747
6748 static int
6749 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6750                    struct rte_pci_device *pci_dev)
6751 {
6752         return rte_eth_dev_pci_generic_probe(pci_dev,
6753                                              sizeof(struct hns3_adapter),
6754                                              hns3_dev_init);
6755 }
6756
6757 static int
6758 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
6759 {
6760         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
6761 }
6762
6763 static const struct rte_pci_id pci_id_hns3_map[] = {
6764         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
6765         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
6766         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
6767         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
6768         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
6769         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
6770         { .vendor_id = 0, }, /* sentinel */
6771 };
6772
6773 static struct rte_pci_driver rte_hns3_pmd = {
6774         .id_table = pci_id_hns3_map,
6775         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
6776         .probe = eth_hns3_pci_probe,
6777         .remove = eth_hns3_pci_remove,
6778 };
6779
6780 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
6781 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
6782 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
6783 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
6784                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
6785                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
6786                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
6787                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16> ");
6788 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_init, init, NOTICE);
6789 RTE_LOG_REGISTER_SUFFIX(hns3_logtype_driver, driver, NOTICE);