drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108
 109 void hns3_ether_format_addr(char *buf, uint16_t size,
 110                             const struct rte_ether_addr *ether_addr)
 111 {
 112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 113                 ether_addr->addr_bytes[0],
 114                 ether_addr->addr_bytes[4],
 115                 ether_addr->addr_bytes[5]);
 116 }
 117
 118 static void
 119 hns3_pf_disable_irq0(struct hns3_hw *hw)
 120 {
 121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 122 }
 123
 124 static void
 125 hns3_pf_enable_irq0(struct hns3_hw *hw)
 126 {
 127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 128 }
 129
 130 static enum hns3_evt_cause
 131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 132                           uint32_t *vec_val)
 133 {
 134         struct hns3_hw *hw = &hns->hw;
 135
 136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 139         if (!is_delay) {
 140                 hw->reset.stats.imp_cnt++;
 141                 hns3_warn(hw, "IMP reset detected, clear reset status");
 142         } else {
 143                 hns3_schedule_delayed_reset(hns);
 144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 145         }
 146
 147         return HNS3_VECTOR0_EVENT_RST;
 148 }
 149
 150 static enum hns3_evt_cause
 151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 152                              uint32_t *vec_val)
 153 {
 154         struct hns3_hw *hw = &hns->hw;
 155
 156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 159         if (!is_delay) {
 160                 hw->reset.stats.global_cnt++;
 161                 hns3_warn(hw, "Global reset detected, clear reset status");
 162         } else {
 163                 hns3_schedule_delayed_reset(hns);
 164                 hns3_warn(hw,
 165                           "Global reset detected, don't clear reset status");
 166         }
 167
 168         return HNS3_VECTOR0_EVENT_RST;
 169 }
 170
 171 static enum hns3_evt_cause
 172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 173 {
 174         struct hns3_hw *hw = &hns->hw;
 175         uint32_t vector0_int_stats;
 176         uint32_t cmdq_src_val;
 177         uint32_t hw_err_src_reg;
 178         uint32_t val;
 179         enum hns3_evt_cause ret;
 180         bool is_delay;
 181
 182         /* fetch the events from their corresponding regs */
 183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 186
 187         is_delay = clearval == NULL ? true : false;
 188         /*
 189          * Assumption: If by any chance reset and mailbox events are reported
 190          * together then we will only process reset event and defer the
 191          * processing of the mailbox events. Since, we would have not cleared
 192          * RX CMDQ event this time we would receive again another interrupt
 193          * from H/W just for the mailbox.
 194          */
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 197                 goto out;
 198         }
 199
 200         /* Global reset */
 201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 203                 goto out;
 204         }
 205
 206         /* Check for vector0 1588 event source */
 207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 209                 ret = HNS3_VECTOR0_EVENT_PTP;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 msix event source */
 214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 216                 val = vector0_int_stats | hw_err_src_reg;
 217                 ret = HNS3_VECTOR0_EVENT_ERR;
 218                 goto out;
 219         }
 220
 221         /* check for vector0 mailbox(=CMDQ RX) event source */
 222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 224                 val = cmdq_src_val;
 225                 ret = HNS3_VECTOR0_EVENT_MBX;
 226                 goto out;
 227         }
 228
 229         val = vector0_int_stats;
 230         ret = HNS3_VECTOR0_EVENT_OTHER;
 231 out:
 232
 233         if (clearval)
 234                 *clearval = val;
 235         return ret;
 236 }
 237
 238 static bool
 239 hns3_is_1588_event_type(uint32_t event_type)
 240 {
 241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 242 }
 243
 244 static void
 245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 246 {
 247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 248             hns3_is_1588_event_type(event_type))
 249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 252 }
 253
 254 static void
 255 hns3_clear_all_event_cause(struct hns3_hw *hw)
 256 {
 257         uint32_t vector0_int_stats;
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259
 260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 261                 hns3_warn(hw, "Probe during IMP reset interrupt");
 262
 263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 264                 hns3_warn(hw, "Probe during Global reset interrupt");
 265
 266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 272                                 BIT(HNS3_VECTOR0_1588_INT_B));
 273 }
 274
 275 static void
 276 hns3_handle_mac_tnl(struct hns3_hw *hw)
 277 {
 278         struct hns3_cmd_desc desc;
 279         uint32_t status;
 280         int ret;
 281
 282         /* query and clear mac tnl interruptions */
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 284         ret = hns3_cmd_send(hw, &desc, 1);
 285         if (ret) {
 286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 287                 return;
 288         }
 289
 290         status = rte_le_to_cpu_32(desc.data[0]);
 291         if (status) {
 292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 294                                           false);
 295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 296                 ret = hns3_cmd_send(hw, &desc, 1);
 297                 if (ret)
 298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 299                                  ret);
 300         }
 301 }
 302
 303 static void
 304 hns3_interrupt_handler(void *param)
 305 {
 306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 307         struct hns3_adapter *hns = dev->data->dev_private;
 308         struct hns3_hw *hw = &hns->hw;
 309         enum hns3_evt_cause event_cause;
 310         uint32_t clearval = 0;
 311         uint32_t vector0_int;
 312         uint32_t ras_int;
 313         uint32_t cmdq_int;
 314
 315         /* Disable interrupt */
 316         hns3_pf_disable_irq0(hw);
 317
 318         event_cause = hns3_check_event_cause(hns, &clearval);
 319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_msix_error(hns, &hw->reset.request);
 328                 hns3_handle_ras_error(hns, &hw->reset.request);
 329                 hns3_handle_mac_tnl(hw);
 330                 hns3_schedule_reset(hns);
 331         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 332                 hns3_warn(hw, "received reset interrupt");
 333                 hns3_schedule_reset(hns);
 334         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 335                 hns3_dev_handle_mbx_msg(hw);
 336         } else {
 337                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 338                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 339                           vector0_int, ras_int, cmdq_int);
 340         }
 341
 342         hns3_clear_event_cause(hw, event_cause, clearval);
 343         /* Enable interrupt if it is not cause by reset */
 344         hns3_pf_enable_irq0(hw);
 345 }
 346
 347 static int
 348 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 349 {
 350 #define HNS3_VLAN_ID_OFFSET_STEP        160
 351 #define HNS3_VLAN_BYTE_SIZE             8
 352         struct hns3_vlan_filter_pf_cfg_cmd *req;
 353         struct hns3_hw *hw = &hns->hw;
 354         uint8_t vlan_offset_byte_val;
 355         struct hns3_cmd_desc desc;
 356         uint8_t vlan_offset_byte;
 357         uint8_t vlan_offset_base;
 358         int ret;
 359
 360         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 361
 362         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 363         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 364                            HNS3_VLAN_BYTE_SIZE;
 365         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 366
 367         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 368         req->vlan_offset = vlan_offset_base;
 369         req->vlan_cfg = on ? 0 : 1;
 370         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 371
 372         ret = hns3_cmd_send(hw, &desc, 1);
 373         if (ret)
 374                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 375                          vlan_id, ret);
 376
 377         return ret;
 378 }
 379
 380 static void
 381 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 382 {
 383         struct hns3_user_vlan_table *vlan_entry;
 384         struct hns3_pf *pf = &hns->pf;
 385
 386         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 387                 if (vlan_entry->vlan_id == vlan_id) {
 388                         if (vlan_entry->hd_tbl_status)
 389                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 390                         LIST_REMOVE(vlan_entry, next);
 391                         rte_free(vlan_entry);
 392                         break;
 393                 }
 394         }
 395 }
 396
 397 static void
 398 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 399                         bool writen_to_tbl)
 400 {
 401         struct hns3_user_vlan_table *vlan_entry;
 402         struct hns3_hw *hw = &hns->hw;
 403         struct hns3_pf *pf = &hns->pf;
 404
 405         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 406                 if (vlan_entry->vlan_id == vlan_id)
 407                         return;
 408         }
 409
 410         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 411         if (vlan_entry == NULL) {
 412                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 413                 return;
 414         }
 415
 416         vlan_entry->hd_tbl_status = writen_to_tbl;
 417         vlan_entry->vlan_id = vlan_id;
 418
 419         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 420 }
 421
 422 static int
 423 hns3_restore_vlan_table(struct hns3_adapter *hns)
 424 {
 425         struct hns3_user_vlan_table *vlan_entry;
 426         struct hns3_hw *hw = &hns->hw;
 427         struct hns3_pf *pf = &hns->pf;
 428         uint16_t vlan_id;
 429         int ret = 0;
 430
 431         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 432                 return hns3_vlan_pvid_configure(hns,
 433                                                 hw->port_base_vlan_cfg.pvid, 1);
 434
 435         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 436                 if (vlan_entry->hd_tbl_status) {
 437                         vlan_id = vlan_entry->vlan_id;
 438                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 439                         if (ret)
 440                                 break;
 441                 }
 442         }
 443
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 449 {
 450         struct hns3_hw *hw = &hns->hw;
 451         bool writen_to_tbl = false;
 452         int ret = 0;
 453
 454         /*
 455          * When vlan filter is enabled, hardware regards packets without vlan
 456          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 457          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 458          */
 459         if (on == 0 && vlan_id == 0)
 460                 return 0;
 461
 462         /*
 463          * When port base vlan enabled, we use port base vlan as the vlan
 464          * filter condition. In this case, we don't update vlan filter table
 465          * when user add new vlan or remove exist vlan, just update the
 466          * vlan list. The vlan id in vlan list will be writen in vlan filter
 467          * table until port base vlan disabled
 468          */
 469         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 470                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 471                 writen_to_tbl = true;
 472         }
 473
 474         if (ret == 0) {
 475                 if (on)
 476                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 477                 else
 478                         hns3_rm_dev_vlan_table(hns, vlan_id);
 479         }
 480         return ret;
 481 }
 482
 483 static int
 484 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 485 {
 486         struct hns3_adapter *hns = dev->data->dev_private;
 487         struct hns3_hw *hw = &hns->hw;
 488         int ret;
 489
 490         rte_spinlock_lock(&hw->lock);
 491         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 492         rte_spinlock_unlock(&hw->lock);
 493         return ret;
 494 }
 495
 496 static int
 497 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 498                          uint16_t tpid)
 499 {
 500         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 501         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 502         struct hns3_hw *hw = &hns->hw;
 503         struct hns3_cmd_desc desc;
 504         int ret;
 505
 506         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 507              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 508                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 509                 return -EINVAL;
 510         }
 511
 512         if (tpid != RTE_ETHER_TYPE_VLAN) {
 513                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 514                 return -EINVAL;
 515         }
 516
 517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 518         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 519
 520         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 521                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 522                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 523         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 524                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 527                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 528         }
 529
 530         ret = hns3_cmd_send(hw, &desc, 1);
 531         if (ret) {
 532                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 533                          ret);
 534                 return ret;
 535         }
 536
 537         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 538
 539         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 540         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 541         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 542
 543         ret = hns3_cmd_send(hw, &desc, 1);
 544         if (ret)
 545                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 546                          ret);
 547         return ret;
 548 }
 549
 550 static int
 551 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 552                    uint16_t tpid)
 553 {
 554         struct hns3_adapter *hns = dev->data->dev_private;
 555         struct hns3_hw *hw = &hns->hw;
 556         int ret;
 557
 558         rte_spinlock_lock(&hw->lock);
 559         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 560         rte_spinlock_unlock(&hw->lock);
 561         return ret;
 562 }
 563
 564 static int
 565 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 566                              struct hns3_rx_vtag_cfg *vcfg)
 567 {
 568         struct hns3_vport_vtag_rx_cfg_cmd *req;
 569         struct hns3_hw *hw = &hns->hw;
 570         struct hns3_cmd_desc desc;
 571         uint16_t vport_id;
 572         uint8_t bitmap;
 573         int ret;
 574
 575         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 576
 577         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 579                      vcfg->strip_tag1_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 581                      vcfg->strip_tag2_en ? 1 : 0);
 582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 583                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 584         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 585                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 586
 587         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 589                      vcfg->strip_tag1_discard_en ? 1 : 0);
 590         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 591                      vcfg->strip_tag2_discard_en ? 1 : 0);
 592         /*
 593          * In current version VF is not supported when PF is driven by DPDK
 594          * driver, just need to configure parameters for PF vport.
 595          */
 596         vport_id = HNS3_PF_FUNC_ID;
 597         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 598         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 599         req->vf_bitmap[req->vf_offset] = bitmap;
 600
 601         ret = hns3_cmd_send(hw, &desc, 1);
 602         if (ret)
 603                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 604         return ret;
 605 }
 606
 607 static void
 608 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 609                            struct hns3_rx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_pf *pf = &hns->pf;
 612         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 613 }
 614
 615 static void
 616 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 617                            struct hns3_tx_vtag_cfg *vcfg)
 618 {
 619         struct hns3_pf *pf = &hns->pf;
 620         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 621 }
 622
 623 static int
 624 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 625 {
 626         struct hns3_rx_vtag_cfg rxvlan_cfg;
 627         struct hns3_hw *hw = &hns->hw;
 628         int ret;
 629
 630         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 631                 rxvlan_cfg.strip_tag1_en = false;
 632                 rxvlan_cfg.strip_tag2_en = enable;
 633                 rxvlan_cfg.strip_tag2_discard_en = false;
 634         } else {
 635                 rxvlan_cfg.strip_tag1_en = enable;
 636                 rxvlan_cfg.strip_tag2_en = true;
 637                 rxvlan_cfg.strip_tag2_discard_en = true;
 638         }
 639
 640         rxvlan_cfg.strip_tag1_discard_en = false;
 641         rxvlan_cfg.vlan1_vlan_prionly = false;
 642         rxvlan_cfg.vlan2_vlan_prionly = false;
 643         rxvlan_cfg.rx_vlan_offload_en = enable;
 644
 645         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 646         if (ret) {
 647                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 648                 return ret;
 649         }
 650
 651         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 652
 653         return ret;
 654 }
 655
 656 static int
 657 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 658                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 659 {
 660         struct hns3_vlan_filter_ctrl_cmd *req;
 661         struct hns3_cmd_desc desc;
 662         int ret;
 663
 664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 665
 666         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 667         req->vlan_type = vlan_type;
 668         req->vlan_fe = filter_en ? fe_type : 0;
 669         req->vf_id = vf_id;
 670
 671         ret = hns3_cmd_send(hw, &desc, 1);
 672         if (ret)
 673                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 674
 675         return ret;
 676 }
 677
 678 static int
 679 hns3_vlan_filter_init(struct hns3_adapter *hns)
 680 {
 681         struct hns3_hw *hw = &hns->hw;
 682         int ret;
 683
 684         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 685                                         HNS3_FILTER_FE_EGRESS, false,
 686                                         HNS3_PF_FUNC_ID);
 687         if (ret) {
 688                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 689                 return ret;
 690         }
 691
 692         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 693                                         HNS3_FILTER_FE_INGRESS, false,
 694                                         HNS3_PF_FUNC_ID);
 695         if (ret)
 696                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 697
 698         return ret;
 699 }
 700
 701 static int
 702 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 703 {
 704         struct hns3_hw *hw = &hns->hw;
 705         int ret;
 706
 707         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 708                                         HNS3_FILTER_FE_INGRESS, enable,
 709                                         HNS3_PF_FUNC_ID);
 710         if (ret)
 711                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 712                          enable ? "enable" : "disable", ret);
 713
 714         return ret;
 715 }
 716
 717 static int
 718 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 719 {
 720         struct hns3_adapter *hns = dev->data->dev_private;
 721         struct hns3_hw *hw = &hns->hw;
 722         struct rte_eth_rxmode *rxmode;
 723         unsigned int tmp_mask;
 724         bool enable;
 725         int ret = 0;
 726
 727         rte_spinlock_lock(&hw->lock);
 728         rxmode = &dev->data->dev_conf.rxmode;
 729         tmp_mask = (unsigned int)mask;
 730         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 731                 /* ignore vlan filter configuration during promiscuous mode */
 732                 if (!dev->data->promiscuous) {
 733                         /* Enable or disable VLAN filter */
 734                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 735                                  true : false;
 736
 737                         ret = hns3_enable_vlan_filter(hns, enable);
 738                         if (ret) {
 739                                 rte_spinlock_unlock(&hw->lock);
 740                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 741                                          enable ? "enable" : "disable", ret);
 742                                 return ret;
 743                         }
 744                 }
 745         }
 746
 747         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 748                 /* Enable or disable VLAN stripping */
 749                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 750                     true : false;
 751
 752                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 753                 if (ret) {
 754                         rte_spinlock_unlock(&hw->lock);
 755                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 756                                  enable ? "enable" : "disable", ret);
 757                         return ret;
 758                 }
 759         }
 760
 761         rte_spinlock_unlock(&hw->lock);
 762
 763         return ret;
 764 }
 765
 766 static int
 767 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 768                              struct hns3_tx_vtag_cfg *vcfg)
 769 {
 770         struct hns3_vport_vtag_tx_cfg_cmd *req;
 771         struct hns3_cmd_desc desc;
 772         struct hns3_hw *hw = &hns->hw;
 773         uint16_t vport_id;
 774         uint8_t bitmap;
 775         int ret;
 776
 777         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 778
 779         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 780         req->def_vlan_tag1 = vcfg->default_tag1;
 781         req->def_vlan_tag2 = vcfg->default_tag2;
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 783                      vcfg->accept_tag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 785                      vcfg->accept_untag1 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 787                      vcfg->accept_tag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 789                      vcfg->accept_untag2 ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 791                      vcfg->insert_tag1_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 793                      vcfg->insert_tag2_en ? 1 : 0);
 794         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 795
 796         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 797         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 798                      vcfg->tag_shift_mode_en ? 1 : 0);
 799
 800         /*
 801          * In current version VF is not supported when PF is driven by DPDK
 802          * driver, just need to configure parameters for PF vport.
 803          */
 804         vport_id = HNS3_PF_FUNC_ID;
 805         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 806         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 807         req->vf_bitmap[req->vf_offset] = bitmap;
 808
 809         ret = hns3_cmd_send(hw, &desc, 1);
 810         if (ret)
 811                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 812
 813         return ret;
 814 }
 815
 816 static int
 817 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 818                      uint16_t pvid)
 819 {
 820         struct hns3_hw *hw = &hns->hw;
 821         struct hns3_tx_vtag_cfg txvlan_cfg;
 822         int ret;
 823
 824         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 825                 txvlan_cfg.accept_tag1 = true;
 826                 txvlan_cfg.insert_tag1_en = false;
 827                 txvlan_cfg.default_tag1 = 0;
 828         } else {
 829                 txvlan_cfg.accept_tag1 =
 830                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 831                 txvlan_cfg.insert_tag1_en = true;
 832                 txvlan_cfg.default_tag1 = pvid;
 833         }
 834
 835         txvlan_cfg.accept_untag1 = true;
 836         txvlan_cfg.accept_tag2 = true;
 837         txvlan_cfg.accept_untag2 = true;
 838         txvlan_cfg.insert_tag2_en = false;
 839         txvlan_cfg.default_tag2 = 0;
 840         txvlan_cfg.tag_shift_mode_en = true;
 841
 842         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 843         if (ret) {
 844                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 845                          ret);
 846                 return ret;
 847         }
 848
 849         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 850         return ret;
 851 }
 852
 853
 854 static void
 855 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 856 {
 857         struct hns3_user_vlan_table *vlan_entry;
 858         struct hns3_pf *pf = &hns->pf;
 859
 860         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 861                 if (vlan_entry->hd_tbl_status) {
 862                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 863                         vlan_entry->hd_tbl_status = false;
 864                 }
 865         }
 866
 867         if (is_del_list) {
 868                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 869                 while (vlan_entry) {
 870                         LIST_REMOVE(vlan_entry, next);
 871                         rte_free(vlan_entry);
 872                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 873                 }
 874         }
 875 }
 876
 877 static void
 878 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 879 {
 880         struct hns3_user_vlan_table *vlan_entry;
 881         struct hns3_pf *pf = &hns->pf;
 882
 883         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 884                 if (!vlan_entry->hd_tbl_status) {
 885                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 886                         vlan_entry->hd_tbl_status = true;
 887                 }
 888         }
 889 }
 890
 891 static void
 892 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 893 {
 894         struct hns3_hw *hw = &hns->hw;
 895         int ret;
 896
 897         hns3_rm_all_vlan_table(hns, true);
 898         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 899                 ret = hns3_set_port_vlan_filter(hns,
 900                                                 hw->port_base_vlan_cfg.pvid, 0);
 901                 if (ret) {
 902                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 903                                  ret);
 904                         return;
 905                 }
 906         }
 907 }
 908
 909 static int
 910 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 911                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 912 {
 913         struct hns3_hw *hw = &hns->hw;
 914         uint16_t old_pvid;
 915         int ret;
 916
 917         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 918                 old_pvid = hw->port_base_vlan_cfg.pvid;
 919                 if (old_pvid != HNS3_INVALID_PVID) {
 920                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 921                         if (ret) {
 922                                 hns3_err(hw, "failed to remove old pvid %u, "
 923                                                 "ret = %d", old_pvid, ret);
 924                                 return ret;
 925                         }
 926                 }
 927
 928                 hns3_rm_all_vlan_table(hns, false);
 929                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 930                 if (ret) {
 931                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 932                                         new_pvid, ret);
 933                         return ret;
 934                 }
 935         } else {
 936                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 937                 if (ret) {
 938                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 939                                         new_pvid, ret);
 940                         return ret;
 941                 }
 942
 943                 hns3_add_all_vlan_table(hns);
 944         }
 945         return 0;
 946 }
 947
 948 static int
 949 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 950 {
 951         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 952         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 953         bool rx_strip_en;
 954         int ret;
 955
 956         rx_strip_en = old_cfg->rx_vlan_offload_en;
 957         if (on) {
 958                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 959                 rx_vlan_cfg.strip_tag2_en = true;
 960                 rx_vlan_cfg.strip_tag2_discard_en = true;
 961         } else {
 962                 rx_vlan_cfg.strip_tag1_en = false;
 963                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 964                 rx_vlan_cfg.strip_tag2_discard_en = false;
 965         }
 966         rx_vlan_cfg.strip_tag1_discard_en = false;
 967         rx_vlan_cfg.vlan1_vlan_prionly = false;
 968         rx_vlan_cfg.vlan2_vlan_prionly = false;
 969         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 970
 971         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 972         if (ret)
 973                 return ret;
 974
 975         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 976         return ret;
 977 }
 978
 979 static int
 980 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         uint16_t port_base_vlan_state;
 984         int ret, err;
 985
 986         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 987                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 988                         hns3_warn(hw, "Invalid operation! As current pvid set "
 989                                   "is %u, disable pvid %u is invalid",
 990                                   hw->port_base_vlan_cfg.pvid, pvid);
 991                 return 0;
 992         }
 993
 994         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 995                                     HNS3_PORT_BASE_VLAN_DISABLE;
 996         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 997         if (ret) {
 998                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 999                          ret);
1000                 return ret;
1001         }
1002
1003         ret = hns3_en_pvid_strip(hns, on);
1004         if (ret) {
1005                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1006                          "ret = %d", ret);
1007                 goto pvid_vlan_strip_fail;
1008         }
1009
1010         if (pvid == HNS3_INVALID_PVID)
1011                 goto out;
1012         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1013         if (ret) {
1014                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1015                          ret);
1016                 goto vlan_filter_set_fail;
1017         }
1018
1019 out:
1020         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1021         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1022         return ret;
1023
1024 vlan_filter_set_fail:
1025         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1026                                         HNS3_PORT_BASE_VLAN_ENABLE);
1027         if (err)
1028                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1029
1030 pvid_vlan_strip_fail:
1031         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1032                                         hw->port_base_vlan_cfg.pvid);
1033         if (err)
1034                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1041 {
1042         struct hns3_adapter *hns = dev->data->dev_private;
1043         struct hns3_hw *hw = &hns->hw;
1044         bool pvid_en_state_change;
1045         uint16_t pvid_state;
1046         int ret;
1047
1048         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1049                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1050                          RTE_ETHER_MAX_VLAN_ID);
1051                 return -EINVAL;
1052         }
1053
1054         /*
1055          * If PVID configuration state change, should refresh the PVID
1056          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1057          */
1058         pvid_state = hw->port_base_vlan_cfg.state;
1059         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1060             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1061                 pvid_en_state_change = false;
1062         else
1063                 pvid_en_state_change = true;
1064
1065         rte_spinlock_lock(&hw->lock);
1066         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1067         rte_spinlock_unlock(&hw->lock);
1068         if (ret)
1069                 return ret;
1070         /*
1071          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1072          * need be processed by PMD driver.
1073          */
1074         if (pvid_en_state_change &&
1075             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1076                 hns3_update_all_queues_pvid_proc_en(hw);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_default_vlan_config(struct hns3_adapter *hns)
1083 {
1084         struct hns3_hw *hw = &hns->hw;
1085         int ret;
1086
1087         /*
1088          * When vlan filter is enabled, hardware regards packets without vlan
1089          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1090          * table, packets without vlan won't be received. So, add vlan 0 as
1091          * the default vlan.
1092          */
1093         ret = hns3_vlan_filter_configure(hns, 0, 1);
1094         if (ret)
1095                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1096         return ret;
1097 }
1098
1099 static int
1100 hns3_init_vlan_config(struct hns3_adapter *hns)
1101 {
1102         struct hns3_hw *hw = &hns->hw;
1103         int ret;
1104
1105         /*
1106          * This function can be called in the initialization and reset process,
1107          * when in reset process, it means that hardware had been reseted
1108          * successfully and we need to restore the hardware configuration to
1109          * ensure that the hardware configuration remains unchanged before and
1110          * after reset.
1111          */
1112         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1113                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1114                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1115         }
1116
1117         ret = hns3_vlan_filter_init(hns);
1118         if (ret) {
1119                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1120                 return ret;
1121         }
1122
1123         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1124                                        RTE_ETHER_TYPE_VLAN);
1125         if (ret) {
1126                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1127                 return ret;
1128         }
1129
1130         /*
1131          * When in the reinit dev stage of the reset process, the following
1132          * vlan-related configurations may differ from those at initialization,
1133          * we will restore configurations to hardware in hns3_restore_vlan_table
1134          * and hns3_restore_vlan_conf later.
1135          */
1136         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1137                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1138                 if (ret) {
1139                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1140                         return ret;
1141                 }
1142
1143                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1144                 if (ret) {
1145                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1146                                  ret);
1147                         return ret;
1148                 }
1149         }
1150
1151         return hns3_default_vlan_config(hns);
1152 }
1153
1154 static int
1155 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1156 {
1157         struct hns3_pf *pf = &hns->pf;
1158         struct hns3_hw *hw = &hns->hw;
1159         uint64_t offloads;
1160         bool enable;
1161         int ret;
1162
1163         if (!hw->data->promiscuous) {
1164                 /* restore vlan filter states */
1165                 offloads = hw->data->dev_conf.rxmode.offloads;
1166                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1167                 ret = hns3_enable_vlan_filter(hns, enable);
1168                 if (ret) {
1169                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1170                                  "ret = %d", ret);
1171                         return ret;
1172                 }
1173         }
1174
1175         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1176         if (ret) {
1177                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1178                 return ret;
1179         }
1180
1181         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1182         if (ret)
1183                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1184
1185         return ret;
1186 }
1187
1188 static int
1189 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1190 {
1191         struct hns3_adapter *hns = dev->data->dev_private;
1192         struct rte_eth_dev_data *data = dev->data;
1193         struct rte_eth_txmode *txmode;
1194         struct hns3_hw *hw = &hns->hw;
1195         int mask;
1196         int ret;
1197
1198         txmode = &data->dev_conf.txmode;
1199         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1200                 hns3_warn(hw,
1201                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1202                           "configuration is not supported! Ignore these two "
1203                           "parameters: hw_vlan_reject_tagged(%u), "
1204                           "hw_vlan_reject_untagged(%u)",
1205                           txmode->hw_vlan_reject_tagged,
1206                           txmode->hw_vlan_reject_untagged);
1207
1208         /* Apply vlan offload setting */
1209         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1210         ret = hns3_vlan_offload_set(dev, mask);
1211         if (ret) {
1212                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1213                          ret);
1214                 return ret;
1215         }
1216
1217         /*
1218          * If pvid config is not set in rte_eth_conf, driver needn't to set
1219          * VLAN pvid related configuration to hardware.
1220          */
1221         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1222                 return 0;
1223
1224         /* Apply pvid setting */
1225         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1226                                  txmode->hw_vlan_insert_pvid);
1227         if (ret)
1228                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1229                          txmode->pvid, ret);
1230
1231         return ret;
1232 }
1233
1234 static int
1235 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1236                 unsigned int tso_mss_max)
1237 {
1238         struct hns3_cfg_tso_status_cmd *req;
1239         struct hns3_cmd_desc desc;
1240         uint16_t tso_mss;
1241
1242         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1243
1244         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1245
1246         tso_mss = 0;
1247         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1248                        tso_mss_min);
1249         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1250
1251         tso_mss = 0;
1252         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1253                        tso_mss_max);
1254         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1255
1256         return hns3_cmd_send(hw, &desc, 1);
1257 }
1258
1259 static int
1260 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1261                    uint16_t *allocated_size, bool is_alloc)
1262 {
1263         struct hns3_umv_spc_alc_cmd *req;
1264         struct hns3_cmd_desc desc;
1265         int ret;
1266
1267         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1268         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1269         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1270         req->space_size = rte_cpu_to_le_32(space_size);
1271
1272         ret = hns3_cmd_send(hw, &desc, 1);
1273         if (ret) {
1274                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1275                              is_alloc ? "allocate" : "free", ret);
1276                 return ret;
1277         }
1278
1279         if (is_alloc && allocated_size)
1280                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1281
1282         return 0;
1283 }
1284
1285 static int
1286 hns3_init_umv_space(struct hns3_hw *hw)
1287 {
1288         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1289         struct hns3_pf *pf = &hns->pf;
1290         uint16_t allocated_size = 0;
1291         int ret;
1292
1293         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1294                                  true);
1295         if (ret)
1296                 return ret;
1297
1298         if (allocated_size < pf->wanted_umv_size)
1299                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1300                              pf->wanted_umv_size, allocated_size);
1301
1302         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1303                                                 pf->wanted_umv_size;
1304         pf->used_umv_size = 0;
1305         return 0;
1306 }
1307
1308 static int
1309 hns3_uninit_umv_space(struct hns3_hw *hw)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313         int ret;
1314
1315         if (pf->max_umv_size == 0)
1316                 return 0;
1317
1318         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1319         if (ret)
1320                 return ret;
1321
1322         pf->max_umv_size = 0;
1323
1324         return 0;
1325 }
1326
1327 static bool
1328 hns3_is_umv_space_full(struct hns3_hw *hw)
1329 {
1330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331         struct hns3_pf *pf = &hns->pf;
1332         bool is_full;
1333
1334         is_full = (pf->used_umv_size >= pf->max_umv_size);
1335
1336         return is_full;
1337 }
1338
1339 static void
1340 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1341 {
1342         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1343         struct hns3_pf *pf = &hns->pf;
1344
1345         if (is_free) {
1346                 if (pf->used_umv_size > 0)
1347                         pf->used_umv_size--;
1348         } else
1349                 pf->used_umv_size++;
1350 }
1351
1352 static void
1353 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1354                       const uint8_t *addr, bool is_mc)
1355 {
1356         const unsigned char *mac_addr = addr;
1357         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1358                             ((uint32_t)mac_addr[2] << 16) |
1359                             ((uint32_t)mac_addr[1] << 8) |
1360                             (uint32_t)mac_addr[0];
1361         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1362
1363         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1364         if (is_mc) {
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1366                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1367                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1368         }
1369
1370         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1371         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1372 }
1373
1374 static int
1375 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1376                              uint8_t resp_code,
1377                              enum hns3_mac_vlan_tbl_opcode op)
1378 {
1379         if (cmdq_resp) {
1380                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1381                          cmdq_resp);
1382                 return -EIO;
1383         }
1384
1385         if (op == HNS3_MAC_VLAN_ADD) {
1386                 if (resp_code == 0 || resp_code == 1) {
1387                         return 0;
1388                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1389                         hns3_err(hw, "add mac addr failed for uc_overflow");
1390                         return -ENOSPC;
1391                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1392                         hns3_err(hw, "add mac addr failed for mc_overflow");
1393                         return -ENOSPC;
1394                 }
1395
1396                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1397                          resp_code);
1398                 return -EIO;
1399         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1400                 if (resp_code == 0) {
1401                         return 0;
1402                 } else if (resp_code == 1) {
1403                         hns3_dbg(hw, "remove mac addr failed for miss");
1404                         return -ENOENT;
1405                 }
1406
1407                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1408                          resp_code);
1409                 return -EIO;
1410         } else if (op == HNS3_MAC_VLAN_LKUP) {
1411                 if (resp_code == 0) {
1412                         return 0;
1413                 } else if (resp_code == 1) {
1414                         hns3_dbg(hw, "lookup mac addr failed for miss");
1415                         return -ENOENT;
1416                 }
1417
1418                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1419                          resp_code);
1420                 return -EIO;
1421         }
1422
1423         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1424                  op);
1425
1426         return -EINVAL;
1427 }
1428
1429 static int
1430 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1431                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1432                          struct hns3_cmd_desc *desc, bool is_mc)
1433 {
1434         uint8_t resp_code;
1435         uint16_t retval;
1436         int ret;
1437
1438         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1439         if (is_mc) {
1440                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1441                 memcpy(desc[0].data, req,
1442                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1443                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1444                                           true);
1445                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1446                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1447                                           true);
1448                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1449         } else {
1450                 memcpy(desc[0].data, req,
1451                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1452                 ret = hns3_cmd_send(hw, desc, 1);
1453         }
1454         if (ret) {
1455                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1456                          ret);
1457                 return ret;
1458         }
1459         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1460         retval = rte_le_to_cpu_16(desc[0].retval);
1461
1462         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1463                                             HNS3_MAC_VLAN_LKUP);
1464 }
1465
1466 static int
1467 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1468                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1469                       struct hns3_cmd_desc *mc_desc)
1470 {
1471         uint8_t resp_code;
1472         uint16_t retval;
1473         int cfg_status;
1474         int ret;
1475
1476         if (mc_desc == NULL) {
1477                 struct hns3_cmd_desc desc;
1478
1479                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1480                 memcpy(desc.data, req,
1481                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1482                 ret = hns3_cmd_send(hw, &desc, 1);
1483                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1484                 retval = rte_le_to_cpu_16(desc.retval);
1485
1486                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1487                                                           HNS3_MAC_VLAN_ADD);
1488         } else {
1489                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1490                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1492                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1493                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1494                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1495                 memcpy(mc_desc[0].data, req,
1496                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1497                 mc_desc[0].retval = 0;
1498                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1499                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1500                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1501
1502                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1503                                                           HNS3_MAC_VLAN_ADD);
1504         }
1505
1506         if (ret) {
1507                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1508                 return ret;
1509         }
1510
1511         return cfg_status;
1512 }
1513
1514 static int
1515 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1516                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1517 {
1518         struct hns3_cmd_desc desc;
1519         uint8_t resp_code;
1520         uint16_t retval;
1521         int ret;
1522
1523         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1524
1525         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1526
1527         ret = hns3_cmd_send(hw, &desc, 1);
1528         if (ret) {
1529                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1530                 return ret;
1531         }
1532         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1533         retval = rte_le_to_cpu_16(desc.retval);
1534
1535         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1536                                             HNS3_MAC_VLAN_REMOVE);
1537 }
1538
1539 static int
1540 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1541 {
1542         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1543         struct hns3_mac_vlan_tbl_entry_cmd req;
1544         struct hns3_pf *pf = &hns->pf;
1545         struct hns3_cmd_desc desc[3];
1546         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1547         uint16_t egress_port = 0;
1548         uint8_t vf_id;
1549         int ret;
1550
1551         /* check if mac addr is valid */
1552         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1553                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1554                                       mac_addr);
1555                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1556                          mac_str);
1557                 return -EINVAL;
1558         }
1559
1560         memset(&req, 0, sizeof(req));
1561
1562         /*
1563          * In current version VF is not supported when PF is driven by DPDK
1564          * driver, just need to configure parameters for PF vport.
1565          */
1566         vf_id = HNS3_PF_FUNC_ID;
1567         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1568                        HNS3_MAC_EPORT_VFID_S, vf_id);
1569
1570         req.egress_port = rte_cpu_to_le_16(egress_port);
1571
1572         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1573
1574         /*
1575          * Lookup the mac address in the mac_vlan table, and add
1576          * it if the entry is inexistent. Repeated unicast entry
1577          * is not allowed in the mac vlan table.
1578          */
1579         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1580         if (ret == -ENOENT) {
1581                 if (!hns3_is_umv_space_full(hw)) {
1582                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1583                         if (!ret)
1584                                 hns3_update_umv_space(hw, false);
1585                         return ret;
1586                 }
1587
1588                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1589
1590                 return -ENOSPC;
1591         }
1592
1593         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1594
1595         /* check if we just hit the duplicate */
1596         if (ret == 0) {
1597                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1598                 return 0;
1599         }
1600
1601         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1602                  mac_str);
1603
1604         return ret;
1605 }
1606
1607 static int
1608 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1609 {
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         struct rte_ether_addr *addr;
1612         int ret;
1613         int i;
1614
1615         for (i = 0; i < hw->mc_addrs_num; i++) {
1616                 addr = &hw->mc_addrs[i];
1617                 /* Check if there are duplicate addresses */
1618                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1619                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1620                                               addr);
1621                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1622                                  "(%s) is added by the set_mc_mac_addr_list "
1623                                  "API", mac_str);
1624                         return -EINVAL;
1625                 }
1626         }
1627
1628         ret = hns3_add_mc_addr(hw, mac_addr);
1629         if (ret) {
1630                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1631                                       mac_addr);
1632                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1633                          mac_str, ret);
1634         }
1635         return ret;
1636 }
1637
1638 static int
1639 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1640 {
1641         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1642         int ret;
1643
1644         ret = hns3_remove_mc_addr(hw, mac_addr);
1645         if (ret) {
1646                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1647                                       mac_addr);
1648                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1649                          mac_str, ret);
1650         }
1651         return ret;
1652 }
1653
1654 static int
1655 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1656                   uint32_t idx, __rte_unused uint32_t pool)
1657 {
1658         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1660         int ret;
1661
1662         rte_spinlock_lock(&hw->lock);
1663
1664         /*
1665          * In hns3 network engine adding UC and MC mac address with different
1666          * commands with firmware. We need to determine whether the input
1667          * address is a UC or a MC address to call different commands.
1668          * By the way, it is recommended calling the API function named
1669          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1670          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1671          * may affect the specifications of UC mac addresses.
1672          */
1673         if (rte_is_multicast_ether_addr(mac_addr))
1674                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1675         else
1676                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1677
1678         if (ret) {
1679                 rte_spinlock_unlock(&hw->lock);
1680                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1681                                       mac_addr);
1682                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1683                          ret);
1684                 return ret;
1685         }
1686
1687         if (idx == 0)
1688                 hw->mac.default_addr_setted = true;
1689         rte_spinlock_unlock(&hw->lock);
1690
1691         return ret;
1692 }
1693
1694 static int
1695 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1696 {
1697         struct hns3_mac_vlan_tbl_entry_cmd req;
1698         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1699         int ret;
1700
1701         /* check if mac addr is valid */
1702         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1703                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1704                                       mac_addr);
1705                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1706                          mac_str);
1707                 return -EINVAL;
1708         }
1709
1710         memset(&req, 0, sizeof(req));
1711         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1712         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1713         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1714         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1715                 return 0;
1716         else if (ret == 0)
1717                 hns3_update_umv_space(hw, true);
1718
1719         return ret;
1720 }
1721
1722 static void
1723 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1724 {
1725         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         /* index will be checked by upper level rte interface */
1727         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1728         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1729         int ret;
1730
1731         rte_spinlock_lock(&hw->lock);
1732
1733         if (rte_is_multicast_ether_addr(mac_addr))
1734                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1735         else
1736                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1737         rte_spinlock_unlock(&hw->lock);
1738         if (ret) {
1739                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       mac_addr);
1741                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1742                          ret);
1743         }
1744 }
1745
1746 static int
1747 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1748                           struct rte_ether_addr *mac_addr)
1749 {
1750         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751         struct rte_ether_addr *oaddr;
1752         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1753         bool default_addr_setted;
1754         bool rm_succes = false;
1755         int ret, ret_val;
1756
1757         /*
1758          * It has been guaranteed that input parameter named mac_addr is valid
1759          * address in the rte layer of DPDK framework.
1760          */
1761         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1762         default_addr_setted = hw->mac.default_addr_setted;
1763         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1764                 return 0;
1765
1766         rte_spinlock_lock(&hw->lock);
1767         if (default_addr_setted) {
1768                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1769                 if (ret) {
1770                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1771                                               oaddr);
1772                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1773                                   mac_str, ret);
1774                         rm_succes = false;
1775                 } else
1776                         rm_succes = true;
1777         }
1778
1779         ret = hns3_add_uc_addr_common(hw, mac_addr);
1780         if (ret) {
1781                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1782                                       mac_addr);
1783                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1784                 goto err_add_uc_addr;
1785         }
1786
1787         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1788         if (ret) {
1789                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1790                 goto err_pause_addr_cfg;
1791         }
1792
1793         rte_ether_addr_copy(mac_addr,
1794                             (struct rte_ether_addr *)hw->mac.mac_addr);
1795         hw->mac.default_addr_setted = true;
1796         rte_spinlock_unlock(&hw->lock);
1797
1798         return 0;
1799
1800 err_pause_addr_cfg:
1801         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1802         if (ret_val) {
1803                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1804                                       mac_addr);
1805                 hns3_warn(hw,
1806                           "Failed to roll back to del setted mac addr(%s): %d",
1807                           mac_str, ret_val);
1808         }
1809
1810 err_add_uc_addr:
1811         if (rm_succes) {
1812                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1813                 if (ret_val) {
1814                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                               oaddr);
1816                         hns3_warn(hw,
1817                                   "Failed to restore old uc mac addr(%s): %d",
1818                                   mac_str, ret_val);
1819                         hw->mac.default_addr_setted = false;
1820                 }
1821         }
1822         rte_spinlock_unlock(&hw->lock);
1823
1824         return ret;
1825 }
1826
1827 static int
1828 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1829 {
1830         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1831         struct hns3_hw *hw = &hns->hw;
1832         struct rte_ether_addr *addr;
1833         int err = 0;
1834         int ret;
1835         int i;
1836
1837         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1838                 addr = &hw->data->mac_addrs[i];
1839                 if (rte_is_zero_ether_addr(addr))
1840                         continue;
1841                 if (rte_is_multicast_ether_addr(addr))
1842                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1843                               hns3_add_mc_addr(hw, addr);
1844                 else
1845                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1846                               hns3_add_uc_addr_common(hw, addr);
1847
1848                 if (ret) {
1849                         err = ret;
1850                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1851                                               addr);
1852                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1853                                  "ret = %d.", del ? "remove" : "restore",
1854                                  mac_str, i, ret);
1855                 }
1856         }
1857         return err;
1858 }
1859
1860 static void
1861 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1862 {
1863 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1864         uint8_t word_num;
1865         uint8_t bit_num;
1866
1867         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1868                 word_num = vfid / 32;
1869                 bit_num = vfid % 32;
1870                 if (clr)
1871                         desc[1].data[word_num] &=
1872                             rte_cpu_to_le_32(~(1UL << bit_num));
1873                 else
1874                         desc[1].data[word_num] |=
1875                             rte_cpu_to_le_32(1UL << bit_num);
1876         } else {
1877                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1878                 bit_num = vfid % 32;
1879                 if (clr)
1880                         desc[2].data[word_num] &=
1881                             rte_cpu_to_le_32(~(1UL << bit_num));
1882                 else
1883                         desc[2].data[word_num] |=
1884                             rte_cpu_to_le_32(1UL << bit_num);
1885         }
1886 }
1887
1888 static int
1889 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1890 {
1891         struct hns3_mac_vlan_tbl_entry_cmd req;
1892         struct hns3_cmd_desc desc[3];
1893         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1894         uint8_t vf_id;
1895         int ret;
1896
1897         /* Check if mac addr is valid */
1898         if (!rte_is_multicast_ether_addr(mac_addr)) {
1899                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1900                                       mac_addr);
1901                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1902                          mac_str);
1903                 return -EINVAL;
1904         }
1905
1906         memset(&req, 0, sizeof(req));
1907         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1908         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1909         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1910         if (ret) {
1911                 /* This mac addr do not exist, add new entry for it */
1912                 memset(desc[0].data, 0, sizeof(desc[0].data));
1913                 memset(desc[1].data, 0, sizeof(desc[0].data));
1914                 memset(desc[2].data, 0, sizeof(desc[0].data));
1915         }
1916
1917         /*
1918          * In current version VF is not supported when PF is driven by DPDK
1919          * driver, just need to configure parameters for PF vport.
1920          */
1921         vf_id = HNS3_PF_FUNC_ID;
1922         hns3_update_desc_vfid(desc, vf_id, false);
1923         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1924         if (ret) {
1925                 if (ret == -ENOSPC)
1926                         hns3_err(hw, "mc mac vlan table is full");
1927                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1928                                       mac_addr);
1929                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1930         }
1931
1932         return ret;
1933 }
1934
1935 static int
1936 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1937 {
1938         struct hns3_mac_vlan_tbl_entry_cmd req;
1939         struct hns3_cmd_desc desc[3];
1940         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1941         uint8_t vf_id;
1942         int ret;
1943
1944         /* Check if mac addr is valid */
1945         if (!rte_is_multicast_ether_addr(mac_addr)) {
1946                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1947                                       mac_addr);
1948                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1949                          mac_str);
1950                 return -EINVAL;
1951         }
1952
1953         memset(&req, 0, sizeof(req));
1954         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1955         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1956         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1957         if (ret == 0) {
1958                 /*
1959                  * This mac addr exist, remove this handle's VFID for it.
1960                  * In current version VF is not supported when PF is driven by
1961                  * DPDK driver, just need to configure parameters for PF vport.
1962                  */
1963                 vf_id = HNS3_PF_FUNC_ID;
1964                 hns3_update_desc_vfid(desc, vf_id, true);
1965
1966                 /* All the vfid is zero, so need to delete this entry */
1967                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1968         } else if (ret == -ENOENT) {
1969                 /* This mac addr doesn't exist. */
1970                 return 0;
1971         }
1972
1973         if (ret) {
1974                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1975                                       mac_addr);
1976                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1977         }
1978
1979         return ret;
1980 }
1981
1982 static int
1983 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1984                            struct rte_ether_addr *mc_addr_set,
1985                            uint32_t nb_mc_addr)
1986 {
1987         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1988         struct rte_ether_addr *addr;
1989         uint32_t i;
1990         uint32_t j;
1991
1992         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1993                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1994                          "invalid. valid range: 0~%d",
1995                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1996                 return -EINVAL;
1997         }
1998
1999         /* Check if input mac addresses are valid */
2000         for (i = 0; i < nb_mc_addr; i++) {
2001                 addr = &mc_addr_set[i];
2002                 if (!rte_is_multicast_ether_addr(addr)) {
2003                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2004                                               addr);
2005                         hns3_err(hw,
2006                                  "failed to set mc mac addr, addr(%s) invalid.",
2007                                  mac_str);
2008                         return -EINVAL;
2009                 }
2010
2011                 /* Check if there are duplicate addresses */
2012                 for (j = i + 1; j < nb_mc_addr; j++) {
2013                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2014                                 hns3_ether_format_addr(mac_str,
2015                                                       RTE_ETHER_ADDR_FMT_SIZE,
2016                                                       addr);
2017                                 hns3_err(hw, "failed to set mc mac addr, "
2018                                          "addrs invalid. two same addrs(%s).",
2019                                          mac_str);
2020                                 return -EINVAL;
2021                         }
2022                 }
2023
2024                 /*
2025                  * Check if there are duplicate addresses between mac_addrs
2026                  * and mc_addr_set
2027                  */
2028                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2029                         if (rte_is_same_ether_addr(addr,
2030                                                    &hw->data->mac_addrs[j])) {
2031                                 hns3_ether_format_addr(mac_str,
2032                                                       RTE_ETHER_ADDR_FMT_SIZE,
2033                                                       addr);
2034                                 hns3_err(hw, "failed to set mc mac addr, "
2035                                          "addrs invalid. addrs(%s) has already "
2036                                          "configured in mac_addr add API",
2037                                          mac_str);
2038                                 return -EINVAL;
2039                         }
2040                 }
2041         }
2042
2043         return 0;
2044 }
2045
2046 static void
2047 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2048                            struct rte_ether_addr *mc_addr_set,
2049                            int mc_addr_num,
2050                            struct rte_ether_addr *reserved_addr_list,
2051                            int *reserved_addr_num,
2052                            struct rte_ether_addr *add_addr_list,
2053                            int *add_addr_num,
2054                            struct rte_ether_addr *rm_addr_list,
2055                            int *rm_addr_num)
2056 {
2057         struct rte_ether_addr *addr;
2058         int current_addr_num;
2059         int reserved_num = 0;
2060         int add_num = 0;
2061         int rm_num = 0;
2062         int num;
2063         int i;
2064         int j;
2065         bool same_addr;
2066
2067         /* Calculate the mc mac address list that should be removed */
2068         current_addr_num = hw->mc_addrs_num;
2069         for (i = 0; i < current_addr_num; i++) {
2070                 addr = &hw->mc_addrs[i];
2071                 same_addr = false;
2072                 for (j = 0; j < mc_addr_num; j++) {
2073                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2074                                 same_addr = true;
2075                                 break;
2076                         }
2077                 }
2078
2079                 if (!same_addr) {
2080                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2081                         rm_num++;
2082                 } else {
2083                         rte_ether_addr_copy(addr,
2084                                             &reserved_addr_list[reserved_num]);
2085                         reserved_num++;
2086                 }
2087         }
2088
2089         /* Calculate the mc mac address list that should be added */
2090         for (i = 0; i < mc_addr_num; i++) {
2091                 addr = &mc_addr_set[i];
2092                 same_addr = false;
2093                 for (j = 0; j < current_addr_num; j++) {
2094                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2095                                 same_addr = true;
2096                                 break;
2097                         }
2098                 }
2099
2100                 if (!same_addr) {
2101                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2102                         add_num++;
2103                 }
2104         }
2105
2106         /* Reorder the mc mac address list maintained by driver */
2107         for (i = 0; i < reserved_num; i++)
2108                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2109
2110         for (i = 0; i < rm_num; i++) {
2111                 num = reserved_num + i;
2112                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2113         }
2114
2115         *reserved_addr_num = reserved_num;
2116         *add_addr_num = add_num;
2117         *rm_addr_num = rm_num;
2118 }
2119
2120 static int
2121 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2122                           struct rte_ether_addr *mc_addr_set,
2123                           uint32_t nb_mc_addr)
2124 {
2125         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2129         struct rte_ether_addr *addr;
2130         int reserved_addr_num;
2131         int add_addr_num;
2132         int rm_addr_num;
2133         int mc_addr_num;
2134         int num;
2135         int ret;
2136         int i;
2137
2138         /* Check if input parameters are valid */
2139         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2140         if (ret)
2141                 return ret;
2142
2143         rte_spinlock_lock(&hw->lock);
2144
2145         /*
2146          * Calculate the mc mac address lists those should be removed and be
2147          * added, Reorder the mc mac address list maintained by driver.
2148          */
2149         mc_addr_num = (int)nb_mc_addr;
2150         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2151                                    reserved_addr_list, &reserved_addr_num,
2152                                    add_addr_list, &add_addr_num,
2153                                    rm_addr_list, &rm_addr_num);
2154
2155         /* Remove mc mac addresses */
2156         for (i = 0; i < rm_addr_num; i++) {
2157                 num = rm_addr_num - i - 1;
2158                 addr = &rm_addr_list[num];
2159                 ret = hns3_remove_mc_addr(hw, addr);
2160                 if (ret) {
2161                         rte_spinlock_unlock(&hw->lock);
2162                         return ret;
2163                 }
2164                 hw->mc_addrs_num--;
2165         }
2166
2167         /* Add mc mac addresses */
2168         for (i = 0; i < add_addr_num; i++) {
2169                 addr = &add_addr_list[i];
2170                 ret = hns3_add_mc_addr(hw, addr);
2171                 if (ret) {
2172                         rte_spinlock_unlock(&hw->lock);
2173                         return ret;
2174                 }
2175
2176                 num = reserved_addr_num + i;
2177                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2178                 hw->mc_addrs_num++;
2179         }
2180         rte_spinlock_unlock(&hw->lock);
2181
2182         return 0;
2183 }
2184
2185 static int
2186 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2187 {
2188         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2189         struct hns3_hw *hw = &hns->hw;
2190         struct rte_ether_addr *addr;
2191         int err = 0;
2192         int ret;
2193         int i;
2194
2195         for (i = 0; i < hw->mc_addrs_num; i++) {
2196                 addr = &hw->mc_addrs[i];
2197                 if (!rte_is_multicast_ether_addr(addr))
2198                         continue;
2199                 if (del)
2200                         ret = hns3_remove_mc_addr(hw, addr);
2201                 else
2202                         ret = hns3_add_mc_addr(hw, addr);
2203                 if (ret) {
2204                         err = ret;
2205                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2206                                               addr);
2207                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2208                                  del ? "Remove" : "Restore", mac_str, ret);
2209                 }
2210         }
2211         return err;
2212 }
2213
2214 static int
2215 hns3_check_mq_mode(struct rte_eth_dev *dev)
2216 {
2217         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2218         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2219         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2222         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2223         uint8_t num_tc;
2224         int max_tc = 0;
2225         int i;
2226
2227         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2228         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2229
2230         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2231                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2232                          "rx_mq_mode = %d", rx_mq_mode);
2233                 return -EINVAL;
2234         }
2235
2236         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2237             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2238                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2239                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2240                          rx_mq_mode, tx_mq_mode);
2241                 return -EINVAL;
2242         }
2243
2244         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2245                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2246                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2247                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2252                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2253                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2254                                  "nb_tcs(%d) != %d or %d in rx direction.",
2255                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2256                         return -EINVAL;
2257                 }
2258
2259                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2260                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2261                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2262                         return -EINVAL;
2263                 }
2264
2265                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2266                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2267                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2268                                          "is not equal to one in tx direction.",
2269                                          i, dcb_rx_conf->dcb_tc[i]);
2270                                 return -EINVAL;
2271                         }
2272                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2273                                 max_tc = dcb_rx_conf->dcb_tc[i];
2274                 }
2275
2276                 num_tc = max_tc + 1;
2277                 if (num_tc > dcb_rx_conf->nb_tcs) {
2278                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2279                                  num_tc, dcb_rx_conf->nb_tcs);
2280                         return -EINVAL;
2281                 }
2282         }
2283
2284         return 0;
2285 }
2286
2287 static int
2288 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2289 {
2290         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291
2292         if (!hns3_dev_dcb_supported(hw)) {
2293                 hns3_err(hw, "this port does not support dcb configurations.");
2294                 return -EOPNOTSUPP;
2295         }
2296
2297         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2298                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2299                 return -EOPNOTSUPP;
2300         }
2301
2302         /* Check multiple queue mode */
2303         return hns3_check_mq_mode(dev);
2304 }
2305
2306 static int
2307 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2308                            enum hns3_ring_type queue_type, uint16_t queue_id)
2309 {
2310         struct hns3_cmd_desc desc;
2311         struct hns3_ctrl_vector_chain_cmd *req =
2312                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2313         enum hns3_opcode_type op;
2314         uint16_t tqp_type_and_id = 0;
2315         uint16_t type;
2316         uint16_t gl;
2317         int ret;
2318
2319         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2320         hns3_cmd_setup_basic_desc(&desc, op, false);
2321         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2322                                               HNS3_TQP_INT_ID_L_S);
2323         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2324                                               HNS3_TQP_INT_ID_H_S);
2325
2326         if (queue_type == HNS3_RING_TYPE_RX)
2327                 gl = HNS3_RING_GL_RX;
2328         else
2329                 gl = HNS3_RING_GL_TX;
2330
2331         type = queue_type;
2332
2333         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2334                        type);
2335         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2336         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2337                        gl);
2338         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2339         req->int_cause_num = 1;
2340         ret = hns3_cmd_send(hw, &desc, 1);
2341         if (ret) {
2342                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2343                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2344                 return ret;
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int
2351 hns3_init_ring_with_vector(struct hns3_hw *hw)
2352 {
2353         uint16_t vec;
2354         int ret;
2355         int i;
2356
2357         /*
2358          * In hns3 network engine, vector 0 is always the misc interrupt of this
2359          * function, vector 1~N can be used respectively for the queues of the
2360          * function. Tx and Rx queues with the same number share the interrupt
2361          * vector. In the initialization clearing the all hardware mapping
2362          * relationship configurations between queues and interrupt vectors is
2363          * needed, so some error caused by the residual configurations, such as
2364          * the unexpected Tx interrupt, can be avoid.
2365          */
2366         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2367         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2368                 vec = vec - 1; /* the last interrupt is reserved */
2369         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2370         for (i = 0; i < hw->intr_tqps_num; i++) {
2371                 /*
2372                  * Set gap limiter/rate limiter/quanity limiter algorithm
2373                  * configuration for interrupt coalesce of queue's interrupt.
2374                  */
2375                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2376                                        HNS3_TQP_INTR_GL_DEFAULT);
2377                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2378                                        HNS3_TQP_INTR_GL_DEFAULT);
2379                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2380                 /*
2381                  * QL(quantity limiter) is not used currently, just set 0 to
2382                  * close it.
2383                  */
2384                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2385
2386                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2387                                                  HNS3_RING_TYPE_TX, i);
2388                 if (ret) {
2389                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2390                                           "vector: %u, ret=%d", i, vec, ret);
2391                         return ret;
2392                 }
2393
2394                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2395                                                  HNS3_RING_TYPE_RX, i);
2396                 if (ret) {
2397                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2398                                           "vector: %u, ret=%d", i, vec, ret);
2399                         return ret;
2400                 }
2401         }
2402
2403         return 0;
2404 }
2405
2406 static int
2407 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2408 {
2409         struct hns3_adapter *hns = dev->data->dev_private;
2410         struct hns3_hw *hw = &hns->hw;
2411         uint32_t max_rx_pkt_len;
2412         uint16_t mtu;
2413         int ret;
2414
2415         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2416                 return 0;
2417
2418         /*
2419          * If jumbo frames are enabled, MTU needs to be refreshed
2420          * according to the maximum RX packet length.
2421          */
2422         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2423         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2424             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2425                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2426                          "and no more than %u when jumbo frame enabled.",
2427                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2428                          (uint16_t)HNS3_MAX_FRAME_LEN);
2429                 return -EINVAL;
2430         }
2431
2432         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2433         ret = hns3_dev_mtu_set(dev, mtu);
2434         if (ret)
2435                 return ret;
2436         dev->data->mtu = mtu;
2437
2438         return 0;
2439 }
2440
2441 static int
2442 hns3_dev_configure(struct rte_eth_dev *dev)
2443 {
2444         struct hns3_adapter *hns = dev->data->dev_private;
2445         struct rte_eth_conf *conf = &dev->data->dev_conf;
2446         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2447         struct hns3_hw *hw = &hns->hw;
2448         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2449         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2450         struct rte_eth_rss_conf rss_conf;
2451         bool gro_en;
2452         int ret;
2453
2454         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2455
2456         /*
2457          * Some versions of hardware network engine does not support
2458          * individually enable/disable/reset the Tx or Rx queue. These devices
2459          * must enable/disable/reset Tx and Rx queues at the same time. When the
2460          * numbers of Tx queues allocated by upper applications are not equal to
2461          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2462          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2463          * work as usual. But these fake queues are imperceptible, and can not
2464          * be used by upper applications.
2465          */
2466         if (!hns3_dev_indep_txrx_supported(hw)) {
2467                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2468                 if (ret) {
2469                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2470                                  ret);
2471                         return ret;
2472                 }
2473         }
2474
2475         hw->adapter_state = HNS3_NIC_CONFIGURING;
2476         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2477                 ret = hns3_check_dcb_cfg(dev);
2478                 if (ret)
2479                         goto cfg_err;
2480         }
2481
2482         /* When RSS is not configured, redirect the packet queue 0 */
2483         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2484                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2485                 rss_conf = conf->rx_adv_conf.rss_conf;
2486                 hw->rss_dis_flag = false;
2487                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2488                 if (ret)
2489                         goto cfg_err;
2490         }
2491
2492         ret = hns3_refresh_mtu(dev, conf);
2493         if (ret)
2494                 goto cfg_err;
2495
2496         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2497         if (ret)
2498                 goto cfg_err;
2499
2500         ret = hns3_dev_configure_vlan(dev);
2501         if (ret)
2502                 goto cfg_err;
2503
2504         /* config hardware GRO */
2505         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2506         ret = hns3_config_gro(hw, gro_en);
2507         if (ret)
2508                 goto cfg_err;
2509
2510         hns3_init_rx_ptype_tble(dev);
2511         hw->adapter_state = HNS3_NIC_CONFIGURED;
2512
2513         return 0;
2514
2515 cfg_err:
2516         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2517         hw->adapter_state = HNS3_NIC_INITIALIZED;
2518
2519         return ret;
2520 }
2521
2522 static int
2523 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2524 {
2525         struct hns3_config_max_frm_size_cmd *req;
2526         struct hns3_cmd_desc desc;
2527
2528         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2529
2530         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2531         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2532         req->min_frm_size = RTE_ETHER_MIN_LEN;
2533
2534         return hns3_cmd_send(hw, &desc, 1);
2535 }
2536
2537 static int
2538 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2539 {
2540         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2541         uint16_t original_mps = hns->pf.mps;
2542         int err;
2543         int ret;
2544
2545         ret = hns3_set_mac_mtu(hw, mps);
2546         if (ret) {
2547                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2548                 return ret;
2549         }
2550
2551         hns->pf.mps = mps;
2552         ret = hns3_buffer_alloc(hw);
2553         if (ret) {
2554                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2555                 goto rollback;
2556         }
2557
2558         return 0;
2559
2560 rollback:
2561         err = hns3_set_mac_mtu(hw, original_mps);
2562         if (err) {
2563                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2564                 return ret;
2565         }
2566         hns->pf.mps = original_mps;
2567
2568         return ret;
2569 }
2570
2571 static int
2572 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2573 {
2574         struct hns3_adapter *hns = dev->data->dev_private;
2575         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2576         struct hns3_hw *hw = &hns->hw;
2577         bool is_jumbo_frame;
2578         int ret;
2579
2580         if (dev->data->dev_started) {
2581                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2582                          "before configuration", dev->data->port_id);
2583                 return -EBUSY;
2584         }
2585
2586         rte_spinlock_lock(&hw->lock);
2587         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2588         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2589
2590         /*
2591          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2592          * assign to "uint16_t" type variable.
2593          */
2594         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2595         if (ret) {
2596                 rte_spinlock_unlock(&hw->lock);
2597                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2598                          dev->data->port_id, mtu, ret);
2599                 return ret;
2600         }
2601
2602         if (is_jumbo_frame)
2603                 dev->data->dev_conf.rxmode.offloads |=
2604                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2605         else
2606                 dev->data->dev_conf.rxmode.offloads &=
2607                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2608         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2609         rte_spinlock_unlock(&hw->lock);
2610
2611         return 0;
2612 }
2613
2614 static uint32_t
2615 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2616 {
2617         uint32_t speed_capa = 0;
2618
2619         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2620                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2621         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2622                 speed_capa |= ETH_LINK_SPEED_10M;
2623         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2624                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2625         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2626                 speed_capa |= ETH_LINK_SPEED_100M;
2627         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2628                 speed_capa |= ETH_LINK_SPEED_1G;
2629
2630         return speed_capa;
2631 }
2632
2633 static uint32_t
2634 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2635 {
2636         uint32_t speed_capa = 0;
2637
2638         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2639                 speed_capa |= ETH_LINK_SPEED_1G;
2640         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2641                 speed_capa |= ETH_LINK_SPEED_10G;
2642         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2643                 speed_capa |= ETH_LINK_SPEED_25G;
2644         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2645                 speed_capa |= ETH_LINK_SPEED_40G;
2646         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2647                 speed_capa |= ETH_LINK_SPEED_50G;
2648         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2649                 speed_capa |= ETH_LINK_SPEED_100G;
2650         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2651                 speed_capa |= ETH_LINK_SPEED_200G;
2652
2653         return speed_capa;
2654 }
2655
2656 static uint32_t
2657 hns3_get_speed_capa(struct hns3_hw *hw)
2658 {
2659         struct hns3_mac *mac = &hw->mac;
2660         uint32_t speed_capa;
2661
2662         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2663                 speed_capa =
2664                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2665         else
2666                 speed_capa =
2667                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2668
2669         if (mac->support_autoneg == 0)
2670                 speed_capa |= ETH_LINK_SPEED_FIXED;
2671
2672         return speed_capa;
2673 }
2674
2675 int
2676 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2677 {
2678         struct hns3_adapter *hns = eth_dev->data->dev_private;
2679         struct hns3_hw *hw = &hns->hw;
2680         uint16_t queue_num = hw->tqps_num;
2681
2682         /*
2683          * In interrupt mode, 'max_rx_queues' is set based on the number of
2684          * MSI-X interrupt resources of the hardware.
2685          */
2686         if (hw->data->dev_conf.intr_conf.rxq == 1)
2687                 queue_num = hw->intr_tqps_num;
2688
2689         info->max_rx_queues = queue_num;
2690         info->max_tx_queues = hw->tqps_num;
2691         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2692         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2693         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2694         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2695         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2696         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2697                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2698                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2699                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2700                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2701                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2702                                  DEV_RX_OFFLOAD_KEEP_CRC |
2703                                  DEV_RX_OFFLOAD_SCATTER |
2704                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2705                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2706                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2707                                  DEV_RX_OFFLOAD_RSS_HASH |
2708                                  DEV_RX_OFFLOAD_TCP_LRO);
2709         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2710                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2711                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2712                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2713                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2714                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2715                                  DEV_TX_OFFLOAD_TCP_TSO |
2716                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2717                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2718                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2719                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2720                                  hns3_txvlan_cap_get(hw));
2721
2722         if (hns3_dev_outer_udp_cksum_supported(hw))
2723                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2724
2725         if (hns3_dev_indep_txrx_supported(hw))
2726                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2727                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2728
2729         if (hns3_dev_ptp_supported(hw))
2730                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2731
2732         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2733                 .nb_max = HNS3_MAX_RING_DESC,
2734                 .nb_min = HNS3_MIN_RING_DESC,
2735                 .nb_align = HNS3_ALIGN_RING_DESC,
2736         };
2737
2738         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2739                 .nb_max = HNS3_MAX_RING_DESC,
2740                 .nb_min = HNS3_MIN_RING_DESC,
2741                 .nb_align = HNS3_ALIGN_RING_DESC,
2742                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2743                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2744         };
2745
2746         info->speed_capa = hns3_get_speed_capa(hw);
2747         info->default_rxconf = (struct rte_eth_rxconf) {
2748                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2749                 /*
2750                  * If there are no available Rx buffer descriptors, incoming
2751                  * packets are always dropped by hardware based on hns3 network
2752                  * engine.
2753                  */
2754                 .rx_drop_en = 1,
2755                 .offloads = 0,
2756         };
2757         info->default_txconf = (struct rte_eth_txconf) {
2758                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2759                 .offloads = 0,
2760         };
2761
2762         info->vmdq_queue_num = 0;
2763
2764         info->reta_size = hw->rss_ind_tbl_size;
2765         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2766         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2767
2768         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2769         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2770         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2771         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2772         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2773         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2774
2775         return 0;
2776 }
2777
2778 static int
2779 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2780                     size_t fw_size)
2781 {
2782         struct hns3_adapter *hns = eth_dev->data->dev_private;
2783         struct hns3_hw *hw = &hns->hw;
2784         uint32_t version = hw->fw_version;
2785         int ret;
2786
2787         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2788                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2789                                       HNS3_FW_VERSION_BYTE3_S),
2790                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2791                                       HNS3_FW_VERSION_BYTE2_S),
2792                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2793                                       HNS3_FW_VERSION_BYTE1_S),
2794                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2795                                       HNS3_FW_VERSION_BYTE0_S));
2796         ret += 1; /* add the size of '\0' */
2797         if (fw_size < (uint32_t)ret)
2798                 return ret;
2799         else
2800                 return 0;
2801 }
2802
2803 static int
2804 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2805 {
2806         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2807         int ret;
2808
2809         (void)hns3_update_link_status(hw);
2810
2811         ret = hns3_update_link_info(eth_dev);
2812         if (ret)
2813                 hw->mac.link_status = ETH_LINK_DOWN;
2814
2815         return ret;
2816 }
2817
2818 static void
2819 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2820                       struct rte_eth_link *new_link)
2821 {
2822         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2823         struct hns3_mac *mac = &hw->mac;
2824
2825         switch (mac->link_speed) {
2826         case ETH_SPEED_NUM_10M:
2827         case ETH_SPEED_NUM_100M:
2828         case ETH_SPEED_NUM_1G:
2829         case ETH_SPEED_NUM_10G:
2830         case ETH_SPEED_NUM_25G:
2831         case ETH_SPEED_NUM_40G:
2832         case ETH_SPEED_NUM_50G:
2833         case ETH_SPEED_NUM_100G:
2834         case ETH_SPEED_NUM_200G:
2835                 new_link->link_speed = mac->link_speed;
2836                 break;
2837         default:
2838                 if (mac->link_status)
2839                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2840                 else
2841                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2842                 break;
2843         }
2844
2845         new_link->link_duplex = mac->link_duplex;
2846         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2847         new_link->link_autoneg = mac->link_autoneg;
2848 }
2849
2850 static int
2851 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2852 {
2853 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2854 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2855
2856         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2857         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2858         struct hns3_mac *mac = &hw->mac;
2859         struct rte_eth_link new_link;
2860         int ret;
2861
2862         do {
2863                 ret = hns3_update_port_link_info(eth_dev);
2864                 if (ret) {
2865                         hns3_err(hw, "failed to get port link info, ret = %d.",
2866                                  ret);
2867                         break;
2868                 }
2869
2870                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2871                         break;
2872
2873                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2874         } while (retry_cnt--);
2875
2876         memset(&new_link, 0, sizeof(new_link));
2877         hns3_setup_linkstatus(eth_dev, &new_link);
2878
2879         return rte_eth_linkstatus_set(eth_dev, &new_link);
2880 }
2881
2882 static int
2883 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2884 {
2885         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2886         struct hns3_pf *pf = &hns->pf;
2887
2888         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2889                 return -EINVAL;
2890
2891         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2892
2893         return 0;
2894 }
2895
2896 static int
2897 hns3_query_function_status(struct hns3_hw *hw)
2898 {
2899 #define HNS3_QUERY_MAX_CNT              10
2900 #define HNS3_QUERY_SLEEP_MSCOEND        1
2901         struct hns3_func_status_cmd *req;
2902         struct hns3_cmd_desc desc;
2903         int timeout = 0;
2904         int ret;
2905
2906         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2907         req = (struct hns3_func_status_cmd *)desc.data;
2908
2909         do {
2910                 ret = hns3_cmd_send(hw, &desc, 1);
2911                 if (ret) {
2912                         PMD_INIT_LOG(ERR, "query function status failed %d",
2913                                      ret);
2914                         return ret;
2915                 }
2916
2917                 /* Check pf reset is done */
2918                 if (req->pf_state)
2919                         break;
2920
2921                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2922         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2923
2924         return hns3_parse_func_status(hw, req);
2925 }
2926
2927 static int
2928 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2929 {
2930         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2931         struct hns3_pf *pf = &hns->pf;
2932
2933         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2934                 /*
2935                  * The total_tqps_num obtained from firmware is maximum tqp
2936                  * numbers of this port, which should be used for PF and VFs.
2937                  * There is no need for pf to have so many tqp numbers in
2938                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2939                  * coming from config file, is assigned to maximum queue number
2940                  * for the PF of this port by user. So users can modify the
2941                  * maximum queue number of PF according to their own application
2942                  * scenarios, which is more flexible to use. In addition, many
2943                  * memories can be saved due to allocating queue statistics
2944                  * room according to the actual number of queues required. The
2945                  * maximum queue number of PF for network engine with
2946                  * revision_id greater than 0x30 is assigned by config file.
2947                  */
2948                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2949                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2950                                  "must be greater than 0.",
2951                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2952                         return -EINVAL;
2953                 }
2954
2955                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2956                                        hw->total_tqps_num);
2957         } else {
2958                 /*
2959                  * Due to the limitation on the number of PF interrupts
2960                  * available, the maximum queue number assigned to PF on
2961                  * the network engine with revision_id 0x21 is 64.
2962                  */
2963                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2964                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2965         }
2966
2967         return 0;
2968 }
2969
2970 static int
2971 hns3_query_pf_resource(struct hns3_hw *hw)
2972 {
2973         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2974         struct hns3_pf *pf = &hns->pf;
2975         struct hns3_pf_res_cmd *req;
2976         struct hns3_cmd_desc desc;
2977         int ret;
2978
2979         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2980         ret = hns3_cmd_send(hw, &desc, 1);
2981         if (ret) {
2982                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2983                 return ret;
2984         }
2985
2986         req = (struct hns3_pf_res_cmd *)desc.data;
2987         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2988                              rte_le_to_cpu_16(req->ext_tqp_num);
2989         ret = hns3_get_pf_max_tqp_num(hw);
2990         if (ret)
2991                 return ret;
2992
2993         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2994         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2995
2996         if (req->tx_buf_size)
2997                 pf->tx_buf_size =
2998                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2999         else
3000                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3001
3002         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3003
3004         if (req->dv_buf_size)
3005                 pf->dv_buf_size =
3006                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3007         else
3008                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3009
3010         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3011
3012         hw->num_msi =
3013                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3014                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3015
3016         return 0;
3017 }
3018
3019 static void
3020 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3021 {
3022         struct hns3_cfg_param_cmd *req;
3023         uint64_t mac_addr_tmp_high;
3024         uint8_t ext_rss_size_max;
3025         uint64_t mac_addr_tmp;
3026         uint32_t i;
3027
3028         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3029
3030         /* get the configuration */
3031         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3032                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3033         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3034                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3035         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3036                                            HNS3_CFG_TQP_DESC_N_M,
3037                                            HNS3_CFG_TQP_DESC_N_S);
3038
3039         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3040                                        HNS3_CFG_PHY_ADDR_M,
3041                                        HNS3_CFG_PHY_ADDR_S);
3042         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3043                                          HNS3_CFG_MEDIA_TP_M,
3044                                          HNS3_CFG_MEDIA_TP_S);
3045         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3046                                          HNS3_CFG_RX_BUF_LEN_M,
3047                                          HNS3_CFG_RX_BUF_LEN_S);
3048         /* get mac address */
3049         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3050         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3051                                            HNS3_CFG_MAC_ADDR_H_M,
3052                                            HNS3_CFG_MAC_ADDR_H_S);
3053
3054         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3055
3056         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3057                                             HNS3_CFG_DEFAULT_SPEED_M,
3058                                             HNS3_CFG_DEFAULT_SPEED_S);
3059         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3060                                            HNS3_CFG_RSS_SIZE_M,
3061                                            HNS3_CFG_RSS_SIZE_S);
3062
3063         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3064                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3065
3066         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3067         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3068
3069         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3070                                             HNS3_CFG_SPEED_ABILITY_M,
3071                                             HNS3_CFG_SPEED_ABILITY_S);
3072         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3073                                         HNS3_CFG_UMV_TBL_SPACE_M,
3074                                         HNS3_CFG_UMV_TBL_SPACE_S);
3075         if (!cfg->umv_space)
3076                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3077
3078         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3079                                                HNS3_CFG_EXT_RSS_SIZE_M,
3080                                                HNS3_CFG_EXT_RSS_SIZE_S);
3081
3082         /*
3083          * Field ext_rss_size_max obtained from firmware will be more flexible
3084          * for future changes and expansions, which is an exponent of 2, instead
3085          * of reading out directly. If this field is not zero, hns3 PF PMD
3086          * driver uses it as rss_size_max under one TC. Device, whose revision
3087          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3088          * maximum number of queues supported under a TC through this field.
3089          */
3090         if (ext_rss_size_max)
3091                 cfg->rss_size_max = 1U << ext_rss_size_max;
3092 }
3093
3094 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3095  * @hw: pointer to struct hns3_hw
3096  * @hcfg: the config structure to be getted
3097  */
3098 static int
3099 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3100 {
3101         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3102         struct hns3_cfg_param_cmd *req;
3103         uint32_t offset;
3104         uint32_t i;
3105         int ret;
3106
3107         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3108                 offset = 0;
3109                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3110                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3111                                           true);
3112                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3113                                i * HNS3_CFG_RD_LEN_BYTES);
3114                 /* Len should be divided by 4 when send to hardware */
3115                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3116                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3117                 req->offset = rte_cpu_to_le_32(offset);
3118         }
3119
3120         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3121         if (ret) {
3122                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3123                 return ret;
3124         }
3125
3126         hns3_parse_cfg(hcfg, desc);
3127
3128         return 0;
3129 }
3130
3131 static int
3132 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3133 {
3134         switch (speed_cmd) {
3135         case HNS3_CFG_SPEED_10M:
3136                 *speed = ETH_SPEED_NUM_10M;
3137                 break;
3138         case HNS3_CFG_SPEED_100M:
3139                 *speed = ETH_SPEED_NUM_100M;
3140                 break;
3141         case HNS3_CFG_SPEED_1G:
3142                 *speed = ETH_SPEED_NUM_1G;
3143                 break;
3144         case HNS3_CFG_SPEED_10G:
3145                 *speed = ETH_SPEED_NUM_10G;
3146                 break;
3147         case HNS3_CFG_SPEED_25G:
3148                 *speed = ETH_SPEED_NUM_25G;
3149                 break;
3150         case HNS3_CFG_SPEED_40G:
3151                 *speed = ETH_SPEED_NUM_40G;
3152                 break;
3153         case HNS3_CFG_SPEED_50G:
3154                 *speed = ETH_SPEED_NUM_50G;
3155                 break;
3156         case HNS3_CFG_SPEED_100G:
3157                 *speed = ETH_SPEED_NUM_100G;
3158                 break;
3159         case HNS3_CFG_SPEED_200G:
3160                 *speed = ETH_SPEED_NUM_200G;
3161                 break;
3162         default:
3163                 return -EINVAL;
3164         }
3165
3166         return 0;
3167 }
3168
3169 static void
3170 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3171 {
3172         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3173         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3174         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3175         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3176         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3177 }
3178
3179 static void
3180 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3181 {
3182         struct hns3_dev_specs_0_cmd *req0;
3183
3184         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3185
3186         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3187         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3188         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3189         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3190         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3191 }
3192
3193 static int
3194 hns3_check_dev_specifications(struct hns3_hw *hw)
3195 {
3196         if (hw->rss_ind_tbl_size == 0 ||
3197             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3198                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3199                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3200                               HNS3_RSS_IND_TBL_SIZE_MAX);
3201                 return -EINVAL;
3202         }
3203
3204         return 0;
3205 }
3206
3207 static int
3208 hns3_query_dev_specifications(struct hns3_hw *hw)
3209 {
3210         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3211         int ret;
3212         int i;
3213
3214         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3215                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3216                                           true);
3217                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3218         }
3219         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3220
3221         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3222         if (ret)
3223                 return ret;
3224
3225         hns3_parse_dev_specifications(hw, desc);
3226
3227         return hns3_check_dev_specifications(hw);
3228 }
3229
3230 static int
3231 hns3_get_capability(struct hns3_hw *hw)
3232 {
3233         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3234         struct rte_pci_device *pci_dev;
3235         struct hns3_pf *pf = &hns->pf;
3236         struct rte_eth_dev *eth_dev;
3237         uint16_t device_id;
3238         uint8_t revision;
3239         int ret;
3240
3241         eth_dev = &rte_eth_devices[hw->data->port_id];
3242         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3243         device_id = pci_dev->id.device_id;
3244
3245         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3246             device_id == HNS3_DEV_ID_50GE_RDMA ||
3247             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3248             device_id == HNS3_DEV_ID_200G_RDMA)
3249                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3250
3251         /* Get PCI revision id */
3252         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3253                                   HNS3_PCI_REVISION_ID);
3254         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3255                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3256                              ret);
3257                 return -EIO;
3258         }
3259         hw->revision = revision;
3260
3261         if (revision < PCI_REVISION_ID_HIP09_A) {
3262                 hns3_set_default_dev_specifications(hw);
3263                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3264                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3265                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3266                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3267                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3268                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3269                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3270                 hw->rss_info.ipv6_sctp_offload_supported = false;
3271                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3272                 return 0;
3273         }
3274
3275         ret = hns3_query_dev_specifications(hw);
3276         if (ret) {
3277                 PMD_INIT_LOG(ERR,
3278                              "failed to query dev specifications, ret = %d",
3279                              ret);
3280                 return ret;
3281         }
3282
3283         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3284         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3285         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3286         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3287         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3288         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3289         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3290         hw->rss_info.ipv6_sctp_offload_supported = true;
3291         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3292
3293         return 0;
3294 }
3295
3296 static int
3297 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3298 {
3299         int ret;
3300
3301         switch (media_type) {
3302         case HNS3_MEDIA_TYPE_COPPER:
3303                 if (!hns3_dev_copper_supported(hw)) {
3304                         PMD_INIT_LOG(ERR,
3305                                      "Media type is copper, not supported.");
3306                         ret = -EOPNOTSUPP;
3307                 } else {
3308                         ret = 0;
3309                 }
3310                 break;
3311         case HNS3_MEDIA_TYPE_FIBER:
3312                 ret = 0;
3313                 break;
3314         case HNS3_MEDIA_TYPE_BACKPLANE:
3315                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3316                 ret = -EOPNOTSUPP;
3317                 break;
3318         default:
3319                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3320                 ret = -EINVAL;
3321                 break;
3322         }
3323
3324         return ret;
3325 }
3326
3327 static int
3328 hns3_get_board_configuration(struct hns3_hw *hw)
3329 {
3330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3331         struct hns3_pf *pf = &hns->pf;
3332         struct hns3_cfg cfg;
3333         int ret;
3334
3335         ret = hns3_get_board_cfg(hw, &cfg);
3336         if (ret) {
3337                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3338                 return ret;
3339         }
3340
3341         ret = hns3_check_media_type(hw, cfg.media_type);
3342         if (ret)
3343                 return ret;
3344
3345         hw->mac.media_type = cfg.media_type;
3346         hw->rss_size_max = cfg.rss_size_max;
3347         hw->rss_dis_flag = false;
3348         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3349         hw->mac.phy_addr = cfg.phy_addr;
3350         hw->mac.default_addr_setted = false;
3351         hw->num_tx_desc = cfg.tqp_desc_num;
3352         hw->num_rx_desc = cfg.tqp_desc_num;
3353         hw->dcb_info.num_pg = 1;
3354         hw->dcb_info.hw_pfc_map = 0;
3355
3356         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3357         if (ret) {
3358                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3359                              cfg.default_speed, ret);
3360                 return ret;
3361         }
3362
3363         pf->tc_max = cfg.tc_num;
3364         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3365                 PMD_INIT_LOG(WARNING,
3366                              "Get TC num(%u) from flash, set TC num to 1",
3367                              pf->tc_max);
3368                 pf->tc_max = 1;
3369         }
3370
3371         /* Dev does not support DCB */
3372         if (!hns3_dev_dcb_supported(hw)) {
3373                 pf->tc_max = 1;
3374                 pf->pfc_max = 0;
3375         } else
3376                 pf->pfc_max = pf->tc_max;
3377
3378         hw->dcb_info.num_tc = 1;
3379         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3380                                      hw->tqps_num / hw->dcb_info.num_tc);
3381         hns3_set_bit(hw->hw_tc_map, 0, 1);
3382         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3383
3384         pf->wanted_umv_size = cfg.umv_space;
3385
3386         return ret;
3387 }
3388
3389 static int
3390 hns3_get_configuration(struct hns3_hw *hw)
3391 {
3392         int ret;
3393
3394         ret = hns3_query_function_status(hw);
3395         if (ret) {
3396                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3397                 return ret;
3398         }
3399
3400         /* Get device capability */
3401         ret = hns3_get_capability(hw);
3402         if (ret) {
3403                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3404                 return ret;
3405         }
3406
3407         /* Get pf resource */
3408         ret = hns3_query_pf_resource(hw);
3409         if (ret) {
3410                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3411                 return ret;
3412         }
3413
3414         ret = hns3_get_board_configuration(hw);
3415         if (ret) {
3416                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3417                 return ret;
3418         }
3419
3420         ret = hns3_query_dev_fec_info(hw);
3421         if (ret)
3422                 PMD_INIT_LOG(ERR,
3423                              "failed to query FEC information, ret = %d", ret);
3424
3425         return ret;
3426 }
3427
3428 static int
3429 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3430                       uint16_t tqp_vid, bool is_pf)
3431 {
3432         struct hns3_tqp_map_cmd *req;
3433         struct hns3_cmd_desc desc;
3434         int ret;
3435
3436         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3437
3438         req = (struct hns3_tqp_map_cmd *)desc.data;
3439         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3440         req->tqp_vf = func_id;
3441         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3442         if (!is_pf)
3443                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3444         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3445
3446         ret = hns3_cmd_send(hw, &desc, 1);
3447         if (ret)
3448                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3449
3450         return ret;
3451 }
3452
3453 static int
3454 hns3_map_tqp(struct hns3_hw *hw)
3455 {
3456         int ret;
3457         int i;
3458
3459         /*
3460          * In current version, VF is not supported when PF is driven by DPDK
3461          * driver, so we assign total tqps_num tqps allocated to this port
3462          * to PF.
3463          */
3464         for (i = 0; i < hw->total_tqps_num; i++) {
3465                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3466                 if (ret)
3467                         return ret;
3468         }
3469
3470         return 0;
3471 }
3472
3473 static int
3474 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3475 {
3476         struct hns3_config_mac_speed_dup_cmd *req;
3477         struct hns3_cmd_desc desc;
3478         int ret;
3479
3480         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3481
3482         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3483
3484         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3485
3486         switch (speed) {
3487         case ETH_SPEED_NUM_10M:
3488                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3489                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3490                 break;
3491         case ETH_SPEED_NUM_100M:
3492                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3493                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3494                 break;
3495         case ETH_SPEED_NUM_1G:
3496                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3497                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3498                 break;
3499         case ETH_SPEED_NUM_10G:
3500                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3501                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3502                 break;
3503         case ETH_SPEED_NUM_25G:
3504                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3505                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3506                 break;
3507         case ETH_SPEED_NUM_40G:
3508                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3509                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3510                 break;
3511         case ETH_SPEED_NUM_50G:
3512                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3513                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3514                 break;
3515         case ETH_SPEED_NUM_100G:
3516                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3517                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3518                 break;
3519         case ETH_SPEED_NUM_200G:
3520                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3521                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3522                 break;
3523         default:
3524                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3525                 return -EINVAL;
3526         }
3527
3528         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3529
3530         ret = hns3_cmd_send(hw, &desc, 1);
3531         if (ret)
3532                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3533
3534         return ret;
3535 }
3536
3537 static int
3538 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3539 {
3540         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3541         struct hns3_pf *pf = &hns->pf;
3542         struct hns3_priv_buf *priv;
3543         uint32_t i, total_size;
3544
3545         total_size = pf->pkt_buf_size;
3546
3547         /* alloc tx buffer for all enabled tc */
3548         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3549                 priv = &buf_alloc->priv_buf[i];
3550
3551                 if (hw->hw_tc_map & BIT(i)) {
3552                         if (total_size < pf->tx_buf_size)
3553                                 return -ENOMEM;
3554
3555                         priv->tx_buf_size = pf->tx_buf_size;
3556                 } else
3557                         priv->tx_buf_size = 0;
3558
3559                 total_size -= priv->tx_buf_size;
3560         }
3561
3562         return 0;
3563 }
3564
3565 static int
3566 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3567 {
3568 /* TX buffer size is unit by 128 byte */
3569 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3570 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3571         struct hns3_tx_buff_alloc_cmd *req;
3572         struct hns3_cmd_desc desc;
3573         uint32_t buf_size;
3574         uint32_t i;
3575         int ret;
3576
3577         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3578
3579         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3580         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3581                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3582
3583                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3584                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3585                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3586         }
3587
3588         ret = hns3_cmd_send(hw, &desc, 1);
3589         if (ret)
3590                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3591
3592         return ret;
3593 }
3594
3595 static int
3596 hns3_get_tc_num(struct hns3_hw *hw)
3597 {
3598         int cnt = 0;
3599         uint8_t i;
3600
3601         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3602                 if (hw->hw_tc_map & BIT(i))
3603                         cnt++;
3604         return cnt;
3605 }
3606
3607 static uint32_t
3608 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3609 {
3610         struct hns3_priv_buf *priv;
3611         uint32_t rx_priv = 0;
3612         int i;
3613
3614         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3615                 priv = &buf_alloc->priv_buf[i];
3616                 if (priv->enable)
3617                         rx_priv += priv->buf_size;
3618         }
3619         return rx_priv;
3620 }
3621
3622 static uint32_t
3623 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3624 {
3625         uint32_t total_tx_size = 0;
3626         uint32_t i;
3627
3628         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3629                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3630
3631         return total_tx_size;
3632 }
3633
3634 /* Get the number of pfc enabled TCs, which have private buffer */
3635 static int
3636 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3637 {
3638         struct hns3_priv_buf *priv;
3639         int cnt = 0;
3640         uint8_t i;
3641
3642         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3643                 priv = &buf_alloc->priv_buf[i];
3644                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3645                         cnt++;
3646         }
3647
3648         return cnt;
3649 }
3650
3651 /* Get the number of pfc disabled TCs, which have private buffer */
3652 static int
3653 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3654                          struct hns3_pkt_buf_alloc *buf_alloc)
3655 {
3656         struct hns3_priv_buf *priv;
3657         int cnt = 0;
3658         uint8_t i;
3659
3660         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3661                 priv = &buf_alloc->priv_buf[i];
3662                 if (hw->hw_tc_map & BIT(i) &&
3663                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3664                         cnt++;
3665         }
3666
3667         return cnt;
3668 }
3669
3670 static bool
3671 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3672                   uint32_t rx_all)
3673 {
3674         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3675         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3676         struct hns3_pf *pf = &hns->pf;
3677         uint32_t shared_buf, aligned_mps;
3678         uint32_t rx_priv;
3679         uint8_t tc_num;
3680         uint8_t i;
3681
3682         tc_num = hns3_get_tc_num(hw);
3683         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3684
3685         if (hns3_dev_dcb_supported(hw))
3686                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3687                                         pf->dv_buf_size;
3688         else
3689                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3690                                         + pf->dv_buf_size;
3691
3692         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3693         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3694                              HNS3_BUF_SIZE_UNIT);
3695
3696         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3697         if (rx_all < rx_priv + shared_std)
3698                 return false;
3699
3700         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3701         buf_alloc->s_buf.buf_size = shared_buf;
3702         if (hns3_dev_dcb_supported(hw)) {
3703                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3704                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3705                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3706                                   HNS3_BUF_SIZE_UNIT);
3707         } else {
3708                 buf_alloc->s_buf.self.high =
3709                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3710                 buf_alloc->s_buf.self.low = aligned_mps;
3711         }
3712
3713         if (hns3_dev_dcb_supported(hw)) {
3714                 hi_thrd = shared_buf - pf->dv_buf_size;
3715
3716                 if (tc_num <= NEED_RESERVE_TC_NUM)
3717                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3718                                   BUF_MAX_PERCENT;
3719
3720                 if (tc_num)
3721                         hi_thrd = hi_thrd / tc_num;
3722
3723                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3724                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3725                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3726         } else {
3727                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3728                 lo_thrd = aligned_mps;
3729         }
3730
3731         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3732                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3733                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3734         }
3735
3736         return true;
3737 }
3738
3739 static bool
3740 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3741                      struct hns3_pkt_buf_alloc *buf_alloc)
3742 {
3743         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3744         struct hns3_pf *pf = &hns->pf;
3745         struct hns3_priv_buf *priv;
3746         uint32_t aligned_mps;
3747         uint32_t rx_all;
3748         uint8_t i;
3749
3750         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3751         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3752
3753         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3754                 priv = &buf_alloc->priv_buf[i];
3755
3756                 priv->enable = 0;
3757                 priv->wl.low = 0;
3758                 priv->wl.high = 0;
3759                 priv->buf_size = 0;
3760
3761                 if (!(hw->hw_tc_map & BIT(i)))
3762                         continue;
3763
3764                 priv->enable = 1;
3765                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3766                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3767                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3768                                                 HNS3_BUF_SIZE_UNIT);
3769                 } else {
3770                         priv->wl.low = 0;
3771                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3772                                         aligned_mps;
3773                 }
3774
3775                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3776         }
3777
3778         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3779 }
3780
3781 static bool
3782 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3783                              struct hns3_pkt_buf_alloc *buf_alloc)
3784 {
3785         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3786         struct hns3_pf *pf = &hns->pf;
3787         struct hns3_priv_buf *priv;
3788         int no_pfc_priv_num;
3789         uint32_t rx_all;
3790         uint8_t mask;
3791         int i;
3792
3793         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3794         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3795
3796         /* let the last to be cleared first */
3797         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3798                 priv = &buf_alloc->priv_buf[i];
3799                 mask = BIT((uint8_t)i);
3800
3801                 if (hw->hw_tc_map & mask &&
3802                     !(hw->dcb_info.hw_pfc_map & mask)) {
3803                         /* Clear the no pfc TC private buffer */
3804                         priv->wl.low = 0;
3805                         priv->wl.high = 0;
3806                         priv->buf_size = 0;
3807                         priv->enable = 0;
3808                         no_pfc_priv_num--;
3809                 }
3810
3811                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3812                     no_pfc_priv_num == 0)
3813                         break;
3814         }
3815
3816         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3817 }
3818
3819 static bool
3820 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3821                            struct hns3_pkt_buf_alloc *buf_alloc)
3822 {
3823         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3824         struct hns3_pf *pf = &hns->pf;
3825         struct hns3_priv_buf *priv;
3826         uint32_t rx_all;
3827         int pfc_priv_num;
3828         uint8_t mask;
3829         int i;
3830
3831         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3832         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3833
3834         /* let the last to be cleared first */
3835         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3836                 priv = &buf_alloc->priv_buf[i];
3837                 mask = BIT((uint8_t)i);
3838                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3839                         /* Reduce the number of pfc TC with private buffer */
3840                         priv->wl.low = 0;
3841                         priv->enable = 0;
3842                         priv->wl.high = 0;
3843                         priv->buf_size = 0;
3844                         pfc_priv_num--;
3845                 }
3846                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3847                     pfc_priv_num == 0)
3848                         break;
3849         }
3850
3851         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3852 }
3853
3854 static bool
3855 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3856                           struct hns3_pkt_buf_alloc *buf_alloc)
3857 {
3858 #define COMPENSATE_BUFFER       0x3C00
3859 #define COMPENSATE_HALF_MPS_NUM 5
3860 #define PRIV_WL_GAP             0x1800
3861         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3862         struct hns3_pf *pf = &hns->pf;
3863         uint32_t tc_num = hns3_get_tc_num(hw);
3864         uint32_t half_mps = pf->mps >> 1;
3865         struct hns3_priv_buf *priv;
3866         uint32_t min_rx_priv;
3867         uint32_t rx_priv;
3868         uint8_t i;
3869
3870         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3871         if (tc_num)
3872                 rx_priv = rx_priv / tc_num;
3873
3874         if (tc_num <= NEED_RESERVE_TC_NUM)
3875                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3876
3877         /*
3878          * Minimum value of private buffer in rx direction (min_rx_priv) is
3879          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3880          * buffer if rx_priv is greater than min_rx_priv.
3881          */
3882         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3883                         COMPENSATE_HALF_MPS_NUM * half_mps;
3884         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3885         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3886
3887         if (rx_priv < min_rx_priv)
3888                 return false;
3889
3890         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3891                 priv = &buf_alloc->priv_buf[i];
3892                 priv->enable = 0;
3893                 priv->wl.low = 0;
3894                 priv->wl.high = 0;
3895                 priv->buf_size = 0;
3896
3897                 if (!(hw->hw_tc_map & BIT(i)))
3898                         continue;
3899
3900                 priv->enable = 1;
3901                 priv->buf_size = rx_priv;
3902                 priv->wl.high = rx_priv - pf->dv_buf_size;
3903                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3904         }
3905
3906         buf_alloc->s_buf.buf_size = 0;
3907
3908         return true;
3909 }
3910
3911 /*
3912  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3913  * @hw: pointer to struct hns3_hw
3914  * @buf_alloc: pointer to buffer calculation data
3915  * @return: 0: calculate sucessful, negative: fail
3916  */
3917 static int
3918 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3919 {
3920         /* When DCB is not supported, rx private buffer is not allocated. */
3921         if (!hns3_dev_dcb_supported(hw)) {
3922                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3923                 struct hns3_pf *pf = &hns->pf;
3924                 uint32_t rx_all = pf->pkt_buf_size;
3925
3926                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3927                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3928                         return -ENOMEM;
3929
3930                 return 0;
3931         }
3932
3933         /*
3934          * Try to allocate privated packet buffer for all TCs without share
3935          * buffer.
3936          */
3937         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3938                 return 0;
3939
3940         /*
3941          * Try to allocate privated packet buffer for all TCs with share
3942          * buffer.
3943          */
3944         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3945                 return 0;
3946
3947         /*
3948          * For different application scenes, the enabled port number, TC number
3949          * and no_drop TC number are different. In order to obtain the better
3950          * performance, software could allocate the buffer size and configure
3951          * the waterline by tring to decrease the private buffer size according
3952          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3953          * enabled tc.
3954          */
3955         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3956                 return 0;
3957
3958         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3959                 return 0;
3960
3961         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3962                 return 0;
3963
3964         return -ENOMEM;
3965 }
3966
3967 static int
3968 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3969 {
3970         struct hns3_rx_priv_buff_cmd *req;
3971         struct hns3_cmd_desc desc;
3972         uint32_t buf_size;
3973         int ret;
3974         int i;
3975
3976         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3977         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3978
3979         /* Alloc private buffer TCs */
3980         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3981                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3982
3983                 req->buf_num[i] =
3984                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3985                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3986         }
3987
3988         buf_size = buf_alloc->s_buf.buf_size;
3989         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3990                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3991
3992         ret = hns3_cmd_send(hw, &desc, 1);
3993         if (ret)
3994                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3995
3996         return ret;
3997 }
3998
3999 static int
4000 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4001 {
4002 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4003         struct hns3_rx_priv_wl_buf *req;
4004         struct hns3_priv_buf *priv;
4005         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4006         int i, j;
4007         int ret;
4008
4009         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4010                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4011                                           false);
4012                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4013
4014                 /* The first descriptor set the NEXT bit to 1 */
4015                 if (i == 0)
4016                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4017                 else
4018                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4019
4020                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4021                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4022
4023                         priv = &buf_alloc->priv_buf[idx];
4024                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4025                                                         HNS3_BUF_UNIT_S);
4026                         req->tc_wl[j].high |=
4027                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4028                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4029                                                         HNS3_BUF_UNIT_S);
4030                         req->tc_wl[j].low |=
4031                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4032                 }
4033         }
4034
4035         /* Send 2 descriptor at one time */
4036         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4037         if (ret)
4038                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4039                              ret);
4040         return ret;
4041 }
4042
4043 static int
4044 hns3_common_thrd_config(struct hns3_hw *hw,
4045                         struct hns3_pkt_buf_alloc *buf_alloc)
4046 {
4047 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4048         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4049         struct hns3_rx_com_thrd *req;
4050         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4051         struct hns3_tc_thrd *tc;
4052         int tc_idx;
4053         int i, j;
4054         int ret;
4055
4056         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4057                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4058                                           false);
4059                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4060
4061                 /* The first descriptor set the NEXT bit to 1 */
4062                 if (i == 0)
4063                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4064                 else
4065                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4066
4067                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4068                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4069                         tc = &s_buf->tc_thrd[tc_idx];
4070
4071                         req->com_thrd[j].high =
4072                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4073                         req->com_thrd[j].high |=
4074                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4075                         req->com_thrd[j].low =
4076                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4077                         req->com_thrd[j].low |=
4078                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4079                 }
4080         }
4081
4082         /* Send 2 descriptors at one time */
4083         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4084         if (ret)
4085                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4086
4087         return ret;
4088 }
4089
4090 static int
4091 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4092 {
4093         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4094         struct hns3_rx_com_wl *req;
4095         struct hns3_cmd_desc desc;
4096         int ret;
4097
4098         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4099
4100         req = (struct hns3_rx_com_wl *)desc.data;
4101         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4102         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4103
4104         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4105         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4106
4107         ret = hns3_cmd_send(hw, &desc, 1);
4108         if (ret)
4109                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4110
4111         return ret;
4112 }
4113
4114 int
4115 hns3_buffer_alloc(struct hns3_hw *hw)
4116 {
4117         struct hns3_pkt_buf_alloc pkt_buf;
4118         int ret;
4119
4120         memset(&pkt_buf, 0, sizeof(pkt_buf));
4121         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4122         if (ret) {
4123                 PMD_INIT_LOG(ERR,
4124                              "could not calc tx buffer size for all TCs %d",
4125                              ret);
4126                 return ret;
4127         }
4128
4129         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4130         if (ret) {
4131                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4132                 return ret;
4133         }
4134
4135         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4136         if (ret) {
4137                 PMD_INIT_LOG(ERR,
4138                              "could not calc rx priv buffer size for all TCs %d",
4139                              ret);
4140                 return ret;
4141         }
4142
4143         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4144         if (ret) {
4145                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4146                 return ret;
4147         }
4148
4149         if (hns3_dev_dcb_supported(hw)) {
4150                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4151                 if (ret) {
4152                         PMD_INIT_LOG(ERR,
4153                                      "could not configure rx private waterline %d",
4154                                      ret);
4155                         return ret;
4156                 }
4157
4158                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4159                 if (ret) {
4160                         PMD_INIT_LOG(ERR,
4161                                      "could not configure common threshold %d",
4162                                      ret);
4163                         return ret;
4164                 }
4165         }
4166
4167         ret = hns3_common_wl_config(hw, &pkt_buf);
4168         if (ret)
4169                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4170                              ret);
4171
4172         return ret;
4173 }
4174
4175 static int
4176 hns3_mac_init(struct hns3_hw *hw)
4177 {
4178         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4179         struct hns3_mac *mac = &hw->mac;
4180         struct hns3_pf *pf = &hns->pf;
4181         int ret;
4182
4183         pf->support_sfp_query = true;
4184         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4185         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4186         if (ret) {
4187                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4188                 return ret;
4189         }
4190
4191         mac->link_status = ETH_LINK_DOWN;
4192
4193         return hns3_config_mtu(hw, pf->mps);
4194 }
4195
4196 static int
4197 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4198 {
4199 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4200 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4201 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4202 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4203         int return_status;
4204
4205         if (cmdq_resp) {
4206                 PMD_INIT_LOG(ERR,
4207                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4208                              cmdq_resp);
4209                 return -EIO;
4210         }
4211
4212         switch (resp_code) {
4213         case HNS3_ETHERTYPE_SUCCESS_ADD:
4214         case HNS3_ETHERTYPE_ALREADY_ADD:
4215                 return_status = 0;
4216                 break;
4217         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4218                 PMD_INIT_LOG(ERR,
4219                              "add mac ethertype failed for manager table overflow.");
4220                 return_status = -EIO;
4221                 break;
4222         case HNS3_ETHERTYPE_KEY_CONFLICT:
4223                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4224                 return_status = -EIO;
4225                 break;
4226         default:
4227                 PMD_INIT_LOG(ERR,
4228                              "add mac ethertype failed for undefined, code=%u.",
4229                              resp_code);
4230                 return_status = -EIO;
4231                 break;
4232         }
4233
4234         return return_status;
4235 }
4236
4237 static int
4238 hns3_add_mgr_tbl(struct hns3_hw *hw,
4239                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4240 {
4241         struct hns3_cmd_desc desc;
4242         uint8_t resp_code;
4243         uint16_t retval;
4244         int ret;
4245
4246         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4247         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4248
4249         ret = hns3_cmd_send(hw, &desc, 1);
4250         if (ret) {
4251                 PMD_INIT_LOG(ERR,
4252                              "add mac ethertype failed for cmd_send, ret =%d.",
4253                              ret);
4254                 return ret;
4255         }
4256
4257         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4258         retval = rte_le_to_cpu_16(desc.retval);
4259
4260         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4261 }
4262
4263 static void
4264 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4265                      int *table_item_num)
4266 {
4267         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4268
4269         /*
4270          * In current version, we add one item in management table as below:
4271          * 0x0180C200000E -- LLDP MC address
4272          */
4273         tbl = mgr_table;
4274         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4275         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4276         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4277         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4278         tbl->i_port_bitmap = 0x1;
4279         *table_item_num = 1;
4280 }
4281
4282 static int
4283 hns3_init_mgr_tbl(struct hns3_hw *hw)
4284 {
4285 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4286         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4287         int table_item_num;
4288         int ret;
4289         int i;
4290
4291         memset(mgr_table, 0, sizeof(mgr_table));
4292         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4293         for (i = 0; i < table_item_num; i++) {
4294                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4295                 if (ret) {
4296                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4297                                      ret);
4298                         return ret;
4299                 }
4300         }
4301
4302         return 0;
4303 }
4304
4305 static void
4306 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4307                         bool en_mc, bool en_bc, int vport_id)
4308 {
4309         if (!param)
4310                 return;
4311
4312         memset(param, 0, sizeof(struct hns3_promisc_param));
4313         if (en_uc)
4314                 param->enable = HNS3_PROMISC_EN_UC;
4315         if (en_mc)
4316                 param->enable |= HNS3_PROMISC_EN_MC;
4317         if (en_bc)
4318                 param->enable |= HNS3_PROMISC_EN_BC;
4319         param->vf_id = vport_id;
4320 }
4321
4322 static int
4323 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4324 {
4325         struct hns3_promisc_cfg_cmd *req;
4326         struct hns3_cmd_desc desc;
4327         int ret;
4328
4329         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4330
4331         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4332         req->vf_id = param->vf_id;
4333         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4334             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4335
4336         ret = hns3_cmd_send(hw, &desc, 1);
4337         if (ret)
4338                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4339
4340         return ret;
4341 }
4342
4343 static int
4344 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4345 {
4346         struct hns3_promisc_param param;
4347         bool en_bc_pmc = true;
4348         uint8_t vf_id;
4349
4350         /*
4351          * In current version VF is not supported when PF is driven by DPDK
4352          * driver, just need to configure parameters for PF vport.
4353          */
4354         vf_id = HNS3_PF_FUNC_ID;
4355
4356         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4357         return hns3_cmd_set_promisc_mode(hw, &param);
4358 }
4359
4360 static int
4361 hns3_promisc_init(struct hns3_hw *hw)
4362 {
4363         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4364         struct hns3_pf *pf = &hns->pf;
4365         struct hns3_promisc_param param;
4366         uint16_t func_id;
4367         int ret;
4368
4369         ret = hns3_set_promisc_mode(hw, false, false);
4370         if (ret) {
4371                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4372                 return ret;
4373         }
4374
4375         /*
4376          * In current version VFs are not supported when PF is driven by DPDK
4377          * driver. After PF has been taken over by DPDK, the original VF will
4378          * be invalid. So, there is a possibility of entry residues. It should
4379          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4380          * during init.
4381          */
4382         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4383                 hns3_promisc_param_init(&param, false, false, false, func_id);
4384                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4385                 if (ret) {
4386                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4387                                         " ret = %d", func_id, ret);
4388                         return ret;
4389                 }
4390         }
4391
4392         return 0;
4393 }
4394
4395 static void
4396 hns3_promisc_uninit(struct hns3_hw *hw)
4397 {
4398         struct hns3_promisc_param param;
4399         uint16_t func_id;
4400         int ret;
4401
4402         func_id = HNS3_PF_FUNC_ID;
4403
4404         /*
4405          * In current version VFs are not supported when PF is driven by
4406          * DPDK driver, and VFs' promisc mode status has been cleared during
4407          * init and their status will not change. So just clear PF's promisc
4408          * mode status during uninit.
4409          */
4410         hns3_promisc_param_init(&param, false, false, false, func_id);
4411         ret = hns3_cmd_set_promisc_mode(hw, &param);
4412         if (ret)
4413                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4414                                 " uninit, ret = %d", ret);
4415 }
4416
4417 static int
4418 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4419 {
4420         bool allmulti = dev->data->all_multicast ? true : false;
4421         struct hns3_adapter *hns = dev->data->dev_private;
4422         struct hns3_hw *hw = &hns->hw;
4423         uint64_t offloads;
4424         int err;
4425         int ret;
4426
4427         rte_spinlock_lock(&hw->lock);
4428         ret = hns3_set_promisc_mode(hw, true, true);
4429         if (ret) {
4430                 rte_spinlock_unlock(&hw->lock);
4431                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4432                          ret);
4433                 return ret;
4434         }
4435
4436         /*
4437          * When promiscuous mode was enabled, disable the vlan filter to let
4438          * all packets coming in in the receiving direction.
4439          */
4440         offloads = dev->data->dev_conf.rxmode.offloads;
4441         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4442                 ret = hns3_enable_vlan_filter(hns, false);
4443                 if (ret) {
4444                         hns3_err(hw, "failed to enable promiscuous mode due to "
4445                                      "failure to disable vlan filter, ret = %d",
4446                                  ret);
4447                         err = hns3_set_promisc_mode(hw, false, allmulti);
4448                         if (err)
4449                                 hns3_err(hw, "failed to restore promiscuous "
4450                                          "status after disable vlan filter "
4451                                          "failed during enabling promiscuous "
4452                                          "mode, ret = %d", ret);
4453                 }
4454         }
4455
4456         rte_spinlock_unlock(&hw->lock);
4457
4458         return ret;
4459 }
4460
4461 static int
4462 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4463 {
4464         bool allmulti = dev->data->all_multicast ? true : false;
4465         struct hns3_adapter *hns = dev->data->dev_private;
4466         struct hns3_hw *hw = &hns->hw;
4467         uint64_t offloads;
4468         int err;
4469         int ret;
4470
4471         /* If now in all_multicast mode, must remain in all_multicast mode. */
4472         rte_spinlock_lock(&hw->lock);
4473         ret = hns3_set_promisc_mode(hw, false, allmulti);
4474         if (ret) {
4475                 rte_spinlock_unlock(&hw->lock);
4476                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4477                          ret);
4478                 return ret;
4479         }
4480         /* when promiscuous mode was disabled, restore the vlan filter status */
4481         offloads = dev->data->dev_conf.rxmode.offloads;
4482         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4483                 ret = hns3_enable_vlan_filter(hns, true);
4484                 if (ret) {
4485                         hns3_err(hw, "failed to disable promiscuous mode due to"
4486                                  " failure to restore vlan filter, ret = %d",
4487                                  ret);
4488                         err = hns3_set_promisc_mode(hw, true, true);
4489                         if (err)
4490                                 hns3_err(hw, "failed to restore promiscuous "
4491                                          "status after enabling vlan filter "
4492                                          "failed during disabling promiscuous "
4493                                          "mode, ret = %d", ret);
4494                 }
4495         }
4496         rte_spinlock_unlock(&hw->lock);
4497
4498         return ret;
4499 }
4500
4501 static int
4502 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4503 {
4504         struct hns3_adapter *hns = dev->data->dev_private;
4505         struct hns3_hw *hw = &hns->hw;
4506         int ret;
4507
4508         if (dev->data->promiscuous)
4509                 return 0;
4510
4511         rte_spinlock_lock(&hw->lock);
4512         ret = hns3_set_promisc_mode(hw, false, true);
4513         rte_spinlock_unlock(&hw->lock);
4514         if (ret)
4515                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4516                          ret);
4517
4518         return ret;
4519 }
4520
4521 static int
4522 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4523 {
4524         struct hns3_adapter *hns = dev->data->dev_private;
4525         struct hns3_hw *hw = &hns->hw;
4526         int ret;
4527
4528         /* If now in promiscuous mode, must remain in all_multicast mode. */
4529         if (dev->data->promiscuous)
4530                 return 0;
4531
4532         rte_spinlock_lock(&hw->lock);
4533         ret = hns3_set_promisc_mode(hw, false, false);
4534         rte_spinlock_unlock(&hw->lock);
4535         if (ret)
4536                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4537                          ret);
4538
4539         return ret;
4540 }
4541
4542 static int
4543 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4544 {
4545         struct hns3_hw *hw = &hns->hw;
4546         bool allmulti = hw->data->all_multicast ? true : false;
4547         int ret;
4548
4549         if (hw->data->promiscuous) {
4550                 ret = hns3_set_promisc_mode(hw, true, true);
4551                 if (ret)
4552                         hns3_err(hw, "failed to restore promiscuous mode, "
4553                                  "ret = %d", ret);
4554                 return ret;
4555         }
4556
4557         ret = hns3_set_promisc_mode(hw, false, allmulti);
4558         if (ret)
4559                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4560                          ret);
4561         return ret;
4562 }
4563
4564 static int
4565 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4566 {
4567         struct hns3_sfp_info_cmd *resp;
4568         struct hns3_cmd_desc desc;
4569         int ret;
4570
4571         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4572         resp = (struct hns3_sfp_info_cmd *)desc.data;
4573         resp->query_type = HNS3_ACTIVE_QUERY;
4574
4575         ret = hns3_cmd_send(hw, &desc, 1);
4576         if (ret == -EOPNOTSUPP) {
4577                 hns3_warn(hw, "firmware does not support get SFP info,"
4578                           " ret = %d.", ret);
4579                 return ret;
4580         } else if (ret) {
4581                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4582                 return ret;
4583         }
4584
4585         /*
4586          * In some case, the speed of MAC obtained from firmware may be 0, it
4587          * shouldn't be set to mac->speed.
4588          */
4589         if (!rte_le_to_cpu_32(resp->sfp_speed))
4590                 return 0;
4591
4592         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4593         /*
4594          * if resp->supported_speed is 0, it means it's an old version
4595          * firmware, do not update these params.
4596          */
4597         if (resp->supported_speed) {
4598                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4599                 mac_info->supported_speed =
4600                                         rte_le_to_cpu_32(resp->supported_speed);
4601                 mac_info->support_autoneg = resp->autoneg_ability;
4602                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4603                                         : ETH_LINK_AUTONEG;
4604         } else {
4605                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4606         }
4607
4608         return 0;
4609 }
4610
4611 static uint8_t
4612 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4613 {
4614         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4615                 duplex = ETH_LINK_FULL_DUPLEX;
4616
4617         return duplex;
4618 }
4619
4620 static int
4621 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4622 {
4623         struct hns3_mac *mac = &hw->mac;
4624         int ret;
4625
4626         duplex = hns3_check_speed_dup(duplex, speed);
4627         if (mac->link_speed == speed && mac->link_duplex == duplex)
4628                 return 0;
4629
4630         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4631         if (ret)
4632                 return ret;
4633
4634         ret = hns3_port_shaper_update(hw, speed);
4635         if (ret)
4636                 return ret;
4637
4638         mac->link_speed = speed;
4639         mac->link_duplex = duplex;
4640
4641         return 0;
4642 }
4643
4644 static int
4645 hns3_update_fiber_link_info(struct hns3_hw *hw)
4646 {
4647         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4648         struct hns3_mac *mac = &hw->mac;
4649         struct hns3_mac mac_info;
4650         int ret;
4651
4652         /* If firmware do not support get SFP/qSFP speed, return directly */
4653         if (!pf->support_sfp_query)
4654                 return 0;
4655
4656         memset(&mac_info, 0, sizeof(struct hns3_mac));
4657         ret = hns3_get_sfp_info(hw, &mac_info);
4658         if (ret == -EOPNOTSUPP) {
4659                 pf->support_sfp_query = false;
4660                 return ret;
4661         } else if (ret)
4662                 return ret;
4663
4664         /* Do nothing if no SFP */
4665         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4666                 return 0;
4667
4668         /*
4669          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4670          * to reconfigure the speed of MAC. Otherwise, it indicates
4671          * that the current firmware only supports to obtain the
4672          * speed of the SFP, and the speed of MAC needs to reconfigure.
4673          */
4674         mac->query_type = mac_info.query_type;
4675         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4676                 if (mac_info.link_speed != mac->link_speed) {
4677                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4678                         if (ret)
4679                                 return ret;
4680                 }
4681
4682                 mac->link_speed = mac_info.link_speed;
4683                 mac->supported_speed = mac_info.supported_speed;
4684                 mac->support_autoneg = mac_info.support_autoneg;
4685                 mac->link_autoneg = mac_info.link_autoneg;
4686
4687                 return 0;
4688         }
4689
4690         /* Config full duplex for SFP */
4691         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4692                                       ETH_LINK_FULL_DUPLEX);
4693 }
4694
4695 static void
4696 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4697 {
4698 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4699
4700         struct hns3_phy_params_bd0_cmd *req;
4701         uint32_t supported;
4702
4703         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4704         mac->link_speed = rte_le_to_cpu_32(req->speed);
4705         mac->link_duplex = hns3_get_bit(req->duplex,
4706                                            HNS3_PHY_DUPLEX_CFG_B);
4707         mac->link_autoneg = hns3_get_bit(req->autoneg,
4708                                            HNS3_PHY_AUTONEG_CFG_B);
4709         mac->advertising = rte_le_to_cpu_32(req->advertising);
4710         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4711         supported = rte_le_to_cpu_32(req->supported);
4712         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4713         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4714 }
4715
4716 static int
4717 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4718 {
4719         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4720         uint16_t i;
4721         int ret;
4722
4723         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4724                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4725                                           true);
4726                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4727         }
4728         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4729
4730         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4731         if (ret) {
4732                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4733                 return ret;
4734         }
4735
4736         hns3_parse_copper_phy_params(desc, mac);
4737
4738         return 0;
4739 }
4740
4741 static int
4742 hns3_update_copper_link_info(struct hns3_hw *hw)
4743 {
4744         struct hns3_mac *mac = &hw->mac;
4745         struct hns3_mac mac_info;
4746         int ret;
4747
4748         memset(&mac_info, 0, sizeof(struct hns3_mac));
4749         ret = hns3_get_copper_phy_params(hw, &mac_info);
4750         if (ret)
4751                 return ret;
4752
4753         if (mac_info.link_speed != mac->link_speed) {
4754                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4755                 if (ret)
4756                         return ret;
4757         }
4758
4759         mac->link_speed = mac_info.link_speed;
4760         mac->link_duplex = mac_info.link_duplex;
4761         mac->link_autoneg = mac_info.link_autoneg;
4762         mac->supported_speed = mac_info.supported_speed;
4763         mac->advertising = mac_info.advertising;
4764         mac->lp_advertising = mac_info.lp_advertising;
4765         mac->support_autoneg = mac_info.support_autoneg;
4766
4767         return 0;
4768 }
4769
4770 static int
4771 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4772 {
4773         struct hns3_adapter *hns = eth_dev->data->dev_private;
4774         struct hns3_hw *hw = &hns->hw;
4775         int ret = 0;
4776
4777         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4778                 ret = hns3_update_copper_link_info(hw);
4779         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4780                 ret = hns3_update_fiber_link_info(hw);
4781
4782         return ret;
4783 }
4784
4785 static int
4786 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4787 {
4788         struct hns3_config_mac_mode_cmd *req;
4789         struct hns3_cmd_desc desc;
4790         uint32_t loop_en = 0;
4791         uint8_t val = 0;
4792         int ret;
4793
4794         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4795
4796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4797         if (enable)
4798                 val = 1;
4799         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4800         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4801         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4802         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4803         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4804         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4805         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4806         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4807         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4808         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4809
4810         /*
4811          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4812          * when receiving frames. Otherwise, CRC will be stripped.
4813          */
4814         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4815                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4816         else
4817                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4818         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4819         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4820         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4821         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4822
4823         ret = hns3_cmd_send(hw, &desc, 1);
4824         if (ret)
4825                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4826
4827         return ret;
4828 }
4829
4830 static int
4831 hns3_get_mac_link_status(struct hns3_hw *hw)
4832 {
4833         struct hns3_link_status_cmd *req;
4834         struct hns3_cmd_desc desc;
4835         int link_status;
4836         int ret;
4837
4838         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4839         ret = hns3_cmd_send(hw, &desc, 1);
4840         if (ret) {
4841                 hns3_err(hw, "get link status cmd failed %d", ret);
4842                 return ETH_LINK_DOWN;
4843         }
4844
4845         req = (struct hns3_link_status_cmd *)desc.data;
4846         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4847
4848         return !!link_status;
4849 }
4850
4851 static bool
4852 hns3_update_link_status(struct hns3_hw *hw)
4853 {
4854         int state;
4855
4856         state = hns3_get_mac_link_status(hw);
4857         if (state != hw->mac.link_status) {
4858                 hw->mac.link_status = state;
4859                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4860                 hns3_config_mac_tnl_int(hw,
4861                                         state == ETH_LINK_UP ? true : false);
4862                 return true;
4863         }
4864
4865         return false;
4866 }
4867
4868 void
4869 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4870 {
4871         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4872         struct rte_eth_link new_link;
4873         int ret;
4874
4875         if (query)
4876                 hns3_update_port_link_info(dev);
4877
4878         memset(&new_link, 0, sizeof(new_link));
4879         hns3_setup_linkstatus(dev, &new_link);
4880
4881         ret = rte_eth_linkstatus_set(dev, &new_link);
4882         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4883                 hns3_start_report_lse(dev);
4884 }
4885
4886 static void
4887 hns3_service_handler(void *param)
4888 {
4889         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4890         struct hns3_adapter *hns = eth_dev->data->dev_private;
4891         struct hns3_hw *hw = &hns->hw;
4892
4893         if (!hns3_is_reset_pending(hns))
4894                 hns3_update_linkstatus_and_event(hw, true);
4895         else
4896                 hns3_warn(hw, "Cancel the query when reset is pending");
4897
4898         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4899 }
4900
4901 static int
4902 hns3_init_hardware(struct hns3_adapter *hns)
4903 {
4904         struct hns3_hw *hw = &hns->hw;
4905         int ret;
4906
4907         ret = hns3_map_tqp(hw);
4908         if (ret) {
4909                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4910                 return ret;
4911         }
4912
4913         ret = hns3_init_umv_space(hw);
4914         if (ret) {
4915                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4916                 return ret;
4917         }
4918
4919         ret = hns3_mac_init(hw);
4920         if (ret) {
4921                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4922                 goto err_mac_init;
4923         }
4924
4925         ret = hns3_init_mgr_tbl(hw);
4926         if (ret) {
4927                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4928                 goto err_mac_init;
4929         }
4930
4931         ret = hns3_promisc_init(hw);
4932         if (ret) {
4933                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4934                              ret);
4935                 goto err_mac_init;
4936         }
4937
4938         ret = hns3_init_vlan_config(hns);
4939         if (ret) {
4940                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4941                 goto err_mac_init;
4942         }
4943
4944         ret = hns3_dcb_init(hw);
4945         if (ret) {
4946                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4947                 goto err_mac_init;
4948         }
4949
4950         ret = hns3_init_fd_config(hns);
4951         if (ret) {
4952                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4953                 goto err_mac_init;
4954         }
4955
4956         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4957         if (ret) {
4958                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4959                 goto err_mac_init;
4960         }
4961
4962         ret = hns3_config_gro(hw, false);
4963         if (ret) {
4964                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4965                 goto err_mac_init;
4966         }
4967
4968         /*
4969          * In the initialization clearing the all hardware mapping relationship
4970          * configurations between queues and interrupt vectors is needed, so
4971          * some error caused by the residual configurations, such as the
4972          * unexpected interrupt, can be avoid.
4973          */
4974         ret = hns3_init_ring_with_vector(hw);
4975         if (ret) {
4976                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4977                 goto err_mac_init;
4978         }
4979
4980         return 0;
4981
4982 err_mac_init:
4983         hns3_uninit_umv_space(hw);
4984         return ret;
4985 }
4986
4987 static int
4988 hns3_clear_hw(struct hns3_hw *hw)
4989 {
4990         struct hns3_cmd_desc desc;
4991         int ret;
4992
4993         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4994
4995         ret = hns3_cmd_send(hw, &desc, 1);
4996         if (ret && ret != -EOPNOTSUPP)
4997                 return ret;
4998
4999         return 0;
5000 }
5001
5002 static void
5003 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5004 {
5005         uint32_t val;
5006
5007         /*
5008          * The new firmware support report more hardware error types by
5009          * msix mode. These errors are defined as RAS errors in hardware
5010          * and belong to a different type from the MSI-x errors processed
5011          * by the network driver.
5012          *
5013          * Network driver should open the new error report on initialition
5014          */
5015         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5016         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5017         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5018 }
5019
5020 static uint32_t
5021 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5022 {
5023         struct hns3_mac *mac = &hw->mac;
5024
5025         switch (mac->link_speed) {
5026         case ETH_SPEED_NUM_1G:
5027                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5028         case ETH_SPEED_NUM_10G:
5029                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5030         case ETH_SPEED_NUM_25G:
5031                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5032         case ETH_SPEED_NUM_40G:
5033                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5034         case ETH_SPEED_NUM_50G:
5035                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5036         case ETH_SPEED_NUM_100G:
5037                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5038         case ETH_SPEED_NUM_200G:
5039                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5040         default:
5041                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5042                 return 0;
5043         }
5044 }
5045
5046 /*
5047  * Validity of supported_speed for firber and copper media type can be
5048  * guaranteed by the following policy:
5049  * Copper:
5050  *       Although the initialization of the phy in the firmware may not be
5051  *       completed, the firmware can guarantees that the supported_speed is
5052  *       an valid value.
5053  * Firber:
5054  *       If the version of firmware supports the acitive query way of the
5055  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5056  *       through it. If unsupported, use the SFP's speed as the value of the
5057  *       supported_speed.
5058  */
5059 static int
5060 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5061 {
5062         struct hns3_adapter *hns = eth_dev->data->dev_private;
5063         struct hns3_hw *hw = &hns->hw;
5064         struct hns3_mac *mac = &hw->mac;
5065         int ret;
5066
5067         ret = hns3_update_link_info(eth_dev);
5068         if (ret)
5069                 return ret;
5070
5071         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5072                 /*
5073                  * Some firmware does not support the report of supported_speed,
5074                  * and only report the effective speed of SFP. In this case, it
5075                  * is necessary to use the SFP's speed as the supported_speed.
5076                  */
5077                 if (mac->supported_speed == 0)
5078                         mac->supported_speed =
5079                                 hns3_set_firber_default_support_speed(hw);
5080         }
5081
5082         return 0;
5083 }
5084
5085 static void
5086 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5087 {
5088         struct hns3_mac *mac = &hns->hw.mac;
5089
5090         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5091                 hns->pf.support_fc_autoneg = true;
5092                 return;
5093         }
5094
5095         /*
5096          * Flow control auto-negotiation requires the cooperation of the driver
5097          * and firmware. Currently, the optical port does not support flow
5098          * control auto-negotiation.
5099          */
5100         hns->pf.support_fc_autoneg = false;
5101 }
5102
5103 static int
5104 hns3_init_pf(struct rte_eth_dev *eth_dev)
5105 {
5106         struct rte_device *dev = eth_dev->device;
5107         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5108         struct hns3_adapter *hns = eth_dev->data->dev_private;
5109         struct hns3_hw *hw = &hns->hw;
5110         int ret;
5111
5112         PMD_INIT_FUNC_TRACE();
5113
5114         /* Get hardware io base address from pcie BAR2 IO space */
5115         hw->io_base = pci_dev->mem_resource[2].addr;
5116
5117         /* Firmware command queue initialize */
5118         ret = hns3_cmd_init_queue(hw);
5119         if (ret) {
5120                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5121                 goto err_cmd_init_queue;
5122         }
5123
5124         hns3_clear_all_event_cause(hw);
5125
5126         /* Firmware command initialize */
5127         ret = hns3_cmd_init(hw);
5128         if (ret) {
5129                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5130                 goto err_cmd_init;
5131         }
5132
5133         /*
5134          * To ensure that the hardware environment is clean during
5135          * initialization, the driver actively clear the hardware environment
5136          * during initialization, including PF and corresponding VFs' vlan, mac,
5137          * flow table configurations, etc.
5138          */
5139         ret = hns3_clear_hw(hw);
5140         if (ret) {
5141                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5142                 goto err_cmd_init;
5143         }
5144
5145         /* Hardware statistics of imissed registers cleared. */
5146         ret = hns3_update_imissed_stats(hw, true);
5147         if (ret) {
5148                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5149                 goto err_cmd_init;
5150         }
5151
5152         hns3_config_all_msix_error(hw, true);
5153
5154         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5155                                          hns3_interrupt_handler,
5156                                          eth_dev);
5157         if (ret) {
5158                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5159                 goto err_intr_callback_register;
5160         }
5161
5162         ret = hns3_ptp_init(hw);
5163         if (ret)
5164                 goto err_get_config;
5165
5166         /* Enable interrupt */
5167         rte_intr_enable(&pci_dev->intr_handle);
5168         hns3_pf_enable_irq0(hw);
5169
5170         /* Get configuration */
5171         ret = hns3_get_configuration(hw);
5172         if (ret) {
5173                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5174                 goto err_get_config;
5175         }
5176
5177         ret = hns3_tqp_stats_init(hw);
5178         if (ret)
5179                 goto err_get_config;
5180
5181         ret = hns3_init_hardware(hns);
5182         if (ret) {
5183                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5184                 goto err_init_hw;
5185         }
5186
5187         /* Initialize flow director filter list & hash */
5188         ret = hns3_fdir_filter_init(hns);
5189         if (ret) {
5190                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5191                 goto err_fdir;
5192         }
5193
5194         hns3_rss_set_default_args(hw);
5195
5196         ret = hns3_enable_hw_error_intr(hns, true);
5197         if (ret) {
5198                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5199                              ret);
5200                 goto err_enable_intr;
5201         }
5202
5203         ret = hns3_get_port_supported_speed(eth_dev);
5204         if (ret) {
5205                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5206                              "by device, ret = %d.", ret);
5207                 goto err_supported_speed;
5208         }
5209
5210         hns3_get_fc_autoneg_capability(hns);
5211
5212         hns3_tm_conf_init(eth_dev);
5213
5214         return 0;
5215
5216 err_supported_speed:
5217         (void)hns3_enable_hw_error_intr(hns, false);
5218 err_enable_intr:
5219         hns3_fdir_filter_uninit(hns);
5220 err_fdir:
5221         hns3_uninit_umv_space(hw);
5222 err_init_hw:
5223         hns3_tqp_stats_uninit(hw);
5224 err_get_config:
5225         hns3_pf_disable_irq0(hw);
5226         rte_intr_disable(&pci_dev->intr_handle);
5227         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5228                              eth_dev);
5229 err_intr_callback_register:
5230 err_cmd_init:
5231         hns3_cmd_uninit(hw);
5232         hns3_cmd_destroy_queue(hw);
5233 err_cmd_init_queue:
5234         hw->io_base = NULL;
5235
5236         return ret;
5237 }
5238
5239 static void
5240 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5241 {
5242         struct hns3_adapter *hns = eth_dev->data->dev_private;
5243         struct rte_device *dev = eth_dev->device;
5244         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5245         struct hns3_hw *hw = &hns->hw;
5246
5247         PMD_INIT_FUNC_TRACE();
5248
5249         hns3_tm_conf_uninit(eth_dev);
5250         hns3_enable_hw_error_intr(hns, false);
5251         hns3_rss_uninit(hns);
5252         (void)hns3_config_gro(hw, false);
5253         hns3_promisc_uninit(hw);
5254         hns3_fdir_filter_uninit(hns);
5255         hns3_uninit_umv_space(hw);
5256         hns3_tqp_stats_uninit(hw);
5257         hns3_config_mac_tnl_int(hw, false);
5258         hns3_pf_disable_irq0(hw);
5259         rte_intr_disable(&pci_dev->intr_handle);
5260         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5261                              eth_dev);
5262         hns3_config_all_msix_error(hw, false);
5263         hns3_cmd_uninit(hw);
5264         hns3_cmd_destroy_queue(hw);
5265         hw->io_base = NULL;
5266 }
5267
5268 static uint32_t
5269 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5270 {
5271         uint32_t speed_bit;
5272
5273         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5274         case ETH_LINK_SPEED_10M:
5275                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5276                 break;
5277         case ETH_LINK_SPEED_10M_HD:
5278                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5279                 break;
5280         case ETH_LINK_SPEED_100M:
5281                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5282                 break;
5283         case ETH_LINK_SPEED_100M_HD:
5284                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5285                 break;
5286         case ETH_LINK_SPEED_1G:
5287                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5288                 break;
5289         default:
5290                 speed_bit = 0;
5291                 break;
5292         }
5293
5294         return speed_bit;
5295 }
5296
5297 static uint32_t
5298 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5299 {
5300         uint32_t speed_bit;
5301
5302         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5303         case ETH_LINK_SPEED_1G:
5304                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5305                 break;
5306         case ETH_LINK_SPEED_10G:
5307                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5308                 break;
5309         case ETH_LINK_SPEED_25G:
5310                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5311                 break;
5312         case ETH_LINK_SPEED_40G:
5313                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5314                 break;
5315         case ETH_LINK_SPEED_50G:
5316                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5317                 break;
5318         case ETH_LINK_SPEED_100G:
5319                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5320                 break;
5321         case ETH_LINK_SPEED_200G:
5322                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5323                 break;
5324         default:
5325                 speed_bit = 0;
5326                 break;
5327         }
5328
5329         return speed_bit;
5330 }
5331
5332 static int
5333 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5334 {
5335         struct hns3_mac *mac = &hw->mac;
5336         uint32_t supported_speed = mac->supported_speed;
5337         uint32_t speed_bit = 0;
5338
5339         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5340                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5341         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5342                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5343
5344         if (!(speed_bit & supported_speed)) {
5345                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5346                          link_speeds);
5347                 return -EINVAL;
5348         }
5349
5350         return 0;
5351 }
5352
5353 static inline uint32_t
5354 hns3_get_link_speed(uint32_t link_speeds)
5355 {
5356         uint32_t speed = ETH_SPEED_NUM_NONE;
5357
5358         if (link_speeds & ETH_LINK_SPEED_10M ||
5359             link_speeds & ETH_LINK_SPEED_10M_HD)
5360                 speed = ETH_SPEED_NUM_10M;
5361         if (link_speeds & ETH_LINK_SPEED_100M ||
5362             link_speeds & ETH_LINK_SPEED_100M_HD)
5363                 speed = ETH_SPEED_NUM_100M;
5364         if (link_speeds & ETH_LINK_SPEED_1G)
5365                 speed = ETH_SPEED_NUM_1G;
5366         if (link_speeds & ETH_LINK_SPEED_10G)
5367                 speed = ETH_SPEED_NUM_10G;
5368         if (link_speeds & ETH_LINK_SPEED_25G)
5369                 speed = ETH_SPEED_NUM_25G;
5370         if (link_speeds & ETH_LINK_SPEED_40G)
5371                 speed = ETH_SPEED_NUM_40G;
5372         if (link_speeds & ETH_LINK_SPEED_50G)
5373                 speed = ETH_SPEED_NUM_50G;
5374         if (link_speeds & ETH_LINK_SPEED_100G)
5375                 speed = ETH_SPEED_NUM_100G;
5376         if (link_speeds & ETH_LINK_SPEED_200G)
5377                 speed = ETH_SPEED_NUM_200G;
5378
5379         return speed;
5380 }
5381
5382 static uint8_t
5383 hns3_get_link_duplex(uint32_t link_speeds)
5384 {
5385         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5386             (link_speeds & ETH_LINK_SPEED_100M_HD))
5387                 return ETH_LINK_HALF_DUPLEX;
5388         else
5389                 return ETH_LINK_FULL_DUPLEX;
5390 }
5391
5392 static int
5393 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5394                                 struct hns3_set_link_speed_cfg *cfg)
5395 {
5396         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5397         struct hns3_phy_params_bd0_cmd *req;
5398         uint16_t i;
5399
5400         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5401                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5402                                           false);
5403                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5404         }
5405         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5406         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5407         req->autoneg = cfg->autoneg;
5408
5409         /*
5410          * The full speed capability is used to negotiate when
5411          * auto-negotiation is enabled.
5412          */
5413         if (cfg->autoneg) {
5414                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5415                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5416                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5417                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5418                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5419         } else {
5420                 req->speed = cfg->speed;
5421                 req->duplex = cfg->duplex;
5422         }
5423
5424         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5425 }
5426
5427 static int
5428 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5429 {
5430         struct hns3_config_auto_neg_cmd *req;
5431         struct hns3_cmd_desc desc;
5432         uint32_t flag = 0;
5433         int ret;
5434
5435         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5436
5437         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5438         if (enable)
5439                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5440         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5441
5442         ret = hns3_cmd_send(hw, &desc, 1);
5443         if (ret)
5444                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5445
5446         return ret;
5447 }
5448
5449 static int
5450 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5451                                struct hns3_set_link_speed_cfg *cfg)
5452 {
5453         int ret;
5454
5455         if (hw->mac.support_autoneg) {
5456                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5457                 if (ret) {
5458                         hns3_err(hw, "failed to configure auto-negotiation.");
5459                         return ret;
5460                 }
5461
5462                 /*
5463                  * To enable auto-negotiation, we only need to open the switch
5464                  * of auto-negotiation, then firmware sets all speed
5465                  * capabilities.
5466                  */
5467                 if (cfg->autoneg)
5468                         return 0;
5469         }
5470
5471         /*
5472          * Some hardware doesn't support auto-negotiation, but users may not
5473          * configure link_speeds (default 0), which means auto-negotiation
5474          * In this case, a warning message need to be printed, instead of
5475          * an error.
5476          */
5477         if (cfg->autoneg) {
5478                 hns3_warn(hw, "auto-negotiation is not supported.");
5479                 return 0;
5480         }
5481
5482         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5483 }
5484
5485 static int
5486 hns3_set_port_link_speed(struct hns3_hw *hw,
5487                          struct hns3_set_link_speed_cfg *cfg)
5488 {
5489         int ret;
5490
5491         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5492 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5493                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5494                 if (pf->is_tmp_phy)
5495                         return 0;
5496 #endif
5497
5498                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5499                 if (ret) {
5500                         hns3_err(hw, "failed to set copper port link speed,"
5501                                  "ret = %d.", ret);
5502                         return ret;
5503                 }
5504         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5505                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5506                 if (ret) {
5507                         hns3_err(hw, "failed to set fiber port link speed,"
5508                                  "ret = %d.", ret);
5509                         return ret;
5510                 }
5511         }
5512
5513         return 0;
5514 }
5515
5516 static int
5517 hns3_apply_link_speed(struct hns3_hw *hw)
5518 {
5519         struct rte_eth_conf *conf = &hw->data->dev_conf;
5520         struct hns3_set_link_speed_cfg cfg;
5521         int ret;
5522
5523         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5524         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5525                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5526         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5527                 ret = hns3_check_port_speed(hw, conf->link_speeds);
5528                 if (ret)
5529                         return ret;
5530
5531                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5532                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5533         }
5534
5535         return hns3_set_port_link_speed(hw, &cfg);
5536 }
5537
5538 static int
5539 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5540 {
5541         struct hns3_hw *hw = &hns->hw;
5542         int ret;
5543
5544         ret = hns3_dcb_cfg_update(hns);
5545         if (ret)
5546                 return ret;
5547
5548         /*
5549          * The hns3_dcb_cfg_update may configure TM module, so
5550          * hns3_tm_conf_update must called later.
5551          */
5552         ret = hns3_tm_conf_update(hw);
5553         if (ret) {
5554                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5555                 return ret;
5556         }
5557
5558         hns3_enable_rxd_adv_layout(hw);
5559
5560         ret = hns3_init_queues(hns, reset_queue);
5561         if (ret) {
5562                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5563                 return ret;
5564         }
5565
5566         ret = hns3_cfg_mac_mode(hw, true);
5567         if (ret) {
5568                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5569                 goto err_config_mac_mode;
5570         }
5571
5572         ret = hns3_apply_link_speed(hw);
5573         if (ret)
5574                 goto err_config_mac_mode;
5575
5576         return 0;
5577
5578 err_config_mac_mode:
5579         (void)hns3_cfg_mac_mode(hw, false);
5580         hns3_dev_release_mbufs(hns);
5581         /*
5582          * Here is exception handling, hns3_reset_all_tqps will have the
5583          * corresponding error message if it is handled incorrectly, so it is
5584          * not necessary to check hns3_reset_all_tqps return value, here keep
5585          * ret as the error code causing the exception.
5586          */
5587         (void)hns3_reset_all_tqps(hns);
5588         return ret;
5589 }
5590
5591 static int
5592 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5593 {
5594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5596         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5597         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5598         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5599         uint32_t intr_vector;
5600         uint16_t q_id;
5601         int ret;
5602
5603         /*
5604          * hns3 needs a separate interrupt to be used as event interrupt which
5605          * could not be shared with task queue pair, so KERNEL drivers need
5606          * support multiple interrupt vectors.
5607          */
5608         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5609             !rte_intr_cap_multiple(intr_handle))
5610                 return 0;
5611
5612         rte_intr_disable(intr_handle);
5613         intr_vector = hw->used_rx_queues;
5614         /* creates event fd for each intr vector when MSIX is used */
5615         if (rte_intr_efd_enable(intr_handle, intr_vector))
5616                 return -EINVAL;
5617
5618         if (intr_handle->intr_vec == NULL) {
5619                 intr_handle->intr_vec =
5620                         rte_zmalloc("intr_vec",
5621                                     hw->used_rx_queues * sizeof(int), 0);
5622                 if (intr_handle->intr_vec == NULL) {
5623                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5624                                         hw->used_rx_queues);
5625                         ret = -ENOMEM;
5626                         goto alloc_intr_vec_error;
5627                 }
5628         }
5629
5630         if (rte_intr_allow_others(intr_handle)) {
5631                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5632                 base = RTE_INTR_VEC_RXTX_OFFSET;
5633         }
5634
5635         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5636                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5637                                                  HNS3_RING_TYPE_RX, q_id);
5638                 if (ret)
5639                         goto bind_vector_error;
5640                 intr_handle->intr_vec[q_id] = vec;
5641                 /*
5642                  * If there are not enough efds (e.g. not enough interrupt),
5643                  * remaining queues will be bond to the last interrupt.
5644                  */
5645                 if (vec < base + intr_handle->nb_efd - 1)
5646                         vec++;
5647         }
5648         rte_intr_enable(intr_handle);
5649         return 0;
5650
5651 bind_vector_error:
5652         rte_free(intr_handle->intr_vec);
5653         intr_handle->intr_vec = NULL;
5654 alloc_intr_vec_error:
5655         rte_intr_efd_disable(intr_handle);
5656         return ret;
5657 }
5658
5659 static int
5660 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5661 {
5662         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5663         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5664         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5665         uint16_t q_id;
5666         int ret;
5667
5668         if (dev->data->dev_conf.intr_conf.rxq == 0)
5669                 return 0;
5670
5671         if (rte_intr_dp_is_en(intr_handle)) {
5672                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5673                         ret = hns3_bind_ring_with_vector(hw,
5674                                         intr_handle->intr_vec[q_id], true,
5675                                         HNS3_RING_TYPE_RX, q_id);
5676                         if (ret)
5677                                 return ret;
5678                 }
5679         }
5680
5681         return 0;
5682 }
5683
5684 static void
5685 hns3_restore_filter(struct rte_eth_dev *dev)
5686 {
5687         hns3_restore_rss_filter(dev);
5688 }
5689
5690 static int
5691 hns3_dev_start(struct rte_eth_dev *dev)
5692 {
5693         struct hns3_adapter *hns = dev->data->dev_private;
5694         struct hns3_hw *hw = &hns->hw;
5695         int ret;
5696
5697         PMD_INIT_FUNC_TRACE();
5698         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5699                 return -EBUSY;
5700
5701         rte_spinlock_lock(&hw->lock);
5702         hw->adapter_state = HNS3_NIC_STARTING;
5703
5704         ret = hns3_do_start(hns, true);
5705         if (ret) {
5706                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5707                 rte_spinlock_unlock(&hw->lock);
5708                 return ret;
5709         }
5710         ret = hns3_map_rx_interrupt(dev);
5711         if (ret)
5712                 goto map_rx_inter_err;
5713
5714         /*
5715          * There are three register used to control the status of a TQP
5716          * (contains a pair of Tx queue and Rx queue) in the new version network
5717          * engine. One is used to control the enabling of Tx queue, the other is
5718          * used to control the enabling of Rx queue, and the last is the master
5719          * switch used to control the enabling of the tqp. The Tx register and
5720          * TQP register must be enabled at the same time to enable a Tx queue.
5721          * The same applies to the Rx queue. For the older network engine, this
5722          * function only refresh the enabled flag, and it is used to update the
5723          * status of queue in the dpdk framework.
5724          */
5725         ret = hns3_start_all_txqs(dev);
5726         if (ret)
5727                 goto map_rx_inter_err;
5728
5729         ret = hns3_start_all_rxqs(dev);
5730         if (ret)
5731                 goto start_all_rxqs_fail;
5732
5733         hw->adapter_state = HNS3_NIC_STARTED;
5734         rte_spinlock_unlock(&hw->lock);
5735
5736         hns3_rx_scattered_calc(dev);
5737         hns3_set_rxtx_function(dev);
5738         hns3_mp_req_start_rxtx(dev);
5739
5740         hns3_restore_filter(dev);
5741
5742         /* Enable interrupt of all rx queues before enabling queues */
5743         hns3_dev_all_rx_queue_intr_enable(hw, true);
5744
5745         /*
5746          * After finished the initialization, enable tqps to receive/transmit
5747          * packets and refresh all queue status.
5748          */
5749         hns3_start_tqps(hw);
5750
5751         hns3_tm_dev_start_proc(hw);
5752
5753         if (dev->data->dev_conf.intr_conf.lsc != 0)
5754                 hns3_dev_link_update(dev, 0);
5755         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5756
5757         hns3_info(hw, "hns3 dev start successful!");
5758
5759         return 0;
5760
5761 start_all_rxqs_fail:
5762         hns3_stop_all_txqs(dev);
5763 map_rx_inter_err:
5764         (void)hns3_do_stop(hns);
5765         hw->adapter_state = HNS3_NIC_CONFIGURED;
5766         rte_spinlock_unlock(&hw->lock);
5767
5768         return ret;
5769 }
5770
5771 static int
5772 hns3_do_stop(struct hns3_adapter *hns)
5773 {
5774         struct hns3_hw *hw = &hns->hw;
5775         int ret;
5776
5777         /*
5778          * The "hns3_do_stop" function will also be called by .stop_service to
5779          * prepare reset. At the time of global or IMP reset, the command cannot
5780          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5781          * accessed during the reset process. So the mbuf can not be released
5782          * during reset and is required to be released after the reset is
5783          * completed.
5784          */
5785         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5786                 hns3_dev_release_mbufs(hns);
5787
5788         ret = hns3_cfg_mac_mode(hw, false);
5789         if (ret)
5790                 return ret;
5791         hw->mac.link_status = ETH_LINK_DOWN;
5792
5793         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5794                 hns3_configure_all_mac_addr(hns, true);
5795                 ret = hns3_reset_all_tqps(hns);
5796                 if (ret) {
5797                         hns3_err(hw, "failed to reset all queues ret = %d.",
5798                                  ret);
5799                         return ret;
5800                 }
5801         }
5802         hw->mac.default_addr_setted = false;
5803         return 0;
5804 }
5805
5806 static void
5807 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5808 {
5809         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5810         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5811         struct hns3_adapter *hns = dev->data->dev_private;
5812         struct hns3_hw *hw = &hns->hw;
5813         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5814         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5815         uint16_t q_id;
5816
5817         if (dev->data->dev_conf.intr_conf.rxq == 0)
5818                 return;
5819
5820         /* unmap the ring with vector */
5821         if (rte_intr_allow_others(intr_handle)) {
5822                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5823                 base = RTE_INTR_VEC_RXTX_OFFSET;
5824         }
5825         if (rte_intr_dp_is_en(intr_handle)) {
5826                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5827                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5828                                                          HNS3_RING_TYPE_RX,
5829                                                          q_id);
5830                         if (vec < base + intr_handle->nb_efd - 1)
5831                                 vec++;
5832                 }
5833         }
5834         /* Clean datapath event and queue/vec mapping */
5835         rte_intr_efd_disable(intr_handle);
5836         if (intr_handle->intr_vec) {
5837                 rte_free(intr_handle->intr_vec);
5838                 intr_handle->intr_vec = NULL;
5839         }
5840 }
5841
5842 static int
5843 hns3_dev_stop(struct rte_eth_dev *dev)
5844 {
5845         struct hns3_adapter *hns = dev->data->dev_private;
5846         struct hns3_hw *hw = &hns->hw;
5847
5848         PMD_INIT_FUNC_TRACE();
5849         dev->data->dev_started = 0;
5850
5851         hw->adapter_state = HNS3_NIC_STOPPING;
5852         hns3_set_rxtx_function(dev);
5853         rte_wmb();
5854         /* Disable datapath on secondary process. */
5855         hns3_mp_req_stop_rxtx(dev);
5856         /* Prevent crashes when queues are still in use. */
5857         rte_delay_ms(hw->tqps_num);
5858
5859         rte_spinlock_lock(&hw->lock);
5860         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5861                 hns3_tm_dev_stop_proc(hw);
5862                 hns3_config_mac_tnl_int(hw, false);
5863                 hns3_stop_tqps(hw);
5864                 hns3_do_stop(hns);
5865                 hns3_unmap_rx_interrupt(dev);
5866                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5867         }
5868         hns3_rx_scattered_reset(dev);
5869         rte_eal_alarm_cancel(hns3_service_handler, dev);
5870         hns3_stop_report_lse(dev);
5871         rte_spinlock_unlock(&hw->lock);
5872
5873         return 0;
5874 }
5875
5876 static int
5877 hns3_dev_close(struct rte_eth_dev *eth_dev)
5878 {
5879         struct hns3_adapter *hns = eth_dev->data->dev_private;
5880         struct hns3_hw *hw = &hns->hw;
5881         int ret = 0;
5882
5883         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5884                 rte_free(eth_dev->process_private);
5885                 eth_dev->process_private = NULL;
5886                 return 0;
5887         }
5888
5889         if (hw->adapter_state == HNS3_NIC_STARTED)
5890                 ret = hns3_dev_stop(eth_dev);
5891
5892         hw->adapter_state = HNS3_NIC_CLOSING;
5893         hns3_reset_abort(hns);
5894         hw->adapter_state = HNS3_NIC_CLOSED;
5895
5896         hns3_configure_all_mc_mac_addr(hns, true);
5897         hns3_remove_all_vlan_table(hns);
5898         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5899         hns3_uninit_pf(eth_dev);
5900         hns3_free_all_queues(eth_dev);
5901         rte_free(hw->reset.wait_data);
5902         rte_free(eth_dev->process_private);
5903         eth_dev->process_private = NULL;
5904         hns3_mp_uninit_primary();
5905         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5906
5907         return ret;
5908 }
5909
5910 static void
5911 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5912                                    bool *tx_pause)
5913 {
5914         struct hns3_mac *mac = &hw->mac;
5915         uint32_t advertising = mac->advertising;
5916         uint32_t lp_advertising = mac->lp_advertising;
5917         *rx_pause = false;
5918         *tx_pause = false;
5919
5920         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5921                 *rx_pause = true;
5922                 *tx_pause = true;
5923         } else if (advertising & lp_advertising &
5924                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5925                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5926                         *rx_pause = true;
5927                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5928                         *tx_pause = true;
5929         }
5930 }
5931
5932 static enum hns3_fc_mode
5933 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5934 {
5935         enum hns3_fc_mode current_mode;
5936         bool rx_pause = false;
5937         bool tx_pause = false;
5938
5939         switch (hw->mac.media_type) {
5940         case HNS3_MEDIA_TYPE_COPPER:
5941                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5942                 break;
5943
5944         /*
5945          * Flow control auto-negotiation is not supported for fiber and
5946          * backpalne media type.
5947          */
5948         case HNS3_MEDIA_TYPE_FIBER:
5949         case HNS3_MEDIA_TYPE_BACKPLANE:
5950                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5951                 current_mode = hw->requested_fc_mode;
5952                 goto out;
5953         default:
5954                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5955                          hw->mac.media_type);
5956                 current_mode = HNS3_FC_NONE;
5957                 goto out;
5958         }
5959
5960         if (rx_pause && tx_pause)
5961                 current_mode = HNS3_FC_FULL;
5962         else if (rx_pause)
5963                 current_mode = HNS3_FC_RX_PAUSE;
5964         else if (tx_pause)
5965                 current_mode = HNS3_FC_TX_PAUSE;
5966         else
5967                 current_mode = HNS3_FC_NONE;
5968
5969 out:
5970         return current_mode;
5971 }
5972
5973 static enum hns3_fc_mode
5974 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5975 {
5976         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5978         struct hns3_mac *mac = &hw->mac;
5979
5980         /*
5981          * When the flow control mode is obtained, the device may not complete
5982          * auto-negotiation. It is necessary to wait for link establishment.
5983          */
5984         (void)hns3_dev_link_update(dev, 1);
5985
5986         /*
5987          * If the link auto-negotiation of the nic is disabled, or the flow
5988          * control auto-negotiation is not supported, the forced flow control
5989          * mode is used.
5990          */
5991         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5992                 return hw->requested_fc_mode;
5993
5994         return hns3_get_autoneg_fc_mode(hw);
5995 }
5996
5997 static int
5998 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5999 {
6000         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6002         enum hns3_fc_mode current_mode;
6003
6004         current_mode = hns3_get_current_fc_mode(dev);
6005         switch (current_mode) {
6006         case HNS3_FC_FULL:
6007                 fc_conf->mode = RTE_FC_FULL;
6008                 break;
6009         case HNS3_FC_TX_PAUSE:
6010                 fc_conf->mode = RTE_FC_TX_PAUSE;
6011                 break;
6012         case HNS3_FC_RX_PAUSE:
6013                 fc_conf->mode = RTE_FC_RX_PAUSE;
6014                 break;
6015         case HNS3_FC_NONE:
6016         default:
6017                 fc_conf->mode = RTE_FC_NONE;
6018                 break;
6019         }
6020
6021         fc_conf->pause_time = pf->pause_time;
6022         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6023
6024         return 0;
6025 }
6026
6027 static void
6028 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6029 {
6030         switch (mode) {
6031         case RTE_FC_NONE:
6032                 hw->requested_fc_mode = HNS3_FC_NONE;
6033                 break;
6034         case RTE_FC_RX_PAUSE:
6035                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6036                 break;
6037         case RTE_FC_TX_PAUSE:
6038                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6039                 break;
6040         case RTE_FC_FULL:
6041                 hw->requested_fc_mode = HNS3_FC_FULL;
6042                 break;
6043         default:
6044                 hw->requested_fc_mode = HNS3_FC_NONE;
6045                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6046                           "configured to RTE_FC_NONE", mode);
6047                 break;
6048         }
6049 }
6050
6051 static int
6052 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6053 {
6054         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6055
6056         if (!pf->support_fc_autoneg) {
6057                 if (autoneg != 0) {
6058                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6059                         return -EOPNOTSUPP;
6060                 }
6061
6062                 /*
6063                  * Flow control auto-negotiation of the NIC is not supported,
6064                  * but other auto-negotiation features may be supported.
6065                  */
6066                 if (autoneg != hw->mac.link_autoneg) {
6067                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6068                         return -EOPNOTSUPP;
6069                 }
6070
6071                 return 0;
6072         }
6073
6074         /*
6075          * If flow control auto-negotiation of the NIC is supported, all
6076          * auto-negotiation features are supported.
6077          */
6078         if (autoneg != hw->mac.link_autoneg) {
6079                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6080                 return -EOPNOTSUPP;
6081         }
6082
6083         return 0;
6084 }
6085
6086 static int
6087 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6088 {
6089         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6090         int ret;
6091
6092         if (fc_conf->high_water || fc_conf->low_water ||
6093             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6094                 hns3_err(hw, "Unsupported flow control settings specified, "
6095                          "high_water(%u), low_water(%u), send_xon(%u) and "
6096                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6097                          fc_conf->high_water, fc_conf->low_water,
6098                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6099                 return -EINVAL;
6100         }
6101
6102         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6103         if (ret)
6104                 return ret;
6105
6106         if (!fc_conf->pause_time) {
6107                 hns3_err(hw, "Invalid pause time %u setting.",
6108                          fc_conf->pause_time);
6109                 return -EINVAL;
6110         }
6111
6112         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6113             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6114                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6115                          "current_fc_status = %d", hw->current_fc_status);
6116                 return -EOPNOTSUPP;
6117         }
6118
6119         if (hw->num_tc > 1) {
6120                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6121                 return -EOPNOTSUPP;
6122         }
6123
6124         hns3_get_fc_mode(hw, fc_conf->mode);
6125
6126         rte_spinlock_lock(&hw->lock);
6127         ret = hns3_fc_enable(dev, fc_conf);
6128         rte_spinlock_unlock(&hw->lock);
6129
6130         return ret;
6131 }
6132
6133 static int
6134 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6135                             struct rte_eth_pfc_conf *pfc_conf)
6136 {
6137         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6138         int ret;
6139
6140         if (!hns3_dev_dcb_supported(hw)) {
6141                 hns3_err(hw, "This port does not support dcb configurations.");
6142                 return -EOPNOTSUPP;
6143         }
6144
6145         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6146             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6147                 hns3_err(hw, "Unsupported flow control settings specified, "
6148                          "high_water(%u), low_water(%u), send_xon(%u) and "
6149                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6150                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6151                          pfc_conf->fc.send_xon,
6152                          pfc_conf->fc.mac_ctrl_frame_fwd);
6153                 return -EINVAL;
6154         }
6155         if (pfc_conf->fc.autoneg) {
6156                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6157                 return -EINVAL;
6158         }
6159         if (pfc_conf->fc.pause_time == 0) {
6160                 hns3_err(hw, "Invalid pause time %u setting.",
6161                          pfc_conf->fc.pause_time);
6162                 return -EINVAL;
6163         }
6164
6165         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6166             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6167                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6168                              "current_fc_status = %d", hw->current_fc_status);
6169                 return -EOPNOTSUPP;
6170         }
6171
6172         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6173
6174         rte_spinlock_lock(&hw->lock);
6175         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6176         rte_spinlock_unlock(&hw->lock);
6177
6178         return ret;
6179 }
6180
6181 static int
6182 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6183 {
6184         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6185         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6186         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6187         int i;
6188
6189         rte_spinlock_lock(&hw->lock);
6190         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6191                 dcb_info->nb_tcs = pf->local_max_tc;
6192         else
6193                 dcb_info->nb_tcs = 1;
6194
6195         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6196                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6197         for (i = 0; i < dcb_info->nb_tcs; i++)
6198                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6199
6200         for (i = 0; i < hw->num_tc; i++) {
6201                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6202                 dcb_info->tc_queue.tc_txq[0][i].base =
6203                                                 hw->tc_queue[i].tqp_offset;
6204                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6205                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6206                                                 hw->tc_queue[i].tqp_count;
6207         }
6208         rte_spinlock_unlock(&hw->lock);
6209
6210         return 0;
6211 }
6212
6213 static int
6214 hns3_reinit_dev(struct hns3_adapter *hns)
6215 {
6216         struct hns3_hw *hw = &hns->hw;
6217         int ret;
6218
6219         ret = hns3_cmd_init(hw);
6220         if (ret) {
6221                 hns3_err(hw, "Failed to init cmd: %d", ret);
6222                 return ret;
6223         }
6224
6225         ret = hns3_reset_all_tqps(hns);
6226         if (ret) {
6227                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6228                 return ret;
6229         }
6230
6231         ret = hns3_init_hardware(hns);
6232         if (ret) {
6233                 hns3_err(hw, "Failed to init hardware: %d", ret);
6234                 return ret;
6235         }
6236
6237         ret = hns3_enable_hw_error_intr(hns, true);
6238         if (ret) {
6239                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6240                              ret);
6241                 return ret;
6242         }
6243         hns3_info(hw, "Reset done, driver initialization finished.");
6244
6245         return 0;
6246 }
6247
6248 static bool
6249 is_pf_reset_done(struct hns3_hw *hw)
6250 {
6251         uint32_t val, reg, reg_bit;
6252
6253         switch (hw->reset.level) {
6254         case HNS3_IMP_RESET:
6255                 reg = HNS3_GLOBAL_RESET_REG;
6256                 reg_bit = HNS3_IMP_RESET_BIT;
6257                 break;
6258         case HNS3_GLOBAL_RESET:
6259                 reg = HNS3_GLOBAL_RESET_REG;
6260                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6261                 break;
6262         case HNS3_FUNC_RESET:
6263                 reg = HNS3_FUN_RST_ING;
6264                 reg_bit = HNS3_FUN_RST_ING_B;
6265                 break;
6266         case HNS3_FLR_RESET:
6267         default:
6268                 hns3_err(hw, "Wait for unsupported reset level: %d",
6269                          hw->reset.level);
6270                 return true;
6271         }
6272         val = hns3_read_dev(hw, reg);
6273         if (hns3_get_bit(val, reg_bit))
6274                 return false;
6275         else
6276                 return true;
6277 }
6278
6279 bool
6280 hns3_is_reset_pending(struct hns3_adapter *hns)
6281 {
6282         struct hns3_hw *hw = &hns->hw;
6283         enum hns3_reset_level reset;
6284
6285         hns3_check_event_cause(hns, NULL);
6286         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6287         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
6288                 hns3_warn(hw, "High level reset %d is pending", reset);
6289                 return true;
6290         }
6291         reset = hns3_get_reset_level(hns, &hw->reset.request);
6292         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
6293                 hns3_warn(hw, "High level reset %d is request", reset);
6294                 return true;
6295         }
6296         return false;
6297 }
6298
6299 static int
6300 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6301 {
6302         struct hns3_hw *hw = &hns->hw;
6303         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6304         struct timeval tv;
6305
6306         if (wait_data->result == HNS3_WAIT_SUCCESS)
6307                 return 0;
6308         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6309                 gettimeofday(&tv, NULL);
6310                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6311                           tv.tv_sec, tv.tv_usec);
6312                 return -ETIME;
6313         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6314                 return -EAGAIN;
6315
6316         wait_data->hns = hns;
6317         wait_data->check_completion = is_pf_reset_done;
6318         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6319                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6320         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6321         wait_data->count = HNS3_RESET_WAIT_CNT;
6322         wait_data->result = HNS3_WAIT_REQUEST;
6323         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6324         return -EAGAIN;
6325 }
6326
6327 static int
6328 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6329 {
6330         struct hns3_cmd_desc desc;
6331         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6332
6333         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6334         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6335         req->fun_reset_vfid = func_id;
6336
6337         return hns3_cmd_send(hw, &desc, 1);
6338 }
6339
6340 static int
6341 hns3_imp_reset_cmd(struct hns3_hw *hw)
6342 {
6343         struct hns3_cmd_desc desc;
6344
6345         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6346         desc.data[0] = 0xeedd;
6347
6348         return hns3_cmd_send(hw, &desc, 1);
6349 }
6350
6351 static void
6352 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6353 {
6354         struct hns3_hw *hw = &hns->hw;
6355         struct timeval tv;
6356         uint32_t val;
6357
6358         gettimeofday(&tv, NULL);
6359         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6360             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6361                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6362                           tv.tv_sec, tv.tv_usec);
6363                 return;
6364         }
6365
6366         switch (reset_level) {
6367         case HNS3_IMP_RESET:
6368                 hns3_imp_reset_cmd(hw);
6369                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6370                           tv.tv_sec, tv.tv_usec);
6371                 break;
6372         case HNS3_GLOBAL_RESET:
6373                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6374                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6375                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6376                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6377                           tv.tv_sec, tv.tv_usec);
6378                 break;
6379         case HNS3_FUNC_RESET:
6380                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6381                           tv.tv_sec, tv.tv_usec);
6382                 /* schedule again to check later */
6383                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6384                 hns3_schedule_reset(hns);
6385                 break;
6386         default:
6387                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6388                 return;
6389         }
6390         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6391 }
6392
6393 static enum hns3_reset_level
6394 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6395 {
6396         struct hns3_hw *hw = &hns->hw;
6397         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6398
6399         /* Return the highest priority reset level amongst all */
6400         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6401                 reset_level = HNS3_IMP_RESET;
6402         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6403                 reset_level = HNS3_GLOBAL_RESET;
6404         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6405                 reset_level = HNS3_FUNC_RESET;
6406         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6407                 reset_level = HNS3_FLR_RESET;
6408
6409         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6410                 return HNS3_NONE_RESET;
6411
6412         return reset_level;
6413 }
6414
6415 static void
6416 hns3_record_imp_error(struct hns3_adapter *hns)
6417 {
6418         struct hns3_hw *hw = &hns->hw;
6419         uint32_t reg_val;
6420
6421         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6422         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6423                 hns3_warn(hw, "Detected IMP RD poison!");
6424                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6425                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6426         }
6427
6428         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6429                 hns3_warn(hw, "Detected IMP CMDQ error!");
6430                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6431                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6432         }
6433 }
6434
6435 static int
6436 hns3_prepare_reset(struct hns3_adapter *hns)
6437 {
6438         struct hns3_hw *hw = &hns->hw;
6439         uint32_t reg_val;
6440         int ret;
6441
6442         switch (hw->reset.level) {
6443         case HNS3_FUNC_RESET:
6444                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6445                 if (ret)
6446                         return ret;
6447
6448                 /*
6449                  * After performaning pf reset, it is not necessary to do the
6450                  * mailbox handling or send any command to firmware, because
6451                  * any mailbox handling or command to firmware is only valid
6452                  * after hns3_cmd_init is called.
6453                  */
6454                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6455                 hw->reset.stats.request_cnt++;
6456                 break;
6457         case HNS3_IMP_RESET:
6458                 hns3_record_imp_error(hns);
6459                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6460                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6461                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6462                 break;
6463         default:
6464                 break;
6465         }
6466         return 0;
6467 }
6468
6469 static int
6470 hns3_set_rst_done(struct hns3_hw *hw)
6471 {
6472         struct hns3_pf_rst_done_cmd *req;
6473         struct hns3_cmd_desc desc;
6474
6475         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6476         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6477         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6478         return hns3_cmd_send(hw, &desc, 1);
6479 }
6480
6481 static int
6482 hns3_stop_service(struct hns3_adapter *hns)
6483 {
6484         struct hns3_hw *hw = &hns->hw;
6485         struct rte_eth_dev *eth_dev;
6486
6487         eth_dev = &rte_eth_devices[hw->data->port_id];
6488         hw->mac.link_status = ETH_LINK_DOWN;
6489         if (hw->adapter_state == HNS3_NIC_STARTED) {
6490                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6491                 hns3_update_linkstatus_and_event(hw, false);
6492         }
6493
6494         hns3_set_rxtx_function(eth_dev);
6495         rte_wmb();
6496         /* Disable datapath on secondary process. */
6497         hns3_mp_req_stop_rxtx(eth_dev);
6498         rte_delay_ms(hw->tqps_num);
6499
6500         rte_spinlock_lock(&hw->lock);
6501         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6502             hw->adapter_state == HNS3_NIC_STOPPING) {
6503                 hns3_enable_all_queues(hw, false);
6504                 hns3_do_stop(hns);
6505                 hw->reset.mbuf_deferred_free = true;
6506         } else
6507                 hw->reset.mbuf_deferred_free = false;
6508
6509         /*
6510          * It is cumbersome for hardware to pick-and-choose entries for deletion
6511          * from table space. Hence, for function reset software intervention is
6512          * required to delete the entries
6513          */
6514         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6515                 hns3_configure_all_mc_mac_addr(hns, true);
6516         rte_spinlock_unlock(&hw->lock);
6517
6518         return 0;
6519 }
6520
6521 static int
6522 hns3_start_service(struct hns3_adapter *hns)
6523 {
6524         struct hns3_hw *hw = &hns->hw;
6525         struct rte_eth_dev *eth_dev;
6526
6527         if (hw->reset.level == HNS3_IMP_RESET ||
6528             hw->reset.level == HNS3_GLOBAL_RESET)
6529                 hns3_set_rst_done(hw);
6530         eth_dev = &rte_eth_devices[hw->data->port_id];
6531         hns3_set_rxtx_function(eth_dev);
6532         hns3_mp_req_start_rxtx(eth_dev);
6533         if (hw->adapter_state == HNS3_NIC_STARTED) {
6534                 /*
6535                  * This API parent function already hold the hns3_hw.lock, the
6536                  * hns3_service_handler may report lse, in bonding application
6537                  * it will call driver's ops which may acquire the hns3_hw.lock
6538                  * again, thus lead to deadlock.
6539                  * We defer calls hns3_service_handler to avoid the deadlock.
6540                  */
6541                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6542                                   hns3_service_handler, eth_dev);
6543
6544                 /* Enable interrupt of all rx queues before enabling queues */
6545                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6546                 /*
6547                  * Enable state of each rxq and txq will be recovered after
6548                  * reset, so we need to restore them before enable all tqps;
6549                  */
6550                 hns3_restore_tqp_enable_state(hw);
6551                 /*
6552                  * When finished the initialization, enable queues to receive
6553                  * and transmit packets.
6554                  */
6555                 hns3_enable_all_queues(hw, true);
6556         }
6557
6558         return 0;
6559 }
6560
6561 static int
6562 hns3_restore_conf(struct hns3_adapter *hns)
6563 {
6564         struct hns3_hw *hw = &hns->hw;
6565         int ret;
6566
6567         ret = hns3_configure_all_mac_addr(hns, false);
6568         if (ret)
6569                 return ret;
6570
6571         ret = hns3_configure_all_mc_mac_addr(hns, false);
6572         if (ret)
6573                 goto err_mc_mac;
6574
6575         ret = hns3_dev_promisc_restore(hns);
6576         if (ret)
6577                 goto err_promisc;
6578
6579         ret = hns3_restore_vlan_table(hns);
6580         if (ret)
6581                 goto err_promisc;
6582
6583         ret = hns3_restore_vlan_conf(hns);
6584         if (ret)
6585                 goto err_promisc;
6586
6587         ret = hns3_restore_all_fdir_filter(hns);
6588         if (ret)
6589                 goto err_promisc;
6590
6591         ret = hns3_restore_ptp(hns);
6592         if (ret)
6593                 goto err_promisc;
6594
6595         ret = hns3_restore_rx_interrupt(hw);
6596         if (ret)
6597                 goto err_promisc;
6598
6599         ret = hns3_restore_gro_conf(hw);
6600         if (ret)
6601                 goto err_promisc;
6602
6603         ret = hns3_restore_fec(hw);
6604         if (ret)
6605                 goto err_promisc;
6606
6607         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6608                 ret = hns3_do_start(hns, false);
6609                 if (ret)
6610                         goto err_promisc;
6611                 hns3_info(hw, "hns3 dev restart successful!");
6612         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6613                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6614         return 0;
6615
6616 err_promisc:
6617         hns3_configure_all_mc_mac_addr(hns, true);
6618 err_mc_mac:
6619         hns3_configure_all_mac_addr(hns, true);
6620         return ret;
6621 }
6622
6623 static void
6624 hns3_reset_service(void *param)
6625 {
6626         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6627         struct hns3_hw *hw = &hns->hw;
6628         enum hns3_reset_level reset_level;
6629         struct timeval tv_delta;
6630         struct timeval tv_start;
6631         struct timeval tv;
6632         uint64_t msec;
6633         int ret;
6634
6635         /*
6636          * The interrupt is not triggered within the delay time.
6637          * The interrupt may have been lost. It is necessary to handle
6638          * the interrupt to recover from the error.
6639          */
6640         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6641                             SCHEDULE_DEFERRED) {
6642                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6643                                   __ATOMIC_RELAXED);
6644                 hns3_err(hw, "Handling interrupts in delayed tasks");
6645                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6646                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6647                 if (reset_level == HNS3_NONE_RESET) {
6648                         hns3_err(hw, "No reset level is set, try IMP reset");
6649                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6650                 }
6651         }
6652         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6653
6654         /*
6655          * Check if there is any ongoing reset in the hardware. This status can
6656          * be checked from reset_pending. If there is then, we need to wait for
6657          * hardware to complete reset.
6658          *    a. If we are able to figure out in reasonable time that hardware
6659          *       has fully resetted then, we can proceed with driver, client
6660          *       reset.
6661          *    b. else, we can come back later to check this status so re-sched
6662          *       now.
6663          */
6664         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6665         if (reset_level != HNS3_NONE_RESET) {
6666                 gettimeofday(&tv_start, NULL);
6667                 ret = hns3_reset_process(hns, reset_level);
6668                 gettimeofday(&tv, NULL);
6669                 timersub(&tv, &tv_start, &tv_delta);
6670                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6671                        tv_delta.tv_usec / USEC_PER_MSEC;
6672                 if (msec > HNS3_RESET_PROCESS_MS)
6673                         hns3_err(hw, "%d handle long time delta %" PRIx64
6674                                      " ms time=%ld.%.6ld",
6675                                  hw->reset.level, msec,
6676                                  tv.tv_sec, tv.tv_usec);
6677                 if (ret == -EAGAIN)
6678                         return;
6679         }
6680
6681         /* Check if we got any *new* reset requests to be honored */
6682         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6683         if (reset_level != HNS3_NONE_RESET)
6684                 hns3_msix_process(hns, reset_level);
6685 }
6686
6687 static unsigned int
6688 hns3_get_speed_capa_num(uint16_t device_id)
6689 {
6690         unsigned int num;
6691
6692         switch (device_id) {
6693         case HNS3_DEV_ID_25GE:
6694         case HNS3_DEV_ID_25GE_RDMA:
6695                 num = 2;
6696                 break;
6697         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6698         case HNS3_DEV_ID_200G_RDMA:
6699                 num = 1;
6700                 break;
6701         default:
6702                 num = 0;
6703                 break;
6704         }
6705
6706         return num;
6707 }
6708
6709 static int
6710 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6711                         uint16_t device_id)
6712 {
6713         switch (device_id) {
6714         case HNS3_DEV_ID_25GE:
6715         /* fallthrough */
6716         case HNS3_DEV_ID_25GE_RDMA:
6717                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6718                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6719
6720                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6721                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6722                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6723                 break;
6724         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6725                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6726                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6727                 break;
6728         case HNS3_DEV_ID_200G_RDMA:
6729                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6730                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6731                 break;
6732         default:
6733                 return -ENOTSUP;
6734         }
6735
6736         return 0;
6737 }
6738
6739 static int
6740 hns3_fec_get_capability(struct rte_eth_dev *dev,
6741                         struct rte_eth_fec_capa *speed_fec_capa,
6742                         unsigned int num)
6743 {
6744         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6746         uint16_t device_id = pci_dev->id.device_id;
6747         unsigned int capa_num;
6748         int ret;
6749
6750         capa_num = hns3_get_speed_capa_num(device_id);
6751         if (capa_num == 0) {
6752                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6753                          device_id);
6754                 return -ENOTSUP;
6755         }
6756
6757         if (speed_fec_capa == NULL || num < capa_num)
6758                 return capa_num;
6759
6760         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6761         if (ret)
6762                 return -ENOTSUP;
6763
6764         return capa_num;
6765 }
6766
6767 static int
6768 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6769 {
6770         struct hns3_config_fec_cmd *req;
6771         struct hns3_cmd_desc desc;
6772         int ret;
6773
6774         /*
6775          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6776          * in device of link speed
6777          * below 10 Gbps.
6778          */
6779         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6780                 *state = 0;
6781                 return 0;
6782         }
6783
6784         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6785         req = (struct hns3_config_fec_cmd *)desc.data;
6786         ret = hns3_cmd_send(hw, &desc, 1);
6787         if (ret) {
6788                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6789                          ret);
6790                 return ret;
6791         }
6792
6793         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6794         return 0;
6795 }
6796
6797 static int
6798 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6799 {
6800         struct hns3_sfp_info_cmd *resp;
6801         uint32_t tmp_fec_capa;
6802         uint8_t auto_state;
6803         struct hns3_cmd_desc desc;
6804         int ret;
6805
6806         /*
6807          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6808          * configured FEC mode is returned.
6809          * If link is up, current FEC mode is returned.
6810          */
6811         if (hw->mac.link_status == ETH_LINK_DOWN) {
6812                 ret = get_current_fec_auto_state(hw, &auto_state);
6813                 if (ret)
6814                         return ret;
6815
6816                 if (auto_state == 0x1) {
6817                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6818                         return 0;
6819                 }
6820         }
6821
6822         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6823         resp = (struct hns3_sfp_info_cmd *)desc.data;
6824         resp->query_type = HNS3_ACTIVE_QUERY;
6825
6826         ret = hns3_cmd_send(hw, &desc, 1);
6827         if (ret == -EOPNOTSUPP) {
6828                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6829                 return ret;
6830         } else if (ret) {
6831                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6832                 return ret;
6833         }
6834
6835         /*
6836          * FEC mode order defined in hns3 hardware is inconsistend with
6837          * that defined in the ethdev library. So the sequence needs
6838          * to be converted.
6839          */
6840         switch (resp->active_fec) {
6841         case HNS3_HW_FEC_MODE_NOFEC:
6842                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6843                 break;
6844         case HNS3_HW_FEC_MODE_BASER:
6845                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6846                 break;
6847         case HNS3_HW_FEC_MODE_RS:
6848                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6849                 break;
6850         default:
6851                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6852                 break;
6853         }
6854
6855         *fec_capa = tmp_fec_capa;
6856         return 0;
6857 }
6858
6859 static int
6860 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6861 {
6862         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6863
6864         return hns3_fec_get_internal(hw, fec_capa);
6865 }
6866
6867 static int
6868 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6869 {
6870         struct hns3_config_fec_cmd *req;
6871         struct hns3_cmd_desc desc;
6872         int ret;
6873
6874         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6875
6876         req = (struct hns3_config_fec_cmd *)desc.data;
6877         switch (mode) {
6878         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6879                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6880                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6881                 break;
6882         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6883                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6884                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6885                 break;
6886         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6887                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6888                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6889                 break;
6890         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6891                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6892                 break;
6893         default:
6894                 return 0;
6895         }
6896         ret = hns3_cmd_send(hw, &desc, 1);
6897         if (ret)
6898                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6899
6900         return ret;
6901 }
6902
6903 static uint32_t
6904 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6905 {
6906         struct hns3_mac *mac = &hw->mac;
6907         uint32_t cur_capa;
6908
6909         switch (mac->link_speed) {
6910         case ETH_SPEED_NUM_10G:
6911                 cur_capa = fec_capa[1].capa;
6912                 break;
6913         case ETH_SPEED_NUM_25G:
6914         case ETH_SPEED_NUM_100G:
6915         case ETH_SPEED_NUM_200G:
6916                 cur_capa = fec_capa[0].capa;
6917                 break;
6918         default:
6919                 cur_capa = 0;
6920                 break;
6921         }
6922
6923         return cur_capa;
6924 }
6925
6926 static bool
6927 is_fec_mode_one_bit_set(uint32_t mode)
6928 {
6929         int cnt = 0;
6930         uint8_t i;
6931
6932         for (i = 0; i < sizeof(mode); i++)
6933                 if (mode >> i & 0x1)
6934                         cnt++;
6935
6936         return cnt == 1 ? true : false;
6937 }
6938
6939 static int
6940 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6941 {
6942 #define FEC_CAPA_NUM 2
6943         struct hns3_adapter *hns = dev->data->dev_private;
6944         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6945         struct hns3_pf *pf = &hns->pf;
6946
6947         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6948         uint32_t cur_capa;
6949         uint32_t num = FEC_CAPA_NUM;
6950         int ret;
6951
6952         ret = hns3_fec_get_capability(dev, fec_capa, num);
6953         if (ret < 0)
6954                 return ret;
6955
6956         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6957         if (!is_fec_mode_one_bit_set(mode))
6958                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6959                              "FEC mode should be only one bit set", mode);
6960
6961         /*
6962          * Check whether the configured mode is within the FEC capability.
6963          * If not, the configured mode will not be supported.
6964          */
6965         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6966         if (!(cur_capa & mode)) {
6967                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6968                 return -EINVAL;
6969         }
6970
6971         rte_spinlock_lock(&hw->lock);
6972         ret = hns3_set_fec_hw(hw, mode);
6973         if (ret) {
6974                 rte_spinlock_unlock(&hw->lock);
6975                 return ret;
6976         }
6977
6978         pf->fec_mode = mode;
6979         rte_spinlock_unlock(&hw->lock);
6980
6981         return 0;
6982 }
6983
6984 static int
6985 hns3_restore_fec(struct hns3_hw *hw)
6986 {
6987         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6988         struct hns3_pf *pf = &hns->pf;
6989         uint32_t mode = pf->fec_mode;
6990         int ret;
6991
6992         ret = hns3_set_fec_hw(hw, mode);
6993         if (ret)
6994                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6995                          mode, ret);
6996
6997         return ret;
6998 }
6999
7000 static int
7001 hns3_query_dev_fec_info(struct hns3_hw *hw)
7002 {
7003         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7004         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7005         int ret;
7006
7007         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7008         if (ret)
7009                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7010
7011         return ret;
7012 }
7013
7014 static bool
7015 hns3_optical_module_existed(struct hns3_hw *hw)
7016 {
7017         struct hns3_cmd_desc desc;
7018         bool existed;
7019         int ret;
7020
7021         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7022         ret = hns3_cmd_send(hw, &desc, 1);
7023         if (ret) {
7024                 hns3_err(hw,
7025                          "fail to get optical module exist state, ret = %d.\n",
7026                          ret);
7027                 return false;
7028         }
7029         existed = !!desc.data[0];
7030
7031         return existed;
7032 }
7033
7034 static int
7035 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7036                                 uint32_t len, uint8_t *data)
7037 {
7038 #define HNS3_SFP_INFO_CMD_NUM 6
7039 #define HNS3_SFP_INFO_MAX_LEN \
7040         (HNS3_SFP_INFO_BD0_LEN + \
7041         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7042         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7043         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7044         uint16_t read_len;
7045         uint16_t copy_len;
7046         int ret;
7047         int i;
7048
7049         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7050                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7051                                           true);
7052                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7053                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7054         }
7055
7056         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7057         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7058         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7059         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7060
7061         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7062         if (ret) {
7063                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7064                                 ret);
7065                 return ret;
7066         }
7067
7068         /* The data format in BD0 is different with the others. */
7069         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7070         memcpy(data, sfp_info_bd0->data, copy_len);
7071         read_len = copy_len;
7072
7073         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7074                 if (read_len >= len)
7075                         break;
7076
7077                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7078                 memcpy(data + read_len, desc[i].data, copy_len);
7079                 read_len += copy_len;
7080         }
7081
7082         return (int)read_len;
7083 }
7084
7085 static int
7086 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7087                        struct rte_dev_eeprom_info *info)
7088 {
7089         struct hns3_adapter *hns = dev->data->dev_private;
7090         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7091         uint32_t offset = info->offset;
7092         uint32_t len = info->length;
7093         uint8_t *data = info->data;
7094         uint32_t read_len = 0;
7095
7096         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7097                 return -ENOTSUP;
7098
7099         if (!hns3_optical_module_existed(hw)) {
7100                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7101                 return -EIO;
7102         }
7103
7104         while (read_len < len) {
7105                 int ret;
7106                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7107                                                   len - read_len,
7108                                                   data + read_len);
7109                 if (ret < 0)
7110                         return -EIO;
7111                 read_len += ret;
7112         }
7113
7114         return 0;
7115 }
7116
7117 static int
7118 hns3_get_module_info(struct rte_eth_dev *dev,
7119                      struct rte_eth_dev_module_info *modinfo)
7120 {
7121 #define HNS3_SFF8024_ID_SFP             0x03
7122 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7123 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7124 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7125 #define HNS3_SFF_8636_V1_3              0x03
7126         struct hns3_adapter *hns = dev->data->dev_private;
7127         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7128         struct rte_dev_eeprom_info info;
7129         struct hns3_sfp_type sfp_type;
7130         int ret;
7131
7132         memset(&sfp_type, 0, sizeof(sfp_type));
7133         memset(&info, 0, sizeof(info));
7134         info.data = (uint8_t *)&sfp_type;
7135         info.length = sizeof(sfp_type);
7136         ret = hns3_get_module_eeprom(dev, &info);
7137         if (ret)
7138                 return ret;
7139
7140         switch (sfp_type.type) {
7141         case HNS3_SFF8024_ID_SFP:
7142                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7143                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7144                 break;
7145         case HNS3_SFF8024_ID_QSFP_8438:
7146                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7147                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7148                 break;
7149         case HNS3_SFF8024_ID_QSFP_8436_8636:
7150                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7151                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7152                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7153                 } else {
7154                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7155                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7156                 }
7157                 break;
7158         case HNS3_SFF8024_ID_QSFP28_8636:
7159                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7160                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7161                 break;
7162         default:
7163                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7164                          sfp_type.type, sfp_type.ext_type);
7165                 return -EINVAL;
7166         }
7167
7168         return 0;
7169 }
7170
7171 static int
7172 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7173 {
7174         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7175
7176         RTE_SET_USED(key);
7177
7178         if (strcmp(value, "vec") == 0)
7179                 hint = HNS3_IO_FUNC_HINT_VEC;
7180         else if (strcmp(value, "sve") == 0)
7181                 hint = HNS3_IO_FUNC_HINT_SVE;
7182         else if (strcmp(value, "simple") == 0)
7183                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7184         else if (strcmp(value, "common") == 0)
7185                 hint = HNS3_IO_FUNC_HINT_COMMON;
7186
7187         /* If the hint is valid then update output parameters */
7188         if (hint != HNS3_IO_FUNC_HINT_NONE)
7189                 *(uint32_t *)extra_args = hint;
7190
7191         return 0;
7192 }
7193
7194 static const char *
7195 hns3_get_io_hint_func_name(uint32_t hint)
7196 {
7197         switch (hint) {
7198         case HNS3_IO_FUNC_HINT_VEC:
7199                 return "vec";
7200         case HNS3_IO_FUNC_HINT_SVE:
7201                 return "sve";
7202         case HNS3_IO_FUNC_HINT_SIMPLE:
7203                 return "simple";
7204         case HNS3_IO_FUNC_HINT_COMMON:
7205                 return "common";
7206         default:
7207                 return "none";
7208         }
7209 }
7210
7211 void
7212 hns3_parse_devargs(struct rte_eth_dev *dev)
7213 {
7214         struct hns3_adapter *hns = dev->data->dev_private;
7215         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7216         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7217         struct hns3_hw *hw = &hns->hw;
7218         struct rte_kvargs *kvlist;
7219
7220         if (dev->device->devargs == NULL)
7221                 return;
7222
7223         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7224         if (!kvlist)
7225                 return;
7226
7227         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7228                            &hns3_parse_io_hint_func, &rx_func_hint);
7229         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7230                            &hns3_parse_io_hint_func, &tx_func_hint);
7231         rte_kvargs_free(kvlist);
7232
7233         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7234                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7235                           hns3_get_io_hint_func_name(rx_func_hint));
7236         hns->rx_func_hint = rx_func_hint;
7237         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7238                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7239                           hns3_get_io_hint_func_name(tx_func_hint));
7240         hns->tx_func_hint = tx_func_hint;
7241 }
7242
7243 static const struct eth_dev_ops hns3_eth_dev_ops = {
7244         .dev_configure      = hns3_dev_configure,
7245         .dev_start          = hns3_dev_start,
7246         .dev_stop           = hns3_dev_stop,
7247         .dev_close          = hns3_dev_close,
7248         .promiscuous_enable = hns3_dev_promiscuous_enable,
7249         .promiscuous_disable = hns3_dev_promiscuous_disable,
7250         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7251         .allmulticast_disable = hns3_dev_allmulticast_disable,
7252         .mtu_set            = hns3_dev_mtu_set,
7253         .stats_get          = hns3_stats_get,
7254         .stats_reset        = hns3_stats_reset,
7255         .xstats_get         = hns3_dev_xstats_get,
7256         .xstats_get_names   = hns3_dev_xstats_get_names,
7257         .xstats_reset       = hns3_dev_xstats_reset,
7258         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7259         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7260         .dev_infos_get          = hns3_dev_infos_get,
7261         .fw_version_get         = hns3_fw_version_get,
7262         .rx_queue_setup         = hns3_rx_queue_setup,
7263         .tx_queue_setup         = hns3_tx_queue_setup,
7264         .rx_queue_release       = hns3_dev_rx_queue_release,
7265         .tx_queue_release       = hns3_dev_tx_queue_release,
7266         .rx_queue_start         = hns3_dev_rx_queue_start,
7267         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7268         .tx_queue_start         = hns3_dev_tx_queue_start,
7269         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7270         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7271         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7272         .rxq_info_get           = hns3_rxq_info_get,
7273         .txq_info_get           = hns3_txq_info_get,
7274         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7275         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7276         .flow_ctrl_get          = hns3_flow_ctrl_get,
7277         .flow_ctrl_set          = hns3_flow_ctrl_set,
7278         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7279         .mac_addr_add           = hns3_add_mac_addr,
7280         .mac_addr_remove        = hns3_remove_mac_addr,
7281         .mac_addr_set           = hns3_set_default_mac_addr,
7282         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7283         .link_update            = hns3_dev_link_update,
7284         .rss_hash_update        = hns3_dev_rss_hash_update,
7285         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7286         .reta_update            = hns3_dev_rss_reta_update,
7287         .reta_query             = hns3_dev_rss_reta_query,
7288         .flow_ops_get           = hns3_dev_flow_ops_get,
7289         .vlan_filter_set        = hns3_vlan_filter_set,
7290         .vlan_tpid_set          = hns3_vlan_tpid_set,
7291         .vlan_offload_set       = hns3_vlan_offload_set,
7292         .vlan_pvid_set          = hns3_vlan_pvid_set,
7293         .get_reg                = hns3_get_regs,
7294         .get_module_info        = hns3_get_module_info,
7295         .get_module_eeprom      = hns3_get_module_eeprom,
7296         .get_dcb_info           = hns3_get_dcb_info,
7297         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7298         .fec_get_capability     = hns3_fec_get_capability,
7299         .fec_get                = hns3_fec_get,
7300         .fec_set                = hns3_fec_set,
7301         .tm_ops_get             = hns3_tm_ops_get,
7302         .tx_done_cleanup        = hns3_tx_done_cleanup,
7303         .timesync_enable            = hns3_timesync_enable,
7304         .timesync_disable           = hns3_timesync_disable,
7305         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7306         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7307         .timesync_adjust_time       = hns3_timesync_adjust_time,
7308         .timesync_read_time         = hns3_timesync_read_time,
7309         .timesync_write_time        = hns3_timesync_write_time,
7310 };
7311
7312 static const struct hns3_reset_ops hns3_reset_ops = {
7313         .reset_service       = hns3_reset_service,
7314         .stop_service        = hns3_stop_service,
7315         .prepare_reset       = hns3_prepare_reset,
7316         .wait_hardware_ready = hns3_wait_hardware_ready,
7317         .reinit_dev          = hns3_reinit_dev,
7318         .restore_conf        = hns3_restore_conf,
7319         .start_service       = hns3_start_service,
7320 };
7321
7322 static int
7323 hns3_dev_init(struct rte_eth_dev *eth_dev)
7324 {
7325         struct hns3_adapter *hns = eth_dev->data->dev_private;
7326         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7327         struct rte_ether_addr *eth_addr;
7328         struct hns3_hw *hw = &hns->hw;
7329         int ret;
7330
7331         PMD_INIT_FUNC_TRACE();
7332
7333         eth_dev->process_private = (struct hns3_process_private *)
7334             rte_zmalloc_socket("hns3_filter_list",
7335                                sizeof(struct hns3_process_private),
7336                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7337         if (eth_dev->process_private == NULL) {
7338                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7339                 return -ENOMEM;
7340         }
7341         /* initialize flow filter lists */
7342         hns3_filterlist_init(eth_dev);
7343
7344         hns3_set_rxtx_function(eth_dev);
7345         eth_dev->dev_ops = &hns3_eth_dev_ops;
7346         eth_dev->rx_queue_count = hns3_rx_queue_count;
7347         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7348                 ret = hns3_mp_init_secondary();
7349                 if (ret) {
7350                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7351                                      "process, ret = %d", ret);
7352                         goto err_mp_init_secondary;
7353                 }
7354
7355                 hw->secondary_cnt++;
7356                 return 0;
7357         }
7358
7359         ret = hns3_mp_init_primary();
7360         if (ret) {
7361                 PMD_INIT_LOG(ERR,
7362                              "Failed to init for primary process, ret = %d",
7363                              ret);
7364                 goto err_mp_init_primary;
7365         }
7366
7367         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7368         hns->is_vf = false;
7369         hw->data = eth_dev->data;
7370         hns3_parse_devargs(eth_dev);
7371
7372         /*
7373          * Set default max packet size according to the mtu
7374          * default vale in DPDK frame.
7375          */
7376         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7377
7378         ret = hns3_reset_init(hw);
7379         if (ret)
7380                 goto err_init_reset;
7381         hw->reset.ops = &hns3_reset_ops;
7382
7383         ret = hns3_init_pf(eth_dev);
7384         if (ret) {
7385                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7386                 goto err_init_pf;
7387         }
7388
7389         /* Allocate memory for storing MAC addresses */
7390         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7391                                                sizeof(struct rte_ether_addr) *
7392                                                HNS3_UC_MACADDR_NUM, 0);
7393         if (eth_dev->data->mac_addrs == NULL) {
7394                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7395                              "to store MAC addresses",
7396                              sizeof(struct rte_ether_addr) *
7397                              HNS3_UC_MACADDR_NUM);
7398                 ret = -ENOMEM;
7399                 goto err_rte_zmalloc;
7400         }
7401
7402         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7403         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7404                 rte_eth_random_addr(hw->mac.mac_addr);
7405                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7406                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7407                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7408                           "unicast address, using random MAC address %s",
7409                           mac_str);
7410         }
7411         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7412                             &eth_dev->data->mac_addrs[0]);
7413
7414         hw->adapter_state = HNS3_NIC_INITIALIZED;
7415
7416         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7417                             SCHEDULE_PENDING) {
7418                 hns3_err(hw, "Reschedule reset service after dev_init");
7419                 hns3_schedule_reset(hns);
7420         } else {
7421                 /* IMP will wait ready flag before reset */
7422                 hns3_notify_reset_ready(hw, false);
7423         }
7424
7425         hns3_info(hw, "hns3 dev initialization successful!");
7426         return 0;
7427
7428 err_rte_zmalloc:
7429         hns3_uninit_pf(eth_dev);
7430
7431 err_init_pf:
7432         rte_free(hw->reset.wait_data);
7433
7434 err_init_reset:
7435         hns3_mp_uninit_primary();
7436
7437 err_mp_init_primary:
7438 err_mp_init_secondary:
7439         eth_dev->dev_ops = NULL;
7440         eth_dev->rx_pkt_burst = NULL;
7441         eth_dev->rx_descriptor_status = NULL;
7442         eth_dev->tx_pkt_burst = NULL;
7443         eth_dev->tx_pkt_prepare = NULL;
7444         eth_dev->tx_descriptor_status = NULL;
7445         rte_free(eth_dev->process_private);
7446         eth_dev->process_private = NULL;
7447         return ret;
7448 }
7449
7450 static int
7451 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7452 {
7453         struct hns3_adapter *hns = eth_dev->data->dev_private;
7454         struct hns3_hw *hw = &hns->hw;
7455
7456         PMD_INIT_FUNC_TRACE();
7457
7458         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7459                 rte_free(eth_dev->process_private);
7460                 eth_dev->process_private = NULL;
7461                 return 0;
7462         }
7463
7464         if (hw->adapter_state < HNS3_NIC_CLOSING)
7465                 hns3_dev_close(eth_dev);
7466
7467         hw->adapter_state = HNS3_NIC_REMOVED;
7468         return 0;
7469 }
7470
7471 static int
7472 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7473                    struct rte_pci_device *pci_dev)
7474 {
7475         return rte_eth_dev_pci_generic_probe(pci_dev,
7476                                              sizeof(struct hns3_adapter),
7477                                              hns3_dev_init);
7478 }
7479
7480 static int
7481 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7482 {
7483         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7484 }
7485
7486 static const struct rte_pci_id pci_id_hns3_map[] = {
7487         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7488         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7489         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7490         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7491         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7492         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7493         { .vendor_id = 0, }, /* sentinel */
7494 };
7495
7496 static struct rte_pci_driver rte_hns3_pmd = {
7497         .id_table = pci_id_hns3_map,
7498         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7499         .probe = eth_hns3_pci_probe,
7500         .remove = eth_hns3_pci_remove,
7501 };
7502
7503 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7504 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7505 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7506 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7507                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7508                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common ");
7509 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7510 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);