drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_INVLID_PVID                0xFFFF
  39
  40 #define HNS3_FILTER_TYPE_VF             0
  41 #define HNS3_FILTER_TYPE_PORT           1
  42 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  43 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  44 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  45 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  46 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  47 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  49 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  51
  52 /* Reset related Registers */
  53 #define HNS3_GLOBAL_RESET_BIT           0
  54 #define HNS3_CORE_RESET_BIT             1
  55 #define HNS3_IMP_RESET_BIT              2
  56 #define HNS3_FUN_RST_ING_B              0
  57
  58 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  59
  60 #define HNS3_RESET_WAIT_MS      100
  61 #define HNS3_RESET_WAIT_CNT     200
  62
  63 enum hns3_evt_cause {
  64         HNS3_VECTOR0_EVENT_RST,
  65         HNS3_VECTOR0_EVENT_MBX,
  66         HNS3_VECTOR0_EVENT_ERR,
  67         HNS3_VECTOR0_EVENT_OTHER,
  68 };
  69
  70 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  71                                                  uint64_t *levels);
  72 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  73 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  74                                     int on);
  75 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  76
  77 static int hns3_add_mc_addr(struct hns3_hw *hw,
  78                             struct rte_ether_addr *mac_addr);
  79 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  80                             struct rte_ether_addr *mac_addr);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_ID_OFFSET_STEP        160
 236 #define HNS3_VLAN_BYTE_SIZE             8
 237         struct hns3_vlan_filter_pf_cfg_cmd *req;
 238         struct hns3_hw *hw = &hns->hw;
 239         uint8_t vlan_offset_byte_val;
 240         struct hns3_cmd_desc desc;
 241         uint8_t vlan_offset_byte;
 242         uint8_t vlan_offset_base;
 243         int ret;
 244
 245         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 246
 247         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 248         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 249                            HNS3_VLAN_BYTE_SIZE;
 250         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 251
 252         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 253         req->vlan_offset = vlan_offset_base;
 254         req->vlan_cfg = on ? 0 : 1;
 255         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 256
 257         ret = hns3_cmd_send(hw, &desc, 1);
 258         if (ret)
 259                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 260                          vlan_id, ret);
 261
 262         return ret;
 263 }
 264
 265 static void
 266 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 267 {
 268         struct hns3_user_vlan_table *vlan_entry;
 269         struct hns3_pf *pf = &hns->pf;
 270
 271         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 272                 if (vlan_entry->vlan_id == vlan_id) {
 273                         if (vlan_entry->hd_tbl_status)
 274                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 275                         LIST_REMOVE(vlan_entry, next);
 276                         rte_free(vlan_entry);
 277                         break;
 278                 }
 279         }
 280 }
 281
 282 static void
 283 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 284                         bool writen_to_tbl)
 285 {
 286         struct hns3_user_vlan_table *vlan_entry;
 287         struct hns3_hw *hw = &hns->hw;
 288         struct hns3_pf *pf = &hns->pf;
 289
 290         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 291                 if (vlan_entry->vlan_id == vlan_id)
 292                         return;
 293         }
 294
 295         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 296         if (vlan_entry == NULL) {
 297                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 298                 return;
 299         }
 300
 301         vlan_entry->hd_tbl_status = writen_to_tbl;
 302         vlan_entry->vlan_id = vlan_id;
 303
 304         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 305 }
 306
 307 static int
 308 hns3_restore_vlan_table(struct hns3_adapter *hns)
 309 {
 310         struct hns3_user_vlan_table *vlan_entry;
 311         struct hns3_hw *hw = &hns->hw;
 312         struct hns3_pf *pf = &hns->pf;
 313         uint16_t vlan_id;
 314         int ret = 0;
 315
 316         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 317                 return hns3_vlan_pvid_configure(hns,
 318                                                 hw->port_base_vlan_cfg.pvid, 1);
 319
 320         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 321                 if (vlan_entry->hd_tbl_status) {
 322                         vlan_id = vlan_entry->vlan_id;
 323                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 324                         if (ret)
 325                                 break;
 326                 }
 327         }
 328
 329         return ret;
 330 }
 331
 332 static int
 333 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 334 {
 335         struct hns3_hw *hw = &hns->hw;
 336         bool writen_to_tbl = false;
 337         int ret = 0;
 338
 339         /*
 340          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 341          * for normal packet, deleting vlan id 0 is not allowed.
 342          */
 343         if (on == 0 && vlan_id == 0)
 344                 return 0;
 345
 346         /*
 347          * When port base vlan enabled, we use port base vlan as the vlan
 348          * filter condition. In this case, we don't update vlan filter table
 349          * when user add new vlan or remove exist vlan, just update the
 350          * vlan list. The vlan id in vlan list will be writen in vlan filter
 351          * table until port base vlan disabled
 352          */
 353         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 354                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 355                 writen_to_tbl = true;
 356         }
 357
 358         if (ret == 0 && vlan_id) {
 359                 if (on)
 360                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 361                 else
 362                         hns3_rm_dev_vlan_table(hns, vlan_id);
 363         }
 364         return ret;
 365 }
 366
 367 static int
 368 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 369 {
 370         struct hns3_adapter *hns = dev->data->dev_private;
 371         struct hns3_hw *hw = &hns->hw;
 372         int ret;
 373
 374         rte_spinlock_lock(&hw->lock);
 375         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 376         rte_spinlock_unlock(&hw->lock);
 377         return ret;
 378 }
 379
 380 static int
 381 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 382                          uint16_t tpid)
 383 {
 384         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 385         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 386         struct hns3_hw *hw = &hns->hw;
 387         struct hns3_cmd_desc desc;
 388         int ret;
 389
 390         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 391              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 392                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 393                 return -EINVAL;
 394         }
 395
 396         if (tpid != RTE_ETHER_TYPE_VLAN) {
 397                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 398                 return -EINVAL;
 399         }
 400
 401         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 402         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 403
 404         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 405                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 406                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 407         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 408                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 411                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 412         }
 413
 414         ret = hns3_cmd_send(hw, &desc, 1);
 415         if (ret) {
 416                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 417                          ret);
 418                 return ret;
 419         }
 420
 421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 422
 423         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 424         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 425         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 426
 427         ret = hns3_cmd_send(hw, &desc, 1);
 428         if (ret)
 429                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 430                          ret);
 431         return ret;
 432 }
 433
 434 static int
 435 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 436                    uint16_t tpid)
 437 {
 438         struct hns3_adapter *hns = dev->data->dev_private;
 439         struct hns3_hw *hw = &hns->hw;
 440         int ret;
 441
 442         rte_spinlock_lock(&hw->lock);
 443         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 444         rte_spinlock_unlock(&hw->lock);
 445         return ret;
 446 }
 447
 448 static int
 449 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 450                              struct hns3_rx_vtag_cfg *vcfg)
 451 {
 452         struct hns3_vport_vtag_rx_cfg_cmd *req;
 453         struct hns3_hw *hw = &hns->hw;
 454         struct hns3_cmd_desc desc;
 455         uint16_t vport_id;
 456         uint8_t bitmap;
 457         int ret;
 458
 459         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 460
 461         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 462         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 463                      vcfg->strip_tag1_en ? 1 : 0);
 464         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 465                      vcfg->strip_tag2_en ? 1 : 0);
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 467                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 469                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 470
 471         /*
 472          * In current version VF is not supported when PF is driven by DPDK
 473          * driver, just need to configure parameters for PF vport.
 474          */
 475         vport_id = HNS3_PF_FUNC_ID;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_hw *hw = &hns->hw;
 507         int ret;
 508
 509         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 510                 rxvlan_cfg.strip_tag1_en = false;
 511                 rxvlan_cfg.strip_tag2_en = enable;
 512         } else {
 513                 rxvlan_cfg.strip_tag1_en = enable;
 514                 rxvlan_cfg.strip_tag2_en = true;
 515         }
 516
 517         rxvlan_cfg.vlan1_vlan_prionly = false;
 518         rxvlan_cfg.vlan2_vlan_prionly = false;
 519         rxvlan_cfg.rx_vlan_offload_en = enable;
 520
 521         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 522         if (ret) {
 523                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 524                 return ret;
 525         }
 526
 527         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 534                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 535 {
 536         struct hns3_vlan_filter_ctrl_cmd *req;
 537         struct hns3_cmd_desc desc;
 538         int ret;
 539
 540         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 541
 542         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 543         req->vlan_type = vlan_type;
 544         req->vlan_fe = filter_en ? fe_type : 0;
 545         req->vf_id = vf_id;
 546
 547         ret = hns3_cmd_send(hw, &desc, 1);
 548         if (ret)
 549                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 550
 551         return ret;
 552 }
 553
 554 static int
 555 hns3_vlan_filter_init(struct hns3_adapter *hns)
 556 {
 557         struct hns3_hw *hw = &hns->hw;
 558         int ret;
 559
 560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 561                                         HNS3_FILTER_FE_EGRESS, false,
 562                                         HNS3_PF_FUNC_ID);
 563         if (ret) {
 564                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, false,
 570                                         HNS3_PF_FUNC_ID);
 571         if (ret)
 572                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 573
 574         return ret;
 575 }
 576
 577 static int
 578 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 579 {
 580         struct hns3_hw *hw = &hns->hw;
 581         int ret;
 582
 583         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 584                                         HNS3_FILTER_FE_INGRESS, enable,
 585                                         HNS3_PF_FUNC_ID);
 586         if (ret)
 587                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 588                          enable ? "enable" : "disable", ret);
 589
 590         return ret;
 591 }
 592
 593 static int
 594 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 595 {
 596         struct hns3_adapter *hns = dev->data->dev_private;
 597         struct hns3_hw *hw = &hns->hw;
 598         struct rte_eth_rxmode *rxmode;
 599         unsigned int tmp_mask;
 600         bool enable;
 601         int ret = 0;
 602
 603         rte_spinlock_lock(&hw->lock);
 604         rxmode = &dev->data->dev_conf.rxmode;
 605         tmp_mask = (unsigned int)mask;
 606         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 607                 /* ignore vlan filter configuration during promiscuous mode */
 608                 if (!dev->data->promiscuous) {
 609                         /* Enable or disable VLAN filter */
 610                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 611                                  true : false;
 612
 613                         ret = hns3_enable_vlan_filter(hns, enable);
 614                         if (ret) {
 615                                 rte_spinlock_unlock(&hw->lock);
 616                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 617                                          enable ? "enable" : "disable", ret);
 618                                 return ret;
 619                         }
 620                 }
 621         }
 622
 623         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 624                 /* Enable or disable VLAN stripping */
 625                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 626                     true : false;
 627
 628                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 629                 if (ret) {
 630                         rte_spinlock_unlock(&hw->lock);
 631                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 632                                  enable ? "enable" : "disable", ret);
 633                         return ret;
 634                 }
 635         }
 636
 637         rte_spinlock_unlock(&hw->lock);
 638
 639         return ret;
 640 }
 641
 642 static int
 643 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 644                              struct hns3_tx_vtag_cfg *vcfg)
 645 {
 646         struct hns3_vport_vtag_tx_cfg_cmd *req;
 647         struct hns3_cmd_desc desc;
 648         struct hns3_hw *hw = &hns->hw;
 649         uint16_t vport_id;
 650         uint8_t bitmap;
 651         int ret;
 652
 653         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 654
 655         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 656         req->def_vlan_tag1 = vcfg->default_tag1;
 657         req->def_vlan_tag2 = vcfg->default_tag2;
 658         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 659                      vcfg->accept_tag1 ? 1 : 0);
 660         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 661                      vcfg->accept_untag1 ? 1 : 0);
 662         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 663                      vcfg->accept_tag2 ? 1 : 0);
 664         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 665                      vcfg->accept_untag2 ? 1 : 0);
 666         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 667                      vcfg->insert_tag1_en ? 1 : 0);
 668         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 669                      vcfg->insert_tag2_en ? 1 : 0);
 670         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 671
 672         /*
 673          * In current version VF is not supported when PF is driven by DPDK
 674          * driver, just need to configure parameters for PF vport.
 675          */
 676         vport_id = HNS3_PF_FUNC_ID;
 677         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 678         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 679         req->vf_bitmap[req->vf_offset] = bitmap;
 680
 681         ret = hns3_cmd_send(hw, &desc, 1);
 682         if (ret)
 683                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 684
 685         return ret;
 686 }
 687
 688 static int
 689 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 690                      uint16_t pvid)
 691 {
 692         struct hns3_hw *hw = &hns->hw;
 693         struct hns3_tx_vtag_cfg txvlan_cfg;
 694         int ret;
 695
 696         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 697                 txvlan_cfg.accept_tag1 = true;
 698                 txvlan_cfg.insert_tag1_en = false;
 699                 txvlan_cfg.default_tag1 = 0;
 700         } else {
 701                 txvlan_cfg.accept_tag1 = false;
 702                 txvlan_cfg.insert_tag1_en = true;
 703                 txvlan_cfg.default_tag1 = pvid;
 704         }
 705
 706         txvlan_cfg.accept_untag1 = true;
 707         txvlan_cfg.accept_tag2 = true;
 708         txvlan_cfg.accept_untag2 = true;
 709         txvlan_cfg.insert_tag2_en = false;
 710         txvlan_cfg.default_tag2 = 0;
 711
 712         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 713         if (ret) {
 714                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 715                          ret);
 716                 return ret;
 717         }
 718
 719         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 720         return ret;
 721 }
 722
 723 static void
 724 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 725 {
 726         struct hns3_hw *hw = &hns->hw;
 727
 728         hw->port_base_vlan_cfg.state = on ?
 729             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 730
 731         hw->port_base_vlan_cfg.pvid = pvid;
 732 }
 733
 734 static void
 735 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 736 {
 737         struct hns3_user_vlan_table *vlan_entry;
 738         struct hns3_pf *pf = &hns->pf;
 739
 740         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 741                 if (vlan_entry->hd_tbl_status)
 742                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 743
 744                 vlan_entry->hd_tbl_status = false;
 745         }
 746
 747         if (is_del_list) {
 748                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 749                 while (vlan_entry) {
 750                         LIST_REMOVE(vlan_entry, next);
 751                         rte_free(vlan_entry);
 752                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 }
 754         }
 755 }
 756
 757 static void
 758 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 759 {
 760         struct hns3_user_vlan_table *vlan_entry;
 761         struct hns3_pf *pf = &hns->pf;
 762
 763         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 764                 if (!vlan_entry->hd_tbl_status)
 765                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 766
 767                 vlan_entry->hd_tbl_status = true;
 768         }
 769 }
 770
 771 static void
 772 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 773 {
 774         struct hns3_hw *hw = &hns->hw;
 775         int ret;
 776
 777         hns3_rm_all_vlan_table(hns, true);
 778         if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 779                 ret = hns3_set_port_vlan_filter(hns,
 780                                                 hw->port_base_vlan_cfg.pvid, 0);
 781                 if (ret) {
 782                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 783                                  ret);
 784                         return;
 785                 }
 786         }
 787 }
 788
 789 static int
 790 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 791                                 uint16_t port_base_vlan_state,
 792                                 uint16_t new_pvid, uint16_t old_pvid)
 793 {
 794         struct hns3_hw *hw = &hns->hw;
 795         int ret = 0;
 796
 797         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 798                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 799                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 800                         if (ret) {
 801                                 hns3_err(hw,
 802                                          "Failed to clear clear old pvid filter, ret =%d",
 803                                          ret);
 804                                 return ret;
 805                         }
 806                 }
 807
 808                 hns3_rm_all_vlan_table(hns, false);
 809                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 810         }
 811
 812         if (new_pvid != 0) {
 813                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 814                 if (ret) {
 815                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 816                                  ret);
 817                         return ret;
 818                 }
 819         }
 820
 821         if (new_pvid == hw->port_base_vlan_cfg.pvid)
 822                 hns3_add_all_vlan_table(hns);
 823
 824         return ret;
 825 }
 826
 827 static int
 828 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 829 {
 830         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 831         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 832         bool rx_strip_en;
 833         int ret;
 834
 835         rx_strip_en = old_cfg->rx_vlan_offload_en ? true : false;
 836         if (on) {
 837                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 838                 rx_vlan_cfg.strip_tag2_en = true;
 839         } else {
 840                 rx_vlan_cfg.strip_tag1_en = false;
 841                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 842         }
 843         rx_vlan_cfg.vlan1_vlan_prionly = false;
 844         rx_vlan_cfg.vlan2_vlan_prionly = false;
 845         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 846
 847         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 848         if (ret)
 849                 return ret;
 850
 851         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 852         return ret;
 853 }
 854
 855 static int
 856 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 857 {
 858         struct hns3_hw *hw = &hns->hw;
 859         uint16_t port_base_vlan_state;
 860         uint16_t old_pvid;
 861         int ret;
 862
 863         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 864                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 865                         hns3_warn(hw, "Invalid operation! As current pvid set "
 866                                   "is %u, disable pvid %u is invalid",
 867                                   hw->port_base_vlan_cfg.pvid, pvid);
 868                 return 0;
 869         }
 870
 871         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 872                                     HNS3_PORT_BASE_VLAN_DISABLE;
 873         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 874         if (ret) {
 875                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 876                          ret);
 877                 return ret;
 878         }
 879
 880         ret = hns3_en_pvid_strip(hns, on);
 881         if (ret) {
 882                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
 883                          "ret = %d", ret);
 884                 return ret;
 885         }
 886
 887         if (pvid == HNS3_INVLID_PVID)
 888                 goto out;
 889         old_pvid = hw->port_base_vlan_cfg.pvid;
 890         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 891                                               old_pvid);
 892         if (ret) {
 893                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 894                          ret);
 895                 return ret;
 896         }
 897
 898 out:
 899         hns3_store_port_base_vlan_info(hns, pvid, on);
 900         return ret;
 901 }
 902
 903 static int
 904 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 905 {
 906         struct hns3_adapter *hns = dev->data->dev_private;
 907         struct hns3_hw *hw = &hns->hw;
 908         int ret;
 909
 910         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 911                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 912                          RTE_ETHER_MAX_VLAN_ID);
 913                 return -EINVAL;
 914         }
 915
 916         rte_spinlock_lock(&hw->lock);
 917         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 918         rte_spinlock_unlock(&hw->lock);
 919         return ret;
 920 }
 921
 922 static void
 923 init_port_base_vlan_info(struct hns3_hw *hw)
 924 {
 925         hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 926         hw->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 927 }
 928
 929 static int
 930 hns3_default_vlan_config(struct hns3_adapter *hns)
 931 {
 932         struct hns3_hw *hw = &hns->hw;
 933         int ret;
 934
 935         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 936         if (ret)
 937                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 938         return ret;
 939 }
 940
 941 static int
 942 hns3_init_vlan_config(struct hns3_adapter *hns)
 943 {
 944         struct hns3_hw *hw = &hns->hw;
 945         int ret;
 946
 947         /*
 948          * This function can be called in the initialization and reset process,
 949          * when in reset process, it means that hardware had been reseted
 950          * successfully and we need to restore the hardware configuration to
 951          * ensure that the hardware configuration remains unchanged before and
 952          * after reset.
 953          */
 954         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 955                 init_port_base_vlan_info(hw);
 956
 957         ret = hns3_vlan_filter_init(hns);
 958         if (ret) {
 959                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 960                 return ret;
 961         }
 962
 963         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 964                                        RTE_ETHER_TYPE_VLAN);
 965         if (ret) {
 966                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 967                 return ret;
 968         }
 969
 970         /*
 971          * When in the reinit dev stage of the reset process, the following
 972          * vlan-related configurations may differ from those at initialization,
 973          * we will restore configurations to hardware in hns3_restore_vlan_table
 974          * and hns3_restore_vlan_conf later.
 975          */
 976         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 977                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 978                 if (ret) {
 979                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 980                         return ret;
 981                 }
 982
 983                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 984                 if (ret) {
 985                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 986                                  ret);
 987                         return ret;
 988                 }
 989         }
 990
 991         return hns3_default_vlan_config(hns);
 992 }
 993
 994 static int
 995 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 996 {
 997         struct hns3_pf *pf = &hns->pf;
 998         struct hns3_hw *hw = &hns->hw;
 999         uint64_t offloads;
1000         bool enable;
1001         int ret;
1002
1003         if (!hw->data->promiscuous) {
1004                 /* restore vlan filter states */
1005                 offloads = hw->data->dev_conf.rxmode.offloads;
1006                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1007                 ret = hns3_enable_vlan_filter(hns, enable);
1008                 if (ret) {
1009                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1010                                  "ret = %d", ret);
1011                         return ret;
1012                 }
1013         }
1014
1015         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1016         if (ret) {
1017                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1018                 return ret;
1019         }
1020
1021         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1022         if (ret)
1023                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1024
1025         return ret;
1026 }
1027
1028 static int
1029 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1030 {
1031         struct hns3_adapter *hns = dev->data->dev_private;
1032         struct rte_eth_dev_data *data = dev->data;
1033         struct rte_eth_txmode *txmode;
1034         struct hns3_hw *hw = &hns->hw;
1035         int mask;
1036         int ret;
1037
1038         txmode = &data->dev_conf.txmode;
1039         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1040                 hns3_warn(hw,
1041                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1042                           "configuration is not supported! Ignore these two "
1043                           "parameters: hw_vlan_reject_tagged(%d), "
1044                           "hw_vlan_reject_untagged(%d)",
1045                           txmode->hw_vlan_reject_tagged,
1046                           txmode->hw_vlan_reject_untagged);
1047
1048         /* Apply vlan offload setting */
1049         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1050         ret = hns3_vlan_offload_set(dev, mask);
1051         if (ret) {
1052                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1053                          ret);
1054                 return ret;
1055         }
1056
1057         /*
1058          * If pvid config is not set in rte_eth_conf, driver needn't to set
1059          * VLAN pvid related configuration to hardware.
1060          */
1061         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1062                 return 0;
1063
1064         /* Apply pvid setting */
1065         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1066                                  txmode->hw_vlan_insert_pvid);
1067         if (ret)
1068                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1069                          txmode->pvid, ret);
1070
1071         return ret;
1072 }
1073
1074 static int
1075 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1076                 unsigned int tso_mss_max)
1077 {
1078         struct hns3_cfg_tso_status_cmd *req;
1079         struct hns3_cmd_desc desc;
1080         uint16_t tso_mss;
1081
1082         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1083
1084         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1085
1086         tso_mss = 0;
1087         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1088                        tso_mss_min);
1089         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1090
1091         tso_mss = 0;
1092         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1093                        tso_mss_max);
1094         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1095
1096         return hns3_cmd_send(hw, &desc, 1);
1097 }
1098
1099 static int
1100 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1101                    uint16_t *allocated_size, bool is_alloc)
1102 {
1103         struct hns3_umv_spc_alc_cmd *req;
1104         struct hns3_cmd_desc desc;
1105         int ret;
1106
1107         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1108         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1109         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1110         req->space_size = rte_cpu_to_le_32(space_size);
1111
1112         ret = hns3_cmd_send(hw, &desc, 1);
1113         if (ret) {
1114                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1115                              is_alloc ? "allocate" : "free", ret);
1116                 return ret;
1117         }
1118
1119         if (is_alloc && allocated_size)
1120                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1121
1122         return 0;
1123 }
1124
1125 static int
1126 hns3_init_umv_space(struct hns3_hw *hw)
1127 {
1128         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1129         struct hns3_pf *pf = &hns->pf;
1130         uint16_t allocated_size = 0;
1131         int ret;
1132
1133         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1134                                  true);
1135         if (ret)
1136                 return ret;
1137
1138         if (allocated_size < pf->wanted_umv_size)
1139                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1140                              pf->wanted_umv_size, allocated_size);
1141
1142         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1143                                                 pf->wanted_umv_size;
1144         pf->used_umv_size = 0;
1145         return 0;
1146 }
1147
1148 static int
1149 hns3_uninit_umv_space(struct hns3_hw *hw)
1150 {
1151         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1152         struct hns3_pf *pf = &hns->pf;
1153         int ret;
1154
1155         if (pf->max_umv_size == 0)
1156                 return 0;
1157
1158         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1159         if (ret)
1160                 return ret;
1161
1162         pf->max_umv_size = 0;
1163
1164         return 0;
1165 }
1166
1167 static bool
1168 hns3_is_umv_space_full(struct hns3_hw *hw)
1169 {
1170         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1171         struct hns3_pf *pf = &hns->pf;
1172         bool is_full;
1173
1174         is_full = (pf->used_umv_size >= pf->max_umv_size);
1175
1176         return is_full;
1177 }
1178
1179 static void
1180 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1181 {
1182         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1183         struct hns3_pf *pf = &hns->pf;
1184
1185         if (is_free) {
1186                 if (pf->used_umv_size > 0)
1187                         pf->used_umv_size--;
1188         } else
1189                 pf->used_umv_size++;
1190 }
1191
1192 static void
1193 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1194                       const uint8_t *addr, bool is_mc)
1195 {
1196         const unsigned char *mac_addr = addr;
1197         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1198                             ((uint32_t)mac_addr[2] << 16) |
1199                             ((uint32_t)mac_addr[1] << 8) |
1200                             (uint32_t)mac_addr[0];
1201         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1202
1203         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1204         if (is_mc) {
1205                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1206                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1207                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1208         }
1209
1210         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1211         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1212 }
1213
1214 static int
1215 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1216                              uint8_t resp_code,
1217                              enum hns3_mac_vlan_tbl_opcode op)
1218 {
1219         if (cmdq_resp) {
1220                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1221                          cmdq_resp);
1222                 return -EIO;
1223         }
1224
1225         if (op == HNS3_MAC_VLAN_ADD) {
1226                 if (resp_code == 0 || resp_code == 1) {
1227                         return 0;
1228                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1229                         hns3_err(hw, "add mac addr failed for uc_overflow");
1230                         return -ENOSPC;
1231                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1232                         hns3_err(hw, "add mac addr failed for mc_overflow");
1233                         return -ENOSPC;
1234                 }
1235
1236                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1237                          resp_code);
1238                 return -EIO;
1239         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1240                 if (resp_code == 0) {
1241                         return 0;
1242                 } else if (resp_code == 1) {
1243                         hns3_dbg(hw, "remove mac addr failed for miss");
1244                         return -ENOENT;
1245                 }
1246
1247                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1248                          resp_code);
1249                 return -EIO;
1250         } else if (op == HNS3_MAC_VLAN_LKUP) {
1251                 if (resp_code == 0) {
1252                         return 0;
1253                 } else if (resp_code == 1) {
1254                         hns3_dbg(hw, "lookup mac addr failed for miss");
1255                         return -ENOENT;
1256                 }
1257
1258                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1259                          resp_code);
1260                 return -EIO;
1261         }
1262
1263         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1264                  op);
1265
1266         return -EINVAL;
1267 }
1268
1269 static int
1270 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1271                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1272                          struct hns3_cmd_desc *desc, bool is_mc)
1273 {
1274         uint8_t resp_code;
1275         uint16_t retval;
1276         int ret;
1277
1278         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1279         if (is_mc) {
1280                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1281                 memcpy(desc[0].data, req,
1282                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1283                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1284                                           true);
1285                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1286                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1287                                           true);
1288                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1289         } else {
1290                 memcpy(desc[0].data, req,
1291                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1292                 ret = hns3_cmd_send(hw, desc, 1);
1293         }
1294         if (ret) {
1295                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1296                          ret);
1297                 return ret;
1298         }
1299         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1300         retval = rte_le_to_cpu_16(desc[0].retval);
1301
1302         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1303                                             HNS3_MAC_VLAN_LKUP);
1304 }
1305
1306 static int
1307 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1308                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1309                       struct hns3_cmd_desc *mc_desc)
1310 {
1311         uint8_t resp_code;
1312         uint16_t retval;
1313         int cfg_status;
1314         int ret;
1315
1316         if (mc_desc == NULL) {
1317                 struct hns3_cmd_desc desc;
1318
1319                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1320                 memcpy(desc.data, req,
1321                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322                 ret = hns3_cmd_send(hw, &desc, 1);
1323                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1324                 retval = rte_le_to_cpu_16(desc.retval);
1325
1326                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1327                                                           HNS3_MAC_VLAN_ADD);
1328         } else {
1329                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1330                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1331                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1332                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1333                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1334                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1335                 memcpy(mc_desc[0].data, req,
1336                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1337                 mc_desc[0].retval = 0;
1338                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1339                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1340                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1341
1342                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1343                                                           HNS3_MAC_VLAN_ADD);
1344         }
1345
1346         if (ret) {
1347                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1348                 return ret;
1349         }
1350
1351         return cfg_status;
1352 }
1353
1354 static int
1355 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1356                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1357 {
1358         struct hns3_cmd_desc desc;
1359         uint8_t resp_code;
1360         uint16_t retval;
1361         int ret;
1362
1363         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1364
1365         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1366
1367         ret = hns3_cmd_send(hw, &desc, 1);
1368         if (ret) {
1369                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1370                 return ret;
1371         }
1372         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1373         retval = rte_le_to_cpu_16(desc.retval);
1374
1375         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1376                                             HNS3_MAC_VLAN_REMOVE);
1377 }
1378
1379 static int
1380 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1381 {
1382         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1383         struct hns3_mac_vlan_tbl_entry_cmd req;
1384         struct hns3_pf *pf = &hns->pf;
1385         struct hns3_cmd_desc desc;
1386         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1387         uint16_t egress_port = 0;
1388         uint8_t vf_id;
1389         int ret;
1390
1391         /* check if mac addr is valid */
1392         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1393                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1394                                       mac_addr);
1395                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1396                          mac_str);
1397                 return -EINVAL;
1398         }
1399
1400         memset(&req, 0, sizeof(req));
1401
1402         /*
1403          * In current version VF is not supported when PF is driven by DPDK
1404          * driver, just need to configure parameters for PF vport.
1405          */
1406         vf_id = HNS3_PF_FUNC_ID;
1407         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1408                        HNS3_MAC_EPORT_VFID_S, vf_id);
1409
1410         req.egress_port = rte_cpu_to_le_16(egress_port);
1411
1412         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1413
1414         /*
1415          * Lookup the mac address in the mac_vlan table, and add
1416          * it if the entry is inexistent. Repeated unicast entry
1417          * is not allowed in the mac vlan table.
1418          */
1419         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1420         if (ret == -ENOENT) {
1421                 if (!hns3_is_umv_space_full(hw)) {
1422                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1423                         if (!ret)
1424                                 hns3_update_umv_space(hw, false);
1425                         return ret;
1426                 }
1427
1428                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1429
1430                 return -ENOSPC;
1431         }
1432
1433         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1434
1435         /* check if we just hit the duplicate */
1436         if (ret == 0) {
1437                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1438                 return 0;
1439         }
1440
1441         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1442                  mac_str);
1443
1444         return ret;
1445 }
1446
1447 static int
1448 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1449 {
1450         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1451         struct rte_ether_addr *addr;
1452         int ret;
1453         int i;
1454
1455         for (i = 0; i < hw->mc_addrs_num; i++) {
1456                 addr = &hw->mc_addrs[i];
1457                 /* Check if there are duplicate addresses */
1458                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1459                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1460                                               addr);
1461                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1462                                  "(%s) is added by the set_mc_mac_addr_list "
1463                                  "API", mac_str);
1464                         return -EINVAL;
1465                 }
1466         }
1467
1468         ret = hns3_add_mc_addr(hw, mac_addr);
1469         if (ret) {
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1473                          mac_str, ret);
1474         }
1475         return ret;
1476 }
1477
1478 static int
1479 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1480 {
1481         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1482         int ret;
1483
1484         ret = hns3_remove_mc_addr(hw, mac_addr);
1485         if (ret) {
1486                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1487                                       mac_addr);
1488                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1489                          mac_str, ret);
1490         }
1491         return ret;
1492 }
1493
1494 static int
1495 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1496                   uint32_t idx, __rte_unused uint32_t pool)
1497 {
1498         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1500         int ret;
1501
1502         rte_spinlock_lock(&hw->lock);
1503
1504         /*
1505          * In hns3 network engine adding UC and MC mac address with different
1506          * commands with firmware. We need to determine whether the input
1507          * address is a UC or a MC address to call different commands.
1508          * By the way, it is recommended calling the API function named
1509          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1510          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1511          * may affect the specifications of UC mac addresses.
1512          */
1513         if (rte_is_multicast_ether_addr(mac_addr))
1514                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1515         else
1516                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1517
1518         if (ret) {
1519                 rte_spinlock_unlock(&hw->lock);
1520                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1521                                       mac_addr);
1522                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1523                          ret);
1524                 return ret;
1525         }
1526
1527         if (idx == 0)
1528                 hw->mac.default_addr_setted = true;
1529         rte_spinlock_unlock(&hw->lock);
1530
1531         return ret;
1532 }
1533
1534 static int
1535 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1536 {
1537         struct hns3_mac_vlan_tbl_entry_cmd req;
1538         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1539         int ret;
1540
1541         /* check if mac addr is valid */
1542         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1543                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1544                                       mac_addr);
1545                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1546                          mac_str);
1547                 return -EINVAL;
1548         }
1549
1550         memset(&req, 0, sizeof(req));
1551         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1552         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1553         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1554         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1555                 return 0;
1556         else if (ret == 0)
1557                 hns3_update_umv_space(hw, true);
1558
1559         return ret;
1560 }
1561
1562 static void
1563 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1564 {
1565         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         /* index will be checked by upper level rte interface */
1567         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1568         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569         int ret;
1570
1571         rte_spinlock_lock(&hw->lock);
1572
1573         if (rte_is_multicast_ether_addr(mac_addr))
1574                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1575         else
1576                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1577         rte_spinlock_unlock(&hw->lock);
1578         if (ret) {
1579                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1580                                       mac_addr);
1581                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1582                          ret);
1583         }
1584 }
1585
1586 static int
1587 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1588                           struct rte_ether_addr *mac_addr)
1589 {
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         struct rte_ether_addr *oaddr;
1592         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1593         bool default_addr_setted;
1594         bool rm_succes = false;
1595         int ret, ret_val;
1596
1597         /*
1598          * It has been guaranteed that input parameter named mac_addr is valid
1599          * address in the rte layer of DPDK framework.
1600          */
1601         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1602         default_addr_setted = hw->mac.default_addr_setted;
1603         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1604                 return 0;
1605
1606         rte_spinlock_lock(&hw->lock);
1607         if (default_addr_setted) {
1608                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1609                 if (ret) {
1610                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1611                                               oaddr);
1612                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1613                                   mac_str, ret);
1614                         rm_succes = false;
1615                 } else
1616                         rm_succes = true;
1617         }
1618
1619         ret = hns3_add_uc_addr_common(hw, mac_addr);
1620         if (ret) {
1621                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1622                                       mac_addr);
1623                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1624                 goto err_add_uc_addr;
1625         }
1626
1627         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1628         if (ret) {
1629                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1630                 goto err_pause_addr_cfg;
1631         }
1632
1633         rte_ether_addr_copy(mac_addr,
1634                             (struct rte_ether_addr *)hw->mac.mac_addr);
1635         hw->mac.default_addr_setted = true;
1636         rte_spinlock_unlock(&hw->lock);
1637
1638         return 0;
1639
1640 err_pause_addr_cfg:
1641         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1642         if (ret_val) {
1643                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1644                                       mac_addr);
1645                 hns3_warn(hw,
1646                           "Failed to roll back to del setted mac addr(%s): %d",
1647                           mac_str, ret_val);
1648         }
1649
1650 err_add_uc_addr:
1651         if (rm_succes) {
1652                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1653                 if (ret_val) {
1654                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1655                                               oaddr);
1656                         hns3_warn(hw,
1657                                   "Failed to restore old uc mac addr(%s): %d",
1658                                   mac_str, ret_val);
1659                         hw->mac.default_addr_setted = false;
1660                 }
1661         }
1662         rte_spinlock_unlock(&hw->lock);
1663
1664         return ret;
1665 }
1666
1667 static int
1668 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1669 {
1670         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1671         struct hns3_hw *hw = &hns->hw;
1672         struct rte_ether_addr *addr;
1673         int err = 0;
1674         int ret;
1675         int i;
1676
1677         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1678                 addr = &hw->data->mac_addrs[i];
1679                 if (rte_is_zero_ether_addr(addr))
1680                         continue;
1681                 if (rte_is_multicast_ether_addr(addr))
1682                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1683                               hns3_add_mc_addr(hw, addr);
1684                 else
1685                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1686                               hns3_add_uc_addr_common(hw, addr);
1687
1688                 if (ret) {
1689                         err = ret;
1690                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1691                                               addr);
1692                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1693                                  "ret = %d.", del ? "remove" : "restore",
1694                                  mac_str, i, ret);
1695                 }
1696         }
1697         return err;
1698 }
1699
1700 static void
1701 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1702 {
1703 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1704         uint8_t word_num;
1705         uint8_t bit_num;
1706
1707         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1708                 word_num = vfid / 32;
1709                 bit_num = vfid % 32;
1710                 if (clr)
1711                         desc[1].data[word_num] &=
1712                             rte_cpu_to_le_32(~(1UL << bit_num));
1713                 else
1714                         desc[1].data[word_num] |=
1715                             rte_cpu_to_le_32(1UL << bit_num);
1716         } else {
1717                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1718                 bit_num = vfid % 32;
1719                 if (clr)
1720                         desc[2].data[word_num] &=
1721                             rte_cpu_to_le_32(~(1UL << bit_num));
1722                 else
1723                         desc[2].data[word_num] |=
1724                             rte_cpu_to_le_32(1UL << bit_num);
1725         }
1726 }
1727
1728 static int
1729 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1730 {
1731         struct hns3_mac_vlan_tbl_entry_cmd req;
1732         struct hns3_cmd_desc desc[3];
1733         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1734         uint8_t vf_id;
1735         int ret;
1736
1737         /* Check if mac addr is valid */
1738         if (!rte_is_multicast_ether_addr(mac_addr)) {
1739                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                       mac_addr);
1741                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1742                          mac_str);
1743                 return -EINVAL;
1744         }
1745
1746         memset(&req, 0, sizeof(req));
1747         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1748         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1749         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1750         if (ret) {
1751                 /* This mac addr do not exist, add new entry for it */
1752                 memset(desc[0].data, 0, sizeof(desc[0].data));
1753                 memset(desc[1].data, 0, sizeof(desc[0].data));
1754                 memset(desc[2].data, 0, sizeof(desc[0].data));
1755         }
1756
1757         /*
1758          * In current version VF is not supported when PF is driven by DPDK
1759          * driver, just need to configure parameters for PF vport.
1760          */
1761         vf_id = HNS3_PF_FUNC_ID;
1762         hns3_update_desc_vfid(desc, vf_id, false);
1763         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1764         if (ret) {
1765                 if (ret == -ENOSPC)
1766                         hns3_err(hw, "mc mac vlan table is full");
1767                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1768                                       mac_addr);
1769                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1770         }
1771
1772         return ret;
1773 }
1774
1775 static int
1776 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1777 {
1778         struct hns3_mac_vlan_tbl_entry_cmd req;
1779         struct hns3_cmd_desc desc[3];
1780         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1781         uint8_t vf_id;
1782         int ret;
1783
1784         /* Check if mac addr is valid */
1785         if (!rte_is_multicast_ether_addr(mac_addr)) {
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1789                          mac_str);
1790                 return -EINVAL;
1791         }
1792
1793         memset(&req, 0, sizeof(req));
1794         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1795         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1796         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1797         if (ret == 0) {
1798                 /*
1799                  * This mac addr exist, remove this handle's VFID for it.
1800                  * In current version VF is not supported when PF is driven by
1801                  * DPDK driver, just need to configure parameters for PF vport.
1802                  */
1803                 vf_id = HNS3_PF_FUNC_ID;
1804                 hns3_update_desc_vfid(desc, vf_id, true);
1805
1806                 /* All the vfid is zero, so need to delete this entry */
1807                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1808         } else if (ret == -ENOENT) {
1809                 /* This mac addr doesn't exist. */
1810                 return 0;
1811         }
1812
1813         if (ret) {
1814                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1815                                       mac_addr);
1816                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1817         }
1818
1819         return ret;
1820 }
1821
1822 static int
1823 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1824                            struct rte_ether_addr *mc_addr_set,
1825                            uint32_t nb_mc_addr)
1826 {
1827         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1828         struct rte_ether_addr *addr;
1829         uint32_t i;
1830         uint32_t j;
1831
1832         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1833                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1834                          "invalid. valid range: 0~%d",
1835                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1836                 return -EINVAL;
1837         }
1838
1839         /* Check if input mac addresses are valid */
1840         for (i = 0; i < nb_mc_addr; i++) {
1841                 addr = &mc_addr_set[i];
1842                 if (!rte_is_multicast_ether_addr(addr)) {
1843                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1844                                               addr);
1845                         hns3_err(hw,
1846                                  "failed to set mc mac addr, addr(%s) invalid.",
1847                                  mac_str);
1848                         return -EINVAL;
1849                 }
1850
1851                 /* Check if there are duplicate addresses */
1852                 for (j = i + 1; j < nb_mc_addr; j++) {
1853                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1854                                 rte_ether_format_addr(mac_str,
1855                                                       RTE_ETHER_ADDR_FMT_SIZE,
1856                                                       addr);
1857                                 hns3_err(hw, "failed to set mc mac addr, "
1858                                          "addrs invalid. two same addrs(%s).",
1859                                          mac_str);
1860                                 return -EINVAL;
1861                         }
1862                 }
1863
1864                 /*
1865                  * Check if there are duplicate addresses between mac_addrs
1866                  * and mc_addr_set
1867                  */
1868                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1869                         if (rte_is_same_ether_addr(addr,
1870                                                    &hw->data->mac_addrs[j])) {
1871                                 rte_ether_format_addr(mac_str,
1872                                                       RTE_ETHER_ADDR_FMT_SIZE,
1873                                                       addr);
1874                                 hns3_err(hw, "failed to set mc mac addr, "
1875                                          "addrs invalid. addrs(%s) has already "
1876                                          "configured in mac_addr add API",
1877                                          mac_str);
1878                                 return -EINVAL;
1879                         }
1880                 }
1881         }
1882
1883         return 0;
1884 }
1885
1886 static void
1887 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1888                            struct rte_ether_addr *mc_addr_set,
1889                            int mc_addr_num,
1890                            struct rte_ether_addr *reserved_addr_list,
1891                            int *reserved_addr_num,
1892                            struct rte_ether_addr *add_addr_list,
1893                            int *add_addr_num,
1894                            struct rte_ether_addr *rm_addr_list,
1895                            int *rm_addr_num)
1896 {
1897         struct rte_ether_addr *addr;
1898         int current_addr_num;
1899         int reserved_num = 0;
1900         int add_num = 0;
1901         int rm_num = 0;
1902         int num;
1903         int i;
1904         int j;
1905         bool same_addr;
1906
1907         /* Calculate the mc mac address list that should be removed */
1908         current_addr_num = hw->mc_addrs_num;
1909         for (i = 0; i < current_addr_num; i++) {
1910                 addr = &hw->mc_addrs[i];
1911                 same_addr = false;
1912                 for (j = 0; j < mc_addr_num; j++) {
1913                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1914                                 same_addr = true;
1915                                 break;
1916                         }
1917                 }
1918
1919                 if (!same_addr) {
1920                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1921                         rm_num++;
1922                 } else {
1923                         rte_ether_addr_copy(addr,
1924                                             &reserved_addr_list[reserved_num]);
1925                         reserved_num++;
1926                 }
1927         }
1928
1929         /* Calculate the mc mac address list that should be added */
1930         for (i = 0; i < mc_addr_num; i++) {
1931                 addr = &mc_addr_set[i];
1932                 same_addr = false;
1933                 for (j = 0; j < current_addr_num; j++) {
1934                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1935                                 same_addr = true;
1936                                 break;
1937                         }
1938                 }
1939
1940                 if (!same_addr) {
1941                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1942                         add_num++;
1943                 }
1944         }
1945
1946         /* Reorder the mc mac address list maintained by driver */
1947         for (i = 0; i < reserved_num; i++)
1948                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1949
1950         for (i = 0; i < rm_num; i++) {
1951                 num = reserved_num + i;
1952                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1953         }
1954
1955         *reserved_addr_num = reserved_num;
1956         *add_addr_num = add_num;
1957         *rm_addr_num = rm_num;
1958 }
1959
1960 static int
1961 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1962                           struct rte_ether_addr *mc_addr_set,
1963                           uint32_t nb_mc_addr)
1964 {
1965         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1967         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1968         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1969         struct rte_ether_addr *addr;
1970         int reserved_addr_num;
1971         int add_addr_num;
1972         int rm_addr_num;
1973         int mc_addr_num;
1974         int num;
1975         int ret;
1976         int i;
1977
1978         /* Check if input parameters are valid */
1979         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1980         if (ret)
1981                 return ret;
1982
1983         rte_spinlock_lock(&hw->lock);
1984
1985         /*
1986          * Calculate the mc mac address lists those should be removed and be
1987          * added, Reorder the mc mac address list maintained by driver.
1988          */
1989         mc_addr_num = (int)nb_mc_addr;
1990         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1991                                    reserved_addr_list, &reserved_addr_num,
1992                                    add_addr_list, &add_addr_num,
1993                                    rm_addr_list, &rm_addr_num);
1994
1995         /* Remove mc mac addresses */
1996         for (i = 0; i < rm_addr_num; i++) {
1997                 num = rm_addr_num - i - 1;
1998                 addr = &rm_addr_list[num];
1999                 ret = hns3_remove_mc_addr(hw, addr);
2000                 if (ret) {
2001                         rte_spinlock_unlock(&hw->lock);
2002                         return ret;
2003                 }
2004                 hw->mc_addrs_num--;
2005         }
2006
2007         /* Add mc mac addresses */
2008         for (i = 0; i < add_addr_num; i++) {
2009                 addr = &add_addr_list[i];
2010                 ret = hns3_add_mc_addr(hw, addr);
2011                 if (ret) {
2012                         rte_spinlock_unlock(&hw->lock);
2013                         return ret;
2014                 }
2015
2016                 num = reserved_addr_num + i;
2017                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2018                 hw->mc_addrs_num++;
2019         }
2020         rte_spinlock_unlock(&hw->lock);
2021
2022         return 0;
2023 }
2024
2025 static int
2026 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2027 {
2028         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2029         struct hns3_hw *hw = &hns->hw;
2030         struct rte_ether_addr *addr;
2031         int err = 0;
2032         int ret;
2033         int i;
2034
2035         for (i = 0; i < hw->mc_addrs_num; i++) {
2036                 addr = &hw->mc_addrs[i];
2037                 if (!rte_is_multicast_ether_addr(addr))
2038                         continue;
2039                 if (del)
2040                         ret = hns3_remove_mc_addr(hw, addr);
2041                 else
2042                         ret = hns3_add_mc_addr(hw, addr);
2043                 if (ret) {
2044                         err = ret;
2045                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2046                                               addr);
2047                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2048                                  del ? "Remove" : "Restore", mac_str, ret);
2049                 }
2050         }
2051         return err;
2052 }
2053
2054 static int
2055 hns3_check_mq_mode(struct rte_eth_dev *dev)
2056 {
2057         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2058         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2059         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2061         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2062         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2063         uint8_t num_tc;
2064         int max_tc = 0;
2065         int i;
2066
2067         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2068         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2069
2070         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2071                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2072                          "rx_mq_mode = %d", rx_mq_mode);
2073                 return -EINVAL;
2074         }
2075
2076         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2077             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2078                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2079                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2080                          rx_mq_mode, tx_mq_mode);
2081                 return -EINVAL;
2082         }
2083
2084         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2085                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2086                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2087                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2088                         return -EINVAL;
2089                 }
2090
2091                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2092                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2093                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2094                                  "nb_tcs(%d) != %d or %d in rx direction.",
2095                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2096                         return -EINVAL;
2097                 }
2098
2099                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2100                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2101                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2102                         return -EINVAL;
2103                 }
2104
2105                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2106                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2107                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2108                                          "is not equal to one in tx direction.",
2109                                          i, dcb_rx_conf->dcb_tc[i]);
2110                                 return -EINVAL;
2111                         }
2112                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2113                                 max_tc = dcb_rx_conf->dcb_tc[i];
2114                 }
2115
2116                 num_tc = max_tc + 1;
2117                 if (num_tc > dcb_rx_conf->nb_tcs) {
2118                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2119                                  num_tc, dcb_rx_conf->nb_tcs);
2120                         return -EINVAL;
2121                 }
2122         }
2123
2124         return 0;
2125 }
2126
2127 static int
2128 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2129 {
2130         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2131
2132         if (!hns3_dev_dcb_supported(hw)) {
2133                 hns3_err(hw, "this port does not support dcb configurations.");
2134                 return -EOPNOTSUPP;
2135         }
2136
2137         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2138                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2139                 return -EOPNOTSUPP;
2140         }
2141
2142         /* Check multiple queue mode */
2143         return hns3_check_mq_mode(dev);
2144 }
2145
2146 static int
2147 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2148                            enum hns3_ring_type queue_type, uint16_t queue_id)
2149 {
2150         struct hns3_cmd_desc desc;
2151         struct hns3_ctrl_vector_chain_cmd *req =
2152                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2153         enum hns3_cmd_status status;
2154         enum hns3_opcode_type op;
2155         uint16_t tqp_type_and_id = 0;
2156         const char *op_str;
2157         uint16_t type;
2158         uint16_t gl;
2159
2160         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2161         hns3_cmd_setup_basic_desc(&desc, op, false);
2162         req->int_vector_id = vector_id;
2163
2164         if (queue_type == HNS3_RING_TYPE_RX)
2165                 gl = HNS3_RING_GL_RX;
2166         else
2167                 gl = HNS3_RING_GL_TX;
2168
2169         type = queue_type;
2170
2171         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2172                        type);
2173         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2174         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2175                        gl);
2176         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2177         req->int_cause_num = 1;
2178         op_str = mmap ? "Map" : "Unmap";
2179         status = hns3_cmd_send(hw, &desc, 1);
2180         if (status) {
2181                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2182                          op_str, queue_id, req->int_vector_id, status);
2183                 return status;
2184         }
2185
2186         return 0;
2187 }
2188
2189 static int
2190 hns3_init_ring_with_vector(struct hns3_hw *hw)
2191 {
2192         uint8_t vec;
2193         int ret;
2194         int i;
2195
2196         /*
2197          * In hns3 network engine, vector 0 is always the misc interrupt of this
2198          * function, vector 1~N can be used respectively for the queues of the
2199          * function. Tx and Rx queues with the same number share the interrupt
2200          * vector. In the initialization clearing the all hardware mapping
2201          * relationship configurations between queues and interrupt vectors is
2202          * needed, so some error caused by the residual configurations, such as
2203          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2204          * constraints in hns3 hardware engine, we have to implement clearing
2205          * the mapping relationship configurations by binding all queues to the
2206          * last interrupt vector and reserving the last interrupt vector. This
2207          * method results in a decrease of the maximum queues when upper
2208          * applications call the rte_eth_dev_configure API function to enable
2209          * Rx interrupt.
2210          */
2211         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2212         /* vec - 1: the last interrupt is reserved */
2213         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
2214         for (i = 0; i < hw->intr_tqps_num; i++) {
2215                 /*
2216                  * Set gap limiter and rate limiter configuration of queue's
2217                  * interrupt.
2218                  */
2219                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2220                                        HNS3_TQP_INTR_GL_DEFAULT);
2221                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2222                                        HNS3_TQP_INTR_GL_DEFAULT);
2223                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2224
2225                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2226                                                  HNS3_RING_TYPE_TX, i);
2227                 if (ret) {
2228                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2229                                           "vector: %d, ret=%d", i, vec, ret);
2230                         return ret;
2231                 }
2232
2233                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2234                                                  HNS3_RING_TYPE_RX, i);
2235                 if (ret) {
2236                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2237                                           "vector: %d, ret=%d", i, vec, ret);
2238                         return ret;
2239                 }
2240         }
2241
2242         return 0;
2243 }
2244
2245 static int
2246 hns3_dev_configure(struct rte_eth_dev *dev)
2247 {
2248         struct hns3_adapter *hns = dev->data->dev_private;
2249         struct rte_eth_conf *conf = &dev->data->dev_conf;
2250         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2251         struct hns3_hw *hw = &hns->hw;
2252         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2253         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2254         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2255         struct rte_eth_rss_conf rss_conf;
2256         uint16_t mtu;
2257         bool gro_en;
2258         int ret;
2259
2260         /*
2261          * Hardware does not support individually enable/disable/reset the Tx or
2262          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2263          * and Rx queues at the same time. When the numbers of Tx queues
2264          * allocated by upper applications are not equal to the numbers of Rx
2265          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2266          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2267          * these fake queues are imperceptible, and can not be used by upper
2268          * applications.
2269          */
2270         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2271         if (ret) {
2272                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2273                 return ret;
2274         }
2275
2276         hw->adapter_state = HNS3_NIC_CONFIGURING;
2277         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2278                 hns3_err(hw, "setting link speed/duplex not supported");
2279                 ret = -EINVAL;
2280                 goto cfg_err;
2281         }
2282
2283         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2284                 ret = hns3_check_dcb_cfg(dev);
2285                 if (ret)
2286                         goto cfg_err;
2287         }
2288
2289         /* When RSS is not configured, redirect the packet queue 0 */
2290         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2291                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2292                 rss_conf = conf->rx_adv_conf.rss_conf;
2293                 if (rss_conf.rss_key == NULL) {
2294                         rss_conf.rss_key = rss_cfg->key;
2295                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2296                 }
2297
2298                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2299                 if (ret)
2300                         goto cfg_err;
2301         }
2302
2303         /*
2304          * If jumbo frames are enabled, MTU needs to be refreshed
2305          * according to the maximum RX packet length.
2306          */
2307         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2308                 /*
2309                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2310                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2311                  * can safely assign to "uint16_t" type variable.
2312                  */
2313                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2314                 ret = hns3_dev_mtu_set(dev, mtu);
2315                 if (ret)
2316                         goto cfg_err;
2317                 dev->data->mtu = mtu;
2318         }
2319
2320         ret = hns3_dev_configure_vlan(dev);
2321         if (ret)
2322                 goto cfg_err;
2323
2324         /* config hardware GRO */
2325         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2326         ret = hns3_config_gro(hw, gro_en);
2327         if (ret)
2328                 goto cfg_err;
2329
2330         hw->adapter_state = HNS3_NIC_CONFIGURED;
2331
2332         return 0;
2333
2334 cfg_err:
2335         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2336         hw->adapter_state = HNS3_NIC_INITIALIZED;
2337
2338         return ret;
2339 }
2340
2341 static int
2342 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2343 {
2344         struct hns3_config_max_frm_size_cmd *req;
2345         struct hns3_cmd_desc desc;
2346
2347         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2348
2349         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2350         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2351         req->min_frm_size = RTE_ETHER_MIN_LEN;
2352
2353         return hns3_cmd_send(hw, &desc, 1);
2354 }
2355
2356 static int
2357 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2358 {
2359         int ret;
2360
2361         ret = hns3_set_mac_mtu(hw, mps);
2362         if (ret) {
2363                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2364                 return ret;
2365         }
2366
2367         ret = hns3_buffer_alloc(hw);
2368         if (ret)
2369                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2370
2371         return ret;
2372 }
2373
2374 static int
2375 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2376 {
2377         struct hns3_adapter *hns = dev->data->dev_private;
2378         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2379         struct hns3_hw *hw = &hns->hw;
2380         bool is_jumbo_frame;
2381         int ret;
2382
2383         if (dev->data->dev_started) {
2384                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2385                          "before configuration", dev->data->port_id);
2386                 return -EBUSY;
2387         }
2388
2389         rte_spinlock_lock(&hw->lock);
2390         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2391         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2392
2393         /*
2394          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2395          * assign to "uint16_t" type variable.
2396          */
2397         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2398         if (ret) {
2399                 rte_spinlock_unlock(&hw->lock);
2400                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2401                          dev->data->port_id, mtu, ret);
2402                 return ret;
2403         }
2404         hns->pf.mps = (uint16_t)frame_size;
2405         if (is_jumbo_frame)
2406                 dev->data->dev_conf.rxmode.offloads |=
2407                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2408         else
2409                 dev->data->dev_conf.rxmode.offloads &=
2410                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2411         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2412         rte_spinlock_unlock(&hw->lock);
2413
2414         return 0;
2415 }
2416
2417 static int
2418 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2419 {
2420         struct hns3_adapter *hns = eth_dev->data->dev_private;
2421         struct hns3_hw *hw = &hns->hw;
2422         uint16_t queue_num = hw->tqps_num;
2423
2424         /*
2425          * In interrupt mode, 'max_rx_queues' is set based on the number of
2426          * MSI-X interrupt resources of the hardware.
2427          */
2428         if (hw->data->dev_conf.intr_conf.rxq == 1)
2429                 queue_num = hw->intr_tqps_num;
2430
2431         info->max_rx_queues = queue_num;
2432         info->max_tx_queues = hw->tqps_num;
2433         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2434         info->min_rx_bufsize = hw->rx_buf_len;
2435         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2436         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2437         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2438         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2439                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2440                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2441                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2442                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2443                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2444                                  DEV_RX_OFFLOAD_KEEP_CRC |
2445                                  DEV_RX_OFFLOAD_SCATTER |
2446                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2447                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2448                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2449                                  DEV_RX_OFFLOAD_RSS_HASH |
2450                                  DEV_RX_OFFLOAD_TCP_LRO);
2451         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2452         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2453                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2454                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2455                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2456                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2457                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2458                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2459                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2460                                  DEV_TX_OFFLOAD_TCP_TSO |
2461                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2462                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2463                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2464                                  info->tx_queue_offload_capa);
2465
2466         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2467                 .nb_max = HNS3_MAX_RING_DESC,
2468                 .nb_min = HNS3_MIN_RING_DESC,
2469                 .nb_align = HNS3_ALIGN_RING_DESC,
2470         };
2471
2472         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2473                 .nb_max = HNS3_MAX_RING_DESC,
2474                 .nb_min = HNS3_MIN_RING_DESC,
2475                 .nb_align = HNS3_ALIGN_RING_DESC,
2476         };
2477
2478         info->vmdq_queue_num = 0;
2479
2480         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2481         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2482         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2483
2484         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2485         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2486         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2487         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2488         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2489         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2490
2491         return 0;
2492 }
2493
2494 static int
2495 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2496                     size_t fw_size)
2497 {
2498         struct hns3_adapter *hns = eth_dev->data->dev_private;
2499         struct hns3_hw *hw = &hns->hw;
2500         uint32_t version = hw->fw_version;
2501         int ret;
2502
2503         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2504                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2505                                       HNS3_FW_VERSION_BYTE3_S),
2506                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2507                                       HNS3_FW_VERSION_BYTE2_S),
2508                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2509                                       HNS3_FW_VERSION_BYTE1_S),
2510                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2511                                       HNS3_FW_VERSION_BYTE0_S));
2512         ret += 1; /* add the size of '\0' */
2513         if (fw_size < (uint32_t)ret)
2514                 return ret;
2515         else
2516                 return 0;
2517 }
2518
2519 static int
2520 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2521                      __rte_unused int wait_to_complete)
2522 {
2523         struct hns3_adapter *hns = eth_dev->data->dev_private;
2524         struct hns3_hw *hw = &hns->hw;
2525         struct hns3_mac *mac = &hw->mac;
2526         struct rte_eth_link new_link;
2527
2528         if (!hns3_is_reset_pending(hns)) {
2529                 hns3_update_speed_duplex(eth_dev);
2530                 hns3_update_link_status(hw);
2531         }
2532
2533         memset(&new_link, 0, sizeof(new_link));
2534         switch (mac->link_speed) {
2535         case ETH_SPEED_NUM_10M:
2536         case ETH_SPEED_NUM_100M:
2537         case ETH_SPEED_NUM_1G:
2538         case ETH_SPEED_NUM_10G:
2539         case ETH_SPEED_NUM_25G:
2540         case ETH_SPEED_NUM_40G:
2541         case ETH_SPEED_NUM_50G:
2542         case ETH_SPEED_NUM_100G:
2543                 new_link.link_speed = mac->link_speed;
2544                 break;
2545         default:
2546                 new_link.link_speed = ETH_SPEED_NUM_100M;
2547                 break;
2548         }
2549
2550         new_link.link_duplex = mac->link_duplex;
2551         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2552         new_link.link_autoneg =
2553             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2554
2555         return rte_eth_linkstatus_set(eth_dev, &new_link);
2556 }
2557
2558 static int
2559 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2560 {
2561         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2562         struct hns3_pf *pf = &hns->pf;
2563
2564         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2565                 return -EINVAL;
2566
2567         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2568
2569         return 0;
2570 }
2571
2572 static int
2573 hns3_query_function_status(struct hns3_hw *hw)
2574 {
2575 #define HNS3_QUERY_MAX_CNT              10
2576 #define HNS3_QUERY_SLEEP_MSCOEND        1
2577         struct hns3_func_status_cmd *req;
2578         struct hns3_cmd_desc desc;
2579         int timeout = 0;
2580         int ret;
2581
2582         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2583         req = (struct hns3_func_status_cmd *)desc.data;
2584
2585         do {
2586                 ret = hns3_cmd_send(hw, &desc, 1);
2587                 if (ret) {
2588                         PMD_INIT_LOG(ERR, "query function status failed %d",
2589                                      ret);
2590                         return ret;
2591                 }
2592
2593                 /* Check pf reset is done */
2594                 if (req->pf_state)
2595                         break;
2596
2597                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2598         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2599
2600         return hns3_parse_func_status(hw, req);
2601 }
2602
2603 static int
2604 hns3_query_pf_resource(struct hns3_hw *hw)
2605 {
2606         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2607         struct hns3_pf *pf = &hns->pf;
2608         struct hns3_pf_res_cmd *req;
2609         struct hns3_cmd_desc desc;
2610         int ret;
2611
2612         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2613         ret = hns3_cmd_send(hw, &desc, 1);
2614         if (ret) {
2615                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2616                 return ret;
2617         }
2618
2619         req = (struct hns3_pf_res_cmd *)desc.data;
2620         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2621         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2622         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2623         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2624
2625         if (req->tx_buf_size)
2626                 pf->tx_buf_size =
2627                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2628         else
2629                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2630
2631         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2632
2633         if (req->dv_buf_size)
2634                 pf->dv_buf_size =
2635                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2636         else
2637                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2638
2639         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2640
2641         hw->num_msi =
2642             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2643                            HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2644
2645         return 0;
2646 }
2647
2648 static void
2649 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2650 {
2651         struct hns3_cfg_param_cmd *req;
2652         uint64_t mac_addr_tmp_high;
2653         uint64_t mac_addr_tmp;
2654         uint32_t i;
2655
2656         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2657
2658         /* get the configuration */
2659         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2660                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2661         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2662                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2663         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2664                                            HNS3_CFG_TQP_DESC_N_M,
2665                                            HNS3_CFG_TQP_DESC_N_S);
2666
2667         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2668                                        HNS3_CFG_PHY_ADDR_M,
2669                                        HNS3_CFG_PHY_ADDR_S);
2670         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2671                                          HNS3_CFG_MEDIA_TP_M,
2672                                          HNS3_CFG_MEDIA_TP_S);
2673         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2674                                          HNS3_CFG_RX_BUF_LEN_M,
2675                                          HNS3_CFG_RX_BUF_LEN_S);
2676         /* get mac address */
2677         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2678         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2679                                            HNS3_CFG_MAC_ADDR_H_M,
2680                                            HNS3_CFG_MAC_ADDR_H_S);
2681
2682         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2683
2684         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2685                                             HNS3_CFG_DEFAULT_SPEED_M,
2686                                             HNS3_CFG_DEFAULT_SPEED_S);
2687         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2688                                            HNS3_CFG_RSS_SIZE_M,
2689                                            HNS3_CFG_RSS_SIZE_S);
2690
2691         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2692                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2693
2694         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2695         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2696
2697         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2698                                             HNS3_CFG_SPEED_ABILITY_M,
2699                                             HNS3_CFG_SPEED_ABILITY_S);
2700         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2701                                         HNS3_CFG_UMV_TBL_SPACE_M,
2702                                         HNS3_CFG_UMV_TBL_SPACE_S);
2703         if (!cfg->umv_space)
2704                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2705 }
2706
2707 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2708  * @hw: pointer to struct hns3_hw
2709  * @hcfg: the config structure to be getted
2710  */
2711 static int
2712 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2713 {
2714         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2715         struct hns3_cfg_param_cmd *req;
2716         uint32_t offset;
2717         uint32_t i;
2718         int ret;
2719
2720         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2721                 offset = 0;
2722                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2723                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2724                                           true);
2725                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2726                                i * HNS3_CFG_RD_LEN_BYTES);
2727                 /* Len should be divided by 4 when send to hardware */
2728                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2729                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2730                 req->offset = rte_cpu_to_le_32(offset);
2731         }
2732
2733         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2734         if (ret) {
2735                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2736                 return ret;
2737         }
2738
2739         hns3_parse_cfg(hcfg, desc);
2740
2741         return 0;
2742 }
2743
2744 static int
2745 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2746 {
2747         switch (speed_cmd) {
2748         case HNS3_CFG_SPEED_10M:
2749                 *speed = ETH_SPEED_NUM_10M;
2750                 break;
2751         case HNS3_CFG_SPEED_100M:
2752                 *speed = ETH_SPEED_NUM_100M;
2753                 break;
2754         case HNS3_CFG_SPEED_1G:
2755                 *speed = ETH_SPEED_NUM_1G;
2756                 break;
2757         case HNS3_CFG_SPEED_10G:
2758                 *speed = ETH_SPEED_NUM_10G;
2759                 break;
2760         case HNS3_CFG_SPEED_25G:
2761                 *speed = ETH_SPEED_NUM_25G;
2762                 break;
2763         case HNS3_CFG_SPEED_40G:
2764                 *speed = ETH_SPEED_NUM_40G;
2765                 break;
2766         case HNS3_CFG_SPEED_50G:
2767                 *speed = ETH_SPEED_NUM_50G;
2768                 break;
2769         case HNS3_CFG_SPEED_100G:
2770                 *speed = ETH_SPEED_NUM_100G;
2771                 break;
2772         default:
2773                 return -EINVAL;
2774         }
2775
2776         return 0;
2777 }
2778
2779 static int
2780 hns3_get_board_configuration(struct hns3_hw *hw)
2781 {
2782         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2783         struct hns3_pf *pf = &hns->pf;
2784         struct hns3_cfg cfg;
2785         int ret;
2786
2787         ret = hns3_get_board_cfg(hw, &cfg);
2788         if (ret) {
2789                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2790                 return ret;
2791         }
2792
2793         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2794                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2795                 return -EOPNOTSUPP;
2796         }
2797
2798         hw->mac.media_type = cfg.media_type;
2799         hw->rss_size_max = cfg.rss_size_max;
2800         hw->rss_dis_flag = false;
2801         hw->rx_buf_len = cfg.rx_buf_len;
2802         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2803         hw->mac.phy_addr = cfg.phy_addr;
2804         hw->mac.default_addr_setted = false;
2805         hw->num_tx_desc = cfg.tqp_desc_num;
2806         hw->num_rx_desc = cfg.tqp_desc_num;
2807         hw->dcb_info.num_pg = 1;
2808         hw->dcb_info.hw_pfc_map = 0;
2809
2810         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2811         if (ret) {
2812                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2813                              cfg.default_speed, ret);
2814                 return ret;
2815         }
2816
2817         pf->tc_max = cfg.tc_num;
2818         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2819                 PMD_INIT_LOG(WARNING,
2820                              "Get TC num(%u) from flash, set TC num to 1",
2821                              pf->tc_max);
2822                 pf->tc_max = 1;
2823         }
2824
2825         /* Dev does not support DCB */
2826         if (!hns3_dev_dcb_supported(hw)) {
2827                 pf->tc_max = 1;
2828                 pf->pfc_max = 0;
2829         } else
2830                 pf->pfc_max = pf->tc_max;
2831
2832         hw->dcb_info.num_tc = 1;
2833         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2834                                      hw->tqps_num / hw->dcb_info.num_tc);
2835         hns3_set_bit(hw->hw_tc_map, 0, 1);
2836         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2837
2838         pf->wanted_umv_size = cfg.umv_space;
2839
2840         return ret;
2841 }
2842
2843 static int
2844 hns3_get_configuration(struct hns3_hw *hw)
2845 {
2846         int ret;
2847
2848         ret = hns3_query_function_status(hw);
2849         if (ret) {
2850                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2851                 return ret;
2852         }
2853
2854         /* Get pf resource */
2855         ret = hns3_query_pf_resource(hw);
2856         if (ret) {
2857                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2858                 return ret;
2859         }
2860
2861         ret = hns3_get_board_configuration(hw);
2862         if (ret)
2863                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2864
2865         return ret;
2866 }
2867
2868 static int
2869 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2870                       uint16_t tqp_vid, bool is_pf)
2871 {
2872         struct hns3_tqp_map_cmd *req;
2873         struct hns3_cmd_desc desc;
2874         int ret;
2875
2876         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2877
2878         req = (struct hns3_tqp_map_cmd *)desc.data;
2879         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2880         req->tqp_vf = func_id;
2881         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2882         if (!is_pf)
2883                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2884         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2885
2886         ret = hns3_cmd_send(hw, &desc, 1);
2887         if (ret)
2888                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2889
2890         return ret;
2891 }
2892
2893 static int
2894 hns3_map_tqp(struct hns3_hw *hw)
2895 {
2896         uint16_t tqps_num = hw->total_tqps_num;
2897         uint16_t func_id;
2898         uint16_t tqp_id;
2899         bool is_pf;
2900         int num;
2901         int ret;
2902         int i;
2903
2904         /*
2905          * In current version VF is not supported when PF is driven by DPDK
2906          * driver, so we allocate tqps to PF as much as possible.
2907          */
2908         tqp_id = 0;
2909         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2910         for (func_id = HNS3_PF_FUNC_ID; func_id < num; func_id++) {
2911                 is_pf = func_id == HNS3_PF_FUNC_ID ? true : false;
2912                 for (i = 0;
2913                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2914                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2915                                                     is_pf);
2916                         if (ret)
2917                                 return ret;
2918                 }
2919         }
2920
2921         return 0;
2922 }
2923
2924 static int
2925 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2926 {
2927         struct hns3_config_mac_speed_dup_cmd *req;
2928         struct hns3_cmd_desc desc;
2929         int ret;
2930
2931         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2932
2933         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2934
2935         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2936
2937         switch (speed) {
2938         case ETH_SPEED_NUM_10M:
2939                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2940                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2941                 break;
2942         case ETH_SPEED_NUM_100M:
2943                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2944                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2945                 break;
2946         case ETH_SPEED_NUM_1G:
2947                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2948                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2949                 break;
2950         case ETH_SPEED_NUM_10G:
2951                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2952                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2953                 break;
2954         case ETH_SPEED_NUM_25G:
2955                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2956                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2957                 break;
2958         case ETH_SPEED_NUM_40G:
2959                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2960                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2961                 break;
2962         case ETH_SPEED_NUM_50G:
2963                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2964                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2965                 break;
2966         case ETH_SPEED_NUM_100G:
2967                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2968                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2969                 break;
2970         default:
2971                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2972                 return -EINVAL;
2973         }
2974
2975         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2976
2977         ret = hns3_cmd_send(hw, &desc, 1);
2978         if (ret)
2979                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2980
2981         return ret;
2982 }
2983
2984 static int
2985 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2986 {
2987         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2988         struct hns3_pf *pf = &hns->pf;
2989         struct hns3_priv_buf *priv;
2990         uint32_t i, total_size;
2991
2992         total_size = pf->pkt_buf_size;
2993
2994         /* alloc tx buffer for all enabled tc */
2995         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2996                 priv = &buf_alloc->priv_buf[i];
2997
2998                 if (hw->hw_tc_map & BIT(i)) {
2999                         if (total_size < pf->tx_buf_size)
3000                                 return -ENOMEM;
3001
3002                         priv->tx_buf_size = pf->tx_buf_size;
3003                 } else
3004                         priv->tx_buf_size = 0;
3005
3006                 total_size -= priv->tx_buf_size;
3007         }
3008
3009         return 0;
3010 }
3011
3012 static int
3013 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3014 {
3015 /* TX buffer size is unit by 128 byte */
3016 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3017 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3018         struct hns3_tx_buff_alloc_cmd *req;
3019         struct hns3_cmd_desc desc;
3020         uint32_t buf_size;
3021         uint32_t i;
3022         int ret;
3023
3024         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3025
3026         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3027         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3028                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3029
3030                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3031                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3032                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3033         }
3034
3035         ret = hns3_cmd_send(hw, &desc, 1);
3036         if (ret)
3037                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3038
3039         return ret;
3040 }
3041
3042 static int
3043 hns3_get_tc_num(struct hns3_hw *hw)
3044 {
3045         int cnt = 0;
3046         uint8_t i;
3047
3048         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3049                 if (hw->hw_tc_map & BIT(i))
3050                         cnt++;
3051         return cnt;
3052 }
3053
3054 static uint32_t
3055 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3056 {
3057         struct hns3_priv_buf *priv;
3058         uint32_t rx_priv = 0;
3059         int i;
3060
3061         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3062                 priv = &buf_alloc->priv_buf[i];
3063                 if (priv->enable)
3064                         rx_priv += priv->buf_size;
3065         }
3066         return rx_priv;
3067 }
3068
3069 static uint32_t
3070 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3071 {
3072         uint32_t total_tx_size = 0;
3073         uint32_t i;
3074
3075         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3076                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3077
3078         return total_tx_size;
3079 }
3080
3081 /* Get the number of pfc enabled TCs, which have private buffer */
3082 static int
3083 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3084 {
3085         struct hns3_priv_buf *priv;
3086         int cnt = 0;
3087         uint8_t i;
3088
3089         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3090                 priv = &buf_alloc->priv_buf[i];
3091                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3092                         cnt++;
3093         }
3094
3095         return cnt;
3096 }
3097
3098 /* Get the number of pfc disabled TCs, which have private buffer */
3099 static int
3100 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3101                          struct hns3_pkt_buf_alloc *buf_alloc)
3102 {
3103         struct hns3_priv_buf *priv;
3104         int cnt = 0;
3105         uint8_t i;
3106
3107         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3108                 priv = &buf_alloc->priv_buf[i];
3109                 if (hw->hw_tc_map & BIT(i) &&
3110                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3111                         cnt++;
3112         }
3113
3114         return cnt;
3115 }
3116
3117 static bool
3118 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3119                   uint32_t rx_all)
3120 {
3121         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3122         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3123         struct hns3_pf *pf = &hns->pf;
3124         uint32_t shared_buf, aligned_mps;
3125         uint32_t rx_priv;
3126         uint8_t tc_num;
3127         uint8_t i;
3128
3129         tc_num = hns3_get_tc_num(hw);
3130         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3131
3132         if (hns3_dev_dcb_supported(hw))
3133                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3134                                         pf->dv_buf_size;
3135         else
3136                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3137                                         + pf->dv_buf_size;
3138
3139         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3140         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3141                              HNS3_BUF_SIZE_UNIT);
3142
3143         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3144         if (rx_all < rx_priv + shared_std)
3145                 return false;
3146
3147         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3148         buf_alloc->s_buf.buf_size = shared_buf;
3149         if (hns3_dev_dcb_supported(hw)) {
3150                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3151                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3152                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3153                                   HNS3_BUF_SIZE_UNIT);
3154         } else {
3155                 buf_alloc->s_buf.self.high =
3156                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3157                 buf_alloc->s_buf.self.low = aligned_mps;
3158         }
3159
3160         if (hns3_dev_dcb_supported(hw)) {
3161                 hi_thrd = shared_buf - pf->dv_buf_size;
3162
3163                 if (tc_num <= NEED_RESERVE_TC_NUM)
3164                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3165                                         / BUF_MAX_PERCENT;
3166
3167                 if (tc_num)
3168                         hi_thrd = hi_thrd / tc_num;
3169
3170                 hi_thrd = max_t(uint32_t, hi_thrd,
3171                                 HNS3_BUF_MUL_BY * aligned_mps);
3172                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3173                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3174         } else {
3175                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3176                 lo_thrd = aligned_mps;
3177         }
3178
3179         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3180                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3181                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3182         }
3183
3184         return true;
3185 }
3186
3187 static bool
3188 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3189                      struct hns3_pkt_buf_alloc *buf_alloc)
3190 {
3191         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3192         struct hns3_pf *pf = &hns->pf;
3193         struct hns3_priv_buf *priv;
3194         uint32_t aligned_mps;
3195         uint32_t rx_all;
3196         uint8_t i;
3197
3198         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3199         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3200
3201         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3202                 priv = &buf_alloc->priv_buf[i];
3203
3204                 priv->enable = 0;
3205                 priv->wl.low = 0;
3206                 priv->wl.high = 0;
3207                 priv->buf_size = 0;
3208
3209                 if (!(hw->hw_tc_map & BIT(i)))
3210                         continue;
3211
3212                 priv->enable = 1;
3213                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3214                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3215                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3216                                                 HNS3_BUF_SIZE_UNIT);
3217                 } else {
3218                         priv->wl.low = 0;
3219                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3220                                         aligned_mps;
3221                 }
3222
3223                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3224         }
3225
3226         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3227 }
3228
3229 static bool
3230 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3231                              struct hns3_pkt_buf_alloc *buf_alloc)
3232 {
3233         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3234         struct hns3_pf *pf = &hns->pf;
3235         struct hns3_priv_buf *priv;
3236         int no_pfc_priv_num;
3237         uint32_t rx_all;
3238         uint8_t mask;
3239         int i;
3240
3241         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3242         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3243
3244         /* let the last to be cleared first */
3245         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3246                 priv = &buf_alloc->priv_buf[i];
3247                 mask = BIT((uint8_t)i);
3248
3249                 if (hw->hw_tc_map & mask &&
3250                     !(hw->dcb_info.hw_pfc_map & mask)) {
3251                         /* Clear the no pfc TC private buffer */
3252                         priv->wl.low = 0;
3253                         priv->wl.high = 0;
3254                         priv->buf_size = 0;
3255                         priv->enable = 0;
3256                         no_pfc_priv_num--;
3257                 }
3258
3259                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3260                     no_pfc_priv_num == 0)
3261                         break;
3262         }
3263
3264         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3265 }
3266
3267 static bool
3268 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3269                            struct hns3_pkt_buf_alloc *buf_alloc)
3270 {
3271         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3272         struct hns3_pf *pf = &hns->pf;
3273         struct hns3_priv_buf *priv;
3274         uint32_t rx_all;
3275         int pfc_priv_num;
3276         uint8_t mask;
3277         int i;
3278
3279         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3280         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3281
3282         /* let the last to be cleared first */
3283         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3284                 priv = &buf_alloc->priv_buf[i];
3285                 mask = BIT((uint8_t)i);
3286
3287                 if (hw->hw_tc_map & mask &&
3288                     hw->dcb_info.hw_pfc_map & mask) {
3289                         /* Reduce the number of pfc TC with private buffer */
3290                         priv->wl.low = 0;
3291                         priv->enable = 0;
3292                         priv->wl.high = 0;
3293                         priv->buf_size = 0;
3294                         pfc_priv_num--;
3295                 }
3296                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3297                     pfc_priv_num == 0)
3298                         break;
3299         }
3300
3301         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3302 }
3303
3304 static bool
3305 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3306                           struct hns3_pkt_buf_alloc *buf_alloc)
3307 {
3308 #define COMPENSATE_BUFFER       0x3C00
3309 #define COMPENSATE_HALF_MPS_NUM 5
3310 #define PRIV_WL_GAP             0x1800
3311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3312         struct hns3_pf *pf = &hns->pf;
3313         uint32_t tc_num = hns3_get_tc_num(hw);
3314         uint32_t half_mps = pf->mps >> 1;
3315         struct hns3_priv_buf *priv;
3316         uint32_t min_rx_priv;
3317         uint32_t rx_priv;
3318         uint8_t i;
3319
3320         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3321         if (tc_num)
3322                 rx_priv = rx_priv / tc_num;
3323
3324         if (tc_num <= NEED_RESERVE_TC_NUM)
3325                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3326
3327         /*
3328          * Minimum value of private buffer in rx direction (min_rx_priv) is
3329          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3330          * buffer if rx_priv is greater than min_rx_priv.
3331          */
3332         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3333                         COMPENSATE_HALF_MPS_NUM * half_mps;
3334         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3335         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3336
3337         if (rx_priv < min_rx_priv)
3338                 return false;
3339
3340         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3341                 priv = &buf_alloc->priv_buf[i];
3342
3343                 priv->enable = 0;
3344                 priv->wl.low = 0;
3345                 priv->wl.high = 0;
3346                 priv->buf_size = 0;
3347
3348                 if (!(hw->hw_tc_map & BIT(i)))
3349                         continue;
3350
3351                 priv->enable = 1;
3352                 priv->buf_size = rx_priv;
3353                 priv->wl.high = rx_priv - pf->dv_buf_size;
3354                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3355         }
3356
3357         buf_alloc->s_buf.buf_size = 0;
3358
3359         return true;
3360 }
3361
3362 /*
3363  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3364  * @hw: pointer to struct hns3_hw
3365  * @buf_alloc: pointer to buffer calculation data
3366  * @return: 0: calculate sucessful, negative: fail
3367  */
3368 static int
3369 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3370 {
3371         /* When DCB is not supported, rx private buffer is not allocated. */
3372         if (!hns3_dev_dcb_supported(hw)) {
3373                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3374                 struct hns3_pf *pf = &hns->pf;
3375                 uint32_t rx_all = pf->pkt_buf_size;
3376
3377                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3378                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3379                         return -ENOMEM;
3380
3381                 return 0;
3382         }
3383
3384         /*
3385          * Try to allocate privated packet buffer for all TCs without share
3386          * buffer.
3387          */
3388         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3389                 return 0;
3390
3391         /*
3392          * Try to allocate privated packet buffer for all TCs with share
3393          * buffer.
3394          */
3395         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3396                 return 0;
3397
3398         /*
3399          * For different application scenes, the enabled port number, TC number
3400          * and no_drop TC number are different. In order to obtain the better
3401          * performance, software could allocate the buffer size and configure
3402          * the waterline by tring to decrease the private buffer size according
3403          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3404          * enabled tc.
3405          */
3406         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3407                 return 0;
3408
3409         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3410                 return 0;
3411
3412         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3413                 return 0;
3414
3415         return -ENOMEM;
3416 }
3417
3418 static int
3419 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3420 {
3421         struct hns3_rx_priv_buff_cmd *req;
3422         struct hns3_cmd_desc desc;
3423         uint32_t buf_size;
3424         int ret;
3425         int i;
3426
3427         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3428         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3429
3430         /* Alloc private buffer TCs */
3431         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3432                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3433
3434                 req->buf_num[i] =
3435                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3436                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3437         }
3438
3439         buf_size = buf_alloc->s_buf.buf_size;
3440         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3441                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3442
3443         ret = hns3_cmd_send(hw, &desc, 1);
3444         if (ret)
3445                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3446
3447         return ret;
3448 }
3449
3450 static int
3451 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3452 {
3453 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3454         struct hns3_rx_priv_wl_buf *req;
3455         struct hns3_priv_buf *priv;
3456         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3457         int i, j;
3458         int ret;
3459
3460         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3461                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3462                                           false);
3463                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3464
3465                 /* The first descriptor set the NEXT bit to 1 */
3466                 if (i == 0)
3467                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3468                 else
3469                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3470
3471                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3472                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3473
3474                         priv = &buf_alloc->priv_buf[idx];
3475                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3476                                                         HNS3_BUF_UNIT_S);
3477                         req->tc_wl[j].high |=
3478                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3479                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3480                                                         HNS3_BUF_UNIT_S);
3481                         req->tc_wl[j].low |=
3482                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3483                 }
3484         }
3485
3486         /* Send 2 descriptor at one time */
3487         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3488         if (ret)
3489                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3490                              ret);
3491         return ret;
3492 }
3493
3494 static int
3495 hns3_common_thrd_config(struct hns3_hw *hw,
3496                         struct hns3_pkt_buf_alloc *buf_alloc)
3497 {
3498 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3499         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3500         struct hns3_rx_com_thrd *req;
3501         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3502         struct hns3_tc_thrd *tc;
3503         int tc_idx;
3504         int i, j;
3505         int ret;
3506
3507         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3508                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3509                                           false);
3510                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3511
3512                 /* The first descriptor set the NEXT bit to 1 */
3513                 if (i == 0)
3514                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3515                 else
3516                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3517
3518                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3519                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3520                         tc = &s_buf->tc_thrd[tc_idx];
3521
3522                         req->com_thrd[j].high =
3523                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3524                         req->com_thrd[j].high |=
3525                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3526                         req->com_thrd[j].low =
3527                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3528                         req->com_thrd[j].low |=
3529                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3530                 }
3531         }
3532
3533         /* Send 2 descriptors at one time */
3534         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3535         if (ret)
3536                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3537
3538         return ret;
3539 }
3540
3541 static int
3542 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3543 {
3544         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3545         struct hns3_rx_com_wl *req;
3546         struct hns3_cmd_desc desc;
3547         int ret;
3548
3549         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3550
3551         req = (struct hns3_rx_com_wl *)desc.data;
3552         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3553         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3554
3555         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3556         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3557
3558         ret = hns3_cmd_send(hw, &desc, 1);
3559         if (ret)
3560                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3561
3562         return ret;
3563 }
3564
3565 int
3566 hns3_buffer_alloc(struct hns3_hw *hw)
3567 {
3568         struct hns3_pkt_buf_alloc pkt_buf;
3569         int ret;
3570
3571         memset(&pkt_buf, 0, sizeof(pkt_buf));
3572         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3573         if (ret) {
3574                 PMD_INIT_LOG(ERR,
3575                              "could not calc tx buffer size for all TCs %d",
3576                              ret);
3577                 return ret;
3578         }
3579
3580         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3581         if (ret) {
3582                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3583                 return ret;
3584         }
3585
3586         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3587         if (ret) {
3588                 PMD_INIT_LOG(ERR,
3589                              "could not calc rx priv buffer size for all TCs %d",
3590                              ret);
3591                 return ret;
3592         }
3593
3594         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3595         if (ret) {
3596                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3597                 return ret;
3598         }
3599
3600         if (hns3_dev_dcb_supported(hw)) {
3601                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3602                 if (ret) {
3603                         PMD_INIT_LOG(ERR,
3604                                      "could not configure rx private waterline %d",
3605                                      ret);
3606                         return ret;
3607                 }
3608
3609                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3610                 if (ret) {
3611                         PMD_INIT_LOG(ERR,
3612                                      "could not configure common threshold %d",
3613                                      ret);
3614                         return ret;
3615                 }
3616         }
3617
3618         ret = hns3_common_wl_config(hw, &pkt_buf);
3619         if (ret)
3620                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3621                              ret);
3622
3623         return ret;
3624 }
3625
3626 static int
3627 hns3_mac_init(struct hns3_hw *hw)
3628 {
3629         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3630         struct hns3_mac *mac = &hw->mac;
3631         struct hns3_pf *pf = &hns->pf;
3632         int ret;
3633
3634         pf->support_sfp_query = true;
3635         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3636         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3637         if (ret) {
3638                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3639                 return ret;
3640         }
3641
3642         mac->link_status = ETH_LINK_DOWN;
3643
3644         return hns3_config_mtu(hw, pf->mps);
3645 }
3646
3647 static int
3648 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3649 {
3650 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3651 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3652 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3653 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3654         int return_status;
3655
3656         if (cmdq_resp) {
3657                 PMD_INIT_LOG(ERR,
3658                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3659                              cmdq_resp);
3660                 return -EIO;
3661         }
3662
3663         switch (resp_code) {
3664         case HNS3_ETHERTYPE_SUCCESS_ADD:
3665         case HNS3_ETHERTYPE_ALREADY_ADD:
3666                 return_status = 0;
3667                 break;
3668         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3669                 PMD_INIT_LOG(ERR,
3670                              "add mac ethertype failed for manager table overflow.");
3671                 return_status = -EIO;
3672                 break;
3673         case HNS3_ETHERTYPE_KEY_CONFLICT:
3674                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3675                 return_status = -EIO;
3676                 break;
3677         default:
3678                 PMD_INIT_LOG(ERR,
3679                              "add mac ethertype failed for undefined, code=%d.",
3680                              resp_code);
3681                 return_status = -EIO;
3682                 break;
3683         }
3684
3685         return return_status;
3686 }
3687
3688 static int
3689 hns3_add_mgr_tbl(struct hns3_hw *hw,
3690                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3691 {
3692         struct hns3_cmd_desc desc;
3693         uint8_t resp_code;
3694         uint16_t retval;
3695         int ret;
3696
3697         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3698         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3699
3700         ret = hns3_cmd_send(hw, &desc, 1);
3701         if (ret) {
3702                 PMD_INIT_LOG(ERR,
3703                              "add mac ethertype failed for cmd_send, ret =%d.",
3704                              ret);
3705                 return ret;
3706         }
3707
3708         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3709         retval = rte_le_to_cpu_16(desc.retval);
3710
3711         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3712 }
3713
3714 static void
3715 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3716                      int *table_item_num)
3717 {
3718         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3719
3720         /*
3721          * In current version, we add one item in management table as below:
3722          * 0x0180C200000E -- LLDP MC address
3723          */
3724         tbl = mgr_table;
3725         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3726         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3727         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3728         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3729         tbl->i_port_bitmap = 0x1;
3730         *table_item_num = 1;
3731 }
3732
3733 static int
3734 hns3_init_mgr_tbl(struct hns3_hw *hw)
3735 {
3736 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3737         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3738         int table_item_num;
3739         int ret;
3740         int i;
3741
3742         memset(mgr_table, 0, sizeof(mgr_table));
3743         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3744         for (i = 0; i < table_item_num; i++) {
3745                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3746                 if (ret) {
3747                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3748                                      ret);
3749                         return ret;
3750                 }
3751         }
3752
3753         return 0;
3754 }
3755
3756 static void
3757 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3758                         bool en_mc, bool en_bc, int vport_id)
3759 {
3760         if (!param)
3761                 return;
3762
3763         memset(param, 0, sizeof(struct hns3_promisc_param));
3764         if (en_uc)
3765                 param->enable = HNS3_PROMISC_EN_UC;
3766         if (en_mc)
3767                 param->enable |= HNS3_PROMISC_EN_MC;
3768         if (en_bc)
3769                 param->enable |= HNS3_PROMISC_EN_BC;
3770         param->vf_id = vport_id;
3771 }
3772
3773 static int
3774 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3775 {
3776         struct hns3_promisc_cfg_cmd *req;
3777         struct hns3_cmd_desc desc;
3778         int ret;
3779
3780         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3781
3782         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3783         req->vf_id = param->vf_id;
3784         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3785             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3786
3787         ret = hns3_cmd_send(hw, &desc, 1);
3788         if (ret)
3789                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3790
3791         return ret;
3792 }
3793
3794 static int
3795 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3796 {
3797         struct hns3_promisc_param param;
3798         bool en_bc_pmc = true;
3799         uint8_t vf_id;
3800
3801         /*
3802          * In current version VF is not supported when PF is driven by DPDK
3803          * driver, just need to configure parameters for PF vport.
3804          */
3805         vf_id = HNS3_PF_FUNC_ID;
3806
3807         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3808         return hns3_cmd_set_promisc_mode(hw, &param);
3809 }
3810
3811 static int
3812 hns3_promisc_init(struct hns3_hw *hw)
3813 {
3814         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3815         struct hns3_pf *pf = &hns->pf;
3816         struct hns3_promisc_param param;
3817         uint16_t func_id;
3818         int ret;
3819
3820         ret = hns3_set_promisc_mode(hw, false, false);
3821         if (ret) {
3822                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
3823                 return ret;
3824         }
3825
3826         /*
3827          * In current version VFs are not supported when PF is driven by DPDK
3828          * driver. After PF has been taken over by DPDK, the original VF will
3829          * be invalid. So, there is a possibility of entry residues. It should
3830          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
3831          * during init.
3832          */
3833         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
3834                 hns3_promisc_param_init(&param, false, false, false, func_id);
3835                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3836                 if (ret) {
3837                         PMD_INIT_LOG(ERR, "failed to clear vf:%d promisc mode,"
3838                                         " ret = %d", func_id, ret);
3839                         return ret;
3840                 }
3841         }
3842
3843         return 0;
3844 }
3845
3846 static void
3847 hns3_promisc_uninit(struct hns3_hw *hw)
3848 {
3849         struct hns3_promisc_param param;
3850         uint16_t func_id;
3851         int ret;
3852
3853         func_id = HNS3_PF_FUNC_ID;
3854
3855         /*
3856          * In current version VFs are not supported when PF is driven by
3857          * DPDK driver, and VFs' promisc mode status has been cleared during
3858          * init and their status will not change. So just clear PF's promisc
3859          * mode status during uninit.
3860          */
3861         hns3_promisc_param_init(&param, false, false, false, func_id);
3862         ret = hns3_cmd_set_promisc_mode(hw, &param);
3863         if (ret)
3864                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
3865                                 " uninit, ret = %d", ret);
3866 }
3867
3868 static int
3869 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3870 {
3871         bool allmulti = dev->data->all_multicast ? true : false;
3872         struct hns3_adapter *hns = dev->data->dev_private;
3873         struct hns3_hw *hw = &hns->hw;
3874         uint64_t offloads;
3875         int err;
3876         int ret;
3877
3878         rte_spinlock_lock(&hw->lock);
3879         ret = hns3_set_promisc_mode(hw, true, true);
3880         if (ret) {
3881                 rte_spinlock_unlock(&hw->lock);
3882                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3883                          ret);
3884                 return ret;
3885         }
3886
3887         /*
3888          * When promiscuous mode was enabled, disable the vlan filter to let
3889          * all packets coming in in the receiving direction.
3890          */
3891         offloads = dev->data->dev_conf.rxmode.offloads;
3892         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3893                 ret = hns3_enable_vlan_filter(hns, false);
3894                 if (ret) {
3895                         hns3_err(hw, "failed to enable promiscuous mode due to "
3896                                      "failure to disable vlan filter, ret = %d",
3897                                  ret);
3898                         err = hns3_set_promisc_mode(hw, false, allmulti);
3899                         if (err)
3900                                 hns3_err(hw, "failed to restore promiscuous "
3901                                          "status after disable vlan filter "
3902                                          "failed during enabling promiscuous "
3903                                          "mode, ret = %d", ret);
3904                 }
3905         }
3906
3907         rte_spinlock_unlock(&hw->lock);
3908
3909         return ret;
3910 }
3911
3912 static int
3913 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3914 {
3915         bool allmulti = dev->data->all_multicast ? true : false;
3916         struct hns3_adapter *hns = dev->data->dev_private;
3917         struct hns3_hw *hw = &hns->hw;
3918         uint64_t offloads;
3919         int err;
3920         int ret;
3921
3922         /* If now in all_multicast mode, must remain in all_multicast mode. */
3923         rte_spinlock_lock(&hw->lock);
3924         ret = hns3_set_promisc_mode(hw, false, allmulti);
3925         if (ret) {
3926                 rte_spinlock_unlock(&hw->lock);
3927                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3928                          ret);
3929                 return ret;
3930         }
3931         /* when promiscuous mode was disabled, restore the vlan filter status */
3932         offloads = dev->data->dev_conf.rxmode.offloads;
3933         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3934                 ret = hns3_enable_vlan_filter(hns, true);
3935                 if (ret) {
3936                         hns3_err(hw, "failed to disable promiscuous mode due to"
3937                                  " failure to restore vlan filter, ret = %d",
3938                                  ret);
3939                         err = hns3_set_promisc_mode(hw, true, true);
3940                         if (err)
3941                                 hns3_err(hw, "failed to restore promiscuous "
3942                                          "status after enabling vlan filter "
3943                                          "failed during disabling promiscuous "
3944                                          "mode, ret = %d", ret);
3945                 }
3946         }
3947         rte_spinlock_unlock(&hw->lock);
3948
3949         return ret;
3950 }
3951
3952 static int
3953 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3954 {
3955         struct hns3_adapter *hns = dev->data->dev_private;
3956         struct hns3_hw *hw = &hns->hw;
3957         int ret;
3958
3959         if (dev->data->promiscuous)
3960                 return 0;
3961
3962         rte_spinlock_lock(&hw->lock);
3963         ret = hns3_set_promisc_mode(hw, false, true);
3964         rte_spinlock_unlock(&hw->lock);
3965         if (ret)
3966                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3967                          ret);
3968
3969         return ret;
3970 }
3971
3972 static int
3973 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3974 {
3975         struct hns3_adapter *hns = dev->data->dev_private;
3976         struct hns3_hw *hw = &hns->hw;
3977         int ret;
3978
3979         /* If now in promiscuous mode, must remain in all_multicast mode. */
3980         if (dev->data->promiscuous)
3981                 return 0;
3982
3983         rte_spinlock_lock(&hw->lock);
3984         ret = hns3_set_promisc_mode(hw, false, false);
3985         rte_spinlock_unlock(&hw->lock);
3986         if (ret)
3987                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
3988                          ret);
3989
3990         return ret;
3991 }
3992
3993 static int
3994 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3995 {
3996         struct hns3_hw *hw = &hns->hw;
3997         bool allmulti = hw->data->all_multicast ? true : false;
3998         int ret;
3999
4000         if (hw->data->promiscuous) {
4001                 ret = hns3_set_promisc_mode(hw, true, true);
4002                 if (ret)
4003                         hns3_err(hw, "failed to restore promiscuous mode, "
4004                                  "ret = %d", ret);
4005                 return ret;
4006         }
4007
4008         ret = hns3_set_promisc_mode(hw, false, allmulti);
4009         if (ret)
4010                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4011                          ret);
4012         return ret;
4013 }
4014
4015 static int
4016 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
4017 {
4018         struct hns3_sfp_speed_cmd *resp;
4019         struct hns3_cmd_desc desc;
4020         int ret;
4021
4022         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
4023         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4024         ret = hns3_cmd_send(hw, &desc, 1);
4025         if (ret == -EOPNOTSUPP) {
4026                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4027                 return ret;
4028         } else if (ret) {
4029                 hns3_err(hw, "get sfp speed failed %d", ret);
4030                 return ret;
4031         }
4032
4033         *speed = resp->sfp_speed;
4034
4035         return 0;
4036 }
4037
4038 static uint8_t
4039 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4040 {
4041         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4042                 duplex = ETH_LINK_FULL_DUPLEX;
4043
4044         return duplex;
4045 }
4046
4047 static int
4048 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4049 {
4050         struct hns3_mac *mac = &hw->mac;
4051         int ret;
4052
4053         duplex = hns3_check_speed_dup(duplex, speed);
4054         if (mac->link_speed == speed && mac->link_duplex == duplex)
4055                 return 0;
4056
4057         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4058         if (ret)
4059                 return ret;
4060
4061         mac->link_speed = speed;
4062         mac->link_duplex = duplex;
4063
4064         return 0;
4065 }
4066
4067 static int
4068 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4069 {
4070         struct hns3_adapter *hns = eth_dev->data->dev_private;
4071         struct hns3_hw *hw = &hns->hw;
4072         struct hns3_pf *pf = &hns->pf;
4073         uint32_t speed;
4074         int ret;
4075
4076         /* If IMP do not support get SFP/qSFP speed, return directly */
4077         if (!pf->support_sfp_query)
4078                 return 0;
4079
4080         ret = hns3_get_sfp_speed(hw, &speed);
4081         if (ret == -EOPNOTSUPP) {
4082                 pf->support_sfp_query = false;
4083                 return ret;
4084         } else if (ret)
4085                 return ret;
4086
4087         if (speed == ETH_SPEED_NUM_NONE)
4088                 return 0; /* do nothing if no SFP */
4089
4090         /* Config full duplex for SFP */
4091         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4092 }
4093
4094 static int
4095 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4096 {
4097         struct hns3_config_mac_mode_cmd *req;
4098         struct hns3_cmd_desc desc;
4099         uint32_t loop_en = 0;
4100         uint8_t val = 0;
4101         int ret;
4102
4103         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4104
4105         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4106         if (enable)
4107                 val = 1;
4108         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4109         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4110         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4111         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4112         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4113         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4114         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4115         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4116         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4117         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4118         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4119         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4120         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4121         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4122         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4123
4124         ret = hns3_cmd_send(hw, &desc, 1);
4125         if (ret)
4126                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4127
4128         return ret;
4129 }
4130
4131 static int
4132 hns3_get_mac_link_status(struct hns3_hw *hw)
4133 {
4134         struct hns3_link_status_cmd *req;
4135         struct hns3_cmd_desc desc;
4136         int link_status;
4137         int ret;
4138
4139         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4140         ret = hns3_cmd_send(hw, &desc, 1);
4141         if (ret) {
4142                 hns3_err(hw, "get link status cmd failed %d", ret);
4143                 return ETH_LINK_DOWN;
4144         }
4145
4146         req = (struct hns3_link_status_cmd *)desc.data;
4147         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4148
4149         return !!link_status;
4150 }
4151
4152 void
4153 hns3_update_link_status(struct hns3_hw *hw)
4154 {
4155         int state;
4156
4157         state = hns3_get_mac_link_status(hw);
4158         if (state != hw->mac.link_status) {
4159                 hw->mac.link_status = state;
4160                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4161         }
4162 }
4163
4164 static void
4165 hns3_service_handler(void *param)
4166 {
4167         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4168         struct hns3_adapter *hns = eth_dev->data->dev_private;
4169         struct hns3_hw *hw = &hns->hw;
4170
4171         if (!hns3_is_reset_pending(hns)) {
4172                 hns3_update_speed_duplex(eth_dev);
4173                 hns3_update_link_status(hw);
4174         } else
4175                 hns3_warn(hw, "Cancel the query when reset is pending");
4176
4177         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4178 }
4179
4180 static int
4181 hns3_init_hardware(struct hns3_adapter *hns)
4182 {
4183         struct hns3_hw *hw = &hns->hw;
4184         int ret;
4185
4186         ret = hns3_map_tqp(hw);
4187         if (ret) {
4188                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4189                 return ret;
4190         }
4191
4192         ret = hns3_init_umv_space(hw);
4193         if (ret) {
4194                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4195                 return ret;
4196         }
4197
4198         ret = hns3_mac_init(hw);
4199         if (ret) {
4200                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4201                 goto err_mac_init;
4202         }
4203
4204         ret = hns3_init_mgr_tbl(hw);
4205         if (ret) {
4206                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4207                 goto err_mac_init;
4208         }
4209
4210         ret = hns3_promisc_init(hw);
4211         if (ret) {
4212                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4213                              ret);
4214                 goto err_mac_init;
4215         }
4216
4217         ret = hns3_init_vlan_config(hns);
4218         if (ret) {
4219                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4220                 goto err_mac_init;
4221         }
4222
4223         ret = hns3_dcb_init(hw);
4224         if (ret) {
4225                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4226                 goto err_mac_init;
4227         }
4228
4229         ret = hns3_init_fd_config(hns);
4230         if (ret) {
4231                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4232                 goto err_mac_init;
4233         }
4234
4235         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4236         if (ret) {
4237                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4238                 goto err_mac_init;
4239         }
4240
4241         ret = hns3_config_gro(hw, false);
4242         if (ret) {
4243                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4244                 goto err_mac_init;
4245         }
4246
4247         /*
4248          * In the initialization clearing the all hardware mapping relationship
4249          * configurations between queues and interrupt vectors is needed, so
4250          * some error caused by the residual configurations, such as the
4251          * unexpected interrupt, can be avoid.
4252          */
4253         ret = hns3_init_ring_with_vector(hw);
4254         if (ret) {
4255                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4256                 goto err_mac_init;
4257         }
4258
4259         return 0;
4260
4261 err_mac_init:
4262         hns3_uninit_umv_space(hw);
4263         return ret;
4264 }
4265
4266 static int
4267 hns3_init_pf(struct rte_eth_dev *eth_dev)
4268 {
4269         struct rte_device *dev = eth_dev->device;
4270         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4271         struct hns3_adapter *hns = eth_dev->data->dev_private;
4272         struct hns3_hw *hw = &hns->hw;
4273         int ret;
4274
4275         PMD_INIT_FUNC_TRACE();
4276
4277         /* Get hardware io base address from pcie BAR2 IO space */
4278         hw->io_base = pci_dev->mem_resource[2].addr;
4279
4280         /* Firmware command queue initialize */
4281         ret = hns3_cmd_init_queue(hw);
4282         if (ret) {
4283                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4284                 goto err_cmd_init_queue;
4285         }
4286
4287         hns3_clear_all_event_cause(hw);
4288
4289         /* Firmware command initialize */
4290         ret = hns3_cmd_init(hw);
4291         if (ret) {
4292                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4293                 goto err_cmd_init;
4294         }
4295
4296         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4297                                          hns3_interrupt_handler,
4298                                          eth_dev);
4299         if (ret) {
4300                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4301                 goto err_intr_callback_register;
4302         }
4303
4304         /* Enable interrupt */
4305         rte_intr_enable(&pci_dev->intr_handle);
4306         hns3_pf_enable_irq0(hw);
4307
4308         /* Get configuration */
4309         ret = hns3_get_configuration(hw);
4310         if (ret) {
4311                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4312                 goto err_get_config;
4313         }
4314
4315         ret = hns3_init_hardware(hns);
4316         if (ret) {
4317                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4318                 goto err_get_config;
4319         }
4320
4321         /* Initialize flow director filter list & hash */
4322         ret = hns3_fdir_filter_init(hns);
4323         if (ret) {
4324                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4325                 goto err_hw_init;
4326         }
4327
4328         hns3_set_default_rss_args(hw);
4329
4330         ret = hns3_enable_hw_error_intr(hns, true);
4331         if (ret) {
4332                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4333                              ret);
4334                 goto err_fdir;
4335         }
4336
4337         return 0;
4338
4339 err_fdir:
4340         hns3_fdir_filter_uninit(hns);
4341 err_hw_init:
4342         hns3_uninit_umv_space(hw);
4343
4344 err_get_config:
4345         hns3_pf_disable_irq0(hw);
4346         rte_intr_disable(&pci_dev->intr_handle);
4347         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4348                              eth_dev);
4349 err_intr_callback_register:
4350 err_cmd_init:
4351         hns3_cmd_uninit(hw);
4352         hns3_cmd_destroy_queue(hw);
4353 err_cmd_init_queue:
4354         hw->io_base = NULL;
4355
4356         return ret;
4357 }
4358
4359 static void
4360 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4361 {
4362         struct hns3_adapter *hns = eth_dev->data->dev_private;
4363         struct rte_device *dev = eth_dev->device;
4364         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4365         struct hns3_hw *hw = &hns->hw;
4366
4367         PMD_INIT_FUNC_TRACE();
4368
4369         hns3_enable_hw_error_intr(hns, false);
4370         hns3_rss_uninit(hns);
4371         (void)hns3_config_gro(hw, false);
4372         hns3_promisc_uninit(hw);
4373         hns3_fdir_filter_uninit(hns);
4374         hns3_uninit_umv_space(hw);
4375         hns3_pf_disable_irq0(hw);
4376         rte_intr_disable(&pci_dev->intr_handle);
4377         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4378                              eth_dev);
4379         hns3_cmd_uninit(hw);
4380         hns3_cmd_destroy_queue(hw);
4381         hw->io_base = NULL;
4382 }
4383
4384 static int
4385 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4386 {
4387         struct hns3_hw *hw = &hns->hw;
4388         int ret;
4389
4390         ret = hns3_dcb_cfg_update(hns);
4391         if (ret)
4392                 return ret;
4393
4394         /* Enable queues */
4395         ret = hns3_start_queues(hns, reset_queue);
4396         if (ret) {
4397                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4398                 return ret;
4399         }
4400
4401         /* Enable MAC */
4402         ret = hns3_cfg_mac_mode(hw, true);
4403         if (ret) {
4404                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4405                 goto err_config_mac_mode;
4406         }
4407         return 0;
4408
4409 err_config_mac_mode:
4410         hns3_stop_queues(hns, true);
4411         return ret;
4412 }
4413
4414 static int
4415 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4416 {
4417         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4418         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4419         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4421         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4422         uint32_t intr_vector;
4423         uint16_t q_id;
4424         int ret;
4425
4426         if (dev->data->dev_conf.intr_conf.rxq == 0)
4427                 return 0;
4428
4429         /* disable uio/vfio intr/eventfd mapping */
4430         rte_intr_disable(intr_handle);
4431
4432         /* check and configure queue intr-vector mapping */
4433         if (rte_intr_cap_multiple(intr_handle) ||
4434             !RTE_ETH_DEV_SRIOV(dev).active) {
4435                 intr_vector = hw->used_rx_queues;
4436                 /* creates event fd for each intr vector when MSIX is used */
4437                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4438                         return -EINVAL;
4439         }
4440         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4441                 intr_handle->intr_vec =
4442                         rte_zmalloc("intr_vec",
4443                                     hw->used_rx_queues * sizeof(int), 0);
4444                 if (intr_handle->intr_vec == NULL) {
4445                         hns3_err(hw, "Failed to allocate %d rx_queues"
4446                                      " intr_vec", hw->used_rx_queues);
4447                         ret = -ENOMEM;
4448                         goto alloc_intr_vec_error;
4449                 }
4450         }
4451
4452         if (rte_intr_allow_others(intr_handle)) {
4453                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4454                 base = RTE_INTR_VEC_RXTX_OFFSET;
4455         }
4456         if (rte_intr_dp_is_en(intr_handle)) {
4457                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4458                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4459                                                          HNS3_RING_TYPE_RX,
4460                                                          q_id);
4461                         if (ret)
4462                                 goto bind_vector_error;
4463                         intr_handle->intr_vec[q_id] = vec;
4464                         if (vec < base + intr_handle->nb_efd - 1)
4465                                 vec++;
4466                 }
4467         }
4468         rte_intr_enable(intr_handle);
4469         return 0;
4470
4471 bind_vector_error:
4472         rte_intr_efd_disable(intr_handle);
4473         if (intr_handle->intr_vec) {
4474                 free(intr_handle->intr_vec);
4475                 intr_handle->intr_vec = NULL;
4476         }
4477         return ret;
4478 alloc_intr_vec_error:
4479         rte_intr_efd_disable(intr_handle);
4480         return ret;
4481 }
4482
4483 static int
4484 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4485 {
4486         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4487         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4488         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4489         uint16_t q_id;
4490         int ret;
4491
4492         if (dev->data->dev_conf.intr_conf.rxq == 0)
4493                 return 0;
4494
4495         if (rte_intr_dp_is_en(intr_handle)) {
4496                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4497                         ret = hns3_bind_ring_with_vector(hw,
4498                                         intr_handle->intr_vec[q_id], true,
4499                                         HNS3_RING_TYPE_RX, q_id);
4500                         if (ret)
4501                                 return ret;
4502                 }
4503         }
4504
4505         return 0;
4506 }
4507
4508 static void
4509 hns3_restore_filter(struct rte_eth_dev *dev)
4510 {
4511         hns3_restore_rss_filter(dev);
4512 }
4513
4514 static int
4515 hns3_dev_start(struct rte_eth_dev *dev)
4516 {
4517         struct hns3_adapter *hns = dev->data->dev_private;
4518         struct hns3_hw *hw = &hns->hw;
4519         int ret;
4520
4521         PMD_INIT_FUNC_TRACE();
4522         if (rte_atomic16_read(&hw->reset.resetting))
4523                 return -EBUSY;
4524
4525         rte_spinlock_lock(&hw->lock);
4526         hw->adapter_state = HNS3_NIC_STARTING;
4527
4528         ret = hns3_do_start(hns, true);
4529         if (ret) {
4530                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4531                 rte_spinlock_unlock(&hw->lock);
4532                 return ret;
4533         }
4534         ret = hns3_map_rx_interrupt(dev);
4535         if (ret) {
4536                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4537                 rte_spinlock_unlock(&hw->lock);
4538                 return ret;
4539         }
4540
4541         hw->adapter_state = HNS3_NIC_STARTED;
4542         rte_spinlock_unlock(&hw->lock);
4543
4544         hns3_set_rxtx_function(dev);
4545         hns3_mp_req_start_rxtx(dev);
4546         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4547
4548         hns3_restore_filter(dev);
4549
4550         /* Enable interrupt of all rx queues before enabling queues */
4551         hns3_dev_all_rx_queue_intr_enable(hw, true);
4552         /*
4553          * When finished the initialization, enable queues to receive/transmit
4554          * packets.
4555          */
4556         hns3_enable_all_queues(hw, true);
4557
4558         hns3_info(hw, "hns3 dev start successful!");
4559         return 0;
4560 }
4561
4562 static int
4563 hns3_do_stop(struct hns3_adapter *hns)
4564 {
4565         struct hns3_hw *hw = &hns->hw;
4566         bool reset_queue;
4567         int ret;
4568
4569         ret = hns3_cfg_mac_mode(hw, false);
4570         if (ret)
4571                 return ret;
4572         hw->mac.link_status = ETH_LINK_DOWN;
4573
4574         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4575                 hns3_configure_all_mac_addr(hns, true);
4576                 reset_queue = true;
4577         } else
4578                 reset_queue = false;
4579         hw->mac.default_addr_setted = false;
4580         return hns3_stop_queues(hns, reset_queue);
4581 }
4582
4583 static void
4584 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4585 {
4586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4588         struct hns3_adapter *hns = dev->data->dev_private;
4589         struct hns3_hw *hw = &hns->hw;
4590         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4591         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4592         uint16_t q_id;
4593
4594         if (dev->data->dev_conf.intr_conf.rxq == 0)
4595                 return;
4596
4597         /* unmap the ring with vector */
4598         if (rte_intr_allow_others(intr_handle)) {
4599                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4600                 base = RTE_INTR_VEC_RXTX_OFFSET;
4601         }
4602         if (rte_intr_dp_is_en(intr_handle)) {
4603                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4604                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4605                                                          HNS3_RING_TYPE_RX,
4606                                                          q_id);
4607                         if (vec < base + intr_handle->nb_efd - 1)
4608                                 vec++;
4609                 }
4610         }
4611         /* Clean datapath event and queue/vec mapping */
4612         rte_intr_efd_disable(intr_handle);
4613         if (intr_handle->intr_vec) {
4614                 rte_free(intr_handle->intr_vec);
4615                 intr_handle->intr_vec = NULL;
4616         }
4617 }
4618
4619 static void
4620 hns3_dev_stop(struct rte_eth_dev *dev)
4621 {
4622         struct hns3_adapter *hns = dev->data->dev_private;
4623         struct hns3_hw *hw = &hns->hw;
4624
4625         PMD_INIT_FUNC_TRACE();
4626
4627         hw->adapter_state = HNS3_NIC_STOPPING;
4628         hns3_set_rxtx_function(dev);
4629         rte_wmb();
4630         /* Disable datapath on secondary process. */
4631         hns3_mp_req_stop_rxtx(dev);
4632         /* Prevent crashes when queues are still in use. */
4633         rte_delay_ms(hw->tqps_num);
4634
4635         rte_spinlock_lock(&hw->lock);
4636         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4637                 hns3_do_stop(hns);
4638                 hns3_unmap_rx_interrupt(dev);
4639                 hns3_dev_release_mbufs(hns);
4640                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4641         }
4642         rte_eal_alarm_cancel(hns3_service_handler, dev);
4643         rte_spinlock_unlock(&hw->lock);
4644 }
4645
4646 static void
4647 hns3_dev_close(struct rte_eth_dev *eth_dev)
4648 {
4649         struct hns3_adapter *hns = eth_dev->data->dev_private;
4650         struct hns3_hw *hw = &hns->hw;
4651
4652         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4653                 rte_free(eth_dev->process_private);
4654                 eth_dev->process_private = NULL;
4655                 return;
4656         }
4657
4658         if (hw->adapter_state == HNS3_NIC_STARTED)
4659                 hns3_dev_stop(eth_dev);
4660
4661         hw->adapter_state = HNS3_NIC_CLOSING;
4662         hns3_reset_abort(hns);
4663         hw->adapter_state = HNS3_NIC_CLOSED;
4664
4665         hns3_configure_all_mc_mac_addr(hns, true);
4666         hns3_remove_all_vlan_table(hns);
4667         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4668         hns3_uninit_pf(eth_dev);
4669         hns3_free_all_queues(eth_dev);
4670         rte_free(hw->reset.wait_data);
4671         rte_free(eth_dev->process_private);
4672         eth_dev->process_private = NULL;
4673         hns3_mp_uninit_primary();
4674         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4675 }
4676
4677 static int
4678 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4679 {
4680         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4682
4683         fc_conf->pause_time = pf->pause_time;
4684
4685         /* return fc current mode */
4686         switch (hw->current_mode) {
4687         case HNS3_FC_FULL:
4688                 fc_conf->mode = RTE_FC_FULL;
4689                 break;
4690         case HNS3_FC_TX_PAUSE:
4691                 fc_conf->mode = RTE_FC_TX_PAUSE;
4692                 break;
4693         case HNS3_FC_RX_PAUSE:
4694                 fc_conf->mode = RTE_FC_RX_PAUSE;
4695                 break;
4696         case HNS3_FC_NONE:
4697         default:
4698                 fc_conf->mode = RTE_FC_NONE;
4699                 break;
4700         }
4701
4702         return 0;
4703 }
4704
4705 static void
4706 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4707 {
4708         switch (mode) {
4709         case RTE_FC_NONE:
4710                 hw->requested_mode = HNS3_FC_NONE;
4711                 break;
4712         case RTE_FC_RX_PAUSE:
4713                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4714                 break;
4715         case RTE_FC_TX_PAUSE:
4716                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4717                 break;
4718         case RTE_FC_FULL:
4719                 hw->requested_mode = HNS3_FC_FULL;
4720                 break;
4721         default:
4722                 hw->requested_mode = HNS3_FC_NONE;
4723                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4724                           "configured to RTE_FC_NONE", mode);
4725                 break;
4726         }
4727 }
4728
4729 static int
4730 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4731 {
4732         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4733         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4734         int ret;
4735
4736         if (fc_conf->high_water || fc_conf->low_water ||
4737             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4738                 hns3_err(hw, "Unsupported flow control settings specified, "
4739                          "high_water(%u), low_water(%u), send_xon(%u) and "
4740                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4741                          fc_conf->high_water, fc_conf->low_water,
4742                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4743                 return -EINVAL;
4744         }
4745         if (fc_conf->autoneg) {
4746                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4747                 return -EINVAL;
4748         }
4749         if (!fc_conf->pause_time) {
4750                 hns3_err(hw, "Invalid pause time %d setting.",
4751                          fc_conf->pause_time);
4752                 return -EINVAL;
4753         }
4754
4755         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4756             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4757                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4758                          "current_fc_status = %d", hw->current_fc_status);
4759                 return -EOPNOTSUPP;
4760         }
4761
4762         hns3_get_fc_mode(hw, fc_conf->mode);
4763         if (hw->requested_mode == hw->current_mode &&
4764             pf->pause_time == fc_conf->pause_time)
4765                 return 0;
4766
4767         rte_spinlock_lock(&hw->lock);
4768         ret = hns3_fc_enable(dev, fc_conf);
4769         rte_spinlock_unlock(&hw->lock);
4770
4771         return ret;
4772 }
4773
4774 static int
4775 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4776                             struct rte_eth_pfc_conf *pfc_conf)
4777 {
4778         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4780         uint8_t priority;
4781         int ret;
4782
4783         if (!hns3_dev_dcb_supported(hw)) {
4784                 hns3_err(hw, "This port does not support dcb configurations.");
4785                 return -EOPNOTSUPP;
4786         }
4787
4788         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4789             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4790                 hns3_err(hw, "Unsupported flow control settings specified, "
4791                          "high_water(%u), low_water(%u), send_xon(%u) and "
4792                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4793                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4794                          pfc_conf->fc.send_xon,
4795                          pfc_conf->fc.mac_ctrl_frame_fwd);
4796                 return -EINVAL;
4797         }
4798         if (pfc_conf->fc.autoneg) {
4799                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4800                 return -EINVAL;
4801         }
4802         if (pfc_conf->fc.pause_time == 0) {
4803                 hns3_err(hw, "Invalid pause time %d setting.",
4804                          pfc_conf->fc.pause_time);
4805                 return -EINVAL;
4806         }
4807
4808         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4809             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4810                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4811                              "current_fc_status = %d", hw->current_fc_status);
4812                 return -EOPNOTSUPP;
4813         }
4814
4815         priority = pfc_conf->priority;
4816         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4817         if (hw->dcb_info.pfc_en & BIT(priority) &&
4818             hw->requested_mode == hw->current_mode &&
4819             pfc_conf->fc.pause_time == pf->pause_time)
4820                 return 0;
4821
4822         rte_spinlock_lock(&hw->lock);
4823         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4824         rte_spinlock_unlock(&hw->lock);
4825
4826         return ret;
4827 }
4828
4829 static int
4830 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4831 {
4832         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4833         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4834         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4835         int i;
4836
4837         rte_spinlock_lock(&hw->lock);
4838         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4839                 dcb_info->nb_tcs = pf->local_max_tc;
4840         else
4841                 dcb_info->nb_tcs = 1;
4842
4843         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4844                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4845         for (i = 0; i < dcb_info->nb_tcs; i++)
4846                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4847
4848         for (i = 0; i < hw->num_tc; i++) {
4849                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4850                 dcb_info->tc_queue.tc_txq[0][i].base =
4851                                                 hw->tc_queue[i].tqp_offset;
4852                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4853                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4854                                                 hw->tc_queue[i].tqp_count;
4855         }
4856         rte_spinlock_unlock(&hw->lock);
4857
4858         return 0;
4859 }
4860
4861 static int
4862 hns3_reinit_dev(struct hns3_adapter *hns)
4863 {
4864         struct hns3_hw *hw = &hns->hw;
4865         int ret;
4866
4867         ret = hns3_cmd_init(hw);
4868         if (ret) {
4869                 hns3_err(hw, "Failed to init cmd: %d", ret);
4870                 return ret;
4871         }
4872
4873         ret = hns3_reset_all_queues(hns);
4874         if (ret) {
4875                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4876                 return ret;
4877         }
4878
4879         ret = hns3_init_hardware(hns);
4880         if (ret) {
4881                 hns3_err(hw, "Failed to init hardware: %d", ret);
4882                 return ret;
4883         }
4884
4885         ret = hns3_enable_hw_error_intr(hns, true);
4886         if (ret) {
4887                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4888                              ret);
4889                 return ret;
4890         }
4891         hns3_info(hw, "Reset done, driver initialization finished.");
4892
4893         return 0;
4894 }
4895
4896 static bool
4897 is_pf_reset_done(struct hns3_hw *hw)
4898 {
4899         uint32_t val, reg, reg_bit;
4900
4901         switch (hw->reset.level) {
4902         case HNS3_IMP_RESET:
4903                 reg = HNS3_GLOBAL_RESET_REG;
4904                 reg_bit = HNS3_IMP_RESET_BIT;
4905                 break;
4906         case HNS3_GLOBAL_RESET:
4907                 reg = HNS3_GLOBAL_RESET_REG;
4908                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4909                 break;
4910         case HNS3_FUNC_RESET:
4911                 reg = HNS3_FUN_RST_ING;
4912                 reg_bit = HNS3_FUN_RST_ING_B;
4913                 break;
4914         case HNS3_FLR_RESET:
4915         default:
4916                 hns3_err(hw, "Wait for unsupported reset level: %d",
4917                          hw->reset.level);
4918                 return true;
4919         }
4920         val = hns3_read_dev(hw, reg);
4921         if (hns3_get_bit(val, reg_bit))
4922                 return false;
4923         else
4924                 return true;
4925 }
4926
4927 bool
4928 hns3_is_reset_pending(struct hns3_adapter *hns)
4929 {
4930         struct hns3_hw *hw = &hns->hw;
4931         enum hns3_reset_level reset;
4932
4933         hns3_check_event_cause(hns, NULL);
4934         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4935         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4936                 hns3_warn(hw, "High level reset %d is pending", reset);
4937                 return true;
4938         }
4939         reset = hns3_get_reset_level(hns, &hw->reset.request);
4940         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4941                 hns3_warn(hw, "High level reset %d is request", reset);
4942                 return true;
4943         }
4944         return false;
4945 }
4946
4947 static int
4948 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4949 {
4950         struct hns3_hw *hw = &hns->hw;
4951         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4952         struct timeval tv;
4953
4954         if (wait_data->result == HNS3_WAIT_SUCCESS)
4955                 return 0;
4956         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4957                 gettimeofday(&tv, NULL);
4958                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4959                           tv.tv_sec, tv.tv_usec);
4960                 return -ETIME;
4961         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4962                 return -EAGAIN;
4963
4964         wait_data->hns = hns;
4965         wait_data->check_completion = is_pf_reset_done;
4966         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4967                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4968         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4969         wait_data->count = HNS3_RESET_WAIT_CNT;
4970         wait_data->result = HNS3_WAIT_REQUEST;
4971         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4972         return -EAGAIN;
4973 }
4974
4975 static int
4976 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4977 {
4978         struct hns3_cmd_desc desc;
4979         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4980
4981         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4982         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4983         req->fun_reset_vfid = func_id;
4984
4985         return hns3_cmd_send(hw, &desc, 1);
4986 }
4987
4988 static int
4989 hns3_imp_reset_cmd(struct hns3_hw *hw)
4990 {
4991         struct hns3_cmd_desc desc;
4992
4993         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4994         desc.data[0] = 0xeedd;
4995
4996         return hns3_cmd_send(hw, &desc, 1);
4997 }
4998
4999 static void
5000 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
5001 {
5002         struct hns3_hw *hw = &hns->hw;
5003         struct timeval tv;
5004         uint32_t val;
5005
5006         gettimeofday(&tv, NULL);
5007         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
5008             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
5009                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
5010                           tv.tv_sec, tv.tv_usec);
5011                 return;
5012         }
5013
5014         switch (reset_level) {
5015         case HNS3_IMP_RESET:
5016                 hns3_imp_reset_cmd(hw);
5017                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
5018                           tv.tv_sec, tv.tv_usec);
5019                 break;
5020         case HNS3_GLOBAL_RESET:
5021                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5022                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5023                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5024                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5025                           tv.tv_sec, tv.tv_usec);
5026                 break;
5027         case HNS3_FUNC_RESET:
5028                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5029                           tv.tv_sec, tv.tv_usec);
5030                 /* schedule again to check later */
5031                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5032                 hns3_schedule_reset(hns);
5033                 break;
5034         default:
5035                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5036                 return;
5037         }
5038         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5039 }
5040
5041 static enum hns3_reset_level
5042 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5043 {
5044         struct hns3_hw *hw = &hns->hw;
5045         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5046
5047         /* Return the highest priority reset level amongst all */
5048         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5049                 reset_level = HNS3_IMP_RESET;
5050         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5051                 reset_level = HNS3_GLOBAL_RESET;
5052         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5053                 reset_level = HNS3_FUNC_RESET;
5054         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5055                 reset_level = HNS3_FLR_RESET;
5056
5057         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5058                 return HNS3_NONE_RESET;
5059
5060         return reset_level;
5061 }
5062
5063 static int
5064 hns3_prepare_reset(struct hns3_adapter *hns)
5065 {
5066         struct hns3_hw *hw = &hns->hw;
5067         uint32_t reg_val;
5068         int ret;
5069
5070         switch (hw->reset.level) {
5071         case HNS3_FUNC_RESET:
5072                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
5073                 if (ret)
5074                         return ret;
5075
5076                 /*
5077                  * After performaning pf reset, it is not necessary to do the
5078                  * mailbox handling or send any command to firmware, because
5079                  * any mailbox handling or command to firmware is only valid
5080                  * after hns3_cmd_init is called.
5081                  */
5082                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5083                 hw->reset.stats.request_cnt++;
5084                 break;
5085         case HNS3_IMP_RESET:
5086                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5087                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5088                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5089                 break;
5090         default:
5091                 break;
5092         }
5093         return 0;
5094 }
5095
5096 static int
5097 hns3_set_rst_done(struct hns3_hw *hw)
5098 {
5099         struct hns3_pf_rst_done_cmd *req;
5100         struct hns3_cmd_desc desc;
5101
5102         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5103         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5104         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5105         return hns3_cmd_send(hw, &desc, 1);
5106 }
5107
5108 static int
5109 hns3_stop_service(struct hns3_adapter *hns)
5110 {
5111         struct hns3_hw *hw = &hns->hw;
5112         struct rte_eth_dev *eth_dev;
5113
5114         eth_dev = &rte_eth_devices[hw->data->port_id];
5115         if (hw->adapter_state == HNS3_NIC_STARTED)
5116                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5117         hw->mac.link_status = ETH_LINK_DOWN;
5118
5119         hns3_set_rxtx_function(eth_dev);
5120         rte_wmb();
5121         /* Disable datapath on secondary process. */
5122         hns3_mp_req_stop_rxtx(eth_dev);
5123         rte_delay_ms(hw->tqps_num);
5124
5125         rte_spinlock_lock(&hw->lock);
5126         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5127             hw->adapter_state == HNS3_NIC_STOPPING) {
5128                 hns3_do_stop(hns);
5129                 hw->reset.mbuf_deferred_free = true;
5130         } else
5131                 hw->reset.mbuf_deferred_free = false;
5132
5133         /*
5134          * It is cumbersome for hardware to pick-and-choose entries for deletion
5135          * from table space. Hence, for function reset software intervention is
5136          * required to delete the entries
5137          */
5138         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5139                 hns3_configure_all_mc_mac_addr(hns, true);
5140         rte_spinlock_unlock(&hw->lock);
5141
5142         return 0;
5143 }
5144
5145 static int
5146 hns3_start_service(struct hns3_adapter *hns)
5147 {
5148         struct hns3_hw *hw = &hns->hw;
5149         struct rte_eth_dev *eth_dev;
5150
5151         if (hw->reset.level == HNS3_IMP_RESET ||
5152             hw->reset.level == HNS3_GLOBAL_RESET)
5153                 hns3_set_rst_done(hw);
5154         eth_dev = &rte_eth_devices[hw->data->port_id];
5155         hns3_set_rxtx_function(eth_dev);
5156         hns3_mp_req_start_rxtx(eth_dev);
5157         if (hw->adapter_state == HNS3_NIC_STARTED) {
5158                 hns3_service_handler(eth_dev);
5159
5160                 /* Enable interrupt of all rx queues before enabling queues */
5161                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5162                 /*
5163                  * When finished the initialization, enable queues to receive
5164                  * and transmit packets.
5165                  */
5166                 hns3_enable_all_queues(hw, true);
5167         }
5168
5169         return 0;
5170 }
5171
5172 static int
5173 hns3_restore_conf(struct hns3_adapter *hns)
5174 {
5175         struct hns3_hw *hw = &hns->hw;
5176         int ret;
5177
5178         ret = hns3_configure_all_mac_addr(hns, false);
5179         if (ret)
5180                 return ret;
5181
5182         ret = hns3_configure_all_mc_mac_addr(hns, false);
5183         if (ret)
5184                 goto err_mc_mac;
5185
5186         ret = hns3_dev_promisc_restore(hns);
5187         if (ret)
5188                 goto err_promisc;
5189
5190         ret = hns3_restore_vlan_table(hns);
5191         if (ret)
5192                 goto err_promisc;
5193
5194         ret = hns3_restore_vlan_conf(hns);
5195         if (ret)
5196                 goto err_promisc;
5197
5198         ret = hns3_restore_all_fdir_filter(hns);
5199         if (ret)
5200                 goto err_promisc;
5201
5202         ret = hns3_restore_rx_interrupt(hw);
5203         if (ret)
5204                 goto err_promisc;
5205
5206         ret = hns3_restore_gro_conf(hw);
5207         if (ret)
5208                 goto err_promisc;
5209
5210         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5211                 ret = hns3_do_start(hns, false);
5212                 if (ret)
5213                         goto err_promisc;
5214                 hns3_info(hw, "hns3 dev restart successful!");
5215         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5216                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5217         return 0;
5218
5219 err_promisc:
5220         hns3_configure_all_mc_mac_addr(hns, true);
5221 err_mc_mac:
5222         hns3_configure_all_mac_addr(hns, true);
5223         return ret;
5224 }
5225
5226 static void
5227 hns3_reset_service(void *param)
5228 {
5229         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5230         struct hns3_hw *hw = &hns->hw;
5231         enum hns3_reset_level reset_level;
5232         struct timeval tv_delta;
5233         struct timeval tv_start;
5234         struct timeval tv;
5235         uint64_t msec;
5236         int ret;
5237
5238         /*
5239          * The interrupt is not triggered within the delay time.
5240          * The interrupt may have been lost. It is necessary to handle
5241          * the interrupt to recover from the error.
5242          */
5243         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5244                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5245                 hns3_err(hw, "Handling interrupts in delayed tasks");
5246                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5247                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5248                 if (reset_level == HNS3_NONE_RESET) {
5249                         hns3_err(hw, "No reset level is set, try IMP reset");
5250                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5251                 }
5252         }
5253         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5254
5255         /*
5256          * Check if there is any ongoing reset in the hardware. This status can
5257          * be checked from reset_pending. If there is then, we need to wait for
5258          * hardware to complete reset.
5259          *    a. If we are able to figure out in reasonable time that hardware
5260          *       has fully resetted then, we can proceed with driver, client
5261          *       reset.
5262          *    b. else, we can come back later to check this status so re-sched
5263          *       now.
5264          */
5265         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5266         if (reset_level != HNS3_NONE_RESET) {
5267                 gettimeofday(&tv_start, NULL);
5268                 ret = hns3_reset_process(hns, reset_level);
5269                 gettimeofday(&tv, NULL);
5270                 timersub(&tv, &tv_start, &tv_delta);
5271                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5272                        tv_delta.tv_usec / USEC_PER_MSEC;
5273                 if (msec > HNS3_RESET_PROCESS_MS)
5274                         hns3_err(hw, "%d handle long time delta %" PRIx64
5275                                      " ms time=%ld.%.6ld",
5276                                  hw->reset.level, msec,
5277                                  tv.tv_sec, tv.tv_usec);
5278                 if (ret == -EAGAIN)
5279                         return;
5280         }
5281
5282         /* Check if we got any *new* reset requests to be honored */
5283         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5284         if (reset_level != HNS3_NONE_RESET)
5285                 hns3_msix_process(hns, reset_level);
5286 }
5287
5288 static const struct eth_dev_ops hns3_eth_dev_ops = {
5289         .dev_start          = hns3_dev_start,
5290         .dev_stop           = hns3_dev_stop,
5291         .dev_close          = hns3_dev_close,
5292         .promiscuous_enable = hns3_dev_promiscuous_enable,
5293         .promiscuous_disable = hns3_dev_promiscuous_disable,
5294         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5295         .allmulticast_disable = hns3_dev_allmulticast_disable,
5296         .mtu_set            = hns3_dev_mtu_set,
5297         .stats_get          = hns3_stats_get,
5298         .stats_reset        = hns3_stats_reset,
5299         .xstats_get         = hns3_dev_xstats_get,
5300         .xstats_get_names   = hns3_dev_xstats_get_names,
5301         .xstats_reset       = hns3_dev_xstats_reset,
5302         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5303         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5304         .dev_infos_get          = hns3_dev_infos_get,
5305         .fw_version_get         = hns3_fw_version_get,
5306         .rx_queue_setup         = hns3_rx_queue_setup,
5307         .tx_queue_setup         = hns3_tx_queue_setup,
5308         .rx_queue_release       = hns3_dev_rx_queue_release,
5309         .tx_queue_release       = hns3_dev_tx_queue_release,
5310         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5311         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5312         .dev_configure          = hns3_dev_configure,
5313         .flow_ctrl_get          = hns3_flow_ctrl_get,
5314         .flow_ctrl_set          = hns3_flow_ctrl_set,
5315         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5316         .mac_addr_add           = hns3_add_mac_addr,
5317         .mac_addr_remove        = hns3_remove_mac_addr,
5318         .mac_addr_set           = hns3_set_default_mac_addr,
5319         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5320         .link_update            = hns3_dev_link_update,
5321         .rss_hash_update        = hns3_dev_rss_hash_update,
5322         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5323         .reta_update            = hns3_dev_rss_reta_update,
5324         .reta_query             = hns3_dev_rss_reta_query,
5325         .filter_ctrl            = hns3_dev_filter_ctrl,
5326         .vlan_filter_set        = hns3_vlan_filter_set,
5327         .vlan_tpid_set          = hns3_vlan_tpid_set,
5328         .vlan_offload_set       = hns3_vlan_offload_set,
5329         .vlan_pvid_set          = hns3_vlan_pvid_set,
5330         .get_reg                = hns3_get_regs,
5331         .get_dcb_info           = hns3_get_dcb_info,
5332         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5333 };
5334
5335 static const struct hns3_reset_ops hns3_reset_ops = {
5336         .reset_service       = hns3_reset_service,
5337         .stop_service        = hns3_stop_service,
5338         .prepare_reset       = hns3_prepare_reset,
5339         .wait_hardware_ready = hns3_wait_hardware_ready,
5340         .reinit_dev          = hns3_reinit_dev,
5341         .restore_conf        = hns3_restore_conf,
5342         .start_service       = hns3_start_service,
5343 };
5344
5345 static int
5346 hns3_dev_init(struct rte_eth_dev *eth_dev)
5347 {
5348         struct rte_device *dev = eth_dev->device;
5349         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5350         struct hns3_adapter *hns = eth_dev->data->dev_private;
5351         struct hns3_hw *hw = &hns->hw;
5352         uint16_t device_id = pci_dev->id.device_id;
5353         uint8_t revision;
5354         int ret;
5355
5356         PMD_INIT_FUNC_TRACE();
5357
5358         /* Get PCI revision id */
5359         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
5360                                   HNS3_PCI_REVISION_ID);
5361         if (ret != HNS3_PCI_REVISION_ID_LEN) {
5362                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
5363                              ret);
5364                 return -EIO;
5365         }
5366         hw->revision = revision;
5367
5368         eth_dev->process_private = (struct hns3_process_private *)
5369             rte_zmalloc_socket("hns3_filter_list",
5370                                sizeof(struct hns3_process_private),
5371                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5372         if (eth_dev->process_private == NULL) {
5373                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5374                 return -ENOMEM;
5375         }
5376         /* initialize flow filter lists */
5377         hns3_filterlist_init(eth_dev);
5378
5379         hns3_set_rxtx_function(eth_dev);
5380         eth_dev->dev_ops = &hns3_eth_dev_ops;
5381         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5382                 hns3_mp_init_secondary();
5383                 hw->secondary_cnt++;
5384                 return 0;
5385         }
5386
5387         hns3_mp_init_primary();
5388         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5389
5390         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5391             device_id == HNS3_DEV_ID_50GE_RDMA ||
5392             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5393                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5394
5395         hns->is_vf = false;
5396         hw->data = eth_dev->data;
5397
5398         /*
5399          * Set default max packet size according to the mtu
5400          * default vale in DPDK frame.
5401          */
5402         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5403
5404         ret = hns3_reset_init(hw);
5405         if (ret)
5406                 goto err_init_reset;
5407         hw->reset.ops = &hns3_reset_ops;
5408
5409         ret = hns3_init_pf(eth_dev);
5410         if (ret) {
5411                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5412                 goto err_init_pf;
5413         }
5414
5415         /* Allocate memory for storing MAC addresses */
5416         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5417                                                sizeof(struct rte_ether_addr) *
5418                                                HNS3_UC_MACADDR_NUM, 0);
5419         if (eth_dev->data->mac_addrs == NULL) {
5420                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5421                              "to store MAC addresses",
5422                              sizeof(struct rte_ether_addr) *
5423                              HNS3_UC_MACADDR_NUM);
5424                 ret = -ENOMEM;
5425                 goto err_rte_zmalloc;
5426         }
5427
5428         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5429                             &eth_dev->data->mac_addrs[0]);
5430
5431         hw->adapter_state = HNS3_NIC_INITIALIZED;
5432         /*
5433          * Pass the information to the rte_eth_dev_close() that it should also
5434          * release the private port resources.
5435          */
5436         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5437
5438         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5439                 hns3_err(hw, "Reschedule reset service after dev_init");
5440                 hns3_schedule_reset(hns);
5441         } else {
5442                 /* IMP will wait ready flag before reset */
5443                 hns3_notify_reset_ready(hw, false);
5444         }
5445
5446         hns3_info(hw, "hns3 dev initialization successful!");
5447         return 0;
5448
5449 err_rte_zmalloc:
5450         hns3_uninit_pf(eth_dev);
5451
5452 err_init_pf:
5453         rte_free(hw->reset.wait_data);
5454 err_init_reset:
5455         eth_dev->dev_ops = NULL;
5456         eth_dev->rx_pkt_burst = NULL;
5457         eth_dev->tx_pkt_burst = NULL;
5458         eth_dev->tx_pkt_prepare = NULL;
5459         rte_free(eth_dev->process_private);
5460         eth_dev->process_private = NULL;
5461         return ret;
5462 }
5463
5464 static int
5465 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5466 {
5467         struct hns3_adapter *hns = eth_dev->data->dev_private;
5468         struct hns3_hw *hw = &hns->hw;
5469
5470         PMD_INIT_FUNC_TRACE();
5471
5472         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5473                 return -EPERM;
5474
5475         eth_dev->dev_ops = NULL;
5476         eth_dev->rx_pkt_burst = NULL;
5477         eth_dev->tx_pkt_burst = NULL;
5478         eth_dev->tx_pkt_prepare = NULL;
5479         if (hw->adapter_state < HNS3_NIC_CLOSING)
5480                 hns3_dev_close(eth_dev);
5481
5482         hw->adapter_state = HNS3_NIC_REMOVED;
5483         return 0;
5484 }
5485
5486 static int
5487 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5488                    struct rte_pci_device *pci_dev)
5489 {
5490         return rte_eth_dev_pci_generic_probe(pci_dev,
5491                                              sizeof(struct hns3_adapter),
5492                                              hns3_dev_init);
5493 }
5494
5495 static int
5496 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5497 {
5498         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5499 }
5500
5501 static const struct rte_pci_id pci_id_hns3_map[] = {
5502         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5503         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5504         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5505         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5506         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5507         { .vendor_id = 0, /* sentinel */ },
5508 };
5509
5510 static struct rte_pci_driver rte_hns3_pmd = {
5511         .id_table = pci_id_hns3_map,
5512         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5513         .probe = eth_hns3_pci_probe,
5514         .remove = eth_hns3_pci_remove,
5515 };
5516
5517 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5518 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5519 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5520 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
5521 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);